
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	b8 11 00 20 01 18 00 00 d5 53 00 00 d5 17 00 00     ... .....S......
  10:	d5 17 00 00 d5 17 00 00 d5 17 00 00 d5 17 00 00     ................
	...
  2c:	31 15 00 00 d5 17 00 00 00 00 00 00 d9 14 00 00     1...............
  3c:	d5 17 00 00                                         ....

00000040 <_irq_vector_table>:
  40:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  50:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  60:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  70:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  80:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  90:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  a0:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  b0:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  c0:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  d0:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  e0:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
  f0:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
 100:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
 110:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
 120:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
 130:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
 140:	b1 15 00 00 b1 15 00 00 b1 15 00 00 b1 15 00 00     ................
 150:	b1 15 00 00                                         ....

Disassembly of section text:

00000154 <__aeabi_uldivmod>:
     154:	b953      	cbnz	r3, 16c <__aeabi_uldivmod+0x18>
     156:	b94a      	cbnz	r2, 16c <__aeabi_uldivmod+0x18>
     158:	2900      	cmp	r1, #0
     15a:	bf08      	it	eq
     15c:	2800      	cmpeq	r0, #0
     15e:	bf1c      	itt	ne
     160:	f04f 31ff 	movne.w	r1, #4294967295
     164:	f04f 30ff 	movne.w	r0, #4294967295
     168:	f000 b80c 	b.w	184 <__aeabi_idiv0>
     16c:	f1ad 0c08 	sub.w	ip, sp, #8
     170:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     174:	f000 f808 	bl	188 <__udivmoddi4>
     178:	f8dd e004 	ldr.w	lr, [sp, #4]
     17c:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     180:	b004      	add	sp, #16
     182:	4770      	bx	lr

00000184 <__aeabi_idiv0>:
     184:	4770      	bx	lr
     186:	bf00      	nop

00000188 <__udivmoddi4>:
     188:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     18c:	4607      	mov	r7, r0
     18e:	468c      	mov	ip, r1
     190:	4608      	mov	r0, r1
     192:	9e09      	ldr	r6, [sp, #36]	; 0x24
     194:	4615      	mov	r5, r2
     196:	463c      	mov	r4, r7
     198:	4619      	mov	r1, r3
     19a:	2b00      	cmp	r3, #0
     19c:	f040 80c5 	bne.w	32a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xaa>
     1a0:	4282      	cmp	r2, r0
     1a2:	fab2 f782 	clz	r7, r2
     1a6:	d946      	bls.n	236 <__data_size+0x32>
     1a8:	b14f      	cbz	r7, 1be <__udivmoddi4+0x36>
     1aa:	f1c7 0e20 	rsb	lr, r7, #32
     1ae:	fa00 f307 	lsl.w	r3, r0, r7
     1b2:	40bd      	lsls	r5, r7
     1b4:	fa24 fe0e 	lsr.w	lr, r4, lr
     1b8:	40bc      	lsls	r4, r7
     1ba:	ea4e 0c03 	orr.w	ip, lr, r3
     1be:	ea4f 4815 	mov.w	r8, r5, lsr #16
     1c2:	fa1f fe85 	uxth.w	lr, r5
     1c6:	0c22      	lsrs	r2, r4, #16
     1c8:	fbbc f9f8 	udiv	r9, ip, r8
     1cc:	fb08 c319 	mls	r3, r8, r9, ip
     1d0:	fb09 fa0e 	mul.w	sl, r9, lr
     1d4:	ea42 4303 	orr.w	r3, r2, r3, lsl #16
     1d8:	459a      	cmp	sl, r3
     1da:	d928      	bls.n	22e <__data_size+0x2a>
     1dc:	18eb      	adds	r3, r5, r3
     1de:	f109 30ff 	add.w	r0, r9, #4294967295
     1e2:	d204      	bcs.n	1ee <CONFIG_SRAM_SIZE+0x2e>
     1e4:	459a      	cmp	sl, r3
     1e6:	d902      	bls.n	1ee <CONFIG_SRAM_SIZE+0x2e>
     1e8:	f1a9 0002 	sub.w	r0, r9, #2
     1ec:	442b      	add	r3, r5
     1ee:	eba3 030a 	sub.w	r3, r3, sl
     1f2:	b2a4      	uxth	r4, r4
     1f4:	fbb3 f2f8 	udiv	r2, r3, r8
     1f8:	fb08 3312 	mls	r3, r8, r2, r3
     1fc:	fb02 fe0e 	mul.w	lr, r2, lr
     200:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     204:	45a6      	cmp	lr, r4
     206:	d914      	bls.n	232 <__data_size+0x2e>
     208:	192c      	adds	r4, r5, r4
     20a:	f102 33ff 	add.w	r3, r2, #4294967295
     20e:	d203      	bcs.n	218 <__data_size+0x14>
     210:	45a6      	cmp	lr, r4
     212:	d901      	bls.n	218 <__data_size+0x14>
     214:	1e93      	subs	r3, r2, #2
     216:	442c      	add	r4, r5
     218:	eba4 040e 	sub.w	r4, r4, lr
     21c:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     220:	b11e      	cbz	r6, 22a <__data_size+0x26>
     222:	40fc      	lsrs	r4, r7
     224:	2300      	movs	r3, #0
     226:	6034      	str	r4, [r6, #0]
     228:	6073      	str	r3, [r6, #4]
     22a:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     22e:	4648      	mov	r0, r9
     230:	e7dd      	b.n	1ee <CONFIG_SRAM_SIZE+0x2e>
     232:	4613      	mov	r3, r2
     234:	e7f0      	b.n	218 <__data_size+0x14>
     236:	b902      	cbnz	r2, 23a <__data_size+0x36>
     238:	deff      	udf	#255	; 0xff
     23a:	bb87      	cbnz	r7, 29e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1e>
     23c:	1a83      	subs	r3, r0, r2
     23e:	2101      	movs	r1, #1
     240:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     244:	b2aa      	uxth	r2, r5
     246:	0c20      	lsrs	r0, r4, #16
     248:	fbb3 fcfe 	udiv	ip, r3, lr
     24c:	fb0e 331c 	mls	r3, lr, ip, r3
     250:	fb0c f802 	mul.w	r8, ip, r2
     254:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
     258:	4598      	cmp	r8, r3
     25a:	d962      	bls.n	322 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa2>
     25c:	18eb      	adds	r3, r5, r3
     25e:	f10c 30ff 	add.w	r0, ip, #4294967295
     262:	d204      	bcs.n	26e <__data_size+0x6a>
     264:	4598      	cmp	r8, r3
     266:	d902      	bls.n	26e <__data_size+0x6a>
     268:	f1ac 0002 	sub.w	r0, ip, #2
     26c:	442b      	add	r3, r5
     26e:	eba3 0308 	sub.w	r3, r3, r8
     272:	b2a4      	uxth	r4, r4
     274:	fbb3 fcfe 	udiv	ip, r3, lr
     278:	fb0e 331c 	mls	r3, lr, ip, r3
     27c:	fb0c f202 	mul.w	r2, ip, r2
     280:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     284:	42a2      	cmp	r2, r4
     286:	d94e      	bls.n	326 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa6>
     288:	192c      	adds	r4, r5, r4
     28a:	f10c 33ff 	add.w	r3, ip, #4294967295
     28e:	d204      	bcs.n	29a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1a>
     290:	42a2      	cmp	r2, r4
     292:	d902      	bls.n	29a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1a>
     294:	f1ac 0302 	sub.w	r3, ip, #2
     298:	442c      	add	r4, r5
     29a:	1aa4      	subs	r4, r4, r2
     29c:	e7be      	b.n	21c <__data_size+0x18>
     29e:	f1c7 0c20 	rsb	ip, r7, #32
     2a2:	40bd      	lsls	r5, r7
     2a4:	fa00 f307 	lsl.w	r3, r0, r7
     2a8:	fa20 f80c 	lsr.w	r8, r0, ip
     2ac:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     2b0:	fa24 fc0c 	lsr.w	ip, r4, ip
     2b4:	40bc      	lsls	r4, r7
     2b6:	ea4c 0203 	orr.w	r2, ip, r3
     2ba:	b2ab      	uxth	r3, r5
     2bc:	fbb8 fcfe 	udiv	ip, r8, lr
     2c0:	0c11      	lsrs	r1, r2, #16
     2c2:	fb0e 801c 	mls	r0, lr, ip, r8
     2c6:	fb0c f903 	mul.w	r9, ip, r3
     2ca:	ea41 4000 	orr.w	r0, r1, r0, lsl #16
     2ce:	4581      	cmp	r9, r0
     2d0:	d923      	bls.n	31a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x9a>
     2d2:	1828      	adds	r0, r5, r0
     2d4:	f10c 31ff 	add.w	r1, ip, #4294967295
     2d8:	d204      	bcs.n	2e4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x64>
     2da:	4581      	cmp	r9, r0
     2dc:	d902      	bls.n	2e4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x64>
     2de:	f1ac 0102 	sub.w	r1, ip, #2
     2e2:	4428      	add	r0, r5
     2e4:	eba0 0009 	sub.w	r0, r0, r9
     2e8:	b292      	uxth	r2, r2
     2ea:	fbb0 fcfe 	udiv	ip, r0, lr
     2ee:	fb0e 001c 	mls	r0, lr, ip, r0
     2f2:	fb0c f803 	mul.w	r8, ip, r3
     2f6:	ea42 4300 	orr.w	r3, r2, r0, lsl #16
     2fa:	4598      	cmp	r8, r3
     2fc:	d90f      	bls.n	31e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x9e>
     2fe:	18eb      	adds	r3, r5, r3
     300:	f10c 32ff 	add.w	r2, ip, #4294967295
     304:	d204      	bcs.n	310 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x90>
     306:	4598      	cmp	r8, r3
     308:	d902      	bls.n	310 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x90>
     30a:	f1ac 0202 	sub.w	r2, ip, #2
     30e:	442b      	add	r3, r5
     310:	eba3 0308 	sub.w	r3, r3, r8
     314:	ea42 4101 	orr.w	r1, r2, r1, lsl #16
     318:	e792      	b.n	240 <__data_size+0x3c>
     31a:	4661      	mov	r1, ip
     31c:	e7e2      	b.n	2e4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x64>
     31e:	4662      	mov	r2, ip
     320:	e7f6      	b.n	310 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x90>
     322:	4660      	mov	r0, ip
     324:	e7a3      	b.n	26e <__data_size+0x6a>
     326:	4663      	mov	r3, ip
     328:	e7b7      	b.n	29a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1a>
     32a:	4283      	cmp	r3, r0
     32c:	d905      	bls.n	33a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xba>
     32e:	b10e      	cbz	r6, 334 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xb4>
     330:	e9c6 7000 	strd	r7, r0, [r6]
     334:	2100      	movs	r1, #0
     336:	4608      	mov	r0, r1
     338:	e777      	b.n	22a <__data_size+0x26>
     33a:	fab3 f183 	clz	r1, r3
     33e:	b981      	cbnz	r1, 362 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xe2>
     340:	4283      	cmp	r3, r0
     342:	d301      	bcc.n	348 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc8>
     344:	42ba      	cmp	r2, r7
     346:	d80a      	bhi.n	35e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xde>
     348:	1abc      	subs	r4, r7, r2
     34a:	eb60 0303 	sbc.w	r3, r0, r3
     34e:	2001      	movs	r0, #1
     350:	469c      	mov	ip, r3
     352:	2e00      	cmp	r6, #0
     354:	d067      	beq.n	426 <CONFIG_FLASH_SIZE+0x26>
     356:	e9c6 4c00 	strd	r4, ip, [r6]
     35a:	2100      	movs	r1, #0
     35c:	e765      	b.n	22a <__data_size+0x26>
     35e:	4608      	mov	r0, r1
     360:	e7f7      	b.n	352 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd2>
     362:	f1c1 0c20 	rsb	ip, r1, #32
     366:	408b      	lsls	r3, r1
     368:	fa02 f501 	lsl.w	r5, r2, r1
     36c:	fa22 f40c 	lsr.w	r4, r2, ip
     370:	fa20 fb0c 	lsr.w	fp, r0, ip
     374:	fa27 f20c 	lsr.w	r2, r7, ip
     378:	408f      	lsls	r7, r1
     37a:	431c      	orrs	r4, r3
     37c:	fa00 f301 	lsl.w	r3, r0, r1
     380:	ea4f 4914 	mov.w	r9, r4, lsr #16
     384:	4313      	orrs	r3, r2
     386:	fa1f fe84 	uxth.w	lr, r4
     38a:	0c1a      	lsrs	r2, r3, #16
     38c:	fbbb f8f9 	udiv	r8, fp, r9
     390:	fb09 bb18 	mls	fp, r9, r8, fp
     394:	fb08 fa0e 	mul.w	sl, r8, lr
     398:	ea42 420b 	orr.w	r2, r2, fp, lsl #16
     39c:	4592      	cmp	sl, r2
     39e:	d93e      	bls.n	41e <CONFIG_FLASH_SIZE+0x1e>
     3a0:	18a2      	adds	r2, r4, r2
     3a2:	f108 30ff 	add.w	r0, r8, #4294967295
     3a6:	d204      	bcs.n	3b2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x132>
     3a8:	4592      	cmp	sl, r2
     3aa:	d902      	bls.n	3b2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x132>
     3ac:	f1a8 0002 	sub.w	r0, r8, #2
     3b0:	4422      	add	r2, r4
     3b2:	eba2 020a 	sub.w	r2, r2, sl
     3b6:	b29b      	uxth	r3, r3
     3b8:	fbb2 f8f9 	udiv	r8, r2, r9
     3bc:	fb09 2218 	mls	r2, r9, r8, r2
     3c0:	fb08 fe0e 	mul.w	lr, r8, lr
     3c4:	ea43 4202 	orr.w	r2, r3, r2, lsl #16
     3c8:	4596      	cmp	lr, r2
     3ca:	d92a      	bls.n	422 <CONFIG_FLASH_SIZE+0x22>
     3cc:	18a2      	adds	r2, r4, r2
     3ce:	f108 33ff 	add.w	r3, r8, #4294967295
     3d2:	d204      	bcs.n	3de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x15e>
     3d4:	4596      	cmp	lr, r2
     3d6:	d902      	bls.n	3de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x15e>
     3d8:	f1a8 0302 	sub.w	r3, r8, #2
     3dc:	4422      	add	r2, r4
     3de:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     3e2:	eba2 020e 	sub.w	r2, r2, lr
     3e6:	fba0 9305 	umull	r9, r3, r0, r5
     3ea:	429a      	cmp	r2, r3
     3ec:	46ce      	mov	lr, r9
     3ee:	4698      	mov	r8, r3
     3f0:	d302      	bcc.n	3f8 <CONFIG_NRF_SW_LPUART_DEFAULT_TX_TIMEOUT+0x10>
     3f2:	d106      	bne.n	402 <CONFIG_FLASH_SIZE+0x2>
     3f4:	454f      	cmp	r7, r9
     3f6:	d204      	bcs.n	402 <CONFIG_FLASH_SIZE+0x2>
     3f8:	3801      	subs	r0, #1
     3fa:	ebb9 0e05 	subs.w	lr, r9, r5
     3fe:	eb63 0804 	sbc.w	r8, r3, r4
     402:	b186      	cbz	r6, 426 <CONFIG_FLASH_SIZE+0x26>
     404:	ebb7 030e 	subs.w	r3, r7, lr
     408:	eb62 0708 	sbc.w	r7, r2, r8
     40c:	fa07 fc0c 	lsl.w	ip, r7, ip
     410:	40cb      	lsrs	r3, r1
     412:	40cf      	lsrs	r7, r1
     414:	ea4c 0303 	orr.w	r3, ip, r3
     418:	e9c6 3700 	strd	r3, r7, [r6]
     41c:	e79d      	b.n	35a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xda>
     41e:	4640      	mov	r0, r8
     420:	e7c7      	b.n	3b2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x132>
     422:	4643      	mov	r3, r8
     424:	e7db      	b.n	3de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x15e>
     426:	4631      	mov	r1, r6
     428:	e6ff      	b.n	22a <__data_size+0x26>
	...

0000042c <uart_irq_handler>:

#define BUF_SIZE 64
static K_MEM_SLAB_DEFINE(uart_slab, BUF_SIZE, 3, 4);

static void uart_irq_handler(const struct device *dev, void *context)
{
     42c:	b510      	push	{r4, lr}
     42e:	4604      	mov	r4, r0
	uint8_t buf[] = {1, 2, 3, 4, 5};
     430:	4b1a      	ldr	r3, [pc, #104]	; (49c <uart_irq_handler+0x70>)
{
     432:	b086      	sub	sp, #24
	uint8_t buf[] = {1, 2, 3, 4, 5};
     434:	6818      	ldr	r0, [r3, #0]
     436:	791b      	ldrb	r3, [r3, #4]
     438:	9001      	str	r0, [sp, #4]
     43a:	f88d 3008 	strb.w	r3, [sp, #8]
{
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	if (api->irq_tx_ready == NULL) {
     43e:	68a3      	ldr	r3, [r4, #8]
     440:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
     442:	b943      	cbnz	r3, 456 <uart_irq_handler+0x2a>
	if (api->fifo_fill == NULL) {
     444:	68a3      	ldr	r3, [r4, #8]
     446:	6adb      	ldr	r3, [r3, #44]	; 0x2c
     448:	b993      	cbnz	r3, 470 <uart_irq_handler+0x44>
	if (api->irq_tx_disable != NULL) {
     44a:	68a3      	ldr	r3, [r4, #8]
     44c:	6b9b      	ldr	r3, [r3, #56]	; 0x38
     44e:	b133      	cbz	r3, 45e <uart_irq_handler+0x32>
		api->irq_tx_disable(dev);
     450:	4620      	mov	r0, r4
     452:	4798      	blx	r3
     454:	e003      	b.n	45e <uart_irq_handler+0x32>
		return -ENOSYS;
	}

	return api->irq_tx_ready(dev);
     456:	4620      	mov	r0, r4
     458:	4798      	blx	r3

	if (uart_irq_tx_ready(dev)) {
     45a:	2800      	cmp	r0, #0
     45c:	d1f2      	bne.n	444 <uart_irq_handler+0x18>
{
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	if (api->irq_rx_ready == NULL) {
     45e:	68a3      	ldr	r3, [r4, #8]
     460:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
     462:	b953      	cbnz	r3, 47a <uart_irq_handler+0x4e>
	if (api->fifo_read == NULL) {
     464:	68a3      	ldr	r3, [r4, #8]
     466:	6b1b      	ldr	r3, [r3, #48]	; 0x30
     468:	b96b      	cbnz	r3, 486 <uart_irq_handler+0x5a>
		return -ENOSYS;
     46a:	f06f 0157 	mvn.w	r1, #87	; 0x57
     46e:	e011      	b.n	494 <uart_irq_handler+0x68>
	return api->fifo_fill(dev, tx_data, size);
     470:	2205      	movs	r2, #5
     472:	4620      	mov	r0, r4
     474:	a901      	add	r1, sp, #4
     476:	4798      	blx	r3
     478:	e7e7      	b.n	44a <uart_irq_handler+0x1e>
		return -ENOSYS;
	}
	return api->irq_rx_ready(dev);
     47a:	4620      	mov	r0, r4
     47c:	4798      	blx	r3
		(void)uart_fifo_fill(dev, buf, sizeof(buf));
		uart_irq_tx_disable(dev);
	}

	if (uart_irq_rx_ready(dev)) {
     47e:	2800      	cmp	r0, #0
     480:	d1f0      	bne.n	464 <uart_irq_handler+0x38>

		if (len) {
			printk("read %d bytes\n", len);
		}
	}
}
     482:	b006      	add	sp, #24
     484:	bd10      	pop	{r4, pc}
	return api->fifo_read(dev, rx_data, size);
     486:	a903      	add	r1, sp, #12
     488:	220a      	movs	r2, #10
     48a:	4620      	mov	r0, r4
     48c:	4798      	blx	r3
		if (len) {
     48e:	4601      	mov	r1, r0
     490:	2800      	cmp	r0, #0
     492:	d0f6      	beq.n	482 <uart_irq_handler+0x56>
			printk("read %d bytes\n", len);
     494:	4802      	ldr	r0, [pc, #8]	; (4a0 <uart_irq_handler+0x74>)
     496:	f004 fe0f 	bl	50b8 <printk>
}
     49a:	e7f2      	b.n	482 <uart_irq_handler+0x56>
     49c:	00006f63 	.word	0x00006f63
     4a0:	00006f54 	.word	0x00006f54

000004a4 <main>:
		k_sleep(K_MSEC(100));
	}
}

void main(void)
{
     4a4:	b570      	push	{r4, r5, r6, lr}
static inline void uart_irq_callback_user_data_set(const struct device *dev,
						   uart_irq_callback_user_data_t cb,
						   void *user_data)
{
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
	const struct uart_driver_api *api =
     4a6:	4c13      	ldr	r4, [pc, #76]	; (4f4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc>)
	const struct device *lpuart = DEVICE_DT_GET(DT_NODELABEL(lpuart));
	printk("LPUART sample started\n");
     4a8:	4813      	ldr	r0, [pc, #76]	; (4f8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x10>)
     4aa:	f004 fe05 	bl	50b8 <printk>
     4ae:	68a3      	ldr	r3, [r4, #8]
		(const struct uart_driver_api *)dev->api;

	if ((api != NULL) && (api->irq_callback_set != NULL)) {
     4b0:	b12b      	cbz	r3, 4be <main+0x1a>
     4b2:	6e1b      	ldr	r3, [r3, #96]	; 0x60
     4b4:	b11b      	cbz	r3, 4be <main+0x1a>
		api->irq_callback_set(dev, cb, user_data);
     4b6:	2200      	movs	r2, #0
     4b8:	4620      	mov	r0, r4
     4ba:	4910      	ldr	r1, [pc, #64]	; (4fc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x14>)
     4bc:	4798      	blx	r3
	if (api->irq_rx_enable != NULL) {
     4be:	68a3      	ldr	r3, [r4, #8]
     4c0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
     4c2:	b10b      	cbz	r3, 4c8 <main+0x24>
		api->irq_rx_enable(dev);
     4c4:	480b      	ldr	r0, [pc, #44]	; (4f4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc>)
     4c6:	4798      	blx	r3
	if (api->irq_tx_enable != NULL) {
     4c8:	68a6      	ldr	r6, [r4, #8]
		api->irq_tx_enable(dev);
     4ca:	4d0a      	ldr	r5, [pc, #40]	; (4f4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc>)
	if (api->irq_tx_enable != NULL) {
     4cc:	6b73      	ldr	r3, [r6, #52]	; 0x34
     4ce:	b10b      	cbz	r3, 4d4 <main+0x30>
		api->irq_tx_enable(dev);
     4d0:	4628      	mov	r0, r5
     4d2:	4798      	blx	r3
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm0 = { .val = timeout };
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
     4d4:	2100      	movs	r1, #0
     4d6:	f44f 4080 	mov.w	r0, #16384	; 0x4000
     4da:	f004 f9f7 	bl	48cc <z_impl_k_sleep>
	api->poll_out(dev, out_char);
     4de:	68a3      	ldr	r3, [r4, #8]
     4e0:	21ff      	movs	r1, #255	; 0xff
     4e2:	4628      	mov	r0, r5
     4e4:	69db      	ldr	r3, [r3, #28]
     4e6:	4798      	blx	r3
     4e8:	2100      	movs	r1, #0
     4ea:	f640 40cd 	movw	r0, #3277	; 0xccd
     4ee:	f004 f9ed 	bl	48cc <z_impl_k_sleep>
	while (1) {
     4f2:	e7eb      	b.n	4cc <main+0x28>
     4f4:	00006a4c 	.word	0x00006a4c
     4f8:	00006f69 	.word	0x00006f69
     4fc:	0000042d 	.word	0x0000042d

00000500 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     500:	680b      	ldr	r3, [r1, #0]
     502:	3301      	adds	r3, #1
     504:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     506:	4b01      	ldr	r3, [pc, #4]	; (50c <char_out+0xc>)
     508:	681b      	ldr	r3, [r3, #0]
     50a:	4718      	bx	r3
     50c:	200000d8 	.word	0x200000d8

00000510 <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
     510:	b507      	push	{r0, r1, r2, lr}
     512:	460b      	mov	r3, r1

		if (ctx.buf_count) {
			buf_flush(&ctx);
		}
	} else {
		struct out_context ctx = { 0 };
     514:	2100      	movs	r1, #0
{
     516:	4602      	mov	r2, r0
		struct out_context ctx = { 0 };
     518:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
		k_spinlock_key_t key = k_spin_lock(&lock);
#endif

		cbvprintf(char_out, &ctx, fmt, ap);
     51a:	4803      	ldr	r0, [pc, #12]	; (528 <vprintk+0x18>)
     51c:	a901      	add	r1, sp, #4
     51e:	f000 f8e5 	bl	6ec <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
     522:	b003      	add	sp, #12
     524:	f85d fb04 	ldr.w	pc, [sp], #4
     528:	00000501 	.word	0x00000501

0000052c <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     52c:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     530:	f8b0 9018 	ldrh.w	r9, [r0, #24]
{
     534:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     536:	f019 0808 	ands.w	r8, r9, #8
{
     53a:	4693      	mov	fp, r2
	if (processing) {
     53c:	d00d      	beq.n	55a <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
     53e:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     540:	bf0c      	ite	eq
     542:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     546:	f049 0920 	orrne.w	r9, r9, #32
     54a:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     54e:	f38b 8811 	msr	BASEPRI, fp
     552:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     556:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     55a:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     55e:	2902      	cmp	r1, #2
     560:	d107      	bne.n	572 <process_event+0x46>
			evt = process_recheck(mgr);
     562:	4620      	mov	r0, r4
     564:	f004 fdcf 	bl	5106 <process_recheck>
		if (evt == EVT_NOP) {
     568:	2800      	cmp	r0, #0
     56a:	d0f0      	beq.n	54e <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     56c:	2801      	cmp	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     56e:	8b23      	ldrh	r3, [r4, #24]
		if (evt == EVT_COMPLETE) {
     570:	d14e      	bne.n	610 <process_event+0xe4>
			res = mgr->last_res;
     572:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     574:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     576:	2f00      	cmp	r7, #0
     578:	da15      	bge.n	5a6 <process_event+0x7a>
		*clients = mgr->clients;
     57a:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     57c:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     580:	e9c4 8800 	strd	r8, r8, [r4]
     584:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     588:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
     58a:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     58c:	8b21      	ldrh	r1, [r4, #24]
     58e:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     592:	45ca      	cmp	sl, r9
     594:	d002      	beq.n	59c <process_event+0x70>
		if (do_monitors
     596:	68a3      	ldr	r3, [r4, #8]
     598:	2b00      	cmp	r3, #0
     59a:	d15a      	bne.n	652 <process_event+0x126>
		    || !sys_slist_is_empty(&clients)
     59c:	b90d      	cbnz	r5, 5a2 <process_event+0x76>
		    || (transit != NULL)) {
     59e:	2e00      	cmp	r6, #0
     5a0:	d071      	beq.n	686 <process_event+0x15a>
     5a2:	2300      	movs	r3, #0
     5a4:	e056      	b.n	654 <process_event+0x128>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5a6:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     5aa:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     5ac:	2a01      	cmp	r2, #1
     5ae:	d81e      	bhi.n	5ee <process_event+0xc2>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5b0:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     5b4:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     5b6:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5b8:	b289      	uxth	r1, r1
     5ba:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     5be:	d10a      	bne.n	5d6 <process_event+0xaa>
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     5c0:	b13d      	cbz	r5, 5d2 <process_event+0xa6>
     5c2:	462a      	mov	r2, r5
     5c4:	8b63      	ldrh	r3, [r4, #26]

#define SYS_SLIST_STATIC_INIT(ptr_to_list) {NULL, NULL}

static inline sys_snode_t *z_snode_next_peek(sys_snode_t *node)
{
	return node->next;
     5c6:	6812      	ldr	r2, [r2, #0]
				mgr->refs += 1U;
     5c8:	3301      	adds	r3, #1
     5ca:	b29b      	uxth	r3, r3
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     5cc:	2a00      	cmp	r2, #0
     5ce:	d1fa      	bne.n	5c6 <process_event+0x9a>
     5d0:	8363      	strh	r3, [r4, #26]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5d2:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
     5d6:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     5d8:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     5da:	f004 fd94 	bl	5106 <process_recheck>
     5de:	4606      	mov	r6, r0
     5e0:	2800      	cmp	r0, #0
     5e2:	d0d3      	beq.n	58c <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     5e4:	8b23      	ldrh	r3, [r4, #24]
     5e6:	f043 0320 	orr.w	r3, r3, #32
     5ea:	8323      	strh	r3, [r4, #24]
     5ec:	e7cd      	b.n	58a <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
     5ee:	2b04      	cmp	r3, #4
     5f0:	d10c      	bne.n	60c <process_event+0xe0>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5f2:	f021 0107 	bic.w	r1, r1, #7
     5f6:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
     5f8:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     5fa:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     5fc:	f004 fd83 	bl	5106 <process_recheck>
     600:	4605      	mov	r5, r0
     602:	2800      	cmp	r0, #0
     604:	d0c1      	beq.n	58a <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     606:	f041 0120 	orr.w	r1, r1, #32
     60a:	8321      	strh	r1, [r4, #24]
     60c:	2500      	movs	r5, #0
     60e:	e7bc      	b.n	58a <process_event+0x5e>
		} else if (evt == EVT_START) {
     610:	2803      	cmp	r0, #3
     612:	d109      	bne.n	628 <process_event+0xfc>
			transit = mgr->transitions->start;
     614:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     616:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     61a:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     61c:	f043 0306 	orr.w	r3, r3, #6
}
     620:	2500      	movs	r5, #0
	mgr->flags = (state & ONOFF_STATE_MASK)
     622:	8323      	strh	r3, [r4, #24]
		res = 0;
     624:	462f      	mov	r7, r5
     626:	e7b1      	b.n	58c <process_event+0x60>
		} else if (evt == EVT_STOP) {
     628:	2804      	cmp	r0, #4
     62a:	d106      	bne.n	63a <process_event+0x10e>
			transit = mgr->transitions->stop;
     62c:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     62e:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     632:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     634:	f043 0304 	orr.w	r3, r3, #4
     638:	e7f2      	b.n	620 <process_event+0xf4>
		} else if (evt == EVT_RESET) {
     63a:	2805      	cmp	r0, #5
     63c:	d106      	bne.n	64c <process_event+0x120>
			transit = mgr->transitions->reset;
     63e:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     640:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     644:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     646:	f043 0305 	orr.w	r3, r3, #5
     64a:	e7e9      	b.n	620 <process_event+0xf4>
     64c:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     64e:	462e      	mov	r6, r5
     650:	e7e8      	b.n	624 <process_event+0xf8>
				   && !sys_slist_is_empty(&mgr->monitors);
     652:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     654:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     658:	8321      	strh	r1, [r4, #24]
     65a:	f38b 8811 	msr	BASEPRI, fp
     65e:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     662:	b9fb      	cbnz	r3, 6a4 <process_event+0x178>
	while (!sys_slist_is_empty(list)) {
     664:	bb85      	cbnz	r5, 6c8 <process_event+0x19c>
			if (transit != NULL) {
     666:	b116      	cbz	r6, 66e <process_event+0x142>
				transit(mgr, transition_complete);
     668:	4620      	mov	r0, r4
     66a:	491f      	ldr	r1, [pc, #124]	; (6e8 <process_event+0x1bc>)
     66c:	47b0      	blx	r6
	__asm__ volatile(
     66e:	f04f 0320 	mov.w	r3, #32
     672:	f3ef 8b11 	mrs	fp, BASEPRI
     676:	f383 8812 	msr	BASEPRI_MAX, r3
     67a:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     67e:	8b23      	ldrh	r3, [r4, #24]
     680:	f023 0308 	bic.w	r3, r3, #8
     684:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     686:	8b23      	ldrh	r3, [r4, #24]
     688:	06da      	lsls	r2, r3, #27
     68a:	d525      	bpl.n	6d8 <process_event+0x1ac>
			evt = EVT_COMPLETE;
     68c:	2101      	movs	r1, #1
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     68e:	f023 0310 	bic.w	r3, r3, #16
     692:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     694:	f8b4 9018 	ldrh.w	r9, [r4, #24]
     698:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     69c:	2900      	cmp	r1, #0
     69e:	f47f af5e 	bne.w	55e <process_event+0x32>
out:
     6a2:	e754      	b.n	54e <process_event+0x22>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     6a4:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     6a6:	2900      	cmp	r1, #0
     6a8:	d0dc      	beq.n	664 <process_event+0x138>
	return node->next;
     6aa:	f8d1 9000 	ldr.w	r9, [r1]
		mon->callback(mgr, mon, state, res);
     6ae:	463b      	mov	r3, r7
     6b0:	4652      	mov	r2, sl
     6b2:	4620      	mov	r0, r4
     6b4:	f8d1 b004 	ldr.w	fp, [r1, #4]
     6b8:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     6ba:	f1b9 0f00 	cmp.w	r9, #0
     6be:	d0d1      	beq.n	664 <process_event+0x138>
     6c0:	4649      	mov	r1, r9
     6c2:	f8d9 9000 	ldr.w	r9, [r9]
     6c6:	e7f2      	b.n	6ae <process_event+0x182>
     6c8:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     6ca:	463b      	mov	r3, r7
     6cc:	4652      	mov	r2, sl
     6ce:	4620      	mov	r0, r4
     6d0:	682d      	ldr	r5, [r5, #0]
     6d2:	f004 fd34 	bl	513e <notify_one>
     6d6:	e7c5      	b.n	664 <process_event+0x138>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     6d8:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     6dc:	bf1e      	ittt	ne
     6de:	f023 0320 	bicne.w	r3, r3, #32
			evt = EVT_RECHECK;
     6e2:	2102      	movne	r1, #2
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     6e4:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
     6e6:	e7d5      	b.n	694 <process_event+0x168>
     6e8:	0000516b 	.word	0x0000516b

000006ec <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     6ec:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     6f0:	468b      	mov	fp, r1
     6f2:	4692      	mov	sl, r2
     6f4:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     6f6:	2500      	movs	r5, #0
{
     6f8:	b091      	sub	sp, #68	; 0x44
     6fa:	9002      	str	r0, [sp, #8]
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     6fc:	f89a 0000 	ldrb.w	r0, [sl]
     700:	b908      	cbnz	r0, 706 <cbvprintf+0x1a>
			OUTC(' ');
			--width;
		}
	}

	return count;
     702:	4628      	mov	r0, r5
     704:	e35f      	b.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
		if (*fp != '%') {
     706:	2825      	cmp	r0, #37	; 0x25
			OUTC(*fp++);
     708:	f10a 0701 	add.w	r7, sl, #1
		if (*fp != '%') {
     70c:	d007      	beq.n	71e <cbvprintf+0x32>
			OUTC('%');
     70e:	4659      	mov	r1, fp
     710:	9b02      	ldr	r3, [sp, #8]
     712:	4798      	blx	r3
     714:	2800      	cmp	r0, #0
     716:	f2c0 8356 	blt.w	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     71a:	3501      	adds	r5, #1
			break;
     71c:	e212      	b.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
		} state = {
     71e:	2218      	movs	r2, #24
     720:	2100      	movs	r1, #0
     722:	a80a      	add	r0, sp, #40	; 0x28
     724:	f004 feae 	bl	5484 <memset>
	if (*sp == '%') {
     728:	f89a 3001 	ldrb.w	r3, [sl, #1]
     72c:	2b25      	cmp	r3, #37	; 0x25
     72e:	d078      	beq.n	822 <CONFIG_ISR_STACK_SIZE+0x22>
     730:	2200      	movs	r2, #0
     732:	4610      	mov	r0, r2
     734:	4696      	mov	lr, r2
     736:	4694      	mov	ip, r2
     738:	4616      	mov	r6, r2
     73a:	4639      	mov	r1, r7
		switch (*sp) {
     73c:	f817 3b01 	ldrb.w	r3, [r7], #1
     740:	2b2b      	cmp	r3, #43	; 0x2b
     742:	f000 809d 	beq.w	880 <CONFIG_ISR_STACK_SIZE+0x80>
     746:	f200 8094 	bhi.w	872 <CONFIG_ISR_STACK_SIZE+0x72>
     74a:	2b20      	cmp	r3, #32
     74c:	f000 809b 	beq.w	886 <CONFIG_ISR_STACK_SIZE+0x86>
     750:	2b23      	cmp	r3, #35	; 0x23
     752:	f000 809b 	beq.w	88c <CONFIG_ISR_STACK_SIZE+0x8c>
     756:	b12e      	cbz	r6, 764 <cbvprintf+0x78>
     758:	f89d 6030 	ldrb.w	r6, [sp, #48]	; 0x30
     75c:	f046 0604 	orr.w	r6, r6, #4
     760:	f88d 6030 	strb.w	r6, [sp, #48]	; 0x30
     764:	f1bc 0f00 	cmp.w	ip, #0
     768:	d005      	beq.n	776 <cbvprintf+0x8a>
     76a:	f89d 6030 	ldrb.w	r6, [sp, #48]	; 0x30
     76e:	f046 0608 	orr.w	r6, r6, #8
     772:	f88d 6030 	strb.w	r6, [sp, #48]	; 0x30
     776:	f1be 0f00 	cmp.w	lr, #0
     77a:	d005      	beq.n	788 <cbvprintf+0x9c>
     77c:	f89d 6030 	ldrb.w	r6, [sp, #48]	; 0x30
     780:	f046 0610 	orr.w	r6, r6, #16
     784:	f88d 6030 	strb.w	r6, [sp, #48]	; 0x30
     788:	b128      	cbz	r0, 796 <cbvprintf+0xaa>
     78a:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     78e:	f040 0020 	orr.w	r0, r0, #32
     792:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     796:	b12a      	cbz	r2, 7a4 <cbvprintf+0xb8>
     798:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     79c:	f042 0240 	orr.w	r2, r2, #64	; 0x40
     7a0:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (conv->flag_zero && conv->flag_dash) {
     7a4:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     7a8:	f002 0044 	and.w	r0, r2, #68	; 0x44
     7ac:	2844      	cmp	r0, #68	; 0x44
     7ae:	d103      	bne.n	7b8 <cbvprintf+0xcc>
		conv->flag_zero = false;
     7b0:	f36f 1286 	bfc	r2, #6, #1
     7b4:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	conv->width_present = true;
     7b8:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
     7bc:	2b2a      	cmp	r3, #42	; 0x2a
	conv->width_present = true;
     7be:	f042 0280 	orr.w	r2, r2, #128	; 0x80
     7c2:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
     7c6:	d17b      	bne.n	8c0 <CONFIG_ISR_STACK_SIZE+0xc0>
		conv->width_star = true;
     7c8:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
			++sp;
     7cc:	1c4b      	adds	r3, r1, #1
		conv->width_star = true;
     7ce:	f042 0201 	orr.w	r2, r2, #1
     7d2:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	conv->prec_present = (*sp == '.');
     7d6:	781a      	ldrb	r2, [r3, #0]
     7d8:	2a2e      	cmp	r2, #46	; 0x2e
     7da:	bf0c      	ite	eq
     7dc:	2101      	moveq	r1, #1
     7de:	2100      	movne	r1, #0
     7e0:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     7e4:	f361 0241 	bfi	r2, r1, #1, #1
     7e8:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	if (!conv->prec_present) {
     7ec:	d174      	bne.n	8d8 <CONFIG_ISR_STACK_SIZE+0xd8>
	if (*sp == '*') {
     7ee:	785a      	ldrb	r2, [r3, #1]
     7f0:	2a2a      	cmp	r2, #42	; 0x2a
     7f2:	d06a      	beq.n	8ca <CONFIG_ISR_STACK_SIZE+0xca>
	size_t val = 0;
     7f4:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
     7f6:	260a      	movs	r6, #10
	++sp;
     7f8:	3301      	adds	r3, #1
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     7fa:	4618      	mov	r0, r3
     7fc:	f810 2b01 	ldrb.w	r2, [r0], #1
     800:	f1a2 0730 	sub.w	r7, r2, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     804:	2f09      	cmp	r7, #9
     806:	f240 808e 	bls.w	926 <CONFIG_ISR_STACK_SIZE+0x126>
	conv->unsupported |= ((conv->prec_value < 0)
     80a:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	conv->prec_value = prec;
     80e:	910e      	str	r1, [sp, #56]	; 0x38
	conv->unsupported |= ((conv->prec_value < 0)
     810:	f3c2 0040 	ubfx	r0, r2, #1, #1
     814:	ea40 71d1 	orr.w	r1, r0, r1, lsr #31
     818:	f361 0241 	bfi	r2, r1, #1, #1
     81c:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
     820:	e05a      	b.n	8d8 <CONFIG_ISR_STACK_SIZE+0xd8>
		conv->specifier = *sp++;
     822:	f10a 0702 	add.w	r7, sl, #2
     826:	f88d 3033 	strb.w	r3, [sp, #51]	; 0x33
		if (conv->width_star) {
     82a:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     82e:	07d9      	lsls	r1, r3, #31
     830:	f140 8149 	bpl.w	ac6 <CONFIG_ISR_STACK_SIZE+0x2c6>
			width = va_arg(ap, int);
     834:	f854 9b04 	ldr.w	r9, [r4], #4
			if (width < 0) {
     838:	f1b9 0f00 	cmp.w	r9, #0
     83c:	da07      	bge.n	84e <CONFIG_ISR_STACK_SIZE+0x4e>
				conv->flag_dash = true;
     83e:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
				width = -width;
     842:	f1c9 0900 	rsb	r9, r9, #0
				conv->flag_dash = true;
     846:	f042 0204 	orr.w	r2, r2, #4
     84a:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
		if (conv->prec_star) {
     84e:	075a      	lsls	r2, r3, #29
     850:	f140 8142 	bpl.w	ad8 <CONFIG_ISR_STACK_SIZE+0x2d8>
			int arg = va_arg(ap, int);
     854:	f854 8b04 	ldr.w	r8, [r4], #4
			if (arg < 0) {
     858:	f1b8 0f00 	cmp.w	r8, #0
     85c:	f280 8141 	bge.w	ae2 <CONFIG_ISR_STACK_SIZE+0x2e2>
				conv->prec_present = false;
     860:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     864:	f36f 0341 	bfc	r3, #1, #1
     868:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		int precision = -1;
     86c:	f04f 38ff 	mov.w	r8, #4294967295
     870:	e137      	b.n	ae2 <CONFIG_ISR_STACK_SIZE+0x2e2>
		switch (*sp) {
     872:	2b2d      	cmp	r3, #45	; 0x2d
     874:	d00c      	beq.n	890 <CONFIG_ISR_STACK_SIZE+0x90>
     876:	2b30      	cmp	r3, #48	; 0x30
     878:	f47f af6d 	bne.w	756 <cbvprintf+0x6a>
			conv->flag_zero = true;
     87c:	2201      	movs	r2, #1
	} while (loop);
     87e:	e75c      	b.n	73a <cbvprintf+0x4e>
			conv->flag_plus = true;
     880:	f04f 0c01 	mov.w	ip, #1
     884:	e759      	b.n	73a <cbvprintf+0x4e>
			conv->flag_space = true;
     886:	f04f 0e01 	mov.w	lr, #1
     88a:	e756      	b.n	73a <cbvprintf+0x4e>
			conv->flag_hash = true;
     88c:	2001      	movs	r0, #1
     88e:	e754      	b.n	73a <cbvprintf+0x4e>
		switch (*sp) {
     890:	2601      	movs	r6, #1
     892:	e752      	b.n	73a <cbvprintf+0x4e>
		val = 10U * val + *sp++ - '0';
     894:	4633      	mov	r3, r6
     896:	fb0c 0202 	mla	r2, ip, r2, r0
     89a:	3a30      	subs	r2, #48	; 0x30
     89c:	461e      	mov	r6, r3
     89e:	f816 0b01 	ldrb.w	r0, [r6], #1
     8a2:	f1a0 0730 	sub.w	r7, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     8a6:	2f09      	cmp	r7, #9
     8a8:	d9f4      	bls.n	894 <CONFIG_ISR_STACK_SIZE+0x94>
	if (sp != wp) {
     8aa:	4299      	cmp	r1, r3
     8ac:	d093      	beq.n	7d6 <cbvprintf+0xea>
		conv->unsupported |= ((conv->width_value < 0)
     8ae:	f89d 1030 	ldrb.w	r1, [sp, #48]	; 0x30
		conv->width_value = width;
     8b2:	920d      	str	r2, [sp, #52]	; 0x34
				      || (width != (size_t)conv->width_value));
     8b4:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
     8b6:	f362 0141 	bfi	r1, r2, #1, #1
     8ba:	f88d 1030 	strb.w	r1, [sp, #48]	; 0x30
     8be:	e78a      	b.n	7d6 <cbvprintf+0xea>
     8c0:	460b      	mov	r3, r1
	size_t val = 0;
     8c2:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     8c4:	f04f 0c0a 	mov.w	ip, #10
     8c8:	e7e8      	b.n	89c <CONFIG_ISR_STACK_SIZE+0x9c>
		conv->prec_star = true;
     8ca:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
		return ++sp;
     8ce:	3302      	adds	r3, #2
		conv->prec_star = true;
     8d0:	f042 0204 	orr.w	r2, r2, #4
     8d4:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	switch (*sp) {
     8d8:	461f      	mov	r7, r3
     8da:	f817 2b01 	ldrb.w	r2, [r7], #1
     8de:	2a6c      	cmp	r2, #108	; 0x6c
     8e0:	d041      	beq.n	966 <CONFIG_ISR_STACK_SIZE+0x166>
     8e2:	d825      	bhi.n	930 <CONFIG_ISR_STACK_SIZE+0x130>
     8e4:	2a68      	cmp	r2, #104	; 0x68
     8e6:	d02b      	beq.n	940 <CONFIG_ISR_STACK_SIZE+0x140>
     8e8:	2a6a      	cmp	r2, #106	; 0x6a
     8ea:	d046      	beq.n	97a <CONFIG_ISR_STACK_SIZE+0x17a>
     8ec:	2a4c      	cmp	r2, #76	; 0x4c
     8ee:	d04c      	beq.n	98a <CONFIG_ISR_STACK_SIZE+0x18a>
     8f0:	461f      	mov	r7, r3
	conv->specifier = *sp++;
     8f2:	f817 2b01 	ldrb.w	r2, [r7], #1
		if (conv->length_mod == LENGTH_UPPER_L) {
     8f6:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
	switch (conv->specifier) {
     8fa:	2a78      	cmp	r2, #120	; 0x78
	conv->specifier = *sp++;
     8fc:	f88d 2033 	strb.w	r2, [sp, #51]	; 0x33
	switch (conv->specifier) {
     900:	f200 80d9 	bhi.w	ab6 <CONFIG_ISR_STACK_SIZE+0x2b6>
     904:	2a57      	cmp	r2, #87	; 0x57
     906:	d84d      	bhi.n	9a4 <CONFIG_ISR_STACK_SIZE+0x1a4>
     908:	2a41      	cmp	r2, #65	; 0x41
     90a:	d003      	beq.n	914 <CONFIG_ISR_STACK_SIZE+0x114>
     90c:	3a45      	subs	r2, #69	; 0x45
     90e:	2a02      	cmp	r2, #2
     910:	f200 80d1 	bhi.w	ab6 <CONFIG_ISR_STACK_SIZE+0x2b6>
		conv->specifier_cat = SPECIFIER_FP;
     914:	2204      	movs	r2, #4
     916:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     91a:	f362 0302 	bfi	r3, r2, #0, #3
     91e:	f88d 3032 	strb.w	r3, [sp, #50]	; 0x32
			unsupported = true;
     922:	2301      	movs	r3, #1
			break;
     924:	e09e      	b.n	a64 <CONFIG_ISR_STACK_SIZE+0x264>
		val = 10U * val + *sp++ - '0';
     926:	fb06 2101 	mla	r1, r6, r1, r2
     92a:	4603      	mov	r3, r0
     92c:	3930      	subs	r1, #48	; 0x30
     92e:	e764      	b.n	7fa <cbvprintf+0x10e>
	switch (*sp) {
     930:	2a74      	cmp	r2, #116	; 0x74
     932:	d026      	beq.n	982 <CONFIG_ISR_STACK_SIZE+0x182>
     934:	2a7a      	cmp	r2, #122	; 0x7a
     936:	d1db      	bne.n	8f0 <CONFIG_ISR_STACK_SIZE+0xf0>
		conv->length_mod = LENGTH_Z;
     938:	2206      	movs	r2, #6
     93a:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     93e:	e00d      	b.n	95c <CONFIG_ISR_STACK_SIZE+0x15c>
		if (*++sp == 'h') {
     940:	785a      	ldrb	r2, [r3, #1]
     942:	2a68      	cmp	r2, #104	; 0x68
     944:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     948:	d106      	bne.n	958 <CONFIG_ISR_STACK_SIZE+0x158>
			conv->length_mod = LENGTH_HH;
     94a:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     94c:	f361 02c6 	bfi	r2, r1, #3, #4
     950:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
			++sp;
     954:	1c9f      	adds	r7, r3, #2
     956:	e7cc      	b.n	8f2 <CONFIG_ISR_STACK_SIZE+0xf2>
			conv->length_mod = LENGTH_H;
     958:	4613      	mov	r3, r2
     95a:	2202      	movs	r2, #2
		conv->length_mod = LENGTH_T;
     95c:	f362 03c6 	bfi	r3, r2, #3, #4
     960:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		break;
     964:	e7c5      	b.n	8f2 <CONFIG_ISR_STACK_SIZE+0xf2>
		if (*++sp == 'l') {
     966:	785a      	ldrb	r2, [r3, #1]
     968:	2a6c      	cmp	r2, #108	; 0x6c
     96a:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     96e:	d101      	bne.n	974 <CONFIG_ISR_STACK_SIZE+0x174>
			conv->length_mod = LENGTH_LL;
     970:	2104      	movs	r1, #4
     972:	e7eb      	b.n	94c <CONFIG_ISR_STACK_SIZE+0x14c>
			conv->length_mod = LENGTH_L;
     974:	4613      	mov	r3, r2
     976:	2203      	movs	r2, #3
     978:	e7f0      	b.n	95c <CONFIG_ISR_STACK_SIZE+0x15c>
		conv->length_mod = LENGTH_J;
     97a:	2205      	movs	r2, #5
     97c:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     980:	e7ec      	b.n	95c <CONFIG_ISR_STACK_SIZE+0x15c>
		conv->length_mod = LENGTH_T;
     982:	2207      	movs	r2, #7
     984:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     988:	e7e8      	b.n	95c <CONFIG_ISR_STACK_SIZE+0x15c>
		conv->unsupported = true;
     98a:	f8bd 3030 	ldrh.w	r3, [sp, #48]	; 0x30
     98e:	f423 43f0 	bic.w	r3, r3, #30720	; 0x7800
     992:	f023 0302 	bic.w	r3, r3, #2
     996:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
     99a:	f043 0302 	orr.w	r3, r3, #2
     99e:	f8ad 3030 	strh.w	r3, [sp, #48]	; 0x30
		break;
     9a2:	e7a6      	b.n	8f2 <CONFIG_ISR_STACK_SIZE+0xf2>
	switch (conv->specifier) {
     9a4:	f1a2 0158 	sub.w	r1, r2, #88	; 0x58
     9a8:	2920      	cmp	r1, #32
     9aa:	f200 8084 	bhi.w	ab6 <CONFIG_ISR_STACK_SIZE+0x2b6>
     9ae:	a001      	add	r0, pc, #4	; (adr r0, 9b4 <CONFIG_ISR_STACK_SIZE+0x1b4>)
     9b0:	f850 f021 	ldr.w	pc, [r0, r1, lsl #2]
     9b4:	00000a79 	.word	0x00000a79
     9b8:	00000ab7 	.word	0x00000ab7
     9bc:	00000ab7 	.word	0x00000ab7
     9c0:	00000ab7 	.word	0x00000ab7
     9c4:	00000ab7 	.word	0x00000ab7
     9c8:	00000ab7 	.word	0x00000ab7
     9cc:	00000ab7 	.word	0x00000ab7
     9d0:	00000ab7 	.word	0x00000ab7
     9d4:	00000ab7 	.word	0x00000ab7
     9d8:	00000915 	.word	0x00000915
     9dc:	00000ab7 	.word	0x00000ab7
     9e0:	00000a79 	.word	0x00000a79
     9e4:	00000a39 	.word	0x00000a39
     9e8:	00000915 	.word	0x00000915
     9ec:	00000915 	.word	0x00000915
     9f0:	00000915 	.word	0x00000915
     9f4:	00000ab7 	.word	0x00000ab7
     9f8:	00000a39 	.word	0x00000a39
     9fc:	00000ab7 	.word	0x00000ab7
     a00:	00000ab7 	.word	0x00000ab7
     a04:	00000ab7 	.word	0x00000ab7
     a08:	00000ab7 	.word	0x00000ab7
     a0c:	00000a81 	.word	0x00000a81
     a10:	00000a79 	.word	0x00000a79
     a14:	00000a9d 	.word	0x00000a9d
     a18:	00000ab7 	.word	0x00000ab7
     a1c:	00000ab7 	.word	0x00000ab7
     a20:	00000a9d 	.word	0x00000a9d
     a24:	00000ab7 	.word	0x00000ab7
     a28:	00000a79 	.word	0x00000a79
     a2c:	00000ab7 	.word	0x00000ab7
     a30:	00000ab7 	.word	0x00000ab7
     a34:	00000a79 	.word	0x00000a79
		conv->specifier_cat = SPECIFIER_SINT;
     a38:	2001      	movs	r0, #1
     a3a:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     a3e:	f003 0378 	and.w	r3, r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
     a42:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     a46:	2b40      	cmp	r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
     a48:	f88d 1032 	strb.w	r1, [sp, #50]	; 0x32
			conv->invalid = true;
     a4c:	bf02      	ittt	eq
     a4e:	f89d 1030 	ldrbeq.w	r1, [sp, #48]	; 0x30
     a52:	f041 0101 	orreq.w	r1, r1, #1
     a56:	f88d 1030 	strbeq.w	r1, [sp, #48]	; 0x30
		if (conv->specifier == 'c') {
     a5a:	2a63      	cmp	r2, #99	; 0x63
     a5c:	d131      	bne.n	ac2 <CONFIG_ISR_STACK_SIZE+0x2c2>
			unsupported = (conv->length_mod != LENGTH_NONE);
     a5e:	3b00      	subs	r3, #0
     a60:	bf18      	it	ne
     a62:	2301      	movne	r3, #1
	conv->unsupported |= unsupported;
     a64:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     a68:	f3c2 0140 	ubfx	r1, r2, #1, #1
     a6c:	430b      	orrs	r3, r1
     a6e:	f363 0241 	bfi	r2, r3, #1, #1
     a72:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
     a76:	e6d8      	b.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
		conv->specifier_cat = SPECIFIER_UINT;
     a78:	2002      	movs	r0, #2
     a7a:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
     a7e:	e7de      	b.n	a3e <CONFIG_ISR_STACK_SIZE+0x23e>
		conv->specifier_cat = SPECIFIER_PTR;
     a80:	2103      	movs	r1, #3
     a82:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     a86:	f003 0378 	and.w	r3, r3, #120	; 0x78
     a8a:	f1a3 0040 	sub.w	r0, r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_PTR;
     a8e:	f361 0202 	bfi	r2, r1, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     a92:	4243      	negs	r3, r0
		conv->specifier_cat = SPECIFIER_PTR;
     a94:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     a98:	4143      	adcs	r3, r0
     a9a:	e7e3      	b.n	a64 <CONFIG_ISR_STACK_SIZE+0x264>
		conv->specifier_cat = SPECIFIER_PTR;
     a9c:	2103      	movs	r1, #3
     a9e:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod != LENGTH_NONE) {
     aa2:	f013 0f78 	tst.w	r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
     aa6:	f361 0202 	bfi	r2, r1, #0, #3
		if (conv->length_mod != LENGTH_NONE) {
     aaa:	bf14      	ite	ne
     aac:	2301      	movne	r3, #1
     aae:	2300      	moveq	r3, #0
		conv->specifier_cat = SPECIFIER_PTR;
     ab0:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod != LENGTH_NONE) {
     ab4:	e7d6      	b.n	a64 <CONFIG_ISR_STACK_SIZE+0x264>
		conv->invalid = true;
     ab6:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
     aba:	f043 0301 	orr.w	r3, r3, #1
     abe:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
	bool unsupported = false;
     ac2:	2300      	movs	r3, #0
     ac4:	e7ce      	b.n	a64 <CONFIG_ISR_STACK_SIZE+0x264>
		} else if (conv->width_present) {
     ac6:	f99d 2030 	ldrsb.w	r2, [sp, #48]	; 0x30
     aca:	2a00      	cmp	r2, #0
		int width = -1;
     acc:	bfac      	ite	ge
     ace:	f04f 39ff 	movge.w	r9, #4294967295
			width = conv->width_value;
     ad2:	f8dd 9034 	ldrlt.w	r9, [sp, #52]	; 0x34
     ad6:	e6ba      	b.n	84e <CONFIG_ISR_STACK_SIZE+0x4e>
		} else if (conv->prec_present) {
     ad8:	079b      	lsls	r3, r3, #30
     ada:	f57f aec7 	bpl.w	86c <CONFIG_ISR_STACK_SIZE+0x6c>
			precision = conv->prec_value;
     ade:	f8dd 8038 	ldr.w	r8, [sp, #56]	; 0x38
		conv->pad0_value = 0;
     ae2:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     ae4:	e9cd 330d 	strd	r3, r3, [sp, #52]	; 0x34
			= (enum specifier_cat_enum)conv->specifier_cat;
     ae8:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
			= (enum length_mod_enum)conv->length_mod;
     aec:	f89d 1031 	ldrb.w	r1, [sp, #49]	; 0x31
		enum specifier_cat_enum specifier_cat
     af0:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     af4:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     af6:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     afa:	d138      	bne.n	b6e <CONFIG_ISR_STACK_SIZE+0x36e>
			switch (length_mod) {
     afc:	1ecb      	subs	r3, r1, #3
     afe:	2b04      	cmp	r3, #4
     b00:	d822      	bhi.n	b48 <CONFIG_ISR_STACK_SIZE+0x348>
     b02:	e8df f003 	tbb	[pc, r3]
     b06:	0903      	.short	0x0903
     b08:	2109      	.short	0x2109
     b0a:	21          	.byte	0x21
     b0b:	00          	.byte	0x00
					value->sint = va_arg(ap, long);
     b0c:	f854 3b04 	ldr.w	r3, [r4], #4
				value->sint = (short)value->sint;
     b10:	17da      	asrs	r2, r3, #31
     b12:	e9cd 320a 	strd	r3, r2, [sp, #40]	; 0x28
     b16:	e006      	b.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
					(sint_value_type)va_arg(ap, intmax_t);
     b18:	3407      	adds	r4, #7
     b1a:	f024 0407 	bic.w	r4, r4, #7
				value->sint =
     b1e:	e8f4 2302 	ldrd	r2, r3, [r4], #8
     b22:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
		if (conv->invalid || conv->unsupported) {
     b26:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
     b2a:	f013 0603 	ands.w	r6, r3, #3
     b2e:	d056      	beq.n	bde <CONFIG_ISR_STACK_SIZE+0x3de>
			OUTS(sp, fp);
     b30:	463b      	mov	r3, r7
     b32:	4652      	mov	r2, sl
     b34:	4659      	mov	r1, fp
     b36:	9802      	ldr	r0, [sp, #8]
     b38:	f004 fc21 	bl	537e <outs>
     b3c:	2800      	cmp	r0, #0
     b3e:	f2c0 8142 	blt.w	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     b42:	4405      	add	r5, r0
			continue;
     b44:	46ba      	mov	sl, r7
     b46:	e5d9      	b.n	6fc <cbvprintf+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     b48:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
     b4c:	2901      	cmp	r1, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
     b4e:	ea4f 72e3 	mov.w	r2, r3, asr #31
     b52:	e9cd 320a 	strd	r3, r2, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
     b56:	d105      	bne.n	b64 <CONFIG_ISR_STACK_SIZE+0x364>
				value->uint = (unsigned char)value->uint;
     b58:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
				value->uint = (unsigned short)value->uint;
     b5c:	930a      	str	r3, [sp, #40]	; 0x28
     b5e:	2300      	movs	r3, #0
     b60:	930b      	str	r3, [sp, #44]	; 0x2c
     b62:	e7e0      	b.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
			} else if (length_mod == LENGTH_H) {
     b64:	2902      	cmp	r1, #2
     b66:	d1de      	bne.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
				value->sint = (short)value->sint;
     b68:	f9bd 3028 	ldrsh.w	r3, [sp, #40]	; 0x28
     b6c:	e7d0      	b.n	b10 <CONFIG_ISR_STACK_SIZE+0x310>
		} else if (specifier_cat == SPECIFIER_UINT) {
     b6e:	2b02      	cmp	r3, #2
     b70:	d123      	bne.n	bba <CONFIG_ISR_STACK_SIZE+0x3ba>
			switch (length_mod) {
     b72:	1ecb      	subs	r3, r1, #3
     b74:	2b04      	cmp	r3, #4
     b76:	d813      	bhi.n	ba0 <CONFIG_ISR_STACK_SIZE+0x3a0>
     b78:	e8df f003 	tbb	[pc, r3]
     b7c:	120a0a03 	.word	0x120a0a03
     b80:	12          	.byte	0x12
     b81:	00          	.byte	0x00
				if ((!WCHAR_IS_SIGNED)
     b82:	2300      	movs	r3, #0
					value->uint = (wchar_t)va_arg(ap,
     b84:	6822      	ldr	r2, [r4, #0]
				value->sint = va_arg(ap, int);
     b86:	1d20      	adds	r0, r4, #4
					value->uint = (wchar_t)va_arg(ap,
     b88:	920a      	str	r2, [sp, #40]	; 0x28
     b8a:	930b      	str	r3, [sp, #44]	; 0x2c
					(uint_value_type)va_arg(ap, size_t);
     b8c:	4604      	mov	r4, r0
     b8e:	e7ca      	b.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
					(uint_value_type)va_arg(ap,
     b90:	1de0      	adds	r0, r4, #7
     b92:	f020 0007 	bic.w	r0, r0, #7
				value->uint =
     b96:	e8f0 2302 	ldrd	r2, r3, [r0], #8
     b9a:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
				break;
     b9e:	e7f5      	b.n	b8c <CONFIG_ISR_STACK_SIZE+0x38c>
					(uint_value_type)va_arg(ap, size_t);
     ba0:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
     ba4:	2901      	cmp	r1, #1
					(uint_value_type)va_arg(ap, size_t);
     ba6:	930a      	str	r3, [sp, #40]	; 0x28
     ba8:	f04f 0300 	mov.w	r3, #0
     bac:	930b      	str	r3, [sp, #44]	; 0x2c
			if (length_mod == LENGTH_HH) {
     bae:	d0d3      	beq.n	b58 <CONFIG_ISR_STACK_SIZE+0x358>
			} else if (length_mod == LENGTH_H) {
     bb0:	2902      	cmp	r1, #2
     bb2:	d1b8      	bne.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
				value->uint = (unsigned short)value->uint;
     bb4:	f8bd 3028 	ldrh.w	r3, [sp, #40]	; 0x28
     bb8:	e7d0      	b.n	b5c <CONFIG_ISR_STACK_SIZE+0x35c>
		} else if (specifier_cat == SPECIFIER_FP) {
     bba:	2b04      	cmp	r3, #4
     bbc:	d109      	bne.n	bd2 <CONFIG_ISR_STACK_SIZE+0x3d2>
					(sint_value_type)va_arg(ap, long long);
     bbe:	1de3      	adds	r3, r4, #7
     bc0:	f023 0307 	bic.w	r3, r3, #7
     bc4:	f103 0408 	add.w	r4, r3, #8
				value->ldbl = va_arg(ap, long double);
     bc8:	e9d3 2300 	ldrd	r2, r3, [r3]
     bcc:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
     bd0:	e7a9      	b.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
		} else if (specifier_cat == SPECIFIER_PTR) {
     bd2:	2b03      	cmp	r3, #3
			value->ptr = va_arg(ap, void *);
     bd4:	bf04      	itt	eq
     bd6:	f854 3b04 	ldreq.w	r3, [r4], #4
     bda:	930a      	streq	r3, [sp, #40]	; 0x28
     bdc:	e7a3      	b.n	b26 <CONFIG_ISR_STACK_SIZE+0x326>
		switch (conv->specifier) {
     bde:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
     be2:	2878      	cmp	r0, #120	; 0x78
     be4:	d8ae      	bhi.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
     be6:	2862      	cmp	r0, #98	; 0x62
     be8:	d822      	bhi.n	c30 <CONFIG_ISR_STACK_SIZE+0x430>
     bea:	2825      	cmp	r0, #37	; 0x25
     bec:	f43f ad8f 	beq.w	70e <cbvprintf+0x22>
     bf0:	2858      	cmp	r0, #88	; 0x58
     bf2:	d1a7      	bne.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
			bps = encode_uint(value->uint, conv, buf, bpe);
     bf4:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
     bf8:	f10d 0326 	add.w	r3, sp, #38	; 0x26
     bfc:	9300      	str	r3, [sp, #0]
     bfe:	aa0c      	add	r2, sp, #48	; 0x30
     c00:	ab04      	add	r3, sp, #16
     c02:	f004 fb76 	bl	52f2 <encode_uint>
     c06:	4682      	mov	sl, r0
			if (precision >= 0) {
     c08:	f1b8 0f00 	cmp.w	r8, #0
     c0c:	f10d 0026 	add.w	r0, sp, #38	; 0x26
     c10:	db0c      	blt.n	c2c <CONFIG_ISR_STACK_SIZE+0x42c>
				conv->flag_zero = false;
     c12:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
				size_t len = bpe - bps;
     c16:	eba0 030a 	sub.w	r3, r0, sl
				conv->flag_zero = false;
     c1a:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
     c1e:	4598      	cmp	r8, r3
				conv->flag_zero = false;
     c20:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				if (len < (size_t)precision) {
     c24:	d902      	bls.n	c2c <CONFIG_ISR_STACK_SIZE+0x42c>
					conv->pad0_value = precision - (int)len;
     c26:	eba8 0303 	sub.w	r3, r8, r3
     c2a:	930d      	str	r3, [sp, #52]	; 0x34
		const char *bpe = buf + sizeof(buf);
     c2c:	4680      	mov	r8, r0
     c2e:	e03d      	b.n	cac <CONFIG_ISR_STACK_SIZE+0x4ac>
		switch (conv->specifier) {
     c30:	3863      	subs	r0, #99	; 0x63
     c32:	2815      	cmp	r0, #21
     c34:	d886      	bhi.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
     c36:	a201      	add	r2, pc, #4	; (adr r2, c3c <CONFIG_ISR_STACK_SIZE+0x43c>)
     c38:	f852 f020 	ldr.w	pc, [r2, r0, lsl #2]
     c3c:	00000cbd 	.word	0x00000cbd
     c40:	00000d21 	.word	0x00000d21
     c44:	00000b45 	.word	0x00000b45
     c48:	00000b45 	.word	0x00000b45
     c4c:	00000b45 	.word	0x00000b45
     c50:	00000b45 	.word	0x00000b45
     c54:	00000d21 	.word	0x00000d21
     c58:	00000b45 	.word	0x00000b45
     c5c:	00000b45 	.word	0x00000b45
     c60:	00000b45 	.word	0x00000b45
     c64:	00000b45 	.word	0x00000b45
     c68:	00000d7b 	.word	0x00000d7b
     c6c:	00000d49 	.word	0x00000d49
     c70:	00000d4d 	.word	0x00000d4d
     c74:	00000b45 	.word	0x00000b45
     c78:	00000b45 	.word	0x00000b45
     c7c:	00000c95 	.word	0x00000c95
     c80:	00000b45 	.word	0x00000b45
     c84:	00000d49 	.word	0x00000d49
     c88:	00000b45 	.word	0x00000b45
     c8c:	00000b45 	.word	0x00000b45
     c90:	00000d49 	.word	0x00000d49
			if (precision >= 0) {
     c94:	f1b8 0f00 	cmp.w	r8, #0
			bps = (const char *)value->ptr;
     c98:	f8dd a028 	ldr.w	sl, [sp, #40]	; 0x28
			if (precision >= 0) {
     c9c:	db0a      	blt.n	cb4 <CONFIG_ISR_STACK_SIZE+0x4b4>
				len = strnlen(bps, precision);
     c9e:	4641      	mov	r1, r8
     ca0:	4650      	mov	r0, sl
     ca2:	f004 fbcf 	bl	5444 <strnlen>
		char sign = 0;
     ca6:	2600      	movs	r6, #0
			bpe = bps + len;
     ca8:	eb0a 0800 	add.w	r8, sl, r0
		if (bps == NULL) {
     cac:	f1ba 0f00 	cmp.w	sl, #0
     cb0:	d10c      	bne.n	ccc <CONFIG_ISR_STACK_SIZE+0x4cc>
     cb2:	e747      	b.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
				len = strlen(bps);
     cb4:	4650      	mov	r0, sl
     cb6:	f004 fbbe 	bl	5436 <strlen>
     cba:	e7f4      	b.n	ca6 <CONFIG_ISR_STACK_SIZE+0x4a6>
			break;
     cbc:	2600      	movs	r6, #0
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     cbe:	9b0a      	ldr	r3, [sp, #40]	; 0x28
			bps = buf;
     cc0:	f10d 0a10 	add.w	sl, sp, #16
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     cc4:	f88d 3010 	strb.w	r3, [sp, #16]
			bpe = buf + 1;
     cc8:	f10d 0811 	add.w	r8, sp, #17
		size_t nj_len = (bpe - bps);
     ccc:	eba8 030a 	sub.w	r3, r8, sl
		if (sign != 0) {
     cd0:	b106      	cbz	r6, cd4 <CONFIG_ISR_STACK_SIZE+0x4d4>
			nj_len += 1U;
     cd2:	3301      	adds	r3, #1
		if (conv->altform_0c) {
     cd4:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
     cd8:	06d0      	lsls	r0, r2, #27
     cda:	d568      	bpl.n	dae <CONFIG_ISR_STACK_SIZE+0x5ae>
			nj_len += 2U;
     cdc:	3302      	adds	r3, #2
		if (conv->pad_fp) {
     cde:	0652      	lsls	r2, r2, #25
		nj_len += conv->pad0_value;
     ce0:	990d      	ldr	r1, [sp, #52]	; 0x34
			nj_len += conv->pad0_pre_exp;
     ce2:	bf48      	it	mi
     ce4:	9a0e      	ldrmi	r2, [sp, #56]	; 0x38
		nj_len += conv->pad0_value;
     ce6:	440b      	add	r3, r1
			nj_len += conv->pad0_pre_exp;
     ce8:	bf48      	it	mi
     cea:	189b      	addmi	r3, r3, r2
		if (width > 0) {
     cec:	f1b9 0f00 	cmp.w	r9, #0
     cf0:	dd76      	ble.n	de0 <CONFIG_ISR_STACK_SIZE+0x5e0>
			if (!conv->flag_dash) {
     cf2:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
			width -= (int)nj_len;
     cf6:	eba9 0903 	sub.w	r9, r9, r3
			if (!conv->flag_dash) {
     cfa:	f3c2 0380 	ubfx	r3, r2, #2, #1
     cfe:	9303      	str	r3, [sp, #12]
     d00:	0753      	lsls	r3, r2, #29
     d02:	d46d      	bmi.n	de0 <CONFIG_ISR_STACK_SIZE+0x5e0>
				if (conv->flag_zero) {
     d04:	0650      	lsls	r0, r2, #25
     d06:	d561      	bpl.n	dcc <CONFIG_ISR_STACK_SIZE+0x5cc>
					if (sign != 0) {
     d08:	b146      	cbz	r6, d1c <CONFIG_ISR_STACK_SIZE+0x51c>
						OUTC(sign);
     d0a:	4659      	mov	r1, fp
     d0c:	4630      	mov	r0, r6
     d0e:	9b02      	ldr	r3, [sp, #8]
     d10:	4798      	blx	r3
     d12:	2800      	cmp	r0, #0
     d14:	db57      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
						sign = 0;
     d16:	9b03      	ldr	r3, [sp, #12]
						OUTC(sign);
     d18:	3501      	adds	r5, #1
						sign = 0;
     d1a:	461e      	mov	r6, r3
					pad = '0';
     d1c:	2330      	movs	r3, #48	; 0x30
     d1e:	e056      	b.n	dce <CONFIG_ISR_STACK_SIZE+0x5ce>
			if (conv->flag_plus) {
     d20:	071e      	lsls	r6, r3, #28
     d22:	d40f      	bmi.n	d44 <CONFIG_ISR_STACK_SIZE+0x544>
				sign = ' ';
     d24:	f013 0610 	ands.w	r6, r3, #16
     d28:	bf18      	it	ne
     d2a:	2620      	movne	r6, #32
			sint = value->sint;
     d2c:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
			if (sint < 0) {
     d30:	2b00      	cmp	r3, #0
     d32:	f6bf af5f 	bge.w	bf4 <CONFIG_ISR_STACK_SIZE+0x3f4>
				value->uint = (uint_value_type)-sint;
     d36:	4252      	negs	r2, r2
     d38:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
				sign = '-';
     d3c:	262d      	movs	r6, #45	; 0x2d
				value->uint = (uint_value_type)-sint;
     d3e:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
     d42:	e757      	b.n	bf4 <CONFIG_ISR_STACK_SIZE+0x3f4>
				sign = '+';
     d44:	262b      	movs	r6, #43	; 0x2b
     d46:	e7f1      	b.n	d2c <CONFIG_ISR_STACK_SIZE+0x52c>
		switch (conv->specifier) {
     d48:	2600      	movs	r6, #0
     d4a:	e753      	b.n	bf4 <CONFIG_ISR_STACK_SIZE+0x3f4>
			if (value->ptr != NULL) {
     d4c:	980a      	ldr	r0, [sp, #40]	; 0x28
     d4e:	b340      	cbz	r0, da2 <CONFIG_ISR_STACK_SIZE+0x5a2>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     d50:	f10d 0326 	add.w	r3, sp, #38	; 0x26
     d54:	9300      	str	r3, [sp, #0]
     d56:	2100      	movs	r1, #0
     d58:	ab04      	add	r3, sp, #16
     d5a:	aa0c      	add	r2, sp, #48	; 0x30
     d5c:	f004 fac9 	bl	52f2 <encode_uint>
				conv->altform_0c = true;
     d60:	f8bd 3032 	ldrh.w	r3, [sp, #50]	; 0x32
				bps = encode_uint((uintptr_t)value->ptr, conv,
     d64:	4682      	mov	sl, r0
				conv->altform_0c = true;
     d66:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     d6a:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     d6e:	f043 0310 	orr.w	r3, r3, #16
		char sign = 0;
     d72:	2600      	movs	r6, #0
				conv->altform_0c = true;
     d74:	f8ad 3032 	strh.w	r3, [sp, #50]	; 0x32
				goto prec_int_pad0;
     d78:	e746      	b.n	c08 <CONFIG_ISR_STACK_SIZE+0x408>
				store_count(conv, value->ptr, count);
     d7a:	9b0a      	ldr	r3, [sp, #40]	; 0x28
	switch ((enum length_mod_enum)conv->length_mod) {
     d7c:	2907      	cmp	r1, #7
     d7e:	f63f aee1 	bhi.w	b44 <CONFIG_ISR_STACK_SIZE+0x344>
     d82:	e8df f001 	tbb	[pc, r1]
     d86:	040c      	.short	0x040c
     d88:	08080c06 	.word	0x08080c06
     d8c:	0c0c      	.short	0x0c0c
		*(signed char *)dp = (signed char)count;
     d8e:	701d      	strb	r5, [r3, #0]
		break;
     d90:	e6d8      	b.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
		*(short *)dp = (short)count;
     d92:	801d      	strh	r5, [r3, #0]
		break;
     d94:	e6d6      	b.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
		*(intmax_t *)dp = (intmax_t)count;
     d96:	17ea      	asrs	r2, r5, #31
     d98:	e9c3 5200 	strd	r5, r2, [r3]
		break;
     d9c:	e6d2      	b.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     d9e:	601d      	str	r5, [r3, #0]
		break;
     da0:	e6d0      	b.n	b44 <CONFIG_ISR_STACK_SIZE+0x344>
			bps = "(nil)";
     da2:	f8df a0c8 	ldr.w	sl, [pc, #200]	; e6c <CONFIG_ISR_STACK_SIZE+0x66c>
     da6:	4606      	mov	r6, r0
			bpe = bps + 5;
     da8:	f10a 0805 	add.w	r8, sl, #5
     dac:	e78e      	b.n	ccc <CONFIG_ISR_STACK_SIZE+0x4cc>
		} else if (conv->altform_0) {
     dae:	0711      	lsls	r1, r2, #28
			nj_len += 1U;
     db0:	bf48      	it	mi
     db2:	3301      	addmi	r3, #1
     db4:	e793      	b.n	cde <CONFIG_ISR_STACK_SIZE+0x4de>
					OUTC(pad);
     db6:	4618      	mov	r0, r3
     db8:	9303      	str	r3, [sp, #12]
     dba:	4659      	mov	r1, fp
     dbc:	9b02      	ldr	r3, [sp, #8]
     dbe:	4798      	blx	r3
     dc0:	2800      	cmp	r0, #0
     dc2:	9b03      	ldr	r3, [sp, #12]
     dc4:	da04      	bge.n	dd0 <CONFIG_ISR_STACK_SIZE+0x5d0>
#undef OUTS
#undef OUTC
}
     dc6:	b011      	add	sp, #68	; 0x44
     dc8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
     dcc:	2320      	movs	r3, #32
     dce:	444d      	add	r5, r9
     dd0:	464a      	mov	r2, r9
				while (width-- > 0) {
     dd2:	2a00      	cmp	r2, #0
     dd4:	eba5 0109 	sub.w	r1, r5, r9
     dd8:	f109 39ff 	add.w	r9, r9, #4294967295
     ddc:	dceb      	bgt.n	db6 <CONFIG_ISR_STACK_SIZE+0x5b6>
     dde:	460d      	mov	r5, r1
		if (sign != 0) {
     de0:	b136      	cbz	r6, df0 <CONFIG_ISR_STACK_SIZE+0x5f0>
			OUTC(sign);
     de2:	4659      	mov	r1, fp
     de4:	4630      	mov	r0, r6
     de6:	9b02      	ldr	r3, [sp, #8]
     de8:	4798      	blx	r3
     dea:	2800      	cmp	r0, #0
     dec:	dbeb      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     dee:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
     df0:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     df4:	06d9      	lsls	r1, r3, #27
     df6:	d401      	bmi.n	dfc <CONFIG_ISR_STACK_SIZE+0x5fc>
     df8:	071a      	lsls	r2, r3, #28
     dfa:	d506      	bpl.n	e0a <CONFIG_ISR_STACK_SIZE+0x60a>
				OUTC('0');
     dfc:	4659      	mov	r1, fp
     dfe:	2030      	movs	r0, #48	; 0x30
     e00:	9b02      	ldr	r3, [sp, #8]
     e02:	4798      	blx	r3
     e04:	2800      	cmp	r0, #0
     e06:	dbde      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     e08:	3501      	adds	r5, #1
			if (conv->altform_0c) {
     e0a:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     e0e:	06db      	lsls	r3, r3, #27
     e10:	d507      	bpl.n	e22 <CONFIG_ISR_STACK_SIZE+0x622>
				OUTC(conv->specifier);
     e12:	4659      	mov	r1, fp
     e14:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
     e18:	9b02      	ldr	r3, [sp, #8]
     e1a:	4798      	blx	r3
     e1c:	2800      	cmp	r0, #0
     e1e:	dbd2      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     e20:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     e22:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     e24:	442e      	add	r6, r5
     e26:	1b73      	subs	r3, r6, r5
     e28:	2b00      	cmp	r3, #0
     e2a:	dc16      	bgt.n	e5a <CONFIG_ISR_STACK_SIZE+0x65a>
			OUTS(bps, bpe);
     e2c:	4643      	mov	r3, r8
     e2e:	4652      	mov	r2, sl
     e30:	4659      	mov	r1, fp
     e32:	9802      	ldr	r0, [sp, #8]
     e34:	f004 faa3 	bl	537e <outs>
     e38:	2800      	cmp	r0, #0
     e3a:	dbc4      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     e3c:	4405      	add	r5, r0
		while (width > 0) {
     e3e:	44a9      	add	r9, r5
     e40:	eba9 0305 	sub.w	r3, r9, r5
     e44:	2b00      	cmp	r3, #0
     e46:	f77f ae7d 	ble.w	b44 <CONFIG_ISR_STACK_SIZE+0x344>
			OUTC(' ');
     e4a:	4659      	mov	r1, fp
     e4c:	2020      	movs	r0, #32
     e4e:	9b02      	ldr	r3, [sp, #8]
     e50:	4798      	blx	r3
     e52:	2800      	cmp	r0, #0
     e54:	dbb7      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     e56:	3501      	adds	r5, #1
			--width;
     e58:	e7f2      	b.n	e40 <CONFIG_ISR_STACK_SIZE+0x640>
				OUTC('0');
     e5a:	4659      	mov	r1, fp
     e5c:	2030      	movs	r0, #48	; 0x30
     e5e:	9b02      	ldr	r3, [sp, #8]
     e60:	4798      	blx	r3
     e62:	2800      	cmp	r0, #0
     e64:	dbaf      	blt.n	dc6 <CONFIG_ISR_STACK_SIZE+0x5c6>
     e66:	3501      	adds	r5, #1
     e68:	e7dd      	b.n	e26 <CONFIG_ISR_STACK_SIZE+0x626>
     e6a:	bf00      	nop
     e6c:	00006f80 	.word	0x00006f80

00000e70 <sys_reboot>:
#include <sys/printk.h>

extern void sys_arch_reboot(int type);

FUNC_NORETURN void sys_reboot(int type)
{
     e70:	b508      	push	{r3, lr}
     e72:	f04f 0220 	mov.w	r2, #32
     e76:	f3ef 8311 	mrs	r3, BASEPRI
     e7a:	f382 8812 	msr	BASEPRI_MAX, r2
     e7e:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
	sys_clock_disable();

	sys_arch_reboot(type);
     e82:	f000 fced 	bl	1860 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
     e86:	4803      	ldr	r0, [pc, #12]	; (e94 <sys_reboot+0x24>)
     e88:	f004 f916 	bl	50b8 <printk>
 * @note In some architectures, before returning, the function unmasks interrupts
 * unconditionally.
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
     e8c:	f000 fa8a 	bl	13a4 <arch_cpu_idle>
     e90:	e7fc      	b.n	e8c <sys_reboot+0x1c>
     e92:	bf00      	nop
     e94:	00006f86 	.word	0x00006f86

00000e98 <nrf_gpio_pin_mcu_select.constprop.0>:

#if defined(GPIO_PIN_CNF_MCUSEL_Msk)
NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu)
{
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
     e98:	4b05      	ldr	r3, [pc, #20]	; (eb0 <nrf_gpio_pin_mcu_select.constprop.0+0x18>)
     e9a:	eb03 0080 	add.w	r0, r3, r0, lsl #2
     e9e:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
     ea2:	f023 43e0 	bic.w	r3, r3, #1879048192	; 0x70000000
    reg->PIN_CNF[pin_number] = cnf | (mcu << GPIO_PIN_CNF_MCUSEL_Pos);
     ea6:	f043 5340 	orr.w	r3, r3, #805306368	; 0x30000000
     eaa:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
}
     eae:	4770      	bx	lr
     eb0:	50842500 	.word	0x50842500

00000eb4 <nordicsemi_nrf53_init>:

#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
LOG_MODULE_REGISTER(soc);

static int nordicsemi_nrf53_init(const struct device *arg)
{
     eb4:	b510      	push	{r4, lr}
     eb6:	f04f 0320 	mov.w	r3, #32
     eba:	f3ef 8411 	mrs	r4, BASEPRI
     ebe:	f383 8812 	msr	BASEPRI_MAX, r3
     ec2:	f3bf 8f6f 	isb	sy

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_cache_enable(NRF_CACHE_Type * p_reg)
{
    p_reg->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
     ec6:	2201      	movs	r2, #1
     ec8:	4b0c      	ldr	r3, [pc, #48]	; (efc <nordicsemi_nrf53_init+0x48>)
}

NRF_STATIC_INLINE void nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS_Type *     p_reg,
                                                    nrf_oscillators_lfxo_cap_t cap)
{
    p_reg->XOSC32KI.INTCAP = (uint32_t)cap;
     eca:	490d      	ldr	r1, [pc, #52]	; (f00 <nordicsemi_nrf53_init+0x4c>)
     ecc:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
     ed0:	2302      	movs	r3, #2
#if !defined(CONFIG_BUILD_WITH_TFM)
	/* This can only be done from secure code.
	 * This is handled by the TF-M platform so we skip it when TF-M is
	 * enabled.
	 */
	nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
     ed2:	2000      	movs	r0, #0
     ed4:	f8c1 36d0 	str.w	r3, [r1, #1744]	; 0x6d0
     ed8:	f7ff ffde 	bl	e98 <nrf_gpio_pin_mcu_select.constprop.0>
	nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
     edc:	4610      	mov	r0, r2
     ede:	f7ff ffdb 	bl	e98 <nrf_gpio_pin_mcu_select.constprop.0>
NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable)
{
#if defined(REGULATORS_DCDCEN_DCDCEN_Msk)
    p_reg->DCDCEN = (enable ? REGULATORS_DCDCEN_DCDCEN_Msk : 0);
#else
    p_reg->VREGMAIN.DCDCEN = (enable ? REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk : 0);
     ee2:	f8c1 2704 	str.w	r2, [r1, #1796]	; 0x704
#endif

#if NRF_REGULATORS_HAS_DCDCEN_RADIO
NRF_STATIC_INLINE void nrf_regulators_dcdcen_radio_set(NRF_REGULATORS_Type * p_reg, bool enable)
{
    p_reg->VREGRADIO.DCDCEN = (enable) ? REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled :
     ee6:	f8c1 2904 	str.w	r2, [r1, #2308]	; 0x904
    p_reg->VREGH.DCDCEN = (enable) ? REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled :
     eea:	f8c1 2b00 	str.w	r2, [r1, #2816]	; 0xb00
	__asm__ volatile(
     eee:	f384 8811 	msr	BASEPRI, r4
     ef2:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
     ef6:	2000      	movs	r0, #0
     ef8:	bd10      	pop	{r4, pc}
     efa:	bf00      	nop
     efc:	50001000 	.word	0x50001000
     f00:	50004000 	.word	0x50004000

00000f04 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
     f04:	b148      	cbz	r0, f1a <arch_busy_wait+0x16>

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
     f06:	4b05      	ldr	r3, [pc, #20]	; (f1c <arch_busy_wait+0x18>)
     f08:	681a      	ldr	r2, [r3, #0]
     f0a:	4b05      	ldr	r3, [pc, #20]	; (f20 <arch_busy_wait+0x1c>)
     f0c:	fbb2 f2f3 	udiv	r2, r2, r3
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
     f10:	4b04      	ldr	r3, [pc, #16]	; (f24 <arch_busy_wait+0x20>)
    delay_cycles(cycles);
     f12:	4350      	muls	r0, r2
     f14:	f043 0301 	orr.w	r3, r3, #1
     f18:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
     f1a:	4770      	bx	lr
     f1c:	20000118 	.word	0x20000118
     f20:	000f4240 	.word	0x000f4240
     f24:	00006cb0 	.word	0x00006cb0

00000f28 <pm_state_set>:
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
	ARG_UNUSED(substate_id);

	switch (state) {
     f28:	2806      	cmp	r0, #6
     f2a:	d107      	bne.n	f3c <pm_state_set+0x14>
    p_reg->SYSTEMOFF = REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk;
     f2c:	2201      	movs	r2, #1
     f2e:	4b04      	ldr	r3, [pc, #16]	; (f40 <pm_state_set+0x18>)
     f30:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
     f34:	f3bf 8f4f 	dsb	sy
        __WFE();
     f38:	bf20      	wfe
    while (true)
     f3a:	e7fd      	b.n	f38 <pm_state_set+0x10>
		break;
	default:
		LOG_DBG("Unsupported power state %u", state);
		break;
	}
}
     f3c:	4770      	bx	lr
     f3e:	bf00      	nop
     f40:	50004000 	.word	0x50004000

00000f44 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
     f44:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
     f48:	4605      	mov	r5, r0
	__asm__ volatile(
     f4a:	f04f 0320 	mov.w	r3, #32
     f4e:	f3ef 8611 	mrs	r6, BASEPRI
     f52:	f383 8812 	msr	BASEPRI_MAX, r3
     f56:	f3bf 8f6f 	isb	sy
	return list->head;
     f5a:	4b0e      	ldr	r3, [pc, #56]	; (f94 <pm_state_notify+0x50>)
     f5c:	681c      	ldr	r4, [r3, #0]
	struct pm_notifier *notifier;
	k_spinlock_key_t pm_notifier_key;
	void (*callback)(enum pm_state state);

	pm_notifier_key = k_spin_lock(&pm_notifier_lock);
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     f5e:	b19c      	cbz	r4, f88 <pm_state_notify+0x44>
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_cpus_pm_state[_current_cpu->id].state);
     f60:	f04f 090c 	mov.w	r9, #12
     f64:	4f0c      	ldr	r7, [pc, #48]	; (f98 <pm_state_notify+0x54>)
     f66:	f8df 8034 	ldr.w	r8, [pc, #52]	; f9c <pm_state_notify+0x58>
			callback = notifier->state_exit;
     f6a:	e9d4 3201 	ldrd	r3, r2, [r4, #4]
     f6e:	2d00      	cmp	r5, #0
     f70:	bf08      	it	eq
     f72:	4613      	moveq	r3, r2
		if (callback) {
     f74:	b12b      	cbz	r3, f82 <pm_state_notify+0x3e>
			callback(z_cpus_pm_state[_current_cpu->id].state);
     f76:	f898 2014 	ldrb.w	r2, [r8, #20]
     f7a:	fb09 f202 	mul.w	r2, r9, r2
     f7e:	5cb8      	ldrb	r0, [r7, r2]
     f80:	4798      	blx	r3
	return node->next;
     f82:	6824      	ldr	r4, [r4, #0]
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     f84:	2c00      	cmp	r4, #0
     f86:	d1f0      	bne.n	f6a <pm_state_notify+0x26>
	__asm__ volatile(
     f88:	f386 8811 	msr	BASEPRI, r6
     f8c:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
     f90:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
     f94:	20000548 	.word	0x20000548
     f98:	20000550 	.word	0x20000550
     f9c:	20000ba0 	.word	0x20000ba0

00000fa0 <atomic_clear_bit.constprop.0>:
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 */
static inline void atomic_clear_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
     fa0:	2301      	movs	r3, #1

	(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
     fa2:	0942      	lsrs	r2, r0, #5
	atomic_val_t mask = ATOMIC_MASK(bit);
     fa4:	f000 001f 	and.w	r0, r0, #31
     fa8:	fa03 f000 	lsl.w	r0, r3, r0
	(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
     fac:	43c0      	mvns	r0, r0
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
     fae:	4b05      	ldr	r3, [pc, #20]	; (fc4 <atomic_clear_bit.constprop.0+0x24>)
     fb0:	eb03 0382 	add.w	r3, r3, r2, lsl #2
     fb4:	e8d3 2fef 	ldaex	r2, [r3]
     fb8:	4002      	ands	r2, r0
     fba:	e8c3 2fe1 	stlex	r1, r2, [r3]
     fbe:	2900      	cmp	r1, #0
     fc0:	d1f8      	bne.n	fb4 <atomic_clear_bit.constprop.0+0x14>
}
     fc2:	4770      	bx	lr
     fc4:	2000055c 	.word	0x2000055c

00000fc8 <pm_system_resume>:
	atomic_val_t mask = ATOMIC_MASK(bit);
     fc8:	2201      	movs	r2, #1

void pm_system_resume(void)
{
     fca:	b538      	push	{r3, r4, r5, lr}
	uint8_t id = _current_cpu->id;
     fcc:	4b17      	ldr	r3, [pc, #92]	; (102c <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x2c>)
     fce:	7d1c      	ldrb	r4, [r3, #20]
     fd0:	f004 031f 	and.w	r3, r4, #31
     fd4:	409a      	lsls	r2, r3
	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
     fd6:	43d0      	mvns	r0, r2
     fd8:	4b15      	ldr	r3, [pc, #84]	; (1030 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x30>)
     fda:	0961      	lsrs	r1, r4, #5
     fdc:	eb03 0381 	add.w	r3, r3, r1, lsl #2
     fe0:	e8d3 1fef 	ldaex	r1, [r3]
     fe4:	ea01 0500 	and.w	r5, r1, r0
     fe8:	e8c3 5fec 	stlex	ip, r5, [r3]
     fec:	f1bc 0f00 	cmp.w	ip, #0
     ff0:	d1f6      	bne.n	fe0 <pm_system_resume+0x18>
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
     ff2:	4211      	tst	r1, r2
     ff4:	d013      	beq.n	101e <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x1e>
	if (pm_state_exit_post_ops != NULL) {
     ff6:	4b0f      	ldr	r3, [pc, #60]	; (1034 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x34>)
     ff8:	4d0f      	ldr	r5, [pc, #60]	; (1038 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x38>)
     ffa:	b18b      	cbz	r3, 1020 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x20>
		pm_state_exit_post_ops(info->state, info->substate_id);
     ffc:	230c      	movs	r3, #12
     ffe:	4363      	muls	r3, r4
    1000:	18ea      	adds	r2, r5, r3
    1002:	7851      	ldrb	r1, [r2, #1]
    1004:	5ce8      	ldrb	r0, [r5, r3]
    1006:	f004 f9d1 	bl	53ac <pm_state_exit_post_ops>
		pm_exit_pos_ops(&z_cpus_pm_state[id]);
		pm_state_notify(false);
    100a:	2000      	movs	r0, #0
    100c:	f7ff ff9a 	bl	f44 <pm_state_notify>
		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE,
    1010:	230c      	movs	r3, #12
    1012:	435c      	muls	r4, r3
    1014:	2300      	movs	r3, #0
    1016:	192a      	adds	r2, r5, r4
    1018:	512b      	str	r3, [r5, r4]
    101a:	e9c2 3301 	strd	r3, r3, [r2, #4]
			0, 0};
	}
}
    101e:	bd38      	pop	{r3, r4, r5, pc}
    1020:	f383 8811 	msr	BASEPRI, r3
    1024:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    1028:	e7ef      	b.n	100a <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xa>
    102a:	bf00      	nop
    102c:	20000ba0 	.word	0x20000ba0
    1030:	20000560 	.word	0x20000560
    1034:	000053ad 	.word	0x000053ad
    1038:	20000550 	.word	0x20000550

0000103c <pm_system_suspend>:

	return ret;
}

bool pm_system_suspend(int32_t ticks)
{
    103c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	bool ret = true;
	uint8_t id = _current_cpu->id;
    1040:	4b2f      	ldr	r3, [pc, #188]	; (1100 <pm_system_suspend+0xc4>)
{
    1042:	4607      	mov	r7, r0
	uint8_t id = _current_cpu->id;
    1044:	7d1c      	ldrb	r4, [r3, #20]
	atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit));
    1046:	ea4f 1854 	mov.w	r8, r4, lsr #5
    104a:	ea4f 0888 	mov.w	r8, r8, lsl #2
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    104e:	4b2d      	ldr	r3, [pc, #180]	; (1104 <pm_system_suspend+0xc8>)
    1050:	4443      	add	r3, r8
    1052:	e8d3 3faf 	lda	r3, [r3]
	return (1 & (val >> (bit & (ATOMIC_BITS - 1)))) != 0;
    1056:	f004 091f 	and.w	r9, r4, #31
    105a:	fa43 f309 	asr.w	r3, r3, r9

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	if (!atomic_test_bit(z_cpus_pm_state_forced, id)) {
    105e:	f013 0f01 	tst.w	r3, #1
    1062:	4e29      	ldr	r6, [pc, #164]	; (1108 <pm_system_suspend+0xcc>)
    1064:	d10a      	bne.n	107c <pm_system_suspend+0x40>
		const struct pm_state_info *info;

		info = pm_policy_next_state(id, ticks);
    1066:	4601      	mov	r1, r0
    1068:	4620      	mov	r0, r4
    106a:	f000 f863 	bl	1134 <pm_policy_next_state>
		if (info != NULL) {
    106e:	b128      	cbz	r0, 107c <pm_system_suspend+0x40>
			z_cpus_pm_state[id] = *info;
    1070:	c807      	ldmia	r0, {r0, r1, r2}
    1072:	230c      	movs	r3, #12
    1074:	fb03 6304 	mla	r3, r3, r4, r6
    1078:	e883 0007 	stmia.w	r3, {r0, r1, r2}
		}
	}

	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
    107c:	230c      	movs	r3, #12
    107e:	4363      	muls	r3, r4
    1080:	5cf5      	ldrb	r5, [r6, r3]
    1082:	18f2      	adds	r2, r6, r3
    1084:	b92d      	cbnz	r5, 1092 <pm_system_suspend+0x56>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);
		ret = false;
		atomic_clear_bit(z_cpus_pm_state_forced, id);
    1086:	4620      	mov	r0, r4
    1088:	f7ff ff8a 	bl	fa0 <atomic_clear_bit.constprop.0>
		ret = false;
    108c:	4628      	mov	r0, r5
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);

end:
	return ret;
}
    108e:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	if (ticks != K_TICKS_FOREVER) {
    1092:	1c7b      	adds	r3, r7, #1
    1094:	d00f      	beq.n	10b6 <pm_system_suspend+0x7a>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    1096:	f44f 4500 	mov.w	r5, #32768	; 0x8000
    109a:	2100      	movs	r1, #0
    109c:	f8d2 c008 	ldr.w	ip, [r2, #8]
    10a0:	481a      	ldr	r0, [pc, #104]	; (110c <pm_system_suspend+0xd0>)
    10a2:	2300      	movs	r3, #0
    10a4:	fbec 0105 	umlal	r0, r1, ip, r5
    10a8:	4a19      	ldr	r2, [pc, #100]	; (1110 <pm_system_suspend+0xd4>)
    10aa:	f7ff f853 	bl	154 <__aeabi_uldivmod>
		z_set_timeout_expiry(ticks -
    10ae:	2101      	movs	r1, #1
    10b0:	1a38      	subs	r0, r7, r0
    10b2:	f005 fc1f 	bl	68f4 <z_set_timeout_expiry>
	k_sched_lock();
    10b6:	f003 f989 	bl	43cc <k_sched_lock>
	pm_state_notify(true);
    10ba:	2001      	movs	r0, #1
    10bc:	f7ff ff42 	bl	f44 <pm_state_notify>
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
    10c0:	2301      	movs	r3, #1
    10c2:	fa03 f909 	lsl.w	r9, r3, r9
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    10c6:	4b13      	ldr	r3, [pc, #76]	; (1114 <pm_system_suspend+0xd8>)
    10c8:	4498      	add	r8, r3
    10ca:	e8d8 3fef 	ldaex	r3, [r8]
    10ce:	ea43 0309 	orr.w	r3, r3, r9
    10d2:	e8c8 3fe2 	stlex	r2, r3, [r8]
    10d6:	2a00      	cmp	r2, #0
    10d8:	d1f7      	bne.n	10ca <pm_system_suspend+0x8e>
	if (pm_state_set != NULL) {
    10da:	4b0f      	ldr	r3, [pc, #60]	; (1118 <pm_system_suspend+0xdc>)
    10dc:	b133      	cbz	r3, 10ec <pm_system_suspend+0xb0>
		pm_state_set(info->state, info->substate_id);
    10de:	230c      	movs	r3, #12
    10e0:	4363      	muls	r3, r4
    10e2:	18f2      	adds	r2, r6, r3
    10e4:	7851      	ldrb	r1, [r2, #1]
    10e6:	5cf0      	ldrb	r0, [r6, r3]
    10e8:	f7ff ff1e 	bl	f28 <pm_state_set>
	pm_system_resume();
    10ec:	f7ff ff6c 	bl	fc8 <pm_system_resume>
	atomic_clear_bit(z_cpus_pm_state_forced, id);
    10f0:	4620      	mov	r0, r4
    10f2:	f7ff ff55 	bl	fa0 <atomic_clear_bit.constprop.0>
	k_sched_unlock();
    10f6:	f003 fb39 	bl	476c <k_sched_unlock>
	bool ret = true;
    10fa:	2001      	movs	r0, #1
    10fc:	e7c7      	b.n	108e <pm_system_suspend+0x52>
    10fe:	bf00      	nop
    1100:	20000ba0 	.word	0x20000ba0
    1104:	2000055c 	.word	0x2000055c
    1108:	20000550 	.word	0x20000550
    110c:	000f423f 	.word	0x000f423f
    1110:	000f4240 	.word	0x000f4240
    1114:	20000560 	.word	0x20000560
    1118:	00000f29 	.word	0x00000f29

0000111c <pm_policy_state_lock_is_active>:
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    111c:	4b04      	ldr	r3, [pc, #16]	; (1130 <pm_policy_state_lock_is_active+0x14>)
    111e:	eb03 0080 	add.w	r0, r3, r0, lsl #2
    1122:	e8d0 0faf 	lda	r0, [r0]
}

bool pm_policy_state_lock_is_active(enum pm_state state)
{
	return (atomic_get(&state_lock_cnt[state]) != 0);
}
    1126:	3800      	subs	r0, #0
    1128:	bf18      	it	ne
    112a:	2001      	movne	r0, #1
    112c:	4770      	bx	lr
    112e:	bf00      	nop
    1130:	20000564 	.word	0x20000564

00001134 <pm_policy_next_state>:
{
    1134:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1138:	b085      	sub	sp, #20
    113a:	460f      	mov	r7, r1
	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
    113c:	a903      	add	r1, sp, #12
    113e:	f000 f847 	bl	11d0 <pm_state_cpu_get_all>
    1142:	f04f 0b00 	mov.w	fp, #0
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    1146:	1e44      	subs	r4, r0, #1
    1148:	f8df 8078 	ldr.w	r8, [pc, #120]	; 11c4 <pm_policy_next_state+0x90>
    114c:	f8df a078 	ldr.w	sl, [pc, #120]	; 11c8 <pm_policy_next_state+0x94>
    1150:	b224      	sxth	r4, r4
    1152:	1c63      	adds	r3, r4, #1
    1154:	d104      	bne.n	1160 <pm_policy_next_state+0x2c>
	return NULL;
    1156:	2600      	movs	r6, #0
}
    1158:	4630      	mov	r0, r6
    115a:	b005      	add	sp, #20
    115c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		const struct pm_state_info *state = &cpu_states[i];
    1160:	9a03      	ldr	r2, [sp, #12]
    1162:	eb04 0344 	add.w	r3, r4, r4, lsl #1
		if (pm_policy_state_lock_is_active(state->state)) {
    1166:	f812 0023 	ldrb.w	r0, [r2, r3, lsl #2]
		const struct pm_state_info *state = &cpu_states[i];
    116a:	eb02 0683 	add.w	r6, r2, r3, lsl #2
		if (pm_policy_state_lock_is_active(state->state)) {
    116e:	f7ff ffd5 	bl	111c <pm_policy_state_lock_is_active>
    1172:	4605      	mov	r5, r0
    1174:	bb10      	cbnz	r0, 11bc <pm_policy_next_state+0x88>
    1176:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    117a:	46c4      	mov	ip, r8
    117c:	4629      	mov	r1, r5
    117e:	6870      	ldr	r0, [r6, #4]
    1180:	4652      	mov	r2, sl
    1182:	fbe0 c109 	umlal	ip, r1, r0, r9
    1186:	465b      	mov	r3, fp
    1188:	4660      	mov	r0, ip
    118a:	f7fe ffe3 	bl	154 <__aeabi_uldivmod>
    118e:	46c4      	mov	ip, r8
    1190:	4629      	mov	r1, r5
    1192:	9001      	str	r0, [sp, #4]
    1194:	68b0      	ldr	r0, [r6, #8]
    1196:	465b      	mov	r3, fp
    1198:	fbe0 c109 	umlal	ip, r1, r0, r9
    119c:	4652      	mov	r2, sl
    119e:	4660      	mov	r0, ip
    11a0:	f7fe ffd8 	bl	154 <__aeabi_uldivmod>
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    11a4:	4b09      	ldr	r3, [pc, #36]	; (11cc <pm_policy_next_state+0x98>)
    11a6:	681b      	ldr	r3, [r3, #0]
    11a8:	1c59      	adds	r1, r3, #1
    11aa:	d001      	beq.n	11b0 <pm_policy_next_state+0x7c>
    11ac:	4283      	cmp	r3, r0
    11ae:	d905      	bls.n	11bc <pm_policy_next_state+0x88>
		if ((ticks == K_TICKS_FOREVER) ||
    11b0:	1c7a      	adds	r2, r7, #1
    11b2:	d0d1      	beq.n	1158 <pm_policy_next_state+0x24>
		    (ticks >= (min_residency + exit_latency))) {
    11b4:	9b01      	ldr	r3, [sp, #4]
    11b6:	4418      	add	r0, r3
		if ((ticks == K_TICKS_FOREVER) ||
    11b8:	42b8      	cmp	r0, r7
    11ba:	d9cd      	bls.n	1158 <pm_policy_next_state+0x24>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    11bc:	3c01      	subs	r4, #1
    11be:	b224      	sxth	r4, r4
    11c0:	e7c7      	b.n	1152 <pm_policy_next_state+0x1e>
    11c2:	bf00      	nop
    11c4:	000f423f 	.word	0x000f423f
    11c8:	000f4240 	.word	0x000f4240
    11cc:	200000dc 	.word	0x200000dc

000011d0 <pm_state_cpu_get_all>:
	DT_FOREACH_CHILD(DT_PATH(cpus), NUM_CPU_STATES)
};

uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
{
	if (cpu >= ARRAY_SIZE(cpus_states)) {
    11d0:	b908      	cbnz	r0, 11d6 <pm_state_cpu_get_all+0x6>
		return 0;
	}

	*states = cpus_states[cpu];
    11d2:	4b02      	ldr	r3, [pc, #8]	; (11dc <pm_state_cpu_get_all+0xc>)
    11d4:	600b      	str	r3, [r1, #0]

	return states_per_cpu[cpu];
}
    11d6:	2000      	movs	r0, #0
    11d8:	4770      	bx	lr
    11da:	bf00      	nop
    11dc:	00006cb8 	.word	0x00006cb8

000011e0 <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    11e0:	4801      	ldr	r0, [pc, #4]	; (11e8 <nrf_cc3xx_platform_abort_init+0x8>)
    11e2:	f003 be1f 	b.w	4e24 <nrf_cc3xx_platform_set_abort>
    11e6:	bf00      	nop
    11e8:	00006cb8 	.word	0x00006cb8

000011ec <mutex_free_platform>:
}


/** @brief Static function to free a mutex
 */
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    11ec:	b510      	push	{r4, lr}
    /* Ensure that the mutex is valid (not NULL) */
    if (mutex == NULL) {
    11ee:	4604      	mov	r4, r0
    11f0:	b918      	cbnz	r0, 11fa <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    11f2:	4b0d      	ldr	r3, [pc, #52]	; (1228 <mutex_free_platform+0x3c>)
    11f4:	480d      	ldr	r0, [pc, #52]	; (122c <mutex_free_platform+0x40>)
    11f6:	685b      	ldr	r3, [r3, #4]
    11f8:	4798      	blx	r3
            "mutex_init called with NULL parameter");
    }

    /* Check if we are freeing a mutex that is atomic */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    11fa:	6861      	ldr	r1, [r4, #4]
    11fc:	2908      	cmp	r1, #8
    11fe:	d00d      	beq.n	121c <mutex_free_platform+0x30>
        /*Nothing to free*/
        return;
    }

    /* Check if we are freeing a mutex that isn't initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1200:	f031 0304 	bics.w	r3, r1, #4
    1204:	d00a      	beq.n	121c <mutex_free_platform+0x30>
        /*Nothing to free*/
        return;
    }

    /* Check if the mutex was allocated or being statically defined */
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    1206:	f011 0102 	ands.w	r1, r1, #2
    120a:	d008      	beq.n	121e <mutex_free_platform+0x32>
        k_mem_slab_free(&mutex_slab, &mutex->mutex);
    120c:	4621      	mov	r1, r4
    120e:	4808      	ldr	r0, [pc, #32]	; (1230 <mutex_free_platform+0x44>)
    1210:	f005 fa3e 	bl	6690 <k_mem_slab_free>
        mutex->mutex = NULL;
    1214:	2300      	movs	r3, #0
    1216:	6023      	str	r3, [r4, #0]
    else {
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    }

    /* Reset the mutex to invalid state */
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    1218:	2300      	movs	r3, #0
    121a:	6063      	str	r3, [r4, #4]
}
    121c:	bd10      	pop	{r4, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    121e:	2214      	movs	r2, #20
    1220:	6820      	ldr	r0, [r4, #0]
    1222:	f004 f92f 	bl	5484 <memset>
    1226:	e7f7      	b.n	1218 <mutex_free_platform+0x2c>
    1228:	200001a4 	.word	0x200001a4
    122c:	00006faf 	.word	0x00006faf
    1230:	20000580 	.word	0x20000580

00001234 <mutex_lock_platform>:


/** @brief Static function to lock a mutex
 */
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1234:	b508      	push	{r3, lr}
    int ret;
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1236:	b340      	cbz	r0, 128a <mutex_lock_platform+0x56>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags) {
    1238:	6843      	ldr	r3, [r0, #4]
    123a:	2b04      	cmp	r3, #4
    123c:	d00b      	beq.n	1256 <mutex_lock_platform+0x22>
    123e:	2b08      	cmp	r3, #8
    1240:	d016      	beq.n	1270 <mutex_lock_platform+0x3c>

#endif /* defined(NRF5340_XXAA_APPLICATION) */

    default:
        /* Ensure that the mutex has been initialized */
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1242:	b303      	cbz	r3, 1286 <mutex_lock_platform+0x52>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
        }

        p_mutex = (struct k_mutex *)mutex->mutex;
    1244:	6800      	ldr	r0, [r0, #0]
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_MUTEX_LOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_lock(mutex, timeout);
    1246:	f04f 32ff 	mov.w	r2, #4294967295
    124a:	f04f 33ff 	mov.w	r3, #4294967295
    124e:	f002 ff63 	bl	4118 <z_impl_k_mutex_lock>

        ret = k_mutex_lock(p_mutex, K_FOREVER);
        if (ret == 0) {
    1252:	b158      	cbz	r0, 126c <mutex_lock_platform+0x38>
    1254:	e015      	b.n	1282 <mutex_lock_platform+0x4e>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    1256:	2201      	movs	r2, #1
    1258:	6803      	ldr	r3, [r0, #0]
    125a:	e8d3 1fef 	ldaex	r1, [r3]
    125e:	2900      	cmp	r1, #0
    1260:	d103      	bne.n	126a <mutex_lock_platform+0x36>
    1262:	e8c3 2fe0 	stlex	r0, r2, [r3]
    1266:	2800      	cmp	r0, #0
    1268:	d1f7      	bne.n	125a <mutex_lock_platform+0x26>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    126a:	d10a      	bne.n	1282 <mutex_lock_platform+0x4e>
    126c:	2000      	movs	r0, #0
            return NRF_CC3XX_PLATFORM_SUCCESS;
        } else {
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
        }
    }
}
    126e:	bd08      	pop	{r3, pc}
        return nrf_mutex_lock(NRF_MUTEX, *((uint8_t *)mutex->mutex)) ?
    1270:	6803      	ldr	r3, [r0, #0]

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_mutex_lock(NRF_MUTEX_Type * p_reg, uint8_t mutex)
{
    return (p_reg->MUTEX[mutex] == MUTEX_MUTEX_MUTEX_Unlocked);
    1272:	4a07      	ldr	r2, [pc, #28]	; (1290 <mutex_lock_platform+0x5c>)
    1274:	781b      	ldrb	r3, [r3, #0]
    1276:	f503 7380 	add.w	r3, r3, #256	; 0x100
    127a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
                       NRF_CC3XX_PLATFORM_SUCCESS :
    127e:	2b00      	cmp	r3, #0
    1280:	d0f4      	beq.n	126c <mutex_lock_platform+0x38>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1282:	4804      	ldr	r0, [pc, #16]	; (1294 <mutex_lock_platform+0x60>)
    1284:	e7f3      	b.n	126e <mutex_lock_platform+0x3a>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1286:	4804      	ldr	r0, [pc, #16]	; (1298 <mutex_lock_platform+0x64>)
    1288:	e7f1      	b.n	126e <mutex_lock_platform+0x3a>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    128a:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    128e:	e7ee      	b.n	126e <mutex_lock_platform+0x3a>
    1290:	50030000 	.word	0x50030000
    1294:	ffff8fe9 	.word	0xffff8fe9
    1298:	ffff8fea 	.word	0xffff8fea

0000129c <mutex_unlock_platform>:

/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    129c:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    129e:	b308      	cbz	r0, 12e4 <mutex_unlock_platform+0x48>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags)
    12a0:	6843      	ldr	r3, [r0, #4]
    12a2:	2b04      	cmp	r3, #4
    12a4:	d007      	beq.n	12b6 <mutex_unlock_platform+0x1a>
    12a6:	2b08      	cmp	r3, #8
    12a8:	d013      	beq.n	12d2 <mutex_unlock_platform+0x36>

#endif /* defined(NRF5340_XXAA_APPLICATION) */

    default:
        /* Ensure that the mutex has been initialized */
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    12aa:	b1f3      	cbz	r3, 12ea <mutex_unlock_platform+0x4e>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
        }

        p_mutex = (struct k_mutex *)mutex->mutex;
    12ac:	6800      	ldr	r0, [r0, #0]
		union { uintptr_t x; struct k_mutex * val; } parm0 = { .val = mutex };
		return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_MUTEX_UNLOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_unlock(mutex);
    12ae:	f002 ffab 	bl	4208 <z_impl_k_mutex_unlock>

        k_mutex_unlock(p_mutex);
        return NRF_CC3XX_PLATFORM_SUCCESS;
    12b2:	2000      	movs	r0, #0
    12b4:	e00c      	b.n	12d0 <mutex_unlock_platform+0x34>
    12b6:	2200      	movs	r2, #0
    12b8:	6803      	ldr	r3, [r0, #0]
    12ba:	e8d3 1fef 	ldaex	r1, [r3]
    12be:	2901      	cmp	r1, #1
    12c0:	d103      	bne.n	12ca <mutex_unlock_platform+0x2e>
    12c2:	e8c3 2fe0 	stlex	r0, r2, [r3]
    12c6:	2800      	cmp	r0, #0
    12c8:	d1f7      	bne.n	12ba <mutex_unlock_platform+0x1e>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    12ca:	4809      	ldr	r0, [pc, #36]	; (12f0 <mutex_unlock_platform+0x54>)
    12cc:	bf08      	it	eq
    12ce:	4610      	moveq	r0, r2
    }
}
    12d0:	bd08      	pop	{r3, pc}
        nrf_mutex_unlock(NRF_MUTEX, *((uint8_t *)mutex->mutex));
    12d2:	6803      	ldr	r3, [r0, #0]
}

NRF_STATIC_INLINE void nrf_mutex_unlock(NRF_MUTEX_Type * p_reg, uint8_t mutex)
{
    p_reg->MUTEX[mutex] = MUTEX_MUTEX_MUTEX_Unlocked;
    12d4:	2000      	movs	r0, #0
    12d6:	781b      	ldrb	r3, [r3, #0]
    12d8:	4a06      	ldr	r2, [pc, #24]	; (12f4 <mutex_unlock_platform+0x58>)
    12da:	f503 7380 	add.w	r3, r3, #256	; 0x100
    12de:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
        return NRF_CC3XX_PLATFORM_SUCCESS;
    12e2:	e7f5      	b.n	12d0 <mutex_unlock_platform+0x34>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    12e4:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    12e8:	e7f2      	b.n	12d0 <mutex_unlock_platform+0x34>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    12ea:	4803      	ldr	r0, [pc, #12]	; (12f8 <mutex_unlock_platform+0x5c>)
    12ec:	e7f0      	b.n	12d0 <mutex_unlock_platform+0x34>
    12ee:	bf00      	nop
    12f0:	ffff8fe9 	.word	0xffff8fe9
    12f4:	50030000 	.word	0x50030000
    12f8:	ffff8fea 	.word	0xffff8fea

000012fc <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    12fc:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    12fe:	4604      	mov	r4, r0
    1300:	b918      	cbnz	r0, 130a <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    1302:	4b16      	ldr	r3, [pc, #88]	; (135c <mutex_init_platform+0x60>)
    1304:	4816      	ldr	r0, [pc, #88]	; (1360 <mutex_init_platform+0x64>)
    1306:	685b      	ldr	r3, [r3, #4]
    1308:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    130a:	6863      	ldr	r3, [r4, #4]
    130c:	2b04      	cmp	r3, #4
    130e:	d023      	beq.n	1358 <mutex_init_platform+0x5c>
    1310:	2b08      	cmp	r3, #8
    1312:	d021      	beq.n	1358 <mutex_init_platform+0x5c>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID &&
    1314:	b9cb      	cbnz	r3, 134a <mutex_init_platform+0x4e>
    1316:	6823      	ldr	r3, [r4, #0]
    1318:	b9bb      	cbnz	r3, 134a <mutex_init_platform+0x4e>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    131a:	f04f 32ff 	mov.w	r2, #4294967295
    131e:	f04f 33ff 	mov.w	r3, #4294967295
    1322:	4621      	mov	r1, r4
    1324:	480f      	ldr	r0, [pc, #60]	; (1364 <mutex_init_platform+0x68>)
    1326:	f002 fe21 	bl	3f6c <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    132a:	b908      	cbnz	r0, 1330 <mutex_init_platform+0x34>
    132c:	6823      	ldr	r3, [r4, #0]
    132e:	b91b      	cbnz	r3, 1338 <mutex_init_platform+0x3c>
            platform_abort_apis.abort_fn(
    1330:	4b0a      	ldr	r3, [pc, #40]	; (135c <mutex_init_platform+0x60>)
    1332:	480d      	ldr	r0, [pc, #52]	; (1368 <mutex_init_platform+0x6c>)
    1334:	685b      	ldr	r3, [r3, #4]
    1336:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1338:	2214      	movs	r2, #20
    133a:	2100      	movs	r1, #0
    133c:	6820      	ldr	r0, [r4, #0]
    133e:	f004 f8a1 	bl	5484 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    1342:	6863      	ldr	r3, [r4, #4]
    1344:	f043 0302 	orr.w	r3, r3, #2
    1348:	6063      	str	r3, [r4, #4]
    p_mutex = (struct k_mutex *)mutex->mutex;
    134a:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    134c:	f005 f9de 	bl	670c <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    1350:	6863      	ldr	r3, [r4, #4]
    1352:	f043 0301 	orr.w	r3, r3, #1
    1356:	6063      	str	r3, [r4, #4]
}
    1358:	bd10      	pop	{r4, pc}
    135a:	bf00      	nop
    135c:	200001a4 	.word	0x200001a4
    1360:	00006faf 	.word	0x00006faf
    1364:	20000580 	.word	0x20000580
    1368:	00006fd5 	.word	0x00006fd5

0000136c <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    136c:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    136e:	4906      	ldr	r1, [pc, #24]	; (1388 <nrf_cc3xx_platform_mutex_init+0x1c>)
    1370:	2340      	movs	r3, #64	; 0x40
    1372:	2214      	movs	r2, #20
    1374:	4805      	ldr	r0, [pc, #20]	; (138c <nrf_cc3xx_platform_mutex_init+0x20>)
    1376:	f005 f970 	bl	665a <k_mem_slab_init>
                mutex_slab_buffer,
                sizeof(struct k_mutex),
                NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    137a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    137e:	4904      	ldr	r1, [pc, #16]	; (1390 <nrf_cc3xx_platform_mutex_init+0x24>)
    1380:	4804      	ldr	r0, [pc, #16]	; (1394 <nrf_cc3xx_platform_mutex_init+0x28>)
    1382:	f003 bdb1 	b.w	4ee8 <nrf_cc3xx_platform_set_mutexes>
    1386:	bf00      	nop
    1388:	2000059c 	.word	0x2000059c
    138c:	20000580 	.word	0x20000580
    1390:	00006cd0 	.word	0x00006cd0
    1394:	00006cc0 	.word	0x00006cc0

00001398 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1398:	4901      	ldr	r1, [pc, #4]	; (13a0 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    139a:	2210      	movs	r2, #16
	str	r2, [r1]
    139c:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    139e:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    13a0:	e000ed10 	.word	0xe000ed10

000013a4 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    13a4:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    13a6:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    13a8:	f380 8811 	msr	BASEPRI, r0
	isb
    13ac:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    13b0:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    13b4:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    13b6:	b662      	cpsie	i
	isb
    13b8:	f3bf 8f6f 	isb	sy

	bx	lr
    13bc:	4770      	bx	lr
    13be:	bf00      	nop

000013c0 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    13c0:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    13c2:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    13c4:	f381 8811 	msr	BASEPRI, r1

	wfe
    13c8:	bf20      	wfe

	msr	BASEPRI, r0
    13ca:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    13ce:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    13d0:	4770      	bx	lr
    13d2:	bf00      	nop

000013d4 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    13d4:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    13d6:	2b00      	cmp	r3, #0
    13d8:	db08      	blt.n	13ec <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    13da:	2201      	movs	r2, #1
    13dc:	f000 001f 	and.w	r0, r0, #31
    13e0:	fa02 f000 	lsl.w	r0, r2, r0
    13e4:	4a02      	ldr	r2, [pc, #8]	; (13f0 <arch_irq_enable+0x1c>)
    13e6:	095b      	lsrs	r3, r3, #5
    13e8:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    13ec:	4770      	bx	lr
    13ee:	bf00      	nop
    13f0:	e000e100 	.word	0xe000e100

000013f4 <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
    13f4:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    13f6:	2b00      	cmp	r3, #0
    13f8:	db0d      	blt.n	1416 <arch_irq_disable+0x22>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    13fa:	2201      	movs	r2, #1
    13fc:	f000 001f 	and.w	r0, r0, #31
    1400:	fa02 f000 	lsl.w	r0, r2, r0
    1404:	095b      	lsrs	r3, r3, #5
    1406:	4a04      	ldr	r2, [pc, #16]	; (1418 <arch_irq_disable+0x24>)
    1408:	3320      	adds	r3, #32
    140a:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
    140e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1412:	f3bf 8f6f 	isb	sy
}
    1416:	4770      	bx	lr
    1418:	e000e100 	.word	0xe000e100

0000141c <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    141c:	4b05      	ldr	r3, [pc, #20]	; (1434 <arch_irq_is_enabled+0x18>)
    141e:	0942      	lsrs	r2, r0, #5
    1420:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1424:	2301      	movs	r3, #1
    1426:	f000 001f 	and.w	r0, r0, #31
    142a:	fa03 f000 	lsl.w	r0, r3, r0
}
    142e:	4010      	ands	r0, r2
    1430:	4770      	bx	lr
    1432:	bf00      	nop
    1434:	e000e100 	.word	0xe000e100

00001438 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1438:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    143a:	2b00      	cmp	r3, #0
		prio += _IRQ_PRIO_OFFSET;
    143c:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1440:	bfac      	ite	ge
    1442:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1446:	4b06      	ldrlt	r3, [pc, #24]	; (1460 <z_arm_irq_priority_set+0x28>)
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1448:	ea4f 1141 	mov.w	r1, r1, lsl #5
    144c:	b2c9      	uxtb	r1, r1
    144e:	bfab      	itete	ge
    1450:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1454:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1458:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    145c:	5419      	strblt	r1, [r3, r0]
}
    145e:	4770      	bx	lr
    1460:	e000ed14 	.word	0xe000ed14

00001464 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1464:	bf30      	wfi
    b z_SysNmiOnReset
    1466:	f7ff bffd 	b.w	1464 <z_SysNmiOnReset>
    146a:	bf00      	nop

0000146c <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    146c:	4a0b      	ldr	r2, [pc, #44]	; (149c <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    146e:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1470:	4b0b      	ldr	r3, [pc, #44]	; (14a0 <z_arm_prep_c+0x34>)
    1472:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1476:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    1478:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    147c:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1480:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1484:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1488:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    148c:	f002 fca2 	bl	3dd4 <z_bss_zero>
	z_data_copy();
    1490:	f003 fa8e 	bl	49b0 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1494:	f000 f9a8 	bl	17e8 <z_arm_interrupt_init>
	z_cstart();
    1498:	f002 fcdc 	bl	3e54 <z_cstart>
    149c:	00000000 	.word	0x00000000
    14a0:	e000ed00 	.word	0xe000ed00

000014a4 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    14a4:	4a09      	ldr	r2, [pc, #36]	; (14cc <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    14a6:	490a      	ldr	r1, [pc, #40]	; (14d0 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    14a8:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    14aa:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    14ac:	6758      	str	r0, [r3, #116]	; 0x74
	_current->arch.swap_return_value = _k_neg_eagain;
    14ae:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    14b0:	4908      	ldr	r1, [pc, #32]	; (14d4 <arch_swap+0x30>)
    14b2:	684b      	ldr	r3, [r1, #4]
    14b4:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    14b8:	604b      	str	r3, [r1, #4]
	__asm__ volatile(
    14ba:	2300      	movs	r3, #0
    14bc:	f383 8811 	msr	BASEPRI, r3
    14c0:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    14c4:	6893      	ldr	r3, [r2, #8]
}
    14c6:	6f98      	ldr	r0, [r3, #120]	; 0x78
    14c8:	4770      	bx	lr
    14ca:	bf00      	nop
    14cc:	20000ba0 	.word	0x20000ba0
    14d0:	00006ec4 	.word	0x00006ec4
    14d4:	e000ed00 	.word	0xe000ed00

000014d8 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    14d8:	4913      	ldr	r1, [pc, #76]	; (1528 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    14da:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    14dc:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    14e0:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    14e2:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    14e6:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    14ea:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    14ec:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    14f0:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    14f4:	4f0d      	ldr	r7, [pc, #52]	; (152c <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    14f6:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    14fa:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    14fc:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    14fe:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    1500:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    1502:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    1504:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    1506:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    150a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    150e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    1512:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    1516:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    151a:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    151c:	f003 ff61 	bl	53e2 <configure_builtin_stack_guard>
    pop {r2, lr}
    1520:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    1524:	4770      	bx	lr
    1526:	0000      	.short	0x0000
    ldr r1, =_kernel
    1528:	20000ba0 	.word	0x20000ba0
    ldr v4, =_SCS_ICSR
    152c:	e000ed04 	.word	0xe000ed04

00001530 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    1530:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1534:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1536:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    153a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    153e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1540:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1544:	2902      	cmp	r1, #2
    beq _oops
    1546:	d0ff      	beq.n	1548 <_oops>

00001548 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1548:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    154a:	f003 ff3b 	bl	53c4 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    154e:	bd01      	pop	{r0, pc}

00001550 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    1550:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    1554:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    1556:	490b      	ldr	r1, [pc, #44]	; (1584 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    1558:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    155c:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    155e:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    1562:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1566:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    1568:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    156c:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    1570:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    1574:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    1578:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    157a:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    157c:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    157e:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1580:	4770      	bx	lr
    1582:	bf00      	nop
    1584:	000052df 	.word	0x000052df

00001588 <arch_switch_to_main_thread>:
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    1588:	4b08      	ldr	r3, [pc, #32]	; (15ac <arch_switch_to_main_thread+0x24>)
    158a:	6098      	str	r0, [r3, #8]
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure PSPLIM is RAZ/WI
  (void)ProcStackPtrLimit;
#else
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    158c:	6e43      	ldr	r3, [r0, #100]	; 0x64
    158e:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    1592:	4610      	mov	r0, r2
    1594:	f381 8809 	msr	PSP, r1
    1598:	2100      	movs	r1, #0
    159a:	b663      	cpsie	if
    159c:	f381 8811 	msr	BASEPRI, r1
    15a0:	f3bf 8f6f 	isb	sy
    15a4:	2200      	movs	r2, #0
    15a6:	2300      	movs	r3, #0
    15a8:	f003 fe99 	bl	52de <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    15ac:	20000ba0 	.word	0x20000ba0

000015b0 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    15b0:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    15b2:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    15b4:	4a0b      	ldr	r2, [pc, #44]	; (15e4 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    15b6:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    15b8:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    15ba:	bf1e      	ittt	ne
	movne	r1, #0
    15bc:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    15be:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    15c0:	f005 f895 	blne	66ee <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    15c4:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    15c6:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    15ca:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    15ce:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    15d2:	4905      	ldr	r1, [pc, #20]	; (15e8 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    15d4:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    15d6:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    15d8:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    15da:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    15de:	4903      	ldr	r1, [pc, #12]	; (15ec <_isr_wrapper+0x3c>)
	bx r1
    15e0:	4708      	bx	r1
    15e2:	0000      	.short	0x0000
	ldr r2, =_kernel
    15e4:	20000ba0 	.word	0x20000ba0
	ldr r1, =_sw_isr_table
    15e8:	00006a64 	.word	0x00006a64
	ldr r1, =z_arm_int_exit
    15ec:	000015f1 	.word	0x000015f1

000015f0 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    15f0:	4b04      	ldr	r3, [pc, #16]	; (1604 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    15f2:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    15f4:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    15f6:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    15f8:	d003      	beq.n	1602 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    15fa:	4903      	ldr	r1, [pc, #12]	; (1608 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    15fc:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    1600:	600a      	str	r2, [r1, #0]

00001602 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    1602:	4770      	bx	lr
	ldr r3, =_kernel
    1604:	20000ba0 	.word	0x20000ba0
	ldr r1, =_SCS_ICSR
    1608:	e000ed04 	.word	0xe000ed04

0000160c <usage_fault.constprop.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    160c:	4b09      	ldr	r3, [pc, #36]	; (1634 <usage_fault.constprop.0+0x28>)
    160e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    1610:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    1612:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    1614:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    1616:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    1618:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    161a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    161c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_STACK_CHK_FAIL;
    161e:	f410 1080 	ands.w	r0, r0, #1048576	; 0x100000
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    1622:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    1626:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
    162a:	bf18      	it	ne
    162c:	2002      	movne	r0, #2
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    162e:	629a      	str	r2, [r3, #40]	; 0x28
}
    1630:	4770      	bx	lr
    1632:	bf00      	nop
    1634:	e000ed00 	.word	0xe000ed00

00001638 <bus_fault.constprop.0>:
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    1638:	4b0d      	ldr	r3, [pc, #52]	; (1670 <bus_fault.constprop.0+0x38>)
    163a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    163c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    163e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1640:	0592      	lsls	r2, r2, #22
    1642:	d508      	bpl.n	1656 <bus_fault.constprop.0+0x1e>
		STORE_xFAR(bfar, SCB->BFAR);
    1644:	6b9a      	ldr	r2, [r3, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    1646:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1648:	0412      	lsls	r2, r2, #16
    164a:	d504      	bpl.n	1656 <bus_fault.constprop.0+0x1e>
			if (from_hard_fault != 0) {
    164c:	b118      	cbz	r0, 1656 <bus_fault.constprop.0+0x1e>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    164e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1650:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    1654:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    1656:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    1658:	4b05      	ldr	r3, [pc, #20]	; (1670 <bus_fault.constprop.0+0x38>)
    165a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    165c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    165e:	05d2      	lsls	r2, r2, #23
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    1660:	bf58      	it	pl
    1662:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1664:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1666:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    166a:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    166c:	7008      	strb	r0, [r1, #0]
}
    166e:	4770      	bx	lr
    1670:	e000ed00 	.word	0xe000ed00

00001674 <mem_manage_fault.constprop.0>:
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1674:	4b12      	ldr	r3, [pc, #72]	; (16c0 <mem_manage_fault.constprop.0+0x4c>)
    1676:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    1678:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    167a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    167c:	0792      	lsls	r2, r2, #30
    167e:	d508      	bpl.n	1692 <mem_manage_fault.constprop.0+0x1e>
		uint32_t temp = SCB->MMFAR;
    1680:	6b5a      	ldr	r2, [r3, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1682:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1684:	0612      	lsls	r2, r2, #24
    1686:	d504      	bpl.n	1692 <mem_manage_fault.constprop.0+0x1e>
			if (from_hard_fault != 0) {
    1688:	b118      	cbz	r0, 1692 <mem_manage_fault.constprop.0+0x1e>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    168a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    168c:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    1690:	629a      	str	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1692:	4b0b      	ldr	r3, [pc, #44]	; (16c0 <mem_manage_fault.constprop.0+0x4c>)
    1694:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1696:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1698:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    169a:	06d0      	lsls	r0, r2, #27
	*recoverable = memory_fault_recoverable(esf, true);
    169c:	f04f 0000 	mov.w	r0, #0
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    16a0:	bf58      	it	pl
    16a2:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    16a4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    16a6:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    16a8:	bf42      	ittt	mi
    16aa:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    16ac:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    16b0:	625a      	strmi	r2, [r3, #36]	; 0x24
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    16b2:	4a03      	ldr	r2, [pc, #12]	; (16c0 <mem_manage_fault.constprop.0+0x4c>)
    16b4:	6a93      	ldr	r3, [r2, #40]	; 0x28
    16b6:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    16ba:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    16bc:	7008      	strb	r0, [r1, #0]
}
    16be:	4770      	bx	lr
    16c0:	e000ed00 	.word	0xe000ed00

000016c4 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    16c4:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    16c6:	4b3c      	ldr	r3, [pc, #240]	; (17b8 <z_arm_fault+0xf4>)
{
    16c8:	460e      	mov	r6, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    16ca:	685b      	ldr	r3, [r3, #4]
    16cc:	2500      	movs	r5, #0
{
    16ce:	b08a      	sub	sp, #40	; 0x28
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    16d0:	f3c3 0308 	ubfx	r3, r3, #0, #9
    16d4:	f385 8811 	msr	BASEPRI, r5
    16d8:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    16dc:	f002 417f 	and.w	r1, r2, #4278190080	; 0xff000000
    16e0:	f1b1 4f7f 	cmp.w	r1, #4278190080	; 0xff000000
    16e4:	d111      	bne.n	170a <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    16e6:	f002 010c 	and.w	r1, r2, #12
    16ea:	2908      	cmp	r1, #8
    16ec:	d00d      	beq.n	170a <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    16ee:	0711      	lsls	r1, r2, #28
    16f0:	d401      	bmi.n	16f6 <z_arm_fault+0x32>
			ptr_esf = (z_arch_esf_t *)msp;
    16f2:	4606      	mov	r6, r0
			*nested_exc = true;
    16f4:	2501      	movs	r5, #1
	*recoverable = false;
    16f6:	2200      	movs	r2, #0
	switch (fault) {
    16f8:	3b03      	subs	r3, #3
	*recoverable = false;
    16fa:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    16fe:	2b03      	cmp	r3, #3
    1700:	d852      	bhi.n	17a8 <z_arm_fault+0xe4>
    1702:	e8df f003 	tbb	[pc, r3]
    1706:	4904      	.short	0x4904
    1708:	464d      	.short	0x464d
		return NULL;
    170a:	462e      	mov	r6, r5
    170c:	e7f3      	b.n	16f6 <z_arm_fault+0x32>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    170e:	4b2a      	ldr	r3, [pc, #168]	; (17b8 <z_arm_fault+0xf4>)
    1710:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    1712:	f014 0402 	ands.w	r4, r4, #2
    1716:	d147      	bne.n	17a8 <z_arm_fault+0xe4>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    1718:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    171a:	2a00      	cmp	r2, #0
    171c:	db14      	blt.n	1748 <z_arm_fault+0x84>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    171e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    1720:	0052      	lsls	r2, r2, #1
    1722:	d511      	bpl.n	1748 <z_arm_fault+0x84>
	uint16_t fault_insn = *(ret_addr - 1);
    1724:	69b2      	ldr	r2, [r6, #24]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    1726:	f832 1c02 	ldrh.w	r1, [r2, #-2]
    172a:	f64d 7202 	movw	r2, #57090	; 0xdf02
    172e:	4291      	cmp	r1, r2
    1730:	d009      	beq.n	1746 <z_arm_fault+0x82>
		} else if (SCB_MMFSR != 0) {
    1732:	f893 2028 	ldrb.w	r2, [r3, #40]	; 0x28
    1736:	b1fa      	cbz	r2, 1778 <z_arm_fault+0xb4>
			reason = mem_manage_fault(esf, 1, recoverable);
    1738:	2001      	movs	r0, #1
    173a:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    173e:	f7ff ff99 	bl	1674 <mem_manage_fault.constprop.0>
    1742:	4604      	mov	r4, r0
		break;
    1744:	e000      	b.n	1748 <z_arm_fault+0x84>
			reason = esf->basic.r0;
    1746:	6834      	ldr	r4, [r6, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    1748:	f89d 3007 	ldrb.w	r3, [sp, #7]
    174c:	b993      	cbnz	r3, 1774 <z_arm_fault+0xb0>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    174e:	2220      	movs	r2, #32
    1750:	4631      	mov	r1, r6
    1752:	a802      	add	r0, sp, #8
    1754:	f003 fe8b 	bl	546e <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    1758:	9b09      	ldr	r3, [sp, #36]	; 0x24
    175a:	b33d      	cbz	r5, 17ac <z_arm_fault+0xe8>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    175c:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1760:	b922      	cbnz	r2, 176c <z_arm_fault+0xa8>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    1762:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1766:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    176a:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    176c:	4620      	mov	r0, r4
    176e:	a902      	add	r1, sp, #8
    1770:	f003 fe26 	bl	53c0 <z_arm_fatal_error>
}
    1774:	b00a      	add	sp, #40	; 0x28
    1776:	bd70      	pop	{r4, r5, r6, pc}
		} else if (SCB_BFSR != 0) {
    1778:	f893 2029 	ldrb.w	r2, [r3, #41]	; 0x29
    177c:	b12a      	cbz	r2, 178a <z_arm_fault+0xc6>
			reason = bus_fault(esf, 1, recoverable);
    177e:	2001      	movs	r0, #1
    1780:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
    1784:	f7ff ff58 	bl	1638 <bus_fault.constprop.0>
    1788:	e7db      	b.n	1742 <z_arm_fault+0x7e>
		} else if (SCB_UFSR != 0) {
    178a:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
    178c:	b29b      	uxth	r3, r3
    178e:	2b00      	cmp	r3, #0
    1790:	d0da      	beq.n	1748 <z_arm_fault+0x84>
		reason = usage_fault(esf);
    1792:	f7ff ff3b 	bl	160c <usage_fault.constprop.0>
    1796:	e7d4      	b.n	1742 <z_arm_fault+0x7e>
		reason = mem_manage_fault(esf, 0, recoverable);
    1798:	2000      	movs	r0, #0
    179a:	f10d 0107 	add.w	r1, sp, #7
    179e:	e7ce      	b.n	173e <z_arm_fault+0x7a>
		reason = bus_fault(esf, 0, recoverable);
    17a0:	2000      	movs	r0, #0
    17a2:	f10d 0107 	add.w	r1, sp, #7
    17a6:	e7ed      	b.n	1784 <z_arm_fault+0xc0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    17a8:	2400      	movs	r4, #0
    17aa:	e7cd      	b.n	1748 <z_arm_fault+0x84>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    17ac:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    17b0:	f023 0301 	bic.w	r3, r3, #1
    17b4:	e7d9      	b.n	176a <z_arm_fault+0xa6>
    17b6:	bf00      	nop
    17b8:	e000ed00 	.word	0xe000ed00

000017bc <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    17bc:	4b04      	ldr	r3, [pc, #16]	; (17d0 <z_arm_fault_init+0x14>)
    17be:	695a      	ldr	r2, [r3, #20]
    17c0:	f042 0210 	orr.w	r2, r2, #16
    17c4:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    17c6:	695a      	ldr	r2, [r3, #20]
    17c8:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    17cc:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    17ce:	4770      	bx	lr
    17d0:	e000ed00 	.word	0xe000ed00

000017d4 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    17d4:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    17d8:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    17dc:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    17de:	4672      	mov	r2, lr
	bl z_arm_fault
    17e0:	f7ff ff70 	bl	16c4 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    17e4:	bd01      	pop	{r0, pc}
    17e6:	bf00      	nop

000017e8 <z_arm_interrupt_init>:
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    17e8:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    17ea:	2120      	movs	r1, #32
    17ec:	4803      	ldr	r0, [pc, #12]	; (17fc <z_arm_interrupt_init+0x14>)
    17ee:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    17f0:	3301      	adds	r3, #1
    17f2:	2b45      	cmp	r3, #69	; 0x45
    17f4:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    17f8:	d1f9      	bne.n	17ee <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    17fa:	4770      	bx	lr
    17fc:	e000e100 	.word	0xe000e100

00001800 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    1800:	2000      	movs	r0, #0
    msr CONTROL, r0
    1802:	f380 8814 	msr	CONTROL, r0
    isb
    1806:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
    /* Clear SPLIM registers */
    movs.n r0, #0
    180a:	2000      	movs	r0, #0
    msr MSPLIM, r0
    180c:	f380 880a 	msr	MSPLIM, r0
    msr PSPLIM, r0
    1810:	f380 880b 	msr	PSPLIM, r0
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    1814:	f005 f8bc 	bl	6990 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    1818:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    181a:	490e      	ldr	r1, [pc, #56]	; (1854 <__start+0x54>)
    str r0, [r1]
    181c:	6008      	str	r0, [r1, #0]
    dsb
    181e:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1822:	480d      	ldr	r0, [pc, #52]	; (1858 <__start+0x58>)
    msr msp, r0
    1824:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    1828:	f000 f83e 	bl	18a8 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    182c:	2020      	movs	r0, #32
    msr BASEPRI, r0
    182e:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    1832:	480a      	ldr	r0, [pc, #40]	; (185c <__start+0x5c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    1834:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    1838:	1840      	adds	r0, r0, r1
    msr PSP, r0
    183a:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    183e:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    1842:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    1844:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1846:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    184a:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    184e:	f7ff fe0d 	bl	146c <z_arm_prep_c>
    1852:	0000      	.short	0x0000
    ldr r1, =_SCS_MPU_CTRL
    1854:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1858:	200011b8 	.word	0x200011b8
    ldr r0, =z_interrupt_stacks
    185c:	200012f8 	.word	0x200012f8

00001860 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    1860:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    1864:	4905      	ldr	r1, [pc, #20]	; (187c <sys_arch_reboot+0x1c>)
    1866:	4b06      	ldr	r3, [pc, #24]	; (1880 <sys_arch_reboot+0x20>)
    1868:	68ca      	ldr	r2, [r1, #12]
    186a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    186e:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    1870:	60cb      	str	r3, [r1, #12]
    1872:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    1876:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    1878:	e7fd      	b.n	1876 <sys_arch_reboot+0x16>
    187a:	bf00      	nop
    187c:	e000ed00 	.word	0xe000ed00
    1880:	05fa0004 	.word	0x05fa0004

00001884 <z_arm_clear_arm_mpu_config>:
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);

	for (i = 0; i < num_regions; i++) {
    1884:	2300      	movs	r3, #0
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
  mpu->RNR = rnr;
  mpu->RLAR = 0U;
    1886:	4618      	mov	r0, r3
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    1888:	4906      	ldr	r1, [pc, #24]	; (18a4 <z_arm_clear_arm_mpu_config+0x20>)
    188a:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90
	int num_regions =
    188e:	f3c2 2207 	ubfx	r2, r2, #8, #8
	for (i = 0; i < num_regions; i++) {
    1892:	4293      	cmp	r3, r2
    1894:	d100      	bne.n	1898 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    1896:	4770      	bx	lr
  mpu->RNR = rnr;
    1898:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  mpu->RLAR = 0U;
    189c:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    18a0:	3301      	adds	r3, #1
    18a2:	e7f6      	b.n	1892 <z_arm_clear_arm_mpu_config+0xe>
    18a4:	e000ed00 	.word	0xe000ed00

000018a8 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    18a8:	b510      	push	{r4, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    18aa:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    18ac:	2400      	movs	r4, #0
    18ae:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    18b2:	f7ff ffe7 	bl	1884 <z_arm_clear_arm_mpu_config>
    18b6:	4623      	mov	r3, r4
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    18b8:	f04f 30ff 	mov.w	r0, #4294967295
    18bc:	4a0b      	ldr	r2, [pc, #44]	; (18ec <z_arm_init_arch_hw_at_boot+0x44>)
    18be:	f103 0120 	add.w	r1, r3, #32
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    18c2:	3301      	adds	r3, #1
    18c4:	2b10      	cmp	r3, #16
		NVIC->ICER[i] = 0xFFFFFFFF;
    18c6:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    18ca:	d1f8      	bne.n	18be <z_arm_init_arch_hw_at_boot+0x16>
    18cc:	2300      	movs	r3, #0
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    18ce:	f04f 30ff 	mov.w	r0, #4294967295
    18d2:	f103 0160 	add.w	r1, r3, #96	; 0x60
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    18d6:	3301      	adds	r3, #1
    18d8:	2b10      	cmp	r3, #16
		NVIC->ICPR[i] = 0xFFFFFFFF;
    18da:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    18de:	d1f8      	bne.n	18d2 <z_arm_init_arch_hw_at_boot+0x2a>
  __ASM volatile ("cpsie i" : : : "memory");
    18e0:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    18e2:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    18e6:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    18ea:	bd10      	pop	{r4, pc}
    18ec:	e000e100 	.word	0xe000e100

000018f0 <z_impl_k_thread_abort>:
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    18f0:	4b08      	ldr	r3, [pc, #32]	; (1914 <z_impl_k_thread_abort+0x24>)
    18f2:	689b      	ldr	r3, [r3, #8]
    18f4:	4283      	cmp	r3, r0
    18f6:	d10b      	bne.n	1910 <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    18f8:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    18fc:	b143      	cbz	r3, 1910 <z_impl_k_thread_abort+0x20>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    18fe:	4b06      	ldr	r3, [pc, #24]	; (1918 <z_impl_k_thread_abort+0x28>)
    1900:	685a      	ldr	r2, [r3, #4]
    1902:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
    1906:	605a      	str	r2, [r3, #4]
			/* Clear any system calls that may be pending
			 * as they have a higher priority than the PendSV
			 * handler and will check the stack of the thread
			 * being aborted.
			 */
			SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk;
    1908:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    190a:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    190e:	625a      	str	r2, [r3, #36]	; 0x24
		}
	}

	z_thread_abort(thread);
    1910:	f002 bffc 	b.w	490c <z_thread_abort>
    1914:	20000ba0 	.word	0x20000ba0
    1918:	e000ed00 	.word	0xe000ed00

0000191c <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    191c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    191e:	4c09      	ldr	r4, [pc, #36]	; (1944 <z_arm_configure_static_mpu_regions+0x28>)
    1920:	4a09      	ldr	r2, [pc, #36]	; (1948 <z_arm_configure_static_mpu_regions+0x2c>)
    1922:	4623      	mov	r3, r4
    1924:	2101      	movs	r1, #1
    1926:	4809      	ldr	r0, [pc, #36]	; (194c <z_arm_configure_static_mpu_regions+0x30>)
    1928:	f000 f8f2 	bl	1b10 <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of z_arm_mpu_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    192c:	2300      	movs	r3, #0
    192e:	9303      	str	r3, [sp, #12]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    1930:	4b07      	ldr	r3, [pc, #28]	; (1950 <z_arm_configure_static_mpu_regions+0x34>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1932:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    1934:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1936:	a801      	add	r0, sp, #4
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    1938:	9301      	str	r3, [sp, #4]
    193a:	9402      	str	r4, [sp, #8]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    193c:	f000 f8f2 	bl	1b24 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    1940:	b004      	add	sp, #16
    1942:	bd10      	pop	{r4, pc}
    1944:	20070000 	.word	0x20070000
    1948:	20000000 	.word	0x20000000
    194c:	00006ce4 	.word	0x00006ce4
    1950:	20000268 	.word	0x20000268

00001954 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    1954:	b510      	push	{r4, lr}
	ARM_MPU_SetRegion(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
    1956:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    1958:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    195a:	f023 021f 	bic.w	r2, r3, #31
		| (region_conf->attr.rbar &
    195e:	f004 031f 	and.w	r3, r4, #31
    1962:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    1964:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    1966:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    1968:	f023 031f 	bic.w	r3, r3, #31
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/   
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
  mpu->RNR = rnr;
    196c:	4905      	ldr	r1, [pc, #20]	; (1984 <region_init+0x30>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    196e:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    1972:	f043 0301 	orr.w	r3, r3, #1
    1976:	f8c1 0098 	str.w	r0, [r1, #152]	; 0x98
  mpu->RBAR = rbar;
    197a:	f8c1 209c 	str.w	r2, [r1, #156]	; 0x9c
  mpu->RLAR = rlar;
    197e:	f8c1 30a0 	str.w	r3, [r1, #160]	; 0xa0
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    1982:	bd10      	pop	{r4, pc}
    1984:	e000ed00 	.word	0xe000ed00

00001988 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    1988:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    198c:	460f      	mov	r7, r1
    198e:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    1990:	4606      	mov	r6, r0
    1992:	f04f 0800 	mov.w	r8, #0
	MPU->RNR = index;
    1996:	4d52      	ldr	r5, [pc, #328]	; (1ae0 <mpu_configure_regions_and_partition.constprop.0+0x158>)
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    1998:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
    199a:	45b8      	cmp	r8, r7
    199c:	da09      	bge.n	19b2 <mpu_configure_regions_and_partition.constprop.0+0x2a>
		if (regions[i].size == 0U) {
    199e:	f8d6 9004 	ldr.w	r9, [r6, #4]
    19a2:	f1b9 0f00 	cmp.w	r9, #0
    19a6:	d03a      	beq.n	1a1e <mpu_configure_regions_and_partition.constprop.0+0x96>
		&&
    19a8:	f1b9 0f1f 	cmp.w	r9, #31
    19ac:	d805      	bhi.n	19ba <mpu_configure_regions_and_partition.constprop.0+0x32>

			reg_index =
				mpu_configure_region(reg_index, &regions[i]);

			if (reg_index == -EINVAL) {
				return reg_index;
    19ae:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
    19b2:	4620      	mov	r0, r4
    19b4:	b005      	add	sp, #20
    19b6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		&&
    19ba:	f019 0f1f 	tst.w	r9, #31
    19be:	d1f6      	bne.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
		((part->start &
    19c0:	f8d6 a000 	ldr.w	sl, [r6]
		&&
    19c4:	f01a 0f1f 	tst.w	sl, #31
    19c8:	d1f1      	bne.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    19ca:	4650      	mov	r0, sl
    19cc:	f003 fd0d 	bl	53ea <arm_cmse_mpu_region_get>
    19d0:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    19d2:	eb09 000a 	add.w	r0, r9, sl
    19d6:	3801      	subs	r0, #1
    19d8:	f003 fd07 	bl	53ea <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    19dc:	4583      	cmp	fp, r0
    19de:	d1e6      	bne.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
		if ((u_reg_index == -EINVAL) ||
    19e0:	f11b 0f16 	cmn.w	fp, #22
    19e4:	d0e3      	beq.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
    19e6:	455c      	cmp	r4, fp
    19e8:	dde1      	ble.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
	MPU->RNR = index;
    19ea:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    19ee:	f8d5 109c 	ldr.w	r1, [r5, #156]	; 0x9c
	MPU->RNR = index;
    19f2:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    19f6:	f8d5 30a0 	ldr.w	r3, [r5, #160]	; 0xa0
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    19fa:	f021 011f 	bic.w	r1, r1, #31
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    19fe:	f043 0a1f 	orr.w	sl, r3, #31
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    1a02:	e9d6 3200 	ldrd	r3, r2, [r6]
    1a06:	441a      	add	r2, r3
		if ((regions[i].start == u_reg_base) &&
    1a08:	4299      	cmp	r1, r3
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    1a0a:	f102 39ff 	add.w	r9, r2, #4294967295
		if ((regions[i].start == u_reg_base) &&
    1a0e:	d11e      	bne.n	1a4e <mpu_configure_regions_and_partition.constprop.0+0xc6>
    1a10:	45ca      	cmp	sl, r9
    1a12:	d108      	bne.n	1a26 <mpu_configure_regions_and_partition.constprop.0+0x9e>
			mpu_configure_region(u_reg_index, &regions[i]);
    1a14:	4631      	mov	r1, r6
    1a16:	fa5f f08b 	uxtb.w	r0, fp
    1a1a:	f003 fcef 	bl	53fc <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    1a1e:	f108 0801 	add.w	r8, r8, #1
    1a22:	360c      	adds	r6, #12
    1a24:	e7b9      	b.n	199a <mpu_configure_regions_and_partition.constprop.0+0x12>
				mpu_configure_region(reg_index, &regions[i]);
    1a26:	4631      	mov	r1, r6
	MPU->RNR = index;
    1a28:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    1a2c:	f8d5 309c 	ldr.w	r3, [r5, #156]	; 0x9c
		| (base & MPU_RBAR_BASE_Msk);
    1a30:	f022 021f 	bic.w	r2, r2, #31
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    1a34:	f003 031f 	and.w	r3, r3, #31
		| (base & MPU_RBAR_BASE_Msk);
    1a38:	431a      	orrs	r2, r3
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    1a3a:	f8c5 209c 	str.w	r2, [r5, #156]	; 0x9c
				mpu_configure_region(reg_index, &regions[i]);
    1a3e:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, &regions[i]);
    1a40:	f003 fcdc 	bl	53fc <mpu_configure_region>
			if (reg_index == -EINVAL) {
    1a44:	f110 0f16 	cmn.w	r0, #22
    1a48:	d0b1      	beq.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
			reg_index++;
    1a4a:	1c44      	adds	r4, r0, #1
    1a4c:	e7e7      	b.n	1a1e <mpu_configure_regions_and_partition.constprop.0+0x96>
				regions[i].start - 1);
    1a4e:	3b01      	subs	r3, #1
		} else if (reg_last == u_reg_last) {
    1a50:	45ca      	cmp	sl, r9
				mpu_configure_region(reg_index, &regions[i]);
    1a52:	b2e0      	uxtb	r0, r4
		| (limit & MPU_RLAR_LIMIT_Msk);
    1a54:	f023 031f 	bic.w	r3, r3, #31
	MPU->RNR = index;
    1a58:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
		} else if (reg_last == u_reg_last) {
    1a5c:	d108      	bne.n	1a70 <mpu_configure_regions_and_partition.constprop.0+0xe8>
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1a5e:	f8d5 20a0 	ldr.w	r2, [r5, #160]	; 0xa0
				mpu_configure_region(reg_index, &regions[i]);
    1a62:	4631      	mov	r1, r6
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1a64:	f002 021f 	and.w	r2, r2, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    1a68:	4313      	orrs	r3, r2
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1a6a:	f8c5 30a0 	str.w	r3, [r5, #160]	; 0xa0
			reg_index =
    1a6e:	e7e7      	b.n	1a40 <mpu_configure_regions_and_partition.constprop.0+0xb8>
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1a70:	f8d5 10a0 	ldr.w	r1, [r5, #160]	; 0xa0
    1a74:	f001 011f 	and.w	r1, r1, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    1a78:	430b      	orrs	r3, r1
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1a7a:	f8c5 30a0 	str.w	r3, [r5, #160]	; 0xa0
				mpu_configure_region(reg_index, &regions[i]);
    1a7e:	4631      	mov	r1, r6
    1a80:	f003 fcbc 	bl	53fc <mpu_configure_region>
			if (reg_index == -EINVAL) {
    1a84:	f110 0f16 	cmn.w	r0, #22
    1a88:	d091      	beq.n	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
	MPU->RNR = index;
    1a8a:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	attr->rbar = MPU->RBAR &
    1a8e:	f8d5 209c 	ldr.w	r2, [r5, #156]	; 0x9c
    1a92:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i].start +
    1a96:	f10a 3aff 	add.w	sl, sl, #4294967295
	attr->rbar = MPU->RBAR &
    1a9a:	f362 0304 	bfi	r3, r2, #0, #5
    1a9e:	f88d 3008 	strb.w	r3, [sp, #8]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    1aa2:	f8d5 30a0 	ldr.w	r3, [r5, #160]	; 0xa0
    1aa6:	f89d 2008 	ldrb.w	r2, [sp, #8]
    1aaa:	085b      	lsrs	r3, r3, #1
    1aac:	f363 1247 	bfi	r2, r3, #5, #3
    1ab0:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i].start +
    1ab4:	e9d6 3200 	ldrd	r3, r2, [r6]
    1ab8:	4413      	add	r3, r2
    1aba:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i].start +
    1abc:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
    1ac0:	1c41      	adds	r1, r0, #1
			REGION_LIMIT_ADDR((regions[i].start +
    1ac2:	4453      	add	r3, sl
    1ac4:	eba3 0309 	sub.w	r3, r3, r9
    1ac8:	b2c8      	uxtb	r0, r1
    1aca:	f023 031f 	bic.w	r3, r3, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1U)) {
    1ace:	2807      	cmp	r0, #7
			fill_region.attr.r_limit =
    1ad0:	9303      	str	r3, [sp, #12]
    1ad2:	f63f af6c 	bhi.w	19ae <mpu_configure_regions_and_partition.constprop.0+0x26>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    1ad6:	4669      	mov	r1, sp
    1ad8:	f7ff ff3c 	bl	1954 <region_init>
    1adc:	e7b5      	b.n	1a4a <mpu_configure_regions_and_partition.constprop.0+0xc2>
    1ade:	bf00      	nop
    1ae0:	e000ed00 	.word	0xe000ed00

00001ae4 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    1ae4:	2205      	movs	r2, #5
    1ae6:	4b04      	ldr	r3, [pc, #16]	; (1af8 <arm_core_mpu_enable+0x14>)
    1ae8:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    1aec:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1af0:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1af4:	4770      	bx	lr
    1af6:	bf00      	nop
    1af8:	e000ed00 	.word	0xe000ed00

00001afc <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    1afc:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1b00:	2200      	movs	r2, #0
    1b02:	4b02      	ldr	r3, [pc, #8]	; (1b0c <arm_core_mpu_disable+0x10>)
    1b04:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    1b08:	4770      	bx	lr
    1b0a:	bf00      	nop
    1b0c:	e000ed00 	.word	0xe000ed00

00001b10 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    1b10:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    1b12:	4c03      	ldr	r4, [pc, #12]	; (1b20 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    1b14:	7822      	ldrb	r2, [r4, #0]
    1b16:	f7ff ff37 	bl	1988 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    1b1a:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    1b1c:	bd10      	pop	{r4, pc}
    1b1e:	bf00      	nop
    1b20:	20000db0 	.word	0x20000db0

00001b24 <arm_core_mpu_mark_areas_for_dynamic_regions>:
 * @brief mark memory areas for dynamic region configuration
 */
void arm_core_mpu_mark_areas_for_dynamic_regions(
	const struct z_arm_mpu_partition dyn_region_areas[],
	const uint8_t dyn_region_areas_num)
{
    1b24:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1b28:	4d29      	ldr	r5, [pc, #164]	; (1bd0 <arm_core_mpu_mark_areas_for_dynamic_regions+0xac>)
    1b2a:	468a      	mov	sl, r1

/* This internal function marks and stores the configuration of memory areas
 * where dynamic region programming is allowed. Return zero on success, or
 * -EINVAL on error.
 */
static int mpu_mark_areas_for_dynamic_regions(
    1b2c:	4606      	mov	r6, r0
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1b2e:	f04f 0800 	mov.w	r8, #0
    1b32:	46ab      	mov	fp, r5
	MPU->RNR = index;
    1b34:	4f27      	ldr	r7, [pc, #156]	; (1bd4 <arm_core_mpu_mark_areas_for_dynamic_regions+0xb0>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1b36:	45d0      	cmp	r8, sl
    1b38:	da1b      	bge.n	1b72 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
    1b3a:	f8d6 9004 	ldr.w	r9, [r6, #4]
    1b3e:	f1b9 0f00 	cmp.w	r9, #0
    1b42:	d03f      	beq.n	1bc4 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    1b44:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1b46:	4608      	mov	r0, r1
    1b48:	9101      	str	r1, [sp, #4]
    1b4a:	f003 fc4e 	bl	53ea <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1b4e:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1b50:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1b52:	eb09 0001 	add.w	r0, r9, r1
    1b56:	3801      	subs	r0, #1
    1b58:	f003 fc47 	bl	53ea <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    1b5c:	4284      	cmp	r4, r0
    1b5e:	f04f 0214 	mov.w	r2, #20
    1b62:	4b1d      	ldr	r3, [pc, #116]	; (1bd8 <arm_core_mpu_mark_areas_for_dynamic_regions+0xb4>)
    1b64:	d008      	beq.n	1b78 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
    1b66:	f06f 0315 	mvn.w	r3, #21
    1b6a:	fb02 f808 	mul.w	r8, r2, r8
    1b6e:	f84b 3008 	str.w	r3, [fp, r8]
						 dyn_region_areas_num) == -EINVAL) {

		__ASSERT(0, "Marking %u areas for dynamic regions failed\n",
			dyn_region_areas_num);
	}
}
    1b72:	b003      	add	sp, #12
    1b74:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    1b78:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    1b7c:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    1b7e:	d0f8      	beq.n	1b72 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    1b80:	7819      	ldrb	r1, [r3, #0]
    1b82:	42a1      	cmp	r1, r4
    1b84:	ddf5      	ble.n	1b72 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = MPU->RBAR &
    1b86:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = index;
    1b8a:	f8c7 4098 	str.w	r4, [r7, #152]	; 0x98
	MPU->RNR = index;
    1b8e:	f8c7 4098 	str.w	r4, [r7, #152]	; 0x98
	attr->rbar = MPU->RBAR &
    1b92:	f8d7 409c 	ldr.w	r4, [r7, #156]	; 0x9c
    1b96:	f100 0108 	add.w	r1, r0, #8
    1b9a:	7b00      	ldrb	r0, [r0, #12]
    1b9c:	f364 0004 	bfi	r0, r4, #0, #5
    1ba0:	7108      	strb	r0, [r1, #4]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    1ba2:	f8d7 00a0 	ldr.w	r0, [r7, #160]	; 0xa0
    1ba6:	790c      	ldrb	r4, [r1, #4]
    1ba8:	0840      	lsrs	r0, r0, #1
    1baa:	f360 1447 	bfi	r4, r0, #5, #3
    1bae:	710c      	strb	r4, [r1, #4]
	region_conf->base = (MPU->RBAR & MPU_RBAR_BASE_Msk);
    1bb0:	f8d7 109c 	ldr.w	r1, [r7, #156]	; 0x9c
    1bb4:	f021 011f 	bic.w	r1, r1, #31
    1bb8:	6069      	str	r1, [r5, #4]
	region_conf->attr.r_limit = MPU->RLAR & MPU_RLAR_LIMIT_Msk;
    1bba:	f8d7 10a0 	ldr.w	r1, [r7, #160]	; 0xa0
    1bbe:	f021 011f 	bic.w	r1, r1, #31
    1bc2:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1bc4:	f108 0801 	add.w	r8, r8, #1
    1bc8:	3514      	adds	r5, #20
    1bca:	360c      	adds	r6, #12
    1bcc:	e7b3      	b.n	1b36 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    1bce:	bf00      	nop
    1bd0:	20000a9c 	.word	0x20000a9c
    1bd4:	e000ed00 	.word	0xe000ed00
    1bd8:	20000db0 	.word	0x20000db0

00001bdc <z_arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
int z_arm_mpu_init(void)
{
    1bdc:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    1bde:	4d0e      	ldr	r5, [pc, #56]	; (1c18 <z_arm_mpu_init+0x3c>)
    1be0:	682c      	ldr	r4, [r5, #0]
    1be2:	2c08      	cmp	r4, #8
    1be4:	d815      	bhi.n	1c12 <z_arm_mpu_init+0x36>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1be6:	2000      	movs	r0, #0
	arm_core_mpu_disable();
    1be8:	f7ff ff88 	bl	1afc <arm_core_mpu_disable>
	MPU->MAIR0 =
    1bec:	4b0b      	ldr	r3, [pc, #44]	; (1c1c <z_arm_mpu_init+0x40>)
    1bee:	4a0c      	ldr	r2, [pc, #48]	; (1c20 <z_arm_mpu_init+0x44>)
    1bf0:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1bf4:	4284      	cmp	r4, r0
    1bf6:	d105      	bne.n	1c04 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    1bf8:	4b0a      	ldr	r3, [pc, #40]	; (1c24 <z_arm_mpu_init+0x48>)
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    1bfa:	2000      	movs	r0, #0
	static_regions_num = mpu_config.num_regions;
    1bfc:	701c      	strb	r4, [r3, #0]
	arm_core_mpu_enable();
    1bfe:	f7ff ff71 	bl	1ae4 <arm_core_mpu_enable>
}
    1c02:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    1c04:	6869      	ldr	r1, [r5, #4]
    1c06:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    1c0a:	f7ff fea3 	bl	1954 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1c0e:	3001      	adds	r0, #1
    1c10:	e7f0      	b.n	1bf4 <z_arm_mpu_init+0x18>
		return -1;
    1c12:	f04f 30ff 	mov.w	r0, #4294967295
    1c16:	e7f4      	b.n	1c02 <z_arm_mpu_init+0x26>
    1c18:	00006cf0 	.word	0x00006cf0
    1c1c:	e000ed00 	.word	0xe000ed00
    1c20:	0044ffaa 	.word	0x0044ffaa
    1c24:	20000db0 	.word	0x20000db0

00001c28 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1c28:	4b08      	ldr	r3, [pc, #32]	; (1c4c <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1c2a:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1c2c:	1ac3      	subs	r3, r0, r3
{
    1c2e:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1c30:	4907      	ldr	r1, [pc, #28]	; (1c50 <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    1c32:	109b      	asrs	r3, r3, #2
{
    1c34:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1c36:	4359      	muls	r1, r3
    1c38:	2240      	movs	r2, #64	; 0x40
    1c3a:	4806      	ldr	r0, [pc, #24]	; (1c54 <onoff_stop+0x2c>)
    1c3c:	f003 fc47 	bl	54ce <stop>
	notify(mgr, res);
    1c40:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1c42:	4601      	mov	r1, r0
	notify(mgr, res);
    1c44:	4620      	mov	r0, r4
}
    1c46:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    1c4a:	4718      	bx	r3
    1c4c:	20000ac0 	.word	0x20000ac0
    1c50:	b6db6db7 	.word	0xb6db6db7
    1c54:	000069ec 	.word	0x000069ec

00001c58 <onoff_start>:
static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1c58:	2340      	movs	r3, #64	; 0x40
{
    1c5a:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1c5c:	4c0b      	ldr	r4, [pc, #44]	; (1c8c <onoff_start+0x34>)
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1c5e:	9300      	str	r3, [sp, #0]
	size_t offset = (size_t)(mgr - data->mgr);
    1c60:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1c62:	460b      	mov	r3, r1
{
    1c64:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1c66:	490a      	ldr	r1, [pc, #40]	; (1c90 <onoff_start+0x38>)
	size_t offset = (size_t)(mgr - data->mgr);
    1c68:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1c6a:	4361      	muls	r1, r4
{
    1c6c:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1c6e:	4a09      	ldr	r2, [pc, #36]	; (1c94 <onoff_start+0x3c>)
    1c70:	4809      	ldr	r0, [pc, #36]	; (1c98 <onoff_start+0x40>)
    1c72:	f003 fc58 	bl	5526 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    1c76:	1e01      	subs	r1, r0, #0
    1c78:	da05      	bge.n	1c86 <onoff_start+0x2e>
		notify(mgr, err);
    1c7a:	4630      	mov	r0, r6
    1c7c:	462b      	mov	r3, r5
	}
}
    1c7e:	b002      	add	sp, #8
    1c80:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    1c84:	4718      	bx	r3
}
    1c86:	b002      	add	sp, #8
    1c88:	bd70      	pop	{r4, r5, r6, pc}
    1c8a:	bf00      	nop
    1c8c:	20000ac0 	.word	0x20000ac0
    1c90:	b6db6db7 	.word	0xb6db6db7
    1c94:	00005597 	.word	0x00005597
    1c98:	000069ec 	.word	0x000069ec

00001c9c <clk_init>:
#endif /* NRF_CLOCK_HAS_HFCLKAUDIO */
#endif
}

static int clk_init(const struct device *dev)
{
    1c9c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1ca0:	2200      	movs	r2, #0
    1ca2:	2101      	movs	r1, #1
{
    1ca4:	4606      	mov	r6, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1ca6:	2005      	movs	r0, #5
    1ca8:	f7ff fbc6 	bl	1438 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1cac:	4811      	ldr	r0, [pc, #68]	; (1cf4 <clk_init+0x58>)
    1cae:	f001 fbbd 	bl	342c <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1cb2:	4b11      	ldr	r3, [pc, #68]	; (1cf8 <clk_init+0x5c>)
    1cb4:	4298      	cmp	r0, r3
    1cb6:	d119      	bne.n	1cec <clk_init+0x50>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    1cb8:	f004 fbc8 	bl	644c <nrfx_clock_enable>
    1cbc:	2400      	movs	r4, #0
	return &data->mgr[type];
    1cbe:	f04f 081c 	mov.w	r8, #28
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1cc2:	270c      	movs	r7, #12
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1cc4:	f8df 9034 	ldr.w	r9, [pc, #52]	; 1cfc <clk_init+0x60>
	struct nrf_clock_control_data *data = dev->data;
    1cc8:	6935      	ldr	r5, [r6, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1cca:	4649      	mov	r1, r9
    1ccc:	fb08 5004 	mla	r0, r8, r4, r5
    1cd0:	f003 fa68 	bl	51a4 <onoff_manager_init>
		if (err < 0) {
    1cd4:	2800      	cmp	r0, #0
    1cd6:	db07      	blt.n	1ce8 <clk_init+0x4c>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1cd8:	2301      	movs	r3, #1
    1cda:	fb07 5504 	mla	r5, r7, r4, r5
	for (enum clock_control_nrf_type i = 0;
    1cde:	441c      	add	r4, r3
    1ce0:	2c04      	cmp	r4, #4
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1ce2:	67ab      	str	r3, [r5, #120]	; 0x78
	for (enum clock_control_nrf_type i = 0;
    1ce4:	d1f0      	bne.n	1cc8 <clk_init+0x2c>
	}

	return 0;
    1ce6:	2000      	movs	r0, #0
}
    1ce8:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
    1cec:	f06f 0004 	mvn.w	r0, #4
    1cf0:	e7fa      	b.n	1ce8 <clk_init+0x4c>
    1cf2:	bf00      	nop
    1cf4:	00001d35 	.word	0x00001d35
    1cf8:	0bad0000 	.word	0x0bad0000
    1cfc:	00006d50 	.word	0x00006d50

00001d00 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1d00:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    1d02:	230c      	movs	r3, #12
	sub_data->cb = NULL;
    1d04:	2200      	movs	r2, #0
	clock_control_cb_t callback = sub_data->cb;
    1d06:	434b      	muls	r3, r1
    1d08:	4808      	ldr	r0, [pc, #32]	; (1d2c <clkstarted_handle.constprop.0+0x2c>)
static void clkstarted_handle(const struct device *dev,
    1d0a:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    1d0c:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
    1d0e:	3378      	adds	r3, #120	; 0x78
	void *user_data = sub_data->user_data;
    1d10:	e9d4 561c 	ldrd	r5, r6, [r4, #112]	; 0x70
	set_on_state(&sub_data->flags);
    1d14:	4418      	add	r0, r3
	sub_data->cb = NULL;
    1d16:	6722      	str	r2, [r4, #112]	; 0x70
	set_on_state(&sub_data->flags);
    1d18:	f003 fbc6 	bl	54a8 <set_on_state>
	if (callback) {
    1d1c:	b12d      	cbz	r5, 1d2a <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1d1e:	4632      	mov	r2, r6
    1d20:	462b      	mov	r3, r5
}
    1d22:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    1d26:	4802      	ldr	r0, [pc, #8]	; (1d30 <clkstarted_handle.constprop.0+0x30>)
    1d28:	4718      	bx	r3
}
    1d2a:	bd70      	pop	{r4, r5, r6, pc}
    1d2c:	20000ac0 	.word	0x20000ac0
    1d30:	000069ec 	.word	0x000069ec

00001d34 <clock_event_handler>:
	switch (event) {
    1d34:	2805      	cmp	r0, #5
    1d36:	d811      	bhi.n	1d5c <clock_event_handler+0x28>
    1d38:	e8df f000 	tbb	[pc, r0]
    1d3c:	10100e03 	.word	0x10100e03
    1d40:	0a0c      	.short	0x0a0c
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    1d42:	4b07      	ldr	r3, [pc, #28]	; (1d60 <clock_event_handler+0x2c>)
    1d44:	6f98      	ldr	r0, [r3, #120]	; 0x78
    1d46:	f010 0007 	ands.w	r0, r0, #7
    1d4a:	d107      	bne.n	1d5c <clock_event_handler+0x28>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    1d4c:	f7ff bfd8 	b.w	1d00 <clkstarted_handle.constprop.0>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK192M);
    1d50:	2002      	movs	r0, #2
    1d52:	e7fb      	b.n	1d4c <clock_event_handler+0x18>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLKAUDIO);
    1d54:	2003      	movs	r0, #3
    1d56:	e7f9      	b.n	1d4c <clock_event_handler+0x18>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    1d58:	2001      	movs	r0, #1
    1d5a:	e7f7      	b.n	1d4c <clock_event_handler+0x18>
}
    1d5c:	4770      	bx	lr
    1d5e:	bf00      	nop
    1d60:	20000ac0 	.word	0x20000ac0

00001d64 <generic_hfclk_start>:
{
    1d64:	b508      	push	{r3, lr}
	__asm__ volatile(
    1d66:	f04f 0320 	mov.w	r3, #32
    1d6a:	f3ef 8111 	mrs	r1, BASEPRI
    1d6e:	f383 8812 	msr	BASEPRI_MAX, r3
    1d72:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    1d76:	4a12      	ldr	r2, [pc, #72]	; (1dc0 <generic_hfclk_start+0x5c>)
    1d78:	6813      	ldr	r3, [r2, #0]
    1d7a:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    1d7e:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    1d82:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1d84:	d00c      	beq.n	1da0 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    1d86:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    1d8a:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1d8e:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1d92:	f013 0301 	ands.w	r3, r3, #1
    1d96:	d003      	beq.n	1da0 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    1d98:	480a      	ldr	r0, [pc, #40]	; (1dc4 <generic_hfclk_start+0x60>)
    1d9a:	f003 fb85 	bl	54a8 <set_on_state>
			already_started = true;
    1d9e:	2301      	movs	r3, #1
	__asm__ volatile(
    1da0:	f381 8811 	msr	BASEPRI, r1
    1da4:	f3bf 8f6f 	isb	sy
	if (already_started) {
    1da8:	b123      	cbz	r3, 1db4 <generic_hfclk_start+0x50>
}
    1daa:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    1dae:	2000      	movs	r0, #0
    1db0:	f7ff bfa6 	b.w	1d00 <clkstarted_handle.constprop.0>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    1db4:	2001      	movs	r0, #1
}
    1db6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    1dba:	f004 bb59 	b.w	6470 <nrfx_clock_start>
    1dbe:	bf00      	nop
    1dc0:	20000b60 	.word	0x20000b60
    1dc4:	20000b38 	.word	0x20000b38

00001dc8 <api_blocking_start>:
{
    1dc8:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1dca:	2200      	movs	r2, #0
    1dcc:	2301      	movs	r3, #1
    1dce:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1dd2:	466b      	mov	r3, sp
    1dd4:	4a08      	ldr	r2, [pc, #32]	; (1df8 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1dd6:	f8cd d000 	str.w	sp, [sp]
    1dda:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1dde:	f003 fbd3 	bl	5588 <api_start>
	if (err < 0) {
    1de2:	2800      	cmp	r0, #0
    1de4:	db05      	blt.n	1df2 <api_blocking_start+0x2a>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    1de6:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1dea:	2300      	movs	r3, #0
    1dec:	4668      	mov	r0, sp
    1dee:	f002 fa6d 	bl	42cc <z_impl_k_sem_take>
}
    1df2:	b005      	add	sp, #20
    1df4:	f85d fb04 	ldr.w	pc, [sp], #4
    1df8:	000055cd 	.word	0x000055cd

00001dfc <generic_hfclk_stop>:
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    1dfc:	4b07      	ldr	r3, [pc, #28]	; (1e1c <generic_hfclk_stop+0x20>)
    1dfe:	e8d3 2fef 	ldaex	r2, [r3]
    1e02:	f022 0102 	bic.w	r1, r2, #2
    1e06:	e8c3 1fe0 	stlex	r0, r1, [r3]
    1e0a:	2800      	cmp	r0, #0
    1e0c:	d1f7      	bne.n	1dfe <generic_hfclk_stop+0x2>
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    1e0e:	07d3      	lsls	r3, r2, #31
    1e10:	d402      	bmi.n	1e18 <generic_hfclk_stop+0x1c>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    1e12:	2001      	movs	r0, #1
    1e14:	f004 bb8c 	b.w	6530 <nrfx_clock_stop>
}
    1e18:	4770      	bx	lr
    1e1a:	bf00      	nop
    1e1c:	20000b60 	.word	0x20000b60

00001e20 <z_nrf_clock_control_get_onoff>:
	return &data->mgr[type];
    1e20:	b2c3      	uxtb	r3, r0
}
    1e22:	201c      	movs	r0, #28
    1e24:	4a01      	ldr	r2, [pc, #4]	; (1e2c <z_nrf_clock_control_get_onoff+0xc>)
    1e26:	fb03 2000 	mla	r0, r3, r0, r2
    1e2a:	4770      	bx	lr
    1e2c:	20000ac0 	.word	0x20000ac0

00001e30 <z_nrf_clock_control_lf_on>:
{
    1e30:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1e34:	2201      	movs	r2, #1
    1e36:	4607      	mov	r7, r0
    1e38:	4937      	ldr	r1, [pc, #220]	; (1f18 <z_nrf_clock_control_lf_on+0xe8>)
    1e3a:	e8d1 3fef 	ldaex	r3, [r1]
    1e3e:	e8c1 2fe0 	stlex	r0, r2, [r1]
    1e42:	2800      	cmp	r0, #0
    1e44:	d1f9      	bne.n	1e3a <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
    1e46:	b933      	cbnz	r3, 1e56 <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    1e48:	4934      	ldr	r1, [pc, #208]	; (1f1c <z_nrf_clock_control_lf_on+0xec>)
		err = onoff_request(mgr, &cli);
    1e4a:	4835      	ldr	r0, [pc, #212]	; (1f20 <z_nrf_clock_control_lf_on+0xf0>)
    1e4c:	604b      	str	r3, [r1, #4]
    1e4e:	60cb      	str	r3, [r1, #12]
    1e50:	608a      	str	r2, [r1, #8]
    1e52:	f003 f9ba 	bl	51ca <onoff_request>
	switch (start_mode) {
    1e56:	1e7b      	subs	r3, r7, #1
    1e58:	2b01      	cmp	r3, #1
    1e5a:	d82f      	bhi.n	1ebc <z_nrf_clock_control_lf_on+0x8c>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    1e5c:	2f01      	cmp	r7, #1
    1e5e:	d107      	bne.n	1e70 <z_nrf_clock_control_lf_on+0x40>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    1e60:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1e64:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    1e68:	f003 0303 	and.w	r3, r3, #3
    1e6c:	2b02      	cmp	r3, #2
    1e6e:	d025      	beq.n	1ebc <z_nrf_clock_control_lf_on+0x8c>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1e70:	f004 fc37 	bl	66e2 <k_is_in_isr>
    1e74:	4604      	mov	r4, r0
    1e76:	b918      	cbnz	r0, 1e80 <z_nrf_clock_control_lf_on+0x50>
	return !z_sys_post_kernel;
    1e78:	4b2a      	ldr	r3, [pc, #168]	; (1f24 <z_nrf_clock_control_lf_on+0xf4>)
	int key = isr_mode ? irq_lock() : 0;
    1e7a:	781b      	ldrb	r3, [r3, #0]
    1e7c:	2b00      	cmp	r3, #0
    1e7e:	d144      	bne.n	1f0a <z_nrf_clock_control_lf_on+0xda>
	__asm__ volatile(
    1e80:	f04f 0320 	mov.w	r3, #32
    1e84:	f3ef 8611 	mrs	r6, BASEPRI
    1e88:	f383 8812 	msr	BASEPRI_MAX, r3
    1e8c:	f3bf 8f6f 	isb	sy
    1e90:	2401      	movs	r4, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1e92:	f04f 2550 	mov.w	r5, #1342197760	; 0x50005000
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1e96:	f8df 8090 	ldr.w	r8, [pc, #144]	; 1f28 <z_nrf_clock_control_lf_on+0xf8>
    1e9a:	f8d5 3418 	ldr.w	r3, [r5, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1e9e:	f8d5 2418 	ldr.w	r2, [r5, #1048]	; 0x418
    1ea2:	03d2      	lsls	r2, r2, #15
    1ea4:	d50c      	bpl.n	1ec0 <z_nrf_clock_control_lf_on+0x90>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1ea6:	f003 0303 	and.w	r3, r3, #3
    1eaa:	2b02      	cmp	r3, #2
    1eac:	d001      	beq.n	1eb2 <z_nrf_clock_control_lf_on+0x82>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1eae:	2f01      	cmp	r7, #1
    1eb0:	d106      	bne.n	1ec0 <z_nrf_clock_control_lf_on+0x90>
	if (isr_mode) {
    1eb2:	b324      	cbz	r4, 1efe <z_nrf_clock_control_lf_on+0xce>
	__asm__ volatile(
    1eb4:	f386 8811 	msr	BASEPRI, r6
    1eb8:	f3bf 8f6f 	isb	sy
}
    1ebc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    1ec0:	b1c4      	cbz	r4, 1ef4 <z_nrf_clock_control_lf_on+0xc4>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1ec2:	4630      	mov	r0, r6
    1ec4:	f7ff fa7c 	bl	13c0 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    1ec8:	f8d5 3518 	ldr.w	r3, [r5, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    1ecc:	b2db      	uxtb	r3, r3
    1ece:	2b01      	cmp	r3, #1
    1ed0:	d1e3      	bne.n	1e9a <z_nrf_clock_control_lf_on+0x6a>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1ed2:	f8d5 2104 	ldr.w	r2, [r5, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    1ed6:	2a00      	cmp	r2, #0
    1ed8:	d0df      	beq.n	1e9a <z_nrf_clock_control_lf_on+0x6a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1eda:	2200      	movs	r2, #0
    1edc:	f8c5 2104 	str.w	r2, [r5, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1ee0:	f8d5 2104 	ldr.w	r2, [r5, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    1ee4:	2202      	movs	r2, #2
    1ee6:	f8c5 2518 	str.w	r2, [r5, #1304]	; 0x518
    1eea:	2220      	movs	r2, #32
    1eec:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1ef0:	60ab      	str	r3, [r5, #8]
}
    1ef2:	e7d2      	b.n	1e9a <z_nrf_clock_control_lf_on+0x6a>
	return z_impl_k_sleep(timeout);
    1ef4:	2100      	movs	r1, #0
    1ef6:	2021      	movs	r0, #33	; 0x21
    1ef8:	f002 fce8 	bl	48cc <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1efc:	e7e4      	b.n	1ec8 <z_nrf_clock_control_lf_on+0x98>
    p_reg->INTENSET = mask;
    1efe:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1f02:	2202      	movs	r2, #2
    1f04:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1f08:	e7d8      	b.n	1ebc <z_nrf_clock_control_lf_on+0x8c>
    p_reg->INTENCLR = mask;
    1f0a:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1f0e:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
    1f10:	4606      	mov	r6, r0
    1f12:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    1f16:	e7bc      	b.n	1e92 <z_nrf_clock_control_lf_on+0x62>
    1f18:	20000b64 	.word	0x20000b64
    1f1c:	20000ab0 	.word	0x20000ab0
    1f20:	20000adc 	.word	0x20000adc
    1f24:	20000db1 	.word	0x20000db1
    1f28:	e000e100 	.word	0xe000e100

00001f2c <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    1f2c:	b530      	push	{r4, r5, lr}
	return port->config;
    1f2e:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1f30:	f001 051f 	and.w	r5, r1, #31
    1f34:	7b04      	ldrb	r4, [r0, #12]
	nrfx_err_t err;

	if (mode == GPIO_INT_MODE_DISABLED) {
    1f36:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1f3a:	ea45 1544 	orr.w	r5, r5, r4, lsl #5
{
    1f3e:	b085      	sub	sp, #20
    1f40:	f04f 0400 	mov.w	r4, #0
	if (mode == GPIO_INT_MODE_DISABLED) {
    1f44:	d104      	bne.n	1f50 <gpio_nrfx_pin_interrupt_configure+0x24>
		nrfx_gpiote_trigger_disable(abs_pin);
    1f46:	4628      	mov	r0, r5
    1f48:	f001 fd38 	bl	39bc <nrfx_gpiote_trigger_disable>
		return -EIO;
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
    1f4c:	2000      	movs	r0, #0
    1f4e:	e031      	b.n	1fb4 <gpio_nrfx_pin_interrupt_configure+0x88>
	if (mode == GPIO_INT_MODE_LEVEL) {
    1f50:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    1f54:	e9cd 4402 	strd	r4, r4, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    1f58:	d12e      	bne.n	1fb8 <gpio_nrfx_pin_interrupt_configure+0x8c>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    1f5a:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    1f5e:	bf0c      	ite	eq
    1f60:	2304      	moveq	r3, #4
    1f62:	2305      	movne	r3, #5
	nrfx_gpiote_trigger_config_t trigger_config = {
    1f64:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    1f68:	6883      	ldr	r3, [r0, #8]
    1f6a:	fa23 f101 	lsr.w	r1, r3, r1
    1f6e:	07c9      	lsls	r1, r1, #31
    1f70:	d42e      	bmi.n	1fd0 <gpio_nrfx_pin_interrupt_configure+0xa4>
    1f72:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    1f76:	d12b      	bne.n	1fd0 <gpio_nrfx_pin_interrupt_configure+0xa4>
        case 1: return NRF_P1;
    1f78:	4a1e      	ldr	r2, [pc, #120]	; (1ff4 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    1f7a:	481f      	ldr	r0, [pc, #124]	; (1ff8 <gpio_nrfx_pin_interrupt_configure+0xcc>)
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    1f7c:	0969      	lsrs	r1, r5, #5
        case 1: return NRF_P1;
    1f7e:	2901      	cmp	r1, #1
    1f80:	bf08      	it	eq
    1f82:	4602      	moveq	r2, r0
    *p_pin = pin_number & 0x1F;
    1f84:	f005 031f 	and.w	r3, r5, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    1f88:	3380      	adds	r3, #128	; 0x80
    1f8a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    1f8e:	07db      	lsls	r3, r3, #31
    1f90:	d41e      	bmi.n	1fd0 <gpio_nrfx_pin_interrupt_configure+0xa4>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1f92:	f10d 0407 	add.w	r4, sp, #7
    1f96:	4621      	mov	r1, r4
    1f98:	4628      	mov	r0, r5
    1f9a:	f001 fc75 	bl	3888 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    1f9e:	4b17      	ldr	r3, [pc, #92]	; (1ffc <gpio_nrfx_pin_interrupt_configure+0xd0>)
    1fa0:	4298      	cmp	r0, r3
    1fa2:	d114      	bne.n	1fce <gpio_nrfx_pin_interrupt_configure+0xa2>
			err = nrfx_gpiote_channel_alloc(&ch);
    1fa4:	4620      	mov	r0, r4
    1fa6:	f001 fcbd 	bl	3924 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    1faa:	4b15      	ldr	r3, [pc, #84]	; (2000 <CONFIG_NRF_SPU_RAM_REGION_SIZE>)
    1fac:	4298      	cmp	r0, r3
    1fae:	d00e      	beq.n	1fce <gpio_nrfx_pin_interrupt_configure+0xa2>
				return -ENOMEM;
    1fb0:	f06f 000b 	mvn.w	r0, #11
}
    1fb4:	b005      	add	sp, #20
    1fb6:	bd30      	pop	{r4, r5, pc}
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    1fb8:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    1fbc:	d005      	beq.n	1fca <gpio_nrfx_pin_interrupt_configure+0x9e>
    1fbe:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    1fc2:	bf0c      	ite	eq
    1fc4:	2302      	moveq	r3, #2
    1fc6:	2301      	movne	r3, #1
    1fc8:	e7cc      	b.n	1f64 <gpio_nrfx_pin_interrupt_configure+0x38>
    1fca:	2303      	movs	r3, #3
    1fcc:	e7ca      	b.n	1f64 <gpio_nrfx_pin_interrupt_configure+0x38>
		trigger_config.p_in_channel = &ch;
    1fce:	9403      	str	r4, [sp, #12]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1fd0:	2300      	movs	r3, #0
    1fd2:	4628      	mov	r0, r5
    1fd4:	4619      	mov	r1, r3
    1fd6:	aa02      	add	r2, sp, #8
    1fd8:	f001 fb30 	bl	363c <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1fdc:	4b08      	ldr	r3, [pc, #32]	; (2000 <CONFIG_NRF_SPU_RAM_REGION_SIZE>)
    1fde:	4298      	cmp	r0, r3
    1fe0:	d104      	bne.n	1fec <gpio_nrfx_pin_interrupt_configure+0xc0>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    1fe2:	2101      	movs	r1, #1
    1fe4:	4628      	mov	r0, r5
    1fe6:	f001 fca3 	bl	3930 <nrfx_gpiote_trigger_enable>
    1fea:	e7af      	b.n	1f4c <gpio_nrfx_pin_interrupt_configure+0x20>
		return -EIO;
    1fec:	f06f 0004 	mvn.w	r0, #4
    1ff0:	e7e0      	b.n	1fb4 <gpio_nrfx_pin_interrupt_configure+0x88>
    1ff2:	bf00      	nop
    1ff4:	50842500 	.word	0x50842500
    1ff8:	50842800 	.word	0x50842800
    1ffc:	0bad0004 	.word	0x0bad0004
    2000:	0bad0000 	.word	0x0bad0000

00002004 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    2004:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    2006:	f001 fc7d 	bl	3904 <nrfx_gpiote_is_init>
    200a:	4604      	mov	r4, r0
    200c:	b968      	cbnz	r0, 202a <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    200e:	f001 fc51 	bl	38b4 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    2012:	4b08      	ldr	r3, [pc, #32]	; (2034 <gpio_nrfx_init+0x30>)
    2014:	4298      	cmp	r0, r3
    2016:	d10a      	bne.n	202e <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    2018:	4621      	mov	r1, r4
    201a:	4807      	ldr	r0, [pc, #28]	; (2038 <gpio_nrfx_init+0x34>)
    201c:	f001 fc2e 	bl	387c <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2020:	4622      	mov	r2, r4
    2022:	2101      	movs	r1, #1
    2024:	200d      	movs	r0, #13
    2026:	f7ff fa07 	bl	1438 <z_arm_irq_priority_set>
		return 0;
    202a:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    202c:	bd10      	pop	{r4, pc}
		return -EIO;
    202e:	f06f 0004 	mvn.w	r0, #4
    2032:	e7fb      	b.n	202c <gpio_nrfx_init+0x28>
    2034:	0bad0000 	.word	0x0bad0000
    2038:	0000203d 	.word	0x0000203d

0000203c <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    203c:	0942      	lsrs	r2, r0, #5
{
    203e:	4603      	mov	r3, r0
    2040:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2042:	d002      	beq.n	204a <nrfx_gpio_handler+0xe>
    2044:	2a01      	cmp	r2, #1
    2046:	d015      	beq.n	2074 <nrfx_gpio_handler+0x38>
}
    2048:	bd70      	pop	{r4, r5, r6, pc}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    204a:	4e0b      	ldr	r6, [pc, #44]	; (2078 <nrfx_gpio_handler+0x3c>)
	gpio_fire_callbacks(list, port, BIT(pin));
    204c:	6932      	ldr	r2, [r6, #16]
    204e:	6851      	ldr	r1, [r2, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2050:	2900      	cmp	r1, #0
    2052:	d0f9      	beq.n	2048 <nrfx_gpio_handler+0xc>
    2054:	2501      	movs	r5, #1
    *p_pin = pin_number & 0x1F;
    2056:	f003 031f 	and.w	r3, r3, #31
    205a:	680c      	ldr	r4, [r1, #0]
    205c:	409d      	lsls	r5, r3
		if (cb->pin_mask & pins) {
    205e:	688a      	ldr	r2, [r1, #8]
    2060:	402a      	ands	r2, r5
    2062:	d002      	beq.n	206a <nrfx_gpio_handler+0x2e>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    2064:	4630      	mov	r0, r6
    2066:	684b      	ldr	r3, [r1, #4]
    2068:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    206a:	2c00      	cmp	r4, #0
    206c:	d0ec      	beq.n	2048 <nrfx_gpio_handler+0xc>
    206e:	4621      	mov	r1, r4
    2070:	6824      	ldr	r4, [r4, #0]
    2072:	e7f4      	b.n	205e <nrfx_gpio_handler+0x22>
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2074:	4e01      	ldr	r6, [pc, #4]	; (207c <nrfx_gpio_handler+0x40>)
    2076:	e7e9      	b.n	204c <nrfx_gpio_handler+0x10>
    2078:	00006a04 	.word	0x00006a04
    207c:	00006a1c 	.word	0x00006a1c

00002080 <gpio_nrfx_pin_configure>:
{
    2080:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	return port->config;
    2084:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2086:	f001 051f 	and.w	r5, r1, #31
    208a:	7b3b      	ldrb	r3, [r7, #12]
{
    208c:	460e      	mov	r6, r1
	if (flags == GPIO_DISCONNECTED) {
    208e:	4614      	mov	r4, r2
{
    2090:	b085      	sub	sp, #20
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2092:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
	if (flags == GPIO_DISCONNECTED) {
    2096:	b9ca      	cbnz	r2, 20cc <gpio_nrfx_pin_configure+0x4c>
	err = nrfx_gpiote_channel_get(pin, &ch);
    2098:	a902      	add	r1, sp, #8
    209a:	4628      	mov	r0, r5
    209c:	f001 fbf4 	bl	3888 <nrfx_gpiote_channel_get>
    20a0:	4604      	mov	r4, r0
	err = nrfx_gpiote_pin_uninit(pin);
    20a2:	4628      	mov	r0, r5
    20a4:	f001 fcb2 	bl	3a0c <nrfx_gpiote_pin_uninit>
	if (err != NRFX_SUCCESS) {
    20a8:	4b49      	ldr	r3, [pc, #292]	; (21d0 <gpio_nrfx_pin_configure+0x150>)
    20aa:	4298      	cmp	r0, r3
    20ac:	d004      	beq.n	20b8 <gpio_nrfx_pin_configure+0x38>
		return -EIO;
    20ae:	f06f 0004 	mvn.w	r0, #4
}
    20b2:	b005      	add	sp, #20
    20b4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	if (free_ch) {
    20b8:	4284      	cmp	r4, r0
    20ba:	d105      	bne.n	20c8 <gpio_nrfx_pin_configure+0x48>
		err = nrfx_gpiote_channel_free(ch);
    20bc:	f89d 0008 	ldrb.w	r0, [sp, #8]
    20c0:	f001 fc2a 	bl	3918 <nrfx_gpiote_channel_free>
	return (err != NRFX_SUCCESS) ? -EIO : 0;
    20c4:	42a0      	cmp	r0, r4
    20c6:	d1f2      	bne.n	20ae <gpio_nrfx_pin_configure+0x2e>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    20c8:	2000      	movs	r0, #0
    20ca:	e7f2      	b.n	20b2 <gpio_nrfx_pin_configure+0x32>
	nrfx_gpiote_trigger_config_t trigger_config = {
    20cc:	f04f 0900 	mov.w	r9, #0
	err = nrfx_gpiote_channel_get(pin, &ch);
    20d0:	f10d 0103 	add.w	r1, sp, #3
    20d4:	4630      	mov	r0, r6
	nrfx_gpiote_trigger_config_t trigger_config = {
    20d6:	e9cd 9902 	strd	r9, r9, [sp, #8]
	err = nrfx_gpiote_channel_get(pin, &ch);
    20da:	f001 fbd5 	bl	3888 <nrfx_gpiote_channel_get>
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    20de:	464b      	mov	r3, r9
	err = nrfx_gpiote_channel_get(pin, &ch);
    20e0:	4680      	mov	r8, r0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    20e2:	4649      	mov	r1, r9
    20e4:	4628      	mov	r0, r5
    20e6:	aa02      	add	r2, sp, #8
    20e8:	f001 faa8 	bl	363c <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    20ec:	4b38      	ldr	r3, [pc, #224]	; (21d0 <gpio_nrfx_pin_configure+0x150>)
    20ee:	4298      	cmp	r0, r3
    20f0:	d002      	beq.n	20f8 <gpio_nrfx_pin_configure+0x78>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    20f2:	f06f 0015 	mvn.w	r0, #21
    20f6:	e7dc      	b.n	20b2 <gpio_nrfx_pin_configure+0x32>
	if (free_ch) {
    20f8:	4580      	cmp	r8, r0
    20fa:	d103      	bne.n	2104 <gpio_nrfx_pin_configure+0x84>
		err = nrfx_gpiote_channel_free(ch);
    20fc:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2100:	f001 fc0a 	bl	3918 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    2104:	03a3      	lsls	r3, r4, #14
    2106:	d54f      	bpl.n	21a8 <gpio_nrfx_pin_configure+0x128>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    2108:	f240 6306 	movw	r3, #1542	; 0x606
    210c:	f240 2206 	movw	r2, #518	; 0x206
    2110:	4023      	ands	r3, r4
    2112:	4293      	cmp	r3, r2
    2114:	d03a      	beq.n	218c <gpio_nrfx_pin_configure+0x10c>
    2116:	d80c      	bhi.n	2132 <gpio_nrfx_pin_configure+0xb2>
    2118:	2b06      	cmp	r3, #6
    211a:	d015      	beq.n	2148 <gpio_nrfx_pin_configure+0xc8>
    211c:	d804      	bhi.n	2128 <gpio_nrfx_pin_configure+0xa8>
    211e:	b19b      	cbz	r3, 2148 <gpio_nrfx_pin_configure+0xc8>
    2120:	2b02      	cmp	r3, #2
    2122:	d1e6      	bne.n	20f2 <gpio_nrfx_pin_configure+0x72>
    2124:	2304      	movs	r3, #4
    2126:	e00f      	b.n	2148 <gpio_nrfx_pin_configure+0xc8>
    2128:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    212c:	d1e1      	bne.n	20f2 <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_H0S1;
    212e:	2301      	movs	r3, #1
    2130:	e00a      	b.n	2148 <gpio_nrfx_pin_configure+0xc8>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    2132:	f240 4202 	movw	r2, #1026	; 0x402
    2136:	4293      	cmp	r3, r2
    2138:	d02a      	beq.n	2190 <gpio_nrfx_pin_configure+0x110>
    213a:	f5b3 6fc0 	cmp.w	r3, #1536	; 0x600
    213e:	d029      	beq.n	2194 <gpio_nrfx_pin_configure+0x114>
    2140:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    2144:	d1d5      	bne.n	20f2 <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_S0H1;
    2146:	2302      	movs	r3, #2
		nrfx_gpiote_output_config_t output_config = {
    2148:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    214c:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    2150:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    2154:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    2156:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLUP;
    215a:	bf4c      	ite	mi
    215c:	2303      	movmi	r3, #3
		return NRF_GPIO_PIN_PULLDOWN;
    215e:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    2162:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    2164:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    2168:	d516      	bpl.n	2198 <gpio_nrfx_pin_configure+0x118>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    216a:	2101      	movs	r1, #1
    216c:	687b      	ldr	r3, [r7, #4]
    216e:	fa01 f606 	lsl.w	r6, r1, r6
    p_reg->OUTSET = set_mask;
    2172:	609e      	str	r6, [r3, #8]
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    2174:	2200      	movs	r2, #0
    2176:	4628      	mov	r0, r5
    2178:	a901      	add	r1, sp, #4
    217a:	f001 fb0b 	bl	3794 <nrfx_gpiote_output_configure>
		return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    217e:	4b14      	ldr	r3, [pc, #80]	; (21d0 <gpio_nrfx_pin_configure+0x150>)
    2180:	4298      	cmp	r0, r3
    2182:	bf14      	ite	ne
    2184:	f06f 0015 	mvnne.w	r0, #21
    2188:	2000      	moveq	r0, #0
    218a:	e792      	b.n	20b2 <gpio_nrfx_pin_configure+0x32>
		*drive = NRF_GPIO_PIN_H0D1;
    218c:	2307      	movs	r3, #7
    218e:	e7db      	b.n	2148 <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_D0H1;
    2190:	2305      	movs	r3, #5
    2192:	e7d9      	b.n	2148 <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_H0H1;
    2194:	2303      	movs	r3, #3
    2196:	e7d7      	b.n	2148 <gpio_nrfx_pin_configure+0xc8>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    2198:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    219a:	bf41      	itttt	mi
    219c:	2101      	movmi	r1, #1
    219e:	687b      	ldrmi	r3, [r7, #4]
    21a0:	fa01 f606 	lslmi.w	r6, r1, r6
    p_reg->OUTCLR = clr_mask;
    21a4:	60de      	strmi	r6, [r3, #12]
}
    21a6:	e7e5      	b.n	2174 <gpio_nrfx_pin_configure+0xf4>
	if (flags & GPIO_PULL_UP) {
    21a8:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    21aa:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    21ae:	bf4c      	ite	mi
    21b0:	2403      	movmi	r4, #3
    21b2:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    21b6:	461a      	mov	r2, r3
    21b8:	4628      	mov	r0, r5
    21ba:	a901      	add	r1, sp, #4
	nrfx_gpiote_input_config_t input_config = {
    21bc:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    21c0:	f001 fa3c 	bl	363c <nrfx_gpiote_input_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    21c4:	4b02      	ldr	r3, [pc, #8]	; (21d0 <gpio_nrfx_pin_configure+0x150>)
    21c6:	4298      	cmp	r0, r3
    21c8:	f43f af7e 	beq.w	20c8 <gpio_nrfx_pin_configure+0x48>
    21cc:	e791      	b.n	20f2 <gpio_nrfx_pin_configure+0x72>
    21ce:	bf00      	nop
    21d0:	0bad0000 	.word	0x0bad0000

000021d4 <uarte_nrfx_tx>:
}

static int uarte_nrfx_tx(const struct device *dev, const uint8_t *buf,
			 size_t len,
			 int32_t timeout)
{
    21d4:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    21d8:	461c      	mov	r4, r3
	return config->uarte_regs;
    21da:	6843      	ldr	r3, [r0, #4]
{
    21dc:	460e      	mov	r6, r1
    21de:	4605      	mov	r5, r0
	struct uarte_nrfx_data *data = dev->data;
    21e0:	6907      	ldr	r7, [r0, #16]
	return config->uarte_regs;
    21e2:	6819      	ldr	r1, [r3, #0]
	__asm__ volatile(
    21e4:	f04f 0320 	mov.w	r3, #32
    21e8:	f3ef 8811 	mrs	r8, BASEPRI
    21ec:	f383 8812 	msr	BASEPRI_MAX, r3
    21f0:	f3bf 8f6f 	isb	sy
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	int key = irq_lock();

	if (data->async->tx_size) {
    21f4:	68f8      	ldr	r0, [r7, #12]
    21f6:	68c3      	ldr	r3, [r0, #12]
    21f8:	b143      	cbz	r3, 220c <uarte_nrfx_tx+0x38>
	__asm__ volatile(
    21fa:	f388 8811 	msr	BASEPRI, r8
    21fe:	f3bf 8f6f 	isb	sy
		irq_unlock(key);
		return -EBUSY;
    2202:	f06f 000f 	mvn.w	r0, #15
	    && timeout != SYS_FOREVER_US) {
		k_timer_start(&data->async->tx_timeout_timer, K_USEC(timeout),
			      K_NO_WAIT);
	}
	return 0;
}
    2206:	b002      	add	sp, #8
    2208:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    p_reg->SHORTS &= ~(mask);
}

NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
{
    p_reg->INTENSET = mask;
    220c:	f44f 0c80 	mov.w	ip, #4194304	; 0x400000
	data->async->tx_size = len;
    2210:	60c2      	str	r2, [r0, #12]
	data->async->tx_buf = buf;
    2212:	6086      	str	r6, [r0, #8]
    2214:	f8c1 c304 	str.w	ip, [r1, #772]	; 0x304

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
{
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    2218:	f006 4160 	and.w	r1, r6, #3758096384	; 0xe0000000
	if (nrfx_is_in_ram(buf)) {
    221c:	f1b1 5f00 	cmp.w	r1, #536870912	; 0x20000000
    2220:	d128      	bne.n	2274 <uarte_nrfx_tx+0xa0>
		data->async->xfer_len = len;
    2222:	e9c0 6204 	strd	r6, r2, [r0, #16]
	start_tx_locked(dev, data);
    2226:	4639      	mov	r1, r7
    2228:	4628      	mov	r0, r5
    222a:	f003 fc2f 	bl	5a8c <start_tx_locked>
    222e:	f388 8811 	msr	BASEPRI, r8
    2232:	f3bf 8f6f 	isb	sy
	if (data->uart_config.flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS
    2236:	7afb      	ldrb	r3, [r7, #11]
    2238:	2b01      	cmp	r3, #1
    223a:	d119      	bne.n	2270 <uarte_nrfx_tx+0x9c>
	    && timeout != SYS_FOREVER_US) {
    223c:	1c63      	adds	r3, r4, #1
    223e:	d017      	beq.n	2270 <uarte_nrfx_tx+0x9c>
		k_timer_start(&data->async->tx_timeout_timer, K_USEC(timeout),
    2240:	ea24 75e4 	bic.w	r5, r4, r4, asr #31
			/* Faster algorithm but source is first multiplied by target frequency
			 * and it can overflow even though final result would not overflow.
			 * Kconfig option shall prevent use of this algorithm when there is a
			 * risk of overflow.
			 */
			return ((t * to_hz + off) / from_hz);
    2244:	2400      	movs	r4, #0
    2246:	68fe      	ldr	r6, [r7, #12]
    2248:	4621      	mov	r1, r4
    224a:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    224e:	480b      	ldr	r0, [pc, #44]	; (227c <uarte_nrfx_tx+0xa8>)
    2250:	2300      	movs	r3, #0
    2252:	fbc5 0107 	smlal	r0, r1, r5, r7
    2256:	4a0a      	ldr	r2, [pc, #40]	; (2280 <uarte_nrfx_tx+0xac>)
    2258:	f7fd ff7c 	bl	154 <__aeabi_uldivmod>
    225c:	3628      	adds	r6, #40	; 0x28
    225e:	4602      	mov	r2, r0
    2260:	460b      	mov	r3, r1
	z_impl_k_timer_start(timer, duration, period);
    2262:	2000      	movs	r0, #0
    2264:	2100      	movs	r1, #0
    2266:	e9cd 0100 	strd	r0, r1, [sp]
    226a:	4630      	mov	r0, r6
    226c:	f002 fd38 	bl	4ce0 <z_impl_k_timer_start>
	return 0;
    2270:	2000      	movs	r0, #0
    2272:	e7c8      	b.n	2206 <uarte_nrfx_tx+0x32>
		data->async->tx_cache_offset = 0;
    2274:	6203      	str	r3, [r0, #32]
		(void)setup_tx_cache(data);
    2276:	f003 fbe4 	bl	5a42 <setup_tx_cache.isra.0>
    227a:	e7d4      	b.n	2226 <uarte_nrfx_tx+0x52>
    227c:	000f423f 	.word	0x000f423f
    2280:	000f4240 	.word	0x000f4240

00002284 <uarte_nrfx_configure>:
{
    2284:	b5f0      	push	{r4, r5, r6, r7, lr}
	switch (cfg->stop_bits) {
    2286:	794b      	ldrb	r3, [r1, #5]
    2288:	2b01      	cmp	r3, #1
    228a:	d028      	beq.n	22de <uarte_nrfx_configure+0x5a>
    228c:	2b03      	cmp	r3, #3
    228e:	d123      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    2290:	2710      	movs	r7, #16
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    2292:	798b      	ldrb	r3, [r1, #6]
    2294:	2b03      	cmp	r3, #3
    2296:	d11f      	bne.n	22d8 <uarte_nrfx_configure+0x54>
	switch (cfg->flow_ctrl) {
    2298:	79cd      	ldrb	r5, [r1, #7]
    229a:	b10d      	cbz	r5, 22a0 <uarte_nrfx_configure+0x1c>
    229c:	2d01      	cmp	r5, #1
    229e:	d11b      	bne.n	22d8 <uarte_nrfx_configure+0x54>
	switch (cfg->parity) {
    22a0:	790a      	ldrb	r2, [r1, #4]
    22a2:	2a01      	cmp	r2, #1
    22a4:	d01d      	beq.n	22e2 <uarte_nrfx_configure+0x5e>
    22a6:	2a02      	cmp	r2, #2
    22a8:	d01f      	beq.n	22ea <uarte_nrfx_configure+0x66>
    22aa:	b9aa      	cbnz	r2, 22d8 <uarte_nrfx_configure+0x54>
    22ac:	4614      	mov	r4, r2
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    22ae:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    22b0:	6846      	ldr	r6, [r0, #4]
	switch (baudrate) {
    22b2:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    22b6:	6836      	ldr	r6, [r6, #0]
	switch (baudrate) {
    22b8:	d06e      	beq.n	2398 <uarte_nrfx_configure+0x114>
    22ba:	d833      	bhi.n	2324 <uarte_nrfx_configure+0xa0>
    22bc:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    22c0:	d06d      	beq.n	239e <uarte_nrfx_configure+0x11a>
    22c2:	d81c      	bhi.n	22fe <uarte_nrfx_configure+0x7a>
    22c4:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    22c8:	d06b      	beq.n	23a2 <uarte_nrfx_configure+0x11e>
    22ca:	d810      	bhi.n	22ee <uarte_nrfx_configure+0x6a>
    22cc:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    22d0:	d06a      	beq.n	23a8 <uarte_nrfx_configure+0x124>
    22d2:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    22d6:	d06a      	beq.n	23ae <uarte_nrfx_configure+0x12a>
    22d8:	f06f 0085 	mvn.w	r0, #133	; 0x85
    22dc:	e05b      	b.n	2396 <uarte_nrfx_configure+0x112>
	switch (cfg->stop_bits) {
    22de:	2700      	movs	r7, #0
    22e0:	e7d7      	b.n	2292 <uarte_nrfx_configure+0xe>
		uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
    22e2:	f44f 7480 	mov.w	r4, #256	; 0x100
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    22e6:	220e      	movs	r2, #14
    22e8:	e7e1      	b.n	22ae <uarte_nrfx_configure+0x2a>
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
    22ea:	2400      	movs	r4, #0
    22ec:	e7fb      	b.n	22e6 <uarte_nrfx_configure+0x62>
	switch (baudrate) {
    22ee:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    22f2:	d05f      	beq.n	23b4 <uarte_nrfx_configure+0x130>
    22f4:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    22f8:	d1ee      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    22fa:	4b39      	ldr	r3, [pc, #228]	; (23e0 <uarte_nrfx_configure+0x15c>)
    22fc:	e03e      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    22fe:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    2302:	d05a      	beq.n	23ba <uarte_nrfx_configure+0x136>
    2304:	d807      	bhi.n	2316 <uarte_nrfx_configure+0x92>
    2306:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    230a:	d058      	beq.n	23be <uarte_nrfx_configure+0x13a>
    230c:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    2310:	d1e2      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    2312:	4b34      	ldr	r3, [pc, #208]	; (23e4 <uarte_nrfx_configure+0x160>)
    2314:	e032      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    2316:	f647 2c12 	movw	ip, #31250	; 0x7a12
    231a:	4563      	cmp	r3, ip
    231c:	d1dc      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    231e:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    2322:	e02b      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    2324:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    2328:	d04b      	beq.n	23c2 <uarte_nrfx_configure+0x13e>
    232a:	d813      	bhi.n	2354 <uarte_nrfx_configure+0xd0>
    232c:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    2330:	d04a      	beq.n	23c8 <uarte_nrfx_configure+0x144>
    2332:	d809      	bhi.n	2348 <uarte_nrfx_configure+0xc4>
    2334:	f64d 2cc0 	movw	ip, #56000	; 0xdac0
    2338:	4563      	cmp	r3, ip
    233a:	d047      	beq.n	23cc <uarte_nrfx_configure+0x148>
    233c:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    2340:	d1ca      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    2342:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    2346:	e019      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    2348:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    234c:	d1c4      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    234e:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    2352:	e013      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    2354:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    2358:	d03b      	beq.n	23d2 <uarte_nrfx_configure+0x14e>
    235a:	d809      	bhi.n	2370 <uarte_nrfx_configure+0xec>
    235c:	f8df c088 	ldr.w	ip, [pc, #136]	; 23e8 <uarte_nrfx_configure+0x164>
    2360:	4563      	cmp	r3, ip
    2362:	d039      	beq.n	23d8 <uarte_nrfx_configure+0x154>
    2364:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    2368:	d1b6      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    236a:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    236e:	e005      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    2370:	f8df c078 	ldr.w	ip, [pc, #120]	; 23ec <uarte_nrfx_configure+0x168>
    2374:	4563      	cmp	r3, ip
    2376:	d1af      	bne.n	22d8 <uarte_nrfx_configure+0x54>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2378:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    237c:	6900      	ldr	r0, [r0, #16]
                    | (uint32_t)p_cfg->stop
#endif
#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
                    | (uint32_t)p_cfg->paritytype
#endif
                    | (uint32_t)p_cfg->hwfc;
    237e:	432c      	orrs	r4, r5
                    | (uint32_t)p_cfg->stop
    2380:	433a      	orrs	r2, r7
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    2382:	f8c6 3524 	str.w	r3, [r6, #1316]	; 0x524
                    | (uint32_t)p_cfg->hwfc;
    2386:	4322      	orrs	r2, r4
	data->uart_config = *cfg;
    2388:	1d03      	adds	r3, r0, #4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    238a:	f8c6 256c 	str.w	r2, [r6, #1388]	; 0x56c
    238e:	c903      	ldmia	r1, {r0, r1}
    2390:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    2394:	2000      	movs	r0, #0
}
    2396:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    2398:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    239c:	e7ee      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    239e:	4b14      	ldr	r3, [pc, #80]	; (23f0 <uarte_nrfx_configure+0x16c>)
    23a0:	e7ec      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    23a2:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    23a6:	e7e9      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = 0x00014000;
    23a8:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    23ac:	e7e6      	b.n	237c <uarte_nrfx_configure+0xf8>
	switch (baudrate) {
    23ae:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    23b2:	e7e3      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    23b4:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    23b8:	e7e0      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    23ba:	4b0e      	ldr	r3, [pc, #56]	; (23f4 <uarte_nrfx_configure+0x170>)
    23bc:	e7de      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    23be:	4b0e      	ldr	r3, [pc, #56]	; (23f8 <uarte_nrfx_configure+0x174>)
    23c0:	e7dc      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    23c2:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    23c6:	e7d9      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    23c8:	4b0c      	ldr	r3, [pc, #48]	; (23fc <uarte_nrfx_configure+0x178>)
    23ca:	e7d7      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    23cc:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    23d0:	e7d4      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    23d2:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    23d6:	e7d1      	b.n	237c <uarte_nrfx_configure+0xf8>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    23d8:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    23dc:	e7ce      	b.n	237c <uarte_nrfx_configure+0xf8>
    23de:	bf00      	nop
    23e0:	0013b000 	.word	0x0013b000
    23e4:	004ea000 	.word	0x004ea000
    23e8:	0003d090 	.word	0x0003d090
    23ec:	000f4240 	.word	0x000f4240
    23f0:	00275000 	.word	0x00275000
    23f4:	0075c000 	.word	0x0075c000
    23f8:	003af000 	.word	0x003af000
    23fc:	013a9000 	.word	0x013a9000

00002400 <uarte_1_init>:
#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    2400:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2404:	4605      	mov	r5, r0
    2406:	2200      	movs	r2, #0
    2408:	2101      	movs	r1, #1
    240a:	2009      	movs	r0, #9
    240c:	f7ff f814 	bl	1438 <z_arm_irq_priority_set>
    2410:	2009      	movs	r0, #9
    2412:	f7fe ffdf 	bl	13d4 <arch_irq_enable>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2416:	2100      	movs	r1, #0
	const struct uarte_nrfx_config *config = dev->config;
    2418:	f8d5 9004 	ldr.w	r9, [r5, #4]
	struct uarte_nrfx_data *data = dev->data;
    241c:	f8d5 8010 	ldr.w	r8, [r5, #16]
	return config->uarte_regs;
    2420:	f8d9 4000 	ldr.w	r4, [r9]
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    2424:	f8d9 700c 	ldr.w	r7, [r9, #12]
    2428:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    242c:	466a      	mov	r2, sp
    242e:	4638      	mov	r0, r7
	data->dev = dev;
    2430:	f8c8 5000 	str.w	r5, [r8]
    2434:	f003 febc 	bl	61b0 <pinctrl_lookup_state>
	if (ret < 0) {
    2438:	1e06      	subs	r6, r0, #0
    243a:	db1b      	blt.n	2474 <uarte_1_init+0x74>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    243c:	9b00      	ldr	r3, [sp, #0]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    243e:	683a      	ldr	r2, [r7, #0]
    2440:	7919      	ldrb	r1, [r3, #4]
    2442:	6818      	ldr	r0, [r3, #0]
    2444:	f003 fed1 	bl	61ea <pinctrl_configure_pins>
	if (err < 0) {
    2448:	1e06      	subs	r6, r0, #0
    244a:	db13      	blt.n	2474 <uarte_1_init+0x74>
	err = uarte_nrfx_configure(dev, &data->uart_config);
    244c:	4628      	mov	r0, r5
    244e:	f108 0104 	add.w	r1, r8, #4
    2452:	f7ff ff17 	bl	2284 <uarte_nrfx_configure>
	if (err) {
    2456:	4606      	mov	r6, r0
    2458:	b960      	cbnz	r0, 2474 <uarte_1_init+0x74>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    245a:	f8d9 3004 	ldr.w	r3, [r9, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    245e:	0798      	lsls	r0, r3, #30
    2460:	d519      	bpl.n	2496 <uarte_1_init+0x96>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    2462:	f108 0016 	add.w	r0, r8, #22
    2466:	f001 f849 	bl	34fc <nrfx_dppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    246a:	4b66      	ldr	r3, [pc, #408]	; (2604 <uarte_1_init+0x204>)
    246c:	4298      	cmp	r0, r3
    246e:	d005      	beq.n	247c <uarte_1_init+0x7c>
		return -EIO;
    2470:	f06f 0604 	mvn.w	r6, #4
UART_NRF_UARTE_DEVICE(1);
    2474:	4630      	mov	r0, r6
    2476:	b003      	add	sp, #12
    2478:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    247c:	f898 2016 	ldrb.w	r2, [r8, #22]
}

__STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
{
    NRFX_ASSERT(eep);
    *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2480:	f042 4300 	orr.w	r3, r2, #2147483648	; 0x80000000
    2484:	f8c4 31a0 	str.w	r3, [r4, #416]	; 0x1a0
}

__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
{
    NRFX_ASSERT(tep);
    *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2488:	f8c4 308c 	str.w	r3, [r4, #140]	; 0x8c
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    248c:	2301      	movs	r3, #1
    248e:	4093      	lsls	r3, r2
    p_reg->CHENCLR = 0xFFFFFFFFuL;
}

NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
    p_reg->CHENSET = mask;
    2490:	4a5d      	ldr	r2, [pc, #372]	; (2608 <uarte_1_init+0x208>)
    2492:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
	if (data->async) {
    2496:	f8d8 300c 	ldr.w	r3, [r8, #12]
    249a:	2b00      	cmp	r3, #0
    249c:	f000 809d 	beq.w	25da <uarte_1_init+0x1da>
	struct uarte_nrfx_data *data = dev->data;
    24a0:	692f      	ldr	r7, [r5, #16]
	const struct uarte_nrfx_config *config = dev->config;
    24a2:	f8d5 a004 	ldr.w	sl, [r5, #4]
	if (HW_RX_COUNTING_ENABLED(data)) {
    24a6:	68fb      	ldr	r3, [r7, #12]
	return config->uarte_regs;
    24a8:	f8da 5000 	ldr.w	r5, [sl]
	if (HW_RX_COUNTING_ENABLED(data)) {
    24ac:	f893 30d3 	ldrb.w	r3, [r3, #211]	; 0xd3
    24b0:	b18b      	cbz	r3, 24d6 <uarte_1_init+0xd6>
		nrfx_timer_config_t tmr_config = NRFX_TIMER_DEFAULT_CONFIG;
    24b2:	2300      	movs	r3, #0
    24b4:	4955      	ldr	r1, [pc, #340]	; (260c <uarte_1_init+0x20c>)
		ret = nrfx_timer_init(&cfg->timer,
    24b6:	f10a 0b10 	add.w	fp, sl, #16
		nrfx_timer_config_t tmr_config = NRFX_TIMER_DEFAULT_CONFIG;
    24ba:	e9cd 1300 	strd	r1, r3, [sp]
		ret = nrfx_timer_init(&cfg->timer,
    24be:	4a54      	ldr	r2, [pc, #336]	; (2610 <uarte_1_init+0x210>)
    24c0:	4669      	mov	r1, sp
    24c2:	4658      	mov	r0, fp
    24c4:	f001 fb9c 	bl	3c00 <nrfx_timer_init>
		if (ret != NRFX_SUCCESS) {
    24c8:	4a4e      	ldr	r2, [pc, #312]	; (2604 <uarte_1_init+0x204>)
    24ca:	4290      	cmp	r0, r2
    24cc:	d07a      	beq.n	25c4 <uarte_1_init+0x1c4>
			data->async->hw_rx_counting = false;
    24ce:	2300      	movs	r3, #0
    24d0:	68fa      	ldr	r2, [r7, #12]
    24d2:	f882 30d3 	strb.w	r3, [r2, #211]	; 0xd3
	if (HW_RX_COUNTING_ENABLED(data)) {
    24d6:	68f8      	ldr	r0, [r7, #12]
    24d8:	f890 30d3 	ldrb.w	r3, [r0, #211]	; 0xd3
    24dc:	b16b      	cbz	r3, 24fa <uarte_1_init+0xfa>
		ret = gppi_channel_alloc(&data->async->rx_cnt.ppi);
    24de:	30c0      	adds	r0, #192	; 0xc0
    24e0:	f001 f80c 	bl	34fc <nrfx_dppi_channel_alloc>
		if (ret != NRFX_SUCCESS) {
    24e4:	4b47      	ldr	r3, [pc, #284]	; (2604 <uarte_1_init+0x204>)
    24e6:	4298      	cmp	r0, r3
    24e8:	d007      	beq.n	24fa <uarte_1_init+0xfa>
			data->async->hw_rx_counting = false;
    24ea:	2200      	movs	r2, #0
    24ec:	68fb      	ldr	r3, [r7, #12]
			nrfx_timer_uninit(&cfg->timer);
    24ee:	f10a 0010 	add.w	r0, sl, #16
			data->async->hw_rx_counting = false;
    24f2:	f883 20d3 	strb.w	r2, [r3, #211]	; 0xd3
			nrfx_timer_uninit(&cfg->timer);
    24f6:	f001 fbeb 	bl	3cd0 <nrfx_timer_uninit>
	if (HW_RX_COUNTING_ENABLED(data)) {
    24fa:	68fb      	ldr	r3, [r7, #12]
    24fc:	f893 20d3 	ldrb.w	r2, [r3, #211]	; 0xd3
    2500:	2a00      	cmp	r2, #0
    2502:	d066      	beq.n	25d2 <uarte_1_init+0x1d2>
            ((uint32_t)channel | UARTE_PUBLISH_CTS_EN_Msk);
    2504:	f893 20c0 	ldrb.w	r2, [r3, #192]	; 0xc0
		nrf_timer_subscribe_set(cfg->timer.p_reg,
    2508:	f8da 1010 	ldr.w	r1, [sl, #16]
    250c:	f042 4200 	orr.w	r2, r2, #2147483648	; 0x80000000
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
    2510:	f8c5 2188 	str.w	r2, [r5, #392]	; 0x188
NRF_STATIC_INLINE void nrf_timer_subscribe_set(NRF_TIMER_Type * p_reg,
                                               nrf_timer_task_t task,
                                               uint8_t          channel)
{
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
            ((uint32_t)channel | TIMER_SUBSCRIBE_START_EN_Msk);
    2514:	f893 20c0 	ldrb.w	r2, [r3, #192]	; 0xc0
    2518:	f042 4200 	orr.w	r2, r2, #2147483648	; 0x80000000
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
    251c:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
		ret = gppi_channel_enable(data->async->rx_cnt.ppi);
    2520:	f893 00c0 	ldrb.w	r0, [r3, #192]	; 0xc0
    2524:	f000 fff0 	bl	3508 <nrfx_dppi_channel_enable>
		if (ret != NRFX_SUCCESS) {
    2528:	4b36      	ldr	r3, [pc, #216]	; (2604 <uarte_1_init+0x204>)
    252a:	4298      	cmp	r0, r3
    252c:	d1a0      	bne.n	2470 <uarte_1_init+0x70>
	data->async->low_power_mask = UARTE_LOW_POWER_TX;
    252e:	2301      	movs	r3, #1
    2530:	68f8      	ldr	r0, [r7, #12]
    p_reg->INTENSET = mask;
    2532:	4a38      	ldr	r2, [pc, #224]	; (2614 <uarte_1_init+0x214>)
    2534:	f8c0 30c8 	str.w	r3, [r0, #200]	; 0xc8
    2538:	f8c5 2304 	str.w	r2, [r5, #772]	; 0x304
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    253c:	2208      	movs	r2, #8
    253e:	f8c5 2500 	str.w	r2, [r5, #1280]	; 0x500
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2542:	f8d5 214c 	ldr.w	r2, [r5, #332]	; 0x14c
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED)) {
    2546:	b1a2      	cbz	r2, 2572 <uarte_1_init+0x172>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2548:	606b      	str	r3, [r5, #4]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    254a:	f8d5 3144 	ldr.w	r3, [r5, #324]	; 0x144
		while (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXTO) &&
    254e:	b91b      	cbnz	r3, 2558 <uarte_1_init+0x158>
    2550:	f8d5 3124 	ldr.w	r3, [r5, #292]	; 0x124
    2554:	2b00      	cmp	r3, #0
    2556:	d0f8      	beq.n	254a <uarte_1_init+0x14a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2558:	2300      	movs	r3, #0
    255a:	f8c5 314c 	str.w	r3, [r5, #332]	; 0x14c
    255e:	f8d5 214c 	ldr.w	r2, [r5, #332]	; 0x14c
    2562:	f8c5 3110 	str.w	r3, [r5, #272]	; 0x110
    2566:	f8d5 2110 	ldr.w	r2, [r5, #272]	; 0x110
    256a:	f8c5 3144 	str.w	r3, [r5, #324]	; 0x144
    256e:	f8d5 3144 	ldr.w	r3, [r5, #324]	; 0x144
	k_timer_init(&data->async->rx_timeout_timer, rx_timeout, NULL);
    2572:	2200      	movs	r2, #0
    2574:	4928      	ldr	r1, [pc, #160]	; (2618 <uarte_1_init+0x218>)
    2576:	3088      	adds	r0, #136	; 0x88
    2578:	f004 f9de 	bl	6938 <k_timer_init>
	k_timer_user_data_set(&data->async->rx_timeout_timer, data);
    257c:	68fb      	ldr	r3, [r7, #12]
	k_timer_init(&data->async->tx_timeout_timer, tx_timeout, NULL);
    257e:	68f8      	ldr	r0, [r7, #12]
	timer->user_data = user_data;
    2580:	f8c3 70bc 	str.w	r7, [r3, #188]	; 0xbc
    2584:	2200      	movs	r2, #0
    2586:	4925      	ldr	r1, [pc, #148]	; (261c <uarte_1_init+0x21c>)
    2588:	3028      	adds	r0, #40	; 0x28
    258a:	f004 f9d5 	bl	6938 <k_timer_init>
	k_timer_user_data_set(&data->async->tx_timeout_timer, data);
    258e:	68fb      	ldr	r3, [r7, #12]
    2590:	65df      	str	r7, [r3, #92]	; 0x5c
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    2592:	f8d9 3004 	ldr.w	r3, [r9, #4]
    2596:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    2598:	bf5c      	itt	pl
    259a:	f44f 7280 	movpl.w	r2, #256	; 0x100
    259e:	f8c4 2304 	strpl.w	r2, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    25a2:	06db      	lsls	r3, r3, #27
    25a4:	bf44      	itt	mi
    25a6:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    25aa:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    25ae:	f108 0314 	add.w	r3, r8, #20

NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t  const * p_buffer,
                                               size_t           length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    25b2:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    25b6:	2300      	movs	r3, #0
    25b8:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    25bc:	2301      	movs	r3, #1
    25be:	60a3      	str	r3, [r4, #8]
    25c0:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(1);
    25c2:	e757      	b.n	2474 <uarte_1_init+0x74>
			nrfx_timer_enable(&cfg->timer);
    25c4:	4658      	mov	r0, fp
    25c6:	f001 fb69 	bl	3c9c <nrfx_timer_enable>
			nrfx_timer_clear(&cfg->timer);
    25ca:	4658      	mov	r0, fp
    25cc:	f004 f808 	bl	65e0 <nrfx_timer_clear>
    25d0:	e781      	b.n	24d6 <uarte_1_init+0xd6>
    p_reg->INTENSET = mask;
    25d2:	2304      	movs	r3, #4
    25d4:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
	if (ret != 0) {
    25d8:	e7a9      	b.n	252e <uarte_1_init+0x12e>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    25da:	2308      	movs	r3, #8
    25dc:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    25e0:	f899 3008 	ldrb.w	r3, [r9, #8]
    25e4:	2b00      	cmp	r3, #0
    25e6:	d1d4      	bne.n	2592 <uarte_1_init+0x192>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    25e8:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    25ec:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    25f0:	f108 0315 	add.w	r3, r8, #21

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    25f4:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    25f8:	2301      	movs	r3, #1
    25fa:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    25fe:	6023      	str	r3, [r4, #0]
}
    2600:	e7c7      	b.n	2592 <uarte_1_init+0x192>
    2602:	bf00      	nop
    2604:	0bad0000 	.word	0x0bad0000
    2608:	50017000 	.word	0x50017000
    260c:	07030100 	.word	0x07030100
    2610:	00005685 	.word	0x00005685
    2614:	000a0210 	.word	0x000a0210
    2618:	00005abf 	.word	0x00005abf
    261c:	00005b93 	.word	0x00005b93

00002620 <uarte_nrfx_poll_out>:
{
    2620:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2622:	4604      	mov	r4, r0
    2624:	460f      	mov	r7, r1
	struct uarte_nrfx_data *data = dev->data;
    2626:	6906      	ldr	r6, [r0, #16]
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2628:	f004 f85b 	bl	66e2 <k_is_in_isr>
    262c:	b910      	cbnz	r0, 2634 <uarte_nrfx_poll_out+0x14>
	return !z_sys_post_kernel;
    262e:	4b28      	ldr	r3, [pc, #160]	; (26d0 <uarte_nrfx_poll_out+0xb0>)
	if (isr_mode) {
    2630:	781b      	ldrb	r3, [r3, #0]
    2632:	bb5b      	cbnz	r3, 268c <uarte_nrfx_poll_out+0x6c>
	__asm__ volatile(
    2634:	f04f 0320 	mov.w	r3, #32
    2638:	f3ef 8111 	mrs	r1, BASEPRI
    263c:	f383 8812 	msr	BASEPRI_MAX, r3
    2640:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    2644:	6860      	ldr	r0, [r4, #4]
			key = irq_lock();
    2646:	460d      	mov	r5, r1
			if (is_tx_ready(dev)) {
    2648:	f003 fa10 	bl	5a6c <is_tx_ready.isra.0>
    264c:	b1c8      	cbz	r0, 2682 <uarte_nrfx_poll_out+0x62>
				if (data->async && data->async->tx_size &&
    264e:	68f3      	ldr	r3, [r6, #12]
    2650:	b15b      	cbz	r3, 266a <uarte_nrfx_poll_out+0x4a>
    2652:	68da      	ldr	r2, [r3, #12]
    2654:	b14a      	cbz	r2, 266a <uarte_nrfx_poll_out+0x4a>
					data->async->tx_amount < 0) {
    2656:	f8d3 20c4 	ldr.w	r2, [r3, #196]	; 0xc4
				if (data->async && data->async->tx_size &&
    265a:	2a00      	cmp	r2, #0
    265c:	da05      	bge.n	266a <uarte_nrfx_poll_out+0x4a>
	return config->uarte_regs;
    265e:	6862      	ldr	r2, [r4, #4]
    2660:	6812      	ldr	r2, [r2, #0]
    return p_reg->TXD.AMOUNT;
    2662:	f8d2 254c 	ldr.w	r2, [r2, #1356]	; 0x54c
					data->async->tx_amount =
    2666:	f8c3 20c4 	str.w	r2, [r3, #196]	; 0xc4
	data->char_out = c;
    266a:	4631      	mov	r1, r6
	tx_start(dev, &data->char_out, 1);
    266c:	2201      	movs	r2, #1
    266e:	4620      	mov	r0, r4
	data->char_out = c;
    2670:	f801 7f14 	strb.w	r7, [r1, #20]!
	tx_start(dev, &data->char_out, 1);
    2674:	f003 f8bf 	bl	57f6 <tx_start>
	__asm__ volatile(
    2678:	f385 8811 	msr	BASEPRI, r5
    267c:	f3bf 8f6f 	isb	sy
}
    2680:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2682:	f381 8811 	msr	BASEPRI, r1
    2686:	f3bf 8f6f 	isb	sy
}
    268a:	e7d3      	b.n	2634 <uarte_nrfx_poll_out+0x14>
{
    268c:	2564      	movs	r5, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    268e:	6860      	ldr	r0, [r4, #4]
    2690:	f003 f9ec 	bl	5a6c <is_tx_ready.isra.0>
    2694:	b948      	cbnz	r0, 26aa <uarte_nrfx_poll_out+0x8a>
    2696:	2001      	movs	r0, #1
    2698:	f003 fe56 	bl	6348 <nrfx_busy_wait>
    269c:	3d01      	subs	r5, #1
    269e:	d1f6      	bne.n	268e <uarte_nrfx_poll_out+0x6e>
	return z_impl_k_sleep(timeout);
    26a0:	2100      	movs	r1, #0
    26a2:	2021      	movs	r0, #33	; 0x21
    26a4:	f002 f912 	bl	48cc <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    26a8:	e7f0      	b.n	268c <uarte_nrfx_poll_out+0x6c>
	__asm__ volatile(
    26aa:	f04f 0320 	mov.w	r3, #32
    26ae:	f3ef 8511 	mrs	r5, BASEPRI
    26b2:	f383 8812 	msr	BASEPRI_MAX, r3
    26b6:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    26ba:	6860      	ldr	r0, [r4, #4]
    26bc:	f003 f9d6 	bl	5a6c <is_tx_ready.isra.0>
    26c0:	2800      	cmp	r0, #0
    26c2:	d1d2      	bne.n	266a <uarte_nrfx_poll_out+0x4a>
	__asm__ volatile(
    26c4:	f385 8811 	msr	BASEPRI, r5
    26c8:	f3bf 8f6f 	isb	sy
}
    26cc:	e7e8      	b.n	26a0 <uarte_nrfx_poll_out+0x80>
    26ce:	bf00      	nop
    26d0:	20000db1 	.word	0x20000db1

000026d4 <uarte_nrfx_isr_async>:
	return config->uarte_regs;
    26d4:	6843      	ldr	r3, [r0, #4]
{
    26d6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return config->uarte_regs;
    26da:	681d      	ldr	r5, [r3, #0]
	if (!HW_RX_COUNTING_ENABLED(data)
    26dc:	6903      	ldr	r3, [r0, #16]
{
    26de:	4604      	mov	r4, r0
	if (!HW_RX_COUNTING_ENABLED(data)
    26e0:	68db      	ldr	r3, [r3, #12]
{
    26e2:	b088      	sub	sp, #32
	if (!HW_RX_COUNTING_ENABLED(data)
    26e4:	f893 20d3 	ldrb.w	r2, [r3, #211]	; 0xd3
    26e8:	b972      	cbnz	r2, 2708 <uarte_nrfx_isr_async+0x34>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    26ea:	f8d5 1108 	ldr.w	r1, [r5, #264]	; 0x108
	    && nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXDRDY)) {
    26ee:	b159      	cbz	r1, 2708 <uarte_nrfx_isr_async+0x34>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    26f0:	f8c5 2108 	str.w	r2, [r5, #264]	; 0x108
    26f4:	f8d5 2108 	ldr.w	r2, [r5, #264]	; 0x108
		data->async->rx_cnt.cnt++;
    26f8:	f8d3 20c0 	ldr.w	r2, [r3, #192]	; 0xc0
    26fc:	3201      	adds	r2, #1
    26fe:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
}
    2702:	b008      	add	sp, #32
    2704:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2708:	f8d5 3124 	ldr.w	r3, [r5, #292]	; 0x124
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ERROR)) {
    270c:	b31b      	cbz	r3, 2756 <uarte_nrfx_isr_async+0x82>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    270e:	2100      	movs	r1, #0
    2710:	f8c5 1124 	str.w	r1, [r5, #292]	; 0x124
    2714:	f8d5 3124 	ldr.w	r3, [r5, #292]	; 0x124
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    2718:	f8d5 6480 	ldr.w	r6, [r5, #1152]	; 0x480
	struct uart_event evt = {
    271c:	2214      	movs	r2, #20
    p_reg->ERRORSRC = errsrc_mask;
    271e:	f8c5 6480 	str.w	r6, [r5, #1152]	; 0x480
    2722:	a803      	add	r0, sp, #12
    2724:	f002 feae 	bl	5484 <memset>
    2728:	2306      	movs	r3, #6
    272a:	f88d 300c 	strb.w	r3, [sp, #12]
		.data.rx_stop.reason = UARTE_ERROR_FROM_MASK(err),
    272e:	07f3      	lsls	r3, r6, #31
    2730:	f100 8100 	bmi.w	2934 <uarte_nrfx_isr_async+0x260>
    2734:	07b7      	lsls	r7, r6, #30
    2736:	f100 80ff 	bmi.w	2938 <uarte_nrfx_isr_async+0x264>
    273a:	0770      	lsls	r0, r6, #29
    273c:	f100 80fe 	bmi.w	293c <uarte_nrfx_isr_async+0x268>
    2740:	f006 0608 	and.w	r6, r6, #8
	user_callback(dev, &evt);
    2744:	4620      	mov	r0, r4
    2746:	a903      	add	r1, sp, #12
	struct uart_event evt = {
    2748:	f88d 6010 	strb.w	r6, [sp, #16]
	user_callback(dev, &evt);
    274c:	f002 ff9b 	bl	5686 <user_callback>
	(void) uarte_nrfx_rx_disable(dev);
    2750:	4620      	mov	r0, r4
    2752:	f003 f86d 	bl	5830 <uarte_nrfx_rx_disable>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2756:	f8d5 3110 	ldr.w	r3, [r5, #272]	; 0x110
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)
    275a:	b37b      	cbz	r3, 27bc <uarte_nrfx_isr_async+0xe8>
    return p_reg->INTENSET & mask;
    275c:	f8d5 3304 	ldr.w	r3, [r5, #772]	; 0x304
	    && nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDRX_MASK)) {
    2760:	06d9      	lsls	r1, r3, #27
    2762:	d52b      	bpl.n	27bc <uarte_nrfx_isr_async+0xe8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2764:	f04f 0800 	mov.w	r8, #0
    2768:	f8c5 8110 	str.w	r8, [r5, #272]	; 0x110
    276c:	f8d5 3110 	ldr.w	r3, [r5, #272]	; 0x110
	return config->uarte_regs;
    2770:	6863      	ldr	r3, [r4, #4]
	struct uarte_nrfx_data *data = dev->data;
    2772:	6927      	ldr	r7, [r4, #16]
	return config->uarte_regs;
    2774:	681e      	ldr	r6, [r3, #0]
	data->async->is_in_irq = true;
    2776:	2301      	movs	r3, #1
    2778:	68f8      	ldr	r0, [r7, #12]
    277a:	f880 30d5 	strb.w	r3, [r0, #213]	; 0xd5
	z_impl_k_timer_stop(timer);
    277e:	3088      	adds	r0, #136	; 0x88
    2780:	f004 f8e6 	bl	6950 <z_impl_k_timer_stop>
				data->async->rx_flush_cnt;
    2784:	68fa      	ldr	r2, [r7, #12]
}

NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
{
    return p_reg->RXD.AMOUNT;
    2786:	f8d6 153c 	ldr.w	r1, [r6, #1340]	; 0x53c
    278a:	f892 30d1 	ldrb.w	r3, [r2, #209]	; 0xd1
	int rx_len = rx_amount - data->async->rx_offset;
    278e:	6e90      	ldr	r0, [r2, #104]	; 0x68
	data->async->rx_flush_cnt = 0;
    2790:	f882 80d1 	strb.w	r8, [r2, #209]	; 0xd1
	int rx_len = rx_amount - data->async->rx_offset;
    2794:	1a1b      	subs	r3, r3, r0
    2796:	440b      	add	r3, r1
	data->async->rx_total_user_byte_cnt += rx_len;
    2798:	6f90      	ldr	r0, [r2, #120]	; 0x78
    279a:	ea23 71e3 	bic.w	r1, r3, r3, asr #31
    279e:	4408      	add	r0, r1
	if (rx_len > 0) {
    27a0:	4543      	cmp	r3, r8
	data->async->rx_total_user_byte_cnt += rx_len;
    27a2:	6790      	str	r0, [r2, #120]	; 0x78
	if (rx_len > 0) {
    27a4:	dd02      	ble.n	27ac <uarte_nrfx_isr_async+0xd8>
		notify_uart_rx_rdy(dev, rx_len);
    27a6:	4620      	mov	r0, r4
    27a8:	f002 ff74 	bl	5694 <notify_uart_rx_rdy>
	if (!data->async->rx_enabled) {
    27ac:	68f9      	ldr	r1, [r7, #12]
    27ae:	f891 30d2 	ldrb.w	r3, [r1, #210]	; 0xd2
    27b2:	2b00      	cmp	r3, #0
    27b4:	f040 80c4 	bne.w	2940 <uarte_nrfx_isr_async+0x26c>
		data->async->is_in_irq = false;
    27b8:	f881 30d5 	strb.w	r3, [r1, #213]	; 0xd5
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    27bc:	f8d5 314c 	ldr.w	r3, [r5, #332]	; 0x14c
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED) &&
    27c0:	b37b      	cbz	r3, 2822 <uarte_nrfx_isr_async+0x14e>
    27c2:	f8d5 6110 	ldr.w	r6, [r5, #272]	; 0x110
    27c6:	bb66      	cbnz	r6, 2822 <uarte_nrfx_isr_async+0x14e>
	struct uart_event evt = {
    27c8:	2214      	movs	r2, #20
    27ca:	4631      	mov	r1, r6
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    27cc:	f8c5 614c 	str.w	r6, [r5, #332]	; 0x14c
    27d0:	a803      	add	r0, sp, #12
    27d2:	f8d5 314c 	ldr.w	r3, [r5, #332]	; 0x14c
	struct uarte_nrfx_data *data = dev->data;
    27d6:	6927      	ldr	r7, [r4, #16]
	struct uart_event evt = {
    27d8:	f002 fe54 	bl	5484 <memset>
    27dc:	2303      	movs	r3, #3
	user_callback(dev, &evt);
    27de:	4620      	mov	r0, r4
    27e0:	a903      	add	r1, sp, #12
	struct uart_event evt = {
    27e2:	f88d 300c 	strb.w	r3, [sp, #12]
	user_callback(dev, &evt);
    27e6:	f002 ff4e 	bl	5686 <user_callback>
	if (data->async->rx_timeout != SYS_FOREVER_US) {
    27ea:	68ff      	ldr	r7, [r7, #12]
    27ec:	6ffb      	ldr	r3, [r7, #124]	; 0x7c
    27ee:	1c5a      	adds	r2, r3, #1
    27f0:	d017      	beq.n	2822 <uarte_nrfx_isr_async+0x14e>
    27f2:	f44f 4e00 	mov.w	lr, #32768	; 0x8000
    27f6:	4631      	mov	r1, r6
		data->async->rx_timeout_left = data->async->rx_timeout;
    27f8:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
			      K_USEC(data->async->rx_timeout_slab),
    27fc:	f8d7 3080 	ldr.w	r3, [r7, #128]	; 0x80
    2800:	4887      	ldr	r0, [pc, #540]	; (2a20 <uarte_nrfx_isr_async+0x34c>)
    2802:	ea23 7ce3 	bic.w	ip, r3, r3, asr #31
    2806:	fbcc 010e 	smlal	r0, r1, ip, lr
    280a:	2300      	movs	r3, #0
    280c:	4a85      	ldr	r2, [pc, #532]	; (2a24 <uarte_nrfx_isr_async+0x350>)
    280e:	f7fd fca1 	bl	154 <__aeabi_uldivmod>
    2812:	4602      	mov	r2, r0
    2814:	460b      	mov	r3, r1
	z_impl_k_timer_start(timer, duration, period);
    2816:	e9cd 0100 	strd	r0, r1, [sp]
    281a:	f107 0088 	add.w	r0, r7, #136	; 0x88
    281e:	f002 fa5f 	bl	4ce0 <z_impl_k_timer_start>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2822:	f8d5 3144 	ldr.w	r3, [r5, #324]	; 0x144
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXTO) &&
    2826:	b333      	cbz	r3, 2876 <uarte_nrfx_isr_async+0x1a2>
    2828:	f8d5 6110 	ldr.w	r6, [r5, #272]	; 0x110
    282c:	bb1e      	cbnz	r6, 2876 <uarte_nrfx_isr_async+0x1a2>
	struct uarte_nrfx_data *data = dev->data;
    282e:	6927      	ldr	r7, [r4, #16]
	rx_buf_release(dev, &data->async->rx_buf);
    2830:	4620      	mov	r0, r4
    2832:	68f9      	ldr	r1, [r7, #12]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2834:	f8c5 6144 	str.w	r6, [r5, #324]	; 0x144
    2838:	3160      	adds	r1, #96	; 0x60
    283a:	f8d5 3144 	ldr.w	r3, [r5, #324]	; 0x144
	const struct uarte_nrfx_config *config = dev->config;
    283e:	f8d4 8004 	ldr.w	r8, [r4, #4]
	rx_buf_release(dev, &data->async->rx_buf);
    2842:	f002 ff40 	bl	56c6 <rx_buf_release>
	rx_buf_release(dev, &data->async->rx_next_buf);
    2846:	68f9      	ldr	r1, [r7, #12]
    2848:	4620      	mov	r0, r4
    284a:	316c      	adds	r1, #108	; 0x6c
    284c:	f002 ff3b 	bl	56c6 <rx_buf_release>
	if (data->async->rx_enabled) {
    2850:	68fb      	ldr	r3, [r7, #12]
    2852:	f893 20d2 	ldrb.w	r2, [r3, #210]	; 0xd2
    2856:	2a00      	cmp	r2, #0
    2858:	f000 809f 	beq.w	299a <uarte_nrfx_isr_async+0x2c6>
		data->async->rx_enabled = false;
    285c:	f883 60d2 	strb.w	r6, [r3, #210]	; 0xd2
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2860:	f8d8 3004 	ldr.w	r3, [r8, #4]
    2864:	06d8      	lsls	r0, r3, #27
    2866:	d503      	bpl.n	2870 <uarte_nrfx_isr_async+0x19c>
		async_uart_release(dev, UARTE_LOW_POWER_RX);
    2868:	2102      	movs	r1, #2
    286a:	4620      	mov	r0, r4
    286c:	f003 f8b4 	bl	59d8 <async_uart_release>
	notify_rx_disable(dev);
    2870:	4620      	mov	r0, r4
    2872:	f002 ff40 	bl	56f6 <notify_rx_disable>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2876:	f8d5 3120 	ldr.w	r3, [r5, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)
    287a:	b1db      	cbz	r3, 28b4 <uarte_nrfx_isr_async+0x1e0>
    return p_reg->INTENSET & mask;
    287c:	f8d5 3304 	ldr.w	r3, [r5, #772]	; 0x304
	    && nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK)) {
    2880:	05d9      	lsls	r1, r3, #23
    2882:	d517      	bpl.n	28b4 <uarte_nrfx_isr_async+0x1e0>
	return config->uarte_regs;
    2884:	6863      	ldr	r3, [r4, #4]
    2886:	681b      	ldr	r3, [r3, #0]
	__asm__ volatile(
    2888:	f04f 0120 	mov.w	r1, #32
    288c:	f3ef 8211 	mrs	r2, BASEPRI
    2890:	f381 8812 	msr	BASEPRI_MAX, r1
    2894:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2898:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    289c:	b131      	cbz	r1, 28ac <uarte_nrfx_isr_async+0x1d8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    289e:	2100      	movs	r1, #0
    28a0:	f8c3 1120 	str.w	r1, [r3, #288]	; 0x120
    28a4:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    28a8:	2101      	movs	r1, #1
    28aa:	60d9      	str	r1, [r3, #12]
	__asm__ volatile(
    28ac:	f382 8811 	msr	BASEPRI, r2
    28b0:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    28b4:	f8d5 3158 	ldr.w	r3, [r5, #344]	; 0x158
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)
    28b8:	2b00      	cmp	r3, #0
    28ba:	f43f af22 	beq.w	2702 <uarte_nrfx_isr_async+0x2e>
    return p_reg->INTENSET & mask;
    28be:	f8d5 3304 	ldr.w	r3, [r5, #772]	; 0x304
	    && nrf_uarte_int_enable_check(uarte,
    28c2:	025a      	lsls	r2, r3, #9
    28c4:	f57f af1d 	bpl.w	2702 <uarte_nrfx_isr_async+0x2e>
	const struct uarte_nrfx_config *config = dev->config;
    28c8:	6863      	ldr	r3, [r4, #4]
	struct uarte_nrfx_data *data = dev->data;
    28ca:	6925      	ldr	r5, [r4, #16]
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    28cc:	e9d3 7300 	ldrd	r7, r3, [r3]
    28d0:	06db      	lsls	r3, r3, #27
    28d2:	d467      	bmi.n	29a4 <uarte_nrfx_isr_async+0x2d0>
	if (!data->async->tx_buf) {
    28d4:	68eb      	ldr	r3, [r5, #12]
    28d6:	689b      	ldr	r3, [r3, #8]
    28d8:	2b00      	cmp	r3, #0
    28da:	f43f af12 	beq.w	2702 <uarte_nrfx_isr_async+0x2e>
	__asm__ volatile(
    28de:	f04f 0320 	mov.w	r3, #32
    28e2:	f3ef 8211 	mrs	r2, BASEPRI
    28e6:	f383 8812 	msr	BASEPRI_MAX, r3
    28ea:	f3bf 8f6f 	isb	sy
	size_t amount = (data->async->tx_amount >= 0) ?
    28ee:	68eb      	ldr	r3, [r5, #12]
    28f0:	f8d3 10c4 	ldr.w	r1, [r3, #196]	; 0xc4
			data->async->tx_amount : nrf_uarte_tx_amount_get(uarte);
    28f4:	2900      	cmp	r1, #0
    28f6:	bfac      	ite	ge
    28f8:	f8d3 60c4 	ldrge.w	r6, [r3, #196]	; 0xc4
    return p_reg->TXD.AMOUNT;
    28fc:	f8d7 654c 	ldrlt.w	r6, [r7, #1356]	; 0x54c
	__asm__ volatile(
    2900:	f382 8811 	msr	BASEPRI, r2
    2904:	f3bf 8f6f 	isb	sy
	if (data->async->pending_tx) {
    2908:	68e8      	ldr	r0, [r5, #12]
    290a:	f890 30d4 	ldrb.w	r3, [r0, #212]	; 0xd4
    290e:	2b00      	cmp	r3, #0
    2910:	d055      	beq.n	29be <uarte_nrfx_isr_async+0x2ea>
	__asm__ volatile(
    2912:	f04f 0320 	mov.w	r3, #32
    2916:	f3ef 8611 	mrs	r6, BASEPRI
    291a:	f383 8812 	msr	BASEPRI_MAX, r3
    291e:	f3bf 8f6f 	isb	sy
				start_tx_locked(dev, data);
    2922:	4629      	mov	r1, r5
    2924:	4620      	mov	r0, r4
    2926:	f003 f8b1 	bl	5a8c <start_tx_locked>
	__asm__ volatile(
    292a:	f386 8811 	msr	BASEPRI, r6
    292e:	f3bf 8f6f 	isb	sy
				return;
    2932:	e6e6      	b.n	2702 <uarte_nrfx_isr_async+0x2e>
		.data.rx_stop.reason = UARTE_ERROR_FROM_MASK(err),
    2934:	2601      	movs	r6, #1
    2936:	e705      	b.n	2744 <uarte_nrfx_isr_async+0x70>
    2938:	2602      	movs	r6, #2
    293a:	e703      	b.n	2744 <uarte_nrfx_isr_async+0x70>
    293c:	2604      	movs	r6, #4
    293e:	e701      	b.n	2744 <uarte_nrfx_isr_async+0x70>
	rx_buf_release(dev, &data->async->rx_buf);
    2940:	4620      	mov	r0, r4
    2942:	3160      	adds	r1, #96	; 0x60
    2944:	f002 febf 	bl	56c6 <rx_buf_release>
	__asm__ volatile(
    2948:	f04f 0320 	mov.w	r3, #32
    294c:	f3ef 8111 	mrs	r1, BASEPRI
    2950:	f383 8812 	msr	BASEPRI_MAX, r3
    2954:	f3bf 8f6f 	isb	sy
	if (data->async->rx_next_buf) {
    2958:	68fb      	ldr	r3, [r7, #12]
    295a:	6eda      	ldr	r2, [r3, #108]	; 0x6c
    295c:	b1d2      	cbz	r2, 2994 <uarte_nrfx_isr_async+0x2c0>
		data->async->rx_buf = data->async->rx_next_buf;
    295e:	661a      	str	r2, [r3, #96]	; 0x60
		data->async->rx_buf_len = data->async->rx_next_buf_len;
    2960:	6f1a      	ldr	r2, [r3, #112]	; 0x70
    2962:	665a      	str	r2, [r3, #100]	; 0x64
		data->async->rx_next_buf = NULL;
    2964:	2200      	movs	r2, #0
		data->async->rx_next_buf_len = 0;
    2966:	e9c3 221b 	strd	r2, r2, [r3, #108]	; 0x6c
		data->async->rx_offset = 0;
    296a:	669a      	str	r2, [r3, #104]	; 0x68
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    296c:	f8d6 314c 	ldr.w	r3, [r6, #332]	; 0x14c
		if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED)) {
    2970:	b90b      	cbnz	r3, 2976 <uarte_nrfx_isr_async+0x2a2>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2972:	2301      	movs	r3, #1
    2974:	6033      	str	r3, [r6, #0]
    p_reg->SHORTS &= ~(mask);
    2976:	f8d6 3200 	ldr.w	r3, [r6, #512]	; 0x200
    297a:	f023 0320 	bic.w	r3, r3, #32
    297e:	f8c6 3200 	str.w	r3, [r6, #512]	; 0x200
	__asm__ volatile(
    2982:	f381 8811 	msr	BASEPRI, r1
    2986:	f3bf 8f6f 	isb	sy
	data->async->is_in_irq = false;
    298a:	2200      	movs	r2, #0
    298c:	68fb      	ldr	r3, [r7, #12]
    298e:	f883 20d5 	strb.w	r2, [r3, #213]	; 0xd5
    2992:	e713      	b.n	27bc <uarte_nrfx_isr_async+0xe8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2994:	2301      	movs	r3, #1
    2996:	6073      	str	r3, [r6, #4]
}
    2998:	e7f3      	b.n	2982 <uarte_nrfx_isr_async+0x2ae>
		(void)rx_flush(dev, NULL, 0);
    299a:	4611      	mov	r1, r2
    299c:	6860      	ldr	r0, [r4, #4]
    299e:	f002 ffe7 	bl	5970 <rx_flush.isra.0>
    29a2:	e75d      	b.n	2860 <uarte_nrfx_isr_async+0x18c>
    p_reg->INTENCLR = mask;
    29a4:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
		async_uart_release(dev, UARTE_LOW_POWER_TX);
    29a8:	2101      	movs	r1, #1
    29aa:	f8c7 3308 	str.w	r3, [r7, #776]	; 0x308
    29ae:	4620      	mov	r0, r4
    29b0:	f003 f812 	bl	59d8 <async_uart_release>
		if (!data->async->tx_size) {
    29b4:	68eb      	ldr	r3, [r5, #12]
    29b6:	68db      	ldr	r3, [r3, #12]
    29b8:	2b00      	cmp	r3, #0
    29ba:	d18b      	bne.n	28d4 <uarte_nrfx_isr_async+0x200>
    29bc:	e6a1      	b.n	2702 <uarte_nrfx_isr_async+0x2e>
	if (data->async->tx_buf != data->async->xfer_buf) {
    29be:	6882      	ldr	r2, [r0, #8]
    29c0:	6903      	ldr	r3, [r0, #16]
    29c2:	429a      	cmp	r2, r3
    29c4:	d00b      	beq.n	29de <uarte_nrfx_isr_async+0x30a>
		if (amount == data->async->xfer_len) {
    29c6:	6942      	ldr	r2, [r0, #20]
			data->async->tx_cache_offset += amount;
    29c8:	6a03      	ldr	r3, [r0, #32]
		if (amount == data->async->xfer_len) {
    29ca:	42b2      	cmp	r2, r6
			data->async->tx_cache_offset += amount;
    29cc:	4433      	add	r3, r6
		if (amount == data->async->xfer_len) {
    29ce:	d125      	bne.n	2a1c <uarte_nrfx_isr_async+0x348>
			data->async->tx_cache_offset += amount;
    29d0:	6203      	str	r3, [r0, #32]
			if (setup_tx_cache(data)) {
    29d2:	f003 f836 	bl	5a42 <setup_tx_cache.isra.0>
    29d6:	2800      	cmp	r0, #0
    29d8:	d19b      	bne.n	2912 <uarte_nrfx_isr_async+0x23e>
			amount = data->async->tx_cache_offset;
    29da:	68eb      	ldr	r3, [r5, #12]
    29dc:	6a1e      	ldr	r6, [r3, #32]
	k_timer_stop(&data->async->tx_timeout_timer);
    29de:	68e8      	ldr	r0, [r5, #12]
    29e0:	3028      	adds	r0, #40	; 0x28
	z_impl_k_timer_stop(timer);
    29e2:	f003 ffb5 	bl	6950 <z_impl_k_timer_stop>
	struct uart_event evt = {
    29e6:	2214      	movs	r2, #20
    29e8:	2100      	movs	r1, #0
    29ea:	a803      	add	r0, sp, #12
    29ec:	f002 fd4a 	bl	5484 <memset>
		.data.tx.buf = data->async->tx_buf,
    29f0:	68eb      	ldr	r3, [r5, #12]
	user_callback(dev, &evt);
    29f2:	4620      	mov	r0, r4
	struct uart_event evt = {
    29f4:	689a      	ldr	r2, [r3, #8]
	user_callback(dev, &evt);
    29f6:	a903      	add	r1, sp, #12
	struct uart_event evt = {
    29f8:	e9cd 2604 	strd	r2, r6, [sp, #16]
	if (amount == data->async->tx_size) {
    29fc:	68da      	ldr	r2, [r3, #12]
    29fe:	4296      	cmp	r6, r2
		evt.type = UART_TX_ABORTED;
    2a00:	bf1c      	itt	ne
    2a02:	2201      	movne	r2, #1
    2a04:	f88d 200c 	strbne.w	r2, [sp, #12]
    2a08:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    2a0c:	f8c7 2308 	str.w	r2, [r7, #776]	; 0x308
	data->async->tx_buf = NULL;
    2a10:	2200      	movs	r2, #0
    2a12:	609a      	str	r2, [r3, #8]
	data->async->tx_size = 0;
    2a14:	60da      	str	r2, [r3, #12]
	user_callback(dev, &evt);
    2a16:	f002 fe36 	bl	5686 <user_callback>
    2a1a:	e672      	b.n	2702 <uarte_nrfx_isr_async+0x2e>
			amount += data->async->tx_cache_offset;
    2a1c:	461e      	mov	r6, r3
    2a1e:	e7de      	b.n	29de <uarte_nrfx_isr_async+0x30a>
    2a20:	000f423f 	.word	0x000f423f
    2a24:	000f4240 	.word	0x000f4240

00002a28 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    2a28:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    2a2a:	f003 021f 	and.w	r2, r3, #31
    2a2e:	6002      	str	r2, [r0, #0]
}
    2a30:	4a03      	ldr	r2, [pc, #12]	; (2a40 <nrf_gpio_pin_port_decode+0x18>)
    2a32:	4804      	ldr	r0, [pc, #16]	; (2a44 <nrf_gpio_pin_port_decode+0x1c>)
    return pin_number >> 5;
    2a34:	095b      	lsrs	r3, r3, #5
}
    2a36:	2b01      	cmp	r3, #1
    2a38:	bf08      	it	eq
    2a3a:	4610      	moveq	r0, r2
    2a3c:	4770      	bx	lr
    2a3e:	bf00      	nop
    2a40:	50842800 	.word	0x50842800
    2a44:	50842500 	.word	0x50842500

00002a48 <start_rx_activation>:
	__ASSERT_NO_MSG(err >= 0);
}

static void start_rx_activation(struct lpuart_data *data)
{
	data->rx_state = RX_PREPARE;
    2a48:	2302      	movs	r3, #2
{
    2a4a:	b510      	push	{r4, lr}
    2a4c:	4604      	mov	r4, r0
	data->rx_state = RX_PREPARE;
    2a4e:	f880 308c 	strb.w	r3, [r0, #140]	; 0x8c
		z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF);
    2a52:	2000      	movs	r0, #0
    2a54:	f7ff f9e4 	bl	1e20 <z_nrf_clock_control_get_onoff>
					      sys_notify_generic_callback handler)
{
	__ASSERT_NO_MSG(notify != NULL);
	__ASSERT_NO_MSG(handler != NULL);

	*notify = (struct sys_notify){
    2a58:	4b07      	ldr	r3, [pc, #28]	; (2a78 <start_rx_activation+0x30>)
    2a5a:	2200      	movs	r2, #0
    2a5c:	f8c4 3094 	str.w	r3, [r4, #148]	; 0x94
    2a60:	2303      	movs	r3, #3
    2a62:	f8c4 209c 	str.w	r2, [r4, #156]	; 0x9c
    2a66:	f8c4 3098 	str.w	r3, [r4, #152]	; 0x98
	err = onoff_request(mgr, &data->rx_clk_cli);
    2a6a:	f104 0190 	add.w	r1, r4, #144	; 0x90
	if (IS_ENABLED(CONFIG_NRF_SW_LPUART_HFXO_ON_RX)) {
		rx_hfclk_request(data);
	} else {
		activate_rx(data);
	}
}
    2a6e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	err = onoff_request(mgr, &data->rx_clk_cli);
    2a72:	f002 bbaa 	b.w	51ca <onoff_request>
    2a76:	bf00      	nop
    2a78:	00005f6f 	.word	0x00005f6f

00002a7c <api_poll_out>:
	return -ENOTSUP;
#endif
}

static void api_poll_out(const struct device *dev, unsigned char out_char)
{
    2a7c:	b570      	push	{r4, r5, r6, lr}
    2a7e:	4605      	mov	r5, r0
    2a80:	460e      	mov	r6, r1
	return dev->data;
    2a82:	6904      	ldr	r4, [r0, #16]
	struct lpuart_data *data = get_dev_data(dev);
	bool thread_ctx = !k_is_in_isr() && !k_is_pre_kernel();
    2a84:	f003 fe2d 	bl	66e2 <k_is_in_isr>
    2a88:	b910      	cbnz	r0, 2a90 <api_poll_out+0x14>
	return !z_sys_post_kernel;
    2a8a:	4b12      	ldr	r3, [pc, #72]	; (2ad4 <api_poll_out+0x58>)
	int err;

	if (thread_ctx) {
    2a8c:	781b      	ldrb	r3, [r3, #0]
    2a8e:	b933      	cbnz	r3, 2a9e <api_poll_out+0x22>
		/* in thread context pend until tx is in idle */
		while (data->tx_buf) {
			k_msleep(1);
		}
	} else if (data->tx_buf) {
    2a90:	6ee3      	ldr	r3, [r4, #108]	; 0x6c
    2a92:	b993      	cbnz	r3, 2aba <api_poll_out+0x3e>
    2a94:	e006      	b.n	2aa4 <api_poll_out+0x28>
	return z_impl_k_sleep(timeout);
    2a96:	2021      	movs	r0, #33	; 0x21
    2a98:	2100      	movs	r1, #0
    2a9a:	f001 ff17 	bl	48cc <z_impl_k_sleep>
		while (data->tx_buf) {
    2a9e:	6ee3      	ldr	r3, [r4, #108]	; 0x6c
    2aa0:	2b00      	cmp	r3, #0
    2aa2:	d1f8      	bne.n	2a96 <api_poll_out+0x1a>
		return;
	}

	if (!atomic_cas(&data->txbyte, -1, out_char)) {
    2aa4:	f104 0168 	add.w	r1, r4, #104	; 0x68
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    2aa8:	e8d1 3fef 	ldaex	r3, [r1]
    2aac:	3301      	adds	r3, #1
    2aae:	d103      	bne.n	2ab8 <api_poll_out+0x3c>
    2ab0:	e8c1 6fe2 	stlex	r2, r6, [r1]
    2ab4:	2a00      	cmp	r2, #0
    2ab6:	d1f7      	bne.n	2aa8 <api_poll_out+0x2c>
    2ab8:	d000      	beq.n	2abc <api_poll_out+0x40>
	err = api_tx(dev, (uint8_t *)&data->txbyte, 1,
		     CONFIG_NRF_SW_LPUART_DEFAULT_TX_TIMEOUT);
	if (err < 0) {
		data->txbyte = -1;
	}
}
    2aba:	bd70      	pop	{r4, r5, r6, pc}
	err = api_tx(dev, (uint8_t *)&data->txbyte, 1,
    2abc:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    2ac0:	2201      	movs	r2, #1
    2ac2:	4628      	mov	r0, r5
    2ac4:	f003 f9c4 	bl	5e50 <api_tx>
	if (err < 0) {
    2ac8:	2800      	cmp	r0, #0
		data->txbyte = -1;
    2aca:	bfbc      	itt	lt
    2acc:	f04f 33ff 	movlt.w	r3, #4294967295
    2ad0:	66a3      	strlt	r3, [r4, #104]	; 0x68
    2ad2:	e7f2      	b.n	2aba <api_poll_out+0x3e>
    2ad4:	20000db1 	.word	0x20000db1

00002ad8 <ctrl_pin_configure>:
{
    2ad8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	io->pin = cfg->pin;
    2ada:	790b      	ldrb	r3, [r1, #4]
{
    2adc:	4604      	mov	r4, r0
	io->pin = cfg->pin;
    2ade:	7403      	strb	r3, [r0, #16]
	io->nrf_pin = cfg->nrf_pin;
    2ae0:	794b      	ldrb	r3, [r1, #5]
{
    2ae2:	4615      	mov	r5, r2
	io->nrf_pin = cfg->nrf_pin;
    2ae4:	7443      	strb	r3, [r0, #17]
	io->req = req;
    2ae6:	74c2      	strb	r2, [r0, #19]
	io->port = device_get_binding(cfg->port_name);
    2ae8:	6808      	ldr	r0, [r1, #0]
		union { uintptr_t x; const char * val; } parm0 = { .val = name };
		return (const struct device *) arch_syscall_invoke1(parm0.x, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
    2aea:	f001 f92f 	bl	3d4c <z_impl_device_get_binding>
    2aee:	60e0      	str	r0, [r4, #12]
	if (!io->port) {
    2af0:	2800      	cmp	r0, #0
    2af2:	d043      	beq.n	2b7c <ctrl_pin_configure+0xa4>
	gpio_init_callback(&io->callback, gpio_handler, BIT(io->pin));
    2af4:	2601      	movs	r6, #1
    2af6:	7c21      	ldrb	r1, [r4, #16]
				      gpio_port_pins_t pin_mask)
{
	__ASSERT(callback, "Callback pointer should not be NULL");
	__ASSERT(handler, "Callback handler pointer should not be NULL");

	callback->handler = handler;
    2af8:	4a23      	ldr	r2, [pc, #140]	; (2b88 <ctrl_pin_configure+0xb0>)
    2afa:	fa06 f701 	lsl.w	r7, r6, r1
	callback->pin_mask = pin_mask;
    2afe:	e9c4 2701 	strd	r2, r7, [r4, #4]
	struct gpio_driver_data *data =
    2b02:	6902      	ldr	r2, [r0, #16]
	const struct gpio_driver_api *api =
    2b04:	f8d0 c008 	ldr.w	ip, [r0, #8]
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    2b08:	6813      	ldr	r3, [r2, #0]
    2b0a:	ea23 0307 	bic.w	r3, r3, r7
    2b0e:	6013      	str	r3, [r2, #0]
	return api->pin_configure(port, pin, flags);
    2b10:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2b14:	f8dc 3000 	ldr.w	r3, [ip]
    2b18:	4798      	blx	r3
	if (err < 0) {
    2b1a:	2800      	cmp	r0, #0
    2b1c:	db29      	blt.n	2b72 <ctrl_pin_configure+0x9a>
	err = gpio_add_callback(io->port, &io->callback);
    2b1e:	68e0      	ldr	r0, [r4, #12]
				    struct gpio_callback *callback)
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;

	if (api->manage_callback == NULL) {
    2b20:	6883      	ldr	r3, [r0, #8]
    2b22:	69db      	ldr	r3, [r3, #28]
    2b24:	b36b      	cbz	r3, 2b82 <ctrl_pin_configure+0xaa>
		return -ENOTSUP;
	}

	return api->manage_callback(port, callback, true);
    2b26:	4632      	mov	r2, r6
    2b28:	4621      	mov	r1, r4
    2b2a:	4798      	blx	r3
	if (err < 0) {
    2b2c:	2800      	cmp	r0, #0
    2b2e:	db20      	blt.n	2b72 <ctrl_pin_configure+0x9a>
	err = gpio_pin_interrupt_configure(io->port, io->pin, req ?
    2b30:	2d00      	cmp	r5, #0
    2b32:	bf14      	ite	ne
    2b34:	f04f 7350 	movne.w	r3, #54525952	; 0x3400000
    2b38:	f04f 63a8 	moveq.w	r3, #88080384	; 0x5400000
    2b3c:	68e0      	ldr	r0, [r4, #12]
    2b3e:	7c21      	ldrb	r1, [r4, #16]
	return api->pin_interrupt_configure(port, pin, mode, trig);
    2b40:	6882      	ldr	r2, [r0, #8]
    2b42:	f003 63c0 	and.w	r3, r3, #100663296	; 0x6000000
    2b46:	6995      	ldr	r5, [r2, #24]
    2b48:	f04f 72a0 	mov.w	r2, #20971520	; 0x1400000
    2b4c:	47a8      	blx	r5
	if (err < 0) {
    2b4e:	2800      	cmp	r0, #0
    2b50:	db0f      	blt.n	2b72 <ctrl_pin_configure+0x9a>
	for (i = 0; i < GPIOTE_CH_NUM; i++) {
    2b52:	2300      	movs	r3, #0
		if (nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == io->nrf_pin) {
    2b54:	7c61      	ldrb	r1, [r4, #17]
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    2b56:	480d      	ldr	r0, [pc, #52]	; (2b8c <ctrl_pin_configure+0xb4>)
    2b58:	f503 72a2 	add.w	r2, r3, #324	; 0x144
    2b5c:	f850 2022 	ldr.w	r2, [r0, r2, lsl #2]
    2b60:	f3c2 2205 	ubfx	r2, r2, #8, #6
    2b64:	4291      	cmp	r1, r2
    2b66:	d105      	bne.n	2b74 <ctrl_pin_configure+0x9c>
			io->ch = i;
    2b68:	74a3      	strb	r3, [r4, #18]
	ctrl_pin_idle(io);
    2b6a:	4620      	mov	r0, r4
    2b6c:	f003 fa1a 	bl	5fa4 <ctrl_pin_idle>
	return 0;
    2b70:	2000      	movs	r0, #0
}
    2b72:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	for (i = 0; i < GPIOTE_CH_NUM; i++) {
    2b74:	3301      	adds	r3, #1
    2b76:	2b08      	cmp	r3, #8
    2b78:	d1ee      	bne.n	2b58 <ctrl_pin_configure+0x80>
    2b7a:	e7f6      	b.n	2b6a <ctrl_pin_configure+0x92>
		return -ENODEV;
    2b7c:	f06f 0012 	mvn.w	r0, #18
    2b80:	e7f7      	b.n	2b72 <ctrl_pin_configure+0x9a>
		return -ENOTSUP;
    2b82:	f06f 0085 	mvn.w	r0, #133	; 0x85
    2b86:	e7f4      	b.n	2b72 <ctrl_pin_configure+0x9a>
    2b88:	00002b91 	.word	0x00002b91
    2b8c:	5000d000 	.word	0x5000d000

00002b90 <gpio_handler>:
{
    2b90:	b573      	push	{r0, r1, r4, r5, r6, lr}
	if (io->req) {
    2b92:	7cc8      	ldrb	r0, [r1, #19]
{
    2b94:	460c      	mov	r4, r1
	if (io->req) {
    2b96:	2800      	cmp	r0, #0
    2b98:	d03f      	beq.n	2c1a <gpio_handler+0x8a>
	if (data->tx_buf == NULL) {
    2b9a:	6e8b      	ldr	r3, [r1, #104]	; 0x68
    2b9c:	b943      	cbnz	r3, 2bb0 <gpio_handler+0x20>
	ctrl_pin_idle(&data->req_pin);
    2b9e:	4620      	mov	r0, r4
    2ba0:	f003 fa00 	bl	5fa4 <ctrl_pin_idle>
	data->tx_buf = NULL;
    2ba4:	2300      	movs	r3, #0
    2ba6:	66a3      	str	r3, [r4, #104]	; 0x68
	data->tx_active = false;
    2ba8:	f884 3070 	strb.w	r3, [r4, #112]	; 0x70
}
    2bac:	b002      	add	sp, #8
    2bae:	bd70      	pop	{r4, r5, r6, pc}
		nrf_gpio_pin_set(io->nrf_pin);
    2bb0:	7c4b      	ldrb	r3, [r1, #17]
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2bb2:	2601      	movs	r6, #1
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    2bb4:	a801      	add	r0, sp, #4
    2bb6:	9301      	str	r3, [sp, #4]
    2bb8:	f7ff ff36 	bl	2a28 <nrf_gpio_pin_port_decode>
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    2bbc:	2500      	movs	r5, #0
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2bbe:	9b01      	ldr	r3, [sp, #4]
    2bc0:	fa06 f303 	lsl.w	r3, r6, r3
    p_reg->OUTSET = set_mask;
    2bc4:	6083      	str	r3, [r0, #8]
    2bc6:	7c8a      	ldrb	r2, [r1, #18]
    2bc8:	0092      	lsls	r2, r2, #2
    2bca:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    2bce:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
    2bd2:	f8c2 5510 	str.w	r5, [r2, #1296]	; 0x510
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
    2bd6:	f8c2 5510 	str.w	r5, [r2, #1296]	; 0x510
		nrf_gpio_cfg_output(io->nrf_pin);
    2bda:	7c48      	ldrb	r0, [r1, #17]
    2bdc:	f003 f998 	bl	5f10 <nrf_gpio_cfg_output>
	z_impl_k_timer_stop(timer);
    2be0:	f101 002c 	add.w	r0, r1, #44	; 0x2c
    2be4:	f003 feb4 	bl	6950 <z_impl_k_timer_stop>
	__asm__ volatile(
    2be8:	f04f 0220 	mov.w	r2, #32
    2bec:	f3ef 8311 	mrs	r3, BASEPRI
    2bf0:	f382 8812 	msr	BASEPRI_MAX, r2
    2bf4:	f3bf 8f6f 	isb	sy
	len = data->tx_len;
    2bf8:	e9d4 121a 	ldrd	r1, r2, [r4, #104]	; 0x68
	data->tx_active = true;
    2bfc:	f884 6070 	strb.w	r6, [r4, #112]	; 0x70
	__asm__ volatile(
    2c00:	f383 8811 	msr	BASEPRI, r3
    2c04:	f3bf 8f6f 	isb	sy
	err = uart_tx(data->uart, buf, len, 0);
    2c08:	f854 0c04 	ldr.w	r0, [r4, #-4]
{
#ifdef CONFIG_UART_ASYNC_API
	const struct uart_driver_api *api =
			(const struct uart_driver_api *)dev->api;

	return api->tx(dev, buf, len, timeout);
    2c0c:	6883      	ldr	r3, [r0, #8]
    2c0e:	685e      	ldr	r6, [r3, #4]
    2c10:	462b      	mov	r3, r5
    2c12:	47b0      	blx	r6
	if (err < 0) {
    2c14:	42a8      	cmp	r0, r5
    2c16:	dac9      	bge.n	2bac <gpio_handler+0x1c>
    2c18:	e7c1      	b.n	2b9e <gpio_handler+0xe>
	if (nrf_gpiote_event_polarity_get(NRF_GPIOTE, data->rdy_pin.ch)
    2c1a:	7c8b      	ldrb	r3, [r1, #18]
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    2c1c:	4a22      	ldr	r2, [pc, #136]	; (2ca8 <gpio_handler+0x118>)
    2c1e:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    2c22:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    2c26:	f3c3 4301 	ubfx	r3, r3, #16, #2
    2c2a:	2b01      	cmp	r3, #1
    2c2c:	d10c      	bne.n	2c48 <gpio_handler+0xb8>
		data->rx_req = true;
    2c2e:	f881 3075 	strb.w	r3, [r1, #117]	; 0x75
		if (data->rx_state == RX_IDLE) {
    2c32:	f891 3074 	ldrb.w	r3, [r1, #116]	; 0x74
    2c36:	2b01      	cmp	r3, #1
    2c38:	d1b8      	bne.n	2bac <gpio_handler+0x1c>
			start_rx_activation(data);
    2c3a:	f1a1 0018 	sub.w	r0, r1, #24
}
    2c3e:	b002      	add	sp, #8
    2c40:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
			start_rx_activation(data);
    2c44:	f7ff bf00 	b.w	2a48 <start_rx_activation>
		     z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF);
    2c48:	f7ff f8ea 	bl	1e20 <z_nrf_clock_control_get_onoff>
 * @retval negative other errors produced by onoff_release().
 */
static inline int onoff_cancel_or_release(struct onoff_manager *mgr,
					  struct onoff_client *cli)
{
	int rv = onoff_cancel(mgr, cli);
    2c4c:	f104 0178 	add.w	r1, r4, #120	; 0x78
    2c50:	4605      	mov	r5, r0
    2c52:	f002 fb28 	bl	52a6 <onoff_cancel>

	if (rv == -EALREADY) {
    2c56:	3078      	adds	r0, #120	; 0x78
    2c58:	d102      	bne.n	2c60 <gpio_handler+0xd0>
		rv = onoff_release(mgr);
    2c5a:	4628      	mov	r0, r5
    2c5c:	f002 fafe 	bl	525c <onoff_release>
	ctrl_pin_idle(&data->rdy_pin);
    2c60:	4620      	mov	r0, r4
    2c62:	f003 f99f 	bl	5fa4 <ctrl_pin_idle>
	if (nrf_gpio_pin_read(data->rdy_pin.nrf_pin)) {
    2c66:	7c63      	ldrb	r3, [r4, #17]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    2c68:	a801      	add	r0, sp, #4
    2c6a:	9301      	str	r3, [sp, #4]
    2c6c:	f7ff fedc 	bl	2a28 <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    2c70:	9a01      	ldr	r2, [sp, #4]
    return p_reg->IN;
    2c72:	6903      	ldr	r3, [r0, #16]
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    2c74:	40d3      	lsrs	r3, r2
    2c76:	07db      	lsls	r3, r3, #31
    2c78:	d50b      	bpl.n	2c92 <gpio_handler+0x102>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2c7a:	2200      	movs	r2, #0
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    2c7c:	7ca3      	ldrb	r3, [r4, #18]
    2c7e:	009b      	lsls	r3, r3, #2
    return ((uint32_t)p_reg + event);
    2c80:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    2c84:	f503 4351 	add.w	r3, r3, #53504	; 0xd100
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2c88:	601a      	str	r2, [r3, #0]
    2c8a:	681b      	ldr	r3, [r3, #0]
		data->rx_req = true;
    2c8c:	2301      	movs	r3, #1
    2c8e:	f884 3075 	strb.w	r3, [r4, #117]	; 0x75
	data->rx_state = RX_TO_IDLE;
    2c92:	2304      	movs	r3, #4
	err = uart_rx_disable(data->uart);
    2c94:	f854 0c18 	ldr.w	r0, [r4, #-24]
	data->rx_state = RX_TO_IDLE;
    2c98:	f884 3074 	strb.w	r3, [r4, #116]	; 0x74
{
#ifdef CONFIG_UART_ASYNC_API
	const struct uart_driver_api *api =
			(const struct uart_driver_api *)dev->api;

	return api->rx_disable(dev);
    2c9c:	6883      	ldr	r3, [r0, #8]
    2c9e:	695b      	ldr	r3, [r3, #20]
}
    2ca0:	b002      	add	sp, #8
    2ca2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    2ca6:	4718      	bx	r3
    2ca8:	5000d000 	.word	0x5000d000

00002cac <lpuart_init>:
{
    2cac:	b570      	push	{r4, r5, r6, lr}
	return dev->config;
    2cae:	6846      	ldr	r6, [r0, #4]
{
    2cb0:	4604      	mov	r4, r0
	return dev->data;
    2cb2:	6905      	ldr	r5, [r0, #16]
	data->uart = device_get_binding(cfg->uart_name);
    2cb4:	6830      	ldr	r0, [r6, #0]
    2cb6:	f001 f849 	bl	3d4c <z_impl_device_get_binding>
    2cba:	6028      	str	r0, [r5, #0]
	if (data->uart == NULL) {
    2cbc:	2800      	cmp	r0, #0
    2cbe:	d039      	beq.n	2d34 <lpuart_init+0x88>
	err = ctrl_pin_configure(&data->req_pin, &cfg->req, true);
    2cc0:	2201      	movs	r2, #1
    2cc2:	1d31      	adds	r1, r6, #4
    2cc4:	1d28      	adds	r0, r5, #4
    2cc6:	f7ff ff07 	bl	2ad8 <ctrl_pin_configure>
	if (err < 0) {
    2cca:	2800      	cmp	r0, #0
    2ccc:	da02      	bge.n	2cd4 <lpuart_init+0x28>
		return -EINVAL;
    2cce:	f06f 0015 	mvn.w	r0, #21
}
    2cd2:	bd70      	pop	{r4, r5, r6, pc}
	err = ctrl_pin_configure(&data->rdy_pin, &cfg->rdy, false);
    2cd4:	2200      	movs	r2, #0
    2cd6:	f106 010c 	add.w	r1, r6, #12
    2cda:	f105 0018 	add.w	r0, r5, #24
    2cde:	f7ff fefb 	bl	2ad8 <ctrl_pin_configure>
	if (err < 0) {
    2ce2:	2800      	cmp	r0, #0
    2ce4:	dbf3      	blt.n	2cce <lpuart_init+0x22>
	k_timer_init(&data->tx_timer, tx_timeout, NULL);
    2ce6:	2200      	movs	r2, #0
    2ce8:	4914      	ldr	r1, [pc, #80]	; (2d3c <lpuart_init+0x90>)
    2cea:	f105 0030 	add.w	r0, r5, #48	; 0x30
    2cee:	f003 fe23 	bl	6938 <k_timer_init>
	err = uart_callback_set(data->uart, uart_callback, (void *)dev);
    2cf2:	6828      	ldr	r0, [r5, #0]
	timer->user_data = user_data;
    2cf4:	666c      	str	r4, [r5, #100]	; 0x64
	if (api->callback_set == NULL) {
    2cf6:	6883      	ldr	r3, [r0, #8]
    2cf8:	681b      	ldr	r3, [r3, #0]
    2cfa:	2b00      	cmp	r3, #0
    2cfc:	d0e7      	beq.n	2cce <lpuart_init+0x22>
	return api->callback_set(dev, callback, user_data);
    2cfe:	4622      	mov	r2, r4
    2d00:	490f      	ldr	r1, [pc, #60]	; (2d40 <lpuart_init+0x94>)
    2d02:	4798      	blx	r3
	if (err < 0) {
    2d04:	2800      	cmp	r0, #0
    2d06:	dbe2      	blt.n	2cce <lpuart_init+0x22>
	if (api->callback_set == NULL) {
    2d08:	68a3      	ldr	r3, [r4, #8]
    2d0a:	681b      	ldr	r3, [r3, #0]
    2d0c:	2b00      	cmp	r3, #0
    2d0e:	d0de      	beq.n	2cce <lpuart_init+0x22>
	return api->callback_set(dev, callback, user_data);
    2d10:	2200      	movs	r2, #0
    2d12:	4620      	mov	r0, r4
    2d14:	490b      	ldr	r1, [pc, #44]	; (2d44 <lpuart_init+0x98>)
    2d16:	4798      	blx	r3
	if (err < 0) {
    2d18:	2800      	cmp	r0, #0
    2d1a:	dbd8      	blt.n	2cce <lpuart_init+0x22>
	err = api_rx_enable(dev, data->int_driven.rxbuf,
    2d1c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    2d20:	2280      	movs	r2, #128	; 0x80
    2d22:	4620      	mov	r0, r4
    2d24:	f505 7196 	add.w	r1, r5, #300	; 0x12c
    2d28:	f002 ffdd 	bl	5ce6 <api_rx_enable>
	data->txbyte = -1;
    2d2c:	f04f 33ff 	mov.w	r3, #4294967295
    2d30:	66ab      	str	r3, [r5, #104]	; 0x68
	return err;
    2d32:	e7ce      	b.n	2cd2 <lpuart_init+0x26>
		return -ENODEV;
    2d34:	f06f 0012 	mvn.w	r0, #18
    2d38:	e7cb      	b.n	2cd2 <lpuart_init+0x26>
    2d3a:	bf00      	nop
    2d3c:	000060d3 	.word	0x000060d3
    2d40:	00006027 	.word	0x00006027
    2d44:	00005d5b 	.word	0x00005d5b

00002d48 <compare_int_lock>:
#endif
}

static bool compare_int_lock(int32_t chan)
{
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    2d48:	2301      	movs	r3, #1
    2d4a:	4083      	lsls	r3, r0
{
    2d4c:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    2d4e:	43dc      	mvns	r4, r3
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2d50:	4a0d      	ldr	r2, [pc, #52]	; (2d88 <compare_int_lock+0x40>)
    2d52:	e8d2 1fef 	ldaex	r1, [r2]
    2d56:	ea01 0c04 	and.w	ip, r1, r4
    2d5a:	e8c2 cfee 	stlex	lr, ip, [r2]
    2d5e:	f1be 0f00 	cmp.w	lr, #0
    2d62:	d1f6      	bne.n	2d52 <compare_int_lock+0xa>

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2d64:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2d68:	fa02 f000 	lsl.w	r0, r2, r0
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    2d6c:	f102 2250 	add.w	r2, r2, #1342197760	; 0x50005000
    2d70:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
    2d74:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2d78:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    2d7c:	420b      	tst	r3, r1
}
    2d7e:	bf14      	ite	ne
    2d80:	2001      	movne	r0, #1
    2d82:	2000      	moveq	r0, #0
    2d84:	bd10      	pop	{r4, pc}
    2d86:	bf00      	nop
    2d88:	20000b84 	.word	0x20000b84

00002d8c <sys_clock_timeout_handler>:
static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2d8c:	4919      	ldr	r1, [pc, #100]	; (2df4 <sys_clock_timeout_handler+0x68>)
{
    2d8e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2d90:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    2d92:	f022 457f 	bic.w	r5, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2d96:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    2d98:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    2d9c:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2da0:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    2da2:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    2da6:	d222      	bcs.n	2dee <sys_clock_timeout_handler+0x62>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    2da8:	4b13      	ldr	r3, [pc, #76]	; (2df8 <sys_clock_timeout_handler+0x6c>)
    2daa:	681b      	ldr	r3, [r3, #0]
    2dac:	0a1a      	lsrs	r2, r3, #8
    2dae:	061b      	lsls	r3, r3, #24
    2db0:	195e      	adds	r6, r3, r5
    2db2:	4b12      	ldr	r3, [pc, #72]	; (2dfc <sys_clock_timeout_handler+0x70>)
    2db4:	f142 0700 	adc.w	r7, r2, #0
    2db8:	e9c3 6700 	strd	r6, r7, [r3]
		return true;
    2dbc:	2601      	movs	r6, #1
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    2dbe:	f001 fed5 	bl	4b6c <sys_clock_announce>
    return p_reg->CC[ch];
    2dc2:	00a3      	lsls	r3, r4, #2
    2dc4:	f103 2350 	add.w	r3, r3, #1342197760	; 0x50005000
    2dc8:	f503 3380 	add.w	r3, r3, #65536	; 0x10000
    2dcc:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    2dd0:	42aa      	cmp	r2, r5
    2dd2:	d10b      	bne.n	2dec <sys_clock_timeout_handler+0x60>
		 * If anchor was updated we can enable same CC value to trigger
		 * interrupt after full cycle. Else set event in anchor update
		 * range. Since anchor was not updated we know that it's very
		 * far from mid point so setting is done without any protection.
		 */
		if (!anchor_updated) {
    2dd4:	b91e      	cbnz	r6, 2dde <sys_clock_timeout_handler+0x52>
    p_reg->CC[ch] = cc_val;
    2dd6:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    2dda:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2dde:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    2de2:	4b07      	ldr	r3, [pc, #28]	; (2e00 <sys_clock_timeout_handler+0x74>)
    2de4:	fa00 f404 	lsl.w	r4, r0, r4
    2de8:	f8c3 4344 	str.w	r4, [r3, #836]	; 0x344
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    2dec:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return false;
    2dee:	2600      	movs	r6, #0
    2df0:	e7e5      	b.n	2dbe <sys_clock_timeout_handler+0x32>
    2df2:	bf00      	nop
    2df4:	20000438 	.word	0x20000438
    2df8:	20000b88 	.word	0x20000b88
    2dfc:	20000420 	.word	0x20000420
    2e00:	50015000 	.word	0x50015000

00002e04 <compare_int_unlock>:
	if (key) {
    2e04:	b1e1      	cbz	r1, 2e40 <compare_int_unlock+0x3c>
		atomic_or(&int_mask, BIT(chan));
    2e06:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    2e08:	4a0e      	ldr	r2, [pc, #56]	; (2e44 <compare_int_unlock+0x40>)
    2e0a:	4083      	lsls	r3, r0
    2e0c:	e8d2 1fef 	ldaex	r1, [r2]
    2e10:	4319      	orrs	r1, r3
    2e12:	e8c2 1fec 	stlex	ip, r1, [r2]
    2e16:	f1bc 0f00 	cmp.w	ip, #0
    2e1a:	d1f7      	bne.n	2e0c <compare_int_unlock+0x8>
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2e1c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    p_reg->INTENSET = mask;
    2e20:	4a09      	ldr	r2, [pc, #36]	; (2e48 <compare_int_unlock+0x44>)
    2e22:	4083      	lsls	r3, r0
    2e24:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    2e28:	4b08      	ldr	r3, [pc, #32]	; (2e4c <compare_int_unlock+0x48>)
    2e2a:	e8d3 3faf 	lda	r3, [r3]
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    2e2e:	fa23 f000 	lsr.w	r0, r3, r0
    2e32:	07c3      	lsls	r3, r0, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2e34:	bf42      	ittt	mi
    2e36:	f44f 1200 	movmi.w	r2, #2097152	; 0x200000
    2e3a:	4b05      	ldrmi	r3, [pc, #20]	; (2e50 <compare_int_unlock+0x4c>)
    2e3c:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    2e40:	4770      	bx	lr
    2e42:	bf00      	nop
    2e44:	20000b84 	.word	0x20000b84
    2e48:	50015000 	.word	0x50015000
    2e4c:	20000b80 	.word	0x20000b80
    2e50:	e000e100 	.word	0xe000e100

00002e54 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    2e54:	4b0d      	ldr	r3, [pc, #52]	; (2e8c <z_nrf_rtc_timer_read+0x38>)
    2e56:	6818      	ldr	r0, [r3, #0]
    2e58:	0a01      	lsrs	r1, r0, #8
    2e5a:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    2e5c:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    2e60:	4b0b      	ldr	r3, [pc, #44]	; (2e90 <z_nrf_rtc_timer_read+0x3c>)
    2e62:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    2e66:	1818      	adds	r0, r3, r0
    2e68:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    2e6c:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2e70:	d20a      	bcs.n	2e88 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    2e72:	4b08      	ldr	r3, [pc, #32]	; (2e94 <z_nrf_rtc_timer_read+0x40>)
    2e74:	e9d3 2300 	ldrd	r2, r3, [r3]
    2e78:	4290      	cmp	r0, r2
    2e7a:	eb71 0303 	sbcs.w	r3, r1, r3
    2e7e:	d203      	bcs.n	2e88 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    2e80:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    2e84:	f141 0100 	adc.w	r1, r1, #0
}
    2e88:	4770      	bx	lr
    2e8a:	bf00      	nop
    2e8c:	20000b88 	.word	0x20000b88
    2e90:	50015000 	.word	0x50015000
    2e94:	20000420 	.word	0x20000420

00002e98 <compare_set>:
{
    2e98:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2e9c:	b085      	sub	sp, #20
    2e9e:	4616      	mov	r6, r2
    2ea0:	4698      	mov	r8, r3
    2ea2:	4605      	mov	r5, r0
	key = compare_int_lock(chan);
    2ea4:	f7ff ff50 	bl	2d48 <compare_int_lock>
    2ea8:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    2eaa:	f7ff ffd3 	bl	2e54 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    2eae:	42b0      	cmp	r0, r6
    2eb0:	eb71 0308 	sbcs.w	r3, r1, r8
    2eb4:	d276      	bcs.n	2fa4 <compare_set+0x10c>
		if (target_time - curr_time > COUNTER_SPAN) {
    2eb6:	4b43      	ldr	r3, [pc, #268]	; (2fc4 <compare_set+0x12c>)
    2eb8:	1a30      	subs	r0, r6, r0
    2eba:	eb68 0101 	sbc.w	r1, r8, r1
    2ebe:	4298      	cmp	r0, r3
    2ec0:	f171 0300 	sbcs.w	r3, r1, #0
    2ec4:	d27b      	bcs.n	2fbe <compare_set+0x126>
		if (target_time != cc_data[chan].target_time) {
    2ec6:	4b40      	ldr	r3, [pc, #256]	; (2fc8 <compare_set+0x130>)
    2ec8:	eb03 1305 	add.w	r3, r3, r5, lsl #4
    2ecc:	e9d3 ab02 	ldrd	sl, fp, [r3, #8]
    2ed0:	45d8      	cmp	r8, fp
    2ed2:	bf08      	it	eq
    2ed4:	4556      	cmpeq	r6, sl
    2ed6:	d050      	beq.n	2f7a <compare_set+0xe2>
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2ed8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
	return absolute_time & COUNTER_MAX;
    2edc:	f026 427f 	bic.w	r2, r6, #4278190080	; 0xff000000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    2ee0:	4614      	mov	r4, r2
    2ee2:	ea4f 0985 	mov.w	r9, r5, lsl #2
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    2ee6:	f105 0750 	add.w	r7, r5, #80	; 0x50
    2eea:	f109 2950 	add.w	r9, r9, #1342197760	; 0x50005000
    2eee:	00bf      	lsls	r7, r7, #2
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2ef0:	40ab      	lsls	r3, r5
    2ef2:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2ef6:	b2bf      	uxth	r7, r7
    2ef8:	f107 2750 	add.w	r7, r7, #1342197760	; 0x50005000
    2efc:	9301      	str	r3, [sp, #4]
    return p_reg->CC[ch];
    2efe:	f8d9 0540 	ldr.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    2f02:	4b32      	ldr	r3, [pc, #200]	; (2fcc <compare_set+0x134>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2f04:	f507 3780 	add.w	r7, r7, #65536	; 0x10000
     return p_reg->COUNTER;
    2f08:	f8d3 1504 	ldr.w	r1, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    2f0c:	1a40      	subs	r0, r0, r1
    2f0e:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2f12:	f021 4c7f 	bic.w	ip, r1, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    2f16:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    2f18:	f8c9 c540 	str.w	ip, [r9, #1344]	; 0x540
    2f1c:	d107      	bne.n	2f2e <compare_set+0x96>
    2f1e:	e9cd 2102 	strd	r2, r1, [sp, #8]
	z_impl_k_busy_wait(usec_to_wait);
    2f22:	2013      	movs	r0, #19
    2f24:	f003 fd04 	bl	6930 <z_impl_k_busy_wait>
    2f28:	e9dd 2102 	ldrd	r2, r1, [sp, #8]
    2f2c:	4b27      	ldr	r3, [pc, #156]	; (2fcc <compare_set+0x134>)
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    2f2e:	f101 0c02 	add.w	ip, r1, #2
	return (a - b) & COUNTER_MAX;
    2f32:	eba4 000c 	sub.w	r0, r4, ip
    2f36:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    2f3a:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2f3e:	bf88      	it	hi
    2f40:	4664      	movhi	r4, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2f42:	2000      	movs	r0, #0
    2f44:	6038      	str	r0, [r7, #0]
    2f46:	6838      	ldr	r0, [r7, #0]
    p_reg->EVTENSET = mask;
    2f48:	9801      	ldr	r0, [sp, #4]
    2f4a:	f8c3 0344 	str.w	r0, [r3, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2f4e:	f024 407f 	bic.w	r0, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    2f52:	f8c9 0540 	str.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    2f56:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    2f5a:	4281      	cmp	r1, r0
    2f5c:	d006      	beq.n	2f6c <compare_set+0xd4>
	return (a - b) & COUNTER_MAX;
    2f5e:	1a20      	subs	r0, r4, r0
    2f60:	3802      	subs	r0, #2
    2f62:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    2f66:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2f6a:	d819      	bhi.n	2fa0 <compare_set+0x108>
	return (a - b) & COUNTER_MAX;
    2f6c:	1aa4      	subs	r4, r4, r2
    2f6e:	f024 447f 	bic.w	r4, r4, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    2f72:	eb14 0a06 	adds.w	sl, r4, r6
    2f76:	f148 0b00 	adc.w	fp, r8, #0
	return ret;
    2f7a:	2400      	movs	r4, #0
	cc_data[chan].target_time = target_time;
    2f7c:	4912      	ldr	r1, [pc, #72]	; (2fc8 <compare_set+0x130>)
	cc_data[chan].callback = handler;
    2f7e:	980e      	ldr	r0, [sp, #56]	; 0x38
	cc_data[chan].target_time = target_time;
    2f80:	012b      	lsls	r3, r5, #4
    2f82:	eb01 1205 	add.w	r2, r1, r5, lsl #4
	cc_data[chan].callback = handler;
    2f86:	50c8      	str	r0, [r1, r3]
	cc_data[chan].target_time = target_time;
    2f88:	e9c2 ab02 	strd	sl, fp, [r2, #8]
	cc_data[chan].user_context = user_data;
    2f8c:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    2f8e:	6053      	str	r3, [r2, #4]
	compare_int_unlock(chan, key);
    2f90:	4628      	mov	r0, r5
    2f92:	9900      	ldr	r1, [sp, #0]
    2f94:	f7ff ff36 	bl	2e04 <compare_int_unlock>
}
    2f98:	4620      	mov	r0, r4
    2f9a:	b005      	add	sp, #20
    2f9c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    2fa0:	4620      	mov	r0, r4
    2fa2:	e7b1      	b.n	2f08 <compare_set+0x70>
		atomic_or(&force_isr_mask, BIT(chan));
    2fa4:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    2fa6:	4a0a      	ldr	r2, [pc, #40]	; (2fd0 <compare_set+0x138>)
    2fa8:	40ab      	lsls	r3, r5
    2faa:	e8d2 1fef 	ldaex	r1, [r2]
    2fae:	4319      	orrs	r1, r3
    2fb0:	e8c2 1fe0 	stlex	r0, r1, [r2]
    2fb4:	2800      	cmp	r0, #0
    2fb6:	d1f8      	bne.n	2faa <compare_set+0x112>
    2fb8:	46b2      	mov	sl, r6
    2fba:	46c3      	mov	fp, r8
    2fbc:	e7dd      	b.n	2f7a <compare_set+0xe2>
			return -EINVAL;
    2fbe:	f06f 0415 	mvn.w	r4, #21
    2fc2:	e7e5      	b.n	2f90 <compare_set+0xf8>
    2fc4:	01000001 	.word	0x01000001
    2fc8:	20000428 	.word	0x20000428
    2fcc:	50015000 	.word	0x50015000
    2fd0:	20000b80 	.word	0x20000b80

00002fd4 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    2fd4:	b573      	push	{r0, r1, r4, r5, r6, lr}
    p_reg->PRESCALER = val;
    2fd6:	2400      	movs	r4, #0
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    2fd8:	f04f 30ff 	mov.w	r0, #4294967295
    2fdc:	f04f 31ff 	mov.w	r1, #4294967295
    2fe0:	4d16      	ldr	r5, [pc, #88]	; (303c <sys_clock_driver_init+0x68>)
    2fe2:	4b17      	ldr	r3, [pc, #92]	; (3040 <sys_clock_driver_init+0x6c>)
    2fe4:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    2fe8:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    2fec:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2ff0:	2602      	movs	r6, #2
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2ff2:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    2ff6:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    2ffa:	4b12      	ldr	r3, [pc, #72]	; (3044 <sys_clock_driver_init+0x70>)

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    2ffc:	2101      	movs	r1, #1
    2ffe:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    3002:	2015      	movs	r0, #21
    3004:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    3008:	4622      	mov	r2, r4
    300a:	f7fe fa15 	bl	1438 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    300e:	2015      	movs	r0, #21
    3010:	f7fe f9e0 	bl	13d4 <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    3014:	2301      	movs	r3, #1

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    3016:	4a0c      	ldr	r2, [pc, #48]	; (3048 <sys_clock_driver_init+0x74>)
    3018:	60ab      	str	r3, [r5, #8]
    301a:	602b      	str	r3, [r5, #0]
    301c:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    301e:	4b0b      	ldr	r3, [pc, #44]	; (304c <sys_clock_driver_init+0x78>)
    3020:	4a0b      	ldr	r2, [pc, #44]	; (3050 <sys_clock_driver_init+0x7c>)
    3022:	9300      	str	r3, [sp, #0]
    3024:	4620      	mov	r0, r4
    3026:	2300      	movs	r3, #0
    3028:	9401      	str	r4, [sp, #4]
    302a:	f7ff ff35 	bl	2e98 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    302e:	4630      	mov	r0, r6
    3030:	f7fe fefe 	bl	1e30 <z_nrf_clock_control_lf_on>

	return 0;
}
    3034:	4620      	mov	r0, r4
    3036:	b002      	add	sp, #8
    3038:	bd70      	pop	{r4, r5, r6, pc}
    303a:	bf00      	nop
    303c:	50015000 	.word	0x50015000
    3040:	20000428 	.word	0x20000428
    3044:	e000e100 	.word	0xe000e100
    3048:	20000b84 	.word	0x20000b84
    304c:	00002d8d 	.word	0x00002d8d
    3050:	007fffff 	.word	0x007fffff

00003054 <rtc_nrf_isr>:
    return p_reg->INTENSET & mask;
    3054:	4b35      	ldr	r3, [pc, #212]	; (312c <rtc_nrf_isr+0xd8>)
{
    3056:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    305a:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    305e:	0791      	lsls	r1, r2, #30
    3060:	d50b      	bpl.n	307a <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3062:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    3066:	b142      	cbz	r2, 307a <rtc_nrf_isr+0x26>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3068:	2200      	movs	r2, #0
    306a:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
		overflow_cnt++;
    306e:	4a30      	ldr	r2, [pc, #192]	; (3130 <rtc_nrf_isr+0xdc>)
    3070:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
    3074:	6813      	ldr	r3, [r2, #0]
    3076:	3301      	adds	r3, #1
    3078:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    307a:	f04f 0320 	mov.w	r3, #32
    307e:	f3ef 8111 	mrs	r1, BASEPRI
    3082:	f383 8812 	msr	BASEPRI_MAX, r3
    3086:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    308a:	4b28      	ldr	r3, [pc, #160]	; (312c <rtc_nrf_isr+0xd8>)
    308c:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    3090:	03d2      	lsls	r2, r2, #15
    3092:	d50e      	bpl.n	30b2 <rtc_nrf_isr+0x5e>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    3094:	4a27      	ldr	r2, [pc, #156]	; (3134 <rtc_nrf_isr+0xe0>)
    3096:	e8d2 0fef 	ldaex	r0, [r2]
    309a:	f020 0401 	bic.w	r4, r0, #1
    309e:	e8c2 4fe5 	stlex	r5, r4, [r2]
    30a2:	2d00      	cmp	r5, #0
    30a4:	d1f7      	bne.n	3096 <rtc_nrf_isr+0x42>
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    30a6:	2800      	cmp	r0, #0
    30a8:	d137      	bne.n	311a <rtc_nrf_isr+0xc6>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    30aa:	f8d3 2140 	ldr.w	r2, [r3, #320]	; 0x140
		if (result) {
    30ae:	2a00      	cmp	r2, #0
    30b0:	d133      	bne.n	311a <rtc_nrf_isr+0xc6>
{
    30b2:	2300      	movs	r3, #0
	__asm__ volatile(
    30b4:	f381 8811 	msr	BASEPRI, r1
    30b8:	f3bf 8f6f 	isb	sy
	if (channel_processing_check_and_clear(chan)) {
    30bc:	b353      	cbz	r3, 3114 <rtc_nrf_isr+0xc0>
		curr_time = z_nrf_rtc_timer_read();
    30be:	f7ff fec9 	bl	2e54 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    30c2:	f04f 0320 	mov.w	r3, #32
    30c6:	f3ef 8711 	mrs	r7, BASEPRI
    30ca:	f383 8812 	msr	BASEPRI_MAX, r3
    30ce:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    30d2:	4b19      	ldr	r3, [pc, #100]	; (3138 <rtc_nrf_isr+0xe4>)
    30d4:	e9d3 4502 	ldrd	r4, r5, [r3, #8]
		if (curr_time >= expire_time) {
    30d8:	42a0      	cmp	r0, r4
    30da:	eb71 0205 	sbcs.w	r2, r1, r5
    30de:	f04f 0200 	mov.w	r2, #0
    30e2:	d321      	bcc.n	3128 <rtc_nrf_isr+0xd4>
			user_context = cc_data[chan].user_context;
    30e4:	e9d3 1600 	ldrd	r1, r6, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    30e8:	f04f 38ff 	mov.w	r8, #4294967295
    30ec:	f04f 39ff 	mov.w	r9, #4294967295
			cc_data[chan].callback = NULL;
    30f0:	601a      	str	r2, [r3, #0]
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    30f2:	f44f 3280 	mov.w	r2, #65536	; 0x10000
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    30f6:	e9c3 8902 	strd	r8, r9, [r3, #8]
    30fa:	4b0c      	ldr	r3, [pc, #48]	; (312c <rtc_nrf_isr+0xd8>)
    30fc:	f8c3 2348 	str.w	r2, [r3, #840]	; 0x348
	__asm__ volatile(
    3100:	f387 8811 	msr	BASEPRI, r7
    3104:	f3bf 8f6f 	isb	sy
		if (handler) {
    3108:	b121      	cbz	r1, 3114 <rtc_nrf_isr+0xc0>
			handler(chan, expire_time, user_context);
    310a:	4622      	mov	r2, r4
    310c:	462b      	mov	r3, r5
    310e:	2000      	movs	r0, #0
    3110:	9600      	str	r6, [sp, #0]
    3112:	4788      	blx	r1
}
    3114:	b003      	add	sp, #12
    3116:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    311a:	2200      	movs	r2, #0
    311c:	f8c3 2140 	str.w	r2, [r3, #320]	; 0x140
    3120:	f8d3 3140 	ldr.w	r3, [r3, #320]	; 0x140
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    3124:	2301      	movs	r3, #1
}
    3126:	e7c5      	b.n	30b4 <rtc_nrf_isr+0x60>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    3128:	4611      	mov	r1, r2
    312a:	e7e9      	b.n	3100 <rtc_nrf_isr+0xac>
    312c:	50015000 	.word	0x50015000
    3130:	20000b88 	.word	0x20000b88
    3134:	20000b80 	.word	0x20000b80
    3138:	20000428 	.word	0x20000428

0000313c <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    313c:	1c43      	adds	r3, r0, #1
{
    313e:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3140:	d020      	beq.n	3184 <sys_clock_set_timeout+0x48>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    3142:	2801      	cmp	r0, #1
    3144:	dd20      	ble.n	3188 <sys_clock_set_timeout+0x4c>
    3146:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    314a:	da1f      	bge.n	318c <sys_clock_set_timeout+0x50>
    314c:	1e44      	subs	r4, r0, #1
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    314e:	f7ff fe81 	bl	2e54 <z_nrf_rtc_timer_read>
    3152:	4b0f      	ldr	r3, [pc, #60]	; (3190 <sys_clock_set_timeout+0x54>)
    3154:	e9d3 1300 	ldrd	r1, r3, [r3]
    3158:	1a40      	subs	r0, r0, r1
		ticks = 0;
    315a:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    315e:	bf28      	it	cs
    3160:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    3162:	3001      	adds	r0, #1
    3164:	1902      	adds	r2, r0, r4
	uint64_t target_time = cyc + last_count;
    3166:	480b      	ldr	r0, [pc, #44]	; (3194 <sys_clock_set_timeout+0x58>)
    3168:	4282      	cmp	r2, r0
    316a:	bf28      	it	cs
    316c:	4602      	movcs	r2, r0
    316e:	2000      	movs	r0, #0
    3170:	1852      	adds	r2, r2, r1
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    3172:	4909      	ldr	r1, [pc, #36]	; (3198 <sys_clock_set_timeout+0x5c>)
    3174:	9001      	str	r0, [sp, #4]
    3176:	9100      	str	r1, [sp, #0]
    3178:	f143 0300 	adc.w	r3, r3, #0
    317c:	f7ff fe8c 	bl	2e98 <compare_set>
}
    3180:	b002      	add	sp, #8
    3182:	bd10      	pop	{r4, pc}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3184:	4803      	ldr	r0, [pc, #12]	; (3194 <sys_clock_set_timeout+0x58>)
    3186:	e7e1      	b.n	314c <sys_clock_set_timeout+0x10>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    3188:	2400      	movs	r4, #0
    318a:	e7e0      	b.n	314e <sys_clock_set_timeout+0x12>
    318c:	4c01      	ldr	r4, [pc, #4]	; (3194 <sys_clock_set_timeout+0x58>)
    318e:	e7de      	b.n	314e <sys_clock_set_timeout+0x12>
    3190:	20000438 	.word	0x20000438
    3194:	007fffff 	.word	0x007fffff
    3198:	00002d8d 	.word	0x00002d8d

0000319c <sys_clock_elapsed>:
{
    319c:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    319e:	f7ff fe59 	bl	2e54 <z_nrf_rtc_timer_read>
    31a2:	4b02      	ldr	r3, [pc, #8]	; (31ac <sys_clock_elapsed+0x10>)
    31a4:	681b      	ldr	r3, [r3, #0]
}
    31a6:	1ac0      	subs	r0, r0, r3
    31a8:	bd08      	pop	{r3, pc}
    31aa:	bf00      	nop
    31ac:	20000438 	.word	0x20000438

000031b0 <nrf_gpio_pin_clear>:
        case 1: return NRF_P1;
    31b0:	4a05      	ldr	r2, [pc, #20]	; (31c8 <nrf_gpio_pin_clear+0x18>)
    31b2:	4b06      	ldr	r3, [pc, #24]	; (31cc <nrf_gpio_pin_clear+0x1c>)
    *p_pin = pin_number & 0x1F;
    31b4:	f000 011f 	and.w	r1, r0, #31
    return pin_number >> 5;
    31b8:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
    31ba:	2801      	cmp	r0, #1
    31bc:	bf08      	it	eq
    31be:	4613      	moveq	r3, r2
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    31c0:	2201      	movs	r2, #1
    31c2:	408a      	lsls	r2, r1
    p_reg->OUTCLR = clr_mask;
    31c4:	60da      	str	r2, [r3, #12]
}
    31c6:	4770      	bx	lr
    31c8:	50842800 	.word	0x50842800
    31cc:	50842500 	.word	0x50842500

000031d0 <nrf_pin_configure>:
__unused static void nrf_pin_configure(pinctrl_soc_pin_t pin,
				       nrf_gpio_pin_dir_t dir,
				       nrf_gpio_pin_input_t input)
{
	/* force input direction and disconnected buffer for low power */
	if (NRF_GET_LP(pin) == NRF_LP_ENABLE) {
    31d0:	f400 5380 	and.w	r3, r0, #4096	; 0x1000
{
    31d4:	b570      	push	{r4, r5, r6, lr}
		dir = NRF_GPIO_PIN_DIR_INPUT;
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    31d6:	2b00      	cmp	r3, #0
        case 1: return NRF_P1;
    31d8:	4e0f      	ldr	r6, [pc, #60]	; (3218 <nrf_pin_configure+0x48>)
    31da:	bf0e      	itee	eq
    31dc:	4615      	moveq	r5, r2
    31de:	2501      	movne	r5, #1
    31e0:	2100      	movne	r1, #0
    31e2:	f010 0f20 	tst.w	r0, #32
    31e6:	4b0d      	ldr	r3, [pc, #52]	; (321c <nrf_pin_configure+0x4c>)
    31e8:	bf18      	it	ne
    31ea:	4633      	movne	r3, r6
    *p_pin = pin_number & 0x1F;
    31ec:	f000 041f 	and.w	r4, r0, #31
	}

	nrf_gpio_cfg(NRF_GET_PIN(pin), dir, input, NRF_GET_PULL(pin),
    31f0:	f3c0 1281 	ubfx	r2, r0, #6, #2
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    31f4:	eb03 0384 	add.w	r3, r3, r4, lsl #2
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    31f8:	f400 6070 	and.w	r0, r0, #3840	; 0xf00
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    31fc:	f8d3 4200 	ldr.w	r4, [r3, #512]	; 0x200
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3200:	ea40 0282 	orr.w	r2, r0, r2, lsl #2
    3204:	430a      	orrs	r2, r1
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    3206:	f004 44e0 	and.w	r4, r4, #1879048192	; 0x70000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    320a:	ea42 0245 	orr.w	r2, r2, r5, lsl #1
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    320e:	4322      	orrs	r2, r4
    reg->PIN_CNF[pin_number] = cnf;
    3210:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
		     NRF_GET_DRIVE(pin), NRF_GPIO_PIN_NOSENSE);
}
    3214:	bd70      	pop	{r4, r5, r6, pc}
    3216:	bf00      	nop
    3218:	50842800 	.word	0x50842800
    321c:	50842500 	.word	0x50842500

00003220 <nrf_gpio_pin_set>:
        case 1: return NRF_P1;
    3220:	4a05      	ldr	r2, [pc, #20]	; (3238 <nrf_gpio_pin_set+0x18>)
    3222:	4b06      	ldr	r3, [pc, #24]	; (323c <nrf_gpio_pin_set+0x1c>)
    *p_pin = pin_number & 0x1F;
    3224:	f000 011f 	and.w	r1, r0, #31
    return pin_number >> 5;
    3228:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
    322a:	2801      	cmp	r0, #1
    322c:	bf08      	it	eq
    322e:	4613      	moveq	r3, r2
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3230:	2201      	movs	r2, #1
    3232:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    3234:	609a      	str	r2, [r3, #8]
}
    3236:	4770      	bx	lr
    3238:	50842800 	.word	0x50842800
    323c:	50842500 	.word	0x50842500

00003240 <nrf53_errata_42>:
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    3240:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3244:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    3248:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                #endif
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
    324c:	2a07      	cmp	r2, #7
    324e:	d105      	bne.n	325c <nrf53_errata_42+0x1c>
                {
                    switch(var2)
    3250:	3b02      	subs	r3, #2
    3252:	2b03      	cmp	r3, #3
    3254:	d802      	bhi.n	325c <nrf53_errata_42+0x1c>
    3256:	4a02      	ldr	r2, [pc, #8]	; (3260 <nrf53_errata_42+0x20>)
    3258:	5cd0      	ldrb	r0, [r2, r3]
    325a:	4770      	bx	lr
                            return false;
                    }
                }
            #endif
        #endif
        return false;
    325c:	2000      	movs	r0, #0
    #endif
}
    325e:	4770      	bx	lr
    3260:	00007033 	.word	0x00007033

00003264 <SystemCoreClockUpdate>:
void SystemCoreClockUpdate(void)
{
#if defined(NRF_TRUSTZONE_NONSECURE)
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_NS->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
#else
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_S->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
    3264:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3268:	f8d3 2558 	ldr.w	r2, [r3, #1368]	; 0x558
    326c:	4b03      	ldr	r3, [pc, #12]	; (327c <SystemCoreClockUpdate+0x18>)
    326e:	f002 0203 	and.w	r2, r2, #3
    3272:	40d3      	lsrs	r3, r2
    3274:	4a02      	ldr	r2, [pc, #8]	; (3280 <SystemCoreClockUpdate+0x1c>)
    3276:	6013      	str	r3, [r2, #0]
#endif
}
    3278:	4770      	bx	lr
    327a:	bf00      	nop
    327c:	07a12000 	.word	0x07a12000
    3280:	20000118 	.word	0x20000118

00003284 <SystemInit>:

void SystemInit(void)
{
    3284:	b508      	push	{r3, lr}
            SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
        #endif

        /* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_97())
    3286:	f7ff ffdb 	bl	3240 <nrf53_errata_42>
    328a:	b158      	cbz	r0, 32a4 <SystemInit+0x20>
        {
            if (*((volatile uint32_t *)0x50004A20ul) == 0)
    328c:	4b3f      	ldr	r3, [pc, #252]	; (338c <SystemInit+0x108>)
    328e:	f8d3 2a20 	ldr.w	r2, [r3, #2592]	; 0xa20
    3292:	b93a      	cbnz	r2, 32a4 <SystemInit+0x20>
            {
                *((volatile uint32_t *)0x50004A20ul) = 0xDul;
    3294:	210d      	movs	r1, #13
    3296:	f8c3 1a20 	str.w	r1, [r3, #2592]	; 0xa20
                *((volatile uint32_t *)0x5000491Cul) = 0x1ul;
    329a:	2101      	movs	r1, #1
    329c:	f8c3 191c 	str.w	r1, [r3, #2332]	; 0x91c
                *((volatile uint32_t *)0x5000491Cul) = 0x0ul;
    32a0:	f8c3 291c 	str.w	r2, [r3, #2332]	; 0x91c
{
    32a4:	2200      	movs	r2, #0
    32a6:	00d3      	lsls	r3, r2, #3
    32a8:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    32ac:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
    32b0:	3101      	adds	r1, #1
    32b2:	d007      	beq.n	32c4 <SystemInit+0x40>
            #if defined ( __ICCARM__ )
                /* IAR will complain about the order of volatile pointer accesses. */
                #pragma diag_suppress=Pa082
            #endif
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    32b4:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    32b8:	3201      	adds	r2, #1
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    32ba:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    32be:	2a20      	cmp	r2, #32
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    32c0:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    32c2:	d1f0      	bne.n	32a6 <SystemInit+0x22>
        }

        /* errata 64 must be before errata 42, as errata 42 is dependant on the changes in errata 64*/
        /* Workaround for Errata 64 "VREGMAIN has invalid configuration when CPU is running at 128 MHz" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_64())
    32c4:	f7ff ffbc 	bl	3240 <nrf53_errata_42>
    32c8:	2800      	cmp	r0, #0
    32ca:	d157      	bne.n	337c <SystemInit+0xf8>
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
        }

        /* Workaround for Errata 42 "Reset value of HFCLKCTRL is invalid" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_42())
    32cc:	f7ff ffb8 	bl	3240 <nrf53_errata_42>
    32d0:	b140      	cbz	r0, 32e4 <SystemInit+0x60>
        {
            *((volatile uint32_t *)0x50039530ul) = 0xBEEF0044ul;
    32d2:	4b2f      	ldr	r3, [pc, #188]	; (3390 <SystemInit+0x10c>)
    32d4:	4a2f      	ldr	r2, [pc, #188]	; (3394 <SystemInit+0x110>)
    32d6:	f8c3 2530 	str.w	r2, [r3, #1328]	; 0x530
            NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
    32da:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    32de:	2201      	movs	r2, #1
    32e0:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    32e4:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    32e8:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    32ec:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                #endif
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
    32f0:	2a07      	cmp	r2, #7
    32f2:	d109      	bne.n	3308 <SystemInit+0x84>
                {
                    switch(var2)
    32f4:	3b02      	subs	r3, #2
    32f6:	2b03      	cmp	r3, #3
    32f8:	d806      	bhi.n	3308 <SystemInit+0x84>
        }

        /* Workaround for Errata 46 "Higher power consumption of LFRC" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_46())
    32fa:	4a27      	ldr	r2, [pc, #156]	; (3398 <SystemInit+0x114>)
    32fc:	5cd3      	ldrb	r3, [r2, r3]
    32fe:	b11b      	cbz	r3, 3308 <SystemInit+0x84>
        {
            *((volatile uint32_t *)0x5003254Cul) = 0;
    3300:	2200      	movs	r2, #0
    3302:	4b26      	ldr	r3, [pc, #152]	; (339c <SystemInit+0x118>)
    3304:	f8c3 254c 	str.w	r2, [r3, #1356]	; 0x54c
        }

        /* Workaround for Errata 49 "SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_49())
    3308:	f7ff ff9a 	bl	3240 <nrf53_errata_42>
    330c:	b150      	cbz	r0, 3324 <SystemInit+0xa0>
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
    330e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3312:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    3316:	07d1      	lsls	r1, r2, #31
            {
                NRF_POWER_S->EVENTS_SLEEPENTER = 0;
    3318:	bf42      	ittt	mi
    331a:	2200      	movmi	r2, #0
    331c:	f8c3 2114 	strmi.w	r2, [r3, #276]	; 0x114
                NRF_POWER_S->EVENTS_SLEEPEXIT = 0;
    3320:	f8c3 2118 	strmi.w	r2, [r3, #280]	; 0x118
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    3324:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3328:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    332c:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)\
             || defined (NRF_NETWORK)
                if (var1 == 0x07)
    3330:	2a07      	cmp	r2, #7
    3332:	d109      	bne.n	3348 <SystemInit+0xc4>

        /* Workaround for Errata 55 "Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_55())
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk){
    3334:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3338:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    333c:	07d2      	lsls	r2, r2, #31
                NRF_RESET_S->RESETREAS = ~RESET_RESETREAS_RESETPIN_Msk;
    333e:	bf44      	itt	mi
    3340:	f06f 0201 	mvnmi.w	r2, #1
    3344:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
            }
        }

        /* Workaround for Errata 69 "VREGMAIN configuration is not retained in System OFF" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_69())
    3348:	f7ff ff7a 	bl	3240 <nrf53_errata_42>
    334c:	b118      	cbz	r0, 3356 <SystemInit+0xd2>
        {
            *((volatile uint32_t *)0x5000470Cul) =0x65ul;
    334e:	2265      	movs	r2, #101	; 0x65
    3350:	4b0e      	ldr	r3, [pc, #56]	; (338c <SystemInit+0x108>)
    3352:	f8c3 270c 	str.w	r2, [r3, #1804]	; 0x70c

        #endif

        /* Allow Non-Secure code to run FPU instructions.
         * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
        SCB->NSACR |= (3UL << 10);
    3356:	4a12      	ldr	r2, [pc, #72]	; (33a0 <SystemInit+0x11c>)
    3358:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
    335c:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
    3360:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
                /* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */

        #else
            /* Load APPROTECT soft branch from UICR.
               If UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. */
            NRF_CTRLAP_S->APPROTECT.DISABLE = NRF_UICR_S->APPROTECT;
    3364:	4a0f      	ldr	r2, [pc, #60]	; (33a4 <SystemInit+0x120>)
    3366:	4b10      	ldr	r3, [pc, #64]	; (33a8 <SystemInit+0x124>)
    3368:	6811      	ldr	r1, [r2, #0]
    336a:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
                /* Do nothing, allow user code to handle SECURE APPROTECT. Use this if you want to enable authenticated debug. */

        #else
            /* Load SECURE APPROTECT soft branch from UICR.
               If UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT will be disabled. */
            NRF_CTRLAP_S->SECUREAPPROTECT.DISABLE = NRF_UICR_S->SECUREAPPROTECT;
    336e:	69d2      	ldr	r2, [r2, #28]
    3370:	f8c3 254c 	str.w	r2, [r3, #1356]	; 0x54c
        __DSB();
        __ISB();
    #endif

    SystemCoreClockUpdate();
}
    3374:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    SystemCoreClockUpdate();
    3378:	f7ff bf74 	b.w	3264 <SystemCoreClockUpdate>
            *((volatile uint32_t *)0x5000470Cul) = 0x29ul;
    337c:	2229      	movs	r2, #41	; 0x29
    337e:	4b03      	ldr	r3, [pc, #12]	; (338c <SystemInit+0x108>)
    3380:	f8c3 270c 	str.w	r2, [r3, #1804]	; 0x70c
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
    3384:	2203      	movs	r2, #3
    3386:	f8c3 273c 	str.w	r2, [r3, #1852]	; 0x73c
    338a:	e79f      	b.n	32cc <SystemInit+0x48>
    338c:	50004000 	.word	0x50004000
    3390:	50039000 	.word	0x50039000
    3394:	beef0044 	.word	0xbeef0044
    3398:	00007037 	.word	0x00007037
    339c:	50032000 	.word	0x50032000
    33a0:	e000ed00 	.word	0xe000ed00
    33a4:	00ff8000 	.word	0x00ff8000
    33a8:	50006000 	.word	0x50006000

000033ac <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    33ac:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    33ae:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    33b0:	6802      	ldr	r2, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    33b2:	fab2 f382 	clz	r3, r2
    33b6:	f1c3 031f 	rsb	r3, r3, #31
        if (idx < 0) {
    33ba:	1c5e      	adds	r6, r3, #1
        idx = 31 - NRF_CLZ(prev_mask);
    33bc:	b2dc      	uxtb	r4, r3
        if (idx < 0) {
    33be:	d010      	beq.n	33e2 <nrfx_flag32_alloc+0x36>
        new_mask = prev_mask & ~NRFX_BIT(idx);
    33c0:	fa05 f303 	lsl.w	r3, r5, r3
    33c4:	ea22 0303 	bic.w	r3, r2, r3
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    33c8:	e8d0 6fef 	ldaex	r6, [r0]
    33cc:	4296      	cmp	r6, r2
    33ce:	d104      	bne.n	33da <nrfx_flag32_alloc+0x2e>
    33d0:	e8c0 3fec 	stlex	ip, r3, [r0]
    33d4:	f1bc 0f00 	cmp.w	ip, #0
    33d8:	d1f6      	bne.n	33c8 <nrfx_flag32_alloc+0x1c>
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    33da:	d1e9      	bne.n	33b0 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
    33dc:	4802      	ldr	r0, [pc, #8]	; (33e8 <nrfx_flag32_alloc+0x3c>)
    *p_flag = idx;
    33de:	700c      	strb	r4, [r1, #0]
}
    33e0:	bd70      	pop	{r4, r5, r6, pc}
            return NRFX_ERROR_NO_MEM;
    33e2:	4802      	ldr	r0, [pc, #8]	; (33ec <nrfx_flag32_alloc+0x40>)
    33e4:	e7fc      	b.n	33e0 <nrfx_flag32_alloc+0x34>
    33e6:	bf00      	nop
    33e8:	0bad0000 	.word	0x0bad0000
    33ec:	0bad0002 	.word	0x0bad0002

000033f0 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    33f0:	6803      	ldr	r3, [r0, #0]
{
    33f2:	b510      	push	{r4, lr}
    if ((NRFX_BIT(flag) & *p_mask))
    33f4:	40cb      	lsrs	r3, r1
    33f6:	07db      	lsls	r3, r3, #31
    33f8:	d411      	bmi.n	341e <nrfx_flag32_free+0x2e>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    33fa:	2301      	movs	r3, #1
    33fc:	fa03 f101 	lsl.w	r1, r3, r1
        prev_mask = *p_mask;
    3400:	6803      	ldr	r3, [r0, #0]
        new_mask = prev_mask | NRFX_BIT(flag);
    3402:	ea41 0203 	orr.w	r2, r1, r3
    3406:	e8d0 4fef 	ldaex	r4, [r0]
    340a:	429c      	cmp	r4, r3
    340c:	d104      	bne.n	3418 <nrfx_flag32_free+0x28>
    340e:	e8c0 2fec 	stlex	ip, r2, [r0]
    3412:	f1bc 0f00 	cmp.w	ip, #0
    3416:	d1f6      	bne.n	3406 <nrfx_flag32_free+0x16>
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    3418:	d1f2      	bne.n	3400 <nrfx_flag32_free+0x10>

    return NRFX_SUCCESS;
    341a:	4802      	ldr	r0, [pc, #8]	; (3424 <nrfx_flag32_free+0x34>)
}
    341c:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    341e:	4802      	ldr	r0, [pc, #8]	; (3428 <nrfx_flag32_free+0x38>)
    3420:	e7fc      	b.n	341c <nrfx_flag32_free+0x2c>
    3422:	bf00      	nop
    3424:	0bad0000 	.word	0x0bad0000
    3428:	0bad0004 	.word	0x0bad0004

0000342c <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    342c:	4b04      	ldr	r3, [pc, #16]	; (3440 <nrfx_clock_init+0x14>)
    342e:	791a      	ldrb	r2, [r3, #4]
    3430:	b922      	cbnz	r2, 343c <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    3432:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    3434:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    3436:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    3438:	4802      	ldr	r0, [pc, #8]	; (3444 <nrfx_clock_init+0x18>)
    343a:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    343c:	4802      	ldr	r0, [pc, #8]	; (3448 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    343e:	4770      	bx	lr
    3440:	20000b8c 	.word	0x20000b8c
    3444:	0bad0000 	.word	0x0bad0000
    3448:	0bad000c 	.word	0x0bad000c

0000344c <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    344c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3450:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    3454:	b510      	push	{r4, lr}
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    3456:	b152      	cbz	r2, 346e <nrfx_power_clock_irq_handler+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3458:	2000      	movs	r0, #0
    345a:	f8c3 0100 	str.w	r0, [r3, #256]	; 0x100
    345e:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    3462:	2201      	movs	r2, #1
    3464:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    3468:	4b23      	ldr	r3, [pc, #140]	; (34f8 <nrfx_power_clock_irq_handler+0xac>)
    346a:	681b      	ldr	r3, [r3, #0]
    346c:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    346e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3472:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    3476:	b18a      	cbz	r2, 349c <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3478:	2200      	movs	r2, #0
    347a:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    347e:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3482:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3486:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    348a:	f002 0203 	and.w	r2, r2, #3
    348e:	2a01      	cmp	r2, #1
    3490:	f04f 0102 	mov.w	r1, #2
    3494:	d128      	bne.n	34e8 <nrfx_power_clock_irq_handler+0x9c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    3496:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    349a:	609a      	str	r2, [r3, #8]
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    349c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    34a0:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    }
#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)

#if NRF_CLOCK_HAS_HFCLKAUDIO
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED))
    34a4:	b162      	cbz	r2, 34c0 <nrfx_power_clock_irq_handler+0x74>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    34a6:	2200      	movs	r2, #0
    34a8:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    34ac:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    p_reg->INTENCLR = mask;
    34b0:	f44f 7280 	mov.w	r2, #256	; 0x100
    34b4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED);
    34b8:	4b0f      	ldr	r3, [pc, #60]	; (34f8 <nrfx_power_clock_irq_handler+0xac>)
    34ba:	2004      	movs	r0, #4
    34bc:	681b      	ldr	r3, [r3, #0]
    34be:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    34c0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    34c4:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    }
#endif

#if NRF_CLOCK_HAS_HFCLK192M
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED))
    34c8:	b1aa      	cbz	r2, 34f6 <nrfx_power_clock_irq_handler+0xaa>
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    34ca:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    34ce:	2200      	movs	r2, #0
    34d0:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    34d4:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    p_reg->INTENCLR = mask;
    34d8:	f44f 7200 	mov.w	r2, #512	; 0x200
    34dc:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    34e0:	4b05      	ldr	r3, [pc, #20]	; (34f8 <nrfx_power_clock_irq_handler+0xac>)
    34e2:	2005      	movs	r0, #5
    34e4:	681b      	ldr	r3, [r3, #0]
    34e6:	4718      	bx	r3
    34e8:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    34ec:	4b02      	ldr	r3, [pc, #8]	; (34f8 <nrfx_power_clock_irq_handler+0xac>)
    34ee:	2001      	movs	r0, #1
    34f0:	681b      	ldr	r3, [r3, #0]
    34f2:	4798      	blx	r3
    34f4:	e7d2      	b.n	349c <nrfx_power_clock_irq_handler+0x50>
}
    34f6:	bd10      	pop	{r4, pc}
    34f8:	20000b8c 	.word	0x20000b8c

000034fc <nrfx_dppi_channel_alloc>:
    // Clear all allocated groups.
    m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK;
}

nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel)
{
    34fc:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_allocated_channels, p_channel);
    34fe:	4801      	ldr	r0, [pc, #4]	; (3504 <nrfx_dppi_channel_alloc+0x8>)
    3500:	f7ff bf54 	b.w	33ac <nrfx_flag32_alloc>
    3504:	2000011c 	.word	0x2000011c

00003508 <nrfx_dppi_channel_enable>:

nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel)
{
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!nrfx_flag32_is_allocated(m_allocated_channels, channel))
    3508:	4b08      	ldr	r3, [pc, #32]	; (352c <nrfx_dppi_channel_enable+0x24>)
{
    350a:	b510      	push	{r4, lr}
    if (!nrfx_flag32_is_allocated(m_allocated_channels, channel))
    350c:	4601      	mov	r1, r0
{
    350e:	4604      	mov	r4, r0
    if (!nrfx_flag32_is_allocated(m_allocated_channels, channel))
    3510:	6818      	ldr	r0, [r3, #0]
    3512:	f002 ff1b 	bl	634c <nrfx_flag32_is_allocated>
    3516:	b130      	cbz	r0, 3526 <nrfx_dppi_channel_enable+0x1e>
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    }
    else
    {
        nrf_dppi_channels_enable(NRF_DPPIC, DPPI_BIT_SET(channel));
    3518:	2001      	movs	r0, #1
    351a:	4b05      	ldr	r3, [pc, #20]	; (3530 <nrfx_dppi_channel_enable+0x28>)
    351c:	40a0      	lsls	r0, r4
    351e:	f8c3 0504 	str.w	r0, [r3, #1284]	; 0x504
    nrfx_err_t err_code = NRFX_SUCCESS;
    3522:	4804      	ldr	r0, [pc, #16]	; (3534 <nrfx_dppi_channel_enable+0x2c>)
    }
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3524:	bd10      	pop	{r4, pc}
        err_code = NRFX_ERROR_INVALID_PARAM;
    3526:	4804      	ldr	r0, [pc, #16]	; (3538 <nrfx_dppi_channel_enable+0x30>)
    return err_code;
    3528:	e7fc      	b.n	3524 <nrfx_dppi_channel_enable+0x1c>
    352a:	bf00      	nop
    352c:	2000011c 	.word	0x2000011c
    3530:	50017000 	.word	0x50017000
    3534:	0bad0000 	.word	0x0bad0000
    3538:	0bad0004 	.word	0x0bad0004

0000353c <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    353c:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    353e:	f003 021f 	and.w	r2, r3, #31
    3542:	6002      	str	r2, [r0, #0]
}
    3544:	4a03      	ldr	r2, [pc, #12]	; (3554 <nrf_gpio_pin_port_decode+0x18>)
    3546:	4804      	ldr	r0, [pc, #16]	; (3558 <nrf_gpio_pin_port_decode+0x1c>)
    return pin_number >> 5;
    3548:	095b      	lsrs	r3, r3, #5
}
    354a:	2b01      	cmp	r3, #1
    354c:	bf08      	it	eq
    354e:	4610      	moveq	r0, r2
    3550:	4770      	bx	lr
    3552:	bf00      	nop
    3554:	50842800 	.word	0x50842800
    3558:	50842500 	.word	0x50842500

0000355c <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    355c:	4b03      	ldr	r3, [pc, #12]	; (356c <pin_in_use_by_te+0x10>)
    355e:	3008      	adds	r0, #8
    3560:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    3564:	f3c0 1040 	ubfx	r0, r0, #5, #1
    3568:	4770      	bx	lr
    356a:	bf00      	nop
    356c:	20000120 	.word	0x20000120

00003570 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    3570:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3572:	4c0d      	ldr	r4, [pc, #52]	; (35a8 <call_handler+0x38>)
    3574:	f100 0308 	add.w	r3, r0, #8
    3578:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
{
    357c:	4605      	mov	r5, r0
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    357e:	05da      	lsls	r2, r3, #23
{
    3580:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3582:	d507      	bpl.n	3594 <call_handler+0x24>
    3584:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    3588:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    358c:	6852      	ldr	r2, [r2, #4]
    358e:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    3592:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    3594:	68a3      	ldr	r3, [r4, #8]
    3596:	b12b      	cbz	r3, 35a4 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    3598:	4631      	mov	r1, r6
    359a:	4628      	mov	r0, r5
    359c:	68e2      	ldr	r2, [r4, #12]
    }
}
    359e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    35a2:	4718      	bx	r3
}
    35a4:	bd70      	pop	{r4, r5, r6, pc}
    35a6:	bf00      	nop
    35a8:	20000120 	.word	0x20000120

000035ac <release_handler>:
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    35ac:	4a12      	ldr	r2, [pc, #72]	; (35f8 <release_handler+0x4c>)
    35ae:	3008      	adds	r0, #8
    35b0:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
{
    35b4:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    35b6:	05d9      	lsls	r1, r3, #23
    35b8:	d51b      	bpl.n	35f2 <release_handler+0x46>
    35ba:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    35be:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    35c2:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    35c6:	2000      	movs	r0, #0
    35c8:	f102 0410 	add.w	r4, r2, #16
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    35cc:	f834 3b02 	ldrh.w	r3, [r4], #2
    35d0:	f413 7f80 	tst.w	r3, #256	; 0x100
    35d4:	d003      	beq.n	35de <release_handler+0x32>
    35d6:	f3c3 2343 	ubfx	r3, r3, #9, #4
    35da:	4299      	cmp	r1, r3
    35dc:	d009      	beq.n	35f2 <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    35de:	3001      	adds	r0, #1
    35e0:	2830      	cmp	r0, #48	; 0x30
    35e2:	d1f3      	bne.n	35cc <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    35e4:	2300      	movs	r3, #0
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    35e6:	4805      	ldr	r0, [pc, #20]	; (35fc <release_handler+0x50>)
}
    35e8:	bc10      	pop	{r4}
        m_cb.handlers[handler_id].handler = NULL;
    35ea:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    35ee:	f7ff beff 	b.w	33f0 <nrfx_flag32_free>
}
    35f2:	bc10      	pop	{r4}
    35f4:	4770      	bx	lr
    35f6:	bf00      	nop
    35f8:	20000120 	.word	0x20000120
    35fc:	20000194 	.word	0x20000194

00003600 <pin_handler_trigger_uninit>:
{
    3600:	b538      	push	{r3, r4, r5, lr}
    3602:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3604:	f7ff ffaa 	bl	355c <pin_in_use_by_te>
    3608:	4c0b      	ldr	r4, [pc, #44]	; (3638 <pin_handler_trigger_uninit+0x38>)
    360a:	f102 0508 	add.w	r5, r2, #8
    360e:	b160      	cbz	r0, 362a <pin_handler_trigger_uninit+0x2a>
    p_reg->CONFIG[idx] = 0;
    3610:	2100      	movs	r1, #0
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3612:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    3616:	0b5b      	lsrs	r3, r3, #13
    3618:	009b      	lsls	r3, r3, #2
    361a:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    361e:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    3622:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    3626:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    release_handler(pin);
    362a:	4610      	mov	r0, r2
    362c:	f7ff ffbe 	bl	35ac <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    3630:	2300      	movs	r3, #0
    3632:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    3636:	bd38      	pop	{r3, r4, r5, pc}
    3638:	20000120 	.word	0x20000120

0000363c <nrfx_gpiote_input_configure>:
{
    363c:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    3640:	4604      	mov	r4, r0
    3642:	4616      	mov	r6, r2
    3644:	461d      	mov	r5, r3
    if (p_input_config)
    3646:	b321      	cbz	r1, 3692 <nrfx_gpiote_input_configure+0x56>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3648:	4f4e      	ldr	r7, [pc, #312]	; (3784 <nrfx_gpiote_input_configure+0x148>)
    364a:	f100 0808 	add.w	r8, r0, #8
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    364e:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    3652:	079b      	lsls	r3, r3, #30
    3654:	d506      	bpl.n	3664 <nrfx_gpiote_input_configure+0x28>
    3656:	f7ff ff81 	bl	355c <pin_in_use_by_te>
        if (pin_is_task_output(pin))
    365a:	b118      	cbz	r0, 3664 <nrfx_gpiote_input_configure+0x28>
                return NRFX_ERROR_INVALID_PARAM;
    365c:	484a      	ldr	r0, [pc, #296]	; (3788 <nrfx_gpiote_input_configure+0x14c>)
}
    365e:	b004      	add	sp, #16
    3660:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    3664:	2300      	movs	r3, #0
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    3666:	4620      	mov	r0, r4
    3668:	e9cd 3300 	strd	r3, r3, [sp]
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    366c:	f88d 300e 	strb.w	r3, [sp, #14]
        nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT;
    3670:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    3674:	f10d 020f 	add.w	r2, sp, #15
    3678:	460b      	mov	r3, r1
    367a:	f10d 010e 	add.w	r1, sp, #14
    367e:	f002 ff59 	bl	6534 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    3682:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    3686:	f023 0302 	bic.w	r3, r3, #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    368a:	f043 0301 	orr.w	r3, r3, #1
    368e:	f827 3018 	strh.w	r3, [r7, r8, lsl #1]
    if (p_trigger_config)
    3692:	b196      	cbz	r6, 36ba <nrfx_gpiote_input_configure+0x7e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3694:	483b      	ldr	r0, [pc, #236]	; (3784 <nrfx_gpiote_input_configure+0x148>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    3696:	7833      	ldrb	r3, [r6, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    3698:	6872      	ldr	r2, [r6, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    369a:	f104 0608 	add.w	r6, r4, #8
    369e:	f830 1016 	ldrh.w	r1, [r0, r6, lsl #1]
        if (pin_is_output(pin))
    36a2:	078f      	lsls	r7, r1, #30
    36a4:	d50c      	bpl.n	36c0 <nrfx_gpiote_input_configure+0x84>
            if (use_evt)
    36a6:	2a00      	cmp	r2, #0
    36a8:	d1d8      	bne.n	365c <nrfx_gpiote_input_configure+0x20>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    36aa:	f830 2016 	ldrh.w	r2, [r0, r6, lsl #1]
    36ae:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    36b2:	ea42 0383 	orr.w	r3, r2, r3, lsl #2
    36b6:	f820 3016 	strh.w	r3, [r0, r6, lsl #1]
    if (p_handler_config)
    36ba:	bbcd      	cbnz	r5, 3730 <nrfx_gpiote_input_configure+0xf4>
    return NRFX_SUCCESS;
    36bc:	4833      	ldr	r0, [pc, #204]	; (378c <nrfx_gpiote_input_configure+0x150>)
    36be:	e7ce      	b.n	365e <nrfx_gpiote_input_configure+0x22>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    36c0:	f021 0120 	bic.w	r1, r1, #32
    36c4:	04c9      	lsls	r1, r1, #19
    36c6:	0cc9      	lsrs	r1, r1, #19
    36c8:	f820 1016 	strh.w	r1, [r0, r6, lsl #1]
            if (use_evt)
    36cc:	2a00      	cmp	r2, #0
    36ce:	d0ec      	beq.n	36aa <nrfx_gpiote_input_configure+0x6e>
                if (!edge)
    36d0:	2b03      	cmp	r3, #3
    36d2:	d8c3      	bhi.n	365c <nrfx_gpiote_input_configure+0x20>
                uint8_t ch = *p_trigger_config->p_in_channel;
    36d4:	f892 c000 	ldrb.w	ip, [r2]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    36d8:	4662      	mov	r2, ip
    36da:	0092      	lsls	r2, r2, #2
    36dc:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    36e0:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
    36e4:	b923      	cbnz	r3, 36f0 <nrfx_gpiote_input_configure+0xb4>
    p_reg->CONFIG[idx] = 0;
    36e6:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    36ea:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
}
    36ee:	e7dc      	b.n	36aa <nrfx_gpiote_input_configure+0x6e>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    36f0:	f8d2 7510 	ldr.w	r7, [r2, #1296]	; 0x510
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    36f4:	ea41 314c 	orr.w	r1, r1, ip, lsl #13
    36f8:	f027 0703 	bic.w	r7, r7, #3
    36fc:	f8c2 7510 	str.w	r7, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    3700:	f8d2 7510 	ldr.w	r7, [r2, #1296]	; 0x510
    3704:	f041 0120 	orr.w	r1, r1, #32
    3708:	f427 374f 	bic.w	r7, r7, #211968	; 0x33c00
    370c:	f427 7740 	bic.w	r7, r7, #768	; 0x300
    3710:	f8c2 7510 	str.w	r7, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3714:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    3718:	0227      	lsls	r7, r4, #8
    371a:	f407 577c 	and.w	r7, r7, #16128	; 0x3f00
    371e:	ea4e 4e03 	orr.w	lr, lr, r3, lsl #16
    3722:	ea47 070e 	orr.w	r7, r7, lr
    3726:	f8c2 7510 	str.w	r7, [r2, #1296]	; 0x510
    372a:	f820 1016 	strh.w	r1, [r0, r6, lsl #1]
    372e:	e7bc      	b.n	36aa <nrfx_gpiote_input_configure+0x6e>
    release_handler(pin);
    3730:	4620      	mov	r0, r4
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    3732:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    3736:	f7ff ff39 	bl	35ac <release_handler>
    if (!handler)
    373a:	2e00      	cmp	r6, #0
    373c:	d0be      	beq.n	36bc <nrfx_gpiote_input_configure+0x80>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    373e:	4d11      	ldr	r5, [pc, #68]	; (3784 <nrfx_gpiote_input_configure+0x148>)
    3740:	682b      	ldr	r3, [r5, #0]
    3742:	429e      	cmp	r6, r3
    3744:	d104      	bne.n	3750 <nrfx_gpiote_input_configure+0x114>
    3746:	686b      	ldr	r3, [r5, #4]
    3748:	429f      	cmp	r7, r3
    374a:	d101      	bne.n	3750 <nrfx_gpiote_input_configure+0x114>
    374c:	2200      	movs	r2, #0
    374e:	e00a      	b.n	3766 <nrfx_gpiote_input_configure+0x12a>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    3750:	480f      	ldr	r0, [pc, #60]	; (3790 <nrfx_gpiote_input_configure+0x154>)
    3752:	f10d 010f 	add.w	r1, sp, #15
    3756:	f7ff fe29 	bl	33ac <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    375a:	4b0c      	ldr	r3, [pc, #48]	; (378c <nrfx_gpiote_input_configure+0x150>)
    375c:	4298      	cmp	r0, r3
    375e:	f47f af7e 	bne.w	365e <nrfx_gpiote_input_configure+0x22>
        handler_id = (int32_t)id;
    3762:	f89d 200f 	ldrb.w	r2, [sp, #15]
    m_cb.handlers[handler_id].p_context = p_context;
    3766:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    376a:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    376c:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    376e:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    m_cb.handlers[handler_id].handler = handler;
    3772:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3776:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    377a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    377e:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    3782:	e79b      	b.n	36bc <nrfx_gpiote_input_configure+0x80>
    3784:	20000120 	.word	0x20000120
    3788:	0bad0004 	.word	0x0bad0004
    378c:	0bad0000 	.word	0x0bad0000
    3790:	20000194 	.word	0x20000194

00003794 <nrfx_gpiote_output_configure>:
{
    3794:	b5f0      	push	{r4, r5, r6, r7, lr}
    3796:	4604      	mov	r4, r0
    3798:	4615      	mov	r5, r2
    379a:	b085      	sub	sp, #20
    if (p_config)
    379c:	b319      	cbz	r1, 37e6 <nrfx_gpiote_output_configure+0x52>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    379e:	4e34      	ldr	r6, [pc, #208]	; (3870 <nrfx_gpiote_output_configure+0xdc>)
    37a0:	f100 0708 	add.w	r7, r0, #8
    37a4:	f836 2017 	ldrh.w	r2, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    37a8:	0793      	lsls	r3, r2, #30
    37aa:	d403      	bmi.n	37b4 <nrfx_gpiote_output_configure+0x20>
    37ac:	f7ff fed6 	bl	355c <pin_in_use_by_te>
    37b0:	2800      	cmp	r0, #0
    37b2:	d15a      	bne.n	386a <nrfx_gpiote_output_configure+0xd6>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    37b4:	f012 0f1c 	tst.w	r2, #28
    37b8:	d002      	beq.n	37c0 <nrfx_gpiote_output_configure+0x2c>
    37ba:	784b      	ldrb	r3, [r1, #1]
    37bc:	2b01      	cmp	r3, #1
    37be:	d054      	beq.n	386a <nrfx_gpiote_output_configure+0xd6>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT;
    37c0:	2301      	movs	r3, #1
    37c2:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull,
    37c6:	2300      	movs	r3, #0
    37c8:	1c4a      	adds	r2, r1, #1
    37ca:	e9cd 1300 	strd	r1, r3, [sp]
    37ce:	4620      	mov	r0, r4
    37d0:	1c8b      	adds	r3, r1, #2
    37d2:	f10d 010f 	add.w	r1, sp, #15
    37d6:	f002 fead 	bl	6534 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    37da:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    37de:	f043 0303 	orr.w	r3, r3, #3
    37e2:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_task_config)
    37e6:	b915      	cbnz	r5, 37ee <nrfx_gpiote_output_configure+0x5a>
    return NRFX_SUCCESS;
    37e8:	4822      	ldr	r0, [pc, #136]	; (3874 <nrfx_gpiote_output_configure+0xe0>)
}
    37ea:	b005      	add	sp, #20
    37ec:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    37ee:	4e20      	ldr	r6, [pc, #128]	; (3870 <nrfx_gpiote_output_configure+0xdc>)
    37f0:	f104 0708 	add.w	r7, r4, #8
    37f4:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    37f8:	0783      	lsls	r3, r0, #30
    37fa:	d536      	bpl.n	386a <nrfx_gpiote_output_configure+0xd6>
        uint32_t ch = p_task_config->task_ch;
    37fc:	f895 c000 	ldrb.w	ip, [r5]
    p_reg->CONFIG[idx] = 0;
    3800:	2300      	movs	r3, #0
    3802:	4661      	mov	r1, ip
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    3804:	f020 0020 	bic.w	r0, r0, #32
    3808:	0089      	lsls	r1, r1, #2
    380a:	f101 41a0 	add.w	r1, r1, #1342177280	; 0x50000000
    380e:	04c0      	lsls	r0, r0, #19
    3810:	f501 4150 	add.w	r1, r1, #53248	; 0xd000
    3814:	0cc0      	lsrs	r0, r0, #19
    3816:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    381a:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    p_reg->CONFIG[idx] = 0;
    381e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    3822:	786a      	ldrb	r2, [r5, #1]
    3824:	2a00      	cmp	r2, #0
    3826:	d0df      	beq.n	37e8 <nrfx_gpiote_output_configure+0x54>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    3828:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
            nrf_gpiote_task_configure(NRF_GPIOTE, ch, pin,
    382c:	78ad      	ldrb	r5, [r5, #2]
    382e:	f423 1399 	bic.w	r3, r3, #1253376	; 0x132000
    3832:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3836:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    383a:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    383e:	0223      	lsls	r3, r4, #8
    3840:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    3844:	0412      	lsls	r2, r2, #16
    3846:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    384a:	ea43 030e 	orr.w	r3, r3, lr
    384e:	4313      	orrs	r3, r2
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    3850:	052a      	lsls	r2, r5, #20
    3852:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3856:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    385a:	4313      	orrs	r3, r2
    385c:	f040 0020 	orr.w	r0, r0, #32
    3860:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    3864:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3868:	e7be      	b.n	37e8 <nrfx_gpiote_output_configure+0x54>
            return NRFX_ERROR_INVALID_PARAM;
    386a:	4803      	ldr	r0, [pc, #12]	; (3878 <nrfx_gpiote_output_configure+0xe4>)
    386c:	e7bd      	b.n	37ea <nrfx_gpiote_output_configure+0x56>
    386e:	bf00      	nop
    3870:	20000120 	.word	0x20000120
    3874:	0bad0000 	.word	0x0bad0000
    3878:	0bad0004 	.word	0x0bad0004

0000387c <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    387c:	4b01      	ldr	r3, [pc, #4]	; (3884 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    387e:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    3882:	4770      	bx	lr
    3884:	20000120 	.word	0x20000120

00003888 <nrfx_gpiote_channel_get>:
{
    3888:	b508      	push	{r3, lr}
    388a:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    388c:	f7ff fe66 	bl	355c <pin_in_use_by_te>
    3890:	b138      	cbz	r0, 38a2 <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3892:	4b05      	ldr	r3, [pc, #20]	; (38a8 <nrfx_gpiote_channel_get+0x20>)
    3894:	3208      	adds	r2, #8
    3896:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
        return NRFX_SUCCESS;
    389a:	4804      	ldr	r0, [pc, #16]	; (38ac <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    389c:	0b5b      	lsrs	r3, r3, #13
    389e:	700b      	strb	r3, [r1, #0]
}
    38a0:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    38a2:	4803      	ldr	r0, [pc, #12]	; (38b0 <nrfx_gpiote_channel_get+0x28>)
    38a4:	e7fc      	b.n	38a0 <nrfx_gpiote_channel_get+0x18>
    38a6:	bf00      	nop
    38a8:	20000120 	.word	0x20000120
    38ac:	0bad0000 	.word	0x0bad0000
    38b0:	0bad0004 	.word	0x0bad0004

000038b4 <nrfx_gpiote_init>:
{
    38b4:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    38b6:	4c0f      	ldr	r4, [pc, #60]	; (38f4 <nrfx_gpiote_init+0x40>)
    38b8:	f894 5078 	ldrb.w	r5, [r4, #120]	; 0x78
    38bc:	b9bd      	cbnz	r5, 38ee <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    38be:	2260      	movs	r2, #96	; 0x60
    38c0:	4629      	mov	r1, r5
    38c2:	f104 0010 	add.w	r0, r4, #16
    38c6:	f001 fddd 	bl	5484 <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    38ca:	200d      	movs	r0, #13
    38cc:	f7fd fd82 	bl	13d4 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    38d0:	4b09      	ldr	r3, [pc, #36]	; (38f8 <nrfx_gpiote_init+0x44>)
    return err_code;
    38d2:	480a      	ldr	r0, [pc, #40]	; (38fc <nrfx_gpiote_init+0x48>)
    38d4:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    38d8:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    38dc:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    38e0:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    38e4:	2301      	movs	r3, #1
    38e6:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    38ea:	6763      	str	r3, [r4, #116]	; 0x74
}
    38ec:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    38ee:	4804      	ldr	r0, [pc, #16]	; (3900 <nrfx_gpiote_init+0x4c>)
    38f0:	e7fc      	b.n	38ec <nrfx_gpiote_init+0x38>
    38f2:	bf00      	nop
    38f4:	20000120 	.word	0x20000120
    38f8:	5000d000 	.word	0x5000d000
    38fc:	0bad0000 	.word	0x0bad0000
    3900:	0bad0005 	.word	0x0bad0005

00003904 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    3904:	4b03      	ldr	r3, [pc, #12]	; (3914 <nrfx_gpiote_is_init+0x10>)
    3906:	f893 0078 	ldrb.w	r0, [r3, #120]	; 0x78
}
    390a:	3800      	subs	r0, #0
    390c:	bf18      	it	ne
    390e:	2001      	movne	r0, #1
    3910:	4770      	bx	lr
    3912:	bf00      	nop
    3914:	20000120 	.word	0x20000120

00003918 <nrfx_gpiote_channel_free>:
{
    3918:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    391a:	4801      	ldr	r0, [pc, #4]	; (3920 <nrfx_gpiote_channel_free+0x8>)
    391c:	f7ff bd68 	b.w	33f0 <nrfx_flag32_free>
    3920:	20000190 	.word	0x20000190

00003924 <nrfx_gpiote_channel_alloc>:
{
    3924:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    3926:	4801      	ldr	r0, [pc, #4]	; (392c <nrfx_gpiote_channel_alloc+0x8>)
    3928:	f7ff bd40 	b.w	33ac <nrfx_flag32_alloc>
    392c:	20000190 	.word	0x20000190

00003930 <nrfx_gpiote_trigger_enable>:
{
    3930:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3932:	4604      	mov	r4, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3934:	f7ff fe12 	bl	355c <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3938:	4b1e      	ldr	r3, [pc, #120]	; (39b4 <nrfx_gpiote_trigger_enable+0x84>)
    393a:	f104 0208 	add.w	r2, r4, #8
    393e:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3942:	b1e8      	cbz	r0, 3980 <nrfx_gpiote_trigger_enable+0x50>
    3944:	f013 0502 	ands.w	r5, r3, #2
    3948:	d11a      	bne.n	3980 <nrfx_gpiote_trigger_enable+0x50>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    394a:	0b5b      	lsrs	r3, r3, #13
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    394c:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    394e:	f102 40a0 	add.w	r0, r2, #1342177280	; 0x50000000
    3952:	f500 4051 	add.w	r0, r0, #53504	; 0xd100
    3956:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    395a:	6005      	str	r5, [r0, #0]
    395c:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
    3960:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    3962:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3966:	f040 0001 	orr.w	r0, r0, #1
    396a:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    396e:	b129      	cbz	r1, 397c <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    3970:	2201      	movs	r2, #1
    3972:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    3976:	4a10      	ldr	r2, [pc, #64]	; (39b8 <nrfx_gpiote_trigger_enable+0x88>)
    3978:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    397c:	b003      	add	sp, #12
    397e:	bd30      	pop	{r4, r5, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3980:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    3984:	2b04      	cmp	r3, #4
    3986:	d011      	beq.n	39ac <nrfx_gpiote_trigger_enable+0x7c>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    3988:	2b05      	cmp	r3, #5
    398a:	d011      	beq.n	39b0 <nrfx_gpiote_trigger_enable+0x80>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    398c:	a801      	add	r0, sp, #4
    398e:	9401      	str	r4, [sp, #4]
    3990:	f7ff fdd4 	bl	353c <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3994:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    3996:	6901      	ldr	r1, [r0, #16]
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3998:	40d9      	lsrs	r1, r3
    399a:	f001 0101 	and.w	r1, r1, #1
        sense = nrf_gpio_pin_read(pin) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    399e:	3102      	adds	r1, #2
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    39a0:	4620      	mov	r0, r4
}
    39a2:	b003      	add	sp, #12
    39a4:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    39a8:	f002 be0b 	b.w	65c2 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    39ac:	2103      	movs	r1, #3
    39ae:	e7f7      	b.n	39a0 <nrfx_gpiote_trigger_enable+0x70>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    39b0:	2102      	movs	r1, #2
    39b2:	e7f5      	b.n	39a0 <nrfx_gpiote_trigger_enable+0x70>
    39b4:	20000120 	.word	0x20000120
    39b8:	5000d000 	.word	0x5000d000

000039bc <nrfx_gpiote_trigger_disable>:
{
    39bc:	b508      	push	{r3, lr}
    39be:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    39c0:	f7ff fdcc 	bl	355c <pin_in_use_by_te>
    39c4:	b1c0      	cbz	r0, 39f8 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    39c6:	4b0f      	ldr	r3, [pc, #60]	; (3a04 <nrfx_gpiote_trigger_disable+0x48>)
    39c8:	f102 0108 	add.w	r1, r2, #8
    39cc:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    39d0:	0799      	lsls	r1, r3, #30
    39d2:	d411      	bmi.n	39f8 <nrfx_gpiote_trigger_disable+0x3c>
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    39d4:	2201      	movs	r2, #1
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    39d6:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    39d8:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    39da:	490b      	ldr	r1, [pc, #44]	; (3a08 <nrfx_gpiote_trigger_disable+0x4c>)
    39dc:	009b      	lsls	r3, r3, #2
    39de:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    39e2:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    39e6:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    39ea:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    39ee:	f022 0203 	bic.w	r2, r2, #3
    39f2:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    39f6:	bd08      	pop	{r3, pc}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    39f8:	2100      	movs	r1, #0
}
    39fa:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    39fe:	4610      	mov	r0, r2
    3a00:	f002 bddf 	b.w	65c2 <nrf_gpio_cfg_sense_set>
    3a04:	20000120 	.word	0x20000120
    3a08:	5000d000 	.word	0x5000d000

00003a0c <nrfx_gpiote_pin_uninit>:
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    3a0c:	4b10      	ldr	r3, [pc, #64]	; (3a50 <nrfx_gpiote_pin_uninit+0x44>)
    3a0e:	f100 0208 	add.w	r2, r0, #8
    3a12:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
{
    3a16:	b513      	push	{r0, r1, r4, lr}
    if (!pin_in_use(pin))
    3a18:	07db      	lsls	r3, r3, #31
{
    3a1a:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    3a1c:	d516      	bpl.n	3a4c <nrfx_gpiote_pin_uninit+0x40>
    nrfx_gpiote_trigger_disable(pin);
    3a1e:	f7ff ffcd 	bl	39bc <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    3a22:	4620      	mov	r0, r4
    3a24:	f7ff fdec 	bl	3600 <pin_handler_trigger_uninit>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3a28:	a801      	add	r0, sp, #4
    3a2a:	9401      	str	r4, [sp, #4]
    3a2c:	f7ff fd86 	bl	353c <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    3a30:	9b01      	ldr	r3, [sp, #4]
    3a32:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    3a36:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    3a3a:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    3a3e:	f043 0302 	orr.w	r3, r3, #2
    reg->PIN_CNF[pin_number] = cnf;
    3a42:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
    nrf_gpio_cfg(
    3a46:	4803      	ldr	r0, [pc, #12]	; (3a54 <nrfx_gpiote_pin_uninit+0x48>)
}
    3a48:	b002      	add	sp, #8
    3a4a:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3a4c:	4802      	ldr	r0, [pc, #8]	; (3a58 <nrfx_gpiote_pin_uninit+0x4c>)
    3a4e:	e7fb      	b.n	3a48 <nrfx_gpiote_pin_uninit+0x3c>
    3a50:	20000120 	.word	0x20000120
    3a54:	0bad0000 	.word	0x0bad0000
    3a58:	0bad0004 	.word	0x0bad0004

00003a5c <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    3a5c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    uint32_t status = 0;
    3a60:	2600      	movs	r6, #0
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    3a62:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3a64:	4634      	mov	r4, r6
{
    3a66:	4b60      	ldr	r3, [pc, #384]	; (3be8 <nrfx_gpiote_irq_handler+0x18c>)
    return p_reg->INTENSET & mask;
    3a68:	4860      	ldr	r0, [pc, #384]	; (3bec <nrfx_gpiote_irq_handler+0x190>)

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3a6a:	4961      	ldr	r1, [pc, #388]	; (3bf0 <nrfx_gpiote_irq_handler+0x194>)
{
    3a6c:	b087      	sub	sp, #28
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3a6e:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    3a70:	b135      	cbz	r5, 3a80 <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    3a72:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    3a76:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3a78:	bf1e      	ittt	ne
    3a7a:	601c      	strne	r4, [r3, #0]
    3a7c:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    3a7e:	4316      	orrne	r6, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3a80:	3304      	adds	r3, #4
    3a82:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    3a84:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3a88:	d1f1      	bne.n	3a6e <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3a8a:	f8df 9160 	ldr.w	r9, [pc, #352]	; 3bec <nrfx_gpiote_irq_handler+0x190>
    3a8e:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    3a92:	2b00      	cmp	r3, #0
    3a94:	f000 808a 	beq.w	3bac <nrfx_gpiote_irq_handler+0x150>
        *p_masks = gpio_regs[i]->LATCH;
    3a98:	4f56      	ldr	r7, [pc, #344]	; (3bf4 <nrfx_gpiote_irq_handler+0x198>)
    3a9a:	6a3b      	ldr	r3, [r7, #32]
    3a9c:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    3a9e:	623b      	str	r3, [r7, #32]
        *p_masks = gpio_regs[i]->LATCH;
    3aa0:	4b55      	ldr	r3, [pc, #340]	; (3bf8 <nrfx_gpiote_irq_handler+0x19c>)
    3aa2:	6a1a      	ldr	r2, [r3, #32]
    3aa4:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    3aa6:	621a      	str	r2, [r3, #32]
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    3aa8:	f04f 0800 	mov.w	r8, #0
            while (latch[i])
    3aac:	f10d 0a10 	add.w	sl, sp, #16
    3ab0:	ea4f 1348 	mov.w	r3, r8, lsl #5
    3ab4:	9300      	str	r3, [sp, #0]
    3ab6:	e049      	b.n	3b4c <nrfx_gpiote_irq_handler+0xf0>
                uint32_t pin = NRF_CTZ(latch[i]);
    3ab8:	fa94 f4a4 	rbit	r4, r4
    3abc:	fab4 f484 	clz	r4, r4
                pin += 32 * i;
    3ac0:	9b00      	ldr	r3, [sp, #0]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3ac2:	4a4e      	ldr	r2, [pc, #312]	; (3bfc <nrfx_gpiote_irq_handler+0x1a0>)
                pin += 32 * i;
    3ac4:	441c      	add	r4, r3
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3ac6:	f104 0308 	add.w	r3, r4, #8
    3aca:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 * @param[in,out] p_mask Pointer to mask with bit fields.
 */
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    3ace:	08e0      	lsrs	r0, r4, #3
    3ad0:	0899      	lsrs	r1, r3, #2
    3ad2:	f3c3 0582 	ubfx	r5, r3, #2, #3
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    3ad6:	2301      	movs	r3, #1
    bit = BITMASK_RELBIT_GET(bit);
    3ad8:	f004 0207 	and.w	r2, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    3adc:	fa03 fc02 	lsl.w	ip, r3, r2
    3ae0:	f81a 2000 	ldrb.w	r2, [sl, r0]
    3ae4:	9403      	str	r4, [sp, #12]
    3ae6:	ea22 020c 	bic.w	r2, r2, ip
    3aea:	f80a 2000 	strb.w	r2, [sl, r0]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3aee:	a803      	add	r0, sp, #12
    3af0:	f7ff fd24 	bl	353c <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3af4:	9a03      	ldr	r2, [sp, #12]
    if (is_level(trigger))
    3af6:	074b      	lsls	r3, r1, #29
    3af8:	f102 0280 	add.w	r2, r2, #128	; 0x80
    3afc:	f850 2022 	ldr.w	r2, [r0, r2, lsl #2]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3b00:	46ab      	mov	fp, r5
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    3b02:	f3c2 4201 	ubfx	r2, r2, #16, #2
    if (is_level(trigger))
    3b06:	d52b      	bpl.n	3b60 <nrfx_gpiote_irq_handler+0x104>
        call_handler(pin, trigger);
    3b08:	4620      	mov	r0, r4
    3b0a:	4659      	mov	r1, fp
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3b0c:	b2d5      	uxtb	r5, r2
    3b0e:	f7ff fd2f 	bl	3570 <call_handler>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3b12:	a803      	add	r0, sp, #12
    3b14:	9403      	str	r4, [sp, #12]
    3b16:	f7ff fd11 	bl	353c <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3b1a:	9b03      	ldr	r3, [sp, #12]
    3b1c:	3380      	adds	r3, #128	; 0x80
    3b1e:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
        if (nrf_gpio_pin_sense_get(pin) == sense)
    3b22:	f3c3 4301 	ubfx	r3, r3, #16, #2
    3b26:	429d      	cmp	r5, r3
    3b28:	d107      	bne.n	3b3a <nrfx_gpiote_irq_handler+0xde>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3b2a:	2100      	movs	r1, #0
    3b2c:	4620      	mov	r0, r4
    3b2e:	f002 fd48 	bl	65c2 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    3b32:	4629      	mov	r1, r5
    3b34:	4620      	mov	r0, r4
    3b36:	f002 fd44 	bl	65c2 <nrf_gpio_cfg_sense_set>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3b3a:	a803      	add	r0, sp, #12
    3b3c:	9403      	str	r4, [sp, #12]
    3b3e:	f7ff fcfd 	bl	353c <nrf_gpio_pin_port_decode>
    reg->LATCH = (1 << pin_number);
    3b42:	2201      	movs	r2, #1
    3b44:	9b03      	ldr	r3, [sp, #12]
    3b46:	fa02 f303 	lsl.w	r3, r2, r3
    3b4a:	6203      	str	r3, [r0, #32]
            while (latch[i])
    3b4c:	f85a 4028 	ldr.w	r4, [sl, r8, lsl #2]
    3b50:	2c00      	cmp	r4, #0
    3b52:	d1b1      	bne.n	3ab8 <nrfx_gpiote_irq_handler+0x5c>
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    3b54:	f1b8 0f00 	cmp.w	r8, #0
    3b58:	d11a      	bne.n	3b90 <nrfx_gpiote_irq_handler+0x134>
    3b5a:	f04f 0801 	mov.w	r8, #1
    3b5e:	e7a7      	b.n	3ab0 <nrfx_gpiote_irq_handler+0x54>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    3b60:	2a02      	cmp	r2, #2
        nrf_gpio_cfg_sense_set(pin, next_sense);
    3b62:	bf0c      	ite	eq
    3b64:	2103      	moveq	r1, #3
    3b66:	2102      	movne	r1, #2
    3b68:	4620      	mov	r0, r4
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    3b6a:	9201      	str	r2, [sp, #4]
        nrf_gpio_cfg_sense_set(pin, next_sense);
    3b6c:	f002 fd29 	bl	65c2 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    3b70:	2d03      	cmp	r5, #3
    3b72:	d004      	beq.n	3b7e <nrfx_gpiote_irq_handler+0x122>
    3b74:	9a01      	ldr	r2, [sp, #4]
    3b76:	2a02      	cmp	r2, #2
    3b78:	d106      	bne.n	3b88 <nrfx_gpiote_irq_handler+0x12c>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    3b7a:	2d01      	cmp	r5, #1
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    3b7c:	d1dd      	bne.n	3b3a <nrfx_gpiote_irq_handler+0xde>
            call_handler(pin, trigger);
    3b7e:	4659      	mov	r1, fp
    3b80:	4620      	mov	r0, r4
    3b82:	f7ff fcf5 	bl	3570 <call_handler>
    3b86:	e7d8      	b.n	3b3a <nrfx_gpiote_irq_handler+0xde>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    3b88:	2a03      	cmp	r2, #3
    3b8a:	d1d6      	bne.n	3b3a <nrfx_gpiote_irq_handler+0xde>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    3b8c:	2d02      	cmp	r5, #2
    3b8e:	e7f5      	b.n	3b7c <nrfx_gpiote_irq_handler+0x120>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3b90:	f8c9 417c 	str.w	r4, [r9, #380]	; 0x17c
    3b94:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    3b98:	6a3a      	ldr	r2, [r7, #32]
    3b9a:	4917      	ldr	r1, [pc, #92]	; (3bf8 <nrfx_gpiote_irq_handler+0x19c>)
    3b9c:	9204      	str	r2, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    3b9e:	623a      	str	r2, [r7, #32]
        *p_masks = gpio_regs[i]->LATCH;
    3ba0:	6a0b      	ldr	r3, [r1, #32]
    3ba2:	9305      	str	r3, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    3ba4:	620b      	str	r3, [r1, #32]
        if (latch[port_idx])
    3ba6:	4313      	orrs	r3, r2
    3ba8:	f47f af7e 	bne.w	3aa8 <nrfx_gpiote_irq_handler+0x4c>
        mask &= ~NRFX_BIT(ch);
    3bac:	2401      	movs	r4, #1
    while (mask)
    3bae:	b916      	cbnz	r6, 3bb6 <nrfx_gpiote_irq_handler+0x15a>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    3bb0:	b007      	add	sp, #28
    3bb2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t ch = NRF_CTZ(mask);
    3bb6:	fa96 f3a6 	rbit	r3, r6
    3bba:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    3bbe:	fa04 f203 	lsl.w	r2, r4, r3
    3bc2:	009b      	lsls	r3, r3, #2
    3bc4:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    3bc8:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    3bcc:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    3bd0:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    3bd4:	f3c0 2005 	ubfx	r0, r0, #8, #6
    3bd8:	f3c1 4101 	ubfx	r1, r1, #16, #2
        mask &= ~NRFX_BIT(ch);
    3bdc:	ea26 0602 	bic.w	r6, r6, r2
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    3be0:	f7ff fcc6 	bl	3570 <call_handler>
    3be4:	e7e3      	b.n	3bae <nrfx_gpiote_irq_handler+0x152>
    3be6:	bf00      	nop
    3be8:	5000d100 	.word	0x5000d100
    3bec:	5000d000 	.word	0x5000d000
    3bf0:	5000d120 	.word	0x5000d120
    3bf4:	50842500 	.word	0x50842500
    3bf8:	50842800 	.word	0x50842800
    3bfc:	20000120 	.word	0x20000120

00003c00 <nrfx_timer_init>:
static timer_control_block_t m_cb[NRFX_TIMER_ENABLED_COUNT];

nrfx_err_t nrfx_timer_init(nrfx_timer_t const *        p_instance,
                           nrfx_timer_config_t const * p_config,
                           nrfx_timer_event_handler_t  timer_event_handler)
{
    3c00:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3c02:	460c      	mov	r4, r1
    NRFX_ASSERT(p_config);
    NRFX_ASSERT(timer_event_handler);

    nrfx_err_t err_code;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    3c04:	210c      	movs	r1, #12
    timer_control_block_t * p_cb = &m_cb[p_instance->instance_id];
    3c06:	7907      	ldrb	r7, [r0, #4]
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    3c08:	4e21      	ldr	r6, [pc, #132]	; (3c90 <nrfx_timer_init+0x90>)
    3c0a:	4379      	muls	r1, r7
{
    3c0c:	4605      	mov	r5, r0
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    3c0e:	1870      	adds	r0, r6, r1
    3c10:	7a03      	ldrb	r3, [r0, #8]
    3c12:	2b00      	cmp	r3, #0
    3c14:	d13a      	bne.n	3c8c <nrfx_timer_init+0x8c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3c16:	469c      	mov	ip, r3
        return err_code;
    }

    NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width));

    p_cb->handler = timer_event_handler;
    3c18:	5072      	str	r2, [r6, r1]
    p_cb->context = p_config->p_context;
    3c1a:	6862      	ldr	r2, [r4, #4]
    3c1c:	6042      	str	r2, [r0, #4]

    uint8_t i;
    for (i = 0; i < p_instance->cc_channel_count; ++i)
    3c1e:	7969      	ldrb	r1, [r5, #5]
    {
        nrf_timer_event_clear(p_instance->p_reg,
    3c20:	6828      	ldr	r0, [r5, #0]
    for (i = 0; i < p_instance->cc_channel_count; ++i)
    3c22:	b2da      	uxtb	r2, r3
    3c24:	4291      	cmp	r1, r2
    3c26:	d829      	bhi.n	3c7c <nrfx_timer_init+0x7c>
                              nrf_timer_compare_event_get(i));
    }

    NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
        p_config->interrupt_priority);
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    3c28:	f340 3007 	sbfx	r0, r0, #12, #8
    3c2c:	f7fd fbd2 	bl	13d4 <arch_irq_enable>

    nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
    3c30:	682b      	ldr	r3, [r5, #0]

NRF_STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
                                          nrf_timer_mode_t mode)
{
    p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) |
                    ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk);
    3c32:	7862      	ldrb	r2, [r4, #1]
    p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) |
    3c34:	f8d3 1504 	ldr.w	r1, [r3, #1284]	; 0x504
                    ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk);
    3c38:	f002 0203 	and.w	r2, r2, #3
    p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) |
    3c3c:	f021 0103 	bic.w	r1, r1, #3
    3c40:	430a      	orrs	r2, r1
    3c42:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}

NRF_STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type *      p_reg,
                                               nrf_timer_bit_width_t bit_width)
{
    p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
    3c46:	f8d3 1508 	ldr.w	r1, [r3, #1288]	; 0x508
                       ((bit_width << TIMER_BITMODE_BITMODE_Pos) &
    3c4a:	78a2      	ldrb	r2, [r4, #2]
    p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
    3c4c:	f021 0103 	bic.w	r1, r1, #3
                       ((bit_width << TIMER_BITMODE_BITMODE_Pos) &
    3c50:	f002 0203 	and.w	r2, r2, #3
    p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
    3c54:	430a      	orrs	r2, r1
    3c56:	f8c3 2508 	str.w	r2, [r3, #1288]	; 0x508
}

NRF_STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type *      p_reg,
                                               nrf_timer_frequency_t frequency)
{
    p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
    3c5a:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
                         ((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
    3c5e:	7822      	ldrb	r2, [r4, #0]
    p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
    3c60:	f021 010f 	bic.w	r1, r1, #15
                         ((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
    3c64:	f002 020f 	and.w	r2, r2, #15
    p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
    3c68:	430a      	orrs	r2, r1
    3c6a:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
    nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);

    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    3c6e:	230c      	movs	r3, #12
    3c70:	fb03 6607 	mla	r6, r3, r7, r6
    3c74:	2301      	movs	r3, #1

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.",
                  __func__,
                  NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    3c76:	4807      	ldr	r0, [pc, #28]	; (3c94 <nrfx_timer_init+0x94>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    3c78:	7233      	strb	r3, [r6, #8]
}
    3c7a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3c7c:	009a      	lsls	r2, r3, #2
    3c7e:	f502 72a0 	add.w	r2, r2, #320	; 0x140
    3c82:	f840 c002 	str.w	ip, [r0, r2]
    3c86:	5882      	ldr	r2, [r0, r2]
    for (i = 0; i < p_instance->cc_channel_count; ++i)
    3c88:	3301      	adds	r3, #1
    3c8a:	e7ca      	b.n	3c22 <nrfx_timer_init+0x22>
        return err_code;
    3c8c:	4802      	ldr	r0, [pc, #8]	; (3c98 <nrfx_timer_init+0x98>)
    3c8e:	e7f4      	b.n	3c7a <nrfx_timer_init+0x7a>
    3c90:	20000b94 	.word	0x20000b94
    3c94:	0bad0000 	.word	0x0bad0000
    3c98:	0bad0005 	.word	0x0bad0005

00003c9c <nrfx_timer_enable>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3c9c:	2201      	movs	r2, #1

void nrfx_timer_enable(nrfx_timer_t const * p_instance)
{
    NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED);
    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
    m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_POWERED_ON;
    3c9e:	210c      	movs	r1, #12
    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
    3ca0:	6803      	ldr	r3, [r0, #0]
    3ca2:	601a      	str	r2, [r3, #0]
    m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_POWERED_ON;
    3ca4:	7902      	ldrb	r2, [r0, #4]
    3ca6:	4b03      	ldr	r3, [pc, #12]	; (3cb4 <nrfx_timer_enable+0x18>)
    3ca8:	fb01 3302 	mla	r3, r1, r2, r3
    3cac:	2202      	movs	r2, #2
    3cae:	721a      	strb	r2, [r3, #8]
    NRFX_LOG_INFO("Enabled instance: %d.", p_instance->instance_id);
}
    3cb0:	4770      	bx	lr
    3cb2:	bf00      	nop
    3cb4:	20000b94 	.word	0x20000b94

00003cb8 <nrfx_timer_disable>:
    3cb8:	2201      	movs	r2, #1

void nrfx_timer_disable(nrfx_timer_t const * p_instance)
{
    NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN);
    3cba:	6803      	ldr	r3, [r0, #0]
    3cbc:	611a      	str	r2, [r3, #16]
    m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED;
    3cbe:	7901      	ldrb	r1, [r0, #4]
    3cc0:	200c      	movs	r0, #12
    3cc2:	4b02      	ldr	r3, [pc, #8]	; (3ccc <nrfx_timer_disable+0x14>)
    3cc4:	fb00 3301 	mla	r3, r0, r1, r3
    3cc8:	721a      	strb	r2, [r3, #8]
    NRFX_LOG_INFO("Disabled instance: %d.", p_instance->instance_id);
}
    3cca:	4770      	bx	lr
    3ccc:	20000b94 	.word	0x20000b94

00003cd0 <nrfx_timer_uninit>:
{
    3cd0:	b538      	push	{r3, r4, r5, lr}
    3cd2:	4604      	mov	r4, r0
    return ((((uint32_t)p_object) & 0x3u) == 0u);
}

NRF_STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg)
{
    return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg);
    3cd4:	6800      	ldr	r0, [r0, #0]
    p_reg->SHORTS &= ~(mask);
    3cd6:	2500      	movs	r5, #0
    NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    3cd8:	f340 3007 	sbfx	r0, r0, #12, #8
    3cdc:	f7fd fb8a 	bl	13f4 <arch_irq_disable>
    nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL);
    3ce0:	6823      	ldr	r3, [r4, #0]
    nrfx_timer_disable(p_instance);
    3ce2:	4620      	mov	r0, r4
    3ce4:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    p_reg->INTENCLR = mask;
    3ce8:	f04f 32ff 	mov.w	r2, #4294967295
    p_reg->SHORTS &= ~(mask);
    3cec:	f8c3 5200 	str.w	r5, [r3, #512]	; 0x200
    p_reg->INTENCLR = mask;
    3cf0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    3cf4:	f7ff ffe0 	bl	3cb8 <nrfx_timer_disable>
    m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_UNINITIALIZED;
    3cf8:	210c      	movs	r1, #12
    3cfa:	7922      	ldrb	r2, [r4, #4]
    3cfc:	4b02      	ldr	r3, [pc, #8]	; (3d08 <nrfx_timer_uninit+0x38>)
    3cfe:	fb01 3302 	mla	r3, r1, r2, r3
    3d02:	721d      	strb	r5, [r3, #8]
}
    3d04:	bd38      	pop	{r3, r4, r5, pc}
    3d06:	bf00      	nop
    3d08:	20000b94 	.word	0x20000b94

00003d0c <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3d0c:	4b0e      	ldr	r3, [pc, #56]	; (3d48 <z_sys_init_run_level+0x3c>)
{
    3d0e:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3d10:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    3d14:	3001      	adds	r0, #1
    3d16:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    3d1a:	42a6      	cmp	r6, r4
    3d1c:	d800      	bhi.n	3d20 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    3d1e:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    3d20:	e9d4 3500 	ldrd	r3, r5, [r4]
    3d24:	4628      	mov	r0, r5
    3d26:	4798      	blx	r3
		if (dev != NULL) {
    3d28:	b165      	cbz	r5, 3d44 <z_sys_init_run_level+0x38>
				dev->state->init_res = rc;
    3d2a:	68eb      	ldr	r3, [r5, #12]
			if (rc != 0) {
    3d2c:	b130      	cbz	r0, 3d3c <z_sys_init_run_level+0x30>
				if (rc < 0) {
    3d2e:	2800      	cmp	r0, #0
    3d30:	bfb8      	it	lt
    3d32:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    3d34:	28ff      	cmp	r0, #255	; 0xff
    3d36:	bfa8      	it	ge
    3d38:	20ff      	movge	r0, #255	; 0xff
    3d3a:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    3d3c:	785a      	ldrb	r2, [r3, #1]
    3d3e:	f042 0201 	orr.w	r2, r2, #1
    3d42:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3d44:	3408      	adds	r4, #8
    3d46:	e7e8      	b.n	3d1a <z_sys_init_run_level+0xe>
    3d48:	00006eb0 	.word	0x00006eb0

00003d4c <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    3d4c:	b570      	push	{r4, r5, r6, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    3d4e:	4605      	mov	r5, r0
    3d50:	b910      	cbnz	r0, 3d58 <z_impl_device_get_binding+0xc>
		return NULL;
    3d52:	2400      	movs	r4, #0
			return dev;
		}
	}

	return NULL;
}
    3d54:	4620      	mov	r0, r4
    3d56:	bd70      	pop	{r4, r5, r6, pc}
	if ((name == NULL) || (name[0] == '\0')) {
    3d58:	7803      	ldrb	r3, [r0, #0]
    3d5a:	2b00      	cmp	r3, #0
    3d5c:	d0f9      	beq.n	3d52 <z_impl_device_get_binding+0x6>
	for (dev = __device_start; dev != __device_end; dev++) {
    3d5e:	4c0e      	ldr	r4, [pc, #56]	; (3d98 <z_impl_device_get_binding+0x4c>)
    3d60:	4e0e      	ldr	r6, [pc, #56]	; (3d9c <z_impl_device_get_binding+0x50>)
    3d62:	42b4      	cmp	r4, r6
    3d64:	d108      	bne.n	3d78 <z_impl_device_get_binding+0x2c>
	for (dev = __device_start; dev != __device_end; dev++) {
    3d66:	4c0c      	ldr	r4, [pc, #48]	; (3d98 <z_impl_device_get_binding+0x4c>)
    3d68:	42b4      	cmp	r4, r6
    3d6a:	d0f2      	beq.n	3d52 <z_impl_device_get_binding+0x6>
		if (z_device_is_ready(dev) && (strcmp(name, dev->name) == 0)) {
    3d6c:	4620      	mov	r0, r4
    3d6e:	f002 fc4b 	bl	6608 <z_device_is_ready>
    3d72:	b950      	cbnz	r0, 3d8a <z_impl_device_get_binding+0x3e>
	for (dev = __device_start; dev != __device_end; dev++) {
    3d74:	3418      	adds	r4, #24
    3d76:	e7f7      	b.n	3d68 <z_impl_device_get_binding+0x1c>
		if (z_device_is_ready(dev) && (dev->name == name)) {
    3d78:	4620      	mov	r0, r4
    3d7a:	f002 fc45 	bl	6608 <z_device_is_ready>
    3d7e:	b110      	cbz	r0, 3d86 <z_impl_device_get_binding+0x3a>
    3d80:	6823      	ldr	r3, [r4, #0]
    3d82:	42ab      	cmp	r3, r5
    3d84:	d0e6      	beq.n	3d54 <z_impl_device_get_binding+0x8>
	for (dev = __device_start; dev != __device_end; dev++) {
    3d86:	3418      	adds	r4, #24
    3d88:	e7eb      	b.n	3d62 <z_impl_device_get_binding+0x16>
		if (z_device_is_ready(dev) && (strcmp(name, dev->name) == 0)) {
    3d8a:	4628      	mov	r0, r5
    3d8c:	6821      	ldr	r1, [r4, #0]
    3d8e:	f001 fb62 	bl	5456 <strcmp>
    3d92:	2800      	cmp	r0, #0
    3d94:	d1ee      	bne.n	3d74 <z_impl_device_get_binding+0x28>
    3d96:	e7dd      	b.n	3d54 <z_impl_device_get_binding+0x8>
    3d98:	000069ec 	.word	0x000069ec
    3d9c:	00006a64 	.word	0x00006a64

00003da0 <bg_thread_main>:
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    3da0:	2201      	movs	r2, #1
{
    3da2:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    3da4:	4b09      	ldr	r3, [pc, #36]	; (3dcc <bg_thread_main+0x2c>)

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3da6:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    3da8:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3daa:	f7ff ffaf 	bl	3d0c <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    3dae:	f002 fdec 	bl	698a <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    3db2:	2003      	movs	r0, #3
    3db4:	f7ff ffaa 	bl	3d0c <z_sys_init_run_level>

	z_init_static_threads();
    3db8:	f000 f936 	bl	4028 <z_init_static_threads>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    3dbc:	f7fc fb72 	bl	4a4 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    3dc0:	4a03      	ldr	r2, [pc, #12]	; (3dd0 <bg_thread_main+0x30>)
    3dc2:	7b13      	ldrb	r3, [r2, #12]
    3dc4:	f023 0301 	bic.w	r3, r3, #1
    3dc8:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    3dca:	bd08      	pop	{r3, pc}
    3dcc:	20000db1 	.word	0x20000db1
    3dd0:	200004c0 	.word	0x200004c0

00003dd4 <z_bss_zero>:
{
    3dd4:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    3dd6:	4803      	ldr	r0, [pc, #12]	; (3de4 <z_bss_zero+0x10>)
    3dd8:	4a03      	ldr	r2, [pc, #12]	; (3de8 <z_bss_zero+0x14>)
    3dda:	2100      	movs	r1, #0
    3ddc:	1a12      	subs	r2, r2, r0
    3dde:	f002 fc38 	bl	6652 <z_early_memset>
}
    3de2:	bd08      	pop	{r3, pc}
    3de4:	20000268 	.word	0x20000268
    3de8:	20000db4 	.word	0x20000db4

00003dec <z_init_cpu>:

#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
    3dec:	2300      	movs	r3, #0
    3dee:	2201      	movs	r2, #1
	thread->base.is_idle = 1U;
#endif
}

void z_init_cpu(int id)
{
    3df0:	b570      	push	{r4, r5, r6, lr}
    3df2:	b086      	sub	sp, #24
	z_setup_new_thread(thread, stack,
    3df4:	e9cd 2304 	strd	r2, r3, [sp, #16]
    3df8:	220f      	movs	r2, #15
    3dfa:	9301      	str	r3, [sp, #4]
    3dfc:	e9cd 3202 	strd	r3, r2, [sp, #8]
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    3e00:	2318      	movs	r3, #24
	z_setup_new_thread(thread, stack,
    3e02:	f44f 72a0 	mov.w	r2, #320	; 0x140
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    3e06:	4d0e      	ldr	r5, [pc, #56]	; (3e40 <z_init_cpu+0x54>)
	struct k_thread *thread = &z_idle_threads[i];
    3e08:	4e0e      	ldr	r6, [pc, #56]	; (3e44 <z_init_cpu+0x58>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    3e0a:	fb03 5500 	mla	r5, r3, r0, r5
	z_setup_new_thread(thread, stack,
    3e0e:	490e      	ldr	r1, [pc, #56]	; (3e48 <z_init_cpu+0x5c>)
	struct k_thread *thread = &z_idle_threads[i];
    3e10:	eb06 16c0 	add.w	r6, r6, r0, lsl #7
{
    3e14:	4604      	mov	r4, r0
	z_setup_new_thread(thread, stack,
    3e16:	fb02 1100 	mla	r1, r2, r0, r1
    3e1a:	4b0c      	ldr	r3, [pc, #48]	; (3e4c <z_init_cpu+0x60>)
    3e1c:	4630      	mov	r0, r6
    3e1e:	9500      	str	r5, [sp, #0]
    3e20:	f000 f8d2 	bl	3fc8 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    3e24:	7b73      	ldrb	r3, [r6, #13]
	init_idle_thread(id);
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
	_kernel.cpus[id].id = id;
	_kernel.cpus[id].irq_stack =
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    3e26:	480a      	ldr	r0, [pc, #40]	; (3e50 <z_init_cpu+0x64>)
	_kernel.cpus[id].id = id;
    3e28:	752c      	strb	r4, [r5, #20]
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    3e2a:	3401      	adds	r4, #1
    3e2c:	f023 0304 	bic.w	r3, r3, #4
    3e30:	eb00 24c4 	add.w	r4, r0, r4, lsl #11
    3e34:	7373      	strb	r3, [r6, #13]
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
    3e36:	60ee      	str	r6, [r5, #12]
	_kernel.cpus[id].irq_stack =
    3e38:	606c      	str	r4, [r5, #4]
		 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id]));
#ifdef CONFIG_SCHED_THREAD_USAGE_ALL
	_kernel.cpus[id].usage.track_usage =
		CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE;
#endif
}
    3e3a:	b006      	add	sp, #24
    3e3c:	bd70      	pop	{r4, r5, r6, pc}
    3e3e:	bf00      	nop
    3e40:	20000ba0 	.word	0x20000ba0
    3e44:	20000440 	.word	0x20000440
    3e48:	200011b8 	.word	0x200011b8
    3e4c:	000040e1 	.word	0x000040e1
    3e50:	200012f8 	.word	0x200012f8

00003e54 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    3e54:	b580      	push	{r7, lr}
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    3e56:	4b2d      	ldr	r3, [pc, #180]	; (3f0c <z_cstart+0xb8>)
    3e58:	b0a6      	sub	sp, #152	; 0x98
	uint32_t msp =
    3e5a:	f503 6200 	add.w	r2, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    3e5e:	f382 8808 	msr	MSP, r2
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure MSPLIM is RAZ/WI
  (void)MainStackPtrLimit;
#else
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    3e62:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3e66:	2400      	movs	r4, #0
    3e68:	23e0      	movs	r3, #224	; 0xe0
    3e6a:	4d29      	ldr	r5, [pc, #164]	; (3f10 <z_cstart+0xbc>)
	k_thread_system_pool_assign(dummy_thread);
#else
	dummy_thread->resource_pool = NULL;
#endif

	_current_cpu->current = dummy_thread;
    3e6c:	4e29      	ldr	r6, [pc, #164]	; (3f14 <z_cstart+0xc0>)
    3e6e:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    3e72:	77ec      	strb	r4, [r5, #31]
    3e74:	762c      	strb	r4, [r5, #24]
    3e76:	766c      	strb	r4, [r5, #25]
    3e78:	76ac      	strb	r4, [r5, #26]
    3e7a:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    3e7e:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3e80:	4f25      	ldr	r7, [pc, #148]	; (3f18 <z_cstart+0xc4>)
    3e82:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    3e86:	626b      	str	r3, [r5, #36]	; 0x24
    3e88:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    3e8c:	f7fd fc96 	bl	17bc <z_arm_fault_init>
	z_arm_cpu_idle_init();
    3e90:	f7fd fa82 	bl	1398 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    3e94:	f04f 33ff 	mov.w	r3, #4294967295
    3e98:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    3e9a:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    3e9c:	f7fd fe9e 	bl	1bdc <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    3ea0:	f7fd fd3c 	bl	191c <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    3ea4:	f240 1301 	movw	r3, #257	; 0x101
    3ea8:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    3eac:	ab06      	add	r3, sp, #24
    3eae:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    3eb0:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	dummy_thread->resource_pool = NULL;
    3eb4:	9422      	str	r4, [sp, #136]	; 0x88
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    3eb6:	f002 fba6 	bl	6606 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    3eba:	4620      	mov	r0, r4
    3ebc:	f7ff ff26 	bl	3d0c <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    3ec0:	2001      	movs	r0, #1
	_kernel.ready_q.cache = &z_main_thread;
    3ec2:	4d16      	ldr	r5, [pc, #88]	; (3f1c <z_cstart+0xc8>)
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    3ec4:	f7ff ff22 	bl	3d0c <z_sys_init_run_level>
	z_sched_init();
    3ec8:	f000 fc6c 	bl	47a4 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3ecc:	4b14      	ldr	r3, [pc, #80]	; (3f20 <z_cstart+0xcc>)
	_kernel.ready_q.cache = &z_main_thread;
    3ece:	61f5      	str	r5, [r6, #28]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3ed0:	9305      	str	r3, [sp, #20]
    3ed2:	2301      	movs	r3, #1
    3ed4:	4913      	ldr	r1, [pc, #76]	; (3f24 <z_cstart+0xd0>)
    3ed6:	f44f 6280 	mov.w	r2, #1024	; 0x400
    3eda:	e9cd 4303 	strd	r4, r3, [sp, #12]
    3ede:	4628      	mov	r0, r5
    3ee0:	463b      	mov	r3, r7
    3ee2:	e9cd 4401 	strd	r4, r4, [sp, #4]
    3ee6:	9400      	str	r4, [sp, #0]
    3ee8:	f000 f86e 	bl	3fc8 <z_setup_new_thread>
    3eec:	4606      	mov	r6, r0
    3eee:	7b6a      	ldrb	r2, [r5, #13]
	z_ready_thread(&z_main_thread);
    3ef0:	4628      	mov	r0, r5
    3ef2:	f022 0204 	bic.w	r2, r2, #4
    3ef6:	736a      	strb	r2, [r5, #13]
    3ef8:	f002 fc4d 	bl	6796 <z_ready_thread>
	z_init_cpu(0);
    3efc:	4620      	mov	r0, r4
    3efe:	f7ff ff75 	bl	3dec <z_init_cpu>
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3f02:	463a      	mov	r2, r7
    3f04:	4631      	mov	r1, r6
    3f06:	4628      	mov	r0, r5
    3f08:	f7fd fb3e 	bl	1588 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    3f0c:	200012f8 	.word	0x200012f8
    3f10:	e000ed00 	.word	0xe000ed00
    3f14:	20000ba0 	.word	0x20000ba0
    3f18:	00003da1 	.word	0x00003da1
    3f1c:	200004c0 	.word	0x200004c0
    3f20:	0000703b 	.word	0x0000703b
    3f24:	20000db8 	.word	0x20000db8

00003f28 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return 0 on success, fails otherwise.
 */
static int init_mem_slab_module(const struct device *dev)
{
    3f28:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    3f2a:	4b0e      	ldr	r3, [pc, #56]	; (3f64 <init_mem_slab_module+0x3c>)
    3f2c:	4c0e      	ldr	r4, [pc, #56]	; (3f68 <init_mem_slab_module+0x40>)
    3f2e:	42a3      	cmp	r3, r4
    3f30:	d301      	bcc.n	3f36 <init_mem_slab_module+0xe>
			goto out;
		}
		z_object_init(slab);
	}

out:
    3f32:	2000      	movs	r0, #0
	return rc;
}
    3f34:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    3f36:	e9d3 0103 	ldrd	r0, r1, [r3, #12]
    3f3a:	ea41 0200 	orr.w	r2, r1, r0
    3f3e:	f012 0203 	ands.w	r2, r2, #3
    3f42:	d10b      	bne.n	3f5c <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
    3f44:	689d      	ldr	r5, [r3, #8]
	slab->free_list = NULL;
    3f46:	615a      	str	r2, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    3f48:	42aa      	cmp	r2, r5
    3f4a:	d101      	bne.n	3f50 <init_mem_slab_module+0x28>
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    3f4c:	331c      	adds	r3, #28
    3f4e:	e7ee      	b.n	3f2e <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
    3f50:	695e      	ldr	r6, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    3f52:	3201      	adds	r2, #1
		*(char **)p = slab->free_list;
    3f54:	600e      	str	r6, [r1, #0]
		slab->free_list = p;
    3f56:	6159      	str	r1, [r3, #20]
		p += slab->block_size;
    3f58:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
    3f5a:	e7f5      	b.n	3f48 <init_mem_slab_module+0x20>
	return rc;
    3f5c:	f06f 0015 	mvn.w	r0, #21
    3f60:	e7e8      	b.n	3f34 <init_mem_slab_module+0xc>
    3f62:	bf00      	nop
    3f64:	20000218 	.word	0x20000218
    3f68:	20000218 	.word	0x20000218

00003f6c <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    3f6c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3f6e:	460c      	mov	r4, r1
	__asm__ volatile(
    3f70:	f04f 0520 	mov.w	r5, #32
    3f74:	f3ef 8111 	mrs	r1, BASEPRI
    3f78:	f385 8812 	msr	BASEPRI_MAX, r5
    3f7c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    3f80:	6945      	ldr	r5, [r0, #20]
    3f82:	b15d      	cbz	r5, 3f9c <k_mem_slab_alloc+0x30>
		/* take a free block */
		*mem = slab->free_list;
    3f84:	6025      	str	r5, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    3f86:	682b      	ldr	r3, [r5, #0]
    3f88:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    3f8a:	6983      	ldr	r3, [r0, #24]
    3f8c:	3301      	adds	r3, #1
    3f8e:	6183      	str	r3, [r0, #24]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    3f90:	2000      	movs	r0, #0
	__asm__ volatile(
    3f92:	f381 8811 	msr	BASEPRI, r1
    3f96:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
    3f9a:	e011      	b.n	3fc0 <k_mem_slab_alloc+0x54>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    3f9c:	ea52 0c03 	orrs.w	ip, r2, r3
    3fa0:	d103      	bne.n	3faa <k_mem_slab_alloc+0x3e>
		result = -ENOMEM;
    3fa2:	f06f 000b 	mvn.w	r0, #11
		*mem = NULL;
    3fa6:	6025      	str	r5, [r4, #0]
		result = -ENOMEM;
    3fa8:	e7f3      	b.n	3f92 <k_mem_slab_alloc+0x26>
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    3faa:	e9cd 2300 	strd	r2, r3, [sp]
    3fae:	4602      	mov	r2, r0
    3fb0:	3008      	adds	r0, #8
    3fb2:	f000 fb4d 	bl	4650 <z_pend_curr>
		if (result == 0) {
    3fb6:	b918      	cbnz	r0, 3fc0 <k_mem_slab_alloc+0x54>
			*mem = _current->base.swap_data;
    3fb8:	4b02      	ldr	r3, [pc, #8]	; (3fc4 <k_mem_slab_alloc+0x58>)
    3fba:	689b      	ldr	r3, [r3, #8]
    3fbc:	695b      	ldr	r3, [r3, #20]
    3fbe:	6023      	str	r3, [r4, #0]
}
    3fc0:	b003      	add	sp, #12
    3fc2:	bd30      	pop	{r4, r5, pc}
    3fc4:	20000ba0 	.word	0x20000ba0

00003fc8 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    3fc8:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    3fcc:	9e0e      	ldr	r6, [sp, #56]	; 0x38
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    3fce:	f100 0558 	add.w	r5, r0, #88	; 0x58
    3fd2:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    3fd4:	2604      	movs	r6, #4
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    3fd6:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	thread_base->pended_on = NULL;
    3fda:	2500      	movs	r5, #0
{
    3fdc:	4604      	mov	r4, r0
	thread_base->thread_state = (uint8_t)initial_state;
    3fde:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    3fe0:	9e0d      	ldr	r6, [sp, #52]	; 0x34
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    3fe2:	e9c0 5506 	strd	r5, r5, [r0, #24]
    3fe6:	7386      	strb	r6, [r0, #14]
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3fe8:	1dd6      	adds	r6, r2, #7
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3fea:	9a0c      	ldr	r2, [sp, #48]	; 0x30
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3fec:	f026 0607 	bic.w	r6, r6, #7
	new_thread->stack_info.size = stack_buf_size;
    3ff0:	e9c0 1619 	strd	r1, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    3ff4:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    3ff6:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    3ff8:	66c5      	str	r5, [r0, #108]	; 0x6c
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3ffa:	9202      	str	r2, [sp, #8]
    3ffc:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
	stack_ptr = (char *)stack + stack_obj_size;
    3ffe:	eb01 0806 	add.w	r8, r1, r6
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    4002:	9201      	str	r2, [sp, #4]
    4004:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    4006:	9200      	str	r2, [sp, #0]
    4008:	4642      	mov	r2, r8
    400a:	f7fd faa1 	bl	1550 <arch_new_thread>
	if (!_current) {
    400e:	4b05      	ldr	r3, [pc, #20]	; (4024 <CONFIG_FPROTECT_BLOCK_SIZE+0x24>)
	new_thread->init_data = NULL;
    4010:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    4012:	689b      	ldr	r3, [r3, #8]
    4014:	b103      	cbz	r3, 4018 <CONFIG_FPROTECT_BLOCK_SIZE+0x18>
	new_thread->resource_pool = _current->resource_pool;
    4016:	6f1b      	ldr	r3, [r3, #112]	; 0x70
}
    4018:	4640      	mov	r0, r8
    401a:	6723      	str	r3, [r4, #112]	; 0x70
    401c:	b004      	add	sp, #16
    401e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4022:	bf00      	nop
    4024:	20000ba0 	.word	0x20000ba0

00004028 <z_init_static_threads>:
{
    4028:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    402c:	4c29      	ldr	r4, [pc, #164]	; (40d4 <z_init_static_threads+0xac>)
	_FOREACH_STATIC_THREAD(thread_data) {
    402e:	4d2a      	ldr	r5, [pc, #168]	; (40d8 <z_init_static_threads+0xb0>)
{
    4030:	b087      	sub	sp, #28
    4032:	4626      	mov	r6, r4
	_FOREACH_STATIC_THREAD(thread_data) {
    4034:	42ae      	cmp	r6, r5
    4036:	f104 0430 	add.w	r4, r4, #48	; 0x30
    403a:	d30f      	bcc.n	405c <z_init_static_threads+0x34>
	k_sched_lock();
    403c:	f000 f9c6 	bl	43cc <k_sched_lock>
    4040:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    4044:	f240 37e7 	movw	r7, #999	; 0x3e7
	_FOREACH_STATIC_THREAD(thread_data) {
    4048:	4c22      	ldr	r4, [pc, #136]	; (40d4 <z_init_static_threads+0xac>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    404a:	f8df 9090 	ldr.w	r9, [pc, #144]	; 40dc <z_init_static_threads+0xb4>
    404e:	42ac      	cmp	r4, r5
    4050:	d320      	bcc.n	4094 <z_init_static_threads+0x6c>
}
    4052:	b007      	add	sp, #28
    4054:	e8bd 43f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, lr}
	k_sched_unlock();
    4058:	f000 bb88 	b.w	476c <k_sched_unlock>
		z_setup_new_thread(
    405c:	f854 3c04 	ldr.w	r3, [r4, #-4]
    4060:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    4064:	9305      	str	r3, [sp, #20]
    4066:	f854 3c10 	ldr.w	r3, [r4, #-16]
    406a:	9304      	str	r3, [sp, #16]
    406c:	f854 3c14 	ldr.w	r3, [r4, #-20]
    4070:	9303      	str	r3, [sp, #12]
    4072:	f854 3c18 	ldr.w	r3, [r4, #-24]
    4076:	9302      	str	r3, [sp, #8]
    4078:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    407c:	9301      	str	r3, [sp, #4]
    407e:	f854 3c20 	ldr.w	r3, [r4, #-32]
    4082:	9300      	str	r3, [sp, #0]
    4084:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    4088:	f7ff ff9e 	bl	3fc8 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    408c:	f854 3c30 	ldr.w	r3, [r4, #-48]
    4090:	655e      	str	r6, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    4092:	e7ce      	b.n	4032 <z_init_static_threads+0xa>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    4094:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4096:	1c5a      	adds	r2, r3, #1
    4098:	d00d      	beq.n	40b6 <z_init_static_threads+0x8e>
    409a:	2100      	movs	r1, #0
    409c:	4638      	mov	r0, r7
					    K_MSEC(thread_data->init_delay));
    409e:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    40a2:	fbc3 0106 	smlal	r0, r1, r3, r6
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    40a6:	ea51 33c3 	orrs.w	r3, r1, r3, lsl #15
			schedule_new_thread(thread_data->init_thread,
    40aa:	f8d4 8000 	ldr.w	r8, [r4]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    40ae:	d104      	bne.n	40ba <z_init_static_threads+0x92>
	z_sched_start(thread);
    40b0:	4640      	mov	r0, r8
    40b2:	f000 fa71 	bl	4598 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    40b6:	3430      	adds	r4, #48	; 0x30
    40b8:	e7c9      	b.n	404e <z_init_static_threads+0x26>
    40ba:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    40be:	2300      	movs	r3, #0
    40c0:	f7fc f848 	bl	154 <__aeabi_uldivmod>
    40c4:	4602      	mov	r2, r0
    40c6:	460b      	mov	r3, r1
    40c8:	f108 0018 	add.w	r0, r8, #24
    40cc:	4649      	mov	r1, r9
    40ce:	f000 fcd3 	bl	4a78 <z_add_timeout>
    40d2:	e7f0      	b.n	40b6 <z_init_static_threads+0x8e>
    40d4:	20000218 	.word	0x20000218
    40d8:	20000218 	.word	0x20000218
    40dc:	000067b7 	.word	0x000067b7

000040e0 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    40e0:	b508      	push	{r3, lr}
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    40e2:	4c0b      	ldr	r4, [pc, #44]	; (4110 <idle+0x30>)
	return !z_sys_post_kernel;
    40e4:	4d0b      	ldr	r5, [pc, #44]	; (4114 <idle+0x34>)
	__asm__ volatile(
    40e6:	f04f 0220 	mov.w	r2, #32
    40ea:	f3ef 8311 	mrs	r3, BASEPRI
    40ee:	f382 8812 	msr	BASEPRI_MAX, r2
    40f2:	f3bf 8f6f 	isb	sy
    40f6:	f002 fbed 	bl	68d4 <z_get_next_timeout_expiry>
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    40fa:	782b      	ldrb	r3, [r5, #0]
		_kernel.idle = z_get_next_timeout_expiry();
    40fc:	61a0      	str	r0, [r4, #24]
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    40fe:	b913      	cbnz	r3, 4106 <idle+0x26>
	arch_cpu_idle();
    4100:	f7fd f950 	bl	13a4 <arch_cpu_idle>
}
    4104:	e7ef      	b.n	40e6 <idle+0x6>
    4106:	f7fc ff99 	bl	103c <pm_system_suspend>
    410a:	2800      	cmp	r0, #0
    410c:	d1eb      	bne.n	40e6 <idle+0x6>
    410e:	e7f7      	b.n	4100 <idle+0x20>
    4110:	20000ba0 	.word	0x20000ba0
    4114:	20000db1 	.word	0x20000db1

00004118 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    4118:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    411c:	4604      	mov	r4, r0
    411e:	4617      	mov	r7, r2
    4120:	461e      	mov	r6, r3
    4122:	f04f 0320 	mov.w	r3, #32
    4126:	f3ef 8811 	mrs	r8, BASEPRI
    412a:	f383 8812 	msr	BASEPRI_MAX, r3
    412e:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    4132:	68c3      	ldr	r3, [r0, #12]
    4134:	4a32      	ldr	r2, [pc, #200]	; (4200 <z_impl_k_mutex_lock+0xe8>)
    4136:	b16b      	cbz	r3, 4154 <z_impl_k_mutex_lock+0x3c>
    4138:	6880      	ldr	r0, [r0, #8]
    413a:	6891      	ldr	r1, [r2, #8]
    413c:	4288      	cmp	r0, r1
    413e:	d019      	beq.n	4174 <z_impl_k_mutex_lock+0x5c>
		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    4140:	ea57 0306 	orrs.w	r3, r7, r6
    4144:	d118      	bne.n	4178 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    4146:	f388 8811 	msr	BASEPRI, r8
    414a:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EBUSY);

		return -EBUSY;
    414e:	f06f 000f 	mvn.w	r0, #15
    4152:	e00c      	b.n	416e <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
    4154:	6891      	ldr	r1, [r2, #8]
    4156:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
    415a:	3301      	adds	r3, #1
    415c:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    415e:	6893      	ldr	r3, [r2, #8]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    4160:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
    4162:	60a3      	str	r3, [r4, #8]
    4164:	f388 8811 	msr	BASEPRI, r8
    4168:	f3bf 8f6f 	isb	sy
		return 0;
    416c:	2000      	movs	r0, #0
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    416e:	b002      	add	sp, #8
    4170:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    4174:	6921      	ldr	r1, [r4, #16]
    4176:	e7f0      	b.n	415a <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    4178:	f991 100e 	ldrsb.w	r1, [r1, #14]
    417c:	f990 300e 	ldrsb.w	r3, [r0, #14]
	thread->base.thread_state &= ~states;
}

static inline bool z_is_under_prio_ceiling(int prio)
{
	return prio >= CONFIG_PRIORITY_CEILING;
    4180:	f06f 027e 	mvn.w	r2, #126	; 0x7e
    4184:	4299      	cmp	r1, r3
    4186:	bfa8      	it	ge
    4188:	4619      	movge	r1, r3
    418a:	4291      	cmp	r1, r2
    418c:	bfb8      	it	lt
    418e:	4611      	movlt	r1, r2
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    4190:	428b      	cmp	r3, r1
    4192:	dd2e      	ble.n	41f2 <z_impl_k_mutex_lock+0xda>
		resched = adjust_owner_prio(mutex, new_prio);
    4194:	f002 fab2 	bl	66fc <adjust_owner_prio.isra.0>
    4198:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    419a:	4622      	mov	r2, r4
    419c:	4641      	mov	r1, r8
    419e:	e9cd 7600 	strd	r7, r6, [sp]
    41a2:	4818      	ldr	r0, [pc, #96]	; (4204 <z_impl_k_mutex_lock+0xec>)
    41a4:	f000 fa54 	bl	4650 <z_pend_curr>
	if (got_mutex == 0) {
    41a8:	2800      	cmp	r0, #0
    41aa:	d0e0      	beq.n	416e <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
    41ac:	f04f 0320 	mov.w	r3, #32
    41b0:	f3ef 8611 	mrs	r6, BASEPRI
    41b4:	f383 8812 	msr	BASEPRI_MAX, r3
    41b8:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    41bc:	6823      	ldr	r3, [r4, #0]
    41be:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    41c0:	429c      	cmp	r4, r3
    41c2:	d00a      	beq.n	41da <z_impl_k_mutex_lock+0xc2>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    41c4:	b14b      	cbz	r3, 41da <z_impl_k_mutex_lock+0xc2>
    41c6:	f993 300e 	ldrsb.w	r3, [r3, #14]
    41ca:	4299      	cmp	r1, r3
    41cc:	bfa8      	it	ge
    41ce:	4619      	movge	r1, r3
    41d0:	f06f 037e 	mvn.w	r3, #126	; 0x7e
    41d4:	4299      	cmp	r1, r3
    41d6:	bfb8      	it	lt
    41d8:	4619      	movlt	r1, r3
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    41da:	68a0      	ldr	r0, [r4, #8]
    41dc:	f002 fa8e 	bl	66fc <adjust_owner_prio.isra.0>
    41e0:	b900      	cbnz	r0, 41e4 <z_impl_k_mutex_lock+0xcc>
	if (resched) {
    41e2:	b145      	cbz	r5, 41f6 <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
    41e4:	4631      	mov	r1, r6
    41e6:	4807      	ldr	r0, [pc, #28]	; (4204 <z_impl_k_mutex_lock+0xec>)
    41e8:	f000 f8de 	bl	43a8 <z_reschedule>
	return -EAGAIN;
    41ec:	f06f 000a 	mvn.w	r0, #10
    41f0:	e7bd      	b.n	416e <z_impl_k_mutex_lock+0x56>
	bool resched = false;
    41f2:	2500      	movs	r5, #0
    41f4:	e7d1      	b.n	419a <z_impl_k_mutex_lock+0x82>
	__asm__ volatile(
    41f6:	f386 8811 	msr	BASEPRI, r6
    41fa:	f3bf 8f6f 	isb	sy
    41fe:	e7f5      	b.n	41ec <z_impl_k_mutex_lock+0xd4>
    4200:	20000ba0 	.word	0x20000ba0
    4204:	20000db2 	.word	0x20000db2

00004208 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    4208:	b538      	push	{r3, r4, r5, lr}

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    420a:	6883      	ldr	r3, [r0, #8]
{
    420c:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    420e:	2b00      	cmp	r3, #0
    4210:	d032      	beq.n	4278 <z_impl_k_mutex_unlock+0x70>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    4212:	4a1c      	ldr	r2, [pc, #112]	; (4284 <z_impl_k_mutex_unlock+0x7c>)
    4214:	6892      	ldr	r2, [r2, #8]
    4216:	4293      	cmp	r3, r2
    4218:	d131      	bne.n	427e <z_impl_k_mutex_unlock+0x76>
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    421a:	7bda      	ldrb	r2, [r3, #15]
    421c:	3a01      	subs	r2, #1
    421e:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    4220:	68c3      	ldr	r3, [r0, #12]
    4222:	2b01      	cmp	r3, #1
    4224:	d905      	bls.n	4232 <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    4226:	3b01      	subs	r3, #1
    4228:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	k_sched_unlock();
    422a:	f000 fa9f 	bl	476c <k_sched_unlock>

	return 0;
    422e:	2000      	movs	r0, #0
}
    4230:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    4232:	f04f 0320 	mov.w	r3, #32
    4236:	f3ef 8511 	mrs	r5, BASEPRI
    423a:	f383 8812 	msr	BASEPRI_MAX, r3
    423e:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    4242:	6901      	ldr	r1, [r0, #16]
    4244:	6880      	ldr	r0, [r0, #8]
    4246:	f002 fa59 	bl	66fc <adjust_owner_prio.isra.0>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    424a:	4620      	mov	r0, r4
    424c:	f002 fb14 	bl	6878 <z_unpend_first_thread>
	mutex->owner = new_owner;
    4250:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    4252:	b158      	cbz	r0, 426c <z_impl_k_mutex_unlock+0x64>
		mutex->owner_orig_prio = new_owner->base.prio;
    4254:	f990 200e 	ldrsb.w	r2, [r0, #14]
    4258:	6122      	str	r2, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    425a:	2200      	movs	r2, #0
    425c:	6782      	str	r2, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    425e:	f002 fa9a 	bl	6796 <z_ready_thread>
		z_reschedule(&lock, key);
    4262:	4629      	mov	r1, r5
    4264:	4808      	ldr	r0, [pc, #32]	; (4288 <z_impl_k_mutex_unlock+0x80>)
    4266:	f000 f89f 	bl	43a8 <z_reschedule>
    426a:	e7de      	b.n	422a <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    426c:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    426e:	f385 8811 	msr	BASEPRI, r5
    4272:	f3bf 8f6f 	isb	sy
    4276:	e7d8      	b.n	422a <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    4278:	f06f 0015 	mvn.w	r0, #21
    427c:	e7d8      	b.n	4230 <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
    427e:	f04f 30ff 	mov.w	r0, #4294967295
    4282:	e7d5      	b.n	4230 <z_impl_k_mutex_unlock+0x28>
    4284:	20000ba0 	.word	0x20000ba0
    4288:	20000db2 	.word	0x20000db2

0000428c <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    428c:	b538      	push	{r3, r4, r5, lr}
    428e:	4604      	mov	r4, r0
	__asm__ volatile(
    4290:	f04f 0320 	mov.w	r3, #32
    4294:	f3ef 8511 	mrs	r5, BASEPRI
    4298:	f383 8812 	msr	BASEPRI_MAX, r3
    429c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    42a0:	f002 faea 	bl	6878 <z_unpend_first_thread>

	if (thread != NULL) {
    42a4:	b148      	cbz	r0, 42ba <z_impl_k_sem_give+0x2e>
    42a6:	2200      	movs	r2, #0
    42a8:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    42aa:	f002 fa74 	bl	6796 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    42ae:	4629      	mov	r1, r5

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    42b0:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    42b4:	4804      	ldr	r0, [pc, #16]	; (42c8 <z_impl_k_sem_give+0x3c>)
    42b6:	f000 b877 	b.w	43a8 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    42ba:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    42be:	429a      	cmp	r2, r3
    42c0:	bf18      	it	ne
    42c2:	3301      	addne	r3, #1
    42c4:	60a3      	str	r3, [r4, #8]
}
    42c6:	e7f2      	b.n	42ae <z_impl_k_sem_give+0x22>
    42c8:	20000db2 	.word	0x20000db2

000042cc <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    42cc:	b513      	push	{r0, r1, r4, lr}
    42ce:	f04f 0420 	mov.w	r4, #32
    42d2:	f3ef 8111 	mrs	r1, BASEPRI
    42d6:	f384 8812 	msr	BASEPRI_MAX, r4
    42da:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    42de:	6884      	ldr	r4, [r0, #8]
    42e0:	b144      	cbz	r4, 42f4 <z_impl_k_sem_take+0x28>
		sem->count--;
    42e2:	3c01      	subs	r4, #1
    42e4:	6084      	str	r4, [r0, #8]
	__asm__ volatile(
    42e6:	f381 8811 	msr	BASEPRI, r1
    42ea:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    42ee:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    42f0:	b002      	add	sp, #8
    42f2:	bd10      	pop	{r4, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    42f4:	ea52 0403 	orrs.w	r4, r2, r3
    42f8:	d106      	bne.n	4308 <z_impl_k_sem_take+0x3c>
    42fa:	f381 8811 	msr	BASEPRI, r1
    42fe:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    4302:	f06f 000f 	mvn.w	r0, #15
    4306:	e7f3      	b.n	42f0 <z_impl_k_sem_take+0x24>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    4308:	e9cd 2300 	strd	r2, r3, [sp]
    430c:	4602      	mov	r2, r0
    430e:	4802      	ldr	r0, [pc, #8]	; (4318 <z_impl_k_sem_take+0x4c>)
    4310:	f000 f99e 	bl	4650 <z_pend_curr>
	return ret;
    4314:	e7ec      	b.n	42f0 <z_impl_k_sem_take+0x24>
    4316:	bf00      	nop
    4318:	20000db2 	.word	0x20000db2

0000431c <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(struct k_thread *curr)
{
    431c:	b538      	push	{r3, r4, r5, lr}
	int ret = slice_ticks;
    431e:	4d07      	ldr	r5, [pc, #28]	; (433c <z_reset_time_slice+0x20>)
    4320:	682c      	ldr	r4, [r5, #0]
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time(curr) != 0) {
    4322:	b154      	cbz	r4, 433a <z_reset_time_slice+0x1e>
		_current_cpu->slice_ticks = slice_time(curr) + sys_clock_elapsed();
    4324:	f7fe ff3a 	bl	319c <sys_clock_elapsed>
    4328:	4b05      	ldr	r3, [pc, #20]	; (4340 <z_reset_time_slice+0x24>)
    432a:	4404      	add	r4, r0
    432c:	611c      	str	r4, [r3, #16]
		z_set_timeout_expiry(slice_time(curr), false);
    432e:	6828      	ldr	r0, [r5, #0]
    4330:	2100      	movs	r1, #0
	}
}
    4332:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		z_set_timeout_expiry(slice_time(curr), false);
    4336:	f002 badd 	b.w	68f4 <z_set_timeout_expiry>
}
    433a:	bd38      	pop	{r3, r4, r5, pc}
    433c:	20000bd0 	.word	0x20000bd0
    4340:	20000ba0 	.word	0x20000ba0

00004344 <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    4344:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4346:	4604      	mov	r4, r0
    4348:	460d      	mov	r5, r1
	__asm__ volatile(
    434a:	f04f 0320 	mov.w	r3, #32
    434e:	f3ef 8711 	mrs	r7, BASEPRI
    4352:	f383 8812 	msr	BASEPRI_MAX, r3
    4356:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    435a:	2100      	movs	r1, #0
			return (uint32_t)((t * to_hz + off) / from_hz);
    435c:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
    4360:	f240 30e7 	movw	r0, #999	; 0x3e7
    4364:	4e0d      	ldr	r6, [pc, #52]	; (439c <k_sched_time_slice_set+0x58>)
    4366:	2300      	movs	r3, #0
    4368:	6131      	str	r1, [r6, #16]
    436a:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    436e:	fbe4 010c 	umlal	r0, r1, r4, ip
    4372:	f7fb feef 	bl	154 <__aeabi_uldivmod>
		slice_ticks = k_ms_to_ticks_ceil32(slice);
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    4376:	2c00      	cmp	r4, #0
    4378:	4b09      	ldr	r3, [pc, #36]	; (43a0 <k_sched_time_slice_set+0x5c>)
    437a:	dc0a      	bgt.n	4392 <k_sched_time_slice_set+0x4e>
			/* It's not possible to reliably set a 1-tick
			 * timeout if ticks aren't regular.
			 */
			slice_ticks = MAX(2, slice_ticks);
    437c:	6018      	str	r0, [r3, #0]
		}
		slice_max_prio = prio;
    437e:	4b09      	ldr	r3, [pc, #36]	; (43a4 <k_sched_time_slice_set+0x60>)
		z_reset_time_slice(_current);
    4380:	68b0      	ldr	r0, [r6, #8]
		slice_max_prio = prio;
    4382:	601d      	str	r5, [r3, #0]
		z_reset_time_slice(_current);
    4384:	f7ff ffca 	bl	431c <z_reset_time_slice>
	__asm__ volatile(
    4388:	f387 8811 	msr	BASEPRI, r7
    438c:	f3bf 8f6f 	isb	sy
	}
}
    4390:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			slice_ticks = MAX(2, slice_ticks);
    4392:	2802      	cmp	r0, #2
    4394:	bfb8      	it	lt
    4396:	2002      	movlt	r0, #2
    4398:	e7f0      	b.n	437c <k_sched_time_slice_set+0x38>
    439a:	bf00      	nop
    439c:	20000ba0 	.word	0x20000ba0
    43a0:	20000bd0 	.word	0x20000bd0
    43a4:	20000bcc 	.word	0x20000bcc

000043a8 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    43a8:	b949      	cbnz	r1, 43be <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    43aa:	f3ef 8005 	mrs	r0, IPSR
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    43ae:	b930      	cbnz	r0, 43be <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    43b0:	4b05      	ldr	r3, [pc, #20]	; (43c8 <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    43b2:	69da      	ldr	r2, [r3, #28]
    43b4:	689b      	ldr	r3, [r3, #8]
    43b6:	429a      	cmp	r2, r3
    43b8:	d001      	beq.n	43be <z_reschedule+0x16>
	ret = arch_swap(key);
    43ba:	f7fd b873 	b.w	14a4 <arch_swap>
    43be:	f381 8811 	msr	BASEPRI, r1
    43c2:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    43c6:	4770      	bx	lr
    43c8:	20000ba0 	.word	0x20000ba0

000043cc <k_sched_lock>:
	__asm__ volatile(
    43cc:	f04f 0320 	mov.w	r3, #32
    43d0:	f3ef 8111 	mrs	r1, BASEPRI
    43d4:	f383 8812 	msr	BASEPRI_MAX, r3
    43d8:	f3bf 8f6f 	isb	sy
    43dc:	4b04      	ldr	r3, [pc, #16]	; (43f0 <k_sched_lock+0x24>)
    43de:	689a      	ldr	r2, [r3, #8]
    43e0:	7bd3      	ldrb	r3, [r2, #15]
    43e2:	3b01      	subs	r3, #1
    43e4:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    43e6:	f381 8811 	msr	BASEPRI, r1
    43ea:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    43ee:	4770      	bx	lr
    43f0:	20000ba0 	.word	0x20000ba0

000043f4 <update_cache>:
{
    43f4:	b538      	push	{r3, r4, r5, lr}
    43f6:	4602      	mov	r2, r0
	return _priq_run_best(curr_cpu_runq());
    43f8:	480c      	ldr	r0, [pc, #48]	; (442c <update_cache+0x38>)
    43fa:	f002 f9c6 	bl	678a <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    43fe:	4d0c      	ldr	r5, [pc, #48]	; (4430 <update_cache+0x3c>)
    4400:	4604      	mov	r4, r0
    4402:	b900      	cbnz	r0, 4406 <update_cache+0x12>
    4404:	68ec      	ldr	r4, [r5, #12]
	if (z_is_thread_prevented_from_running(_current)) {
    4406:	68ab      	ldr	r3, [r5, #8]
	if (preempt_ok != 0) {
    4408:	b94a      	cbnz	r2, 441e <update_cache+0x2a>
	if (z_is_thread_prevented_from_running(_current)) {
    440a:	7b5a      	ldrb	r2, [r3, #13]
    440c:	06d2      	lsls	r2, r2, #27
    440e:	d106      	bne.n	441e <update_cache+0x2a>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    4410:	69a2      	ldr	r2, [r4, #24]
    4412:	b922      	cbnz	r2, 441e <update_cache+0x2a>
	if (is_preempt(_current) || is_metairq(thread)) {
    4414:	89da      	ldrh	r2, [r3, #14]
    4416:	2a7f      	cmp	r2, #127	; 0x7f
    4418:	d901      	bls.n	441e <update_cache+0x2a>
		_kernel.ready_q.cache = _current;
    441a:	61eb      	str	r3, [r5, #28]
}
    441c:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    441e:	429c      	cmp	r4, r3
    4420:	d002      	beq.n	4428 <update_cache+0x34>
			z_reset_time_slice(thread);
    4422:	4620      	mov	r0, r4
    4424:	f7ff ff7a 	bl	431c <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    4428:	61ec      	str	r4, [r5, #28]
}
    442a:	e7f7      	b.n	441c <update_cache+0x28>
    442c:	20000bc0 	.word	0x20000bc0
    4430:	20000ba0 	.word	0x20000ba0

00004434 <move_thread_to_end_of_prio_q>:
{
    4434:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    4436:	f990 200d 	ldrsb.w	r2, [r0, #13]
{
    443a:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    443c:	2a00      	cmp	r2, #0
	return (thread->base.thread_state & state) != 0U;
    443e:	7b43      	ldrb	r3, [r0, #13]
    4440:	da04      	bge.n	444c <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4442:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    4446:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    4448:	f002 f967 	bl	671a <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    444c:	7b4b      	ldrb	r3, [r1, #13]
	return list->head == list;
    444e:	4a15      	ldr	r2, [pc, #84]	; (44a4 <move_thread_to_end_of_prio_q+0x70>)
    4450:	f063 037f 	orn	r3, r3, #127	; 0x7f
    4454:	734b      	strb	r3, [r1, #13]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4456:	f102 0520 	add.w	r5, r2, #32
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    445a:	e9d2 3408 	ldrd	r3, r4, [r2, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    445e:	42ab      	cmp	r3, r5
    4460:	d01b      	beq.n	449a <move_thread_to_end_of_prio_q+0x66>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4462:	b1d3      	cbz	r3, 449a <move_thread_to_end_of_prio_q+0x66>
	int32_t b1 = thread_1->base.prio;
    4464:	f991 600e 	ldrsb.w	r6, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    4468:	f993 000e 	ldrsb.w	r0, [r3, #14]
	if (b1 != b2) {
    446c:	4286      	cmp	r6, r0
    446e:	d00f      	beq.n	4490 <move_thread_to_end_of_prio_q+0x5c>
		return b2 - b1;
    4470:	1b80      	subs	r0, r0, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    4472:	2800      	cmp	r0, #0
    4474:	dd0c      	ble.n	4490 <move_thread_to_end_of_prio_q+0x5c>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    4476:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    4478:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    447c:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    447e:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    4480:	6890      	ldr	r0, [r2, #8]
}
    4482:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    4486:	1a43      	subs	r3, r0, r1
    4488:	4258      	negs	r0, r3
    448a:	4158      	adcs	r0, r3
    448c:	f7ff bfb2 	b.w	43f4 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    4490:	42a3      	cmp	r3, r4
    4492:	d002      	beq.n	449a <move_thread_to_end_of_prio_q+0x66>
    4494:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4496:	2b00      	cmp	r3, #0
    4498:	d1e6      	bne.n	4468 <move_thread_to_end_of_prio_q+0x34>
	node->prev = tail;
    449a:	e9c1 5400 	strd	r5, r4, [r1]
	tail->next = node;
    449e:	6021      	str	r1, [r4, #0]
	list->tail = node;
    44a0:	6251      	str	r1, [r2, #36]	; 0x24
}
    44a2:	e7ed      	b.n	4480 <move_thread_to_end_of_prio_q+0x4c>
    44a4:	20000ba0 	.word	0x20000ba0

000044a8 <z_time_slice>:
{
    44a8:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    44aa:	f04f 0320 	mov.w	r3, #32
    44ae:	f3ef 8511 	mrs	r5, BASEPRI
    44b2:	f383 8812 	msr	BASEPRI_MAX, r3
    44b6:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    44ba:	4b17      	ldr	r3, [pc, #92]	; (4518 <z_time_slice+0x70>)
    44bc:	4a17      	ldr	r2, [pc, #92]	; (451c <z_time_slice+0x74>)
    44be:	689c      	ldr	r4, [r3, #8]
    44c0:	6811      	ldr	r1, [r2, #0]
    44c2:	428c      	cmp	r4, r1
    44c4:	d107      	bne.n	44d6 <z_time_slice+0x2e>
	z_reset_time_slice(curr);
    44c6:	4620      	mov	r0, r4
    44c8:	f7ff ff28 	bl	431c <z_reset_time_slice>
	__asm__ volatile(
    44cc:	f385 8811 	msr	BASEPRI, r5
    44d0:	f3bf 8f6f 	isb	sy
}
    44d4:	bd38      	pop	{r3, r4, r5, pc}
	pending_current = NULL;
    44d6:	2100      	movs	r1, #0
    44d8:	6011      	str	r1, [r2, #0]
	int ret = slice_ticks;
    44da:	4a11      	ldr	r2, [pc, #68]	; (4520 <z_time_slice+0x78>)
	if (slice_time(_current) && sliceable(_current)) {
    44dc:	6812      	ldr	r2, [r2, #0]
    44de:	b1c2      	cbz	r2, 4512 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    44e0:	89e2      	ldrh	r2, [r4, #14]
    44e2:	2a7f      	cmp	r2, #127	; 0x7f
    44e4:	d815      	bhi.n	4512 <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    44e6:	7b62      	ldrb	r2, [r4, #13]
    44e8:	06d2      	lsls	r2, r2, #27
    44ea:	d112      	bne.n	4512 <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    44ec:	4a0d      	ldr	r2, [pc, #52]	; (4524 <z_time_slice+0x7c>)
    44ee:	f994 100e 	ldrsb.w	r1, [r4, #14]
    44f2:	6812      	ldr	r2, [r2, #0]
    44f4:	4291      	cmp	r1, r2
    44f6:	db0c      	blt.n	4512 <z_time_slice+0x6a>
	if (slice_time(_current) && sliceable(_current)) {
    44f8:	4a0b      	ldr	r2, [pc, #44]	; (4528 <z_time_slice+0x80>)
    44fa:	4294      	cmp	r4, r2
    44fc:	d009      	beq.n	4512 <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    44fe:	691a      	ldr	r2, [r3, #16]
    4500:	4282      	cmp	r2, r0
    4502:	dc03      	bgt.n	450c <z_time_slice+0x64>
		move_thread_to_end_of_prio_q(curr);
    4504:	4620      	mov	r0, r4
    4506:	f7ff ff95 	bl	4434 <move_thread_to_end_of_prio_q>
    450a:	e7dc      	b.n	44c6 <z_time_slice+0x1e>
			_current_cpu->slice_ticks -= ticks;
    450c:	1a12      	subs	r2, r2, r0
		_current_cpu->slice_ticks = 0;
    450e:	611a      	str	r2, [r3, #16]
    4510:	e7dc      	b.n	44cc <z_time_slice+0x24>
    4512:	2200      	movs	r2, #0
    4514:	e7fb      	b.n	450e <z_time_slice+0x66>
    4516:	bf00      	nop
    4518:	20000ba0 	.word	0x20000ba0
    451c:	20000bc8 	.word	0x20000bc8
    4520:	20000bd0 	.word	0x20000bd0
    4524:	20000bcc 	.word	0x20000bcc
    4528:	20000440 	.word	0x20000440

0000452c <ready_thread>:
{
    452c:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    452e:	f990 200d 	ldrsb.w	r2, [r0, #13]
    4532:	7b43      	ldrb	r3, [r0, #13]
    4534:	2a00      	cmp	r2, #0
    4536:	db2a      	blt.n	458e <ready_thread+0x62>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    4538:	06da      	lsls	r2, r3, #27
    453a:	d128      	bne.n	458e <ready_thread+0x62>
    453c:	6982      	ldr	r2, [r0, #24]
    453e:	bb32      	cbnz	r2, 458e <ready_thread+0x62>
	return list->head == list;
    4540:	4a14      	ldr	r2, [pc, #80]	; (4594 <ready_thread+0x68>)
	thread->base.thread_state |= _THREAD_QUEUED;
    4542:	f063 037f 	orn	r3, r3, #127	; 0x7f
    4546:	7343      	strb	r3, [r0, #13]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4548:	f102 0520 	add.w	r5, r2, #32
	return (node == list->tail) ? NULL : node->next;
    454c:	e9d2 3408 	ldrd	r3, r4, [r2, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4550:	42ab      	cmp	r3, r5
    4552:	d017      	beq.n	4584 <ready_thread+0x58>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4554:	b1b3      	cbz	r3, 4584 <ready_thread+0x58>
	int32_t b1 = thread_1->base.prio;
    4556:	f990 600e 	ldrsb.w	r6, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    455a:	f993 100e 	ldrsb.w	r1, [r3, #14]
	if (b1 != b2) {
    455e:	428e      	cmp	r6, r1
    4560:	d00b      	beq.n	457a <ready_thread+0x4e>
		return b2 - b1;
    4562:	1b89      	subs	r1, r1, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    4564:	2900      	cmp	r1, #0
    4566:	dd08      	ble.n	457a <ready_thread+0x4e>
	sys_dnode_t *const prev = successor->prev;
    4568:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    456a:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    456e:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    4570:	6058      	str	r0, [r3, #4]
		update_cache(0);
    4572:	2000      	movs	r0, #0
}
    4574:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    4576:	f7ff bf3d 	b.w	43f4 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    457a:	42a3      	cmp	r3, r4
    457c:	d002      	beq.n	4584 <ready_thread+0x58>
    457e:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4580:	2b00      	cmp	r3, #0
    4582:	d1ea      	bne.n	455a <ready_thread+0x2e>
	node->prev = tail;
    4584:	e9c0 5400 	strd	r5, r4, [r0]
	tail->next = node;
    4588:	6020      	str	r0, [r4, #0]
	list->tail = node;
    458a:	6250      	str	r0, [r2, #36]	; 0x24
}
    458c:	e7f1      	b.n	4572 <ready_thread+0x46>
}
    458e:	bc70      	pop	{r4, r5, r6}
    4590:	4770      	bx	lr
    4592:	bf00      	nop
    4594:	20000ba0 	.word	0x20000ba0

00004598 <z_sched_start>:
{
    4598:	b510      	push	{r4, lr}
	__asm__ volatile(
    459a:	f04f 0220 	mov.w	r2, #32
    459e:	f3ef 8411 	mrs	r4, BASEPRI
    45a2:	f382 8812 	msr	BASEPRI_MAX, r2
    45a6:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    45aa:	7b42      	ldrb	r2, [r0, #13]
	if (z_has_thread_started(thread)) {
    45ac:	0751      	lsls	r1, r2, #29
    45ae:	d404      	bmi.n	45ba <z_sched_start+0x22>
	__asm__ volatile(
    45b0:	f384 8811 	msr	BASEPRI, r4
    45b4:	f3bf 8f6f 	isb	sy
}
    45b8:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    45ba:	f022 0204 	bic.w	r2, r2, #4
    45be:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    45c0:	f7ff ffb4 	bl	452c <ready_thread>
	z_reschedule(&sched_spinlock, key);
    45c4:	4621      	mov	r1, r4
}
    45c6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    45ca:	4801      	ldr	r0, [pc, #4]	; (45d0 <z_sched_start+0x38>)
    45cc:	f7ff beec 	b.w	43a8 <z_reschedule>
    45d0:	20000db2 	.word	0x20000db2

000045d4 <unready_thread>:
{
    45d4:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    45d6:	f990 200d 	ldrsb.w	r2, [r0, #13]
{
    45da:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    45dc:	2a00      	cmp	r2, #0
	return (thread->base.thread_state & state) != 0U;
    45de:	7b43      	ldrb	r3, [r0, #13]
    45e0:	da04      	bge.n	45ec <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    45e2:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    45e6:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    45e8:	f002 f897 	bl	671a <sys_dlist_remove>
	update_cache(thread == _current);
    45ec:	4b04      	ldr	r3, [pc, #16]	; (4600 <unready_thread+0x2c>)
    45ee:	6898      	ldr	r0, [r3, #8]
    45f0:	1a43      	subs	r3, r0, r1
    45f2:	4258      	negs	r0, r3
    45f4:	4158      	adcs	r0, r3
}
    45f6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    45fa:	f7ff befb 	b.w	43f4 <update_cache>
    45fe:	bf00      	nop
    4600:	20000ba0 	.word	0x20000ba0

00004604 <pend>:
{
    4604:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4608:	4606      	mov	r6, r0
    460a:	4615      	mov	r5, r2
    460c:	461c      	mov	r4, r3
	__asm__ volatile(
    460e:	f04f 0320 	mov.w	r3, #32
    4612:	f3ef 8711 	mrs	r7, BASEPRI
    4616:	f383 8812 	msr	BASEPRI_MAX, r3
    461a:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    461e:	f002 f8ec 	bl	67fa <add_to_waitq_locked>
	__asm__ volatile(
    4622:	f387 8811 	msr	BASEPRI, r7
    4626:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    462a:	f1b4 3fff 	cmp.w	r4, #4294967295
    462e:	bf08      	it	eq
    4630:	f1b5 3fff 	cmpeq.w	r5, #4294967295
    4634:	d008      	beq.n	4648 <pend+0x44>
    4636:	462a      	mov	r2, r5
    4638:	4623      	mov	r3, r4
    463a:	f106 0018 	add.w	r0, r6, #24
    463e:	4903      	ldr	r1, [pc, #12]	; (464c <pend+0x48>)
}
    4640:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    4644:	f000 ba18 	b.w	4a78 <z_add_timeout>
    4648:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    464c:	000067b7 	.word	0x000067b7

00004650 <z_pend_curr>:
{
    4650:	b510      	push	{r4, lr}
    4652:	460c      	mov	r4, r1
	pending_current = _current;
    4654:	4b06      	ldr	r3, [pc, #24]	; (4670 <z_pend_curr+0x20>)
{
    4656:	4611      	mov	r1, r2
	pending_current = _current;
    4658:	6898      	ldr	r0, [r3, #8]
    465a:	4b06      	ldr	r3, [pc, #24]	; (4674 <z_pend_curr+0x24>)
    465c:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    465e:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    4662:	f7ff ffcf 	bl	4604 <pend>
    4666:	4620      	mov	r0, r4
}
    4668:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    466c:	f7fc bf1a 	b.w	14a4 <arch_swap>
    4670:	20000ba0 	.word	0x20000ba0
    4674:	20000bc8 	.word	0x20000bc8

00004678 <z_set_prio>:
{
    4678:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    467a:	4604      	mov	r4, r0
	__asm__ volatile(
    467c:	f04f 0320 	mov.w	r3, #32
    4680:	f3ef 8611 	mrs	r6, BASEPRI
    4684:	f383 8812 	msr	BASEPRI_MAX, r3
    4688:	f3bf 8f6f 	isb	sy
	uint8_t state = thread->base.thread_state;
    468c:	7b43      	ldrb	r3, [r0, #13]
				thread->base.prio = prio;
    468e:	b249      	sxtb	r1, r1
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    4690:	06da      	lsls	r2, r3, #27
    4692:	d133      	bne.n	46fc <z_set_prio+0x84>
		if (need_sched) {
    4694:	6982      	ldr	r2, [r0, #24]
    4696:	bb8a      	cbnz	r2, 46fc <z_set_prio+0x84>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4698:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    469c:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    469e:	f002 f83c 	bl	671a <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    46a2:	7b43      	ldrb	r3, [r0, #13]
	return list->head == list;
    46a4:	4a17      	ldr	r2, [pc, #92]	; (4704 <z_set_prio+0x8c>)
    46a6:	f063 037f 	orn	r3, r3, #127	; 0x7f
    46aa:	7343      	strb	r3, [r0, #13]
				thread->base.prio = prio;
    46ac:	7381      	strb	r1, [r0, #14]
    46ae:	4610      	mov	r0, r2
    46b0:	f850 3f20 	ldr.w	r3, [r0, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    46b4:	4283      	cmp	r3, r0
    46b6:	d01b      	beq.n	46f0 <z_set_prio+0x78>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    46b8:	b1d3      	cbz	r3, 46f0 <z_set_prio+0x78>
	return (node == list->tail) ? NULL : node->next;
    46ba:	6a57      	ldr	r7, [r2, #36]	; 0x24
	int32_t b2 = thread_2->base.prio;
    46bc:	f993 500e 	ldrsb.w	r5, [r3, #14]
	if (b1 != b2) {
    46c0:	42a9      	cmp	r1, r5
    46c2:	d010      	beq.n	46e6 <z_set_prio+0x6e>
		return b2 - b1;
    46c4:	1a6d      	subs	r5, r5, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    46c6:	2d00      	cmp	r5, #0
    46c8:	dd0d      	ble.n	46e6 <z_set_prio+0x6e>
	sys_dnode_t *const prev = successor->prev;
    46ca:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    46cc:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    46d0:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    46d2:	605c      	str	r4, [r3, #4]
			update_cache(1);
    46d4:	2001      	movs	r0, #1
    46d6:	f7ff fe8d 	bl	43f4 <update_cache>
    46da:	2001      	movs	r0, #1
	__asm__ volatile(
    46dc:	f386 8811 	msr	BASEPRI, r6
    46e0:	f3bf 8f6f 	isb	sy
}
    46e4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return (node == list->tail) ? NULL : node->next;
    46e6:	42bb      	cmp	r3, r7
    46e8:	d002      	beq.n	46f0 <z_set_prio+0x78>
    46ea:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    46ec:	2b00      	cmp	r3, #0
    46ee:	d1e5      	bne.n	46bc <z_set_prio+0x44>
	sys_dnode_t *const tail = list->tail;
    46f0:	6a53      	ldr	r3, [r2, #36]	; 0x24
	node->prev = tail;
    46f2:	e9c4 0300 	strd	r0, r3, [r4]
	tail->next = node;
    46f6:	601c      	str	r4, [r3, #0]
	list->tail = node;
    46f8:	6254      	str	r4, [r2, #36]	; 0x24
}
    46fa:	e7eb      	b.n	46d4 <z_set_prio+0x5c>
			thread->base.prio = prio;
    46fc:	2000      	movs	r0, #0
    46fe:	73a1      	strb	r1, [r4, #14]
    4700:	e7ec      	b.n	46dc <z_set_prio+0x64>
    4702:	bf00      	nop
    4704:	20000ba0 	.word	0x20000ba0

00004708 <z_impl_k_thread_suspend>:
{
    4708:	b570      	push	{r4, r5, r6, lr}
    470a:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    470c:	3018      	adds	r0, #24
    470e:	f002 f8cb 	bl	68a8 <z_abort_timeout>
	__asm__ volatile(
    4712:	f04f 0320 	mov.w	r3, #32
    4716:	f3ef 8611 	mrs	r6, BASEPRI
    471a:	f383 8812 	msr	BASEPRI_MAX, r3
    471e:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    4722:	f994 200d 	ldrsb.w	r2, [r4, #13]
	return (thread->base.thread_state & state) != 0U;
    4726:	7b63      	ldrb	r3, [r4, #13]
    4728:	2a00      	cmp	r2, #0
    472a:	da05      	bge.n	4738 <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    472c:	f003 037f 	and.w	r3, r3, #127	; 0x7f
	sys_dlist_remove(&thread->base.qnode_dlist);
    4730:	4620      	mov	r0, r4
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4732:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    4734:	f001 fff1 	bl	671a <sys_dlist_remove>
		update_cache(thread == _current);
    4738:	4d0b      	ldr	r5, [pc, #44]	; (4768 <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    473a:	7b63      	ldrb	r3, [r4, #13]
    473c:	68a8      	ldr	r0, [r5, #8]
    473e:	f043 0310 	orr.w	r3, r3, #16
    4742:	7363      	strb	r3, [r4, #13]
    4744:	1b03      	subs	r3, r0, r4
    4746:	4258      	negs	r0, r3
    4748:	4158      	adcs	r0, r3
    474a:	f7ff fe53 	bl	43f4 <update_cache>
	__asm__ volatile(
    474e:	f386 8811 	msr	BASEPRI, r6
    4752:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    4756:	68ab      	ldr	r3, [r5, #8]
    4758:	42a3      	cmp	r3, r4
    475a:	d103      	bne.n	4764 <z_impl_k_thread_suspend+0x5c>
}
    475c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    4760:	f002 b809 	b.w	6776 <z_reschedule_unlocked>
}
    4764:	bd70      	pop	{r4, r5, r6, pc}
    4766:	bf00      	nop
    4768:	20000ba0 	.word	0x20000ba0

0000476c <k_sched_unlock>:
{
    476c:	b510      	push	{r4, lr}
	__asm__ volatile(
    476e:	f04f 0320 	mov.w	r3, #32
    4772:	f3ef 8411 	mrs	r4, BASEPRI
    4776:	f383 8812 	msr	BASEPRI_MAX, r3
    477a:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    477e:	4b08      	ldr	r3, [pc, #32]	; (47a0 <k_sched_unlock+0x34>)
		update_cache(0);
    4780:	2000      	movs	r0, #0
		++_current->base.sched_locked;
    4782:	689a      	ldr	r2, [r3, #8]
    4784:	7bd3      	ldrb	r3, [r2, #15]
    4786:	3301      	adds	r3, #1
    4788:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    478a:	f7ff fe33 	bl	43f4 <update_cache>
	__asm__ volatile(
    478e:	f384 8811 	msr	BASEPRI, r4
    4792:	f3bf 8f6f 	isb	sy
}
    4796:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    479a:	f001 bfec 	b.w	6776 <z_reschedule_unlocked>
    479e:	bf00      	nop
    47a0:	20000ba0 	.word	0x20000ba0

000047a4 <z_sched_init>:
#else
	init_ready_q(&_kernel.ready_q);
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    47a4:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    47a6:	4b04      	ldr	r3, [pc, #16]	; (47b8 <z_sched_init+0x14>)
    47a8:	4608      	mov	r0, r1
    47aa:	f103 0220 	add.w	r2, r3, #32
	list->tail = (sys_dnode_t *)list;
    47ae:	e9c3 2208 	strd	r2, r2, [r3, #32]
    47b2:	f7ff bdc7 	b.w	4344 <k_sched_time_slice_set>
    47b6:	bf00      	nop
    47b8:	20000ba0 	.word	0x20000ba0

000047bc <z_impl_k_yield>:
#include <syscalls/k_thread_deadline_set_mrsh.c>
#endif
#endif

void z_impl_k_yield(void)
{
    47bc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    47be:	f04f 0320 	mov.w	r3, #32
    47c2:	f3ef 8511 	mrs	r5, BASEPRI
    47c6:	f383 8812 	msr	BASEPRI_MAX, r3
    47ca:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    47ce:	491a      	ldr	r1, [pc, #104]	; (4838 <z_impl_k_yield+0x7c>)
    47d0:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    47d2:	7b43      	ldrb	r3, [r0, #13]
    47d4:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    47d8:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    47da:	f001 ff9e 	bl	671a <sys_dlist_remove>
	return list->head == list;
    47de:	4608      	mov	r0, r1
	}
	queue_thread(_current);
    47e0:	688b      	ldr	r3, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    47e2:	7b5a      	ldrb	r2, [r3, #13]
    47e4:	f062 027f 	orn	r2, r2, #127	; 0x7f
    47e8:	735a      	strb	r2, [r3, #13]
    47ea:	f850 2f20 	ldr.w	r2, [r0, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    47ee:	4282      	cmp	r2, r0
    47f0:	d01c      	beq.n	482c <z_impl_k_yield+0x70>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    47f2:	b1da      	cbz	r2, 482c <z_impl_k_yield+0x70>
	return (node == list->tail) ? NULL : node->next;
    47f4:	6a4f      	ldr	r7, [r1, #36]	; 0x24
	int32_t b1 = thread_1->base.prio;
    47f6:	f993 600e 	ldrsb.w	r6, [r3, #14]
	int32_t b2 = thread_2->base.prio;
    47fa:	f992 400e 	ldrsb.w	r4, [r2, #14]
	if (b1 != b2) {
    47fe:	42a6      	cmp	r6, r4
    4800:	d00f      	beq.n	4822 <z_impl_k_yield+0x66>
		return b2 - b1;
    4802:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    4804:	2c00      	cmp	r4, #0
    4806:	dd0c      	ble.n	4822 <z_impl_k_yield+0x66>
	sys_dnode_t *const prev = successor->prev;
    4808:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    480a:	e9c3 2100 	strd	r2, r1, [r3]
	prev->next = node;
    480e:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    4810:	6053      	str	r3, [r2, #4]
	update_cache(1);
    4812:	2001      	movs	r0, #1
    4814:	f7ff fdee 	bl	43f4 <update_cache>
    4818:	4628      	mov	r0, r5
	z_swap(&sched_spinlock, key);
}
    481a:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    481e:	f7fc be41 	b.w	14a4 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    4822:	42ba      	cmp	r2, r7
    4824:	d002      	beq.n	482c <z_impl_k_yield+0x70>
    4826:	6812      	ldr	r2, [r2, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4828:	2a00      	cmp	r2, #0
    482a:	d1e6      	bne.n	47fa <z_impl_k_yield+0x3e>
	sys_dnode_t *const tail = list->tail;
    482c:	6a4a      	ldr	r2, [r1, #36]	; 0x24
	node->prev = tail;
    482e:	e9c3 0200 	strd	r0, r2, [r3]
	tail->next = node;
    4832:	6013      	str	r3, [r2, #0]
	list->tail = node;
    4834:	624b      	str	r3, [r1, #36]	; 0x24
}
    4836:	e7ec      	b.n	4812 <z_impl_k_yield+0x56>
    4838:	20000ba0 	.word	0x20000ba0

0000483c <z_tick_sleep>:
	 */
	LOG_DBG("thread %p for %u ticks", _current, ticks);
#endif

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    483c:	ea50 0301 	orrs.w	r3, r0, r1
{
    4840:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4844:	4605      	mov	r5, r0
    4846:	460e      	mov	r6, r1
	if (ticks == 0) {
    4848:	d103      	bne.n	4852 <z_tick_sleep+0x16>
	z_impl_k_yield();
    484a:	f7ff ffb7 	bl	47bc <z_impl_k_yield>
	if (ticks > 0) {
		return ticks;
	}
#endif

	return 0;
    484e:	2000      	movs	r0, #0
    4850:	e033      	b.n	48ba <z_tick_sleep+0x7e>
	if (Z_TICK_ABS(ticks) <= 0) {
    4852:	f06f 0401 	mvn.w	r4, #1
    4856:	f04f 33ff 	mov.w	r3, #4294967295
    485a:	1a24      	subs	r4, r4, r0
    485c:	eb63 0301 	sbc.w	r3, r3, r1
    4860:	2c01      	cmp	r4, #1
    4862:	f173 0300 	sbcs.w	r3, r3, #0
    4866:	da02      	bge.n	486e <z_tick_sleep+0x32>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    4868:	f002 f85e 	bl	6928 <sys_clock_tick_get_32>
    486c:	1944      	adds	r4, r0, r5
    486e:	f04f 0320 	mov.w	r3, #32
    4872:	f3ef 8811 	mrs	r8, BASEPRI
    4876:	f383 8812 	msr	BASEPRI_MAX, r3
    487a:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    487e:	4f10      	ldr	r7, [pc, #64]	; (48c0 <z_tick_sleep+0x84>)
    4880:	4b10      	ldr	r3, [pc, #64]	; (48c4 <z_tick_sleep+0x88>)
    4882:	68b8      	ldr	r0, [r7, #8]
    4884:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    4886:	f7ff fea5 	bl	45d4 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    488a:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    488c:	490e      	ldr	r1, [pc, #56]	; (48c8 <z_tick_sleep+0x8c>)
    488e:	462a      	mov	r2, r5
    4890:	4633      	mov	r3, r6
    4892:	3018      	adds	r0, #24
    4894:	f000 f8f0 	bl	4a78 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    4898:	68ba      	ldr	r2, [r7, #8]
    489a:	4640      	mov	r0, r8
    489c:	7b53      	ldrb	r3, [r2, #13]
    489e:	f043 0310 	orr.w	r3, r3, #16
    48a2:	7353      	strb	r3, [r2, #13]
    48a4:	f7fc fdfe 	bl	14a4 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    48a8:	f002 f83e 	bl	6928 <sys_clock_tick_get_32>
    48ac:	1a20      	subs	r0, r4, r0
    48ae:	eb63 0303 	sbc.w	r3, r3, r3
	if (ticks > 0) {
    48b2:	2801      	cmp	r0, #1
    48b4:	f173 0300 	sbcs.w	r3, r3, #0
    48b8:	dbc9      	blt.n	484e <z_tick_sleep+0x12>
}
    48ba:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    48be:	bf00      	nop
    48c0:	20000ba0 	.word	0x20000ba0
    48c4:	20000bc8 	.word	0x20000bc8
    48c8:	000067b7 	.word	0x000067b7

000048cc <z_impl_k_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    48cc:	f1b1 3fff 	cmp.w	r1, #4294967295
    48d0:	bf08      	it	eq
    48d2:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    48d6:	b508      	push	{r3, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    48d8:	d106      	bne.n	48e8 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    48da:	4b08      	ldr	r3, [pc, #32]	; (48fc <z_impl_k_sleep+0x30>)
    48dc:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    48de:	f7ff ff13 	bl	4708 <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    48e2:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    48e6:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    48e8:	f7ff ffa8 	bl	483c <z_tick_sleep>
			return ((t * to_hz + off) / from_hz);
    48ec:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    48f0:	fb80 0303 	smull	r0, r3, r0, r3
    48f4:	0bc0      	lsrs	r0, r0, #15
    48f6:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    48fa:	e7f4      	b.n	48e6 <z_impl_k_sleep+0x1a>
    48fc:	20000ba0 	.word	0x20000ba0

00004900 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    4900:	4b01      	ldr	r3, [pc, #4]	; (4908 <z_impl_z_current_get+0x8>)
    4902:	6898      	ldr	r0, [r3, #8]
    4904:	4770      	bx	lr
    4906:	bf00      	nop
    4908:	20000ba0 	.word	0x20000ba0

0000490c <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    490c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4910:	4604      	mov	r4, r0
    4912:	f04f 0320 	mov.w	r3, #32
    4916:	f3ef 8611 	mrs	r6, BASEPRI
    491a:	f383 8812 	msr	BASEPRI_MAX, r3
    491e:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    4922:	7b43      	ldrb	r3, [r0, #13]
    4924:	071a      	lsls	r2, r3, #28
    4926:	d505      	bpl.n	4934 <z_thread_abort+0x28>
	__asm__ volatile(
    4928:	f386 8811 	msr	BASEPRI, r6
    492c:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    4930:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		thread->base.thread_state &= ~_THREAD_ABORTING;
    4934:	f023 0220 	bic.w	r2, r3, #32
    4938:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    493c:	09d2      	lsrs	r2, r2, #7
    493e:	d120      	bne.n	4982 <z_thread_abort+0x76>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    4940:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    4942:	68a3      	ldr	r3, [r4, #8]
    4944:	b113      	cbz	r3, 494c <z_thread_abort+0x40>
			unpend_thread_no_timeout(thread);
    4946:	4620      	mov	r0, r4
    4948:	f001 feef 	bl	672a <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    494c:	f104 0018 	add.w	r0, r4, #24
    4950:	f001 ffaa 	bl	68a8 <z_abort_timeout>
    4954:	f04f 0800 	mov.w	r8, #0
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    4958:	f104 0758 	add.w	r7, r4, #88	; 0x58
	return list->head == list;
    495c:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    495e:	42bd      	cmp	r5, r7
    4960:	d000      	beq.n	4964 <z_thread_abort+0x58>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    4962:	b9b5      	cbnz	r5, 4992 <z_thread_abort+0x86>
		update_cache(1);
    4964:	2001      	movs	r0, #1
    4966:	f7ff fd45 	bl	43f4 <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    496a:	4b10      	ldr	r3, [pc, #64]	; (49ac <z_thread_abort+0xa0>)
    496c:	689b      	ldr	r3, [r3, #8]
    496e:	42a3      	cmp	r3, r4
    4970:	d1da      	bne.n	4928 <z_thread_abort+0x1c>
    4972:	f3ef 8305 	mrs	r3, IPSR
    4976:	2b00      	cmp	r3, #0
    4978:	d1d6      	bne.n	4928 <z_thread_abort+0x1c>
    497a:	4630      	mov	r0, r6
    497c:	f7fc fd92 	bl	14a4 <arch_swap>
	return ret;
    4980:	e7d2      	b.n	4928 <z_thread_abort+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4982:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    4986:	f043 0308 	orr.w	r3, r3, #8
    498a:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    498c:	f001 fec5 	bl	671a <sys_dlist_remove>
}
    4990:	e7d7      	b.n	4942 <z_thread_abort+0x36>
		unpend_thread_no_timeout(thread);
    4992:	4628      	mov	r0, r5
    4994:	f001 fec9 	bl	672a <unpend_thread_no_timeout>
    4998:	f105 0018 	add.w	r0, r5, #24
    499c:	f001 ff84 	bl	68a8 <z_abort_timeout>
		ready_thread(thread);
    49a0:	4628      	mov	r0, r5
    49a2:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
    49a6:	f7ff fdc1 	bl	452c <ready_thread>
    49aa:	e7d7      	b.n	495c <z_thread_abort+0x50>
    49ac:	20000ba0 	.word	0x20000ba0

000049b0 <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    49b0:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    49b2:	4806      	ldr	r0, [pc, #24]	; (49cc <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    49b4:	4a06      	ldr	r2, [pc, #24]	; (49d0 <z_data_copy+0x20>)
    49b6:	4907      	ldr	r1, [pc, #28]	; (49d4 <z_data_copy+0x24>)
    49b8:	1a12      	subs	r2, r2, r0
    49ba:	f001 fe4c 	bl	6656 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    49be:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    49c2:	4a05      	ldr	r2, [pc, #20]	; (49d8 <z_data_copy+0x28>)
    49c4:	4905      	ldr	r1, [pc, #20]	; (49dc <z_data_copy+0x2c>)
    49c6:	4806      	ldr	r0, [pc, #24]	; (49e0 <z_data_copy+0x30>)
    49c8:	f001 be45 	b.w	6656 <z_early_memcpy>
    49cc:	20000000 	.word	0x20000000
    49d0:	20000268 	.word	0x20000268
    49d4:	00007040 	.word	0x00007040
    49d8:	00000000 	.word	0x00000000
    49dc:	00007040 	.word	0x00007040
    49e0:	20000000 	.word	0x20000000

000049e4 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    49e4:	4b03      	ldr	r3, [pc, #12]	; (49f4 <elapsed+0x10>)
    49e6:	681b      	ldr	r3, [r3, #0]
    49e8:	b90b      	cbnz	r3, 49ee <elapsed+0xa>
    49ea:	f7fe bbd7 	b.w	319c <sys_clock_elapsed>
}
    49ee:	2000      	movs	r0, #0
    49f0:	4770      	bx	lr
    49f2:	bf00      	nop
    49f4:	20000bd4 	.word	0x20000bd4

000049f8 <next_timeout>:
	return list->head == list;
    49f8:	4b10      	ldr	r3, [pc, #64]	; (4a3c <next_timeout+0x44>)

static int32_t next_timeout(void)
{
    49fa:	b510      	push	{r4, lr}
    49fc:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    49fe:	429c      	cmp	r4, r3
    4a00:	bf08      	it	eq
    4a02:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    4a04:	f7ff ffee 	bl	49e4 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
    4a08:	b1a4      	cbz	r4, 4a34 <next_timeout+0x3c>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    4a0a:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    4a0e:	1a1b      	subs	r3, r3, r0
    4a10:	eb62 70e0 	sbc.w	r0, r2, r0, asr #31
	if ((to == NULL) ||
    4a14:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    4a18:	f170 0200 	sbcs.w	r2, r0, #0
    4a1c:	da0a      	bge.n	4a34 <next_timeout+0x3c>
		ret = MAX_WAIT;
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
    4a1e:	2800      	cmp	r0, #0
    4a20:	bfac      	ite	ge
    4a22:	4618      	movge	r0, r3
    4a24:	2000      	movlt	r0, #0
	}

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    4a26:	4b06      	ldr	r3, [pc, #24]	; (4a40 <next_timeout+0x48>)
    4a28:	691b      	ldr	r3, [r3, #16]
    4a2a:	b113      	cbz	r3, 4a32 <next_timeout+0x3a>
    4a2c:	4298      	cmp	r0, r3
    4a2e:	bfa8      	it	ge
    4a30:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    4a32:	bd10      	pop	{r4, pc}
		ret = MAX_WAIT;
    4a34:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    4a38:	e7f5      	b.n	4a26 <next_timeout+0x2e>
    4a3a:	bf00      	nop
    4a3c:	2000019c 	.word	0x2000019c
    4a40:	20000ba0 	.word	0x20000ba0

00004a44 <remove_timeout>:
{
    4a44:	b530      	push	{r4, r5, lr}
	return (node == list->tail) ? NULL : node->next;
    4a46:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4a48:	b168      	cbz	r0, 4a66 <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    4a4a:	4a0a      	ldr	r2, [pc, #40]	; (4a74 <remove_timeout+0x30>)
    4a4c:	6852      	ldr	r2, [r2, #4]
    4a4e:	4290      	cmp	r0, r2
    4a50:	d009      	beq.n	4a66 <remove_timeout+0x22>
	if (next(t) != NULL) {
    4a52:	b143      	cbz	r3, 4a66 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    4a54:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    4a58:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    4a5c:	1912      	adds	r2, r2, r4
    4a5e:	eb41 0105 	adc.w	r1, r1, r5
    4a62:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @param node the node to remove
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    4a66:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    4a68:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    4a6a:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    4a6c:	2300      	movs	r3, #0
	node->prev = NULL;
    4a6e:	e9c0 3300 	strd	r3, r3, [r0]
}
    4a72:	bd30      	pop	{r4, r5, pc}
    4a74:	2000019c 	.word	0x2000019c

00004a78 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4a78:	f1b3 3fff 	cmp.w	r3, #4294967295
    4a7c:	bf08      	it	eq
    4a7e:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    4a82:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4a84:	4604      	mov	r4, r0
    4a86:	461f      	mov	r7, r3
    4a88:	4615      	mov	r5, r2
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4a8a:	d067      	beq.n	4b5c <z_add_timeout+0xe4>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    4a8c:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    4a8e:	f04f 0320 	mov.w	r3, #32
    4a92:	f3ef 8611 	mrs	r6, BASEPRI
    4a96:	f383 8812 	msr	BASEPRI_MAX, r3
    4a9a:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    4a9e:	f06f 0201 	mvn.w	r2, #1
    4aa2:	f04f 3cff 	mov.w	ip, #4294967295
    4aa6:	1b53      	subs	r3, r2, r5
    4aa8:	eb6c 0307 	sbc.w	r3, ip, r7
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    4aac:	2b00      	cmp	r3, #0
    4aae:	db1b      	blt.n	4ae8 <z_add_timeout+0x70>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    4ab0:	4b2b      	ldr	r3, [pc, #172]	; (4b60 <z_add_timeout+0xe8>)
    4ab2:	e9d3 1300 	ldrd	r1, r3, [r3]
    4ab6:	1a52      	subs	r2, r2, r1
    4ab8:	eb6c 0303 	sbc.w	r3, ip, r3
    4abc:	1b55      	subs	r5, r2, r5

			to->dticks = MAX(1, ticks);
    4abe:	eb63 0307 	sbc.w	r3, r3, r7
    4ac2:	2d01      	cmp	r5, #1
    4ac4:	f173 0200 	sbcs.w	r2, r3, #0
    4ac8:	bfbc      	itt	lt
    4aca:	2501      	movlt	r5, #1
    4acc:	2300      	movlt	r3, #0
    4ace:	e9c0 5304 	strd	r5, r3, [r0, #16]
	return list->head == list;
    4ad2:	4824      	ldr	r0, [pc, #144]	; (4b64 <z_add_timeout+0xec>)
	sys_dnode_t *const tail = list->tail;
    4ad4:	e9d0 3c00 	ldrd	r3, ip, [r0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4ad8:	4283      	cmp	r3, r0
    4ada:	d118      	bne.n	4b0e <z_add_timeout+0x96>
	node->prev = tail;
    4adc:	e9c4 0c00 	strd	r0, ip, [r4]
	tail->next = node;
    4ae0:	f8cc 4000 	str.w	r4, [ip]
	list->tail = node;
    4ae4:	6044      	str	r4, [r0, #4]
}
    4ae6:	e026      	b.n	4b36 <z_add_timeout+0xbe>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    4ae8:	f7ff ff7c 	bl	49e4 <elapsed>
    4aec:	3501      	adds	r5, #1
    4aee:	f147 0700 	adc.w	r7, r7, #0
    4af2:	182d      	adds	r5, r5, r0
    4af4:	eb47 77e0 	adc.w	r7, r7, r0, asr #31
    4af8:	e9c4 5704 	strd	r5, r7, [r4, #16]
    4afc:	e7e9      	b.n	4ad2 <z_add_timeout+0x5a>
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
				sys_dlist_insert(&t->node, &to->node);
				break;
			}
			to->dticks -= t->dticks;
    4afe:	1a52      	subs	r2, r2, r1
    4b00:	eb65 0507 	sbc.w	r5, r5, r7
	return (node == list->tail) ? NULL : node->next;
    4b04:	459c      	cmp	ip, r3
    4b06:	e9c4 2504 	strd	r2, r5, [r4, #16]
    4b0a:	d0e7      	beq.n	4adc <z_add_timeout+0x64>
    4b0c:	681b      	ldr	r3, [r3, #0]
		for (t = first(); t != NULL; t = next(t)) {
    4b0e:	2b00      	cmp	r3, #0
    4b10:	d0e4      	beq.n	4adc <z_add_timeout+0x64>
			if (t->dticks > to->dticks) {
    4b12:	e9d3 1704 	ldrd	r1, r7, [r3, #16]
    4b16:	e9d4 2504 	ldrd	r2, r5, [r4, #16]
    4b1a:	428a      	cmp	r2, r1
    4b1c:	eb75 0e07 	sbcs.w	lr, r5, r7
    4b20:	daed      	bge.n	4afe <z_add_timeout+0x86>
				t->dticks -= to->dticks;
    4b22:	1a8a      	subs	r2, r1, r2
    4b24:	eb67 0505 	sbc.w	r5, r7, r5
    4b28:	e9c3 2504 	strd	r2, r5, [r3, #16]
	sys_dnode_t *const prev = successor->prev;
    4b2c:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    4b2e:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    4b32:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    4b34:	605c      	str	r4, [r3, #4]
	return list->head == list;
    4b36:	6803      	ldr	r3, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4b38:	4283      	cmp	r3, r0
    4b3a:	d00b      	beq.n	4b54 <z_add_timeout+0xdc>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    4b3c:	429c      	cmp	r4, r3
    4b3e:	d109      	bne.n	4b54 <z_add_timeout+0xdc>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    4b40:	f7ff ff5a 	bl	49f8 <next_timeout>

			if (next_time == 0 ||
    4b44:	b118      	cbz	r0, 4b4e <z_add_timeout+0xd6>
			    _current_cpu->slice_ticks != next_time) {
    4b46:	4b08      	ldr	r3, [pc, #32]	; (4b68 <z_add_timeout+0xf0>)
			if (next_time == 0 ||
    4b48:	691b      	ldr	r3, [r3, #16]
    4b4a:	4283      	cmp	r3, r0
    4b4c:	d002      	beq.n	4b54 <z_add_timeout+0xdc>
				sys_clock_set_timeout(next_time, false);
    4b4e:	2100      	movs	r1, #0
    4b50:	f7fe faf4 	bl	313c <sys_clock_set_timeout>
	__asm__ volatile(
    4b54:	f386 8811 	msr	BASEPRI, r6
    4b58:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    4b5c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    4b5e:	bf00      	nop
    4b60:	20000540 	.word	0x20000540
    4b64:	2000019c 	.word	0x2000019c
    4b68:	20000ba0 	.word	0x20000ba0

00004b6c <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    4b6c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4b70:	4605      	mov	r5, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    4b72:	f7ff fc99 	bl	44a8 <z_time_slice>
	__asm__ volatile(
    4b76:	f04f 0320 	mov.w	r3, #32
    4b7a:	f3ef 8411 	mrs	r4, BASEPRI
    4b7e:	f383 8812 	msr	BASEPRI_MAX, r3
    4b82:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    4b86:	4e24      	ldr	r6, [pc, #144]	; (4c18 <sys_clock_announce+0xac>)
	return list->head == list;
    4b88:	f8df 8090 	ldr.w	r8, [pc, #144]	; 4c1c <sys_clock_announce+0xb0>
    4b8c:	6035      	str	r5, [r6, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    4b8e:	4d24      	ldr	r5, [pc, #144]	; (4c20 <sys_clock_announce+0xb4>)
    4b90:	f8d8 0000 	ldr.w	r0, [r8]
	while (first() != NULL && first()->dticks <= announce_remaining) {
    4b94:	6832      	ldr	r2, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4b96:	4540      	cmp	r0, r8
    4b98:	ea4f 77e2 	mov.w	r7, r2, asr #31
		curr_tick += dt;
    4b9c:	e9d5 1e00 	ldrd	r1, lr, [r5]
    4ba0:	d00b      	beq.n	4bba <sys_clock_announce+0x4e>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    4ba2:	b150      	cbz	r0, 4bba <sys_clock_announce+0x4e>
    4ba4:	e9d0 3c04 	ldrd	r3, ip, [r0, #16]
    4ba8:	429a      	cmp	r2, r3
    4baa:	eb77 090c 	sbcs.w	r9, r7, ip
    4bae:	da16      	bge.n	4bde <sys_clock_announce+0x72>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    4bb0:	1a9b      	subs	r3, r3, r2
    4bb2:	eb6c 0c07 	sbc.w	ip, ip, r7
    4bb6:	e9c0 3c04 	strd	r3, ip, [r0, #16]
	}

	curr_tick += announce_remaining;
    4bba:	1852      	adds	r2, r2, r1
    4bbc:	eb4e 0707 	adc.w	r7, lr, r7
    4bc0:	e9c5 2700 	strd	r2, r7, [r5]
	announce_remaining = 0;
    4bc4:	2500      	movs	r5, #0
    4bc6:	6035      	str	r5, [r6, #0]

	sys_clock_set_timeout(next_timeout(), false);
    4bc8:	f7ff ff16 	bl	49f8 <next_timeout>
    4bcc:	4629      	mov	r1, r5
    4bce:	f7fe fab5 	bl	313c <sys_clock_set_timeout>
	__asm__ volatile(
    4bd2:	f384 8811 	msr	BASEPRI, r4
    4bd6:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    4bda:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    4bde:	1859      	adds	r1, r3, r1
    4be0:	eb4e 77e3 	adc.w	r7, lr, r3, asr #31
		announce_remaining -= dt;
    4be4:	1ad3      	subs	r3, r2, r3
    4be6:	6033      	str	r3, [r6, #0]
		t->dticks = 0;
    4be8:	2200      	movs	r2, #0
    4bea:	2300      	movs	r3, #0
    4bec:	e9c0 2304 	strd	r2, r3, [r0, #16]
		curr_tick += dt;
    4bf0:	e9c5 1700 	strd	r1, r7, [r5]
		remove_timeout(t);
    4bf4:	f7ff ff26 	bl	4a44 <remove_timeout>
    4bf8:	f384 8811 	msr	BASEPRI, r4
    4bfc:	f3bf 8f6f 	isb	sy
		t->fn(t);
    4c00:	6883      	ldr	r3, [r0, #8]
    4c02:	4798      	blx	r3
	__asm__ volatile(
    4c04:	f04f 0320 	mov.w	r3, #32
    4c08:	f3ef 8411 	mrs	r4, BASEPRI
    4c0c:	f383 8812 	msr	BASEPRI_MAX, r3
    4c10:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    4c14:	e7bc      	b.n	4b90 <sys_clock_announce+0x24>
    4c16:	bf00      	nop
    4c18:	20000bd4 	.word	0x20000bd4
    4c1c:	2000019c 	.word	0x2000019c
    4c20:	20000540 	.word	0x20000540

00004c24 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    4c24:	b510      	push	{r4, lr}
    4c26:	f04f 0320 	mov.w	r3, #32
    4c2a:	f3ef 8411 	mrs	r4, BASEPRI
    4c2e:	f383 8812 	msr	BASEPRI_MAX, r3
    4c32:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + sys_clock_elapsed();
    4c36:	f7fe fab1 	bl	319c <sys_clock_elapsed>
    4c3a:	4a05      	ldr	r2, [pc, #20]	; (4c50 <sys_clock_tick_get+0x2c>)
    4c3c:	e9d2 3100 	ldrd	r3, r1, [r2]
    4c40:	18c0      	adds	r0, r0, r3
    4c42:	f141 0100 	adc.w	r1, r1, #0
	__asm__ volatile(
    4c46:	f384 8811 	msr	BASEPRI, r4
    4c4a:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    4c4e:	bd10      	pop	{r4, pc}
    4c50:	20000540 	.word	0x20000540

00004c54 <z_timer_expiration_handler>:
 * @brief Handle expiration of a kernel timer object.
 *
 * @param t  Timeout used by the timer.
 */
void z_timer_expiration_handler(struct _timeout *t)
{
    4c54:	b570      	push	{r4, r5, r6, lr}
    4c56:	4604      	mov	r4, r0
	__asm__ volatile(
    4c58:	f04f 0320 	mov.w	r3, #32
    4c5c:	f3ef 8511 	mrs	r5, BASEPRI
    4c60:	f383 8812 	msr	BASEPRI_MAX, r3
    4c64:	f3bf 8f6f 	isb	sy

	/*
	 * if the timer is periodic, start it again; don't add _TICK_ALIGN
	 * since we're already aligned to a tick boundary
	 */
	if (!K_TIMEOUT_EQ(timer->period, K_NO_WAIT) &&
    4c68:	e9d0 320a 	ldrd	r3, r2, [r0, #40]	; 0x28
    4c6c:	3301      	adds	r3, #1
    4c6e:	f142 0200 	adc.w	r2, r2, #0
    4c72:	2b02      	cmp	r3, #2
    4c74:	f172 0300 	sbcs.w	r3, r2, #0
    4c78:	d304      	bcc.n	4c84 <z_timer_expiration_handler+0x30>
	    !K_TIMEOUT_EQ(timer->period, K_FOREVER)) {
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4c7a:	e9d0 230a 	ldrd	r2, r3, [r0, #40]	; 0x28
    4c7e:	4917      	ldr	r1, [pc, #92]	; (4cdc <z_timer_expiration_handler+0x88>)
    4c80:	f7ff fefa 	bl	4a78 <z_add_timeout>
			     timer->period);
	}

	/* update timer's status */
	timer->status += 1U;
    4c84:	6b23      	ldr	r3, [r4, #48]	; 0x30
    4c86:	3301      	adds	r3, #1
    4c88:	6323      	str	r3, [r4, #48]	; 0x30

	/* invoke timer expiry function */
	if (timer->expiry_fn != NULL) {
    4c8a:	6a23      	ldr	r3, [r4, #32]
    4c8c:	b173      	cbz	r3, 4cac <z_timer_expiration_handler+0x58>
	__asm__ volatile(
    4c8e:	f385 8811 	msr	BASEPRI, r5
    4c92:	f3bf 8f6f 	isb	sy
		/* Unlock for user handler. */
		k_spin_unlock(&lock, key);
		timer->expiry_fn(timer);
    4c96:	4620      	mov	r0, r4
    4c98:	6a23      	ldr	r3, [r4, #32]
    4c9a:	4798      	blx	r3
	__asm__ volatile(
    4c9c:	f04f 0320 	mov.w	r3, #32
    4ca0:	f3ef 8511 	mrs	r5, BASEPRI
    4ca4:	f383 8812 	msr	BASEPRI_MAX, r3
    4ca8:	f3bf 8f6f 	isb	sy
	return list->head == list;
    4cac:	f854 6f18 	ldr.w	r6, [r4, #24]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4cb0:	42a6      	cmp	r6, r4
    4cb2:	d000      	beq.n	4cb6 <z_timer_expiration_handler+0x62>
		return;
	}

	thread = z_waitq_head(&timer->wait_q);

	if (thread == NULL) {
    4cb4:	b926      	cbnz	r6, 4cc0 <z_timer_expiration_handler+0x6c>
	__asm__ volatile(
    4cb6:	f385 8811 	msr	BASEPRI, r5
    4cba:	f3bf 8f6f 	isb	sy
	arch_thread_return_value_set(thread, 0);

	k_spin_unlock(&lock, key);

	z_ready_thread(thread);
}
    4cbe:	bd70      	pop	{r4, r5, r6, pc}
	z_unpend_thread_no_timeout(thread);
    4cc0:	4630      	mov	r0, r6
    4cc2:	f001 fd3c 	bl	673e <z_unpend_thread_no_timeout>
    4cc6:	2300      	movs	r3, #0
    4cc8:	67b3      	str	r3, [r6, #120]	; 0x78
    4cca:	f385 8811 	msr	BASEPRI, r5
    4cce:	f3bf 8f6f 	isb	sy
	z_ready_thread(thread);
    4cd2:	4630      	mov	r0, r6
}
    4cd4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	z_ready_thread(thread);
    4cd8:	f001 bd5d 	b.w	6796 <z_ready_thread>
    4cdc:	00004c55 	.word	0x00004c55

00004ce0 <z_impl_k_timer_start>:
}


void z_impl_k_timer_start(struct k_timer *timer, k_timeout_t duration,
			  k_timeout_t period)
{
    4ce0:	4611      	mov	r1, r2
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, start, timer);

	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    4ce2:	f1b3 3fff 	cmp.w	r3, #4294967295
    4ce6:	bf08      	it	eq
    4ce8:	f1b1 3fff 	cmpeq.w	r1, #4294967295
{
    4cec:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    4cf0:	4606      	mov	r6, r0
    4cf2:	e9dd 2008 	ldrd	r2, r0, [sp, #32]
    4cf6:	461c      	mov	r4, r3
    4cf8:	4689      	mov	r9, r1
    4cfa:	4698      	mov	r8, r3
	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    4cfc:	d03e      	beq.n	4d7c <z_impl_k_timer_start+0x9c>
	 * for backwards compatibility.  This is unfortunate
	 * (i.e. k_timer_start() doesn't treat its initial sleep
	 * argument the same way k_sleep() does), but historical.  The
	 * timer_api test relies on this behavior.
	 */
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    4cfe:	f1b0 3fff 	cmp.w	r0, #4294967295
    4d02:	bf08      	it	eq
    4d04:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    4d08:	4615      	mov	r5, r2
    4d0a:	4607      	mov	r7, r0
    4d0c:	d014      	beq.n	4d38 <z_impl_k_timer_start+0x58>
    4d0e:	ea50 0302 	orrs.w	r3, r0, r2
    4d12:	d011      	beq.n	4d38 <z_impl_k_timer_start+0x58>
	    Z_TICK_ABS(period.ticks) < 0) {
    4d14:	f06f 0301 	mvn.w	r3, #1
    4d18:	1a9b      	subs	r3, r3, r2
    4d1a:	f04f 33ff 	mov.w	r3, #4294967295
    4d1e:	eb63 0300 	sbc.w	r3, r3, r0
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    4d22:	2b00      	cmp	r3, #0
    4d24:	da08      	bge.n	4d38 <z_impl_k_timer_start+0x58>
		period.ticks = MAX(period.ticks - 1, 1);
    4d26:	2a02      	cmp	r2, #2
    4d28:	f170 0300 	sbcs.w	r3, r0, #0
    4d2c:	bfbc      	itt	lt
    4d2e:	2502      	movlt	r5, #2
    4d30:	2700      	movlt	r7, #0
    4d32:	3d01      	subs	r5, #1
    4d34:	f147 37ff 	adc.w	r7, r7, #4294967295
	}
	if (Z_TICK_ABS(duration.ticks) < 0) {
    4d38:	f06f 0301 	mvn.w	r3, #1
    4d3c:	1a5b      	subs	r3, r3, r1
    4d3e:	f04f 33ff 	mov.w	r3, #4294967295
    4d42:	eb63 0304 	sbc.w	r3, r3, r4
    4d46:	2b00      	cmp	r3, #0
    4d48:	da09      	bge.n	4d5e <z_impl_k_timer_start+0x7e>
		duration.ticks = MAX(duration.ticks - 1, 0);
    4d4a:	2901      	cmp	r1, #1
    4d4c:	f174 0300 	sbcs.w	r3, r4, #0
    4d50:	bfbc      	itt	lt
    4d52:	2101      	movlt	r1, #1
    4d54:	2400      	movlt	r4, #0
    4d56:	f111 39ff 	adds.w	r9, r1, #4294967295
    4d5a:	f144 38ff 	adc.w	r8, r4, #4294967295
	}

	(void)z_abort_timeout(&timer->timeout);
    4d5e:	4630      	mov	r0, r6
    4d60:	f001 fda2 	bl	68a8 <z_abort_timeout>
	timer->period = period;
	timer->status = 0U;
    4d64:	2300      	movs	r3, #0

	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4d66:	464a      	mov	r2, r9
	timer->status = 0U;
    4d68:	6333      	str	r3, [r6, #48]	; 0x30
	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4d6a:	4630      	mov	r0, r6
    4d6c:	4643      	mov	r3, r8
	timer->period = period;
    4d6e:	e9c6 570a 	strd	r5, r7, [r6, #40]	; 0x28
		     duration);
}
    4d72:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4d76:	4902      	ldr	r1, [pc, #8]	; (4d80 <z_impl_k_timer_start+0xa0>)
    4d78:	f7ff be7e 	b.w	4a78 <z_add_timeout>
}
    4d7c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    4d80:	00004c55 	.word	0x00004c55

00004d84 <nrf_cc3xx_platform_init_no_rng>:
    4d84:	b510      	push	{r4, lr}
    4d86:	4c0a      	ldr	r4, [pc, #40]	; (4db0 <nrf_cc3xx_platform_init_no_rng+0x2c>)
    4d88:	6823      	ldr	r3, [r4, #0]
    4d8a:	b11b      	cbz	r3, 4d94 <nrf_cc3xx_platform_init_no_rng+0x10>
    4d8c:	2301      	movs	r3, #1
    4d8e:	2000      	movs	r0, #0
    4d90:	6023      	str	r3, [r4, #0]
    4d92:	bd10      	pop	{r4, pc}
    4d94:	f000 f8dc 	bl	4f50 <CC_LibInitNoRng>
    4d98:	2800      	cmp	r0, #0
    4d9a:	d0f7      	beq.n	4d8c <nrf_cc3xx_platform_init_no_rng+0x8>
    4d9c:	3801      	subs	r0, #1
    4d9e:	2807      	cmp	r0, #7
    4da0:	d803      	bhi.n	4daa <nrf_cc3xx_platform_init_no_rng+0x26>
    4da2:	4b04      	ldr	r3, [pc, #16]	; (4db4 <nrf_cc3xx_platform_init_no_rng+0x30>)
    4da4:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    4da8:	bd10      	pop	{r4, pc}
    4daa:	4803      	ldr	r0, [pc, #12]	; (4db8 <nrf_cc3xx_platform_init_no_rng+0x34>)
    4dac:	bd10      	pop	{r4, pc}
    4dae:	bf00      	nop
    4db0:	20000bd8 	.word	0x20000bd8
    4db4:	00006ec8 	.word	0x00006ec8
    4db8:	ffff8ffe 	.word	0xffff8ffe

00004dbc <nrf_cc3xx_platform_abort>:
    4dbc:	f3bf 8f4f 	dsb	sy
    4dc0:	4905      	ldr	r1, [pc, #20]	; (4dd8 <nrf_cc3xx_platform_abort+0x1c>)
    4dc2:	4b06      	ldr	r3, [pc, #24]	; (4ddc <nrf_cc3xx_platform_abort+0x20>)
    4dc4:	68ca      	ldr	r2, [r1, #12]
    4dc6:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    4dca:	4313      	orrs	r3, r2
    4dcc:	60cb      	str	r3, [r1, #12]
    4dce:	f3bf 8f4f 	dsb	sy
    4dd2:	bf00      	nop
    4dd4:	e7fd      	b.n	4dd2 <nrf_cc3xx_platform_abort+0x16>
    4dd6:	bf00      	nop
    4dd8:	e000ed00 	.word	0xe000ed00
    4ddc:	05fa0004 	.word	0x05fa0004

00004de0 <CC_PalAbort>:
    4de0:	b430      	push	{r4, r5}
    4de2:	f04f 32fe 	mov.w	r2, #4278124286	; 0xfefefefe
    4de6:	2500      	movs	r5, #0
    4de8:	4b0b      	ldr	r3, [pc, #44]	; (4e18 <CC_PalAbort+0x38>)
    4dea:	4c0c      	ldr	r4, [pc, #48]	; (4e1c <CC_PalAbort+0x3c>)
    4dec:	490c      	ldr	r1, [pc, #48]	; (4e20 <CC_PalAbort+0x40>)
    4dee:	6849      	ldr	r1, [r1, #4]
    4df0:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    4df4:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    4df8:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    4dfc:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    4e00:	f8c3 2410 	str.w	r2, [r3, #1040]	; 0x410
    4e04:	f8c3 2414 	str.w	r2, [r3, #1044]	; 0x414
    4e08:	f8c3 2418 	str.w	r2, [r3, #1048]	; 0x418
    4e0c:	f8c3 241c 	str.w	r2, [r3, #1052]	; 0x41c
    4e10:	f8c4 5500 	str.w	r5, [r4, #1280]	; 0x500
    4e14:	bc30      	pop	{r4, r5}
    4e16:	4708      	bx	r1
    4e18:	50845000 	.word	0x50845000
    4e1c:	50844000 	.word	0x50844000
    4e20:	200001a4 	.word	0x200001a4

00004e24 <nrf_cc3xx_platform_set_abort>:
    4e24:	4b02      	ldr	r3, [pc, #8]	; (4e30 <nrf_cc3xx_platform_set_abort+0xc>)
    4e26:	e9d0 1200 	ldrd	r1, r2, [r0]
    4e2a:	e9c3 1200 	strd	r1, r2, [r3]
    4e2e:	4770      	bx	lr
    4e30:	200001a4 	.word	0x200001a4

00004e34 <mutex_free>:
    4e34:	b510      	push	{r4, lr}
    4e36:	4604      	mov	r4, r0
    4e38:	b130      	cbz	r0, 4e48 <mutex_free+0x14>
    4e3a:	6863      	ldr	r3, [r4, #4]
    4e3c:	06db      	lsls	r3, r3, #27
    4e3e:	d502      	bpl.n	4e46 <mutex_free+0x12>
    4e40:	2300      	movs	r3, #0
    4e42:	6023      	str	r3, [r4, #0]
    4e44:	6063      	str	r3, [r4, #4]
    4e46:	bd10      	pop	{r4, pc}
    4e48:	4b02      	ldr	r3, [pc, #8]	; (4e54 <mutex_free+0x20>)
    4e4a:	4803      	ldr	r0, [pc, #12]	; (4e58 <mutex_free+0x24>)
    4e4c:	685b      	ldr	r3, [r3, #4]
    4e4e:	4798      	blx	r3
    4e50:	e7f3      	b.n	4e3a <mutex_free+0x6>
    4e52:	bf00      	nop
    4e54:	200001a4 	.word	0x200001a4
    4e58:	00006ee8 	.word	0x00006ee8

00004e5c <mutex_lock>:
    4e5c:	b1b0      	cbz	r0, 4e8c <mutex_lock+0x30>
    4e5e:	6843      	ldr	r3, [r0, #4]
    4e60:	b193      	cbz	r3, 4e88 <mutex_lock+0x2c>
    4e62:	06db      	lsls	r3, r3, #27
    4e64:	d50e      	bpl.n	4e84 <mutex_lock+0x28>
    4e66:	2301      	movs	r3, #1
    4e68:	e850 2f00 	ldrex	r2, [r0]
    4e6c:	4619      	mov	r1, r3
    4e6e:	e840 1c00 	strex	ip, r1, [r0]
    4e72:	f09c 0f00 	teq	ip, #0
    4e76:	d1f7      	bne.n	4e68 <mutex_lock+0xc>
    4e78:	2a01      	cmp	r2, #1
    4e7a:	d0f5      	beq.n	4e68 <mutex_lock+0xc>
    4e7c:	f3bf 8f5f 	dmb	sy
    4e80:	2000      	movs	r0, #0
    4e82:	4770      	bx	lr
    4e84:	4803      	ldr	r0, [pc, #12]	; (4e94 <mutex_lock+0x38>)
    4e86:	4770      	bx	lr
    4e88:	4803      	ldr	r0, [pc, #12]	; (4e98 <mutex_lock+0x3c>)
    4e8a:	4770      	bx	lr
    4e8c:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    4e90:	4770      	bx	lr
    4e92:	bf00      	nop
    4e94:	ffff8fe9 	.word	0xffff8fe9
    4e98:	ffff8fea 	.word	0xffff8fea

00004e9c <mutex_unlock>:
    4e9c:	4603      	mov	r3, r0
    4e9e:	b168      	cbz	r0, 4ebc <mutex_unlock+0x20>
    4ea0:	6842      	ldr	r2, [r0, #4]
    4ea2:	b13a      	cbz	r2, 4eb4 <mutex_unlock+0x18>
    4ea4:	06d2      	lsls	r2, r2, #27
    4ea6:	d507      	bpl.n	4eb8 <mutex_unlock+0x1c>
    4ea8:	f3bf 8f5f 	dmb	sy
    4eac:	2200      	movs	r2, #0
    4eae:	4610      	mov	r0, r2
    4eb0:	601a      	str	r2, [r3, #0]
    4eb2:	4770      	bx	lr
    4eb4:	4803      	ldr	r0, [pc, #12]	; (4ec4 <mutex_unlock+0x28>)
    4eb6:	4770      	bx	lr
    4eb8:	4803      	ldr	r0, [pc, #12]	; (4ec8 <mutex_unlock+0x2c>)
    4eba:	4770      	bx	lr
    4ebc:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    4ec0:	4770      	bx	lr
    4ec2:	bf00      	nop
    4ec4:	ffff8fea 	.word	0xffff8fea
    4ec8:	ffff8fe9 	.word	0xffff8fe9

00004ecc <mutex_init>:
    4ecc:	b510      	push	{r4, lr}
    4ece:	4604      	mov	r4, r0
    4ed0:	b120      	cbz	r0, 4edc <mutex_init+0x10>
    4ed2:	2200      	movs	r2, #0
    4ed4:	2311      	movs	r3, #17
    4ed6:	6022      	str	r2, [r4, #0]
    4ed8:	6063      	str	r3, [r4, #4]
    4eda:	bd10      	pop	{r4, pc}
    4edc:	4801      	ldr	r0, [pc, #4]	; (4ee4 <mutex_init+0x18>)
    4ede:	f7ff ff7f 	bl	4de0 <CC_PalAbort>
    4ee2:	e7f6      	b.n	4ed2 <mutex_init+0x6>
    4ee4:	00006f10 	.word	0x00006f10

00004ee8 <nrf_cc3xx_platform_set_mutexes>:
    4ee8:	b570      	push	{r4, r5, r6, lr}
    4eea:	4c16      	ldr	r4, [pc, #88]	; (4f44 <nrf_cc3xx_platform_set_mutexes+0x5c>)
    4eec:	f8d0 c004 	ldr.w	ip, [r0, #4]
    4ef0:	6806      	ldr	r6, [r0, #0]
    4ef2:	f8c4 c004 	str.w	ip, [r4, #4]
    4ef6:	f8d0 c008 	ldr.w	ip, [r0, #8]
    4efa:	68c0      	ldr	r0, [r0, #12]
    4efc:	f8c4 c008 	str.w	ip, [r4, #8]
    4f00:	60e0      	str	r0, [r4, #12]
    4f02:	6026      	str	r6, [r4, #0]
    4f04:	6808      	ldr	r0, [r1, #0]
    4f06:	4b10      	ldr	r3, [pc, #64]	; (4f48 <nrf_cc3xx_platform_set_mutexes+0x60>)
    4f08:	4d10      	ldr	r5, [pc, #64]	; (4f4c <nrf_cc3xx_platform_set_mutexes+0x64>)
    4f0a:	6018      	str	r0, [r3, #0]
    4f0c:	6848      	ldr	r0, [r1, #4]
    4f0e:	f8d5 2118 	ldr.w	r2, [r5, #280]	; 0x118
    4f12:	6058      	str	r0, [r3, #4]
    4f14:	6888      	ldr	r0, [r1, #8]
    4f16:	6098      	str	r0, [r3, #8]
    4f18:	68c8      	ldr	r0, [r1, #12]
    4f1a:	6909      	ldr	r1, [r1, #16]
    4f1c:	60d8      	str	r0, [r3, #12]
    4f1e:	6119      	str	r1, [r3, #16]
    4f20:	06d3      	lsls	r3, r2, #27
    4f22:	d50d      	bpl.n	4f40 <nrf_cc3xx_platform_set_mutexes+0x58>
    4f24:	2300      	movs	r3, #0
    4f26:	f505 708a 	add.w	r0, r5, #276	; 0x114
    4f2a:	e9c5 3345 	strd	r3, r3, [r5, #276]	; 0x114
    4f2e:	e9c5 336e 	strd	r3, r3, [r5, #440]	; 0x1b8
    4f32:	47b0      	blx	r6
    4f34:	6823      	ldr	r3, [r4, #0]
    4f36:	f505 70dc 	add.w	r0, r5, #440	; 0x1b8
    4f3a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    4f3e:	4718      	bx	r3
    4f40:	bd70      	pop	{r4, r5, r6, pc}
    4f42:	bf00      	nop
    4f44:	200001b4 	.word	0x200001b4
    4f48:	200001c4 	.word	0x200001c4
    4f4c:	20000bf0 	.word	0x20000bf0

00004f50 <CC_LibInitNoRng>:
    4f50:	b508      	push	{r3, lr}
    4f52:	f000 f811 	bl	4f78 <CC_HalInit>
    4f56:	b930      	cbnz	r0, 4f66 <CC_LibInitNoRng+0x16>
    4f58:	f000 f810 	bl	4f7c <CC_PalInit>
    4f5c:	b938      	cbnz	r0, 4f6e <CC_LibInitNoRng+0x1e>
    4f5e:	4a05      	ldr	r2, [pc, #20]	; (4f74 <CC_LibInitNoRng+0x24>)
    4f60:	f8c2 0a0c 	str.w	r0, [r2, #2572]	; 0xa0c
    4f64:	bd08      	pop	{r3, pc}
    4f66:	f000 f837 	bl	4fd8 <CC_PalTerminate>
    4f6a:	2003      	movs	r0, #3
    4f6c:	bd08      	pop	{r3, pc}
    4f6e:	2004      	movs	r0, #4
    4f70:	bd08      	pop	{r3, pc}
    4f72:	bf00      	nop
    4f74:	50845000 	.word	0x50845000

00004f78 <CC_HalInit>:
    4f78:	2000      	movs	r0, #0
    4f7a:	4770      	bx	lr

00004f7c <CC_PalInit>:
    4f7c:	b510      	push	{r4, lr}
    4f7e:	4811      	ldr	r0, [pc, #68]	; (4fc4 <CC_PalInit+0x48>)
    4f80:	f000 f848 	bl	5014 <CC_PalMutexCreate>
    4f84:	b100      	cbz	r0, 4f88 <CC_PalInit+0xc>
    4f86:	bd10      	pop	{r4, pc}
    4f88:	480f      	ldr	r0, [pc, #60]	; (4fc8 <CC_PalInit+0x4c>)
    4f8a:	f000 f843 	bl	5014 <CC_PalMutexCreate>
    4f8e:	2800      	cmp	r0, #0
    4f90:	d1f9      	bne.n	4f86 <CC_PalInit+0xa>
    4f92:	4c0e      	ldr	r4, [pc, #56]	; (4fcc <CC_PalInit+0x50>)
    4f94:	4620      	mov	r0, r4
    4f96:	f000 f83d 	bl	5014 <CC_PalMutexCreate>
    4f9a:	2800      	cmp	r0, #0
    4f9c:	d1f3      	bne.n	4f86 <CC_PalInit+0xa>
    4f9e:	4b0c      	ldr	r3, [pc, #48]	; (4fd0 <CC_PalInit+0x54>)
    4fa0:	480c      	ldr	r0, [pc, #48]	; (4fd4 <CC_PalInit+0x58>)
    4fa2:	601c      	str	r4, [r3, #0]
    4fa4:	f000 f836 	bl	5014 <CC_PalMutexCreate>
    4fa8:	4601      	mov	r1, r0
    4faa:	2800      	cmp	r0, #0
    4fac:	d1eb      	bne.n	4f86 <CC_PalInit+0xa>
    4fae:	f000 f82d 	bl	500c <CC_PalDmaInit>
    4fb2:	4604      	mov	r4, r0
    4fb4:	b108      	cbz	r0, 4fba <CC_PalInit+0x3e>
    4fb6:	4620      	mov	r0, r4
    4fb8:	bd10      	pop	{r4, pc}
    4fba:	f000 f83f 	bl	503c <CC_PalPowerSaveModeInit>
    4fbe:	4620      	mov	r0, r4
    4fc0:	e7fa      	b.n	4fb8 <CC_PalInit+0x3c>
    4fc2:	bf00      	nop
    4fc4:	200001fc 	.word	0x200001fc
    4fc8:	200001f0 	.word	0x200001f0
    4fcc:	200001f8 	.word	0x200001f8
    4fd0:	20000200 	.word	0x20000200
    4fd4:	200001f4 	.word	0x200001f4

00004fd8 <CC_PalTerminate>:
    4fd8:	b508      	push	{r3, lr}
    4fda:	4808      	ldr	r0, [pc, #32]	; (4ffc <CC_PalTerminate+0x24>)
    4fdc:	f000 f824 	bl	5028 <CC_PalMutexDestroy>
    4fe0:	4807      	ldr	r0, [pc, #28]	; (5000 <CC_PalTerminate+0x28>)
    4fe2:	f000 f821 	bl	5028 <CC_PalMutexDestroy>
    4fe6:	4807      	ldr	r0, [pc, #28]	; (5004 <CC_PalTerminate+0x2c>)
    4fe8:	f000 f81e 	bl	5028 <CC_PalMutexDestroy>
    4fec:	4806      	ldr	r0, [pc, #24]	; (5008 <CC_PalTerminate+0x30>)
    4fee:	f000 f81b 	bl	5028 <CC_PalMutexDestroy>
    4ff2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    4ff6:	f000 b80b 	b.w	5010 <CC_PalDmaTerminate>
    4ffa:	bf00      	nop
    4ffc:	200001fc 	.word	0x200001fc
    5000:	200001f0 	.word	0x200001f0
    5004:	200001f8 	.word	0x200001f8
    5008:	200001f4 	.word	0x200001f4

0000500c <CC_PalDmaInit>:
    500c:	2000      	movs	r0, #0
    500e:	4770      	bx	lr

00005010 <CC_PalDmaTerminate>:
    5010:	4770      	bx	lr
    5012:	bf00      	nop

00005014 <CC_PalMutexCreate>:
    5014:	b508      	push	{r3, lr}
    5016:	4b03      	ldr	r3, [pc, #12]	; (5024 <CC_PalMutexCreate+0x10>)
    5018:	6802      	ldr	r2, [r0, #0]
    501a:	681b      	ldr	r3, [r3, #0]
    501c:	6810      	ldr	r0, [r2, #0]
    501e:	4798      	blx	r3
    5020:	2000      	movs	r0, #0
    5022:	bd08      	pop	{r3, pc}
    5024:	200001b4 	.word	0x200001b4

00005028 <CC_PalMutexDestroy>:
    5028:	b508      	push	{r3, lr}
    502a:	4b03      	ldr	r3, [pc, #12]	; (5038 <CC_PalMutexDestroy+0x10>)
    502c:	6802      	ldr	r2, [r0, #0]
    502e:	685b      	ldr	r3, [r3, #4]
    5030:	6810      	ldr	r0, [r2, #0]
    5032:	4798      	blx	r3
    5034:	2000      	movs	r0, #0
    5036:	bd08      	pop	{r3, pc}
    5038:	200001b4 	.word	0x200001b4

0000503c <CC_PalPowerSaveModeInit>:
    503c:	b570      	push	{r4, r5, r6, lr}
    503e:	4c09      	ldr	r4, [pc, #36]	; (5064 <CC_PalPowerSaveModeInit+0x28>)
    5040:	4d09      	ldr	r5, [pc, #36]	; (5068 <CC_PalPowerSaveModeInit+0x2c>)
    5042:	6920      	ldr	r0, [r4, #16]
    5044:	68ab      	ldr	r3, [r5, #8]
    5046:	4798      	blx	r3
    5048:	b118      	cbz	r0, 5052 <CC_PalPowerSaveModeInit+0x16>
    504a:	4b08      	ldr	r3, [pc, #32]	; (506c <CC_PalPowerSaveModeInit+0x30>)
    504c:	4808      	ldr	r0, [pc, #32]	; (5070 <CC_PalPowerSaveModeInit+0x34>)
    504e:	685b      	ldr	r3, [r3, #4]
    5050:	4798      	blx	r3
    5052:	2100      	movs	r1, #0
    5054:	4a07      	ldr	r2, [pc, #28]	; (5074 <CC_PalPowerSaveModeInit+0x38>)
    5056:	68eb      	ldr	r3, [r5, #12]
    5058:	6011      	str	r1, [r2, #0]
    505a:	6920      	ldr	r0, [r4, #16]
    505c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5060:	4718      	bx	r3
    5062:	bf00      	nop
    5064:	200001c4 	.word	0x200001c4
    5068:	200001b4 	.word	0x200001b4
    506c:	200001a4 	.word	0x200001a4
    5070:	00006f34 	.word	0x00006f34
    5074:	20000bec 	.word	0x20000bec

00005078 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5078:	4603      	mov	r3, r0
    507a:	b158      	cbz	r0, 5094 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    507c:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    507e:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5082:	2a01      	cmp	r2, #1
    5084:	d003      	beq.n	508e <sys_notify_validate+0x16>
    5086:	2a03      	cmp	r2, #3
    5088:	d104      	bne.n	5094 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    508a:	6802      	ldr	r2, [r0, #0]
    508c:	b112      	cbz	r2, 5094 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    508e:	2000      	movs	r0, #0
    5090:	6098      	str	r0, [r3, #8]
    5092:	4770      	bx	lr
		return -EINVAL;
    5094:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5098:	4770      	bx	lr

0000509a <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    509a:	6842      	ldr	r2, [r0, #4]

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    509c:	4603      	mov	r3, r0
	return method & SYS_NOTIFY_METHOD_MASK;
    509e:	f002 0203 	and.w	r2, r2, #3

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
	switch (method) {
    50a2:	2a03      	cmp	r2, #3
    50a4:	f04f 0200 	mov.w	r2, #0
	notify->result = res;
    50a8:	6081      	str	r1, [r0, #8]
	sys_notify_generic_callback rv = NULL;
    50aa:	bf14      	ite	ne
    50ac:	4610      	movne	r0, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    50ae:	6800      	ldreq	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    50b0:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    50b2:	4770      	bx	lr

000050b4 <arch_printk_char_out>:
}
    50b4:	2000      	movs	r0, #0
    50b6:	4770      	bx	lr

000050b8 <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    50b8:	b40f      	push	{r0, r1, r2, r3}
    50ba:	b507      	push	{r0, r1, r2, lr}
    50bc:	a904      	add	r1, sp, #16
    50be:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    50c2:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    50c4:	f7fb fa24 	bl	510 <vprintk>

	va_end(ap);
}
    50c8:	b003      	add	sp, #12
    50ca:	f85d eb04 	ldr.w	lr, [sp], #4
    50ce:	b004      	add	sp, #16
    50d0:	4770      	bx	lr

000050d2 <sys_slist_find_and_remove>:
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    50d2:	2200      	movs	r2, #0
    50d4:	b510      	push	{r4, lr}
    50d6:	4603      	mov	r3, r0
	return list->head;
    50d8:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    50da:	b158      	cbz	r0, 50f4 <sys_slist_find_and_remove+0x22>
    50dc:	4288      	cmp	r0, r1
    50de:	d10f      	bne.n	5100 <sys_slist_find_and_remove+0x2e>
	return node->next;
    50e0:	6808      	ldr	r0, [r1, #0]
	return list->tail;
    50e2:	685c      	ldr	r4, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    50e4:	b93a      	cbnz	r2, 50f6 <sys_slist_find_and_remove+0x24>
    50e6:	42a1      	cmp	r1, r4
	list->head = node;
    50e8:	6018      	str	r0, [r3, #0]
Z_GENLIST_REMOVE(slist, snode)
    50ea:	d100      	bne.n	50ee <sys_slist_find_and_remove+0x1c>
	list->tail = node;
    50ec:	6058      	str	r0, [r3, #4]
	parent->next = child;
    50ee:	2300      	movs	r3, #0
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    50f0:	2001      	movs	r0, #1
	parent->next = child;
    50f2:	600b      	str	r3, [r1, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    50f4:	bd10      	pop	{r4, pc}
Z_GENLIST_REMOVE(slist, snode)
    50f6:	42a1      	cmp	r1, r4
	parent->next = child;
    50f8:	6010      	str	r0, [r2, #0]
	list->tail = node;
    50fa:	bf08      	it	eq
    50fc:	605a      	streq	r2, [r3, #4]
}
    50fe:	e7f6      	b.n	50ee <sys_slist_find_and_remove+0x1c>
	return node->next;
    5100:	4602      	mov	r2, r0
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    5102:	6800      	ldr	r0, [r0, #0]
    5104:	e7e9      	b.n	50da <sys_slist_find_and_remove+0x8>

00005106 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5106:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    5108:	f013 0307 	ands.w	r3, r3, #7
    510c:	d105      	bne.n	511a <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    510e:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    5110:	2b00      	cmp	r3, #0
    5112:	bf0c      	ite	eq
    5114:	2000      	moveq	r0, #0
    5116:	2003      	movne	r0, #3
    5118:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    511a:	2b02      	cmp	r3, #2
    511c:	d105      	bne.n	512a <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    511e:	8b43      	ldrh	r3, [r0, #26]
		evt = EVT_STOP;
    5120:	2b00      	cmp	r3, #0
    5122:	bf14      	ite	ne
    5124:	2000      	movne	r0, #0
    5126:	2004      	moveq	r0, #4
    5128:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    512a:	2b01      	cmp	r3, #1
    512c:	d105      	bne.n	513a <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    512e:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    5130:	2b00      	cmp	r3, #0
    5132:	bf0c      	ite	eq
    5134:	2000      	moveq	r0, #0
    5136:	2005      	movne	r0, #5
    5138:	4770      	bx	lr
	int evt = EVT_NOP;
    513a:	2000      	movs	r0, #0
}
    513c:	4770      	bx	lr

0000513e <notify_one>:
{
    513e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5142:	460d      	mov	r5, r1
    5144:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5146:	4619      	mov	r1, r3
    5148:	1d28      	adds	r0, r5, #4
{
    514a:	4690      	mov	r8, r2
    514c:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    514e:	f7ff ffa4 	bl	509a <sys_notify_finalize>
	if (cb) {
    5152:	4604      	mov	r4, r0
    5154:	b138      	cbz	r0, 5166 <notify_one+0x28>
		cb(mgr, cli, state, res);
    5156:	4633      	mov	r3, r6
    5158:	4642      	mov	r2, r8
    515a:	4629      	mov	r1, r5
    515c:	4638      	mov	r0, r7
    515e:	46a4      	mov	ip, r4
}
    5160:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    5164:	4760      	bx	ip
}
    5166:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000516a <transition_complete>:
{
    516a:	b410      	push	{r4}
	__asm__ volatile(
    516c:	f04f 0420 	mov.w	r4, #32
    5170:	f3ef 8211 	mrs	r2, BASEPRI
    5174:	f384 8812 	msr	BASEPRI_MAX, r4
    5178:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    517c:	6141      	str	r1, [r0, #20]
}
    517e:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    5180:	2101      	movs	r1, #1
    5182:	f7fb b9d3 	b.w	52c <process_event>

00005186 <validate_args>:
{
    5186:	b510      	push	{r4, lr}
    5188:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    518a:	b140      	cbz	r0, 519e <validate_args+0x18>
    518c:	b139      	cbz	r1, 519e <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    518e:	1d08      	adds	r0, r1, #4
    5190:	f7ff ff72 	bl	5078 <sys_notify_validate>
	if ((rv == 0)
    5194:	b928      	cbnz	r0, 51a2 <validate_args+0x1c>
	    && ((cli->notify.flags
    5196:	68a3      	ldr	r3, [r4, #8]
    5198:	f033 0303 	bics.w	r3, r3, #3
    519c:	d001      	beq.n	51a2 <validate_args+0x1c>
		rv = -EINVAL;
    519e:	f06f 0015 	mvn.w	r0, #21
}
    51a2:	bd10      	pop	{r4, pc}

000051a4 <onoff_manager_init>:
{
    51a4:	b538      	push	{r3, r4, r5, lr}
    51a6:	460c      	mov	r4, r1
	if ((mgr == NULL)
    51a8:	4605      	mov	r5, r0
    51aa:	b158      	cbz	r0, 51c4 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    51ac:	b151      	cbz	r1, 51c4 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    51ae:	680b      	ldr	r3, [r1, #0]
    51b0:	b143      	cbz	r3, 51c4 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    51b2:	684b      	ldr	r3, [r1, #4]
    51b4:	b133      	cbz	r3, 51c4 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    51b6:	221c      	movs	r2, #28
    51b8:	2100      	movs	r1, #0
    51ba:	f000 f963 	bl	5484 <memset>
	return 0;
    51be:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    51c0:	612c      	str	r4, [r5, #16]
}
    51c2:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    51c4:	f06f 0015 	mvn.w	r0, #21
    51c8:	e7fb      	b.n	51c2 <onoff_manager_init+0x1e>

000051ca <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    51ca:	b570      	push	{r4, r5, r6, lr}
    51cc:	4604      	mov	r4, r0
    51ce:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    51d0:	f7ff ffd9 	bl	5186 <validate_args>

	if (rv < 0) {
    51d4:	1e05      	subs	r5, r0, #0
    51d6:	db31      	blt.n	523c <onoff_request+0x72>
    51d8:	f04f 0320 	mov.w	r3, #32
    51dc:	f3ef 8111 	mrs	r1, BASEPRI
    51e0:	f383 8812 	msr	BASEPRI_MAX, r3
    51e4:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    51e8:	f64f 75ff 	movw	r5, #65535	; 0xffff
    51ec:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    51ee:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    51f0:	42ab      	cmp	r3, r5
    51f2:	f000 0207 	and.w	r2, r0, #7
    51f6:	d02e      	beq.n	5256 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    51f8:	2a02      	cmp	r2, #2
    51fa:	d10e      	bne.n	521a <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    51fc:	3301      	adds	r3, #1
    51fe:	8363      	strh	r3, [r4, #26]
	rv = state;
    5200:	4615      	mov	r5, r2
		notify = true;
    5202:	2301      	movs	r3, #1
	__asm__ volatile(
    5204:	f381 8811 	msr	BASEPRI, r1
    5208:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    520c:	b1b3      	cbz	r3, 523c <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    520e:	2300      	movs	r3, #0
    5210:	4631      	mov	r1, r6
    5212:	4620      	mov	r0, r4
    5214:	f7ff ff93 	bl	513e <notify_one>
    5218:	e010      	b.n	523c <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    521a:	0783      	lsls	r3, r0, #30
    521c:	d001      	beq.n	5222 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    521e:	2a06      	cmp	r2, #6
    5220:	d10e      	bne.n	5240 <onoff_request+0x76>
	parent->next = child;
    5222:	2300      	movs	r3, #0
    5224:	6033      	str	r3, [r6, #0]
	return list->tail;
    5226:	6863      	ldr	r3, [r4, #4]
Z_GENLIST_APPEND(slist, snode)
    5228:	b993      	cbnz	r3, 5250 <onoff_request+0x86>
	list->head = node;
    522a:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    522e:	4615      	mov	r5, r2
    5230:	b962      	cbnz	r2, 524c <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    5232:	460a      	mov	r2, r1
    5234:	4620      	mov	r0, r4
    5236:	2102      	movs	r1, #2
    5238:	f7fb f978 	bl	52c <process_event>
		}
	}

	return rv;
}
    523c:	4628      	mov	r0, r5
    523e:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    5240:	2a05      	cmp	r2, #5
    5242:	bf0c      	ite	eq
    5244:	f06f 0585 	mvneq.w	r5, #133	; 0x85
    5248:	f06f 0504 	mvnne.w	r5, #4
    524c:	2300      	movs	r3, #0
    524e:	e7d9      	b.n	5204 <onoff_request+0x3a>
	parent->next = child;
    5250:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5252:	6066      	str	r6, [r4, #4]
}
    5254:	e7eb      	b.n	522e <onoff_request+0x64>
		rv = -EAGAIN;
    5256:	f06f 050a 	mvn.w	r5, #10
    525a:	e7f7      	b.n	524c <onoff_request+0x82>

0000525c <onoff_release>:

int onoff_release(struct onoff_manager *mgr)
{
    525c:	b510      	push	{r4, lr}
	__asm__ volatile(
    525e:	f04f 0320 	mov.w	r3, #32
    5262:	f3ef 8211 	mrs	r2, BASEPRI
    5266:	f383 8812 	msr	BASEPRI_MAX, r3
    526a:	f3bf 8f6f 	isb	sy
	bool stop = false;      /* trigger a stop transition */

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    526e:	8b04      	ldrh	r4, [r0, #24]
    5270:	f004 0407 	and.w	r4, r4, #7
	int rv = state;

	if (state != ONOFF_STATE_ON) {
    5274:	2c02      	cmp	r4, #2
    5276:	d00a      	beq.n	528e <onoff_release+0x32>
		if (state == ONOFF_STATE_ERROR) {
			rv = -EIO;
		} else {
			rv = -ENOTSUP;
    5278:	2c01      	cmp	r4, #1
    527a:	bf0c      	ite	eq
    527c:	f06f 0004 	mvneq.w	r0, #4
    5280:	f06f 0085 	mvnne.w	r0, #133	; 0x85
	__asm__ volatile(
    5284:	f382 8811 	msr	BASEPRI, r2
    5288:	f3bf 8f6f 	isb	sy
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);
	}

	return rv;
    528c:	e008      	b.n	52a0 <onoff_release+0x44>
	mgr->refs -= 1U;
    528e:	8b43      	ldrh	r3, [r0, #26]
    5290:	3b01      	subs	r3, #1
    5292:	b29b      	uxth	r3, r3
    5294:	8343      	strh	r3, [r0, #26]
	if (stop) {
    5296:	b923      	cbnz	r3, 52a2 <onoff_release+0x46>
		process_event(mgr, EVT_RECHECK, key);
    5298:	4621      	mov	r1, r4
    529a:	f7fb f947 	bl	52c <process_event>
	int rv = state;
    529e:	4620      	mov	r0, r4
}
    52a0:	bd10      	pop	{r4, pc}
	int rv = state;
    52a2:	4620      	mov	r0, r4
    52a4:	e7ee      	b.n	5284 <onoff_release+0x28>

000052a6 <onoff_cancel>:
	return rv;
}

int onoff_cancel(struct onoff_manager *mgr,
		 struct onoff_client *cli)
{
    52a6:	b538      	push	{r3, r4, r5, lr}
	if ((mgr == NULL) || (cli == NULL)) {
    52a8:	b1b0      	cbz	r0, 52d8 <onoff_cancel+0x32>
    52aa:	b1a9      	cbz	r1, 52d8 <onoff_cancel+0x32>
	__asm__ volatile(
    52ac:	f04f 0220 	mov.w	r2, #32
    52b0:	f3ef 8511 	mrs	r5, BASEPRI
    52b4:	f382 8812 	msr	BASEPRI_MAX, r2
    52b8:	f3bf 8f6f 	isb	sy
		return -EINVAL;
	}

	int rv = -EALREADY;
	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    52bc:	8b04      	ldrh	r4, [r0, #24]

	if (sys_slist_find_and_remove(&mgr->clients, &cli->node)) {
    52be:	f7ff ff08 	bl	50d2 <sys_slist_find_and_remove>
    52c2:	b130      	cbz	r0, 52d2 <onoff_cancel+0x2c>
		__ASSERT_NO_MSG((state == ONOFF_STATE_TO_ON)
				|| (state == ONOFF_STATE_TO_OFF)
				|| (state == ONOFF_STATE_RESETTING));
		rv = state;
    52c4:	f004 0007 	and.w	r0, r4, #7
	__asm__ volatile(
    52c8:	f385 8811 	msr	BASEPRI, r5
    52cc:	f3bf 8f6f 	isb	sy
	}

	k_spin_unlock(&mgr->lock, key);

	return rv;
}
    52d0:	bd38      	pop	{r3, r4, r5, pc}
	int rv = -EALREADY;
    52d2:	f06f 0077 	mvn.w	r0, #119	; 0x77
    52d6:	e7f7      	b.n	52c8 <onoff_cancel+0x22>
		return -EINVAL;
    52d8:	f06f 0015 	mvn.w	r0, #21
    52dc:	e7f8      	b.n	52d0 <onoff_cancel+0x2a>

000052de <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    52de:	4604      	mov	r4, r0
    52e0:	b508      	push	{r3, lr}
    52e2:	4608      	mov	r0, r1
    52e4:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    52e6:	461a      	mov	r2, r3
    52e8:	47a0      	blx	r4
	return z_impl_z_current_get();
    52ea:	f7ff fb09 	bl	4900 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    52ee:	f7fc faff 	bl	18f0 <z_impl_k_thread_abort>

000052f2 <encode_uint>:
{
    52f2:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    52f6:	469a      	mov	sl, r3
	bool upcase = isupper((int)conv->specifier);
    52f8:	78d3      	ldrb	r3, [r2, #3]
{
    52fa:	4680      	mov	r8, r0
	switch (specifier) {
    52fc:	2b6f      	cmp	r3, #111	; 0x6f
{
    52fe:	460f      	mov	r7, r1
    5300:	4615      	mov	r5, r2
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    5302:	f1a3 0b41 	sub.w	fp, r3, #65	; 0x41
	switch (specifier) {
    5306:	d029      	beq.n	535c <encode_uint+0x6a>
    5308:	d824      	bhi.n	5354 <encode_uint+0x62>
		return 16;
    530a:	2b58      	cmp	r3, #88	; 0x58
    530c:	bf14      	ite	ne
    530e:	260a      	movne	r6, #10
    5310:	2610      	moveq	r6, #16
	char *bp = bps + (bpe - bps);
    5312:	f8dd 9028 	ldr.w	r9, [sp, #40]	; 0x28
		unsigned int lsv = (unsigned int)(value % radix);
    5316:	4632      	mov	r2, r6
    5318:	2300      	movs	r3, #0
    531a:	4640      	mov	r0, r8
    531c:	4639      	mov	r1, r7
    531e:	f7fa ff19 	bl	154 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5322:	2a09      	cmp	r2, #9
    5324:	b2d4      	uxtb	r4, r2
    5326:	d81e      	bhi.n	5366 <encode_uint+0x74>
    5328:	3430      	adds	r4, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    532a:	45b0      	cmp	r8, r6
		*--bp = (lsv <= 9) ? ('0' + lsv)
    532c:	b2e4      	uxtb	r4, r4
	} while ((value != 0) && (bps < bp));
    532e:	f177 0300 	sbcs.w	r3, r7, #0
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5332:	f809 4d01 	strb.w	r4, [r9, #-1]!
	} while ((value != 0) && (bps < bp));
    5336:	d301      	bcc.n	533c <encode_uint+0x4a>
    5338:	45d1      	cmp	r9, sl
    533a:	d811      	bhi.n	5360 <encode_uint+0x6e>
	if (conv->flag_hash) {
    533c:	782b      	ldrb	r3, [r5, #0]
    533e:	069b      	lsls	r3, r3, #26
    5340:	d505      	bpl.n	534e <encode_uint+0x5c>
		if (radix == 8) {
    5342:	2e08      	cmp	r6, #8
    5344:	d115      	bne.n	5372 <encode_uint+0x80>
			conv->altform_0 = true;
    5346:	78ab      	ldrb	r3, [r5, #2]
    5348:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    534c:	70ab      	strb	r3, [r5, #2]
}
    534e:	4648      	mov	r0, r9
    5350:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    5354:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
    5358:	2b70      	cmp	r3, #112	; 0x70
    535a:	e7d7      	b.n	530c <encode_uint+0x1a>
	switch (specifier) {
    535c:	2608      	movs	r6, #8
    535e:	e7d8      	b.n	5312 <encode_uint+0x20>
		value /= radix;
    5360:	4680      	mov	r8, r0
    5362:	460f      	mov	r7, r1
    5364:	e7d7      	b.n	5316 <encode_uint+0x24>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5366:	f1bb 0f19 	cmp.w	fp, #25
    536a:	bf94      	ite	ls
    536c:	3437      	addls	r4, #55	; 0x37
    536e:	3457      	addhi	r4, #87	; 0x57
    5370:	e7db      	b.n	532a <encode_uint+0x38>
		} else if (radix == 16) {
    5372:	2e10      	cmp	r6, #16
    5374:	d1eb      	bne.n	534e <encode_uint+0x5c>
			conv->altform_0c = true;
    5376:	78ab      	ldrb	r3, [r5, #2]
    5378:	f043 0310 	orr.w	r3, r3, #16
    537c:	e7e6      	b.n	534c <encode_uint+0x5a>

0000537e <outs>:
{
    537e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5382:	4607      	mov	r7, r0
    5384:	4688      	mov	r8, r1
    5386:	4615      	mov	r5, r2
    5388:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    538a:	4614      	mov	r4, r2
    538c:	42b4      	cmp	r4, r6
    538e:	eba4 0005 	sub.w	r0, r4, r5
    5392:	d302      	bcc.n	539a <outs+0x1c>
    5394:	b93e      	cbnz	r6, 53a6 <outs+0x28>
    5396:	7823      	ldrb	r3, [r4, #0]
    5398:	b12b      	cbz	r3, 53a6 <outs+0x28>
		int rc = out((int)*sp++, ctx);
    539a:	4641      	mov	r1, r8
    539c:	f814 0b01 	ldrb.w	r0, [r4], #1
    53a0:	47b8      	blx	r7
		if (rc < 0) {
    53a2:	2800      	cmp	r0, #0
    53a4:	daf2      	bge.n	538c <outs+0xe>
}
    53a6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000053aa <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_LEGACY_INCLUDE_PATH, 1);

GEN_ABS_SYM_END
    53aa:	4770      	bx	lr

000053ac <pm_state_exit_post_ops>:
    53ac:	2300      	movs	r3, #0
    53ae:	f383 8811 	msr	BASEPRI, r3
    53b2:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    53b6:	4770      	bx	lr

000053b8 <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
    53b8:	2000      	movs	r0, #0
{
    53ba:	b508      	push	{r3, lr}
	sys_reboot(SYS_REBOOT_WARM);
    53bc:	f7fb fd58 	bl	e70 <sys_reboot>

000053c0 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    53c0:	f001 b92c 	b.w	661c <z_fatal_error>

000053c4 <z_do_kernel_oops>:
 *   fault handler will executed instead of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    53c4:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    53c6:	6800      	ldr	r0, [r0, #0]
    53c8:	f001 b928 	b.w	661c <z_fatal_error>

000053cc <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    53cc:	2100      	movs	r1, #0
    53ce:	2001      	movs	r0, #1
    53d0:	f7ff bff6 	b.w	53c0 <z_arm_fatal_error>

000053d4 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    53d4:	b508      	push	{r3, lr}
	handler();
    53d6:	f7fc f845 	bl	1464 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    53da:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    53de:	f7fc b907 	b.w	15f0 <z_arm_exc_exit>

000053e2 <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    53e2:	6e43      	ldr	r3, [r0, #100]	; 0x64
    53e4:	f383 880b 	msr	PSPLIM, r3
}
    53e8:	4770      	bx	lr

000053ea <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    53ea:	e840 f300 	tt	r3, r0
int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
		return addr_info.flags.mpu_region;
    53ee:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    53f2:	b2d8      	uxtb	r0, r3
	}

	return -EINVAL;
}
    53f4:	bf08      	it	eq
    53f6:	f06f 0015 	mvneq.w	r0, #21
    53fa:	4770      	bx	lr

000053fc <mpu_configure_region>:
{
    53fc:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	p_attr->rbar = attr->rbar &
    53fe:	890a      	ldrh	r2, [r1, #8]
    5400:	894e      	ldrh	r6, [r1, #10]
	region_conf.base = new_region->start;
    5402:	680b      	ldr	r3, [r1, #0]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    5404:	684d      	ldr	r5, [r1, #4]
    5406:	f002 021f 	and.w	r2, r2, #31
    540a:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
	region_conf.base = new_region->start;
    540e:	9300      	str	r3, [sp, #0]
    5410:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    5414:	f023 031f 	bic.w	r3, r3, #31
    5418:	1e6a      	subs	r2, r5, #1
    541a:	4413      	add	r3, r2
    541c:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1U)) {
    5420:	2807      	cmp	r0, #7
    5422:	9303      	str	r3, [sp, #12]
    5424:	d804      	bhi.n	5430 <mpu_configure_region+0x34>
	region_init(index, region_conf);
    5426:	4669      	mov	r1, sp
    5428:	f7fc fa94 	bl	1954 <region_init>
}
    542c:	b004      	add	sp, #16
    542e:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    5430:	f06f 0015 	mvn.w	r0, #21
	return region_allocate_and_init(index,
    5434:	e7fa      	b.n	542c <mpu_configure_region+0x30>

00005436 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    5436:	4603      	mov	r3, r0
	size_t n = 0;
    5438:	2000      	movs	r0, #0

	while (*s != '\0') {
    543a:	5c1a      	ldrb	r2, [r3, r0]
    543c:	b902      	cbnz	r2, 5440 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    543e:	4770      	bx	lr
		n++;
    5440:	3001      	adds	r0, #1
    5442:	e7fa      	b.n	543a <strlen+0x4>

00005444 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    5444:	4603      	mov	r3, r0
	size_t n = 0;
    5446:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    5448:	5c1a      	ldrb	r2, [r3, r0]
    544a:	b10a      	cbz	r2, 5450 <strnlen+0xc>
    544c:	4288      	cmp	r0, r1
    544e:	d100      	bne.n	5452 <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    5450:	4770      	bx	lr
		n++;
    5452:	3001      	adds	r0, #1
    5454:	e7f8      	b.n	5448 <strnlen+0x4>

00005456 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    5456:	1e43      	subs	r3, r0, #1
    5458:	3901      	subs	r1, #1
    545a:	f813 2f01 	ldrb.w	r2, [r3, #1]!
    545e:	f811 0f01 	ldrb.w	r0, [r1, #1]!
    5462:	4282      	cmp	r2, r0
    5464:	d101      	bne.n	546a <strcmp+0x14>
    5466:	2a00      	cmp	r2, #0
    5468:	d1f7      	bne.n	545a <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    546a:	1a10      	subs	r0, r2, r0
    546c:	4770      	bx	lr

0000546e <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    546e:	b510      	push	{r4, lr}
    5470:	1e43      	subs	r3, r0, #1
    5472:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    5474:	4291      	cmp	r1, r2
    5476:	d100      	bne.n	547a <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    5478:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    547a:	f811 4b01 	ldrb.w	r4, [r1], #1
    547e:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    5482:	e7f7      	b.n	5474 <memcpy+0x6>

00005484 <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    5484:	4603      	mov	r3, r0
	unsigned char c_byte = (unsigned char)c;
    5486:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    5488:	4402      	add	r2, r0
    548a:	4293      	cmp	r3, r2
    548c:	d100      	bne.n	5490 <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    548e:	4770      	bx	lr
		*(d_byte++) = c_byte;
    5490:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5494:	e7f9      	b.n	548a <memset+0x6>

00005496 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    5496:	220c      	movs	r2, #12
    5498:	6903      	ldr	r3, [r0, #16]
    549a:	b2c9      	uxtb	r1, r1
    549c:	fb01 3302 	mla	r3, r1, r2, r3
    54a0:	6f98      	ldr	r0, [r3, #120]	; 0x78
}
    54a2:	f000 0007 	and.w	r0, r0, #7
    54a6:	4770      	bx	lr

000054a8 <set_on_state>:
	__asm__ volatile(
    54a8:	f04f 0320 	mov.w	r3, #32
    54ac:	f3ef 8211 	mrs	r2, BASEPRI
    54b0:	f383 8812 	msr	BASEPRI_MAX, r3
    54b4:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    54b8:	6803      	ldr	r3, [r0, #0]
    54ba:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    54be:	f043 0302 	orr.w	r3, r3, #2
    54c2:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    54c4:	f382 8811 	msr	BASEPRI, r2
    54c8:	f3bf 8f6f 	isb	sy
}
    54cc:	4770      	bx	lr

000054ce <stop>:
{
    54ce:	4603      	mov	r3, r0
    54d0:	b570      	push	{r4, r5, r6, lr}
	struct nrf_clock_control_data *data = dev->data;
    54d2:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
    54d4:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    54d6:	f04f 0420 	mov.w	r4, #32
    54da:	f3ef 8611 	mrs	r6, BASEPRI
    54de:	f384 8812 	msr	BASEPRI_MAX, r4
    54e2:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    54e6:	250c      	movs	r5, #12
    54e8:	fb05 0401 	mla	r4, r5, r1, r0
    54ec:	6fa4      	ldr	r4, [r4, #120]	; 0x78
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    54ee:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    54f2:	d001      	beq.n	54f8 <stop+0x2a>
    54f4:	42a2      	cmp	r2, r4
    54f6:	d110      	bne.n	551a <stop+0x4c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    54f8:	2201      	movs	r2, #1
    54fa:	fb05 0001 	mla	r0, r5, r1, r0
    54fe:	6782      	str	r2, [r0, #120]	; 0x78
	int err = 0;
    5500:	2000      	movs	r0, #0
	__asm__ volatile(
    5502:	f386 8811 	msr	BASEPRI, r6
    5506:	f3bf 8f6f 	isb	sy
	if (err < 0) {
    550a:	b928      	cbnz	r0, 5518 <stop+0x4a>
	get_sub_config(dev, type)->stop();
    550c:	685b      	ldr	r3, [r3, #4]
    550e:	eb03 01c1 	add.w	r1, r3, r1, lsl #3
    5512:	684b      	ldr	r3, [r1, #4]
    5514:	4798      	blx	r3
	return 0;
    5516:	2000      	movs	r0, #0
}
    5518:	bd70      	pop	{r4, r5, r6, pc}
		err = -EPERM;
    551a:	f04f 30ff 	mov.w	r0, #4294967295
    551e:	e7f0      	b.n	5502 <stop+0x34>

00005520 <api_stop>:
	return stop(dev, subsys, CTX_API);
    5520:	2280      	movs	r2, #128	; 0x80
    5522:	f7ff bfd4 	b.w	54ce <stop>

00005526 <async_start>:
{
    5526:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5528:	9f06      	ldr	r7, [sp, #24]
    552a:	4605      	mov	r5, r0
	struct nrf_clock_control_data *data = dev->data;
    552c:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    552e:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    5530:	f04f 0020 	mov.w	r0, #32
    5534:	f3ef 8c11 	mrs	ip, BASEPRI
    5538:	f380 8812 	msr	BASEPRI_MAX, r0
    553c:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    5540:	260c      	movs	r6, #12
    5542:	fb06 4601 	mla	r6, r6, r1, r4
    5546:	6fb0      	ldr	r0, [r6, #120]	; 0x78
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    5548:	f000 0e07 	and.w	lr, r0, #7
    554c:	f1be 0f01 	cmp.w	lr, #1
    5550:	d111      	bne.n	5576 <async_start+0x50>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    5552:	67b7      	str	r7, [r6, #120]	; 0x78
	int err = 0;
    5554:	2600      	movs	r6, #0
	__asm__ volatile(
    5556:	f38c 8811 	msr	BASEPRI, ip
    555a:	f3bf 8f6f 	isb	sy
	if (err < 0) {
    555e:	b946      	cbnz	r6, 5572 <async_start+0x4c>
	subdata->cb = cb;
    5560:	200c      	movs	r0, #12
    5562:	fb00 4401 	mla	r4, r0, r1, r4
	subdata->user_data = user_data;
    5566:	e9c4 231c 	strd	r2, r3, [r4, #112]	; 0x70
	 get_sub_config(dev, type)->start();
    556a:	686b      	ldr	r3, [r5, #4]
    556c:	f853 3031 	ldr.w	r3, [r3, r1, lsl #3]
    5570:	4798      	blx	r3
}
    5572:	4630      	mov	r0, r6
    5574:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    5576:	f000 00c0 	and.w	r0, r0, #192	; 0xc0
		err = -EALREADY;
    557a:	4287      	cmp	r7, r0
    557c:	bf14      	ite	ne
    557e:	f04f 36ff 	movne.w	r6, #4294967295
    5582:	f06f 0677 	mvneq.w	r6, #119	; 0x77
    5586:	e7e6      	b.n	5556 <async_start+0x30>

00005588 <api_start>:
{
    5588:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    558a:	2480      	movs	r4, #128	; 0x80
    558c:	9400      	str	r4, [sp, #0]
    558e:	f7ff ffca 	bl	5526 <async_start>
}
    5592:	b002      	add	sp, #8
    5594:	bd10      	pop	{r4, pc}

00005596 <onoff_started_callback>:
{
    5596:	b410      	push	{r4}
	notify(mgr, 0);
    5598:	241c      	movs	r4, #28
	return &data->mgr[type];
    559a:	6900      	ldr	r0, [r0, #16]
    559c:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    559e:	fb03 0004 	mla	r0, r3, r4, r0
    55a2:	2100      	movs	r1, #0
}
    55a4:	bc10      	pop	{r4}
	notify(mgr, 0);
    55a6:	4710      	bx	r2

000055a8 <hfclkaudio_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
    55a8:	2003      	movs	r0, #3
    55aa:	f000 bf61 	b.w	6470 <nrfx_clock_start>

000055ae <hfclk192m_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK192M);
    55ae:	2002      	movs	r0, #2
    55b0:	f000 bf5e 	b.w	6470 <nrfx_clock_start>

000055b4 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    55b4:	2000      	movs	r0, #0
    55b6:	f000 bf5b 	b.w	6470 <nrfx_clock_start>

000055ba <hfclkaudio_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
    55ba:	2003      	movs	r0, #3
    55bc:	f000 bfb8 	b.w	6530 <nrfx_clock_stop>

000055c0 <hfclk192m_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK192M);
    55c0:	2002      	movs	r0, #2
    55c2:	f000 bfb5 	b.w	6530 <nrfx_clock_stop>

000055c6 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    55c6:	2000      	movs	r0, #0
    55c8:	f000 bfb2 	b.w	6530 <nrfx_clock_stop>

000055cc <blocking_start_callback>:
{
    55cc:	4610      	mov	r0, r2
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    55ce:	f7fe be5d 	b.w	428c <z_impl_k_sem_give>

000055d2 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55d2:	6843      	ldr	r3, [r0, #4]
}
    55d4:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55d6:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    55d8:	691b      	ldr	r3, [r3, #16]
	*value = nrf_gpio_port_in_read(reg);
    55da:	600b      	str	r3, [r1, #0]
}
    55dc:	4770      	bx	lr

000055de <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55de:	6843      	ldr	r3, [r0, #4]
    55e0:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    55e2:	6858      	ldr	r0, [r3, #4]
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    55e4:	4042      	eors	r2, r0
    55e6:	400a      	ands	r2, r1
    55e8:	4042      	eors	r2, r0
    p_reg->OUT = value;
    55ea:	605a      	str	r2, [r3, #4]
}
    55ec:	2000      	movs	r0, #0
    55ee:	4770      	bx	lr

000055f0 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55f0:	6843      	ldr	r3, [r0, #4]
}
    55f2:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55f4:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    55f6:	6099      	str	r1, [r3, #8]
}
    55f8:	4770      	bx	lr

000055fa <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55fa:	6843      	ldr	r3, [r0, #4]
}
    55fc:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    55fe:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    5600:	60d9      	str	r1, [r3, #12]
}
    5602:	4770      	bx	lr

00005604 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5604:	6843      	ldr	r3, [r0, #4]
}
    5606:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5608:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    560a:	6853      	ldr	r3, [r2, #4]
	nrf_gpio_port_out_write(reg, value ^ mask);
    560c:	404b      	eors	r3, r1
    p_reg->OUT = value;
    560e:	6053      	str	r3, [r2, #4]
}
    5610:	4770      	bx	lr

00005612 <gpio_nrfx_manage_callback>:
	return port->data;
    5612:	6903      	ldr	r3, [r0, #16]
{
    5614:	b530      	push	{r4, r5, lr}
	return list->head;
    5616:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    5618:	b158      	cbz	r0, 5632 <gpio_nrfx_manage_callback+0x20>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    561a:	2400      	movs	r4, #0
    561c:	4281      	cmp	r1, r0
    561e:	d112      	bne.n	5646 <gpio_nrfx_manage_callback+0x34>
	return node->next;
    5620:	6808      	ldr	r0, [r1, #0]
	return list->tail;
    5622:	689d      	ldr	r5, [r3, #8]
Z_GENLIST_REMOVE(slist, snode)
    5624:	b954      	cbnz	r4, 563c <gpio_nrfx_manage_callback+0x2a>
    5626:	428d      	cmp	r5, r1
	list->head = node;
    5628:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    562a:	d100      	bne.n	562e <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    562c:	6098      	str	r0, [r3, #8]
	parent->next = child;
    562e:	2000      	movs	r0, #0
    5630:	6008      	str	r0, [r1, #0]
	if (set) {
    5632:	b96a      	cbnz	r2, 5650 <gpio_nrfx_manage_callback+0x3e>
	return 0;
    5634:	2000      	movs	r0, #0
}
    5636:	bd30      	pop	{r4, r5, pc}
    5638:	4628      	mov	r0, r5
    563a:	e7ef      	b.n	561c <gpio_nrfx_manage_callback+0xa>
Z_GENLIST_REMOVE(slist, snode)
    563c:	428d      	cmp	r5, r1
	parent->next = child;
    563e:	6020      	str	r0, [r4, #0]
	list->tail = node;
    5640:	bf08      	it	eq
    5642:	609c      	streq	r4, [r3, #8]
}
    5644:	e7f3      	b.n	562e <gpio_nrfx_manage_callback+0x1c>
	return node->next;
    5646:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    5648:	4604      	mov	r4, r0
    564a:	2d00      	cmp	r5, #0
    564c:	d1f4      	bne.n	5638 <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    564e:	b13a      	cbz	r2, 5660 <gpio_nrfx_manage_callback+0x4e>
	parent->next = child;
    5650:	685a      	ldr	r2, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    5652:	6898      	ldr	r0, [r3, #8]
	parent->next = child;
    5654:	600a      	str	r2, [r1, #0]
	list->head = node;
    5656:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    5658:	2800      	cmp	r0, #0
    565a:	d1eb      	bne.n	5634 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    565c:	6099      	str	r1, [r3, #8]
}
    565e:	e7ea      	b.n	5636 <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    5660:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    5664:	e7e7      	b.n	5636 <gpio_nrfx_manage_callback+0x24>

00005666 <uarte_nrfx_config_get>:
{
    5666:	460b      	mov	r3, r1
	*cfg = data->uart_config;
    5668:	6902      	ldr	r2, [r0, #16]
    566a:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    566e:	e883 0003 	stmia.w	r3, {r0, r1}
}
    5672:	2000      	movs	r0, #0
    5674:	4770      	bx	lr

00005676 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    5676:	6843      	ldr	r3, [r0, #4]
    5678:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    567a:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    567e:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    5682:	4770      	bx	lr

00005684 <timer_handler>:
static void timer_handler(nrf_timer_event_t event_type, void *p_context) { }
    5684:	4770      	bx	lr

00005686 <user_callback>:
	if (data->async->user_callback) {
    5686:	6903      	ldr	r3, [r0, #16]
    5688:	68da      	ldr	r2, [r3, #12]
    568a:	6813      	ldr	r3, [r2, #0]
    568c:	b10b      	cbz	r3, 5692 <user_callback+0xc>
		data->async->user_callback(dev, evt, data->async->user_data);
    568e:	6852      	ldr	r2, [r2, #4]
    5690:	4718      	bx	r3
}
    5692:	4770      	bx	lr

00005694 <notify_uart_rx_rdy>:
{
    5694:	b570      	push	{r4, r5, r6, lr}
    5696:	b086      	sub	sp, #24
	struct uarte_nrfx_data *data = dev->data;
    5698:	6906      	ldr	r6, [r0, #16]
{
    569a:	4604      	mov	r4, r0
    569c:	460d      	mov	r5, r1
	struct uart_event evt = {
    569e:	2214      	movs	r2, #20
    56a0:	2100      	movs	r1, #0
    56a2:	a801      	add	r0, sp, #4
    56a4:	f7ff feee 	bl	5484 <memset>
    56a8:	2302      	movs	r3, #2
    56aa:	f88d 3004 	strb.w	r3, [sp, #4]
		.data.rx.buf = data->async->rx_buf,
    56ae:	68f3      	ldr	r3, [r6, #12]
	user_callback(dev, &evt);
    56b0:	4620      	mov	r0, r4
	struct uart_event evt = {
    56b2:	6e1a      	ldr	r2, [r3, #96]	; 0x60
    56b4:	6e9b      	ldr	r3, [r3, #104]	; 0x68
	user_callback(dev, &evt);
    56b6:	a901      	add	r1, sp, #4
	struct uart_event evt = {
    56b8:	e9cd 3503 	strd	r3, r5, [sp, #12]
    56bc:	9202      	str	r2, [sp, #8]
	user_callback(dev, &evt);
    56be:	f7ff ffe2 	bl	5686 <user_callback>
}
    56c2:	b006      	add	sp, #24
    56c4:	bd70      	pop	{r4, r5, r6, pc}

000056c6 <rx_buf_release>:
{
    56c6:	b570      	push	{r4, r5, r6, lr}
	if (*buf) {
    56c8:	680e      	ldr	r6, [r1, #0]
{
    56ca:	4605      	mov	r5, r0
    56cc:	460c      	mov	r4, r1
    56ce:	b086      	sub	sp, #24
	if (*buf) {
    56d0:	b17e      	cbz	r6, 56f2 <rx_buf_release+0x2c>
		struct uart_event evt = {
    56d2:	2214      	movs	r2, #20
    56d4:	2100      	movs	r1, #0
    56d6:	a801      	add	r0, sp, #4
    56d8:	f7ff fed4 	bl	5484 <memset>
    56dc:	2304      	movs	r3, #4
		user_callback(dev, &evt);
    56de:	4628      	mov	r0, r5
    56e0:	eb0d 0103 	add.w	r1, sp, r3
		struct uart_event evt = {
    56e4:	f88d 3004 	strb.w	r3, [sp, #4]
    56e8:	9602      	str	r6, [sp, #8]
		user_callback(dev, &evt);
    56ea:	f7ff ffcc 	bl	5686 <user_callback>
		*buf = NULL;
    56ee:	2300      	movs	r3, #0
    56f0:	6023      	str	r3, [r4, #0]
}
    56f2:	b006      	add	sp, #24
    56f4:	bd70      	pop	{r4, r5, r6, pc}

000056f6 <notify_rx_disable>:
{
    56f6:	b510      	push	{r4, lr}
    56f8:	b086      	sub	sp, #24
    56fa:	4604      	mov	r4, r0
	struct uart_event evt = {
    56fc:	2214      	movs	r2, #20
    56fe:	2100      	movs	r1, #0
    5700:	a801      	add	r0, sp, #4
    5702:	f7ff febf 	bl	5484 <memset>
    5706:	2305      	movs	r3, #5
	user_callback(dev, (struct uart_event *)&evt);
    5708:	4620      	mov	r0, r4
    570a:	a901      	add	r1, sp, #4
	struct uart_event evt = {
    570c:	f88d 3004 	strb.w	r3, [sp, #4]
	user_callback(dev, (struct uart_event *)&evt);
    5710:	f7ff ffb9 	bl	5686 <user_callback>
}
    5714:	b006      	add	sp, #24
    5716:	bd10      	pop	{r4, pc}

00005718 <uarte_nrfx_rx_buf_rsp>:
	return config->uarte_regs;
    5718:	6843      	ldr	r3, [r0, #4]
{
    571a:	b530      	push	{r4, r5, lr}
	return config->uarte_regs;
    571c:	681b      	ldr	r3, [r3, #0]
	struct uarte_nrfx_data *data = dev->data;
    571e:	6904      	ldr	r4, [r0, #16]
	__asm__ volatile(
    5720:	f04f 0020 	mov.w	r0, #32
    5724:	f3ef 8511 	mrs	r5, BASEPRI
    5728:	f380 8812 	msr	BASEPRI_MAX, r0
    572c:	f3bf 8f6f 	isb	sy
	if (data->async->rx_buf == NULL) {
    5730:	68e4      	ldr	r4, [r4, #12]
    5732:	6e20      	ldr	r0, [r4, #96]	; 0x60
    5734:	b190      	cbz	r0, 575c <uarte_nrfx_rx_buf_rsp+0x44>
	} else if (data->async->rx_next_buf == NULL) {
    5736:	6ee0      	ldr	r0, [r4, #108]	; 0x6c
    5738:	b998      	cbnz	r0, 5762 <uarte_nrfx_rx_buf_rsp+0x4a>
		data->async->rx_next_buf_len = len;
    573a:	e9c4 121b 	strd	r1, r2, [r4, #108]	; 0x6c
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    573e:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    5742:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    p_reg->SHORTS |= mask;
    5746:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    574a:	f042 0220 	orr.w	r2, r2, #32
    574e:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
	__asm__ volatile(
    5752:	f385 8811 	msr	BASEPRI, r5
    5756:	f3bf 8f6f 	isb	sy
}
    575a:	bd30      	pop	{r4, r5, pc}
		err = -EACCES;
    575c:	f06f 000c 	mvn.w	r0, #12
    5760:	e7f7      	b.n	5752 <uarte_nrfx_rx_buf_rsp+0x3a>
		err = -EBUSY;
    5762:	f06f 000f 	mvn.w	r0, #15
    5766:	e7f4      	b.n	5752 <uarte_nrfx_rx_buf_rsp+0x3a>

00005768 <uarte_nrfx_callback_set>:
	if (!data->async) {
    5768:	6903      	ldr	r3, [r0, #16]
    576a:	68db      	ldr	r3, [r3, #12]
    576c:	b11b      	cbz	r3, 5776 <uarte_nrfx_callback_set+0xe>
	return 0;
    576e:	2000      	movs	r0, #0
	data->async->user_data = user_data;
    5770:	e9c3 1200 	strd	r1, r2, [r3]
	return 0;
    5774:	4770      	bx	lr
		return -ENOTSUP;
    5776:	f06f 0085 	mvn.w	r0, #133	; 0x85
}
    577a:	4770      	bx	lr

0000577c <uarte_nrfx_poll_in>:
	const struct uarte_nrfx_data *data = dev->data;
    577c:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    577e:	6843      	ldr	r3, [r0, #4]
	if (data->async) {
    5780:	68d0      	ldr	r0, [r2, #12]
{
    5782:	b510      	push	{r4, lr}
	return config->uarte_regs;
    5784:	681b      	ldr	r3, [r3, #0]
	if (data->async) {
    5786:	b958      	cbnz	r0, 57a0 <uarte_nrfx_poll_in+0x24>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5788:	f8d3 4110 	ldr.w	r4, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    578c:	b15c      	cbz	r4, 57a6 <uarte_nrfx_poll_in+0x2a>
	*c = data->rx_data;
    578e:	7d52      	ldrb	r2, [r2, #21]
    5790:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5792:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    5796:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    579a:	2201      	movs	r2, #1
    579c:	601a      	str	r2, [r3, #0]
}
    579e:	bd10      	pop	{r4, pc}
		return -ENOTSUP;
    57a0:	f06f 0085 	mvn.w	r0, #133	; 0x85
    57a4:	e7fb      	b.n	579e <uarte_nrfx_poll_in+0x22>
		return -1;
    57a6:	f04f 30ff 	mov.w	r0, #4294967295
    57aa:	e7f8      	b.n	579e <uarte_nrfx_poll_in+0x22>

000057ac <uarte_enable>:
{
    57ac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
    57ae:	6907      	ldr	r7, [r0, #16]
{
    57b0:	4604      	mov	r4, r0
	if (data->async) {
    57b2:	68fb      	ldr	r3, [r7, #12]
    57b4:	b92b      	cbnz	r3, 57c2 <uarte_enable+0x16>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    57b6:	2208      	movs	r2, #8
	return config->uarte_regs;
    57b8:	6863      	ldr	r3, [r4, #4]
    57ba:	681b      	ldr	r3, [r3, #0]
    57bc:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
}
    57c0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		bool disabled = data->async->low_power_mask == 0;
    57c2:	f8d3 50c8 	ldr.w	r5, [r3, #200]	; 0xc8
	const struct uarte_nrfx_config *config = dev->config;
    57c6:	6846      	ldr	r6, [r0, #4]
		data->async->low_power_mask |= mask;
    57c8:	4329      	orrs	r1, r5
    57ca:	f8c3 10c8 	str.w	r1, [r3, #200]	; 0xc8
		if (HW_RX_COUNTING_ENABLED(data) && disabled) {
    57ce:	f893 30d3 	ldrb.w	r3, [r3, #211]	; 0xd3
    57d2:	2b00      	cmp	r3, #0
    57d4:	d0ef      	beq.n	57b6 <uarte_enable+0xa>
    57d6:	2d00      	cmp	r5, #0
    57d8:	d1ed      	bne.n	57b6 <uarte_enable+0xa>
			const nrfx_timer_t *timer = &config->timer;
    57da:	3610      	adds	r6, #16
			nrfx_timer_enable(timer);
    57dc:	4630      	mov	r0, r6
    57de:	f7fe fa5d 	bl	3c9c <nrfx_timer_enable>
			for (int i = 0; i < data->async->rx_flush_cnt; i++) {
    57e2:	68fb      	ldr	r3, [r7, #12]
    57e4:	f893 30d1 	ldrb.w	r3, [r3, #209]	; 0xd1
    57e8:	42ab      	cmp	r3, r5
    57ea:	dde4      	ble.n	57b6 <uarte_enable+0xa>
				nrfx_timer_increment(timer);
    57ec:	4630      	mov	r0, r6
    57ee:	f000 fefb 	bl	65e8 <nrfx_timer_increment>
			for (int i = 0; i < data->async->rx_flush_cnt; i++) {
    57f2:	3501      	adds	r5, #1
    57f4:	e7f5      	b.n	57e2 <uarte_enable+0x36>

000057f6 <tx_start>:
	const struct uarte_nrfx_config *config = dev->config;
    57f6:	6843      	ldr	r3, [r0, #4]
{
    57f8:	b510      	push	{r4, lr}
	return config->uarte_regs;
    57fa:	681c      	ldr	r4, [r3, #0]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    57fc:	f8c4 1544 	str.w	r1, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    5800:	f8c4 2548 	str.w	r2, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5804:	2200      	movs	r2, #0
    5806:	f8c4 2120 	str.w	r2, [r4, #288]	; 0x120
    580a:	f8d4 1120 	ldr.w	r1, [r4, #288]	; 0x120
    580e:	f8c4 2158 	str.w	r2, [r4, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    5812:	685b      	ldr	r3, [r3, #4]
    5814:	f8d4 2158 	ldr.w	r2, [r4, #344]	; 0x158
    5818:	06db      	lsls	r3, r3, #27
    581a:	d506      	bpl.n	582a <tx_start+0x34>
		uarte_enable(dev, UARTE_LOW_POWER_TX);
    581c:	2101      	movs	r1, #1
    581e:	f7ff ffc5 	bl	57ac <uarte_enable>
    p_reg->INTENSET = mask;
    5822:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
    5826:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    582a:	2301      	movs	r3, #1
    582c:	60a3      	str	r3, [r4, #8]
}
    582e:	bd10      	pop	{r4, pc}

00005830 <uarte_nrfx_rx_disable>:
{
    5830:	b538      	push	{r3, r4, r5, lr}
	struct uarte_nrfx_data *data = dev->data;
    5832:	6905      	ldr	r5, [r0, #16]
	return config->uarte_regs;
    5834:	6843      	ldr	r3, [r0, #4]
	if (data->async->rx_buf == NULL) {
    5836:	68e8      	ldr	r0, [r5, #12]
	return config->uarte_regs;
    5838:	681c      	ldr	r4, [r3, #0]
	if (data->async->rx_buf == NULL) {
    583a:	6e03      	ldr	r3, [r0, #96]	; 0x60
    583c:	b1b3      	cbz	r3, 586c <uarte_nrfx_rx_disable+0x3c>
	if (data->async->rx_next_buf != NULL) {
    583e:	6ec3      	ldr	r3, [r0, #108]	; 0x6c
    5840:	b153      	cbz	r3, 5858 <uarte_nrfx_rx_disable+0x28>
    p_reg->SHORTS &= ~(mask);
    5842:	f8d4 3200 	ldr.w	r3, [r4, #512]	; 0x200
    5846:	f023 0320 	bic.w	r3, r3, #32
    584a:	f8c4 3200 	str.w	r3, [r4, #512]	; 0x200
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    584e:	2300      	movs	r3, #0
    5850:	f8c4 314c 	str.w	r3, [r4, #332]	; 0x14c
    5854:	f8d4 314c 	ldr.w	r3, [r4, #332]	; 0x14c
	z_impl_k_timer_stop(timer);
    5858:	3088      	adds	r0, #136	; 0x88
    585a:	f001 f879 	bl	6950 <z_impl_k_timer_stop>
	data->async->rx_enabled = false;
    585e:	2000      	movs	r0, #0
    5860:	68eb      	ldr	r3, [r5, #12]
    5862:	f883 00d2 	strb.w	r0, [r3, #210]	; 0xd2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5866:	2301      	movs	r3, #1
    5868:	6063      	str	r3, [r4, #4]
}
    586a:	bd38      	pop	{r3, r4, r5, pc}
		return -EFAULT;
    586c:	f06f 000d 	mvn.w	r0, #13
    5870:	e7fb      	b.n	586a <uarte_nrfx_rx_disable+0x3a>

00005872 <uarte_nrfx_rx_enable>:
{
    5872:	e92d 4fd0 	stmdb	sp!, {r4, r6, r7, r8, r9, sl, fp, lr}
	const struct uarte_nrfx_config *cfg = dev->config;
    5876:	f8d0 a004 	ldr.w	sl, [r0, #4]
{
    587a:	4614      	mov	r4, r2
	if (cfg->disable_rx) {
    587c:	f89a 2008 	ldrb.w	r2, [sl, #8]
{
    5880:	4607      	mov	r7, r0
    5882:	4689      	mov	r9, r1
	struct uarte_nrfx_data *data = dev->data;
    5884:	f8d0 b010 	ldr.w	fp, [r0, #16]
	return config->uarte_regs;
    5888:	f8da 8000 	ldr.w	r8, [sl]
	if (cfg->disable_rx) {
    588c:	2a00      	cmp	r2, #0
    588e:	d169      	bne.n	5964 <uarte_nrfx_rx_enable+0xf2>
	if (data->async->rx_enabled) {
    5890:	f8db 100c 	ldr.w	r1, [fp, #12]
    5894:	f891 20d2 	ldrb.w	r2, [r1, #210]	; 0xd2
    5898:	2a00      	cmp	r2, #0
    589a:	d166      	bne.n	596a <uarte_nrfx_rx_enable+0xf8>
		MAX(timeout / RX_TIMEOUT_DIV,
    589c:	f5b3 7fe8 	cmp.w	r3, #464	; 0x1d0
    58a0:	bfc8      	it	gt
    58a2:	2205      	movgt	r2, #5
	data->async->rx_timeout = timeout;
    58a4:	67cb      	str	r3, [r1, #124]	; 0x7c
		MAX(timeout / RX_TIMEOUT_DIV,
    58a6:	bfcc      	ite	gt
    58a8:	fb93 f3f2 	sdivgt	r3, r3, r2
    58ac:	235c      	movle	r3, #92	; 0x5c
	data->async->rx_timeout_slab =
    58ae:	f8c1 3080 	str.w	r3, [r1, #128]	; 0x80
	data->async->rx_offset = 0;
    58b2:	2300      	movs	r3, #0
	data->async->rx_next_buf = NULL;
    58b4:	e9c1 331a 	strd	r3, r3, [r1, #104]	; 0x68
	data->async->rx_next_buf_len = 0;
    58b8:	670b      	str	r3, [r1, #112]	; 0x70
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    58ba:	f8da 3004 	ldr.w	r3, [sl, #4]
	data->async->rx_buf_len = len;
    58be:	e9c1 9418 	strd	r9, r4, [r1, #96]	; 0x60
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    58c2:	06da      	lsls	r2, r3, #27
    58c4:	d524      	bpl.n	5910 <uarte_nrfx_rx_enable+0x9e>
		if (data->async->rx_flush_cnt) {
    58c6:	f891 60d1 	ldrb.w	r6, [r1, #209]	; 0xd1
    58ca:	b30e      	cbz	r6, 5910 <uarte_nrfx_rx_enable+0x9e>
			int cpy_len = MIN(len, data->async->rx_flush_cnt);
    58cc:	42a6      	cmp	r6, r4
    58ce:	bf28      	it	cs
    58d0:	4626      	movcs	r6, r4
			memcpy(buf, data->async->rx_flush_buffer, cpy_len);
    58d2:	4648      	mov	r0, r9
    58d4:	4632      	mov	r2, r6
    58d6:	31cc      	adds	r1, #204	; 0xcc
    58d8:	f7ff fdc9 	bl	546e <memcpy>
			if (!len) {
    58dc:	1ba4      	subs	r4, r4, r6
			buf += cpy_len;
    58de:	44b1      	add	r9, r6
			if (!len) {
    58e0:	d116      	bne.n	5910 <uarte_nrfx_rx_enable+0x9e>
				data->async->rx_flush_cnt -= cpy_len;
    58e2:	f8db 200c 	ldr.w	r2, [fp, #12]
				notify_uart_rx_rdy(dev, cpy_len);
    58e6:	4631      	mov	r1, r6
				data->async->rx_flush_cnt -= cpy_len;
    58e8:	f892 30d1 	ldrb.w	r3, [r2, #209]	; 0xd1
				notify_uart_rx_rdy(dev, cpy_len);
    58ec:	4638      	mov	r0, r7
				data->async->rx_flush_cnt -= cpy_len;
    58ee:	1b9b      	subs	r3, r3, r6
    58f0:	f882 30d1 	strb.w	r3, [r2, #209]	; 0xd1
				notify_uart_rx_rdy(dev, cpy_len);
    58f4:	f7ff fece 	bl	5694 <notify_uart_rx_rdy>
				rx_buf_release(dev, &data->async->rx_buf);
    58f8:	f8db 100c 	ldr.w	r1, [fp, #12]
    58fc:	4638      	mov	r0, r7
    58fe:	3160      	adds	r1, #96	; 0x60
    5900:	f7ff fee1 	bl	56c6 <rx_buf_release>
				notify_rx_disable(dev);
    5904:	4638      	mov	r0, r7
    5906:	f7ff fef6 	bl	56f6 <notify_rx_disable>
	return 0;
    590a:	2000      	movs	r0, #0
}
    590c:	e8bd 8fd0 	ldmia.w	sp!, {r4, r6, r7, r8, r9, sl, fp, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5910:	2300      	movs	r3, #0
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    5912:	f8c8 9534 	str.w	r9, [r8, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    5916:	f8c8 4538 	str.w	r4, [r8, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    591a:	f8c8 3110 	str.w	r3, [r8, #272]	; 0x110
    591e:	f8d8 2110 	ldr.w	r2, [r8, #272]	; 0x110
	data->async->rx_enabled = true;
    5922:	2201      	movs	r2, #1
    5924:	f8c8 314c 	str.w	r3, [r8, #332]	; 0x14c
    5928:	f8d8 314c 	ldr.w	r3, [r8, #332]	; 0x14c
    592c:	f8db 300c 	ldr.w	r3, [fp, #12]
    5930:	f883 20d2 	strb.w	r2, [r3, #210]	; 0xd2
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    5934:	f8da 3004 	ldr.w	r3, [sl, #4]
    5938:	06db      	lsls	r3, r3, #27
    593a:	d50f      	bpl.n	595c <uarte_nrfx_rx_enable+0xea>
	__asm__ volatile(
    593c:	f04f 0320 	mov.w	r3, #32
    5940:	f3ef 8411 	mrs	r4, BASEPRI
    5944:	f383 8812 	msr	BASEPRI_MAX, r3
    5948:	f3bf 8f6f 	isb	sy
		uarte_enable(dev, UARTE_LOW_POWER_RX);
    594c:	2102      	movs	r1, #2
    594e:	4638      	mov	r0, r7
    5950:	f7ff ff2c 	bl	57ac <uarte_enable>
	__asm__ volatile(
    5954:	f384 8811 	msr	BASEPRI, r4
    5958:	f3bf 8f6f 	isb	sy
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    595c:	2301      	movs	r3, #1
    595e:	f8c8 3000 	str.w	r3, [r8]
    5962:	e7d2      	b.n	590a <uarte_nrfx_rx_enable+0x98>
		return -ENOTSUP;
    5964:	f06f 0085 	mvn.w	r0, #133	; 0x85
    5968:	e7d0      	b.n	590c <uarte_nrfx_rx_enable+0x9a>
		return -EBUSY;
    596a:	f06f 000f 	mvn.w	r0, #15
    596e:	e7cd      	b.n	590c <uarte_nrfx_rx_enable+0x9a>

00005970 <rx_flush.isra.0>:
static uint8_t rx_flush(const struct device *dev, uint8_t *buf, uint32_t len)
    5970:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	return config->uarte_regs;
    5972:	6807      	ldr	r7, [r0, #0]
static uint8_t rx_flush(const struct device *dev, uint8_t *buf, uint32_t len)
    5974:	4615      	mov	r5, r2
	size_t flush_len = buf ? len : sizeof(tmp_buf);
    5976:	460c      	mov	r4, r1
    return p_reg->RXD.AMOUNT;
    5978:	f8d7 653c 	ldr.w	r6, [r7, #1340]	; 0x53c
    597c:	bb31      	cbnz	r1, 59cc <rx_flush.isra.0+0x5c>
    597e:	2505      	movs	r5, #5
		flush_buf = tmp_buf;
    5980:	466b      	mov	r3, sp
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    5982:	f8c7 3534 	str.w	r3, [r7, #1332]	; 0x534
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5986:	2300      	movs	r3, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5988:	2101      	movs	r1, #1
    p_reg->RXD.MAXCNT = length;
    598a:	f8c7 5538 	str.w	r5, [r7, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    598e:	f8c7 3110 	str.w	r3, [r7, #272]	; 0x110
    5992:	f8d7 2110 	ldr.w	r2, [r7, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5996:	62f9      	str	r1, [r7, #44]	; 0x2c
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5998:	f8d7 1110 	ldr.w	r1, [r7, #272]	; 0x110
	while (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    599c:	2900      	cmp	r1, #0
    599e:	d0fb      	beq.n	5998 <rx_flush.isra.0+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    59a0:	f8c7 3110 	str.w	r3, [r7, #272]	; 0x110
    59a4:	f8d7 3110 	ldr.w	r3, [r7, #272]	; 0x110
    return p_reg->RXD.AMOUNT;
    59a8:	f8d7 053c 	ldr.w	r0, [r7, #1340]	; 0x53c
	if (!buf) {
    59ac:	b914      	cbnz	r4, 59b4 <rx_flush.isra.0+0x44>
			return rx_amount;
    59ae:	b2c0      	uxtb	r0, r0
}
    59b0:	b003      	add	sp, #12
    59b2:	bdf0      	pop	{r4, r5, r6, r7, pc}
	if (rx_amount != prev_rx_amount) {
    59b4:	4286      	cmp	r6, r0
    59b6:	d1fa      	bne.n	59ae <rx_flush.isra.0+0x3e>
    59b8:	1962      	adds	r2, r4, r5
	for (int i = 0; i < flush_len; i++) {
    59ba:	42a2      	cmp	r2, r4
    59bc:	d101      	bne.n	59c2 <rx_flush.isra.0+0x52>
	return 0;
    59be:	2000      	movs	r0, #0
    59c0:	e7f6      	b.n	59b0 <rx_flush.isra.0+0x40>
		if (buf[i] != dirty) {
    59c2:	f814 3b01 	ldrb.w	r3, [r4], #1
    59c6:	2b00      	cmp	r3, #0
    59c8:	d0f7      	beq.n	59ba <rx_flush.isra.0+0x4a>
    59ca:	e7f0      	b.n	59ae <rx_flush.isra.0+0x3e>
		memset(buf, dirty, len);
    59cc:	2100      	movs	r1, #0
    59ce:	4620      	mov	r0, r4
    59d0:	f7ff fd58 	bl	5484 <memset>
		flush_len = len;
    59d4:	4623      	mov	r3, r4
    59d6:	e7d4      	b.n	5982 <rx_flush.isra.0+0x12>

000059d8 <async_uart_release>:
{
    59d8:	b570      	push	{r4, r5, r6, lr}
	struct uarte_nrfx_data *data = dev->data;
    59da:	6903      	ldr	r3, [r0, #16]
{
    59dc:	4604      	mov	r4, r0
	__asm__ volatile(
    59de:	f04f 0220 	mov.w	r2, #32
    59e2:	f3ef 8611 	mrs	r6, BASEPRI
    59e6:	f382 8812 	msr	BASEPRI_MAX, r2
    59ea:	f3bf 8f6f 	isb	sy
	data->async->low_power_mask &= ~dir_mask;
    59ee:	68dd      	ldr	r5, [r3, #12]
    59f0:	f8d5 30c8 	ldr.w	r3, [r5, #200]	; 0xc8
    59f4:	ea23 0301 	bic.w	r3, r3, r1
    59f8:	f8c5 30c8 	str.w	r3, [r5, #200]	; 0xc8
	if (!data->async->low_power_mask) {
    59fc:	b9e3      	cbnz	r3, 5a38 <async_uart_release+0x60>
		if (dir_mask == UARTE_LOW_POWER_RX) {
    59fe:	2902      	cmp	r1, #2
    5a00:	d107      	bne.n	5a12 <async_uart_release+0x3a>
				rx_flush(dev, data->async->rx_flush_buffer,
    5a02:	2205      	movs	r2, #5
    5a04:	6840      	ldr	r0, [r0, #4]
    5a06:	f105 01cc 	add.w	r1, r5, #204	; 0xcc
    5a0a:	f7ff ffb1 	bl	5970 <rx_flush.isra.0>
			data->async->rx_flush_cnt =
    5a0e:	f885 00d1 	strb.w	r0, [r5, #209]	; 0xd1
	struct uarte_nrfx_data *data = dev->data;
    5a12:	6925      	ldr	r5, [r4, #16]
	if (data->async && HW_RX_COUNTING_ENABLED(data)) {
    5a14:	68eb      	ldr	r3, [r5, #12]
    5a16:	b153      	cbz	r3, 5a2e <async_uart_release+0x56>
    5a18:	f893 30d3 	ldrb.w	r3, [r3, #211]	; 0xd3
    5a1c:	b13b      	cbz	r3, 5a2e <async_uart_release+0x56>
		nrfx_timer_disable(&config->timer);
    5a1e:	6860      	ldr	r0, [r4, #4]
    5a20:	3010      	adds	r0, #16
    5a22:	f7fe f949 	bl	3cb8 <nrfx_timer_disable>
		data->async->rx_total_byte_cnt = 0;
    5a26:	2200      	movs	r2, #0
    5a28:	68eb      	ldr	r3, [r5, #12]
		data->async->rx_total_user_byte_cnt = 0;
    5a2a:	e9c3 221d 	strd	r2, r2, [r3, #116]	; 0x74
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    5a2e:	2200      	movs	r2, #0
	return config->uarte_regs;
    5a30:	6863      	ldr	r3, [r4, #4]
    5a32:	681b      	ldr	r3, [r3, #0]
    5a34:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
	__asm__ volatile(
    5a38:	f386 8811 	msr	BASEPRI, r6
    5a3c:	f3bf 8f6f 	isb	sy
}
    5a40:	bd70      	pop	{r4, r5, r6, pc}

00005a42 <setup_tx_cache.isra.0>:
	size_t remaining = data->async->tx_size - data->async->tx_cache_offset;
    5a42:	68c2      	ldr	r2, [r0, #12]
    5a44:	6a01      	ldr	r1, [r0, #32]
static bool setup_tx_cache(struct uarte_nrfx_data *data)
    5a46:	b508      	push	{r3, lr}
	if (!remaining) {
    5a48:	1a52      	subs	r2, r2, r1
static bool setup_tx_cache(struct uarte_nrfx_data *data)
    5a4a:	4603      	mov	r3, r0
	if (!remaining) {
    5a4c:	d00c      	beq.n	5a68 <setup_tx_cache.isra.0+0x26>
	size_t len = MIN(remaining, sizeof(data->async->tx_cache));
    5a4e:	2a08      	cmp	r2, #8
    5a50:	bf28      	it	cs
    5a52:	2208      	movcs	r2, #8
	data->async->xfer_buf = data->async->tx_cache;
    5a54:	3018      	adds	r0, #24
	data->async->xfer_len = len;
    5a56:	f840 2c04 	str.w	r2, [r0, #-4]
	data->async->xfer_buf = data->async->tx_cache;
    5a5a:	6118      	str	r0, [r3, #16]
	memcpy(data->async->tx_cache, &data->async->tx_buf[data->async->tx_cache_offset], len);
    5a5c:	689b      	ldr	r3, [r3, #8]
    5a5e:	4419      	add	r1, r3
    5a60:	f7ff fd05 	bl	546e <memcpy>
	return true;
    5a64:	2001      	movs	r0, #1
}
    5a66:	bd08      	pop	{r3, pc}
		return false;
    5a68:	4610      	mov	r0, r2
    5a6a:	e7fc      	b.n	5a66 <setup_tx_cache.isra.0+0x24>

00005a6c <is_tx_ready.isra.0>:
	return config->uarte_regs;
    5a6c:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    5a6e:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5a70:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    5a74:	b940      	cbnz	r0, 5a88 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    5a76:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    5a78:	079b      	lsls	r3, r3, #30
    5a7a:	d406      	bmi.n	5a8a <is_tx_ready.isra.0+0x1e>
    5a7c:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    5a80:	3800      	subs	r0, #0
    5a82:	bf18      	it	ne
    5a84:	2001      	movne	r0, #1
    5a86:	4770      	bx	lr
    5a88:	2001      	movs	r0, #1
}
    5a8a:	4770      	bx	lr

00005a8c <start_tx_locked>:
{
    5a8c:	b510      	push	{r4, lr}
    5a8e:	4604      	mov	r4, r0
	if (!is_tx_ready(dev)) {
    5a90:	6840      	ldr	r0, [r0, #4]
    5a92:	f7ff ffeb 	bl	5a6c <is_tx_ready.isra.0>
		data->async->pending_tx = true;
    5a96:	68cb      	ldr	r3, [r1, #12]
	if (!is_tx_ready(dev)) {
    5a98:	b918      	cbnz	r0, 5aa2 <start_tx_locked+0x16>
		data->async->pending_tx = true;
    5a9a:	2201      	movs	r2, #1
    5a9c:	f883 20d4 	strb.w	r2, [r3, #212]	; 0xd4
}
    5aa0:	bd10      	pop	{r4, pc}
		data->async->pending_tx = false;
    5aa2:	2200      	movs	r2, #0
    5aa4:	f883 20d4 	strb.w	r2, [r3, #212]	; 0xd4
		data->async->tx_amount = -1;
    5aa8:	f04f 32ff 	mov.w	r2, #4294967295
		tx_start(dev, data->async->xfer_buf, data->async->xfer_len);
    5aac:	4620      	mov	r0, r4
}
    5aae:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		data->async->tx_amount = -1;
    5ab2:	f8c3 20c4 	str.w	r2, [r3, #196]	; 0xc4
		tx_start(dev, data->async->xfer_buf, data->async->xfer_len);
    5ab6:	e9d3 1204 	ldrd	r1, r2, [r3, #16]
    5aba:	f7ff be9c 	b.w	57f6 <tx_start>

00005abe <rx_timeout>:
{
    5abe:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	return timer->user_data;
    5ac0:	6b45      	ldr	r5, [r0, #52]	; 0x34
	if (data->async->is_in_irq) {
    5ac2:	68eb      	ldr	r3, [r5, #12]
    5ac4:	f893 20d5 	ldrb.w	r2, [r3, #213]	; 0xd5
    5ac8:	f002 07ff 	and.w	r7, r2, #255	; 0xff
    5acc:	2a00      	cmp	r2, #0
    5ace:	d134      	bne.n	5b3a <rx_timeout+0x7c>
    p_reg->INTENCLR = mask;
    5ad0:	2110      	movs	r1, #16
	const struct device *dev = data->dev;
    5ad2:	682e      	ldr	r6, [r5, #0]
	const struct uarte_nrfx_config *cfg = dev->config;
    5ad4:	6870      	ldr	r0, [r6, #4]
	return config->uarte_regs;
    5ad6:	6802      	ldr	r2, [r0, #0]
    5ad8:	f8c2 1308 	str.w	r1, [r2, #776]	; 0x308
	if (HW_RX_COUNTING_ENABLED(data)) {
    5adc:	f893 20d3 	ldrb.w	r2, [r3, #211]	; 0xd3
    5ae0:	b302      	cbz	r2, 5b24 <rx_timeout+0x66>
		read = nrfx_timer_capture(&cfg->timer, 0);
    5ae2:	4639      	mov	r1, r7
    5ae4:	3010      	adds	r0, #16
    5ae6:	f000 fd83 	bl	65f0 <nrfx_timer_capture>
	if (read != data->async->rx_total_byte_cnt) {
    5aea:	68eb      	ldr	r3, [r5, #12]
    5aec:	6f5a      	ldr	r2, [r3, #116]	; 0x74
    5aee:	4282      	cmp	r2, r0
		data->async->rx_timeout_left = data->async->rx_timeout;
    5af0:	bf1e      	ittt	ne
    5af2:	6fda      	ldrne	r2, [r3, #124]	; 0x7c
		data->async->rx_total_byte_cnt = read;
    5af4:	6758      	strne	r0, [r3, #116]	; 0x74
		data->async->rx_timeout_left = data->async->rx_timeout;
    5af6:	f8c3 2084 	strne.w	r2, [r3, #132]	; 0x84
	if (!HW_RX_COUNTING_ENABLED(data) &&
    5afa:	f893 20d3 	ldrb.w	r2, [r3, #211]	; 0xd3
		    - data->async->rx_total_user_byte_cnt;
    5afe:	e9d3 411d 	ldrd	r4, r1, [r3, #116]	; 0x74
    5b02:	1a64      	subs	r4, r4, r1
	if (!HW_RX_COUNTING_ENABLED(data) &&
    5b04:	b922      	cbnz	r2, 5b10 <rx_timeout+0x52>
    5b06:	2c00      	cmp	r4, #0
		len = 0;
    5b08:	bfbc      	itt	lt
    5b0a:	4614      	movlt	r4, r2
		data->async->rx_cnt.cnt = data->async->rx_total_user_byte_cnt;
    5b0c:	f8c3 10c0 	strlt.w	r1, [r3, #192]	; 0xc0
	if (len + data->async->rx_offset > data->async->rx_buf_len) {
    5b10:	e9d3 1219 	ldrd	r1, r2, [r3, #100]	; 0x64
    5b14:	18a0      	adds	r0, r4, r2
    5b16:	4288      	cmp	r0, r1
    5b18:	d910      	bls.n	5b3c <rx_timeout+0x7e>
		len = data->async->rx_buf_len - data->async->rx_offset;
    5b1a:	1a8c      	subs	r4, r1, r2
	if (len > 0) {
    5b1c:	2c00      	cmp	r4, #0
    5b1e:	dd07      	ble.n	5b30 <rx_timeout+0x72>
		clipped = true;
    5b20:	2701      	movs	r7, #1
    5b22:	e011      	b.n	5b48 <rx_timeout+0x8a>
		read = data->async->rx_cnt.cnt;
    5b24:	f8d3 00c0 	ldr.w	r0, [r3, #192]	; 0xc0
    5b28:	e7df      	b.n	5aea <rx_timeout+0x2c>
			data->async->rx_timeout_left -=
    5b2a:	1a52      	subs	r2, r2, r1
    5b2c:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    p_reg->INTENSET = mask;
    5b30:	2210      	movs	r2, #16
	return config->uarte_regs;
    5b32:	6873      	ldr	r3, [r6, #4]
    5b34:	681b      	ldr	r3, [r3, #0]
    5b36:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    5b3a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	if (len > 0) {
    5b3c:	2c00      	cmp	r4, #0
    5b3e:	ddf7      	ble.n	5b30 <rx_timeout+0x72>
				< data->async->rx_timeout_slab)) {
    5b40:	e9d3 1220 	ldrd	r1, r2, [r3, #128]	; 0x80
		if (clipped ||
    5b44:	428a      	cmp	r2, r1
    5b46:	daf0      	bge.n	5b2a <rx_timeout+0x6c>
			notify_uart_rx_rdy(dev, len);
    5b48:	4630      	mov	r0, r6
    5b4a:	4621      	mov	r1, r4
    5b4c:	f7ff fda2 	bl	5694 <notify_uart_rx_rdy>
			data->async->rx_offset += len;
    5b50:	68e8      	ldr	r0, [r5, #12]
    5b52:	6e83      	ldr	r3, [r0, #104]	; 0x68
    5b54:	4423      	add	r3, r4
    5b56:	6683      	str	r3, [r0, #104]	; 0x68
			data->async->rx_total_user_byte_cnt += len;
    5b58:	6f83      	ldr	r3, [r0, #120]	; 0x78
    5b5a:	4423      	add	r3, r4
    5b5c:	6783      	str	r3, [r0, #120]	; 0x78
		if (clipped) {
    5b5e:	2f00      	cmp	r7, #0
    5b60:	d0e6      	beq.n	5b30 <rx_timeout+0x72>
    5b62:	3088      	adds	r0, #136	; 0x88
    5b64:	f000 fef4 	bl	6950 <z_impl_k_timer_stop>
}
    5b68:	e7e2      	b.n	5b30 <rx_timeout+0x72>

00005b6a <uarte_nrfx_tx_abort>:
{
    5b6a:	b538      	push	{r3, r4, r5, lr}
	return config->uarte_regs;
    5b6c:	6843      	ldr	r3, [r0, #4]
    5b6e:	681d      	ldr	r5, [r3, #0]
	if (data->async->tx_buf == NULL) {
    5b70:	6903      	ldr	r3, [r0, #16]
    5b72:	68d8      	ldr	r0, [r3, #12]
    5b74:	6883      	ldr	r3, [r0, #8]
    5b76:	b14b      	cbz	r3, 5b8c <uarte_nrfx_tx_abort+0x22>
	data->async->pending_tx = false;
    5b78:	2400      	movs	r4, #0
    5b7a:	f880 40d4 	strb.w	r4, [r0, #212]	; 0xd4
	z_impl_k_timer_stop(timer);
    5b7e:	3028      	adds	r0, #40	; 0x28
    5b80:	f000 fee6 	bl	6950 <z_impl_k_timer_stop>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5b84:	2301      	movs	r3, #1
	return 0;
    5b86:	4620      	mov	r0, r4
    5b88:	60eb      	str	r3, [r5, #12]
}
    5b8a:	bd38      	pop	{r3, r4, r5, pc}
		return -EFAULT;
    5b8c:	f06f 000d 	mvn.w	r0, #13
    5b90:	e7fb      	b.n	5b8a <uarte_nrfx_tx_abort+0x20>

00005b92 <tx_timeout>:
	(void) uarte_nrfx_tx_abort(data->dev);
    5b92:	6b43      	ldr	r3, [r0, #52]	; 0x34
    5b94:	6818      	ldr	r0, [r3, #0]
    5b96:	f7ff bfe8 	b.w	5b6a <uarte_nrfx_tx_abort>

00005b9a <api_callback_set>:
	return dev->data;
    5b9a:	6903      	ldr	r3, [r0, #16]
}
    5b9c:	2000      	movs	r0, #0
	data->user_data = user_data;
    5b9e:	e9c3 1221 	strd	r1, r2, [r3, #132]	; 0x84
}
    5ba2:	4770      	bx	lr

00005ba4 <user_callback>:
	return dev->data;
    5ba4:	6902      	ldr	r2, [r0, #16]
	if (data->user_callback) {
    5ba6:	f8d2 3084 	ldr.w	r3, [r2, #132]	; 0x84
    5baa:	b113      	cbz	r3, 5bb2 <user_callback+0xe>
		data->user_callback(dev, evt, data->user_data);
    5bac:	f8d2 2088 	ldr.w	r2, [r2, #136]	; 0x88
    5bb0:	4718      	bx	r3
}
    5bb2:	4770      	bx	lr

00005bb4 <api_irq_tx_enable>:
	data->int_driven.tx_enabled = true;
    5bb4:	2201      	movs	r2, #1
	return dev->data;
    5bb6:	6903      	ldr	r3, [r0, #16]
	data->int_driven.tx_enabled = true;
    5bb8:	f883 21b4 	strb.w	r2, [r3, #436]	; 0x1b4
	if (data->tx_buf == NULL) {
    5bbc:	6eda      	ldr	r2, [r3, #108]	; 0x6c
    5bbe:	b912      	cbnz	r2, 5bc6 <api_irq_tx_enable+0x12>
		data->int_driven.callback(dev, data->int_driven.user_data);
    5bc0:	e9d3 2128 	ldrd	r2, r1, [r3, #160]	; 0xa0
    5bc4:	4710      	bx	r2
}
    5bc6:	4770      	bx	lr

00005bc8 <api_irq_tx_disable>:
	data->int_driven.tx_enabled = false;
    5bc8:	2200      	movs	r2, #0
    5bca:	6903      	ldr	r3, [r0, #16]
    5bcc:	f883 21b4 	strb.w	r2, [r3, #436]	; 0x1b4
}
    5bd0:	4770      	bx	lr

00005bd2 <api_irq_tx_ready>:
	return dev->data;
    5bd2:	6903      	ldr	r3, [r0, #16]
	return data->int_driven.tx_enabled && (data->tx_buf == NULL);
    5bd4:	f893 01b4 	ldrb.w	r0, [r3, #436]	; 0x1b4
    5bd8:	b118      	cbz	r0, 5be2 <api_irq_tx_ready+0x10>
    5bda:	6ed8      	ldr	r0, [r3, #108]	; 0x6c
    5bdc:	fab0 f080 	clz	r0, r0
    5be0:	0940      	lsrs	r0, r0, #5
}
    5be2:	4770      	bx	lr

00005be4 <api_irq_callback_set>:
	return dev->data;
    5be4:	6903      	ldr	r3, [r0, #16]
	data->int_driven.user_data = user_data;
    5be6:	e9c3 1228 	strd	r1, r2, [r3, #160]	; 0xa0
}
    5bea:	4770      	bx	lr

00005bec <api_irq_rx_disable>:
	data->int_driven.rx_enabled = false;
    5bec:	2200      	movs	r2, #0
    5bee:	6903      	ldr	r3, [r0, #16]
    5bf0:	f883 21b5 	strb.w	r2, [r3, #437]	; 0x1b5
}
    5bf4:	4770      	bx	lr

00005bf6 <api_irq_rx_ready>:
	return dev->data;
    5bf6:	6903      	ldr	r3, [r0, #16]
	return data->int_driven.rx_enabled &&
    5bf8:	f893 01b5 	ldrb.w	r0, [r3, #437]	; 0x1b5
    5bfc:	b120      	cbz	r0, 5c08 <api_irq_rx_ready+0x12>
    5bfe:	e9d3 306b 	ldrd	r3, r0, [r3, #428]	; 0x1ac
    5c02:	1ac0      	subs	r0, r0, r3
    5c04:	bf18      	it	ne
    5c06:	2001      	movne	r0, #1
}
    5c08:	4770      	bx	lr

00005c0a <api_irq_tx_complete>:
	return api_irq_tx_ready(dev);
    5c0a:	f7ff bfe2 	b.w	5bd2 <api_irq_tx_ready>

00005c0e <api_irq_err_enable>:
	data->int_driven.err_enabled = true;
    5c0e:	2201      	movs	r2, #1
    5c10:	6903      	ldr	r3, [r0, #16]
    5c12:	f883 21b6 	strb.w	r2, [r3, #438]	; 0x1b6
}
    5c16:	4770      	bx	lr

00005c18 <api_irq_err_disable>:
	data->int_driven.err_enabled = false;
    5c18:	2200      	movs	r2, #0
    5c1a:	6903      	ldr	r3, [r0, #16]
    5c1c:	f883 21b6 	strb.w	r2, [r3, #438]	; 0x1b6
}
    5c20:	4770      	bx	lr

00005c22 <api_irq_update>:
}
    5c22:	2001      	movs	r0, #1
    5c24:	4770      	bx	lr

00005c26 <api_configure>:

static int api_configure(const struct device *dev, const struct uart_config *cfg)
{
	const struct lpuart_data *data = get_dev_data(dev);

	if (cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
    5c26:	79ca      	ldrb	r2, [r1, #7]
	return dev->data;
    5c28:	6903      	ldr	r3, [r0, #16]
	if (cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
    5c2a:	b922      	cbnz	r2, 5c36 <api_configure+0x10>
		return -ENOTSUP;
	}

	return uart_configure(data->uart, cfg);
    5c2c:	6818      	ldr	r0, [r3, #0]
	if (api->configure == NULL) {
    5c2e:	6883      	ldr	r3, [r0, #8]
    5c30:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    5c32:	b11b      	cbz	r3, 5c3c <api_configure+0x16>
	return api->configure(dev, cfg);
    5c34:	4718      	bx	r3
		return -ENOTSUP;
    5c36:	f06f 0085 	mvn.w	r0, #133	; 0x85
    5c3a:	4770      	bx	lr
		return -ENOSYS;
    5c3c:	f06f 0057 	mvn.w	r0, #87	; 0x57
}
    5c40:	4770      	bx	lr

00005c42 <api_config_get>:

static int api_config_get(const struct device *dev, struct uart_config *cfg)
{
	const struct lpuart_data *data = get_dev_data(dev);

	return uart_config_get(data->uart, cfg);
    5c42:	6903      	ldr	r3, [r0, #16]
    5c44:	6818      	ldr	r0, [r3, #0]
	if (api->config_get == NULL) {
    5c46:	6883      	ldr	r3, [r0, #8]
    5c48:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    5c4a:	b103      	cbz	r3, 5c4e <api_config_get+0xc>
	return api->config_get(dev, cfg);
    5c4c:	4718      	bx	r3
}
    5c4e:	f06f 0057 	mvn.w	r0, #87	; 0x57
    5c52:	4770      	bx	lr

00005c54 <api_fifo_read>:
{
    5c54:	b538      	push	{r3, r4, r5, lr}
    5c56:	4603      	mov	r3, r0
	return dev->data;
    5c58:	691d      	ldr	r5, [r3, #16]
{
    5c5a:	4608      	mov	r0, r1
	return data->int_driven.rxlen - data->int_driven.rxrd;
    5c5c:	e9d5 436b 	ldrd	r4, r3, [r5, #428]	; 0x1ac
	if (available) {
    5c60:	1ae4      	subs	r4, r4, r3
    5c62:	d00d      	beq.n	5c80 <api_fifo_read+0x2c>
		cpylen = MIN(available, size);
    5c64:	4294      	cmp	r4, r2
    5c66:	bf28      	it	cs
    5c68:	4614      	movcs	r4, r2
		       &data->int_driven.rxbuf[data->int_driven.rxrd],
    5c6a:	f503 7396 	add.w	r3, r3, #300	; 0x12c
		memcpy(rx_data,
    5c6e:	18e9      	adds	r1, r5, r3
    5c70:	4622      	mov	r2, r4
    5c72:	f7ff fbfc 	bl	546e <memcpy>
		data->int_driven.rxrd += cpylen;
    5c76:	f8d5 31b0 	ldr.w	r3, [r5, #432]	; 0x1b0
    5c7a:	4423      	add	r3, r4
    5c7c:	f8c5 31b0 	str.w	r3, [r5, #432]	; 0x1b0
}
    5c80:	4620      	mov	r0, r4
    5c82:	bd38      	pop	{r3, r4, r5, pc}

00005c84 <api_poll_in>:
	return api_fifo_read(dev, p_char, 1) ? 0 : -1;
    5c84:	2201      	movs	r2, #1
{
    5c86:	b508      	push	{r3, lr}
	return api_fifo_read(dev, p_char, 1) ? 0 : -1;
    5c88:	f7ff ffe4 	bl	5c54 <api_fifo_read>
    5c8c:	fab0 f080 	clz	r0, r0
    5c90:	0940      	lsrs	r0, r0, #5
}
    5c92:	4240      	negs	r0, r0
    5c94:	bd08      	pop	{r3, pc}

00005c96 <api_irq_is_pending>:
{
    5c96:	b508      	push	{r3, lr}
    5c98:	4602      	mov	r2, r0
	return api_irq_rx_ready(dev) || api_irq_tx_ready(dev);
    5c9a:	f7ff ffac 	bl	5bf6 <api_irq_rx_ready>
    5c9e:	b930      	cbnz	r0, 5cae <api_irq_is_pending+0x18>
    5ca0:	4610      	mov	r0, r2
    5ca2:	f7ff ff96 	bl	5bd2 <api_irq_tx_ready>
    5ca6:	3800      	subs	r0, #0
    5ca8:	bf18      	it	ne
    5caa:	2001      	movne	r0, #1
}
    5cac:	bd08      	pop	{r3, pc}
	return api_irq_rx_ready(dev) || api_irq_tx_ready(dev);
    5cae:	2001      	movs	r0, #1
    5cb0:	e7fc      	b.n	5cac <api_irq_is_pending+0x16>

00005cb2 <api_rx_buf_rsp>:
{
    5cb2:	b570      	push	{r4, r5, r6, lr}
	return dev->data;
    5cb4:	6900      	ldr	r0, [r0, #16]
	if (data->rx_state == RX_TO_IDLE || data->rx_state == RX_BLOCKED) {
    5cb6:	f890 508c 	ldrb.w	r5, [r0, #140]	; 0x8c
    5cba:	3d04      	subs	r5, #4
    5cbc:	2d01      	cmp	r5, #1
    5cbe:	d80c      	bhi.n	5cda <api_rx_buf_rsp+0x28>
		if (data->rx_req) {
    5cc0:	f890 308d 	ldrb.w	r3, [r0, #141]	; 0x8d
		data->rx_len = len;
    5cc4:	e9c0 121e 	strd	r1, r2, [r0, #120]	; 0x78
		if (data->rx_req) {
    5cc8:	b11b      	cbz	r3, 5cd2 <api_rx_buf_rsp+0x20>
			start_rx_activation(data);
    5cca:	f7fc febd 	bl	2a48 <start_rx_activation>
}
    5cce:	2000      	movs	r0, #0
    5cd0:	bd70      	pop	{r4, r5, r6, pc}
			data->rx_state = RX_IDLE;
    5cd2:	2301      	movs	r3, #1
    5cd4:	f880 308c 	strb.w	r3, [r0, #140]	; 0x8c
			LOG_DBG("RX: Idle");
    5cd8:	e7f9      	b.n	5cce <api_rx_buf_rsp+0x1c>
	return uart_rx_buf_rsp(data->uart, buf, len);
    5cda:	6800      	ldr	r0, [r0, #0]
}
    5cdc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	return api->rx_buf_rsp(dev, buf, len);
    5ce0:	6883      	ldr	r3, [r0, #8]
    5ce2:	691b      	ldr	r3, [r3, #16]
    5ce4:	4718      	bx	r3

00005ce6 <api_rx_enable>:
{
    5ce6:	b537      	push	{r0, r1, r2, r4, r5, lr}
	return dev->data;
    5ce8:	6904      	ldr	r4, [r0, #16]
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    5cea:	f104 0078 	add.w	r0, r4, #120	; 0x78
    5cee:	e8d0 5fef 	ldaex	r5, [r0]
    5cf2:	2d00      	cmp	r5, #0
    5cf4:	d104      	bne.n	5d00 <api_rx_enable+0x1a>
    5cf6:	e8c0 1fec 	stlex	ip, r1, [r0]
    5cfa:	f1bc 0f00 	cmp.w	ip, #0
    5cfe:	d1f6      	bne.n	5cee <api_rx_enable+0x8>
	if (atomic_ptr_cas((atomic_ptr_t *)&data->rx_buf, NULL, buf) == false) {
    5d00:	d128      	bne.n	5d54 <api_rx_enable+0x6e>
	data->rx_timeout = timeout;
    5d02:	e9c4 231f 	strd	r2, r3, [r4, #124]	; 0x7c
	data->rx_state = RX_IDLE;
    5d06:	2301      	movs	r3, #1
    5d08:	f884 308c 	strb.w	r3, [r4, #140]	; 0x8c
	__asm__ volatile(
    5d0c:	f04f 0320 	mov.w	r3, #32
    5d10:	f3ef 8111 	mrs	r1, BASEPRI
    5d14:	f383 8812 	msr	BASEPRI_MAX, r3
    5d18:	f3bf 8f6f 	isb	sy
	pending_rx = nrf_gpio_pin_read(data->rdy_pin.nrf_pin)
    5d1c:	f894 3029 	ldrb.w	r3, [r4, #41]	; 0x29
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5d20:	a801      	add	r0, sp, #4
    5d22:	9301      	str	r3, [sp, #4]
    5d24:	f7fc fe80 	bl	2a28 <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    5d28:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    5d2a:	6900      	ldr	r0, [r0, #16]
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    5d2c:	40d8      	lsrs	r0, r3
		     && (data->rx_state == RX_IDLE);
    5d2e:	f010 0001 	ands.w	r0, r0, #1
    5d32:	d004      	beq.n	5d3e <api_rx_enable+0x58>
    5d34:	f894 008c 	ldrb.w	r0, [r4, #140]	; 0x8c
    5d38:	1e43      	subs	r3, r0, #1
    5d3a:	4258      	negs	r0, r3
    5d3c:	4158      	adcs	r0, r3
	__asm__ volatile(
    5d3e:	f381 8811 	msr	BASEPRI, r1
    5d42:	f3bf 8f6f 	isb	sy
	if (pending_rx) {
    5d46:	b118      	cbz	r0, 5d50 <api_rx_enable+0x6a>
		start_rx_activation(data);
    5d48:	4620      	mov	r0, r4
    5d4a:	f7fc fe7d 	bl	2a48 <start_rx_activation>
	return 0;
    5d4e:	2000      	movs	r0, #0
}
    5d50:	b003      	add	sp, #12
    5d52:	bd30      	pop	{r4, r5, pc}
		return -EBUSY;
    5d54:	f06f 000f 	mvn.w	r0, #15
    5d58:	e7fa      	b.n	5d50 <api_rx_enable+0x6a>

00005d5a <int_driven_evt_handler>:
{
    5d5a:	460b      	mov	r3, r1
	switch (evt->type) {
    5d5c:	781a      	ldrb	r2, [r3, #0]
	return dev->data;
    5d5e:	6901      	ldr	r1, [r0, #16]
	switch (evt->type) {
    5d60:	2a06      	cmp	r2, #6
    5d62:	d812      	bhi.n	5d8a <int_driven_evt_handler+0x30>
    5d64:	e8df f002 	tbb	[pc, r2]
    5d68:	120a1104 	.word	0x120a1104
    5d6c:	2111      	.short	0x2111
    5d6e:	1e          	.byte	0x1e
    5d6f:	00          	.byte	0x00
		data->int_driven.txlen = 0;
    5d70:	2300      	movs	r3, #0
    5d72:	f8c1 3128 	str.w	r3, [r1, #296]	; 0x128
		data->int_driven.callback(lpuart, data->int_driven.user_data);
    5d76:	e9d1 3128 	ldrd	r3, r1, [r1, #160]	; 0xa0
    5d7a:	4718      	bx	r3
		data->int_driven.rxlen = evt->data.rx.len;
    5d7c:	68db      	ldr	r3, [r3, #12]
    5d7e:	f8c1 31ac 	str.w	r3, [r1, #428]	; 0x1ac
		call_handler = data->int_driven.rx_enabled;
    5d82:	f891 31b5 	ldrb.w	r3, [r1, #437]	; 0x1b5
	if (call_handler) {
    5d86:	2b00      	cmp	r3, #0
    5d88:	d1f5      	bne.n	5d76 <int_driven_evt_handler+0x1c>
}
    5d8a:	4770      	bx	lr
		if (int_driven_rd_available(data) == 0) {
    5d8c:	e9d1 236b 	ldrd	r2, r3, [r1, #428]	; 0x1ac
    5d90:	429a      	cmp	r2, r3
    5d92:	d1fa      	bne.n	5d8a <int_driven_evt_handler+0x30>
	data->int_driven.rxlen = 0;
    5d94:	2300      	movs	r3, #0
	err = api_rx_buf_rsp(dev, data->int_driven.rxbuf,
    5d96:	2280      	movs	r2, #128	; 0x80
	data->int_driven.rxrd = 0;
    5d98:	e9c1 336b 	strd	r3, r3, [r1, #428]	; 0x1ac
	err = api_rx_buf_rsp(dev, data->int_driven.rxbuf,
    5d9c:	f501 7196 	add.w	r1, r1, #300	; 0x12c
    5da0:	f7ff bf87 	b.w	5cb2 <api_rx_buf_rsp>
		call_handler = data->int_driven.err_enabled;
    5da4:	f891 31b6 	ldrb.w	r3, [r1, #438]	; 0x1b6
		break;
    5da8:	e7ed      	b.n	5d86 <int_driven_evt_handler+0x2c>
		data->int_driven.rxlen = 0;
    5daa:	2300      	movs	r3, #0
		err = api_rx_enable(lpuart, data->int_driven.rxbuf,
    5dac:	2280      	movs	r2, #128	; 0x80
		data->int_driven.rxrd = 0;
    5dae:	e9c1 336b 	strd	r3, r3, [r1, #428]	; 0x1ac
		err = api_rx_enable(lpuart, data->int_driven.rxbuf,
    5db2:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    5db6:	f501 7196 	add.w	r1, r1, #300	; 0x12c
    5dba:	f7ff bf94 	b.w	5ce6 <api_rx_enable>

00005dbe <ctrl_pin_set.part.0>:
static void ctrl_pin_set(const struct lpuart_bidir_gpio *io, bool force)
    5dbe:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5dc0:	4604      	mov	r4, r0
	__asm__ volatile(
    5dc2:	f04f 0320 	mov.w	r3, #32
    5dc6:	f3ef 8111 	mrs	r1, BASEPRI
    5dca:	f383 8812 	msr	BASEPRI_MAX, r3
    5dce:	f3bf 8f6f 	isb	sy
    p_reg->CONFIG[idx] = 0;
    5dd2:	2200      	movs	r2, #0
    5dd4:	7c83      	ldrb	r3, [r0, #18]
    5dd6:	009b      	lsls	r3, r3, #2
    5dd8:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    5ddc:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    5de0:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    5de4:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    5de8:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
	nrf_gpiote_event_configure(NRF_GPIOTE, io->ch, io->nrf_pin,
    5dec:	7c40      	ldrb	r0, [r0, #17]
    5dee:	f422 324f 	bic.w	r2, r2, #211968	; 0x33c00
    5df2:	f422 7240 	bic.w	r2, r2, #768	; 0x300
    5df6:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    5dfa:	f8d3 5510 	ldr.w	r5, [r3, #1296]	; 0x510
    5dfe:	0202      	lsls	r2, r0, #8
    5e00:	f402 527c 	and.w	r2, r2, #16128	; 0x3f00
    5e04:	432a      	orrs	r2, r5
    5e06:	f442 3200 	orr.w	r2, r2, #131072	; 0x20000
    5e0a:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    nrf_gpio_cfg(
    5e0e:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5e10:	a801      	add	r0, sp, #4
    5e12:	f7fc fe09 	bl	2a28 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    5e16:	9b01      	ldr	r3, [sp, #4]
    5e18:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    5e1c:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    5e20:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    5e24:	f043 030c 	orr.w	r3, r3, #12
    reg->PIN_CNF[pin_number] = cnf;
    5e28:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    5e2c:	7ca3      	ldrb	r3, [r4, #18]
    5e2e:	009b      	lsls	r3, r3, #2
    5e30:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    5e34:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    5e38:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    5e3c:	f042 0201 	orr.w	r2, r2, #1
    5e40:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
	__asm__ volatile(
    5e44:	f381 8811 	msr	BASEPRI, r1
    5e48:	f3bf 8f6f 	isb	sy
}
    5e4c:	b003      	add	sp, #12
    5e4e:	bd30      	pop	{r4, r5, pc}

00005e50 <api_tx>:
{
    5e50:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	return dev->data;
    5e52:	6905      	ldr	r5, [r0, #16]
    5e54:	f105 006c 	add.w	r0, r5, #108	; 0x6c
    5e58:	e8d0 4fef 	ldaex	r4, [r0]
    5e5c:	2c00      	cmp	r4, #0
    5e5e:	d103      	bne.n	5e68 <api_tx+0x18>
    5e60:	e8c0 1fe6 	stlex	r6, r1, [r0]
    5e64:	2e00      	cmp	r6, #0
    5e66:	d1f7      	bne.n	5e58 <api_tx+0x8>
	if (!atomic_ptr_cas((atomic_ptr_t *)&data->tx_buf, NULL, (void *)buf)) {
    5e68:	d125      	bne.n	5eb6 <api_tx+0x66>
	data->tx_len = len;
    5e6a:	672a      	str	r2, [r5, #112]	; 0x70
	k_timer_start(&data->tx_timer, SYS_TIMEOUT_MS(timeout), K_NO_WAIT);
    5e6c:	1c5a      	adds	r2, r3, #1
    5e6e:	f105 0630 	add.w	r6, r5, #48	; 0x30
    5e72:	d01c      	beq.n	5eae <api_tx+0x5e>
    5e74:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    5e78:	f240 30e7 	movw	r0, #999	; 0x3e7
    5e7c:	2100      	movs	r1, #0
    5e7e:	ea23 74e3 	bic.w	r4, r3, r3, asr #31
    5e82:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    5e86:	2300      	movs	r3, #0
    5e88:	fbc4 0107 	smlal	r0, r1, r4, r7
    5e8c:	f7fa f962 	bl	154 <__aeabi_uldivmod>
    5e90:	4602      	mov	r2, r0
    5e92:	460b      	mov	r3, r1
	z_impl_k_timer_start(timer, duration, period);
    5e94:	2100      	movs	r1, #0
    5e96:	2000      	movs	r0, #0
    5e98:	e9cd 0100 	strd	r0, r1, [sp]
    5e9c:	4630      	mov	r0, r6
    5e9e:	f7fe ff1f 	bl	4ce0 <z_impl_k_timer_start>
	if (force) {
    5ea2:	1d28      	adds	r0, r5, #4
    5ea4:	f7ff ff8b 	bl	5dbe <ctrl_pin_set.part.0>
	return 0;
    5ea8:	2000      	movs	r0, #0
}
    5eaa:	b003      	add	sp, #12
    5eac:	bdf0      	pop	{r4, r5, r6, r7, pc}
	k_timer_start(&data->tx_timer, SYS_TIMEOUT_MS(timeout), K_NO_WAIT);
    5eae:	f04f 32ff 	mov.w	r2, #4294967295
    5eb2:	4613      	mov	r3, r2
    5eb4:	e7ee      	b.n	5e94 <api_tx+0x44>
		return -EBUSY;
    5eb6:	f06f 000f 	mvn.w	r0, #15
    5eba:	e7f6      	b.n	5eaa <api_tx+0x5a>

00005ebc <api_fifo_fill>:
	size = MIN(size, sizeof(data->int_driven.txbuf));
    5ebc:	2a80      	cmp	r2, #128	; 0x80
    5ebe:	bf28      	it	cs
    5ec0:	2280      	movcs	r2, #128	; 0x80
{
    5ec2:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5ec4:	4607      	mov	r7, r0
	size = MIN(size, sizeof(data->int_driven.txbuf));
    5ec6:	4614      	mov	r4, r2
	return dev->data;
    5ec8:	6905      	ldr	r5, [r0, #16]
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    5eca:	f505 7394 	add.w	r3, r5, #296	; 0x128
    5ece:	e8d3 2fef 	ldaex	r2, [r3]
    5ed2:	2a00      	cmp	r2, #0
    5ed4:	d103      	bne.n	5ede <api_fifo_fill+0x22>
    5ed6:	e8c3 4fe0 	stlex	r0, r4, [r3]
    5eda:	2800      	cmp	r0, #0
    5edc:	d1f7      	bne.n	5ece <api_fifo_fill+0x12>
    5ede:	bf0c      	ite	eq
    5ee0:	2001      	moveq	r0, #1
    5ee2:	2000      	movne	r0, #0
	if (!atomic_cas((atomic_t *)&data->int_driven.txlen, 0, size)) {
    5ee4:	d113      	bne.n	5f0e <api_fifo_fill+0x52>
	memcpy(data->int_driven.txbuf, tx_data, size);
    5ee6:	f105 06a8 	add.w	r6, r5, #168	; 0xa8
    5eea:	4622      	mov	r2, r4
    5eec:	4630      	mov	r0, r6
    5eee:	f7ff fabe 	bl	546e <memcpy>
	err = api_tx(dev, data->int_driven.txbuf,
    5ef2:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    5ef6:	4631      	mov	r1, r6
    5ef8:	4638      	mov	r0, r7
    5efa:	f8d5 2128 	ldr.w	r2, [r5, #296]	; 0x128
    5efe:	f7ff ffa7 	bl	5e50 <api_tx>
	if (err < 0) {
    5f02:	2800      	cmp	r0, #0
		data->int_driven.txlen = 0;
    5f04:	bfb6      	itet	lt
    5f06:	2000      	movlt	r0, #0
	size = MIN(size, sizeof(data->int_driven.txbuf));
    5f08:	4620      	movge	r0, r4
		data->int_driven.txlen = 0;
    5f0a:	f8c5 0128 	strlt.w	r0, [r5, #296]	; 0x128
}
    5f0e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00005f10 <nrf_gpio_cfg_output>:
{
    5f10:	b507      	push	{r0, r1, r2, lr}
    5f12:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5f14:	a801      	add	r0, sp, #4
    5f16:	f7fc fd87 	bl	2a28 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    5f1a:	9b01      	ldr	r3, [sp, #4]
    5f1c:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    5f20:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    5f24:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    5f28:	f043 0303 	orr.w	r3, r3, #3
    reg->PIN_CNF[pin_number] = cnf;
    5f2c:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
}
    5f30:	b003      	add	sp, #12
    5f32:	f85d fb04 	ldr.w	pc, [sp], #4

00005f36 <ctrl_pin_clear>:
{
    5f36:	b507      	push	{r0, r1, r2, lr}
	nrf_gpio_pin_clear(io->nrf_pin);
    5f38:	7c43      	ldrb	r3, [r0, #17]
{
    5f3a:	4601      	mov	r1, r0
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5f3c:	a801      	add	r0, sp, #4
	nrf_gpio_pin_clear(io->nrf_pin);
    5f3e:	9301      	str	r3, [sp, #4]
    5f40:	f7fc fd72 	bl	2a28 <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    5f44:	2301      	movs	r3, #1
    5f46:	9a01      	ldr	r2, [sp, #4]
    5f48:	4093      	lsls	r3, r2
    p_reg->CONFIG[idx] = 0;
    5f4a:	2200      	movs	r2, #0
    p_reg->OUTCLR = clr_mask;
    5f4c:	60c3      	str	r3, [r0, #12]
    5f4e:	7c8b      	ldrb	r3, [r1, #18]
    5f50:	009b      	lsls	r3, r3, #2
    5f52:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    5f56:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    5f5a:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    5f5e:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
	nrf_gpio_cfg_output(io->nrf_pin);
    5f62:	7c48      	ldrb	r0, [r1, #17]
}
    5f64:	b003      	add	sp, #12
    5f66:	f85d eb04 	ldr.w	lr, [sp], #4
	nrf_gpio_cfg_output(io->nrf_pin);
    5f6a:	f7ff bfd1 	b.w	5f10 <nrf_gpio_cfg_output>

00005f6e <rx_hfclk_callback>:
{
    5f6e:	b538      	push	{r3, r4, r5, lr}
    5f70:	460c      	mov	r4, r1
	if (data->rx_buf == NULL) {
    5f72:	f851 1c18 	ldr.w	r1, [r1, #-24]
    5f76:	b1a1      	cbz	r1, 5fa2 <rx_hfclk_callback+0x34>
	err = uart_rx_enable(data->uart, data->rx_buf,
    5f78:	e954 2305 	ldrd	r2, r3, [r4, #-20]
    5f7c:	f854 0c90 	ldr.w	r0, [r4, #-144]
	return api->rx_enable(dev, buf, len, timeout);
    5f80:	6885      	ldr	r5, [r0, #8]
    5f82:	68ed      	ldr	r5, [r5, #12]
    5f84:	47a8      	blx	r5
	ctrl_pin_clear(&data->rdy_pin);
    5f86:	f1a4 0578 	sub.w	r5, r4, #120	; 0x78
    5f8a:	4628      	mov	r0, r5
    5f8c:	f7ff ffd3 	bl	5f36 <ctrl_pin_clear>
	if (force) {
    5f90:	4628      	mov	r0, r5
    5f92:	f7ff ff14 	bl	5dbe <ctrl_pin_set.part.0>
	data->rx_req = false;
    5f96:	2300      	movs	r3, #0
    5f98:	f804 3c03 	strb.w	r3, [r4, #-3]
	data->rx_state = RX_ACTIVE;
    5f9c:	2303      	movs	r3, #3
    5f9e:	f804 3c04 	strb.w	r3, [r4, #-4]
}
    5fa2:	bd38      	pop	{r3, r4, r5, pc}

00005fa4 <ctrl_pin_idle>:
	if (io->req) {
    5fa4:	7cc2      	ldrb	r2, [r0, #19]
{
    5fa6:	b513      	push	{r0, r1, r4, lr}
    5fa8:	4601      	mov	r1, r0
	if (io->req) {
    5faa:	b122      	cbz	r2, 5fb6 <ctrl_pin_idle+0x12>
}
    5fac:	b002      	add	sp, #8
    5fae:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		ctrl_pin_clear(io);
    5fb2:	f7ff bfc0 	b.w	5f36 <ctrl_pin_clear>
    p_reg->CONFIG[idx] = 0;
    5fb6:	7c83      	ldrb	r3, [r0, #18]
    5fb8:	009b      	lsls	r3, r3, #2
    5fba:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    5fbe:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    5fc2:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    5fc6:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    5fca:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
	nrf_gpiote_event_configure(NRF_GPIOTE, io->ch, io->nrf_pin,
    5fce:	7c40      	ldrb	r0, [r0, #17]
    5fd0:	f422 324f 	bic.w	r2, r2, #211968	; 0x33c00
    5fd4:	f422 7240 	bic.w	r2, r2, #768	; 0x300
    5fd8:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    5fdc:	f8d3 4510 	ldr.w	r4, [r3, #1296]	; 0x510
    5fe0:	0202      	lsls	r2, r0, #8
    5fe2:	f402 527c 	and.w	r2, r2, #16128	; 0x3f00
    5fe6:	4322      	orrs	r2, r4
    5fe8:	f442 3280 	orr.w	r2, r2, #65536	; 0x10000
    5fec:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    nrf_gpio_cfg(
    5ff0:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5ff2:	a801      	add	r0, sp, #4
    5ff4:	f7fc fd18 	bl	2a28 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    5ff8:	9b01      	ldr	r3, [sp, #4]
    5ffa:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    5ffe:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    6002:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    reg->PIN_CNF[pin_number] = cnf;
    6006:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    600a:	7c8b      	ldrb	r3, [r1, #18]
    600c:	009b      	lsls	r3, r3, #2
    600e:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    6012:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    6016:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    601a:	f042 0201 	orr.w	r2, r2, #1
    601e:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    6022:	b002      	add	sp, #8
    6024:	bd10      	pop	{r4, pc}

00006026 <uart_callback>:
{
    6026:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	switch (evt->type) {
    6028:	780b      	ldrb	r3, [r1, #0]
{
    602a:	460d      	mov	r5, r1
    602c:	4616      	mov	r6, r2
	return dev->data;
    602e:	6914      	ldr	r4, [r2, #16]
	switch (evt->type) {
    6030:	2b06      	cmp	r3, #6
    6032:	d814      	bhi.n	605e <uart_callback+0x38>
    6034:	e8df f003 	tbb	[pc, r3]
    6038:	14171704 	.word	0x14171704
    603c:	1d17      	.short	0x1d17
    603e:	17          	.byte	0x17
    603f:	00          	.byte	0x00
	ctrl_pin_idle(&data->req_pin);
    6040:	1d20      	adds	r0, r4, #4
		const uint8_t *txbuf = evt->data.tx.buf;
    6042:	684f      	ldr	r7, [r1, #4]
	ctrl_pin_idle(&data->req_pin);
    6044:	f7ff ffae 	bl	5fa4 <ctrl_pin_idle>
	data->tx_buf = NULL;
    6048:	2300      	movs	r3, #0
    604a:	66e3      	str	r3, [r4, #108]	; 0x6c
	data->tx_active = false;
    604c:	f884 3074 	strb.w	r3, [r4, #116]	; 0x74
		if (txbuf == (void *)&data->txbyte) {
    6050:	f104 0368 	add.w	r3, r4, #104	; 0x68
    6054:	429f      	cmp	r7, r3
    6056:	d106      	bne.n	6066 <uart_callback+0x40>
			data->txbyte = -1;
    6058:	f04f 33ff 	mov.w	r3, #4294967295
    605c:	66a3      	str	r3, [r4, #104]	; 0x68
}
    605e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if (data->rx_len < CONFIG_NRF_SW_LPUART_MAX_PACKET_SIZE) {
    6060:	6fe3      	ldr	r3, [r4, #124]	; 0x7c
    6062:	2b7f      	cmp	r3, #127	; 0x7f
    6064:	d8fb      	bhi.n	605e <uart_callback+0x38>
		user_callback(dev, evt);
    6066:	4629      	mov	r1, r5
    6068:	4630      	mov	r0, r6
}
    606a:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
		user_callback(dev, evt);
    606e:	f7ff bd99 	b.w	5ba4 <user_callback>
		if (data->rx_state == RX_TO_IDLE) {
    6072:	f894 308c 	ldrb.w	r3, [r4, #140]	; 0x8c
    6076:	2b04      	cmp	r3, #4
			data->rx_state = RX_BLOCKED;
    6078:	bf09      	itett	eq
    607a:	2305      	moveq	r3, #5
			data->rx_buf = NULL;
    607c:	2300      	movne	r3, #0
			data->rx_state = RX_BLOCKED;
    607e:	f884 308c 	strbeq.w	r3, [r4, #140]	; 0x8c
			evt->type = UART_RX_BUF_REQUEST;
    6082:	2303      	moveq	r3, #3
			data->rx_buf = NULL;
    6084:	bf16      	itet	ne
    6086:	67a3      	strne	r3, [r4, #120]	; 0x78
			evt->type = UART_RX_BUF_REQUEST;
    6088:	700b      	strbeq	r3, [r1, #0]
			data->rx_state = RX_OFF;
    608a:	f884 308c 	strbne.w	r3, [r4, #140]	; 0x8c
    608e:	e7ea      	b.n	6066 <uart_callback+0x40>

00006090 <api_irq_rx_enable>:
{
    6090:	b538      	push	{r3, r4, r5, lr}
	data->int_driven.rx_enabled = true;
    6092:	2301      	movs	r3, #1
	return dev->data;
    6094:	6904      	ldr	r4, [r0, #16]
{
    6096:	4605      	mov	r5, r0
	data->int_driven.rx_enabled = true;
    6098:	f884 31b5 	strb.w	r3, [r4, #437]	; 0x1b5
	if (int_driven_rd_available(data)) {
    609c:	e9d4 326b 	ldrd	r3, r2, [r4, #428]	; 0x1ac
    60a0:	429a      	cmp	r2, r3
    60a2:	d10e      	bne.n	60c2 <api_irq_rx_enable+0x32>
	if (!int_driven_rd_available(data) && data->rx_state == RX_BLOCKED) {
    60a4:	f894 308c 	ldrb.w	r3, [r4, #140]	; 0x8c
    60a8:	2b05      	cmp	r3, #5
    60aa:	d111      	bne.n	60d0 <api_irq_rx_enable+0x40>
	data->int_driven.rxlen = 0;
    60ac:	2300      	movs	r3, #0
	err = api_rx_buf_rsp(dev, data->int_driven.rxbuf,
    60ae:	4628      	mov	r0, r5
	data->int_driven.rxrd = 0;
    60b0:	e9c4 336b 	strd	r3, r3, [r4, #428]	; 0x1ac
	err = api_rx_buf_rsp(dev, data->int_driven.rxbuf,
    60b4:	f504 7196 	add.w	r1, r4, #300	; 0x12c
    60b8:	2280      	movs	r2, #128	; 0x80
}
    60ba:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	err = api_rx_buf_rsp(dev, data->int_driven.rxbuf,
    60be:	f7ff bdf8 	b.w	5cb2 <api_rx_buf_rsp>
		data->int_driven.callback(dev, data->int_driven.user_data);
    60c2:	e9d4 3128 	ldrd	r3, r1, [r4, #160]	; 0xa0
    60c6:	4798      	blx	r3
	if (!int_driven_rd_available(data) && data->rx_state == RX_BLOCKED) {
    60c8:	e9d4 236b 	ldrd	r2, r3, [r4, #428]	; 0x1ac
    60cc:	429a      	cmp	r2, r3
    60ce:	d0e9      	beq.n	60a4 <api_irq_rx_enable+0x14>
}
    60d0:	bd38      	pop	{r3, r4, r5, pc}

000060d2 <tx_timeout>:
{
    60d2:	b5f0      	push	{r4, r5, r6, r7, lr}
    60d4:	b087      	sub	sp, #28
    60d6:	6b46      	ldr	r6, [r0, #52]	; 0x34
	return dev->data;
    60d8:	6934      	ldr	r4, [r6, #16]
	if (data->tx_active) {
    60da:	f894 5074 	ldrb.w	r5, [r4, #116]	; 0x74
    60de:	b135      	cbz	r5, 60ee <tx_timeout+0x1c>
		err = uart_tx_abort(data->uart);
    60e0:	6820      	ldr	r0, [r4, #0]
	return api->tx_abort(dev);
    60e2:	6883      	ldr	r3, [r0, #8]
    60e4:	689b      	ldr	r3, [r3, #8]
}
    60e6:	b007      	add	sp, #28
    60e8:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
    60ec:	4718      	bx	r3
	const uint8_t *txbuf = data->tx_buf;
    60ee:	6ee7      	ldr	r7, [r4, #108]	; 0x6c
	ctrl_pin_idle(&data->req_pin);
    60f0:	1d20      	adds	r0, r4, #4
    60f2:	f7ff ff57 	bl	5fa4 <ctrl_pin_idle>
	if (txbuf == (void *)&data->txbyte) {
    60f6:	f104 0368 	add.w	r3, r4, #104	; 0x68
    60fa:	429f      	cmp	r7, r3
	data->tx_buf = NULL;
    60fc:	66e5      	str	r5, [r4, #108]	; 0x6c
	data->tx_active = false;
    60fe:	f884 5074 	strb.w	r5, [r4, #116]	; 0x74
	if (txbuf == (void *)&data->txbyte) {
    6102:	d104      	bne.n	610e <tx_timeout+0x3c>
		data->txbyte = -1;
    6104:	f04f 33ff 	mov.w	r3, #4294967295
    6108:	66a3      	str	r3, [r4, #104]	; 0x68
}
    610a:	b007      	add	sp, #28
    610c:	bdf0      	pop	{r4, r5, r6, r7, pc}
		struct uart_event evt = {
    610e:	4629      	mov	r1, r5
    6110:	2214      	movs	r2, #20
    6112:	a801      	add	r0, sp, #4
    6114:	f7ff f9b6 	bl	5484 <memset>
    6118:	2301      	movs	r3, #1
		user_callback(dev, &evt);
    611a:	4630      	mov	r0, r6
    611c:	a901      	add	r1, sp, #4
		struct uart_event evt = {
    611e:	f88d 3004 	strb.w	r3, [sp, #4]
    6122:	9702      	str	r7, [sp, #8]
		user_callback(dev, &evt);
    6124:	f7ff fd3e 	bl	5ba4 <user_callback>
    6128:	e7ef      	b.n	610a <tx_timeout+0x38>

0000612a <api_rx_disable>:
	data->rx_state = RX_TO_OFF;
    612a:	2206      	movs	r2, #6
	return dev->data;
    612c:	6903      	ldr	r3, [r0, #16]
	return uart_rx_disable(data->uart);
    612e:	6818      	ldr	r0, [r3, #0]
	data->rx_state = RX_TO_OFF;
    6130:	f883 208c 	strb.w	r2, [r3, #140]	; 0x8c
	return api->rx_disable(dev);
    6134:	6883      	ldr	r3, [r0, #8]
    6136:	695b      	ldr	r3, [r3, #20]
    6138:	4718      	bx	r3

0000613a <api_tx_abort>:
{
    613a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return dev->data;
    613e:	6904      	ldr	r4, [r0, #16]
{
    6140:	4605      	mov	r5, r0
	const uint8_t *buf = data->tx_buf;
    6142:	6ee7      	ldr	r7, [r4, #108]	; 0x6c
{
    6144:	b086      	sub	sp, #24
	if (data->tx_buf == NULL) {
    6146:	b37f      	cbz	r7, 61a8 <api_tx_abort+0x6e>
	z_impl_k_timer_stop(timer);
    6148:	f104 0030 	add.w	r0, r4, #48	; 0x30
    614c:	f000 fc00 	bl	6950 <z_impl_k_timer_stop>
	__asm__ volatile(
    6150:	f04f 0320 	mov.w	r3, #32
    6154:	f3ef 8811 	mrs	r8, BASEPRI
    6158:	f383 8812 	msr	BASEPRI_MAX, r3
    615c:	f3bf 8f6f 	isb	sy
	data->tx_buf = NULL;
    6160:	2600      	movs	r6, #0
	ctrl_pin_idle(&data->req_pin);
    6162:	1d20      	adds	r0, r4, #4
    6164:	f7ff ff1e 	bl	5fa4 <ctrl_pin_idle>
	data->tx_buf = NULL;
    6168:	66e6      	str	r6, [r4, #108]	; 0x6c
	data->tx_active = false;
    616a:	f884 6074 	strb.w	r6, [r4, #116]	; 0x74
	__asm__ volatile(
    616e:	f388 8811 	msr	BASEPRI, r8
    6172:	f3bf 8f6f 	isb	sy
	err = uart_tx_abort(data->uart);
    6176:	6820      	ldr	r0, [r4, #0]
	return api->tx_abort(dev);
    6178:	6883      	ldr	r3, [r0, #8]
    617a:	689b      	ldr	r3, [r3, #8]
    617c:	4798      	blx	r3
	if (err != -EFAULT) {
    617e:	f110 0f0e 	cmn.w	r0, #14
    6182:	4604      	mov	r4, r0
    6184:	d10c      	bne.n	61a0 <api_tx_abort+0x66>
	struct uart_event event = {
    6186:	4631      	mov	r1, r6
    6188:	2214      	movs	r2, #20
    618a:	a801      	add	r0, sp, #4
    618c:	f7ff f97a 	bl	5484 <memset>
    6190:	2301      	movs	r3, #1
	user_callback(dev, &event);
    6192:	4628      	mov	r0, r5
    6194:	a901      	add	r1, sp, #4
	struct uart_event event = {
    6196:	f88d 3004 	strb.w	r3, [sp, #4]
    619a:	9702      	str	r7, [sp, #8]
	user_callback(dev, &event);
    619c:	f7ff fd02 	bl	5ba4 <user_callback>
}
    61a0:	4620      	mov	r0, r4
    61a2:	b006      	add	sp, #24
    61a4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		return -EFAULT;
    61a8:	f06f 040d 	mvn.w	r4, #13
    61ac:	e7f8      	b.n	61a0 <api_tx_abort+0x66>

000061ae <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    61ae:	4770      	bx	lr

000061b0 <pinctrl_lookup_state>:

#include <drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    61b0:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
    61b2:	6843      	ldr	r3, [r0, #4]
    61b4:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    61b6:	7a03      	ldrb	r3, [r0, #8]
    61b8:	f103 5300 	add.w	r3, r3, #536870912	; 0x20000000
    61bc:	3b01      	subs	r3, #1
    61be:	00db      	lsls	r3, r3, #3
    61c0:	6845      	ldr	r5, [r0, #4]
    61c2:	6814      	ldr	r4, [r2, #0]
    61c4:	441d      	add	r5, r3
    61c6:	42ac      	cmp	r4, r5
    61c8:	d902      	bls.n	61d0 <pinctrl_lookup_state+0x20>
		}

		(*state)++;
	}

	return -ENOENT;
    61ca:	f06f 0001 	mvn.w	r0, #1
}
    61ce:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
    61d0:	7965      	ldrb	r5, [r4, #5]
    61d2:	428d      	cmp	r5, r1
    61d4:	d002      	beq.n	61dc <pinctrl_lookup_state+0x2c>
		(*state)++;
    61d6:	3408      	adds	r4, #8
    61d8:	6014      	str	r4, [r2, #0]
    61da:	e7f1      	b.n	61c0 <pinctrl_lookup_state+0x10>
			return 0;
    61dc:	2000      	movs	r0, #0
    61de:	e7f6      	b.n	61ce <pinctrl_lookup_state+0x1e>

000061e0 <nrf_gpio_pin_write>:
    if (value == 0)
    61e0:	b909      	cbnz	r1, 61e6 <nrf_gpio_pin_write+0x6>
        nrf_gpio_pin_clear(pin_number);
    61e2:	f7fc bfe5 	b.w	31b0 <nrf_gpio_pin_clear>
        nrf_gpio_pin_set(pin_number);
    61e6:	f7fd b81b 	b.w	3220 <nrf_gpio_pin_set>

000061ea <pinctrl_configure_pins>:

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    61ea:	b570      	push	{r4, r5, r6, lr}
    61ec:	4615      	mov	r5, r2
    61ee:	4604      	mov	r4, r0
    61f0:	eb00 0681 	add.w	r6, r0, r1, lsl #2
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    61f4:	42a6      	cmp	r6, r4
    61f6:	d101      	bne.n	61fc <pinctrl_configure_pins+0x12>
		default:
			return -ENOTSUP;
		}
	}

	return 0;
    61f8:	2000      	movs	r0, #0
}
    61fa:	bd70      	pop	{r4, r5, r6, pc}
		switch (NRF_GET_FUN(pins[i])) {
    61fc:	6823      	ldr	r3, [r4, #0]
    61fe:	0c1a      	lsrs	r2, r3, #16
    6200:	2a22      	cmp	r2, #34	; 0x22
    6202:	f200 808e 	bhi.w	6322 <pinctrl_configure_pins+0x138>
    6206:	e8df f002 	tbb	[pc, r2]
    620a:	1d12      	.short	0x1d12
    620c:	39294324 	.word	0x39294324
    6210:	8c8c8c43 	.word	0x8c8c8c43
    6214:	8c4d488c 	.word	0x8c4d488c
    6218:	8c8c8c8c 	.word	0x8c8c8c8c
    621c:	8c8c8c8c 	.word	0x8c8c8c8c
    6220:	68635e52 	.word	0x68635e52
    6224:	6d8c8c8c 	.word	0x6d8c8c8c
    6228:	827d7873 	.word	0x827d7873
    622c:	87          	.byte	0x87
    622d:	00          	.byte	0x00
			NRF_PSEL_UART(reg, TXD) = NRF_GET_PIN(pins[i]);
    622e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6232:	f8c5 350c 	str.w	r3, [r5, #1292]	; 0x50c
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 1);
    6236:	6820      	ldr	r0, [r4, #0]
    6238:	f000 003f 	and.w	r0, r0, #63	; 0x3f
    623c:	f7fc fff0 	bl	3220 <nrf_gpio_pin_set>
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6240:	2201      	movs	r2, #1
    6242:	e015      	b.n	6270 <pinctrl_configure_pins+0x86>
			NRF_PSEL_UART(reg, RXD) = NRF_GET_PIN(pins[i]);
    6244:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6248:	f8c5 3514 	str.w	r3, [r5, #1300]	; 0x514
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    624c:	2200      	movs	r2, #0
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    624e:	2100      	movs	r1, #0
    6250:	e00f      	b.n	6272 <pinctrl_configure_pins+0x88>
			NRF_PSEL_UART(reg, RTS) = NRF_GET_PIN(pins[i]);
    6252:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6256:	f8c5 3508 	str.w	r3, [r5, #1288]	; 0x508
    625a:	e7ec      	b.n	6236 <pinctrl_configure_pins+0x4c>
			NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
    625c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6260:	f8c5 3508 	str.w	r3, [r5, #1288]	; 0x508
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
    6264:	6820      	ldr	r0, [r4, #0]
        nrf_gpio_pin_clear(pin_number);
    6266:	f000 003f 	and.w	r0, r0, #63	; 0x3f
    626a:	f7fc ffa1 	bl	31b0 <nrf_gpio_pin_clear>
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    626e:	2200      	movs	r2, #0
    6270:	2101      	movs	r1, #1
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6272:	6820      	ldr	r0, [r4, #0]
    6274:	f7fc ffac 	bl	31d0 <nrf_pin_configure>
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    6278:	3404      	adds	r4, #4
    627a:	e7bb      	b.n	61f4 <pinctrl_configure_pins+0xa>
			NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
    627c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6280:	f8c5 350c 	str.w	r3, [r5, #1292]	; 0x50c
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
    6284:	6820      	ldr	r0, [r4, #0]
    6286:	f000 003f 	and.w	r0, r0, #63	; 0x3f
    628a:	f7fc ff91 	bl	31b0 <nrf_gpio_pin_clear>
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    628e:	e7d7      	b.n	6240 <pinctrl_configure_pins+0x56>
			NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
    6290:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6294:	f8c5 3510 	str.w	r3, [r5, #1296]	; 0x510
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6298:	e7d8      	b.n	624c <pinctrl_configure_pins+0x62>
			NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
    629a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    629e:	f8c5 3508 	str.w	r3, [r5, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    62a2:	e7d3      	b.n	624c <pinctrl_configure_pins+0x62>
			NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
    62a4:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62a8:	f8c5 350c 	str.w	r3, [r5, #1292]	; 0x50c
    62ac:	e7ce      	b.n	624c <pinctrl_configure_pins+0x62>
			NRF_PSEL_PWM(reg, OUT[0]) = NRF_GET_PIN(pins[i]);
    62ae:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62b2:	f8c5 3560 	str.w	r3, [r5, #1376]	; 0x560
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    62b6:	6820      	ldr	r0, [r4, #0]
    62b8:	f3c0 3140 	ubfx	r1, r0, #13, #1
    62bc:	f000 003f 	and.w	r0, r0, #63	; 0x3f
    62c0:	f7ff ff8e 	bl	61e0 <nrf_gpio_pin_write>
    62c4:	e7bc      	b.n	6240 <pinctrl_configure_pins+0x56>
			NRF_PSEL_PWM(reg, OUT[1]) = NRF_GET_PIN(pins[i]);
    62c6:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62ca:	f8c5 3564 	str.w	r3, [r5, #1380]	; 0x564
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    62ce:	e7f2      	b.n	62b6 <pinctrl_configure_pins+0xcc>
			NRF_PSEL_PWM(reg, OUT[2]) = NRF_GET_PIN(pins[i]);
    62d0:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62d4:	f8c5 3568 	str.w	r3, [r5, #1384]	; 0x568
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    62d8:	e7ed      	b.n	62b6 <pinctrl_configure_pins+0xcc>
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
    62da:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62de:	f8c5 356c 	str.w	r3, [r5, #1388]	; 0x56c
    62e2:	e7e8      	b.n	62b6 <pinctrl_configure_pins+0xcc>
			NRF_PSEL_QSPI(reg, SCK) = NRF_GET_PIN(pins[i]);
    62e4:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62e8:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    62ec:	2201      	movs	r2, #1
    62ee:	e7ae      	b.n	624e <pinctrl_configure_pins+0x64>
			NRF_PSEL_QSPI(reg, CSN) = NRF_GET_PIN(pins[i]);
    62f0:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62f4:	f8c5 3528 	str.w	r3, [r5, #1320]	; 0x528
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    62f8:	e7f8      	b.n	62ec <pinctrl_configure_pins+0x102>
			NRF_PSEL_QSPI(reg, IO0) = NRF_GET_PIN(pins[i]);
    62fa:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    62fe:	f8c5 3530 	str.w	r3, [r5, #1328]	; 0x530
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6302:	e7f3      	b.n	62ec <pinctrl_configure_pins+0x102>
			NRF_PSEL_QSPI(reg, IO1) = NRF_GET_PIN(pins[i]);
    6304:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6308:	f8c5 3534 	str.w	r3, [r5, #1332]	; 0x534
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    630c:	e7ee      	b.n	62ec <pinctrl_configure_pins+0x102>
			NRF_PSEL_QSPI(reg, IO2) = NRF_GET_PIN(pins[i]);
    630e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6312:	f8c5 3538 	str.w	r3, [r5, #1336]	; 0x538
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6316:	e7e9      	b.n	62ec <pinctrl_configure_pins+0x102>
			NRF_PSEL_QSPI(reg, IO3) = NRF_GET_PIN(pins[i]);
    6318:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    631c:	f8c5 353c 	str.w	r3, [r5, #1340]	; 0x53c
    6320:	e7e4      	b.n	62ec <pinctrl_configure_pins+0x102>
		switch (NRF_GET_FUN(pins[i])) {
    6322:	f06f 0085 	mvn.w	r0, #133	; 0x85
    6326:	e768      	b.n	61fa <pinctrl_configure_pins+0x10>

00006328 <k_sys_fatal_error_handler>:
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
    6328:	2000      	movs	r0, #0
{
    632a:	b508      	push	{r3, lr}
		sys_arch_reboot(0);
    632c:	f7fb fa98 	bl	1860 <sys_arch_reboot>

00006330 <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    6330:	f7fe bd28 	b.w	4d84 <nrf_cc3xx_platform_init_no_rng>

00006334 <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    6334:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    6336:	f7fa ff53 	bl	11e0 <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    633a:	f7fb f817 	bl	136c <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    633e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    6342:	f7fe bd1f 	b.w	4d84 <nrf_cc3xx_platform_init_no_rng>

00006346 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    6346:	4700      	bx	r0

00006348 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    6348:	f000 baf2 	b.w	6930 <z_impl_k_busy_wait>

0000634c <nrfx_flag32_is_allocated>:
    return (mask & NRFX_BIT(bitpos)) ? false : true;
    634c:	40c8      	lsrs	r0, r1
    634e:	43c0      	mvns	r0, r0
}
    6350:	f000 0001 	and.w	r0, r0, #1
    6354:	4770      	bx	lr

00006356 <clock_stop>:
{
    6356:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    6358:	4605      	mov	r5, r0
    switch (domain)
    635a:	2803      	cmp	r0, #3
    635c:	d874      	bhi.n	6448 <clock_stop+0xf2>
    635e:	e8df f000 	tbb	[pc, r0]
    6362:	2102      	.short	0x2102
    6364:	3b2d      	.short	0x3b2d
    6366:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    636a:	2202      	movs	r2, #2
    636c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6370:	2200      	movs	r2, #0
    6372:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    6376:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    637a:	2201      	movs	r2, #1
    637c:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    637e:	2301      	movs	r3, #1
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    6380:	429d      	cmp	r5, r3
    6382:	bf18      	it	ne
    6384:	2400      	movne	r4, #0
    6386:	f242 7710 	movw	r7, #10000	; 0x2710
            return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) ==
    638a:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    638e:	f88d 3007 	strb.w	r3, [sp, #7]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    6392:	bf08      	it	eq
    6394:	f10d 0407 	addeq.w	r4, sp, #7
    switch (domain)
    6398:	2d03      	cmp	r5, #3
    639a:	d855      	bhi.n	6448 <clock_stop+0xf2>
    639c:	e8df f005 	tbb	[pc, r5]
    63a0:	4d443b2a 	.word	0x4d443b2a
    p_reg->INTENCLR = mask;
    63a4:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    63a8:	2201      	movs	r2, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    63aa:	2100      	movs	r1, #0
    p_reg->INTENCLR = mask;
    63ac:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    63b0:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    63b4:	f8d3 1100 	ldr.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    63b8:	605a      	str	r2, [r3, #4]
}
    63ba:	e7e0      	b.n	637e <clock_stop+0x28>
    p_reg->INTENCLR = mask;
    63bc:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    63c0:	f44f 7200 	mov.w	r2, #512	; 0x200
    63c4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    63c8:	2200      	movs	r2, #0
    63ca:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    63ce:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    63d2:	2201      	movs	r2, #1
    63d4:	625a      	str	r2, [r3, #36]	; 0x24
}
    63d6:	e7d2      	b.n	637e <clock_stop+0x28>
    p_reg->INTENCLR = mask;
    63d8:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    63dc:	f44f 7280 	mov.w	r2, #256	; 0x100
    63e0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    63e4:	2200      	movs	r2, #0
    63e6:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    63ea:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    63ee:	2201      	movs	r2, #1
    63f0:	61da      	str	r2, [r3, #28]
}
    63f2:	e7c4      	b.n	637e <clock_stop+0x28>
            if (p_clk_src != NULL)
    63f4:	b124      	cbz	r4, 6400 <clock_stop+0xaa>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    63f6:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    63fa:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    63fe:	7023      	strb	r3, [r4, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    6400:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    6404:	03db      	lsls	r3, r3, #15
    6406:	d51f      	bpl.n	6448 <clock_stop+0xf2>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    6408:	b9d4      	cbnz	r4, 6440 <clock_stop+0xea>
    640a:	2001      	movs	r0, #1
    640c:	f7ff ff9c 	bl	6348 <nrfx_busy_wait>
    6410:	3f01      	subs	r7, #1
    6412:	d1c1      	bne.n	6398 <clock_stop+0x42>
    6414:	e018      	b.n	6448 <clock_stop+0xf2>
            if (p_clk_src != NULL)
    6416:	b124      	cbz	r4, 6422 <clock_stop+0xcc>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    6418:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    641c:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    6420:	7023      	strb	r3, [r4, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    6422:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    6426:	e7ed      	b.n	6404 <clock_stop+0xae>
            if (p_clk_src != NULL)
    6428:	b124      	cbz	r4, 6434 <clock_stop+0xde>
                    (nrf_clock_hfclk_t)((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
    642a:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    642e:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    6432:	7023      	strb	r3, [r4, #0]
            if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
    6434:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    6438:	e7e4      	b.n	6404 <clock_stop+0xae>
            return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) ==
    643a:	f8d6 3454 	ldr.w	r3, [r6, #1108]	; 0x454
    643e:	e7e1      	b.n	6404 <clock_stop+0xae>
    6440:	f89d 3007 	ldrb.w	r3, [sp, #7]
    6444:	2b01      	cmp	r3, #1
    6446:	d0e0      	beq.n	640a <clock_stop+0xb4>
}
    6448:	b003      	add	sp, #12
    644a:	bdf0      	pop	{r4, r5, r6, r7, pc}

0000644c <nrfx_clock_enable>:
{
    644c:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    644e:	2005      	movs	r0, #5
    6450:	f7fa ffe4 	bl	141c <arch_irq_is_enabled>
    6454:	b910      	cbnz	r0, 645c <nrfx_clock_enable+0x10>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    6456:	2005      	movs	r0, #5
    6458:	f7fa ffbc 	bl	13d4 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    645c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6460:	2201      	movs	r2, #1
    6462:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}

#if NRF_CLOCK_HAS_HFCLKSRC
NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLKSRC = (uint32_t)(source);
    6466:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
                                   >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos);
}

NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLK192MSRC = (uint32_t)(source);
    646a:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
}
    646e:	bd08      	pop	{r3, pc}

00006470 <nrfx_clock_start>:
{
    6470:	b508      	push	{r3, lr}
    switch (domain)
    6472:	2803      	cmp	r0, #3
    6474:	d81e      	bhi.n	64b4 <nrfx_clock_start+0x44>
    6476:	e8df f000 	tbb	[pc, r0]
    647a:	3302      	.short	0x3302
    647c:	4d3f      	.short	0x4d3f
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    647e:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    6482:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    6486:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    648a:	03c9      	lsls	r1, r1, #15
    648c:	d413      	bmi.n	64b6 <nrfx_clock_start+0x46>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    648e:	f8d2 3414 	ldr.w	r3, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    6492:	07db      	lsls	r3, r3, #31
    6494:	d419      	bmi.n	64ca <nrfx_clock_start+0x5a>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    6496:	2301      	movs	r3, #1
    p_reg->LFCLKSRC = (uint32_t)(source);
    6498:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    649c:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    64a0:	2300      	movs	r3, #0
    64a2:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    64a6:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    64aa:	2302      	movs	r3, #2
    64ac:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    64b0:	2301      	movs	r3, #1
    64b2:	6093      	str	r3, [r2, #8]
}
    64b4:	bd08      	pop	{r3, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    64b6:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    64ba:	2b02      	cmp	r3, #2
    64bc:	d0ec      	beq.n	6498 <nrfx_clock_start+0x28>
    if (!is_correct_clk)
    64be:	2b01      	cmp	r3, #1
    64c0:	d0ea      	beq.n	6498 <nrfx_clock_start+0x28>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    64c2:	2000      	movs	r0, #0
    64c4:	f7ff ff47 	bl	6356 <clock_stop>
    64c8:	e7e5      	b.n	6496 <nrfx_clock_start+0x26>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    64ca:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    64ce:	f003 0303 	and.w	r3, r3, #3
    if (!is_correct_clk)
    64d2:	3b01      	subs	r3, #1
    64d4:	2b01      	cmp	r3, #1
    64d6:	d8f4      	bhi.n	64c2 <nrfx_clock_start+0x52>
    p_reg->INTENSET = mask;
    64d8:	2302      	movs	r3, #2
    64da:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    64de:	e7e9      	b.n	64b4 <nrfx_clock_start+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    64e0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    64e4:	2200      	movs	r2, #0
    64e6:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    64ea:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    64ee:	2201      	movs	r2, #1
    64f0:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    64f4:	601a      	str	r2, [r3, #0]
}
    64f6:	e7dd      	b.n	64b4 <nrfx_clock_start+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    64f8:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    64fc:	2200      	movs	r2, #0
    64fe:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    6502:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    p_reg->INTENSET = mask;
    6506:	f44f 7200 	mov.w	r2, #512	; 0x200
    650a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    650e:	2201      	movs	r2, #1
    6510:	621a      	str	r2, [r3, #32]
}
    6512:	e7cf      	b.n	64b4 <nrfx_clock_start+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6514:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6518:	2200      	movs	r2, #0
    651a:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    651e:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    p_reg->INTENSET = mask;
    6522:	f44f 7280 	mov.w	r2, #256	; 0x100
    6526:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    652a:	2201      	movs	r2, #1
    652c:	619a      	str	r2, [r3, #24]
}
    652e:	e7c1      	b.n	64b4 <nrfx_clock_start+0x44>

00006530 <nrfx_clock_stop>:
    clock_stop(domain);
    6530:	f7ff bf11 	b.w	6356 <clock_stop>

00006534 <nrf_gpio_reconfigure>:
{
    6534:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    6536:	4617      	mov	r7, r2
    6538:	e9dd 4608 	ldrd	r4, r6, [sp, #32]
    653c:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    653e:	a801      	add	r0, sp, #4
{
    6540:	461d      	mov	r5, r3
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6542:	f7fc fffb 	bl	353c <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6546:	9b01      	ldr	r3, [sp, #4]
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    6548:	2f00      	cmp	r7, #0
    654a:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    654e:	bf14      	ite	ne
    6550:	2302      	movne	r3, #2
    6552:	2300      	moveq	r3, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6554:	2900      	cmp	r1, #0
    6556:	bf18      	it	ne
    6558:	f043 0301 	orrne.w	r3, r3, #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    655c:	2d00      	cmp	r5, #0
    655e:	bf14      	ite	ne
    6560:	f04f 0c0c 	movne.w	ip, #12
    6564:	f04f 0c00 	moveq.w	ip, #0
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    6568:	2c00      	cmp	r4, #0
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    656a:	ea43 030c 	orr.w	r3, r3, ip
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    656e:	bf14      	ite	ne
    6570:	f44f 6c70 	movne.w	ip, #3840	; 0xf00
    6574:	f04f 0c00 	moveq.w	ip, #0
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    6578:	2e00      	cmp	r6, #0
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    657a:	ea43 030c 	orr.w	r3, r3, ip
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    657e:	bf14      	ite	ne
    6580:	f44f 3c40 	movne.w	ip, #196608	; 0x30000
    6584:	f04f 0c00 	moveq.w	ip, #0
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6588:	f8d0 2200 	ldr.w	r2, [r0, #512]	; 0x200
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    658c:	ea43 030c 	orr.w	r3, r3, ip
    cnf &= ~to_update;
    6590:	ea22 0303 	bic.w	r3, r2, r3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    6594:	b101      	cbz	r1, 6598 <nrf_gpio_reconfigure+0x64>
    6596:	7809      	ldrb	r1, [r1, #0]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    6598:	b10f      	cbz	r7, 659e <nrf_gpio_reconfigure+0x6a>
    659a:	783f      	ldrb	r7, [r7, #0]
    659c:	007f      	lsls	r7, r7, #1
    659e:	4319      	orrs	r1, r3
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    65a0:	b10d      	cbz	r5, 65a6 <nrf_gpio_reconfigure+0x72>
    65a2:	782d      	ldrb	r5, [r5, #0]
    65a4:	00ad      	lsls	r5, r5, #2
    65a6:	4339      	orrs	r1, r7
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    65a8:	b10c      	cbz	r4, 65ae <nrf_gpio_reconfigure+0x7a>
    65aa:	7822      	ldrb	r2, [r4, #0]
    65ac:	0214      	lsls	r4, r2, #8
    65ae:	430d      	orrs	r5, r1
           ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
    65b0:	b10e      	cbz	r6, 65b6 <nrf_gpio_reconfigure+0x82>
    65b2:	7836      	ldrb	r6, [r6, #0]
    65b4:	0436      	lsls	r6, r6, #16
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    65b6:	432c      	orrs	r4, r5
    65b8:	4334      	orrs	r4, r6
    reg->PIN_CNF[pin_number] = cnf;
    65ba:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
}
    65be:	b003      	add	sp, #12
    65c0:	bdf0      	pop	{r4, r5, r6, r7, pc}

000065c2 <nrf_gpio_cfg_sense_set>:
{
    65c2:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    65c4:	f10d 030f 	add.w	r3, sp, #15
    65c8:	9301      	str	r3, [sp, #4]
    65ca:	2300      	movs	r3, #0
{
    65cc:	f88d 100f 	strb.w	r1, [sp, #15]
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    65d0:	461a      	mov	r2, r3
    65d2:	4619      	mov	r1, r3
    65d4:	9300      	str	r3, [sp, #0]
    65d6:	f7ff ffad 	bl	6534 <nrf_gpio_reconfigure>
}
    65da:	b005      	add	sp, #20
    65dc:	f85d fb04 	ldr.w	pc, [sp], #4

000065e0 <nrfx_timer_clear>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    65e0:	2201      	movs	r2, #1
}

void nrfx_timer_clear(nrfx_timer_t const * p_instance)
{
    NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR);
    65e2:	6803      	ldr	r3, [r0, #0]
    65e4:	60da      	str	r2, [r3, #12]
}
    65e6:	4770      	bx	lr

000065e8 <nrfx_timer_increment>:
    65e8:	2201      	movs	r2, #1
void nrfx_timer_increment(nrfx_timer_t const * p_instance)
{
    NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
    NRFX_ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER);

    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT);
    65ea:	6803      	ldr	r3, [r0, #0]
    65ec:	609a      	str	r2, [r3, #8]
}
    65ee:	4770      	bx	lr

000065f0 <nrfx_timer_capture>:
                            nrf_timer_cc_channel_t cc_channel)
{
    NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
    NRFX_ASSERT(cc_channel < p_instance->cc_channel_count);

    nrf_timer_task_trigger(p_instance->p_reg,
    65f0:	6802      	ldr	r2, [r0, #0]
    65f2:	2001      	movs	r0, #1
    return (uint32_t)p_reg->CC[cc_channel];
}

NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
{
    return (nrf_timer_task_t)NRFX_OFFSETOF(NRF_TIMER_Type, TASKS_CAPTURE[channel]);
    65f4:	008b      	lsls	r3, r1, #2
    65f6:	3340      	adds	r3, #64	; 0x40
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    65f8:	b2db      	uxtb	r3, r3
    65fa:	50d0      	str	r0, [r2, r3]
    return (uint32_t)p_reg->CC[cc_channel];
    65fc:	f501 71a8 	add.w	r1, r1, #336	; 0x150
    6600:	f852 0021 	ldr.w	r0, [r2, r1, lsl #2]
        nrf_timer_capture_task_get(cc_channel));
    return nrf_timer_cc_get(p_instance->p_reg, cc_channel);
}
    6604:	4770      	bx	lr

00006606 <z_device_state_init>:
}
    6606:	4770      	bx	lr

00006608 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    6608:	b138      	cbz	r0, 661a <z_device_is_ready+0x12>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    660a:	68c3      	ldr	r3, [r0, #12]
    660c:	8818      	ldrh	r0, [r3, #0]
    660e:	f3c0 0008 	ubfx	r0, r0, #0, #9
    6612:	f5a0 7380 	sub.w	r3, r0, #256	; 0x100
    6616:	4258      	negs	r0, r3
    6618:	4158      	adcs	r0, r3
}
    661a:	4770      	bx	lr

0000661c <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    661c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    661e:	4605      	mov	r5, r0
    6620:	460e      	mov	r6, r1
	__asm__ volatile(
    6622:	f04f 0320 	mov.w	r3, #32
    6626:	f3ef 8711 	mrs	r7, BASEPRI
    662a:	f383 8812 	msr	BASEPRI_MAX, r3
    662e:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    6632:	f7fe f965 	bl	4900 <z_impl_z_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    6636:	4631      	mov	r1, r6
    6638:	4604      	mov	r4, r0
    663a:	4628      	mov	r0, r5
    663c:	f7ff fe74 	bl	6328 <k_sys_fatal_error_handler>
	__asm__ volatile(
    6640:	f387 8811 	msr	BASEPRI, r7
    6644:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    6648:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    664a:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    664e:	f7fb b94f 	b.w	18f0 <z_impl_k_thread_abort>

00006652 <z_early_memset>:
	(void) memset(dst, c, n);
    6652:	f7fe bf17 	b.w	5484 <memset>

00006656 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    6656:	f7fe bf0a 	b.w	546e <memcpy>

0000665a <k_mem_slab_init>:
{
    665a:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
    665c:	2400      	movs	r4, #0
    665e:	6184      	str	r4, [r0, #24]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    6660:	ea41 0402 	orr.w	r4, r1, r2
    6664:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
    6668:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->buffer = buffer;
    666c:	6101      	str	r1, [r0, #16]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    666e:	d10c      	bne.n	668a <k_mem_slab_init+0x30>
	slab->free_list = NULL;
    6670:	6144      	str	r4, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    6672:	42a3      	cmp	r3, r4
    6674:	d103      	bne.n	667e <k_mem_slab_init+0x24>
	list->tail = (sys_dnode_t *)list;
    6676:	e9c0 0000 	strd	r0, r0, [r0]
}
    667a:	2000      	movs	r0, #0
}
    667c:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
    667e:	6945      	ldr	r5, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    6680:	3401      	adds	r4, #1
		*(char **)p = slab->free_list;
    6682:	600d      	str	r5, [r1, #0]
		slab->free_list = p;
    6684:	6141      	str	r1, [r0, #20]
		p += slab->block_size;
    6686:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
    6688:	e7f3      	b.n	6672 <k_mem_slab_init+0x18>
		return -EINVAL;
    668a:	f06f 0015 	mvn.w	r0, #21
	return rc;
    668e:	e7f5      	b.n	667c <k_mem_slab_init+0x22>

00006690 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    6690:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6692:	4604      	mov	r4, r0
    6694:	460d      	mov	r5, r1
	__asm__ volatile(
    6696:	f04f 0320 	mov.w	r3, #32
    669a:	f3ef 8611 	mrs	r6, BASEPRI
    669e:	f383 8812 	msr	BASEPRI_MAX, r3
    66a2:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    66a6:	6947      	ldr	r7, [r0, #20]
    66a8:	b977      	cbnz	r7, 66c8 <k_mem_slab_free+0x38>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    66aa:	f000 f8e5 	bl	6878 <z_unpend_first_thread>

		if (pending_thread != NULL) {
    66ae:	b158      	cbz	r0, 66c8 <k_mem_slab_free+0x38>
			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    66b0:	682a      	ldr	r2, [r5, #0]
    66b2:	6787      	str	r7, [r0, #120]	; 0x78
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    66b4:	6142      	str	r2, [r0, #20]
			z_ready_thread(pending_thread);
    66b6:	f000 f86e 	bl	6796 <z_ready_thread>
			z_reschedule(&slab->lock, key);
    66ba:	4631      	mov	r1, r6
    66bc:	f104 0008 	add.w	r0, r4, #8
	slab->num_used--;

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    66c0:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
			z_reschedule(&slab->lock, key);
    66c4:	f7fd be70 	b.w	43a8 <z_reschedule>
	**(char ***) mem = slab->free_list;
    66c8:	682b      	ldr	r3, [r5, #0]
    66ca:	6962      	ldr	r2, [r4, #20]
    66cc:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    66ce:	682b      	ldr	r3, [r5, #0]
    66d0:	6163      	str	r3, [r4, #20]
	slab->num_used--;
    66d2:	69a3      	ldr	r3, [r4, #24]
    66d4:	3b01      	subs	r3, #1
    66d6:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    66d8:	f386 8811 	msr	BASEPRI, r6
    66dc:	f3bf 8f6f 	isb	sy
}
    66e0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

000066e2 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    66e2:	f3ef 8005 	mrs	r0, IPSR
}
    66e6:	3800      	subs	r0, #0
    66e8:	bf18      	it	ne
    66ea:	2001      	movne	r0, #1
    66ec:	4770      	bx	lr

000066ee <z_pm_save_idle_exit>:
{
    66ee:	b508      	push	{r3, lr}
	pm_system_resume();
    66f0:	f7fa fc6a 	bl	fc8 <pm_system_resume>
}
    66f4:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    66f8:	f7ff bd59 	b.w	61ae <sys_clock_idle_exit>

000066fc <adjust_owner_prio.isra.0>:
	if (mutex->owner->base.prio != new_prio) {
    66fc:	f990 300e 	ldrsb.w	r3, [r0, #14]
    6700:	428b      	cmp	r3, r1
    6702:	d001      	beq.n	6708 <adjust_owner_prio.isra.0+0xc>
		return z_set_prio(mutex->owner, new_prio);
    6704:	f7fd bfb8 	b.w	4678 <z_set_prio>
}
    6708:	2000      	movs	r0, #0
    670a:	4770      	bx	lr

0000670c <z_impl_k_mutex_init>:
{
    670c:	4603      	mov	r3, r0
	mutex->owner = NULL;
    670e:	2000      	movs	r0, #0
    6710:	e9c3 3300 	strd	r3, r3, [r3]
	mutex->lock_count = 0U;
    6714:	e9c3 0002 	strd	r0, r0, [r3, #8]
}
    6718:	4770      	bx	lr

0000671a <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    671a:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    671e:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    6720:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    6722:	2300      	movs	r3, #0
	node->prev = NULL;
    6724:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    6728:	4770      	bx	lr

0000672a <unpend_thread_no_timeout>:
{
    672a:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    672c:	f7ff fff5 	bl	671a <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    6730:	7b43      	ldrb	r3, [r0, #13]
    6732:	f023 0302 	bic.w	r3, r3, #2
    6736:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    6738:	2300      	movs	r3, #0
    673a:	6083      	str	r3, [r0, #8]
}
    673c:	bd08      	pop	{r3, pc}

0000673e <z_unpend_thread_no_timeout>:
{
    673e:	b508      	push	{r3, lr}
	__asm__ volatile(
    6740:	f04f 0320 	mov.w	r3, #32
    6744:	f3ef 8111 	mrs	r1, BASEPRI
    6748:	f383 8812 	msr	BASEPRI_MAX, r3
    674c:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
    6750:	f7ff ffeb 	bl	672a <unpend_thread_no_timeout>
	__asm__ volatile(
    6754:	f381 8811 	msr	BASEPRI, r1
    6758:	f3bf 8f6f 	isb	sy
}
    675c:	bd08      	pop	{r3, pc}

0000675e <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    675e:	4603      	mov	r3, r0
    6760:	b920      	cbnz	r0, 676c <z_reschedule_irqlock+0xe>
    6762:	f3ef 8205 	mrs	r2, IPSR
	if (resched(key)) {
    6766:	b90a      	cbnz	r2, 676c <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    6768:	f7fa be9c 	b.w	14a4 <arch_swap>
    676c:	f383 8811 	msr	BASEPRI, r3
    6770:	f3bf 8f6f 	isb	sy
}
    6774:	4770      	bx	lr

00006776 <z_reschedule_unlocked>:
	__asm__ volatile(
    6776:	f04f 0320 	mov.w	r3, #32
    677a:	f3ef 8011 	mrs	r0, BASEPRI
    677e:	f383 8812 	msr	BASEPRI_MAX, r3
    6782:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    6786:	f7ff bfea 	b.w	675e <z_reschedule_irqlock>

0000678a <z_priq_dumb_best>:
{
    678a:	4603      	mov	r3, r0
	return list->head == list;
    678c:	6800      	ldr	r0, [r0, #0]
}
    678e:	4283      	cmp	r3, r0
    6790:	bf08      	it	eq
    6792:	2000      	moveq	r0, #0
    6794:	4770      	bx	lr

00006796 <z_ready_thread>:
{
    6796:	b510      	push	{r4, lr}
    6798:	f04f 0320 	mov.w	r3, #32
    679c:	f3ef 8411 	mrs	r4, BASEPRI
    67a0:	f383 8812 	msr	BASEPRI_MAX, r3
    67a4:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    67a8:	f7fd fec0 	bl	452c <ready_thread>
	__asm__ volatile(
    67ac:	f384 8811 	msr	BASEPRI, r4
    67b0:	f3bf 8f6f 	isb	sy
}
    67b4:	bd10      	pop	{r4, pc}

000067b6 <z_thread_timeout>:
{
    67b6:	4601      	mov	r1, r0
    67b8:	b510      	push	{r4, lr}
	__asm__ volatile(
    67ba:	f04f 0320 	mov.w	r3, #32
    67be:	f3ef 8411 	mrs	r4, BASEPRI
    67c2:	f383 8812 	msr	BASEPRI_MAX, r3
    67c6:	f3bf 8f6f 	isb	sy
		if (!killed) {
    67ca:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
    67ce:	f013 0f28 	tst.w	r3, #40	; 0x28
    67d2:	d10d      	bne.n	67f0 <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
    67d4:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    67d8:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
    67da:	b10b      	cbz	r3, 67e0 <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
    67dc:	f7ff ffa5 	bl	672a <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    67e0:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
    67e4:	f023 0314 	bic.w	r3, r3, #20
    67e8:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
    67ec:	f7fd fe9e 	bl	452c <ready_thread>
	__asm__ volatile(
    67f0:	f384 8811 	msr	BASEPRI, r4
    67f4:	f3bf 8f6f 	isb	sy
}
    67f8:	bd10      	pop	{r4, pc}

000067fa <add_to_waitq_locked>:
{
    67fa:	b538      	push	{r3, r4, r5, lr}
    67fc:	4604      	mov	r4, r0
    67fe:	460d      	mov	r5, r1
	unready_thread(thread);
    6800:	f7fd fee8 	bl	45d4 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    6804:	7b63      	ldrb	r3, [r4, #13]
    6806:	f043 0302 	orr.w	r3, r3, #2
    680a:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    680c:	b195      	cbz	r5, 6834 <add_to_waitq_locked+0x3a>
    680e:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    6810:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6812:	429d      	cmp	r5, r3
    6814:	d015      	beq.n	6842 <add_to_waitq_locked+0x48>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6816:	b1a3      	cbz	r3, 6842 <add_to_waitq_locked+0x48>
	int32_t b1 = thread_1->base.prio;
    6818:	f994 100e 	ldrsb.w	r1, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    681c:	f993 200e 	ldrsb.w	r2, [r3, #14]
	if (b1 != b2) {
    6820:	4291      	cmp	r1, r2
    6822:	d008      	beq.n	6836 <add_to_waitq_locked+0x3c>
		return b2 - b1;
    6824:	1a52      	subs	r2, r2, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    6826:	2a00      	cmp	r2, #0
    6828:	dd05      	ble.n	6836 <add_to_waitq_locked+0x3c>
	sys_dnode_t *const prev = successor->prev;
    682a:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    682c:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    6830:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    6832:	605c      	str	r4, [r3, #4]
}
    6834:	bd38      	pop	{r3, r4, r5, pc}
	return (node == list->tail) ? NULL : node->next;
    6836:	686a      	ldr	r2, [r5, #4]
    6838:	4293      	cmp	r3, r2
    683a:	d002      	beq.n	6842 <add_to_waitq_locked+0x48>
    683c:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    683e:	2b00      	cmp	r3, #0
    6840:	d1ec      	bne.n	681c <add_to_waitq_locked+0x22>
	sys_dnode_t *const tail = list->tail;
    6842:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    6844:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    6848:	601c      	str	r4, [r3, #0]
	list->tail = node;
    684a:	606c      	str	r4, [r5, #4]
}
    684c:	e7f2      	b.n	6834 <add_to_waitq_locked+0x3a>

0000684e <z_unpend1_no_timeout>:
{
    684e:	b510      	push	{r4, lr}
	__asm__ volatile(
    6850:	f04f 0320 	mov.w	r3, #32
    6854:	f3ef 8411 	mrs	r4, BASEPRI
    6858:	f383 8812 	msr	BASEPRI_MAX, r3
    685c:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    6860:	f7ff ff93 	bl	678a <z_priq_dumb_best>
		if (thread != NULL) {
    6864:	4601      	mov	r1, r0
    6866:	b108      	cbz	r0, 686c <z_unpend1_no_timeout+0x1e>
			unpend_thread_no_timeout(thread);
    6868:	f7ff ff5f 	bl	672a <unpend_thread_no_timeout>
	__asm__ volatile(
    686c:	f384 8811 	msr	BASEPRI, r4
    6870:	f3bf 8f6f 	isb	sy
}
    6874:	4608      	mov	r0, r1
    6876:	bd10      	pop	{r4, pc}

00006878 <z_unpend_first_thread>:
{
    6878:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    687a:	f04f 0320 	mov.w	r3, #32
    687e:	f3ef 8511 	mrs	r5, BASEPRI
    6882:	f383 8812 	msr	BASEPRI_MAX, r3
    6886:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    688a:	f7ff ff7e 	bl	678a <z_priq_dumb_best>
		if (thread != NULL) {
    688e:	4604      	mov	r4, r0
    6890:	b120      	cbz	r0, 689c <z_unpend_first_thread+0x24>
			unpend_thread_no_timeout(thread);
    6892:	f7ff ff4a 	bl	672a <unpend_thread_no_timeout>
    6896:	3018      	adds	r0, #24
    6898:	f000 f806 	bl	68a8 <z_abort_timeout>
	__asm__ volatile(
    689c:	f385 8811 	msr	BASEPRI, r5
    68a0:	f3bf 8f6f 	isb	sy
}
    68a4:	4620      	mov	r0, r4
    68a6:	bd38      	pop	{r3, r4, r5, pc}

000068a8 <z_abort_timeout>:
{
    68a8:	b510      	push	{r4, lr}
	__asm__ volatile(
    68aa:	f04f 0220 	mov.w	r2, #32
    68ae:	f3ef 8411 	mrs	r4, BASEPRI
    68b2:	f382 8812 	msr	BASEPRI_MAX, r2
    68b6:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    68ba:	6803      	ldr	r3, [r0, #0]
    68bc:	b13b      	cbz	r3, 68ce <z_abort_timeout+0x26>
			remove_timeout(to);
    68be:	f7fe f8c1 	bl	4a44 <remove_timeout>
			ret = 0;
    68c2:	2000      	movs	r0, #0
	__asm__ volatile(
    68c4:	f384 8811 	msr	BASEPRI, r4
    68c8:	f3bf 8f6f 	isb	sy
}
    68cc:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    68ce:	f06f 0015 	mvn.w	r0, #21
    68d2:	e7f7      	b.n	68c4 <z_abort_timeout+0x1c>

000068d4 <z_get_next_timeout_expiry>:
{
    68d4:	b510      	push	{r4, lr}
	__asm__ volatile(
    68d6:	f04f 0320 	mov.w	r3, #32
    68da:	f3ef 8411 	mrs	r4, BASEPRI
    68de:	f383 8812 	msr	BASEPRI_MAX, r3
    68e2:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    68e6:	f7fe f887 	bl	49f8 <next_timeout>
	__asm__ volatile(
    68ea:	f384 8811 	msr	BASEPRI, r4
    68ee:	f3bf 8f6f 	isb	sy
}
    68f2:	bd10      	pop	{r4, pc}

000068f4 <z_set_timeout_expiry>:
{
    68f4:	b570      	push	{r4, r5, r6, lr}
    68f6:	4604      	mov	r4, r0
    68f8:	460d      	mov	r5, r1
	__asm__ volatile(
    68fa:	f04f 0320 	mov.w	r3, #32
    68fe:	f3ef 8611 	mrs	r6, BASEPRI
    6902:	f383 8812 	msr	BASEPRI_MAX, r3
    6906:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    690a:	f7fe f875 	bl	49f8 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    690e:	2801      	cmp	r0, #1
    6910:	dd05      	ble.n	691e <z_set_timeout_expiry+0x2a>
    6912:	42a0      	cmp	r0, r4
    6914:	db03      	blt.n	691e <z_set_timeout_expiry+0x2a>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    6916:	4629      	mov	r1, r5
    6918:	4620      	mov	r0, r4
    691a:	f7fc fc0f 	bl	313c <sys_clock_set_timeout>
	__asm__ volatile(
    691e:	f386 8811 	msr	BASEPRI, r6
    6922:	f3bf 8f6f 	isb	sy
}
    6926:	bd70      	pop	{r4, r5, r6, pc}

00006928 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    6928:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    692a:	f7fe f97b 	bl	4c24 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    692e:	bd08      	pop	{r3, pc}

00006930 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    6930:	b108      	cbz	r0, 6936 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    6932:	f7fa bae7 	b.w	f04 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    6936:	4770      	bx	lr

00006938 <k_timer_init>:
	timer->status = 0U;
    6938:	2300      	movs	r3, #0
	timer->stop_fn = stop_fn;
    693a:	e9c0 1208 	strd	r1, r2, [r0, #32]
	sys_dlist_init(&w->waitq);
    693e:	f100 0218 	add.w	r2, r0, #24
	list->tail = (sys_dnode_t *)list;
    6942:	e9c0 2206 	strd	r2, r2, [r0, #24]
	node->prev = NULL;
    6946:	e9c0 3300 	strd	r3, r3, [r0]
	timer->status = 0U;
    694a:	6303      	str	r3, [r0, #48]	; 0x30
	timer->user_data = NULL;
    694c:	6343      	str	r3, [r0, #52]	; 0x34
}
    694e:	4770      	bx	lr

00006950 <z_impl_k_timer_stop>:
}
#include <syscalls/k_timer_start_mrsh.c>
#endif

void z_impl_k_timer_stop(struct k_timer *timer)
{
    6950:	b510      	push	{r4, lr}
    6952:	4604      	mov	r4, r0
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, stop, timer);

	int inactive = z_abort_timeout(&timer->timeout) != 0;
    6954:	f7ff ffa8 	bl	68a8 <z_abort_timeout>

	if (inactive) {
    6958:	b9b0      	cbnz	r0, 6988 <z_impl_k_timer_stop+0x38>
		return;
	}

	if (timer->stop_fn != NULL) {
    695a:	6a63      	ldr	r3, [r4, #36]	; 0x24
    695c:	b10b      	cbz	r3, 6962 <z_impl_k_timer_stop+0x12>
		timer->stop_fn(timer);
    695e:	4620      	mov	r0, r4
    6960:	4798      	blx	r3
	}

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		struct k_thread *pending_thread = z_unpend1_no_timeout(&timer->wait_q);
    6962:	f104 0018 	add.w	r0, r4, #24
    6966:	f7ff ff72 	bl	684e <z_unpend1_no_timeout>

		if (pending_thread != NULL) {
    696a:	b168      	cbz	r0, 6988 <z_impl_k_timer_stop+0x38>
			z_ready_thread(pending_thread);
    696c:	f7ff ff13 	bl	6796 <z_ready_thread>
	__asm__ volatile(
    6970:	f04f 0320 	mov.w	r3, #32
    6974:	f3ef 8011 	mrs	r0, BASEPRI
    6978:	f383 8812 	msr	BASEPRI_MAX, r3
    697c:	f3bf 8f6f 	isb	sy
			z_reschedule_unlocked();
		}
	}
}
    6980:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	(void) z_reschedule_irqlock(arch_irq_lock());
    6984:	f7ff beeb 	b.w	675e <z_reschedule_irqlock>
    6988:	bd10      	pop	{r4, pc}

0000698a <boot_banner>:
#else
	printk("*** Booting Zephyr OS version %s %s ***\n",
	       KERNEL_VERSION_STRING, BOOT_DELAY_BANNER);
#endif
#endif
}
    698a:	4770      	bx	lr

0000698c <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    698c:	4770      	bx	lr
	...

00006990 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    6990:	f7fc bc78 	b.w	3284 <SystemInit>
