
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
   0:	40 48 00 20 99 13 00 00 1d 5f 00 00 6d 13 00 00     @H. ....._..m...
  10:	6d 13 00 00 6d 13 00 00 6d 13 00 00 00 00 00 00     m...m...m.......
	...
  2c:	c9 10 00 00 6d 13 00 00 00 00 00 00 6d 13 00 00     ....m.......m...
  3c:	6d 13 00 00                                         m...

00000040 <_irq_vector_table>:
  40:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  50:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  60:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  70:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  80:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  90:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  a0:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  b0:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  c0:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  d0:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  e0:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...
  f0:	49 11 00 00 49 11 00 00 49 11 00 00 49 11 00 00     I...I...I...I...

Disassembly of section text:

00000100 <main>:
    return (bool)pin_active;
}
#endif

void main(void)
{
     100:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
}

NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type *        p_reg,
                                                  nrf_wdt_rr_register_t rr_register)
{
    p_reg->RR[rr_register] = NRF_WDT_RR_VALUE;
     102:	4b1f      	ldr	r3, [pc, #124]	; (180 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x13>)
     104:	4a1f      	ldr	r2, [pc, #124]	; (184 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x17>)
     106:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
     10a:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
     10e:	f8c3 2608 	str.w	r2, [r3, #1544]	; 0x608
     112:	f8c3 260c 	str.w	r2, [r3, #1548]	; 0x60c
     116:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
     11a:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
     11e:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
     122:	f8c3 261c 	str.w	r2, [r3, #1564]	; 0x61c
#ifdef CONFIG_MCUBOOT_INDICATION_LED
    /* LED init */
    led_init();
#endif

    os_heap_init();
     126:	f005 f997 	bl	5458 <os_heap_init>

0000012a <FIH_LABEL_FIH_CALL_START_180>:
    rc = boot_console_init();
    int timeout_in_ms = CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT;
    uint32_t start = k_uptime_get_32();
#endif

    FIH_CALL(boot_go, fih_rc, &rsp);
     12a:	a801      	add	r0, sp, #4
     12c:	f000 fbf8 	bl	920 <boot_go>

00000130 <FIH_LABEL_FIH_CALL_END_192>:
        timeout_in_ms = 1;
    }
    boot_serial_check_start(&boot_funcs,timeout_in_ms);
#endif

    if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     130:	4b15      	ldr	r3, [pc, #84]	; (188 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x1b>)
     132:	681b      	ldr	r3, [r3, #0]
     134:	4283      	cmp	r3, r0
     136:	d000      	beq.n	13a <FIH_LABEL_FIH_CALL_END_192+0xa>
        BOOT_LOG_ERR("Unable to find bootable image");

        mcuboot_status_change(MCUBOOT_STATUS_NO_BOOTABLE_IMAGE_FOUND);

        FIH_PANIC;
     138:	e7fe      	b.n	138 <FIH_LABEL_FIH_CALL_END_192+0x8>
/* There is only one instance of MCUBoot */
#define PROTECT_SIZE (PM_MCUBOOT_PRIMARY_ADDRESS - PM_MCUBOOT_ADDRESS)
#define PROTECT_ADDR PM_MCUBOOT_ADDRESS
#endif

    rc = fprotect_area(PROTECT_ADDR, PROTECT_SIZE);
     13a:	f44f 41e0 	mov.w	r1, #28672	; 0x7000
     13e:	2000      	movs	r0, #0
     140:	f006 f95a 	bl	63f8 <fprotect_area>

    if (rc != 0) {
     144:	b100      	cbz	r0, 148 <CONFIG_IDLE_STACK_SIZE+0x8>
        BOOT_LOG_ERR("Protect mcuboot flash failed, cancel startup.");
        while (1)
     146:	e7fe      	b.n	146 <CONFIG_IDLE_STACK_SIZE+0x6>
    rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
     148:	4669      	mov	r1, sp
     14a:	f89d 0008 	ldrb.w	r0, [sp, #8]
     14e:	f005 f971 	bl	5434 <flash_device_base>
    vt = (struct arm_vector_table *)(flash_base +
     152:	9b00      	ldr	r3, [sp, #0]
     154:	9c03      	ldr	r4, [sp, #12]
     156:	441c      	add	r4, r3
                                     rsp->br_hdr->ih_hdr_size);
     158:	9b01      	ldr	r3, [sp, #4]
     15a:	891d      	ldrh	r5, [r3, #8]
    nrf_cleanup_peripheral();
     15c:	f000 fd8c 	bl	c78 <nrf_cleanup_peripheral>
                                     rsp->br_image_off +
     160:	1966      	adds	r6, r4, r5
		:
		: "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	unsigned int tmp;

	__asm__ volatile(
     162:	f04f 0220 	mov.w	r2, #32
     166:	f3ef 8311 	mrs	r3, BASEPRI
     16a:	f382 8812 	msr	BASEPRI_MAX, r2
     16e:	f3bf 8f6f 	isb	sy
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
     172:	5963      	ldr	r3, [r4, r5]
     174:	f383 8808 	msr	MSP, r3
    ((void (*)(void))vt->reset)();
     178:	6873      	ldr	r3, [r6, #4]
     17a:	4798      	blx	r3
    do_boot(&rsp);

    mcuboot_status_change(MCUBOOT_STATUS_BOOT_FAILED);

    BOOT_LOG_ERR("Never should get here");
    while (1)
     17c:	e7fe      	b.n	17c <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0xf>
     17e:	bf00      	nop
     180:	40010000 	.word	0x40010000
     184:	6e524635 	.word	0x6e524635
     188:	20000128 	.word	0x20000128

0000018c <flash_area_sector_from_off>:
    return -EINVAL;
}
#endif

int flash_area_sector_from_off(off_t off, struct flash_sector *sector)
{
     18c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
     18e:	460c      	mov	r4, r1
		union { uintptr_t x; struct flash_pages_info * val; } parm2 = { .val = info };
		return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS);
	}
#endif
	compiler_barrier();
	return z_impl_flash_get_page_info_by_offs(dev, offset, info);
     190:	4601      	mov	r1, r0
     192:	aa01      	add	r2, sp, #4
     194:	4804      	ldr	r0, [pc, #16]	; (1a8 <flash_area_sector_from_off+0x1c>)
     196:	f006 f8a7 	bl	62e8 <z_impl_flash_get_page_info_by_offs>
    int rc;
    struct flash_pages_info page;

    rc = flash_get_page_info_by_offs(flash_dev, off, &page);
    if (rc) {
     19a:	b918      	cbnz	r0, 1a4 <flash_area_sector_from_off+0x18>
        return rc;
    }

    sector->fs_off = page.start_offset;
     19c:	9b01      	ldr	r3, [sp, #4]
     19e:	6023      	str	r3, [r4, #0]
    sector->fs_size = page.size;
     1a0:	9b02      	ldr	r3, [sp, #8]
     1a2:	6063      	str	r3, [r4, #4]

    return rc;
}
     1a4:	b004      	add	sp, #16
     1a6:	bd10      	pop	{r4, pc}
     1a8:	0000685c 	.word	0x0000685c

000001ac <bootutil_img_validate>:
fih_int
bootutil_img_validate(struct enc_key_data *enc_state, int image_index,
                      struct image_header *hdr, const struct flash_area *fap,
                      uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *seed,
                      int seed_len, uint8_t *out_hash)
{
     1ac:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     1b0:	461e      	mov	r6, r3
     1b2:	b0db      	sub	sp, #364	; 0x16c
    uint32_t off;
    uint16_t len;
    uint16_t type;
    int sha256_valid = 0;
#ifdef EXPECTED_SIG_TLV
    fih_int valid_signature = FIH_FAILURE;
     1b4:	4b82      	ldr	r3, [pc, #520]	; (3c0 <FIH_LABEL_FIH_CALL_END_1006+0x20>)
{
     1b6:	f8dd b1a0 	ldr.w	fp, [sp, #416]	; 0x1a0
    fih_int valid_signature = FIH_FAILURE;
     1ba:	f8d3 8000 	ldr.w	r8, [r3]
{
     1be:	e9dd 5766 	ldrd	r5, r7, [sp, #408]	; 0x198
     1c2:	4614      	mov	r4, r2
}

/* Enable and disable cc310 to reduce power consumption */
static inline void cc310_sha256_init(nrf_cc310_bl_hash_context_sha256_t * ctx)
{
    cc310_init();
     1c4:	f000 fd22 	bl	c0c <cc310_init>
    NRF_CRYPTOCELL->ENABLE=1;
     1c8:	4b7e      	ldr	r3, [pc, #504]	; (3c4 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     1ca:	2201      	movs	r2, #1
     1cc:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    nrf_cc310_enable();
    nrf_cc310_bl_hash_sha256_init(ctx);
     1d0:	a83a      	add	r0, sp, #232	; 0xe8
     1d2:	f004 f86f 	bl	42b4 <nrf_cc310_bl_hash_sha256_init>
    if (seed && (seed_len > 0)) {
     1d6:	b135      	cbz	r5, 1e6 <bootutil_img_validate+0x3a>
     1d8:	2f00      	cmp	r7, #0
     1da:	dd04      	ble.n	1e6 <bootutil_img_validate+0x3a>

static inline int bootutil_sha256_update(bootutil_sha256_context *ctx,
                                          const void *data,
                                          uint32_t data_len)
{
    cc310_sha256_update(ctx, data, data_len);
     1dc:	463a      	mov	r2, r7
     1de:	4629      	mov	r1, r5
     1e0:	a83a      	add	r0, sp, #232	; 0xe8
     1e2:	f005 fd28 	bl	5c36 <cc310_sha256_update>
    size += hdr->ih_protect_tlv_size;
     1e6:	8963      	ldrh	r3, [r4, #10]
    size = hdr_size = hdr->ih_hdr_size;
     1e8:	8927      	ldrh	r7, [r4, #8]
     1ea:	441f      	add	r7, r3
    size += hdr->ih_protect_tlv_size;
     1ec:	68e3      	ldr	r3, [r4, #12]
    for (off = 0; off < size; off += blk_sz) {
     1ee:	f04f 0900 	mov.w	r9, #0
    size += hdr->ih_protect_tlv_size;
     1f2:	441f      	add	r7, r3
    for (off = 0; off < size; off += blk_sz) {
     1f4:	454f      	cmp	r7, r9
     1f6:	d825      	bhi.n	244 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x44>
}

static inline void cc310_sha256_finalize(bootutil_sha256_context *ctx,
                                          uint8_t *output)
{
    nrf_cc310_bl_hash_sha256_finalize(ctx,
     1f8:	a90d      	add	r1, sp, #52	; 0x34
     1fa:	a83a      	add	r0, sp, #232	; 0xe8
     1fc:	f004 f8cc 	bl	4398 <nrf_cc310_bl_hash_sha256_finalize>
    NRF_CRYPTOCELL->ENABLE=0;
     200:	4b70      	ldr	r3, [pc, #448]	; (3c4 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     202:	2200      	movs	r2, #0
     204:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
     208:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
            tmp_buf_sz, hash, seed, seed_len);
    if (rc) {
        goto out;
    }

    if (out_hash) {
     20c:	f1bb 0f00 	cmp.w	fp, #0
     210:	d004      	beq.n	21c <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x1c>
        memcpy(out_hash, hash, 32);
     212:	2220      	movs	r2, #32
     214:	a90d      	add	r1, sp, #52	; 0x34
     216:	4658      	mov	r0, fp
     218:	f005 feae 	bl	5f78 <memcpy>
    }

    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
     21c:	2300      	movs	r3, #0
     21e:	9300      	str	r3, [sp, #0]
     220:	4632      	mov	r2, r6
     222:	f64f 73ff 	movw	r3, #65535	; 0xffff
     226:	4621      	mov	r1, r4
     228:	a807      	add	r0, sp, #28
     22a:	f005 f916 	bl	545a <bootutil_tlv_iter_begin>
    if (rc) {
     22e:	4605      	mov	r5, r0
     230:	b9d0      	cbnz	r0, 268 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x68>
        goto out;
    }

    if (it.tlv_end > bootutil_max_image_size(fap)) {
     232:	4630      	mov	r0, r6
     234:	9c0c      	ldr	r4, [sp, #48]	; 0x30
     236:	f005 fa09 	bl	564c <bootutil_max_image_size>
     23a:	4284      	cmp	r4, r0
     23c:	d91f      	bls.n	27e <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x7e>
        rc = -1;
     23e:	f04f 35ff 	mov.w	r5, #4294967295
     242:	e011      	b.n	268 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x68>
        if (blk_sz > tmp_buf_sz) {
     244:	9b65      	ldr	r3, [sp, #404]	; 0x194
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     246:	9a64      	ldr	r2, [sp, #400]	; 0x190
        blk_sz = size - off;
     248:	eba7 0a09 	sub.w	sl, r7, r9
     24c:	459a      	cmp	sl, r3
     24e:	bf28      	it	cs
     250:	469a      	movcs	sl, r3
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     252:	4653      	mov	r3, sl
     254:	4649      	mov	r1, r9
     256:	4630      	mov	r0, r6
     258:	f005 fde4 	bl	5e24 <flash_area_read>
        if (rc) {
     25c:	4605      	mov	r5, r0
     25e:	b138      	cbz	r0, 270 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x70>
     260:	4b58      	ldr	r3, [pc, #352]	; (3c4 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     262:	2200      	movs	r2, #0
     264:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     268:	4628      	mov	r0, r5
     26a:	b05b      	add	sp, #364	; 0x16c
     26c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     270:	9964      	ldr	r1, [sp, #400]	; 0x190
     272:	4652      	mov	r2, sl
     274:	a83a      	add	r0, sp, #232	; 0xe8
     276:	f005 fcde 	bl	5c36 <cc310_sha256_update>
    for (off = 0; off < size; off += blk_sz) {
     27a:	44d1      	add	r9, sl
     27c:	e7ba      	b.n	1f4 <bootutil_img_validate+0x48>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     27e:	f8df b150 	ldr.w	fp, [pc, #336]	; 3d0 <FIH_LABEL_FIH_CALL_END_1006+0x30>
     282:	f8df 9140 	ldr.w	r9, [pc, #320]	; 3c4 <FIH_LABEL_FIH_CALL_END_1006+0x24>
    int key_id = -1;
     286:	f04f 37ff 	mov.w	r7, #4294967295
        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
     28a:	f10d 0316 	add.w	r3, sp, #22
     28e:	aa05      	add	r2, sp, #20
     290:	a906      	add	r1, sp, #24
     292:	a807      	add	r0, sp, #28
     294:	f005 f92f 	bl	54f6 <bootutil_tlv_iter_next>
        if (rc < 0) {
     298:	1e04      	subs	r4, r0, #0
     29a:	f2c0 808f 	blt.w	3bc <FIH_LABEL_FIH_CALL_END_1006+0x1c>
        } else if (rc > 0) {
     29e:	f040 8082 	bne.w	3a6 <FIH_LABEL_FIH_CALL_END_1006+0x6>
        if (type == IMAGE_TLV_SHA256) {
     2a2:	f8bd a016 	ldrh.w	sl, [sp, #22]
     2a6:	f1ba 0f10 	cmp.w	sl, #16
     2aa:	d118      	bne.n	2de <FIH_LABEL_FIH_CALL_END_689+0xc>
            if (len != sizeof(hash)) {
     2ac:	f8bd 5014 	ldrh.w	r5, [sp, #20]
     2b0:	2d20      	cmp	r5, #32
     2b2:	d1c4      	bne.n	23e <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x3e>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, sizeof(hash));
     2b4:	9906      	ldr	r1, [sp, #24]
     2b6:	462b      	mov	r3, r5
     2b8:	aa3a      	add	r2, sp, #232	; 0xe8
     2ba:	4630      	mov	r0, r6
     2bc:	f005 fdb2 	bl	5e24 <flash_area_read>
            if (rc) {
     2c0:	4604      	mov	r4, r0
     2c2:	2800      	cmp	r0, #0
     2c4:	d17a      	bne.n	3bc <FIH_LABEL_FIH_CALL_END_1006+0x1c>

000002c6 <FIH_LABEL_FIH_CALL_START_672>:
            FIH_CALL(boot_fih_memequal, fih_rc, hash, buf, sizeof(hash));
     2c6:	462a      	mov	r2, r5
     2c8:	a93a      	add	r1, sp, #232	; 0xe8
     2ca:	a80d      	add	r0, sp, #52	; 0x34
     2cc:	f005 f98b 	bl	55e6 <boot_fih_memequal>
     2d0:	4605      	mov	r5, r0

000002d2 <FIH_LABEL_FIH_CALL_END_689>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     2d2:	4b3d      	ldr	r3, [pc, #244]	; (3c8 <FIH_LABEL_FIH_CALL_END_1006+0x28>)
     2d4:	681b      	ldr	r3, [r3, #0]
     2d6:	4283      	cmp	r3, r0
     2d8:	d1c6      	bne.n	268 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x68>
            sha256_valid = 1;
     2da:	2501      	movs	r5, #1
     2dc:	e7d5      	b.n	28a <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8a>
        } else if (type == IMAGE_TLV_KEYHASH) {
     2de:	f1ba 0f01 	cmp.w	sl, #1
     2e2:	d13e      	bne.n	362 <FIH_LABEL_FIH_CALL_END_689+0x90>
            if (len > 32) {
     2e4:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     2e8:	2b20      	cmp	r3, #32
     2ea:	d8a8      	bhi.n	23e <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x3e>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     2ec:	9906      	ldr	r1, [sp, #24]
     2ee:	aa3a      	add	r2, sp, #232	; 0xe8
     2f0:	4630      	mov	r0, r6
     2f2:	f005 fd97 	bl	5e24 <flash_area_read>
            if (rc) {
     2f6:	4604      	mov	r4, r0
     2f8:	2800      	cmp	r0, #0
     2fa:	d15f      	bne.n	3bc <FIH_LABEL_FIH_CALL_END_1006+0x1c>
            key_id = bootutil_find_key(buf, len);
     2fc:	f89d 3014 	ldrb.w	r3, [sp, #20]
     300:	9302      	str	r3, [sp, #8]
    if (keyhash_len > 32) {
     302:	2b20      	cmp	r3, #32
     304:	d809      	bhi.n	31a <FIH_LABEL_FIH_CALL_END_689+0x48>
    for (i = 0; i < bootutil_key_cnt; i++) {
     306:	f8db 3000 	ldr.w	r3, [fp]
     30a:	4f30      	ldr	r7, [pc, #192]	; (3cc <FIH_LABEL_FIH_CALL_END_1006+0x2c>)
     30c:	9303      	str	r3, [sp, #12]
     30e:	9b03      	ldr	r3, [sp, #12]
     310:	429c      	cmp	r4, r3
     312:	db05      	blt.n	320 <FIH_LABEL_FIH_CALL_END_689+0x4e>
     314:	2300      	movs	r3, #0
     316:	f8c9 3500 	str.w	r3, [r9, #1280]	; 0x500
        return -1;
     31a:	f04f 34ff 	mov.w	r4, #4294967295
     31e:	e01c      	b.n	35a <FIH_LABEL_FIH_CALL_END_689+0x88>
    cc310_init();
     320:	f000 fc74 	bl	c0c <cc310_init>
    NRF_CRYPTOCELL->ENABLE=1;
     324:	f8c9 a500 	str.w	sl, [r9, #1280]	; 0x500
    nrf_cc310_bl_hash_sha256_init(ctx);
     328:	a81d      	add	r0, sp, #116	; 0x74
     32a:	f003 ffc3 	bl	42b4 <nrf_cc310_bl_hash_sha256_init>
        bootutil_sha256_update(&sha256_ctx, key->key, *key->len);
     32e:	687a      	ldr	r2, [r7, #4]
     330:	f857 1b08 	ldr.w	r1, [r7], #8
     334:	6812      	ldr	r2, [r2, #0]
     336:	a81d      	add	r0, sp, #116	; 0x74
     338:	f005 fc7d 	bl	5c36 <cc310_sha256_update>
    nrf_cc310_bl_hash_sha256_finalize(ctx,
     33c:	a915      	add	r1, sp, #84	; 0x54
     33e:	a81d      	add	r0, sp, #116	; 0x74
     340:	f004 f82a 	bl	4398 <nrf_cc310_bl_hash_sha256_finalize>
    NRF_CRYPTOCELL->ENABLE=0;
     344:	2200      	movs	r2, #0
     346:	f8c9 2500 	str.w	r2, [r9, #1280]	; 0x500
        if (!memcmp(hash, keyhash, keyhash_len)) {
     34a:	9a02      	ldr	r2, [sp, #8]
     34c:	a93a      	add	r1, sp, #232	; 0xe8
     34e:	a815      	add	r0, sp, #84	; 0x54
     350:	f005 fdeb 	bl	5f2a <memcmp>
     354:	b918      	cbnz	r0, 35e <FIH_LABEL_FIH_CALL_END_689+0x8c>
     356:	f8c9 0500 	str.w	r0, [r9, #1280]	; 0x500
            key_id = bootutil_find_key(buf, len);
     35a:	4627      	mov	r7, r4
     35c:	e795      	b.n	28a <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8a>
    for (i = 0; i < bootutil_key_cnt; i++) {
     35e:	3401      	adds	r4, #1
     360:	e7d5      	b.n	30e <FIH_LABEL_FIH_CALL_END_689+0x3c>
        } else if (type == EXPECTED_SIG_TLV) {
     362:	f1ba 0f22 	cmp.w	sl, #34	; 0x22
     366:	d190      	bne.n	28a <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8a>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     368:	1c7b      	adds	r3, r7, #1
     36a:	d08e      	beq.n	28a <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8a>
     36c:	f8db 3000 	ldr.w	r3, [fp]
     370:	42bb      	cmp	r3, r7
     372:	dd15      	ble.n	3a0 <FIH_LABEL_FIH_CALL_END_1006>
            if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {
     374:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     378:	2b80      	cmp	r3, #128	; 0x80
     37a:	f63f af60 	bhi.w	23e <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x3e>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     37e:	9906      	ldr	r1, [sp, #24]
     380:	aa3a      	add	r2, sp, #232	; 0xe8
     382:	4630      	mov	r0, r6
     384:	f005 fd4e 	bl	5e24 <flash_area_read>
            if (rc) {
     388:	4604      	mov	r4, r0
     38a:	b9b8      	cbnz	r0, 3bc <FIH_LABEL_FIH_CALL_END_1006+0x1c>

0000038c <FIH_LABEL_FIH_CALL_START_985>:
            FIH_CALL(bootutil_verify_sig, valid_signature, hash, sizeof(hash),
     38c:	b2ff      	uxtb	r7, r7
     38e:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     392:	9700      	str	r7, [sp, #0]
     394:	aa3a      	add	r2, sp, #232	; 0xe8
     396:	2120      	movs	r1, #32
     398:	a80d      	add	r0, sp, #52	; 0x34
     39a:	f000 f81b 	bl	3d4 <bootutil_verify_sig>
     39e:	4680      	mov	r8, r0

000003a0 <FIH_LABEL_FIH_CALL_END_1006>:
            key_id = -1;
     3a0:	f04f 37ff 	mov.w	r7, #4294967295
     3a4:	e771      	b.n	28a <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8a>
    if (rc) {
     3a6:	b145      	cbz	r5, 3ba <FIH_LABEL_FIH_CALL_END_1006+0x1a>
    fih_rc = fih_int_encode_zero_equality(fih_not_eq(valid_signature,
     3a8:	4b07      	ldr	r3, [pc, #28]	; (3c8 <FIH_LABEL_FIH_CALL_END_1006+0x28>)
 * value that is not FIH_SUCCESS
 */
__attribute__((always_inline)) inline
fih_int fih_int_encode_zero_equality(int x)
{
    if (x) {
     3aa:	681b      	ldr	r3, [r3, #0]
     3ac:	4543      	cmp	r3, r8
        return FIH_FAILURE;
     3ae:	bf1c      	itt	ne
     3b0:	4b03      	ldrne	r3, [pc, #12]	; (3c0 <FIH_LABEL_FIH_CALL_END_1006+0x20>)
     3b2:	f8d3 8000 	ldrne.w	r8, [r3]
        return -1;
     3b6:	4645      	mov	r5, r8
     3b8:	e756      	b.n	268 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x68>
    rc = !sha256_valid;
     3ba:	2401      	movs	r4, #1
        return -1;
     3bc:	4625      	mov	r5, r4
     3be:	e753      	b.n	268 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x68>
     3c0:	20000000 	.word	0x20000000
     3c4:	5002a000 	.word	0x5002a000
     3c8:	20000128 	.word	0x20000128
     3cc:	00006a4c 	.word	0x00006a4c
     3d0:	00006a48 	.word	0x00006a48

000003d4 <bootutil_verify_sig>:
#endif /* not MCUBOOT_ECDSA_NEED_ASN1_SIG */

int
bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen,
  uint8_t key_id)
{
     3d4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     3d8:	b096      	sub	sp, #88	; 0x58
     3da:	4617      	mov	r7, r2
     3dc:	461d      	mov	r5, r3
     3de:	f89d 2070 	ldrb.w	r2, [sp, #112]	; 0x70

#ifndef MCUBOOT_ECDSA_NEED_ASN1_SIG
    uint8_t signature[2 * NUM_ECC_BYTES];
#endif

    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     3e2:	4b35      	ldr	r3, [pc, #212]	; (4b8 <CONFIG_FLASH_SIZE+0xb8>)
{
     3e4:	460e      	mov	r6, r1
    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     3e6:	f853 1032 	ldr.w	r1, [r3, r2, lsl #3]
     3ea:	9101      	str	r1, [sp, #4]
    end = pubkey + *bootutil_keys[key_id].len;
     3ec:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
{
     3f0:	4680      	mov	r8, r0
    end = pubkey + *bootutil_keys[key_id].len;
     3f2:	685b      	ldr	r3, [r3, #4]
     3f4:	6818      	ldr	r0, [r3, #0]
    if (mbedtls_asn1_get_tag(cp, end, &len,
     3f6:	aa02      	add	r2, sp, #8
     3f8:	4401      	add	r1, r0
     3fa:	2330      	movs	r3, #48	; 0x30
     3fc:	a801      	add	r0, sp, #4
     3fe:	f005 fba8 	bl	5b52 <mbedtls_asn1_get_tag>
     402:	b120      	cbz	r0, 40e <CONFIG_FLASH_SIZE+0xe>
    rc = bootutil_parse_eckey(&ctx, &pubkey, end);
#else
    rc = bootutil_import_key(&pubkey, end);
#endif
    if (rc) {
        return -1;
     404:	f04f 30ff 	mov.w	r0, #4294967295
#endif /* CY_MBEDTLS_HW_ACCELERATION */

    bootutil_ecdsa_p256_drop(&ctx);

    return rc;
}
     408:	b016      	add	sp, #88	; 0x58
     40a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    end = *cp + len;
     40e:	e9dd 4301 	ldrd	r4, r3, [sp, #4]
     412:	441c      	add	r4, r3
    if (mbedtls_asn1_get_alg(cp, end, &alg, &param)) {
     414:	aa03      	add	r2, sp, #12
     416:	ab06      	add	r3, sp, #24
     418:	4621      	mov	r1, r4
     41a:	a801      	add	r0, sp, #4
     41c:	f005 fbc1 	bl	5ba2 <mbedtls_asn1_get_alg>
     420:	2800      	cmp	r0, #0
     422:	d1ef      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     424:	9a04      	ldr	r2, [sp, #16]
     426:	2a07      	cmp	r2, #7
     428:	d1ec      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
        memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
     42a:	4924      	ldr	r1, [pc, #144]	; (4bc <CONFIG_FLASH_SIZE+0xbc>)
     42c:	9805      	ldr	r0, [sp, #20]
     42e:	f005 fd7c 	bl	5f2a <memcmp>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     432:	2800      	cmp	r0, #0
     434:	d1e6      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     436:	9a07      	ldr	r2, [sp, #28]
     438:	2a08      	cmp	r2, #8
     43a:	d1e3      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
        memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
     43c:	4920      	ldr	r1, [pc, #128]	; (4c0 <CONFIG_FLASH_SIZE+0xc0>)
     43e:	9808      	ldr	r0, [sp, #32]
     440:	f005 fd73 	bl	5f2a <memcmp>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     444:	2800      	cmp	r0, #0
     446:	d1dd      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (mbedtls_asn1_get_bitstring_null(cp, end, &len)) {
     448:	aa02      	add	r2, sp, #8
     44a:	4621      	mov	r1, r4
     44c:	a801      	add	r0, sp, #4
     44e:	f005 fb94 	bl	5b7a <mbedtls_asn1_get_bitstring_null>
     452:	2800      	cmp	r0, #0
     454:	d1d6      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (*cp + len != end) {
     456:	e9dd 3201 	ldrd	r3, r2, [sp, #4]
     45a:	4413      	add	r3, r2
     45c:	429c      	cmp	r4, r3
     45e:	d1d1      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (len != 2 * NUM_ECC_BYTES + 1) {
     460:	2a41      	cmp	r2, #65	; 0x41
     462:	d1cf      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    rc = bootutil_decode_sig(signature, sig, sig + slen);
     464:	443d      	add	r5, r7
    rc = mbedtls_asn1_get_tag(&cp, end, &len,
     466:	2330      	movs	r3, #48	; 0x30
     468:	aa03      	add	r2, sp, #12
     46a:	4629      	mov	r1, r5
     46c:	a802      	add	r0, sp, #8
     46e:	9702      	str	r7, [sp, #8]
     470:	f005 fb6f 	bl	5b52 <mbedtls_asn1_get_tag>
    if (rc) {
     474:	2800      	cmp	r0, #0
     476:	d1c5      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (cp + len > end) {
     478:	e9dd 3202 	ldrd	r3, r2, [sp, #8]
     47c:	4413      	add	r3, r2
     47e:	429d      	cmp	r5, r3
     480:	d3c0      	bcc.n	404 <CONFIG_FLASH_SIZE+0x4>
    rc = bootutil_read_bigint(signature, &cp, end);
     482:	462a      	mov	r2, r5
     484:	a902      	add	r1, sp, #8
     486:	a806      	add	r0, sp, #24
     488:	f005 f881 	bl	558e <bootutil_read_bigint>
    if (rc) {
     48c:	2800      	cmp	r0, #0
     48e:	d1b9      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    rc = bootutil_read_bigint(signature + NUM_ECC_BYTES, &cp, end);
     490:	462a      	mov	r2, r5
     492:	a902      	add	r1, sp, #8
     494:	a80e      	add	r0, sp, #56	; 0x38
     496:	f005 f87a 	bl	558e <bootutil_read_bigint>
    if (rc) {
     49a:	2800      	cmp	r0, #0
     49c:	d1b2      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    if (hlen != NUM_ECC_BYTES) {
     49e:	2e20      	cmp	r6, #32
     4a0:	d1b0      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
    rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, signature,
     4a2:	9901      	ldr	r1, [sp, #4]
    (void)ctx;
    (void)pk_len;
    (void)sig_len;

    /* Only support uncompressed keys. */
    if (pk[0] != 0x04) {
     4a4:	780b      	ldrb	r3, [r1, #0]
     4a6:	2b04      	cmp	r3, #4
     4a8:	d1ac      	bne.n	404 <CONFIG_FLASH_SIZE+0x4>
        return -1;
    }
    pk++;

    return cc310_ecdsa_verify_secp256r1(hash, pk, sig, BOOTUTIL_CRYPTO_ECDSA_P256_HASH_SIZE);
     4aa:	4633      	mov	r3, r6
     4ac:	aa06      	add	r2, sp, #24
     4ae:	3101      	adds	r1, #1
     4b0:	4640      	mov	r0, r8
     4b2:	f000 fbc3 	bl	c3c <cc310_ecdsa_verify_secp256r1>
     4b6:	e7a7      	b.n	408 <CONFIG_FLASH_SIZE+0x8>
     4b8:	00006a4c 	.word	0x00006a4c
     4bc:	00006df3 	.word	0x00006df3
     4c0:	00006dea 	.word	0x00006dea

000004c4 <boot_read_swap_size>:
    return -1;
}

int
boot_read_swap_size(int image_index, uint32_t *swap_size)
{
     4c4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     4c8:	b086      	sub	sp, #24
    uint8_t areas[2] = {
     4ca:	2303      	movs	r3, #3
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     4cc:	f8df 806c 	ldr.w	r8, [pc, #108]	; 53c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x54>
    uint8_t areas[2] = {
     4d0:	f8ad 3000 	strh.w	r3, [sp]
{
     4d4:	460d      	mov	r5, r1
     4d6:	466f      	mov	r7, sp
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     4d8:	2600      	movs	r6, #0
        rc = flash_area_open(areas[i], fap);
     4da:	f817 0b01 	ldrb.w	r0, [r7], #1
     4de:	a901      	add	r1, sp, #4
     4e0:	f000 fd0a 	bl	ef8 <flash_area_open>
        if (rc != 0) {
     4e4:	4604      	mov	r4, r0
     4e6:	b9a0      	cbnz	r0, 512 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2a>
        off = boot_magic_off(*fap);
     4e8:	9801      	ldr	r0, [sp, #4]
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
     4ea:	6881      	ldr	r1, [r0, #8]
        rc = flash_area_read(*fap, off, magic, BOOT_MAGIC_SZ);
     4ec:	2310      	movs	r3, #16
     4ee:	aa02      	add	r2, sp, #8
     4f0:	3910      	subs	r1, #16
     4f2:	f005 fc97 	bl	5e24 <flash_area_read>
     4f6:	4604      	mov	r4, r0
        flash_area_close(*fap);
     4f8:	9801      	ldr	r0, [sp, #4]
     4fa:	f005 fc92 	bl	5e22 <flash_area_close>
        if (rc != 0) {
     4fe:	b944      	cbnz	r4, 512 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2a>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     500:	2210      	movs	r2, #16
     502:	4641      	mov	r1, r8
     504:	a802      	add	r0, sp, #8
     506:	f005 fd10 	bl	5f2a <memcmp>
     50a:	b140      	cbz	r0, 51e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x36>
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     50c:	b12e      	cbz	r6, 51a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x32>
    return -1;
     50e:	f04f 34ff 	mov.w	r4, #4294967295
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
        flash_area_close(fap);
    }

    return rc;
}
     512:	4620      	mov	r0, r4
     514:	b006      	add	sp, #24
     516:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     51a:	2601      	movs	r6, #1
     51c:	e7dd      	b.n	4da <boot_read_swap_size+0x16>
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
     51e:	9801      	ldr	r0, [sp, #4]
     520:	f005 ff78 	bl	6414 <boot_swap_info_off>
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
     524:	2304      	movs	r3, #4
     526:	f1a0 0108 	sub.w	r1, r0, #8
     52a:	462a      	mov	r2, r5
     52c:	9801      	ldr	r0, [sp, #4]
     52e:	f005 fc79 	bl	5e24 <flash_area_read>
     532:	4604      	mov	r4, r0
        flash_area_close(fap);
     534:	9801      	ldr	r0, [sp, #4]
     536:	f005 fc74 	bl	5e22 <flash_area_close>
     53a:	e7ea      	b.n	512 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2a>
     53c:	00006dda 	.word	0x00006dda

00000540 <boot_validate_slot.isra.0>:
 *         FIH_SUCCESS                      if image was successfully validated
 *         1 (or its fih_int encoded form)  if no bootloable image was found
 *         FIH_FAILURE                      on any errors
 */
static fih_int
boot_validate_slot(struct boot_loader_state *state, int slot,
     540:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
                   struct boot_status *bs)
{
    const struct flash_area *fap;
    struct image_header *hdr;
    int area_id;
    fih_int fih_rc = FIH_FAILURE;
     544:	4b32      	ldr	r3, [pc, #200]	; (610 <FIH_LABEL_FIH_CALL_END_437+0x6a>)
boot_validate_slot(struct boot_loader_state *state, int slot,
     546:	b088      	sub	sp, #32
     548:	4606      	mov	r6, r0
    int rc;

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     54a:	2000      	movs	r0, #0
boot_validate_slot(struct boot_loader_state *state, int slot,
     54c:	460c      	mov	r4, r1
    fih_int fih_rc = FIH_FAILURE;
     54e:	681d      	ldr	r5, [r3, #0]
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     550:	f004 ff76 	bl	5440 <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     554:	a906      	add	r1, sp, #24
     556:	b2c0      	uxtb	r0, r0
     558:	f000 fcce 	bl	ef8 <flash_area_open>
    if (rc != 0) {
     55c:	2800      	cmp	r0, #0
     55e:	d152      	bne.n	606 <FIH_LABEL_FIH_CALL_END_437+0x60>
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     560:	4621      	mov	r1, r4
     562:	f004 ff6d 	bl	5440 <flash_area_id_from_multi_image_slot>
     ((swap_type) == BOOT_SWAP_TYPE_PERM))

static inline struct image_header*
boot_img_hdr(struct boot_loader_state *state, size_t slot)
{
    return &BOOT_IMG(state, slot).hdr;
     566:	252c      	movs	r5, #44	; 0x2c
    rc = flash_area_open(area_id, &fap);
     568:	a907      	add	r1, sp, #28
     56a:	b2c0      	uxtb	r0, r0
     56c:	fb05 6504 	mla	r5, r5, r4, r6
     570:	f000 fcc2 	bl	ef8 <flash_area_open>
    if (rc != 0) {
     574:	2800      	cmp	r0, #0
     576:	d02e      	beq.n	5d6 <FIH_LABEL_FIH_CALL_END_437+0x30>
        FIH_RET(fih_rc);
    }

    hdr = boot_img_hdr(state, slot);
    if (boot_check_header_erased(state, slot) == 0 ||
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     578:	272c      	movs	r7, #44	; 0x2c
     57a:	4367      	muls	r7, r4
     57c:	eb06 0807 	add.w	r8, r6, r7
#endif
    BOOT_HOOK_CALL_FIH(boot_image_check_hook, fih_int_encode(BOOT_HOOK_REGULAR),
                       fih_rc, BOOT_CURR_IMG(state), slot);
    if (fih_eq(fih_rc, fih_int_encode(BOOT_HOOK_REGULAR)))
    {
        FIH_CALL(boot_image_check, fih_rc, state, hdr, fap, bs);
     580:	9b06      	ldr	r3, [sp, #24]
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     582:	f8d8 1010 	ldr.w	r1, [r8, #16]
    if (boot_check_header_erased(state, slot) == 0 ||
     586:	f011 0110 	ands.w	r1, r1, #16
     58a:	d133      	bne.n	5f4 <FIH_LABEL_FIH_CALL_END_437+0x4e>

0000058c <FIH_LABEL_FIH_CALL_START_388>:
    FIH_CALL(bootutil_img_validate, fih_rc, BOOT_CURR_ENC(state), image_index,
     58c:	f44f 7280 	mov.w	r2, #256	; 0x100
     590:	9201      	str	r2, [sp, #4]
     592:	4a20      	ldr	r2, [pc, #128]	; (614 <FIH_LABEL_FIH_CALL_END_437+0x6e>)
     594:	9200      	str	r2, [sp, #0]
     596:	e9cd 1103 	strd	r1, r1, [sp, #12]
     59a:	462a      	mov	r2, r5
     59c:	9102      	str	r1, [sp, #8]
     59e:	4608      	mov	r0, r1
     5a0:	f7ff fe04 	bl	1ac <bootutil_img_validate>
     5a4:	4605      	mov	r5, r0

000005a6 <FIH_LABEL_FIH_CALL_END_437>:
    if (hdr->ih_magic != IMAGE_MAGIC) {
     5a6:	4b1c      	ldr	r3, [pc, #112]	; (618 <FIH_LABEL_FIH_CALL_END_437+0x72>)
     5a8:	59f2      	ldr	r2, [r6, r7]
    }
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     5aa:	9806      	ldr	r0, [sp, #24]
    if (hdr->ih_magic != IMAGE_MAGIC) {
     5ac:	429a      	cmp	r2, r3
     5ae:	d10c      	bne.n	5ca <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (!boot_u32_safe_add(&size, hdr->ih_img_size, hdr->ih_hdr_size)) {
     5b0:	f8d8 200c 	ldr.w	r2, [r8, #12]
     5b4:	f8b8 3008 	ldrh.w	r3, [r8, #8]
    if (a > UINT32_MAX - b) {
     5b8:	189b      	adds	r3, r3, r2
     5ba:	d206      	bcs.n	5ca <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (size >= flash_area_get_size(fap)) {
     5bc:	6882      	ldr	r2, [r0, #8]
     5be:	4293      	cmp	r3, r2
     5c0:	d203      	bcs.n	5ca <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     5c2:	4b16      	ldr	r3, [pc, #88]	; (61c <FIH_LABEL_FIH_CALL_END_437+0x76>)
     5c4:	681b      	ldr	r3, [r3, #0]
     5c6:	42ab      	cmp	r3, r5
     5c8:	d01a      	beq.n	600 <FIH_LABEL_FIH_CALL_END_437+0x5a>
        if ((slot != BOOT_PRIMARY_SLOT) || ARE_SLOTS_EQUIVALENT()) {
     5ca:	b1c4      	cbz	r4, 5fe <FIH_LABEL_FIH_CALL_END_437+0x58>
            flash_area_erase(fap, 0, flash_area_get_size(fap));
     5cc:	6882      	ldr	r2, [r0, #8]
     5ce:	2100      	movs	r1, #0
     5d0:	f005 fc52 	bl	5e78 <flash_area_erase>
     5d4:	e013      	b.n	5fe <FIH_LABEL_FIH_CALL_END_437+0x58>
    erased_val = flash_area_erased_val(fap);
     5d6:	9807      	ldr	r0, [sp, #28]
     5d8:	f005 fc6b 	bl	5eb2 <flash_area_erased_val>
     5dc:	4607      	mov	r7, r0
    flash_area_close(fap);
     5de:	9807      	ldr	r0, [sp, #28]
     5e0:	f005 fc1f 	bl	5e22 <flash_area_close>
    for (i = 0; i < len; i++) {
     5e4:	1e6b      	subs	r3, r5, #1
     5e6:	1cea      	adds	r2, r5, #3
        if (val != p[i]) {
     5e8:	f813 1f01 	ldrb.w	r1, [r3, #1]!
     5ec:	42b9      	cmp	r1, r7
     5ee:	d1c3      	bne.n	578 <boot_validate_slot.isra.0+0x38>
    for (i = 0; i < len; i++) {
     5f0:	4293      	cmp	r3, r2
     5f2:	d1f9      	bne.n	5e8 <FIH_LABEL_FIH_CALL_END_437+0x42>
            swap_erase_trailer_sectors(state, fap);
     5f4:	9906      	ldr	r1, [sp, #24]
        if (slot != BOOT_PRIMARY_SLOT) {
     5f6:	b114      	cbz	r4, 5fe <FIH_LABEL_FIH_CALL_END_437+0x58>
            swap_erase_trailer_sectors(state, fap);
     5f8:	4630      	mov	r0, r6
     5fa:	f005 f8f7 	bl	57ec <swap_erase_trailer_sectors>
        fih_rc = fih_int_encode(1);
     5fe:	2501      	movs	r5, #1
        }
    }
#endif

out:
    flash_area_close(fap);
     600:	9806      	ldr	r0, [sp, #24]
     602:	f005 fc0e 	bl	5e22 <flash_area_close>

    FIH_RET(fih_rc);
}
     606:	4628      	mov	r0, r5
     608:	b008      	add	sp, #32
     60a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
     60e:	bf00      	nop
     610:	20000000 	.word	0x20000000
     614:	200016f4 	.word	0x200016f4
     618:	96f3b83d 	.word	0x96f3b83d
     61c:	20000128 	.word	0x20000128

00000620 <boot_swap_image>:
 *
 * @return                      0 on success; nonzero on failure.
 */
static int
boot_swap_image(struct boot_loader_state *state, struct boot_status *bs)
{
     620:	b573      	push	{r0, r1, r4, r5, r6, lr}
     622:	460d      	mov	r5, r1
     624:	4604      	mov	r4, r0
    uint8_t image_index;
    int rc;

    /* FIXME: just do this if asked by user? */

    size = copy_size = 0;
     626:	2100      	movs	r1, #0
    image_index = BOOT_CURR_IMG(state);

    if (boot_status_is_reset(bs)) {
     628:	4628      	mov	r0, r5
    size = copy_size = 0;
     62a:	e9cd 1100 	strd	r1, r1, [sp]
    if (boot_status_is_reset(bs)) {
     62e:	f005 f89c 	bl	576a <boot_status_is_reset>
     632:	b1f0      	cbz	r0, 672 <boot_swap_image+0x52>
        /*
         * No swap ever happened, so need to find the largest image which
         * will be used to determine the amount of sectors to swap.
         */
        hdr = boot_img_hdr(state, BOOT_PRIMARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     634:	4e12      	ldr	r6, [pc, #72]	; (680 <boot_swap_image+0x60>)
     636:	6823      	ldr	r3, [r4, #0]
     638:	42b3      	cmp	r3, r6
     63a:	d103      	bne.n	644 <boot_swap_image+0x24>
            rc = boot_read_image_size(state, BOOT_PRIMARY_SLOT, &copy_size);
     63c:	aa01      	add	r2, sp, #4
     63e:	4620      	mov	r0, r4
     640:	f005 f827 	bl	5692 <boot_read_image_size.constprop.0.isra.0>
            memset(bs->enckey[0], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        hdr = boot_img_hdr(state, BOOT_SECONDARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     644:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     646:	42b3      	cmp	r3, r6
     648:	d104      	bne.n	654 <boot_swap_image+0x34>
            rc = boot_read_image_size(state, BOOT_SECONDARY_SLOT, &size);
     64a:	466a      	mov	r2, sp
     64c:	2101      	movs	r1, #1
     64e:	4620      	mov	r0, r4
     650:	f005 f81f 	bl	5692 <boot_read_image_size.constprop.0.isra.0>
        } else {
            memset(bs->enckey[1], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        if (size > copy_size) {
     654:	e9dd 3200 	ldrd	r3, r2, [sp]
     658:	4293      	cmp	r3, r2
            copy_size = size;
     65a:	bf88      	it	hi
     65c:	9301      	strhi	r3, [sp, #4]
        }

        bs->swap_size = copy_size;
     65e:	9b01      	ldr	r3, [sp, #4]
     660:	60ab      	str	r3, [r5, #8]
            }
        }
#endif
    }

    swap_run(state, bs, copy_size);
     662:	4620      	mov	r0, r4
     664:	9a01      	ldr	r2, [sp, #4]
     666:	4629      	mov	r1, r5
     668:	f000 f9e0 	bl	a2c <swap_run>
#endif
    rc = BOOT_HOOK_CALL(boot_copy_region_post_hook, 0, BOOT_CURR_IMG(state),
                        BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT), size);

    return 0;
}
     66c:	2000      	movs	r0, #0
     66e:	b002      	add	sp, #8
     670:	bd70      	pop	{r4, r5, r6, pc}
        rc = boot_read_swap_size(image_index, &bs->swap_size);
     672:	f105 0108 	add.w	r1, r5, #8
     676:	f7ff ff25 	bl	4c4 <boot_read_swap_size>
        copy_size = bs->swap_size;
     67a:	68ab      	ldr	r3, [r5, #8]
     67c:	9301      	str	r3, [sp, #4]
     67e:	e7f0      	b.n	662 <boot_swap_image+0x42>
     680:	96f3b83d 	.word	0x96f3b83d

00000684 <boot_copy_region>:
{
     684:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     688:	f8df b078 	ldr.w	fp, [pc, #120]	; 704 <boot_copy_region+0x80>
     68c:	4c1b      	ldr	r4, [pc, #108]	; (6fc <boot_copy_region+0x78>)
     68e:	4d1c      	ldr	r5, [pc, #112]	; (700 <boot_copy_region+0x7c>)
{
     690:	4688      	mov	r8, r1
     692:	4691      	mov	r9, r2
     694:	469a      	mov	sl, r3
    bytes_copied = 0;
     696:	2600      	movs	r6, #0
    while (bytes_copied < sz) {
     698:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
     69a:	429e      	cmp	r6, r3
     69c:	d301      	bcc.n	6a2 <boot_copy_region+0x1e>
    return 0;
     69e:	2000      	movs	r0, #0
     6a0:	e00f      	b.n	6c2 <boot_copy_region+0x3e>
        if (sz - bytes_copied > sizeof buf) {
     6a2:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     6a4:	4a17      	ldr	r2, [pc, #92]	; (704 <boot_copy_region+0x80>)
        if (sz - bytes_copied > sizeof buf) {
     6a6:	1b9f      	subs	r7, r3, r6
     6a8:	f5b7 6f80 	cmp.w	r7, #1024	; 0x400
     6ac:	bf28      	it	cs
     6ae:	f44f 6780 	movcs.w	r7, #1024	; 0x400
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     6b2:	463b      	mov	r3, r7
     6b4:	eb06 010a 	add.w	r1, r6, sl
     6b8:	4640      	mov	r0, r8
     6ba:	f005 fbb3 	bl	5e24 <flash_area_read>
        if (rc != 0) {
     6be:	b110      	cbz	r0, 6c6 <boot_copy_region+0x42>
            return BOOT_EFLASH;
     6c0:	2001      	movs	r0, #1
}
     6c2:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_write(fap_dst, off_dst + bytes_copied, buf, chunk_sz);
     6c6:	990a      	ldr	r1, [sp, #40]	; 0x28
     6c8:	463b      	mov	r3, r7
     6ca:	465a      	mov	r2, fp
     6cc:	1871      	adds	r1, r6, r1
     6ce:	4648      	mov	r0, r9
     6d0:	f005 fbbd 	bl	5e4e <flash_area_write>
        if (rc != 0) {
     6d4:	2800      	cmp	r0, #0
     6d6:	d1f3      	bne.n	6c0 <boot_copy_region+0x3c>
     6d8:	f8c4 5600 	str.w	r5, [r4, #1536]	; 0x600
        bytes_copied += chunk_sz;
     6dc:	443e      	add	r6, r7
     6de:	f8c4 5604 	str.w	r5, [r4, #1540]	; 0x604
     6e2:	f8c4 5608 	str.w	r5, [r4, #1544]	; 0x608
     6e6:	f8c4 560c 	str.w	r5, [r4, #1548]	; 0x60c
     6ea:	f8c4 5610 	str.w	r5, [r4, #1552]	; 0x610
     6ee:	f8c4 5614 	str.w	r5, [r4, #1556]	; 0x614
     6f2:	f8c4 5618 	str.w	r5, [r4, #1560]	; 0x618
     6f6:	f8c4 561c 	str.w	r5, [r4, #1564]	; 0x61c
        MCUBOOT_WATCHDOG_FEED();
     6fa:	e7cd      	b.n	698 <boot_copy_region+0x14>
     6fc:	40010000 	.word	0x40010000
     700:	6e524635 	.word	0x6e524635
     704:	2000112c 	.word	0x2000112c

00000708 <context_boot_go>:
#endif
}

fih_int
context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
{
     708:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
        boot_enc_zeroize(BOOT_CURR_ENC(state));
#endif

        image_index = BOOT_CURR_IMG(state);

        BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors =
     70c:	4b81      	ldr	r3, [pc, #516]	; (914 <FIH_LABEL_FIH_CALL_END_2144+0x40>)
     70e:	6243      	str	r3, [r0, #36]	; 0x24
{
     710:	460e      	mov	r6, r1
            primary_slot_sectors[image_index];
        BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors =
     712:	4b81      	ldr	r3, [pc, #516]	; (918 <FIH_LABEL_FIH_CALL_END_2144+0x44>)
     714:	6503      	str	r3, [r0, #80]	; 0x50

        /* Open primary and secondary image areas for the duration
         * of this call.
         */
        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     716:	2100      	movs	r1, #0
{
     718:	4604      	mov	r4, r0
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     71a:	4608      	mov	r0, r1
     71c:	f004 fe90 	bl	5440 <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     720:	f104 0120 	add.w	r1, r4, #32
     724:	b2c0      	uxtb	r0, r0
     726:	f000 fbe7 	bl	ef8 <flash_area_open>
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     72a:	2101      	movs	r1, #1
     72c:	2000      	movs	r0, #0
     72e:	f004 fe87 	bl	5440 <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     732:	f104 014c 	add.w	r1, r4, #76	; 0x4c
     736:	b2c0      	uxtb	r0, r0
     738:	f000 fbde 	bl	ef8 <flash_area_open>
     73c:	4605      	mov	r5, r0
    rc = boot_read_sectors(state);
     73e:	4620      	mov	r0, r4
     740:	f004 ffe8 	bl	5714 <boot_read_sectors>
    if (rc != 0) {
     744:	2800      	cmp	r0, #0
     746:	d148      	bne.n	7da <context_boot_go+0xd2>
    rc = boot_read_image_headers(state, false, NULL);
     748:	2200      	movs	r2, #0
     74a:	4611      	mov	r1, r2
     74c:	4620      	mov	r0, r4
     74e:	f004 ff8a 	bl	5666 <boot_read_image_headers>
    if (rc != 0) {
     752:	2800      	cmp	r0, #0
     754:	d158      	bne.n	808 <CONFIG_ISR_STACK_SIZE+0x8>
    if (boot_slots_compatible(state)) {
     756:	4620      	mov	r0, r4
     758:	f005 f96a 	bl	5a30 <boot_slots_compatible>
     75c:	2800      	cmp	r0, #0
     75e:	d053      	beq.n	808 <CONFIG_ISR_STACK_SIZE+0x8>
        boot_status_reset(bs);
     760:	4668      	mov	r0, sp
     762:	f004 fff9 	bl	5758 <boot_status_reset>
        rc = swap_read_status(state, bs);
     766:	4669      	mov	r1, sp
     768:	4620      	mov	r0, r4
     76a:	f005 f893 	bl	5894 <swap_read_status>
        if (rc != 0) {
     76e:	2800      	cmp	r0, #0
     770:	d14a      	bne.n	808 <CONFIG_ISR_STACK_SIZE+0x8>
        rc = boot_read_image_headers(state, !boot_status_is_reset(bs), bs);
     772:	4668      	mov	r0, sp
     774:	f004 fff9 	bl	576a <boot_status_is_reset>
     778:	f080 0101 	eor.w	r1, r0, #1
     77c:	466a      	mov	r2, sp
     77e:	b2c9      	uxtb	r1, r1
     780:	4620      	mov	r0, r4
     782:	f004 ff70 	bl	5666 <boot_read_image_headers>
        if (rc != 0) {
     786:	4602      	mov	r2, r0
     788:	bbf0      	cbnz	r0, 808 <CONFIG_ISR_STACK_SIZE+0x8>
        if (!boot_status_is_reset(bs)) {
     78a:	4668      	mov	r0, sp
     78c:	f004 ffed 	bl	576a <boot_status_is_reset>
     790:	4607      	mov	r7, r0
     792:	bbe8      	cbnz	r0, 810 <CONFIG_ISR_STACK_SIZE+0x10>
    rc = boot_swap_image(state, bs);
     794:	4669      	mov	r1, sp
     796:	4620      	mov	r0, r4
     798:	f7ff ff42 	bl	620 <boot_swap_image>
    BOOT_SWAP_TYPE(state) = bs->swap_type;
     79c:	f89d 3007 	ldrb.w	r3, [sp, #7]
     7a0:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (bs->swap_type == BOOT_SWAP_TYPE_REVERT ||
     7a4:	3b03      	subs	r3, #3
     7a6:	2b01      	cmp	r3, #1
     7a8:	d806      	bhi.n	7b8 <context_boot_go+0xb0>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     7aa:	4638      	mov	r0, r7
     7ac:	f005 f8c1 	bl	5932 <swap_set_image_ok>
        if (rc != 0) {
     7b0:	b110      	cbz	r0, 7b8 <context_boot_go+0xb0>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     7b2:	23ff      	movs	r3, #255	; 0xff
     7b4:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (BOOT_IS_UPGRADE(bs->swap_type)) {
     7b8:	f89d 3007 	ldrb.w	r3, [sp, #7]
     7bc:	3b02      	subs	r3, #2
     7be:	2b02      	cmp	r3, #2
     7c0:	d806      	bhi.n	7d0 <context_boot_go+0xc8>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     7c2:	2000      	movs	r0, #0
     7c4:	f005 f8a3 	bl	590e <swap_set_copy_done>
        if (rc != 0) {
     7c8:	b110      	cbz	r0, 7d0 <context_boot_go+0xc8>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     7ca:	23ff      	movs	r3, #255	; 0xff
     7cc:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     7d0:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     7d4:	2bff      	cmp	r3, #255	; 0xff
     7d6:	d112      	bne.n	7fe <context_boot_go+0xf6>
        while (1) {}
     7d8:	e7fe      	b.n	7d8 <context_boot_go+0xd0>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     7da:	2301      	movs	r3, #1
        if (rc == BOOT_EFLASH)
     7dc:	4298      	cmp	r0, r3
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     7de:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        if (rc == BOOT_EFLASH)
     7e2:	d1b1      	bne.n	748 <context_boot_go+0x40>
#endif

        /* Determine swap type and complete swap if it has been aborted. */
        boot_prepare_image_for_update(state, &bs);

        if (BOOT_IS_UPGRADE(BOOT_SWAP_TYPE(state))) {
     7e4:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
        /* Indicate that swap is not aborted */
        boot_status_reset(&bs);
#endif /* (BOOT_IMAGE_NUMBER > 1) */

        /* Set the previously determined swap type */
        bs.swap_type = BOOT_SWAP_TYPE(state);
     7e8:	f88d 3007 	strb.w	r3, [sp, #7]

        switch (BOOT_SWAP_TYPE(state)) {
     7ec:	2b04      	cmp	r3, #4
     7ee:	d836      	bhi.n	85e <FIH_LABEL_FIH_CALL_END_1914+0x10>
     7f0:	2b01      	cmp	r3, #1
     7f2:	d83a      	bhi.n	86a <FIH_LABEL_FIH_CALL_END_1914+0x1c>
     7f4:	d051      	beq.n	89a <FIH_LABEL_FIH_CALL_END_1914+0x4c>
            }
#endif /* !MCUBOOT_OVERWRITE_ONLY */
            break;

        default:
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     7f6:	23ff      	movs	r3, #255	; 0xff
     7f8:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     7fc:	e04d      	b.n	89a <FIH_LABEL_FIH_CALL_END_1914+0x4c>
            rc = boot_read_image_headers(state, false, bs);
     7fe:	466a      	mov	r2, sp
     800:	2100      	movs	r1, #0
     802:	4620      	mov	r0, r4
     804:	f004 ff2f 	bl	5666 <boot_read_image_headers>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     808:	2301      	movs	r3, #1
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     80a:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     80e:	e7e9      	b.n	7e4 <context_boot_go+0xdc>
            if (bs->swap_type == BOOT_SWAP_TYPE_NONE) {
     810:	f89d 8007 	ldrb.w	r8, [sp, #7]
     814:	f1b8 0f01 	cmp.w	r8, #1
     818:	d115      	bne.n	846 <FIH_LABEL_FIH_CALL_START_1899>
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     81a:	4610      	mov	r0, r2
     81c:	f002 f840 	bl	28a0 <boot_swap_type_multi>
    if (BOOT_IS_UPGRADE(swap_type)) {
     820:	1e83      	subs	r3, r0, #2
     822:	2b02      	cmp	r3, #2
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     824:	4607      	mov	r7, r0
    if (BOOT_IS_UPGRADE(swap_type)) {
     826:	d80b      	bhi.n	840 <__z_interrupt_stack_SIZEOF>

00000828 <FIH_LABEL_FIH_CALL_START_1848>:
        FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_SECONDARY_SLOT, bs);
     828:	4641      	mov	r1, r8
     82a:	4620      	mov	r0, r4
     82c:	f7ff fe88 	bl	540 <boot_validate_slot.isra.0>

00000830 <FIH_LABEL_FIH_CALL_END_1863>:
        if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     830:	4b3a      	ldr	r3, [pc, #232]	; (91c <FIH_LABEL_FIH_CALL_END_2144+0x48>)
     832:	681b      	ldr	r3, [r3, #0]
     834:	4298      	cmp	r0, r3
     836:	d003      	beq.n	840 <__z_interrupt_stack_SIZEOF>
                swap_type = BOOT_SWAP_TYPE_NONE;
     838:	2801      	cmp	r0, #1
     83a:	bf14      	ite	ne
     83c:	2705      	movne	r7, #5
     83e:	2701      	moveq	r7, #1
                BOOT_SWAP_TYPE(state) = boot_validated_swap_type(state, bs);
     840:	f884 7058 	strb.w	r7, [r4, #88]	; 0x58
     844:	e7ce      	b.n	7e4 <context_boot_go+0xdc>

00000846 <FIH_LABEL_FIH_CALL_START_1899>:
                FIH_CALL(boot_validate_slot, fih_rc,
     846:	2101      	movs	r1, #1
     848:	4620      	mov	r0, r4
     84a:	f7ff fe79 	bl	540 <boot_validate_slot.isra.0>

0000084e <FIH_LABEL_FIH_CALL_END_1914>:
                if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     84e:	4b33      	ldr	r3, [pc, #204]	; (91c <FIH_LABEL_FIH_CALL_END_2144+0x48>)
     850:	681b      	ldr	r3, [r3, #0]
     852:	4298      	cmp	r0, r3
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     854:	bf0c      	ite	eq
     856:	f89d 3007 	ldrbeq.w	r3, [sp, #7]
                    BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
     85a:	2305      	movne	r3, #5
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     85c:	e7d5      	b.n	80a <CONFIG_ISR_STACK_SIZE+0xa>
        switch (BOOT_SWAP_TYPE(state)) {
     85e:	2b05      	cmp	r3, #5
     860:	d1c9      	bne.n	7f6 <context_boot_go+0xee>
            rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     862:	2000      	movs	r0, #0
     864:	f005 f865 	bl	5932 <swap_set_image_ok>
     868:	e012      	b.n	890 <FIH_LABEL_FIH_CALL_END_1914+0x42>
        rc = boot_swap_image(state, bs);
     86a:	4669      	mov	r1, sp
     86c:	4620      	mov	r0, r4
     86e:	f7ff fed7 	bl	620 <boot_swap_image>
    swap_type = BOOT_SWAP_TYPE(state);
     872:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     876:	1eda      	subs	r2, r3, #3
     878:	2a01      	cmp	r2, #1
        rc = boot_swap_image(state, bs);
     87a:	4605      	mov	r5, r0
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     87c:	d80b      	bhi.n	896 <FIH_LABEL_FIH_CALL_END_1914+0x48>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     87e:	2000      	movs	r0, #0
     880:	f005 f857 	bl	5932 <swap_set_image_ok>
        if (rc != 0) {
     884:	4605      	mov	r5, r0
     886:	2800      	cmp	r0, #0
     888:	d1b5      	bne.n	7f6 <context_boot_go+0xee>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     88a:	2000      	movs	r0, #0
     88c:	f005 f83f 	bl	590e <swap_set_copy_done>
            if (rc != 0) {
     890:	4605      	mov	r5, r0
     892:	b110      	cbz	r0, 89a <FIH_LABEL_FIH_CALL_END_1914+0x4c>
     894:	e7af      	b.n	7f6 <context_boot_go+0xee>
    if (BOOT_IS_UPGRADE(swap_type)) {
     896:	2b02      	cmp	r3, #2
     898:	d0f7      	beq.n	88a <FIH_LABEL_FIH_CALL_END_1914+0x3c>
        }

        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     89a:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     89e:	2bff      	cmp	r3, #255	; 0xff
     8a0:	d100      	bne.n	8a4 <FIH_LABEL_FIH_CALL_END_1914+0x56>
            BOOT_LOG_ERR("panic!");
            assert(0);

            /* Loop forever... */
            FIH_PANIC;
     8a2:	e7fe      	b.n	8a2 <FIH_LABEL_FIH_CALL_END_1914+0x54>
#if BOOT_IMAGE_NUMBER > 1
        if (state->img_mask[BOOT_CURR_IMG(state)]) {
            continue;
        }
#endif
        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE) {
     8a4:	2b01      	cmp	r3, #1
     8a6:	d010      	beq.n	8ca <FIH_LABEL_FIH_CALL_START_2129>
            /* Attempt to read an image header from each slot. Ensure that image
             * headers in slots are aligned with headers in boot_data.
             */
            rc = boot_read_image_headers(state, false, &bs);
     8a8:	466a      	mov	r2, sp
     8aa:	2100      	movs	r1, #0
     8ac:	4620      	mov	r0, r4
     8ae:	f004 feda 	bl	5666 <boot_read_image_headers>
            if (rc != 0) {
     8b2:	4605      	mov	r5, r0
     8b4:	b148      	cbz	r0, 8ca <FIH_LABEL_FIH_CALL_START_2129>
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     8b6:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     8b8:	f005 fab3 	bl	5e22 <flash_area_close>
     8bc:	6a20      	ldr	r0, [r4, #32]
     8be:	f005 fab0 	bl	5e22 <flash_area_close>
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     8c2:	4628      	mov	r0, r5
     8c4:	b004      	add	sp, #16
     8c6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000008ca <FIH_LABEL_FIH_CALL_START_2129>:
            FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_PRIMARY_SLOT, NULL);
     8ca:	2100      	movs	r1, #0
     8cc:	4620      	mov	r0, r4
     8ce:	f7ff fe37 	bl	540 <boot_validate_slot.isra.0>
     8d2:	4607      	mov	r7, r0

000008d4 <FIH_LABEL_FIH_CALL_END_2144>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     8d4:	f8df 8044 	ldr.w	r8, [pc, #68]	; 91c <FIH_LABEL_FIH_CALL_END_2144+0x48>
     8d8:	f8d8 3000 	ldr.w	r3, [r8]
     8dc:	4283      	cmp	r3, r0
     8de:	d10f      	bne.n	900 <FIH_LABEL_FIH_CALL_END_2144+0x2c>
    memset(&bs, 0, sizeof(struct boot_status));
     8e0:	2210      	movs	r2, #16
     8e2:	2100      	movs	r1, #0
     8e4:	4668      	mov	r0, sp
     8e6:	f005 fb52 	bl	5f8e <memset>
    rsp->br_flash_dev_id = flash_area_get_device_id(BOOT_IMG_AREA(state, active_slot));
     8ea:	6a20      	ldr	r0, [r4, #32]
     8ec:	f004 fdb2 	bl	5454 <flash_area_get_device_id>
     8f0:	7130      	strb	r0, [r6, #4]
 */
int flash_area_sector_from_off(off_t off, struct flash_sector *sector);

static inline uint32_t flash_area_get_off(const struct flash_area *fa)
{
	return (uint32_t)fa->fa_off;
     8f2:	6a23      	ldr	r3, [r4, #32]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     8f4:	685b      	ldr	r3, [r3, #4]
    rsp->br_hdr = boot_img_hdr(state, active_slot);
     8f6:	6034      	str	r4, [r6, #0]
    fih_rc = FIH_SUCCESS;
     8f8:	f8d8 5000 	ldr.w	r5, [r8]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     8fc:	60b3      	str	r3, [r6, #8]
    fih_rc = FIH_SUCCESS;
     8fe:	e7da      	b.n	8b6 <FIH_LABEL_FIH_CALL_END_1914+0x68>
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     900:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     902:	f005 fa8e 	bl	5e22 <flash_area_close>
     906:	6a20      	ldr	r0, [r4, #32]
     908:	f005 fa8b 	bl	5e22 <flash_area_close>
    if (rc) {
     90c:	2d00      	cmp	r5, #0
     90e:	bf08      	it	eq
     910:	463d      	moveq	r5, r7
     912:	e7d6      	b.n	8c2 <FIH_LABEL_FIH_CALL_END_1914+0x74>
     914:	2000092c 	.word	0x2000092c
     918:	2000012c 	.word	0x2000012c
     91c:	20000128 	.word	0x20000128

00000920 <boot_go>:
 *
 * @return                      FIH_SUCCESS on success; nonzero on failure.
 */
fih_int
boot_go(struct boot_rsp *rsp)
{
     920:	b538      	push	{r3, r4, r5, lr}
void boot_state_clear(struct boot_loader_state *state)
{
    if (state != NULL) {
        memset(state, 0, sizeof(struct boot_loader_state));
    } else {
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     922:	4d06      	ldr	r5, [pc, #24]	; (93c <FIH_LABEL_FIH_CALL_END_2763+0x4>)
{
     924:	4604      	mov	r4, r0
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     926:	2260      	movs	r2, #96	; 0x60
     928:	2100      	movs	r1, #0
     92a:	4628      	mov	r0, r5
     92c:	f005 fb2f 	bl	5f8e <memset>

00000930 <FIH_LABEL_FIH_CALL_START_2749>:
    FIH_CALL(context_boot_go, fih_rc, &boot_data, rsp);
     930:	4621      	mov	r1, r4
     932:	4628      	mov	r0, r5
     934:	f7ff fee8 	bl	708 <context_boot_go>

00000938 <FIH_LABEL_FIH_CALL_END_2763>:
}
     938:	bd38      	pop	{r3, r4, r5, pc}
     93a:	bf00      	nop
     93c:	2000152c 	.word	0x2000152c

00000940 <boot_read_image_header>:
static uint32_t g_last_idx = UINT32_MAX;

int
boot_read_image_header(struct boot_loader_state *state, int slot,
                       struct image_header *out_hdr, struct boot_status *bs)
{
     940:	b573      	push	{r0, r1, r4, r5, r6, lr}
     942:	4616      	mov	r6, r2
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    off = 0;
    if (bs) {
     944:	461d      	mov	r5, r3
     946:	b143      	cbz	r3, 95a <boot_read_image_header+0x1a>
        sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
        if (bs->op == BOOT_STATUS_OP_MOVE) {
     948:	795b      	ldrb	r3, [r3, #5]
     94a:	2b01      	cmp	r3, #1
     94c:	d107      	bne.n	95e <boot_read_image_header+0x1e>
            if (slot == 0 && bs->idx > g_last_idx) {
     94e:	b921      	cbnz	r1, 95a <boot_read_image_header+0x1a>
     950:	4b20      	ldr	r3, [pc, #128]	; (9d4 <boot_read_image_header+0x94>)
     952:	682a      	ldr	r2, [r5, #0]
     954:	681b      	ldr	r3, [r3, #0]
     956:	429a      	cmp	r2, r3
     958:	d817      	bhi.n	98a <boot_read_image_header+0x4a>
    off = 0;
     95a:	2400      	movs	r4, #0
     95c:	e018      	b.n	990 <boot_read_image_header+0x50>
                /* second sector */
                off = sz;
            }
        } else if (bs->op == BOOT_STATUS_OP_SWAP) {
     95e:	2b02      	cmp	r3, #2
     960:	d1fb      	bne.n	95a <boot_read_image_header+0x1a>
            if (bs->idx > 1 && bs->idx <= g_last_idx) {
     962:	682b      	ldr	r3, [r5, #0]
     964:	2b01      	cmp	r3, #1
     966:	d907      	bls.n	978 <boot_read_image_header+0x38>
     968:	4a1a      	ldr	r2, [pc, #104]	; (9d4 <boot_read_image_header+0x94>)
     96a:	6812      	ldr	r2, [r2, #0]
     96c:	4293      	cmp	r3, r2
     96e:	d8f4      	bhi.n	95a <boot_read_image_header+0x1a>
                if (slot == 0) {
     970:	fab1 f181 	clz	r1, r1
     974:	0949      	lsrs	r1, r1, #5
     976:	e7f0      	b.n	95a <boot_read_image_header+0x1a>
                    slot = 1;
                } else {
                    slot = 0;
                }
            } else if (bs->idx == 1) {
     978:	d1ef      	bne.n	95a <boot_read_image_header+0x1a>
                if (slot == 0) {
     97a:	b131      	cbz	r1, 98a <boot_read_image_header+0x4a>
                    off = sz;
                }
                if (slot == 1 && bs->state == 2) {
     97c:	2901      	cmp	r1, #1
     97e:	d1ec      	bne.n	95a <boot_read_image_header+0x1a>
     980:	7929      	ldrb	r1, [r5, #4]
     982:	3902      	subs	r1, #2
     984:	bf18      	it	ne
     986:	2101      	movne	r1, #1
     988:	e7e7      	b.n	95a <boot_read_image_header+0x1a>
	return fs->fs_off;
}

static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
{
	return fs->fs_size;
     98a:	6a43      	ldr	r3, [r0, #36]	; 0x24
     98c:	685c      	ldr	r4, [r3, #4]
     98e:	2100      	movs	r1, #0
                }
            }
        }
    }

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     990:	2000      	movs	r0, #0
     992:	f004 fd55 	bl	5440 <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     996:	a901      	add	r1, sp, #4
     998:	b2c0      	uxtb	r0, r0
     99a:	f000 faad 	bl	ef8 <flash_area_open>
    if (rc != 0) {
     99e:	b130      	cbz	r0, 9ae <boot_read_image_header+0x6e>
        rc = BOOT_EFLASH;
     9a0:	2401      	movs	r4, #1
    }

    rc = 0;

done:
    flash_area_close(fap);
     9a2:	9801      	ldr	r0, [sp, #4]
     9a4:	f005 fa3d 	bl	5e22 <flash_area_close>
    return rc;
}
     9a8:	4620      	mov	r0, r4
     9aa:	b002      	add	sp, #8
     9ac:	bd70      	pop	{r4, r5, r6, pc}
    rc = flash_area_read(fap, off, out_hdr, sizeof *out_hdr);
     9ae:	4621      	mov	r1, r4
     9b0:	9801      	ldr	r0, [sp, #4]
     9b2:	2320      	movs	r3, #32
     9b4:	4632      	mov	r2, r6
     9b6:	f005 fa35 	bl	5e24 <flash_area_read>
    if (rc != 0) {
     9ba:	4604      	mov	r4, r0
     9bc:	2800      	cmp	r0, #0
     9be:	d1ef      	bne.n	9a0 <boot_read_image_header+0x60>
    if (bs != NULL && out_hdr->ih_magic != IMAGE_MAGIC) {
     9c0:	2d00      	cmp	r5, #0
     9c2:	d0ee      	beq.n	9a2 <boot_read_image_header+0x62>
     9c4:	6834      	ldr	r4, [r6, #0]
     9c6:	4b04      	ldr	r3, [pc, #16]	; (9d8 <boot_read_image_header+0x98>)
     9c8:	1ae4      	subs	r4, r4, r3
     9ca:	bf18      	it	ne
     9cc:	f04f 34ff 	movne.w	r4, #4294967295
     9d0:	e7e7      	b.n	9a2 <boot_read_image_header+0x62>
     9d2:	bf00      	nop
     9d4:	20000004 	.word	0x20000004
     9d8:	96f3b83d 	.word	0x96f3b83d

000009dc <fixup_revert>:
 * upgrade (by initializing the secondary slot).
 */
void
fixup_revert(const struct boot_loader_state *state, struct boot_status *bs,
        const struct flash_area *fap_sec)
{
     9dc:	b573      	push	{r0, r1, r4, r5, r6, lr}
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    /* No fixup required */
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     9de:	684b      	ldr	r3, [r1, #4]
{
     9e0:	4614      	mov	r4, r2
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     9e2:	4a11      	ldr	r2, [pc, #68]	; (a28 <fixup_revert+0x4c>)
     9e4:	f003 23ff 	and.w	r3, r3, #4278255360	; 0xff00ff00
     9e8:	4293      	cmp	r3, r2
{
     9ea:	4606      	mov	r6, r0
     9ec:	460d      	mov	r5, r1
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     9ee:	d118      	bne.n	a22 <fixup_revert+0x46>
        bs->op != BOOT_STATUS_OP_MOVE ||
     9f0:	680b      	ldr	r3, [r1, #0]
     9f2:	2b01      	cmp	r3, #1
     9f4:	d115      	bne.n	a22 <fixup_revert+0x46>
        bs->idx != BOOT_STATUS_IDX_0) {
        return;
    }

    rc = boot_read_swap_state(fap_sec, &swap_state);
     9f6:	4669      	mov	r1, sp
     9f8:	4620      	mov	r0, r4
     9fa:	f001 fefb 	bl	27f4 <boot_read_swap_state>
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);

    if (swap_state.magic == BOOT_MAGIC_UNSET) {
     9fe:	f89d 3000 	ldrb.w	r3, [sp]
     a02:	2b03      	cmp	r3, #3
     a04:	d10d      	bne.n	a22 <fixup_revert+0x46>
        rc = swap_erase_trailer_sectors(state, fap_sec);
     a06:	4621      	mov	r1, r4
     a08:	4630      	mov	r0, r6
     a0a:	f004 feef 	bl	57ec <swap_erase_trailer_sectors>
        assert(rc == 0);

        rc = boot_write_image_ok(fap_sec);
     a0e:	4620      	mov	r0, r4
     a10:	f005 fd79 	bl	6506 <boot_write_image_ok>
        assert(rc == 0);

        rc = boot_write_swap_size(fap_sec, bs->swap_size);
     a14:	68a9      	ldr	r1, [r5, #8]
     a16:	4620      	mov	r0, r4
     a18:	f004 fe09 	bl	562e <boot_write_swap_size>
        assert(rc == 0);

        rc = boot_write_magic(fap_sec);
     a1c:	4620      	mov	r0, r4
     a1e:	f001 fec9 	bl	27b4 <boot_write_magic>
        assert(rc == 0);
    }
}
     a22:	b002      	add	sp, #8
     a24:	bd70      	pop	{r4, r5, r6, pc}
     a26:	bf00      	nop
     a28:	04000100 	.word	0x04000100

00000a2c <swap_run>:

void
swap_run(struct boot_loader_state *state, struct boot_status *bs,
         uint32_t copy_size)
{
     a2c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     a30:	6a43      	ldr	r3, [r0, #36]	; 0x24
     a32:	460c      	mov	r4, r1
     a34:	685e      	ldr	r6, [r3, #4]
     a36:	b089      	sub	sp, #36	; 0x24
     a38:	4605      	mov	r5, r0
     a3a:	2101      	movs	r1, #1
    const struct flash_area *fap_sec;
    int rc;

    BOOT_LOG_INF("Starting swap using move algorithm.");

    sz = 0;
     a3c:	2300      	movs	r3, #0
    g_last_idx = 0;

    sector_sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
    while (1) {
        sz += sector_sz;
     a3e:	4433      	add	r3, r6
        /* Skip to next sector because all sectors will be moved up. */
        g_last_idx++;
        if (sz >= copy_size) {
     a40:	4293      	cmp	r3, r2
     a42:	4608      	mov	r0, r1
     a44:	f101 0101 	add.w	r1, r1, #1
     a48:	d3f9      	bcc.n	a3e <swap_run+0x12>
     a4a:	f8df 81bc 	ldr.w	r8, [pc, #444]	; c08 <swap_run+0x1dc>
     a4e:	f8c8 0000 	str.w	r0, [r8]
    }

    /*
     * When starting a new swap upgrade, check that there is enough space.
     */
    if (boot_status_is_reset(bs)) {
     a52:	4620      	mov	r0, r4
     a54:	f004 fe89 	bl	576a <boot_status_is_reset>
     a58:	b198      	cbz	r0, a82 <swap_run+0x56>
        sz = 0;
        trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
     a5a:	6de8      	ldr	r0, [r5, #92]	; 0x5c
     a5c:	f004 fdc5 	bl	55ea <boot_trailer_sz>
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
     a60:	6aab      	ldr	r3, [r5, #40]	; 0x28
        sz = 0;
     a62:	2200      	movs	r2, #0
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
     a64:	3b01      	subs	r3, #1

        while (1) {
            sz += sector_sz;
     a66:	4432      	add	r2, r6
            if  (sz >= trailer_sz) {
     a68:	4290      	cmp	r0, r2
     a6a:	d901      	bls.n	a70 <swap_run+0x44>
                break;
            }
            first_trailer_idx--;
     a6c:	3b01      	subs	r3, #1
            sz += sector_sz;
     a6e:	e7fa      	b.n	a66 <swap_run+0x3a>
        }

        if (g_last_idx >= first_trailer_idx) {
     a70:	f8d8 2000 	ldr.w	r2, [r8]
     a74:	429a      	cmp	r2, r3
     a76:	d304      	bcc.n	a82 <swap_run+0x56>
            BOOT_LOG_WRN("Not enough free space to run swap upgrade");
            BOOT_LOG_WRN("required %d bytes but only %d are available",
                         (g_last_idx + 1) * sector_sz ,
                         first_trailer_idx * sector_sz);
            bs->swap_type = BOOT_SWAP_TYPE_NONE;
     a78:	2301      	movs	r3, #1
     a7a:	71e3      	strb	r3, [r4, #7]
        idx++;
    }

    flash_area_close(fap_pri);
    flash_area_close(fap_sec);
}
     a7c:	b009      	add	sp, #36	; 0x24
     a7e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index), &fap_pri);
     a82:	a906      	add	r1, sp, #24
     a84:	2003      	movs	r0, #3
     a86:	f000 fa37 	bl	ef8 <flash_area_open>
    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index), &fap_sec);
     a8a:	a907      	add	r1, sp, #28
     a8c:	2001      	movs	r0, #1
     a8e:	f000 fa33 	bl	ef8 <flash_area_open>
    fixup_revert(state, bs, fap_sec);
     a92:	9a07      	ldr	r2, [sp, #28]
     a94:	4621      	mov	r1, r4
     a96:	4628      	mov	r0, r5
     a98:	f7ff ffa0 	bl	9dc <fixup_revert>
    if (bs->op == BOOT_STATUS_OP_MOVE) {
     a9c:	7963      	ldrb	r3, [r4, #5]
     a9e:	2b01      	cmp	r3, #1
     aa0:	d10a      	bne.n	ab8 <swap_run+0x8c>
        idx = g_last_idx;
     aa2:	f8d8 7000 	ldr.w	r7, [r8]
    BOOT_STATUS_ASSERT(rc == 0);
     aa6:	f8df b15c 	ldr.w	fp, [pc, #348]	; c04 <swap_run+0x1d8>
            if (idx <= (g_last_idx - bs->idx + 1)) {
     aaa:	f8d8 3000 	ldr.w	r3, [r8]
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
     aae:	f8dd 9018 	ldr.w	r9, [sp, #24]
        while (idx > 0) {
     ab2:	b98f      	cbnz	r7, ad8 <swap_run+0xac>
        bs->idx = BOOT_STATUS_IDX_0;
     ab4:	2301      	movs	r3, #1
     ab6:	6023      	str	r3, [r4, #0]
    bs->op = BOOT_STATUS_OP_SWAP;
     ab8:	2302      	movs	r3, #2
     aba:	7163      	strb	r3, [r4, #5]
    idx = 1;
     abc:	2701      	movs	r7, #1
    while (idx <= g_last_idx) {
     abe:	f8d8 3000 	ldr.w	r3, [r8]
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
     ac2:	f8dd a018 	ldr.w	sl, [sp, #24]
    while (idx <= g_last_idx) {
     ac6:	42bb      	cmp	r3, r7
     ac8:	d248      	bcs.n	b5c <swap_run+0x130>
    flash_area_close(fap_pri);
     aca:	4650      	mov	r0, sl
     acc:	f005 f9a9 	bl	5e22 <flash_area_close>
    flash_area_close(fap_sec);
     ad0:	9807      	ldr	r0, [sp, #28]
     ad2:	f005 f9a6 	bl	5e22 <flash_area_close>
     ad6:	e7d1      	b.n	a7c <swap_run+0x50>
            if (idx <= (g_last_idx - bs->idx + 1)) {
     ad8:	6822      	ldr	r2, [r4, #0]
     ada:	3301      	adds	r3, #1
     adc:	1a9b      	subs	r3, r3, r2
     ade:	42bb      	cmp	r3, r7
     ae0:	d33a      	bcc.n	b58 <swap_run+0x12c>

static inline uint32_t
boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
                    size_t sector)
{
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
     ae2:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	return fs->fs_off;
     ae4:	6819      	ldr	r1, [r3, #0]
     ae6:	f853 0037 	ldr.w	r0, [r3, r7, lsl #3]
     aea:	eb03 03c7 	add.w	r3, r3, r7, lsl #3
    if (bs->idx == BOOT_STATUS_IDX_0) {
     aee:	2a01      	cmp	r2, #1
     af0:	f853 3c08 	ldr.w	r3, [r3, #-8]
     af4:	eba3 0301 	sub.w	r3, r3, r1
     af8:	eba0 0a01 	sub.w	sl, r0, r1
     afc:	9304      	str	r3, [sp, #16]
     afe:	d111      	bne.n	b24 <swap_run+0xf8>
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
     b00:	9b07      	ldr	r3, [sp, #28]
     b02:	9303      	str	r3, [sp, #12]
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
     b04:	68e3      	ldr	r3, [r4, #12]
     b06:	2b02      	cmp	r3, #2
     b08:	d008      	beq.n	b1c <swap_run+0xf0>
            rc = swap_erase_trailer_sectors(state, fap_pri);
     b0a:	4649      	mov	r1, r9
     b0c:	4628      	mov	r0, r5
     b0e:	f004 fe6d 	bl	57ec <swap_erase_trailer_sectors>
            rc = swap_status_init(state, fap_pri, bs);
     b12:	4622      	mov	r2, r4
     b14:	4649      	mov	r1, r9
     b16:	4628      	mov	r0, r5
     b18:	f004 fe9d 	bl	5856 <swap_status_init>
        rc = swap_erase_trailer_sectors(state, fap_sec);
     b1c:	9903      	ldr	r1, [sp, #12]
     b1e:	4628      	mov	r0, r5
     b20:	f004 fe64 	bl	57ec <swap_erase_trailer_sectors>
    rc = boot_erase_region(fap_pri, new_off, sz);
     b24:	4632      	mov	r2, r6
     b26:	4651      	mov	r1, sl
     b28:	4648      	mov	r0, r9
     b2a:	f004 fe5d 	bl	57e8 <boot_erase_region>
    rc = boot_copy_region(state, fap_pri, fap_pri, old_off, new_off, sz);
     b2e:	9b04      	ldr	r3, [sp, #16]
     b30:	464a      	mov	r2, r9
     b32:	4649      	mov	r1, r9
     b34:	e9cd a600 	strd	sl, r6, [sp]
     b38:	4628      	mov	r0, r5
     b3a:	f7ff fda3 	bl	684 <boot_copy_region>
    rc = boot_write_status(state, bs);
     b3e:	4621      	mov	r1, r4
     b40:	4628      	mov	r0, r5
     b42:	f004 fe1f 	bl	5784 <boot_write_status>
    bs->idx++;
     b46:	6823      	ldr	r3, [r4, #0]
     b48:	3301      	adds	r3, #1
     b4a:	6023      	str	r3, [r4, #0]
    BOOT_STATUS_ASSERT(rc == 0);
     b4c:	b120      	cbz	r0, b58 <swap_run+0x12c>
     b4e:	f8db 3000 	ldr.w	r3, [fp]
     b52:	3301      	adds	r3, #1
     b54:	f8cb 3000 	str.w	r3, [fp]
            idx--;
     b58:	3f01      	subs	r7, #1
     b5a:	e7a6      	b.n	aaa <swap_run+0x7e>
        if (idx >= bs->idx) {
     b5c:	6823      	ldr	r3, [r4, #0]
     b5e:	42bb      	cmp	r3, r7
     b60:	d84d      	bhi.n	bfe <swap_run+0x1d2>
     b62:	6a6a      	ldr	r2, [r5, #36]	; 0x24
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
     b64:	f8dd b01c 	ldr.w	fp, [sp, #28]
     b68:	f852 1037 	ldr.w	r1, [r2, r7, lsl #3]
     b6c:	9104      	str	r1, [sp, #16]
     b6e:	00fb      	lsls	r3, r7, #3
     b70:	3b08      	subs	r3, #8
     b72:	6811      	ldr	r1, [r2, #0]
     b74:	9103      	str	r1, [sp, #12]
     b76:	58d1      	ldr	r1, [r2, r3]
     b78:	6d2a      	ldr	r2, [r5, #80]	; 0x50
     b7a:	58d0      	ldr	r0, [r2, r3]
     b7c:	6813      	ldr	r3, [r2, #0]
     b7e:	eba0 0903 	sub.w	r9, r0, r3
    if (bs->state == BOOT_STATUS_STATE_0) {
     b82:	7923      	ldrb	r3, [r4, #4]
     b84:	2b01      	cmp	r3, #1
     b86:	d138      	bne.n	bfa <swap_run+0x1ce>
     b88:	9b03      	ldr	r3, [sp, #12]
        rc = boot_erase_region(fap_pri, pri_off, sz);
     b8a:	4632      	mov	r2, r6
     b8c:	1ac9      	subs	r1, r1, r3
     b8e:	4650      	mov	r0, sl
     b90:	9105      	str	r1, [sp, #20]
     b92:	f004 fe29 	bl	57e8 <boot_erase_region>
        rc = boot_copy_region(state, fap_sec, fap_pri, sec_off, pri_off, sz);
     b96:	9905      	ldr	r1, [sp, #20]
     b98:	9100      	str	r1, [sp, #0]
     b9a:	464b      	mov	r3, r9
     b9c:	4652      	mov	r2, sl
     b9e:	4659      	mov	r1, fp
     ba0:	9601      	str	r6, [sp, #4]
     ba2:	4628      	mov	r0, r5
     ba4:	f7ff fd6e 	bl	684 <boot_copy_region>
        rc = boot_write_status(state, bs);
     ba8:	4621      	mov	r1, r4
     baa:	4628      	mov	r0, r5
     bac:	f004 fdea 	bl	5784 <boot_write_status>
        bs->state = BOOT_STATUS_STATE_1;
     bb0:	2302      	movs	r3, #2
     bb2:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
     bb4:	b118      	cbz	r0, bbe <swap_run+0x192>
     bb6:	4a13      	ldr	r2, [pc, #76]	; (c04 <swap_run+0x1d8>)
     bb8:	6813      	ldr	r3, [r2, #0]
     bba:	3301      	adds	r3, #1
     bbc:	6013      	str	r3, [r2, #0]
        rc = boot_erase_region(fap_sec, sec_off, sz);
     bbe:	4632      	mov	r2, r6
     bc0:	4649      	mov	r1, r9
     bc2:	4658      	mov	r0, fp
     bc4:	f004 fe10 	bl	57e8 <boot_erase_region>
        rc = boot_copy_region(state, fap_pri, fap_sec, pri_up_off, sec_off, sz);
     bc8:	e9dd 2303 	ldrd	r2, r3, [sp, #12]
     bcc:	4651      	mov	r1, sl
     bce:	1a9b      	subs	r3, r3, r2
     bd0:	e9cd 9600 	strd	r9, r6, [sp]
     bd4:	465a      	mov	r2, fp
     bd6:	4628      	mov	r0, r5
     bd8:	f7ff fd54 	bl	684 <boot_copy_region>
        rc = boot_write_status(state, bs);
     bdc:	4621      	mov	r1, r4
     bde:	4628      	mov	r0, r5
     be0:	f004 fdd0 	bl	5784 <boot_write_status>
        bs->idx++;
     be4:	6823      	ldr	r3, [r4, #0]
     be6:	3301      	adds	r3, #1
     be8:	6023      	str	r3, [r4, #0]
        bs->state = BOOT_STATUS_STATE_0;
     bea:	2301      	movs	r3, #1
     bec:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
     bee:	b130      	cbz	r0, bfe <swap_run+0x1d2>
     bf0:	4a04      	ldr	r2, [pc, #16]	; (c04 <swap_run+0x1d8>)
     bf2:	6813      	ldr	r3, [r2, #0]
     bf4:	3301      	adds	r3, #1
     bf6:	6013      	str	r3, [r2, #0]
     bf8:	e001      	b.n	bfe <swap_run+0x1d2>
    if (bs->state == BOOT_STATUS_STATE_1) {
     bfa:	2b02      	cmp	r3, #2
     bfc:	d0df      	beq.n	bbe <swap_run+0x192>
        idx++;
     bfe:	3701      	adds	r7, #1
     c00:	e75d      	b.n	abe <swap_run+0x92>
     c02:	bf00      	nop
     c04:	2000158c 	.word	0x2000158c
     c08:	20000004 	.word	0x20000004

00000c0c <cc310_init>:
 */

#include "cc310_glue.h"

int cc310_init(void)
{
     c0c:	b570      	push	{r4, r5, r6, lr}
    /* Only initialize once */
    static bool initialized;

    if (!initialized) {
     c0e:	4d09      	ldr	r5, [pc, #36]	; (c34 <cc310_init+0x28>)
     c10:	782b      	ldrb	r3, [r5, #0]
     c12:	b10b      	cbz	r3, c18 <cc310_init+0xc>
        }
        initialized = true;
        nrf_cc310_disable();
    }

    return 0;
     c14:	2000      	movs	r0, #0
}
     c16:	bd70      	pop	{r4, r5, r6, pc}
    NRF_CRYPTOCELL->ENABLE=1;
     c18:	4c07      	ldr	r4, [pc, #28]	; (c38 <cc310_init+0x2c>)
     c1a:	2601      	movs	r6, #1
     c1c:	f8c4 6500 	str.w	r6, [r4, #1280]	; 0x500
        if (nrf_cc310_bl_init() != 0) {
     c20:	f003 fbea 	bl	43f8 <nrf_cc310_bl_init>
     c24:	b918      	cbnz	r0, c2e <cc310_init+0x22>
        initialized = true;
     c26:	702e      	strb	r6, [r5, #0]
    NRF_CRYPTOCELL->ENABLE=0;
     c28:	f8c4 0500 	str.w	r0, [r4, #1280]	; 0x500
}
     c2c:	e7f2      	b.n	c14 <cc310_init+0x8>
            return -1;
     c2e:	f04f 30ff 	mov.w	r0, #4294967295
     c32:	e7f0      	b.n	c16 <cc310_init+0xa>
     c34:	200017f4 	.word	0x200017f4
     c38:	5002a000 	.word	0x5002a000

00000c3c <cc310_ecdsa_verify_secp256r1>:

int cc310_ecdsa_verify_secp256r1(uint8_t *hash,
                                 uint8_t *public_key,
                                 uint8_t *signature,
                                 size_t hash_len)
{
     c3c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    NRF_CRYPTOCELL->ENABLE=1;
     c40:	f8df 8030 	ldr.w	r8, [pc, #48]	; c74 <cc310_ecdsa_verify_secp256r1+0x38>
     c44:	b0ac      	sub	sp, #176	; 0xb0
     c46:	461f      	mov	r7, r3
     c48:	4606      	mov	r6, r0
     c4a:	460c      	mov	r4, r1
     c4c:	4615      	mov	r5, r2
        int rc;
        nrf_cc310_bl_ecdsa_verify_context_secp256r1_t ctx;
        cc310_init();
     c4e:	f7ff ffdd 	bl	c0c <cc310_init>
     c52:	2301      	movs	r3, #1
     c54:	f8c8 3500 	str.w	r3, [r8, #1280]	; 0x500
        nrf_cc310_enable();
        rc = nrf_cc310_bl_ecdsa_verify_secp256r1(&ctx,
     c58:	462a      	mov	r2, r5
     c5a:	4633      	mov	r3, r6
     c5c:	9700      	str	r7, [sp, #0]
     c5e:	4621      	mov	r1, r4
     c60:	a803      	add	r0, sp, #12
     c62:	f005 fd86 	bl	6772 <nrf_cc310_bl_ecdsa_verify_secp256r1>
    NRF_CRYPTOCELL->ENABLE=0;
     c66:	2300      	movs	r3, #0
     c68:	f8c8 3500 	str.w	r3, [r8, #1280]	; 0x500
                                                 (nrf_cc310_bl_ecc_signature_secp256r1_t  *) signature,
                                                 hash,
                                                 hash_len);
        nrf_cc310_disable();
        return rc;
}
     c6c:	b02c      	add	sp, #176	; 0xb0
     c6e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
     c72:	bf00      	nop
     c74:	5002a000 	.word	0x5002a000

00000c78 <nrf_cleanup_peripheral>:
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
     c78:	4a16      	ldr	r2, [pc, #88]	; (cd4 <nrf_cleanup_peripheral+0x5c>)
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
     c7a:	f04f 33ff 	mov.w	r3, #4294967295
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
     c7e:	2101      	movs	r1, #1
     c80:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
     c82:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
     c86:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
     c8a:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
     c8e:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
     c90:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
     c94:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
     c98:	f502 3298 	add.w	r2, r2, #77824	; 0x13000
     c9c:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
     c9e:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
     ca2:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
}

NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
{
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
     ca6:	f5a2 3208 	sub.w	r2, r2, #139264	; 0x22000
     caa:	2100      	movs	r1, #0
     cac:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
     cb0:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
     cb4:	f502 3218 	add.w	r2, r2, #155648	; 0x26000
     cb8:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
     cbc:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    }
}

NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
{
    p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
     cc0:	f5a2 4210 	sub.w	r2, r2, #36864	; 0x9000
     cc4:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
     cc8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
     ccc:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
#endif
#if defined(NRF_DPPIC)
    nrf_dppi_channels_disable_all(NRF_DPPIC);
#endif
    nrf_cleanup_clock();
}
     cd0:	4770      	bx	lr
     cd2:	bf00      	nop
     cd4:	4000b000 	.word	0x4000b000

00000cd8 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     cd8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     cdc:	8b05      	ldrh	r5, [r0, #24]
{
     cde:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     ce0:	0728      	lsls	r0, r5, #28
{
     ce2:	4690      	mov	r8, r2
	if (processing) {
     ce4:	d411      	bmi.n	d0a <process_event+0x32>

	sys_slist_init(&clients);
	do {
		onoff_transition_fn transit = NULL;

		if (evt == EVT_RECHECK) {
     ce6:	2902      	cmp	r1, #2
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     ce8:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
     cec:	f040 80cd 	bne.w	e8a <process_event+0x1b2>
			evt = process_recheck(mgr);
     cf0:	4620      	mov	r0, r4
     cf2:	f004 ffbb 	bl	5c6c <process_recheck>
		}

		if (evt == EVT_NOP) {
     cf6:	b178      	cbz	r0, d18 <process_event+0x40>
			break;
		}

		res = 0;
		if (evt == EVT_COMPLETE) {
     cf8:	3801      	subs	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     cfa:	8b21      	ldrh	r1, [r4, #24]
     cfc:	2804      	cmp	r0, #4
     cfe:	d811      	bhi.n	d24 <process_event+0x4c>
     d00:	e8df f000 	tbb	[pc, r0]
     d04:	856d10c3 	.word	0x856d10c3
     d08:	95          	.byte	0x95
     d09:	00          	.byte	0x00
		if (evt == EVT_COMPLETE) {
     d0a:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     d0c:	bf0c      	ite	eq
     d0e:	f045 0510 	orreq.w	r5, r5, #16
			mgr->flags |= ONOFF_FLAG_RECHECK;
     d12:	f045 0520 	orrne.w	r5, r5, #32
     d16:	8325      	strh	r5, [r4, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     d18:	f388 8811 	msr	BASEPRI, r8
     d1c:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     d20:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     d24:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     d28:	45aa      	cmp	sl, r5
     d2a:	f000 80a6 	beq.w	e7a <process_event+0x1a2>
	 * a memory barrier when used like this, and we don't have a
	 * Zephyr framework for that.
	 */
	atomic_clear(&l->locked);
#endif
	arch_irq_unlock(key.key);
     d2e:	2700      	movs	r7, #0
     d30:	46b9      	mov	r9, r7
     d32:	463e      	mov	r6, r7
     d34:	68a3      	ldr	r3, [r4, #8]
     d36:	2b00      	cmp	r3, #0
     d38:	f000 80bd 	beq.w	eb6 <process_event+0x1de>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     d3c:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     d40:	8321      	strh	r1, [r4, #24]
     d42:	f388 8811 	msr	BASEPRI, r8
     d46:	f3bf 8f6f 	isb	sy
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     d4a:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     d4c:	2900      	cmp	r1, #0
     d4e:	f000 80bb 	beq.w	ec8 <process_event+0x1f0>
	return node->next;
     d52:	680d      	ldr	r5, [r1, #0]
     d54:	2900      	cmp	r1, #0
     d56:	f000 80b7 	beq.w	ec8 <process_event+0x1f0>
		mon->callback(mgr, mon, state, res);
     d5a:	f8d1 8004 	ldr.w	r8, [r1, #4]
     d5e:	4633      	mov	r3, r6
     d60:	4652      	mov	r2, sl
     d62:	4620      	mov	r0, r4
     d64:	47c0      	blx	r8
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     d66:	2d00      	cmp	r5, #0
     d68:	d076      	beq.n	e58 <process_event+0x180>
     d6a:	682b      	ldr	r3, [r5, #0]
     d6c:	4629      	mov	r1, r5
     d6e:	461d      	mov	r5, r3
     d70:	e7f0      	b.n	d54 <process_event+0x7c>
     d72:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     d76:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     d78:	2a01      	cmp	r2, #1
     d7a:	d81b      	bhi.n	db4 <process_event+0xdc>
	list->head = NULL;
     d7c:	2200      	movs	r2, #0
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     d7e:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     d82:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     d84:	6827      	ldr	r7, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     d86:	b289      	uxth	r1, r1
	list->tail = NULL;
     d88:	e9c4 2200 	strd	r2, r2, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     d8c:	d109      	bne.n	da2 <process_event+0xca>
     d8e:	463b      	mov	r3, r7
     d90:	e003      	b.n	d9a <process_event+0xc2>
				mgr->refs += 1U;
     d92:	8b62      	ldrh	r2, [r4, #26]
     d94:	3201      	adds	r2, #1
     d96:	8362      	strh	r2, [r4, #26]
	return node->next;
     d98:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     d9a:	2b00      	cmp	r3, #0
     d9c:	d1f9      	bne.n	d92 <process_event+0xba>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     d9e:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
     da2:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     da4:	4620      	mov	r0, r4
     da6:	f004 ff61 	bl	5c6c <process_recheck>
     daa:	2800      	cmp	r0, #0
     dac:	d07b      	beq.n	ea6 <process_event+0x1ce>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     dae:	f041 0120 	orr.w	r1, r1, #32
     db2:	e077      	b.n	ea4 <process_event+0x1cc>
	} else if (state == ONOFF_STATE_TO_OFF) {
     db4:	2b04      	cmp	r3, #4
     db6:	d10a      	bne.n	dce <process_event+0xf6>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     db8:	f021 0107 	bic.w	r1, r1, #7
     dbc:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
     dbe:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     dc0:	4620      	mov	r0, r4
     dc2:	f004 ff53 	bl	5c6c <process_recheck>
     dc6:	b110      	cbz	r0, dce <process_event+0xf6>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     dc8:	f041 0120 	orr.w	r1, r1, #32
     dcc:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     dce:	8b21      	ldrh	r1, [r4, #24]
     dd0:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     dd4:	45aa      	cmp	sl, r5
     dd6:	d050      	beq.n	e7a <process_event+0x1a2>
     dd8:	2700      	movs	r7, #0
		onoff_transition_fn transit = NULL;
     dda:	46b9      	mov	r9, r7
     ddc:	e7aa      	b.n	d34 <process_event+0x5c>
			transit = mgr->transitions->start;
     dde:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     de0:	f021 0107 	bic.w	r1, r1, #7
     de4:	f041 0106 	orr.w	r1, r1, #6
				   && !sys_slist_is_empty(&mgr->monitors);
     de8:	2d06      	cmp	r5, #6
			transit = mgr->transitions->start;
     dea:	f8d3 9000 	ldr.w	r9, [r3]
	mgr->flags = (state & ONOFF_STATE_MASK)
     dee:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     df0:	d12d      	bne.n	e4e <process_event+0x176>
		    || (transit != NULL)) {
     df2:	f1b9 0f00 	cmp.w	r9, #0
     df6:	d040      	beq.n	e7a <process_event+0x1a2>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     df8:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     dfc:	8321      	strh	r1, [r4, #24]
     dfe:	f388 8811 	msr	BASEPRI, r8
     e02:	f3bf 8f6f 	isb	sy
				transit(mgr, transition_complete);
     e06:	493a      	ldr	r1, [pc, #232]	; (ef0 <process_event+0x218>)
     e08:	4620      	mov	r0, r4
     e0a:	47c8      	blx	r9
     e0c:	e029      	b.n	e62 <process_event+0x18a>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e0e:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->stop;
     e12:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e14:	f041 0104 	orr.w	r1, r1, #4
     e18:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
     e1a:	2d04      	cmp	r5, #4
			transit = mgr->transitions->stop;
     e1c:	f8d3 9004 	ldr.w	r9, [r3, #4]
	mgr->flags = (state & ONOFF_STATE_MASK)
     e20:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     e22:	d0e6      	beq.n	df2 <process_event+0x11a>
     e24:	2700      	movs	r7, #0
		res = 0;
     e26:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     e28:	f04f 0a04 	mov.w	sl, #4
     e2c:	e782      	b.n	d34 <process_event+0x5c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e2e:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->reset;
     e32:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e34:	f041 0105 	orr.w	r1, r1, #5
     e38:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
     e3a:	2d05      	cmp	r5, #5
			transit = mgr->transitions->reset;
     e3c:	f8d3 9008 	ldr.w	r9, [r3, #8]
	mgr->flags = (state & ONOFF_STATE_MASK)
     e40:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     e42:	d0d6      	beq.n	df2 <process_event+0x11a>
     e44:	2700      	movs	r7, #0
		res = 0;
     e46:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     e48:	f04f 0a05 	mov.w	sl, #5
     e4c:	e772      	b.n	d34 <process_event+0x5c>
				   && !sys_slist_is_empty(&mgr->monitors);
     e4e:	2700      	movs	r7, #0
		res = 0;
     e50:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     e52:	f04f 0a06 	mov.w	sl, #6
     e56:	e76d      	b.n	d34 <process_event+0x5c>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     e58:	462b      	mov	r3, r5
     e5a:	e787      	b.n	d6c <process_event+0x94>
			if (transit != NULL) {
     e5c:	f1b9 0f00 	cmp.w	r9, #0
     e60:	d1d1      	bne.n	e06 <process_event+0x12e>
	__asm__ volatile(
     e62:	f04f 0320 	mov.w	r3, #32
     e66:	f3ef 8811 	mrs	r8, BASEPRI
     e6a:	f383 8812 	msr	BASEPRI_MAX, r3
     e6e:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     e72:	8b23      	ldrh	r3, [r4, #24]
     e74:	f023 0308 	bic.w	r3, r3, #8
     e78:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     e7a:	8b25      	ldrh	r5, [r4, #24]
     e7c:	06ea      	lsls	r2, r5, #27
     e7e:	d52e      	bpl.n	ede <process_event+0x206>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     e80:	f025 0310 	bic.w	r3, r5, #16
     e84:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     e86:	f005 0507 	and.w	r5, r5, #7
			res = mgr->last_res;
     e8a:	6966      	ldr	r6, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     e8c:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     e8e:	2e00      	cmp	r6, #0
     e90:	f6bf af6f 	bge.w	d72 <process_event+0x9a>
	list->head = NULL;
     e94:	2300      	movs	r3, #0
		*clients = mgr->clients;
     e96:	6827      	ldr	r7, [r4, #0]
	list->tail = NULL;
     e98:	e9c4 3300 	strd	r3, r3, [r4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e9c:	f021 0107 	bic.w	r1, r1, #7
     ea0:	f041 0101 	orr.w	r1, r1, #1
			mgr->flags |= ONOFF_FLAG_RECHECK;
     ea4:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     ea6:	8b21      	ldrh	r1, [r4, #24]
     ea8:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     eac:	45aa      	cmp	sl, r5
     eae:	f04f 0900 	mov.w	r9, #0
     eb2:	f47f af3f 	bne.w	d34 <process_event+0x5c>
		    || !sys_slist_is_empty(&clients)
     eb6:	2f00      	cmp	r7, #0
     eb8:	d09b      	beq.n	df2 <process_event+0x11a>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     eba:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     ebe:	8321      	strh	r1, [r4, #24]
	__asm__ volatile(
     ec0:	f388 8811 	msr	BASEPRI, r8
     ec4:	f3bf 8f6f 	isb	sy
			if (!sys_slist_is_empty(&clients)) {
     ec8:	2f00      	cmp	r7, #0
     eca:	d0c7      	beq.n	e5c <process_event+0x184>
	return node->next;
     ecc:	683d      	ldr	r5, [r7, #0]
		notify_one(mgr, cli, state, res);
     ece:	4639      	mov	r1, r7
     ed0:	4633      	mov	r3, r6
     ed2:	4652      	mov	r2, sl
     ed4:	4620      	mov	r0, r4
     ed6:	f004 fef5 	bl	5cc4 <notify_one>
	list->head = node;
     eda:	462f      	mov	r7, r5
	while (!sys_slist_is_empty(list)) {
     edc:	e7f4      	b.n	ec8 <process_event+0x1f0>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     ede:	06ab      	lsls	r3, r5, #26
     ee0:	f57f af1a 	bpl.w	d18 <process_event+0x40>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     ee4:	f025 0320 	bic.w	r3, r5, #32
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     ee8:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     eea:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
     eee:	e6ff      	b.n	cf0 <process_event+0x18>
     ef0:	00005cf1 	.word	0x00005cf1

00000ef4 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
     ef4:	f001 bd38 	b.w	2968 <SystemInit>

00000ef8 <flash_area_open>:
		user_cb(&flash_map[i], user_data);
	}
}

int flash_area_open(uint8_t id, const struct flash_area **fap)
{
     ef8:	b570      	push	{r4, r5, r6, lr}
	const struct flash_area *area;

	if (flash_map == NULL) {
     efa:	4b11      	ldr	r3, [pc, #68]	; (f40 <flash_area_open+0x48>)
     efc:	681c      	ldr	r4, [r3, #0]
{
     efe:	460d      	mov	r5, r1
	if (flash_map == NULL) {
     f00:	b1dc      	cbz	r4, f3a <flash_area_open+0x42>
extern const struct flash_area *flash_map;
extern const int flash_map_entries;

static inline struct flash_area const *get_flash_area_from_id(int idx)
{
	for (int i = 0; i < flash_map_entries; i++) {
     f02:	4b10      	ldr	r3, [pc, #64]	; (f44 <flash_area_open+0x4c>)
     f04:	6819      	ldr	r1, [r3, #0]
     f06:	2300      	movs	r3, #0
     f08:	428b      	cmp	r3, r1
     f0a:	db02      	blt.n	f12 <flash_area_open+0x1a>
		return -EACCES;
	}

	area = get_flash_area_from_id(id);
	if (area == NULL) {
		return -ENOENT;
     f0c:	f06f 0001 	mvn.w	r0, #1
	}

	*fap = area;

	return 0;
}
     f10:	bd70      	pop	{r4, r5, r6, pc}
		if (flash_map[i].fa_id == idx) {
     f12:	4622      	mov	r2, r4
     f14:	f812 6b10 	ldrb.w	r6, [r2], #16
     f18:	4286      	cmp	r6, r0
     f1a:	d002      	beq.n	f22 <flash_area_open+0x2a>
	for (int i = 0; i < flash_map_entries; i++) {
     f1c:	3301      	adds	r3, #1
     f1e:	4614      	mov	r4, r2
     f20:	e7f2      	b.n	f08 <flash_area_open+0x10>
	if (!area->fa_dev || !device_is_ready(area->fa_dev)) {
     f22:	68e0      	ldr	r0, [r4, #12]
     f24:	b910      	cbnz	r0, f2c <flash_area_open+0x34>
		return -ENODEV;
     f26:	f06f 0012 	mvn.w	r0, #18
     f2a:	e7f1      	b.n	f10 <flash_area_open+0x18>
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
     f2c:	f005 fbea 	bl	6704 <z_device_is_ready>
	if (!area->fa_dev || !device_is_ready(area->fa_dev)) {
     f30:	2800      	cmp	r0, #0
     f32:	d0f8      	beq.n	f26 <flash_area_open+0x2e>
	*fap = area;
     f34:	602c      	str	r4, [r5, #0]
	return 0;
     f36:	2000      	movs	r0, #0
     f38:	e7ea      	b.n	f10 <flash_area_open+0x18>
		return -EACCES;
     f3a:	f06f 000c 	mvn.w	r0, #12
     f3e:	e7e7      	b.n	f10 <flash_area_open+0x18>
     f40:	20000008 	.word	0x20000008
     f44:	00006a58 	.word	0x00006a58

00000f48 <flash_area_get_sectors>:

	return true;
}

int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
{
     f48:	b570      	push	{r4, r5, r6, lr}
     f4a:	b088      	sub	sp, #32
     f4c:	4605      	mov	r5, r0
     f4e:	460c      	mov	r4, r1
	int rc = flash_area_open(idx, &fa);
     f50:	b2c0      	uxtb	r0, r0
     f52:	4669      	mov	r1, sp
{
     f54:	4616      	mov	r6, r2
	int rc = flash_area_open(idx, &fa);
     f56:	f7ff ffcf 	bl	ef8 <flash_area_open>
	if (rc < 0 || fa == NULL) {
     f5a:	2800      	cmp	r0, #0
     f5c:	db1b      	blt.n	f96 <flash_area_get_sectors+0x4e>
     f5e:	9800      	ldr	r0, [sp, #0]
     f60:	b1c8      	cbz	r0, f96 <flash_area_get_sectors+0x4e>
	cb_data->area_off = fa->fa_off;
     f62:	6843      	ldr	r3, [r0, #4]
     f64:	9302      	str	r3, [sp, #8]
	cb_data->area_len = fa->fa_size;
     f66:	6883      	ldr	r3, [r0, #8]
	cb_data->ret_len = *cnt;
     f68:	6822      	ldr	r2, [r4, #0]
	cb_data->area_idx = idx;
     f6a:	9501      	str	r5, [sp, #4]
	cb_data->ret = ret;
     f6c:	e9cd 3603 	strd	r3, r6, [sp, #12]
	cb_data->ret_idx = 0U;
     f70:	2300      	movs	r3, #0
	cb_data->status = 0;
     f72:	e9cd 2306 	strd	r2, r3, [sp, #24]
	cb_data->ret_idx = 0U;
     f76:	9305      	str	r3, [sp, #20]
	flash_dev = fa->fa_dev;
     f78:	68c5      	ldr	r5, [r0, #12]
	flash_area_close(fa);
     f7a:	f004 ff52 	bl	5e22 <flash_area_close>
	if (flash_dev == NULL) {
     f7e:	b16d      	cbz	r5, f9c <flash_area_get_sectors+0x54>
	flash_page_foreach(flash_dev, cb, cb_data);
     f80:	4628      	mov	r0, r5
     f82:	4908      	ldr	r1, [pc, #32]	; (fa4 <flash_area_get_sectors+0x5c>)
     f84:	aa01      	add	r2, sp, #4
     f86:	f005 f9b3 	bl	62f0 <flash_page_foreach>
	if (cb_data->status == 0) {
     f8a:	9807      	ldr	r0, [sp, #28]
     f8c:	b908      	cbnz	r0, f92 <flash_area_get_sectors+0x4a>
		*cnt = cb_data->ret_idx;
     f8e:	9b05      	ldr	r3, [sp, #20]
     f90:	6023      	str	r3, [r4, #0]
	struct layout_data data;

	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
}
     f92:	b008      	add	sp, #32
     f94:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
     f96:	f06f 0015 	mvn.w	r0, #21
     f9a:	e7fa      	b.n	f92 <flash_area_get_sectors+0x4a>
		return -ENODEV;
     f9c:	f06f 0012 	mvn.w	r0, #18
	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
     fa0:	e7f7      	b.n	f92 <flash_area_get_sectors+0x4a>
     fa2:	bf00      	nop
     fa4:	00005ec1 	.word	0x00005ec1

00000fa8 <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
     fa8:	4801      	ldr	r0, [pc, #4]	; (fb0 <nrf_cc3xx_platform_abort_init+0x8>)
     faa:	f002 becb 	b.w	3d44 <nrf_cc3xx_platform_set_abort>
     fae:	bf00      	nop
     fb0:	00006aec 	.word	0x00006aec

00000fb4 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
     fb4:	4901      	ldr	r1, [pc, #4]	; (fbc <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
     fb6:	2210      	movs	r2, #16
	str	r2, [r1]
     fb8:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
     fba:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
     fbc:	e000ed10 	.word	0xe000ed10

00000fc0 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
     fc0:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
     fc2:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
     fc4:	f381 8811 	msr	BASEPRI, r1

	wfe
     fc8:	bf20      	wfe

	msr	BASEPRI, r0
     fca:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
     fce:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
     fd0:	4770      	bx	lr
     fd2:	bf00      	nop

00000fd4 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
     fd4:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
     fd6:	2800      	cmp	r0, #0
     fd8:	db07      	blt.n	fea <arch_irq_enable+0x16>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
     fda:	4a04      	ldr	r2, [pc, #16]	; (fec <arch_irq_enable+0x18>)
     fdc:	0941      	lsrs	r1, r0, #5
     fde:	2301      	movs	r3, #1
     fe0:	f000 001f 	and.w	r0, r0, #31
     fe4:	4083      	lsls	r3, r0
     fe6:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
     fea:	4770      	bx	lr
     fec:	e000e100 	.word	0xe000e100

00000ff0 <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
     ff0:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
     ff2:	2800      	cmp	r0, #0
     ff4:	db0c      	blt.n	1010 <CONFIG_FPROTECT_BLOCK_SIZE+0x10>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
     ff6:	0943      	lsrs	r3, r0, #5
     ff8:	4906      	ldr	r1, [pc, #24]	; (1014 <CONFIG_FPROTECT_BLOCK_SIZE+0x14>)
     ffa:	f000 001f 	and.w	r0, r0, #31
     ffe:	3320      	adds	r3, #32
    1000:	2201      	movs	r2, #1
    1002:	4082      	lsls	r2, r0
    1004:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
    1008:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    100c:	f3bf 8f6f 	isb	sy
}
    1010:	4770      	bx	lr
    1012:	bf00      	nop
    1014:	e000e100 	.word	0xe000e100

00001018 <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    1018:	4b05      	ldr	r3, [pc, #20]	; (1030 <arch_irq_is_enabled+0x18>)
    101a:	0942      	lsrs	r2, r0, #5
    101c:	f000 001f 	and.w	r0, r0, #31
    1020:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1024:	2301      	movs	r3, #1
    1026:	fa03 f000 	lsl.w	r0, r3, r0
}
    102a:	4010      	ands	r0, r2
    102c:	4770      	bx	lr
    102e:	bf00      	nop
    1030:	e000e100 	.word	0xe000e100

00001034 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1034:	b240      	sxtb	r0, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    1036:	2800      	cmp	r0, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1038:	bfa8      	it	ge
    103a:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    103e:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1042:	bfb8      	it	lt
    1044:	4b06      	ldrlt	r3, [pc, #24]	; (1060 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1046:	ea4f 1141 	mov.w	r1, r1, lsl #5
    104a:	bfac      	ite	ge
    104c:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1050:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1054:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1056:	bfb4      	ite	lt
    1058:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    105a:	f880 1300 	strbge.w	r1, [r0, #768]	; 0x300
}
    105e:	4770      	bx	lr
    1060:	e000ed14 	.word	0xe000ed14

00001064 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1064:	bf30      	wfi
    b z_SysNmiOnReset
    1066:	f7ff bffd 	b.w	1064 <z_SysNmiOnReset>
    106a:	bf00      	nop

0000106c <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    106c:	4a14      	ldr	r2, [pc, #80]	; (10c0 <z_arm_prep_c+0x54>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    106e:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1070:	4b14      	ldr	r3, [pc, #80]	; (10c4 <z_arm_prep_c+0x58>)
    1072:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1076:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    1078:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    107c:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1080:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1084:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1088:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
    108c:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1090:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
    1094:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	FPU->FPCCR = FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
    1098:	f04f 4240 	mov.w	r2, #3221225472	; 0xc0000000
    109c:	f8c3 2234 	str.w	r2, [r3, #564]	; 0x234
  __ASM volatile ("dsb 0xF":::"memory");
    10a0:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    10a4:	f3bf 8f6f 	isb	sy
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
  __builtin_arm_set_fpscr(fpscr);
    10a8:	2300      	movs	r3, #0
    10aa:	eee1 3a10 	vmsr	fpscr, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    10ae:	f002 fd17 	bl	3ae0 <z_bss_zero>
	z_data_copy();
    10b2:	f002 fd5d 	bl	3b70 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    10b6:	f000 f963 	bl	1380 <z_arm_interrupt_init>
	z_cstart();
    10ba:	f002 fd1d 	bl	3af8 <z_cstart>
    10be:	bf00      	nop
    10c0:	00000000 	.word	0x00000000
    10c4:	e000ed00 	.word	0xe000ed00

000010c8 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    10c8:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    10cc:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    10ce:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    10d2:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    10d6:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    10d8:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    10dc:	2902      	cmp	r1, #2
    beq _oops
    10de:	d0ff      	beq.n	10e0 <_oops>

000010e0 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    10e0:	b501      	push	{r0, lr}
    push {r1, r2}
    push {r4-r11}
    mov  r1, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    bl z_do_kernel_oops
    10e2:	f004 ff13 	bl	5f0c <z_do_kernel_oops>
     * the MSP to its value prior to entering the function
     */
    add sp, #40
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    pop {r0, pc}
    10e6:	bd01      	pop	{r0, pc}

000010e8 <z_check_thread_stack_fail>:
			fault_addr, psp)) {
		/* Thread stack corruption */
		return thread->stack_info.start;
	}
#else
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    10e8:	f110 0f16 	cmn.w	r0, #22
    10ec:	4b07      	ldr	r3, [pc, #28]	; (110c <z_check_thread_stack_fail+0x24>)
    10ee:	d008      	beq.n	1102 <z_check_thread_stack_fail+0x1a>
    10f0:	4298      	cmp	r0, r3
    10f2:	d308      	bcc.n	1106 <z_check_thread_stack_fail+0x1e>
    10f4:	3340      	adds	r3, #64	; 0x40
    10f6:	4283      	cmp	r3, r0
    10f8:	d905      	bls.n	1106 <z_check_thread_stack_fail+0x1e>
    10fa:	428b      	cmp	r3, r1
    10fc:	d903      	bls.n	1106 <z_check_thread_stack_fail+0x1e>
			guard_len,
			fault_addr, psp)) {
		/* Thread stack corruption */
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
    10fe:	4804      	ldr	r0, [pc, #16]	; (1110 <z_check_thread_stack_fail+0x28>)
    1100:	4770      	bx	lr
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    1102:	3340      	adds	r3, #64	; 0x40
    1104:	e7f9      	b.n	10fa <z_check_thread_stack_fail+0x12>
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    1106:	2000      	movs	r0, #0
}
    1108:	4770      	bx	lr
    110a:	bf00      	nop
    110c:	20002040 	.word	0x20002040
    1110:	20002080 	.word	0x20002080

00001114 <z_arm_switch_to_main_no_multithreading>:

#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)

FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
	k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
{
    1114:	4604      	mov	r4, r0
    1116:	4608      	mov	r0, r1
    1118:	4611      	mov	r1, r2
    111a:	461a      	mov	r2, r3
    111c:	2300      	movs	r3, #0
    111e:	eee1 3a10 	vmsr	fpscr, r3
	 */
	register void *p1_inreg __asm__("r0") = p1;
	register void *p2_inreg __asm__("r1") = p2;
	register void *p3_inreg __asm__("r2") = p3;

	__asm__ volatile (
    1122:	4b08      	ldr	r3, [pc, #32]	; (1144 <loop+0x2>)
    1124:	2520      	movs	r5, #32
    1126:	f383 8809 	msr	PSP, r3
    112a:	b663      	cpsie	if
    112c:	f04f 0300 	mov.w	r3, #0
    1130:	f383 8811 	msr	BASEPRI, r3
    1134:	f3bf 8f6f 	isb	sy
    1138:	47a0      	blx	r4
    113a:	f385 8811 	msr	BASEPRI, r5
    113e:	f3bf 8f6f 	isb	sy

00001142 <loop>:
    1142:	e7fe      	b.n	1142 <loop>
	, [_psplim]"r" (psplim)
#endif
	:
	);

	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    1144:	20004880 	.word	0x20004880

00001148 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    1148:	b501      	push	{r0, lr}
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    114a:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    114e:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    1152:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    1156:	4904      	ldr	r1, [pc, #16]	; (1168 <_isr_wrapper+0x20>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1158:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    115a:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    115c:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    115e:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    1162:	4902      	ldr	r1, [pc, #8]	; (116c <_isr_wrapper+0x24>)
	bx r1
    1164:	4708      	bx	r1
    1166:	0000      	.short	0x0000
	ldr r1, =_sw_isr_table
    1168:	0000688c 	.word	0x0000688c
	ldr r1, =z_arm_int_exit
    116c:	00001171 	.word	0x00001171

00001170 <z_arm_exc_exit>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    1170:	4770      	bx	lr
    1172:	bf00      	nop

00001174 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    1174:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1176:	4b1d      	ldr	r3, [pc, #116]	; (11ec <mem_manage_fault+0x78>)
{
    1178:	4615      	mov	r5, r2
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    117a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    117c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    117e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1180:	0792      	lsls	r2, r2, #30
{
    1182:	4606      	mov	r6, r0
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1184:	d522      	bpl.n	11cc <mem_manage_fault+0x58>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    1186:	6b58      	ldr	r0, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1188:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    118a:	0614      	lsls	r4, r2, #24
    118c:	d51e      	bpl.n	11cc <mem_manage_fault+0x58>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault != 0) {
    118e:	b119      	cbz	r1, 1198 <mem_manage_fault+0x24>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1190:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1192:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    1196:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1198:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Instruction Access Violation");
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    119a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    119c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    119e:	4c13      	ldr	r4, [pc, #76]	; (11ec <mem_manage_fault+0x78>)
    11a0:	f012 0f10 	tst.w	r2, #16
    11a4:	d115      	bne.n	11d2 <mem_manage_fault+0x5e>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    11a6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    11a8:	0799      	lsls	r1, r3, #30
    11aa:	d412      	bmi.n	11d2 <mem_manage_fault+0x5e>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    11ac:	2000      	movs	r0, #0
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    11ae:	6aa3      	ldr	r3, [r4, #40]	; 0x28
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    11b0:	4a0e      	ldr	r2, [pc, #56]	; (11ec <mem_manage_fault+0x78>)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    11b2:	069b      	lsls	r3, r3, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    11b4:	bf42      	ittt	mi
    11b6:	6a63      	ldrmi	r3, [r4, #36]	; 0x24
    11b8:	f423 5300 	bicmi.w	r3, r3, #8192	; 0x2000
    11bc:	6263      	strmi	r3, [r4, #36]	; 0x24
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    11be:	6a93      	ldr	r3, [r2, #40]	; 0x28
    11c0:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    11c4:	6293      	str	r3, [r2, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    11c6:	2300      	movs	r3, #0
    11c8:	702b      	strb	r3, [r5, #0]

	return reason;
}
    11ca:	bd70      	pop	{r4, r5, r6, pc}
	uint32_t mmfar = -EINVAL;
    11cc:	f06f 0015 	mvn.w	r0, #21
    11d0:	e7e2      	b.n	1198 <mem_manage_fault+0x24>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    11d2:	6863      	ldr	r3, [r4, #4]
    11d4:	051a      	lsls	r2, r3, #20
    11d6:	d5e9      	bpl.n	11ac <mem_manage_fault+0x38>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    11d8:	4631      	mov	r1, r6
    11da:	f7ff ff85 	bl	10e8 <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    11de:	2800      	cmp	r0, #0
    11e0:	d0e4      	beq.n	11ac <mem_manage_fault+0x38>
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    11e2:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    11e6:	2002      	movs	r0, #2
    11e8:	e7e1      	b.n	11ae <mem_manage_fault+0x3a>
    11ea:	bf00      	nop
    11ec:	e000ed00 	.word	0xe000ed00

000011f0 <bus_fault.constprop.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    11f0:	4b0d      	ldr	r3, [pc, #52]	; (1228 <bus_fault.constprop.0+0x38>)
    11f2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    11f4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    11f6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    11f8:	0592      	lsls	r2, r2, #22
    11fa:	d508      	bpl.n	120e <bus_fault.constprop.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    11fc:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    11fe:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1200:	0412      	lsls	r2, r2, #16
    1202:	d504      	bpl.n	120e <bus_fault.constprop.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault != 0) {
    1204:	b118      	cbz	r0, 120e <bus_fault.constprop.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    1206:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1208:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    120c:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    120e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Imprecise data bus error");
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    1210:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1212:	05d2      	lsls	r2, r2, #23
		SYSMPU->CESR &= ~sperr;
	}
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1214:	4a04      	ldr	r2, [pc, #16]	; (1228 <bus_fault.constprop.0+0x38>)
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    1216:	bf58      	it	pl
    1218:	6a9b      	ldrpl	r3, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    121a:	6a93      	ldr	r3, [r2, #40]	; 0x28

	*recoverable = memory_fault_recoverable(esf, true);
    121c:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    121e:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    1222:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    1224:	7008      	strb	r0, [r1, #0]

	return reason;
}
    1226:	4770      	bx	lr
    1228:	e000ed00 	.word	0xe000ed00

0000122c <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    122c:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    122e:	4b4a      	ldr	r3, [pc, #296]	; (1358 <z_arm_fault+0x12c>)
    1230:	685b      	ldr	r3, [r3, #4]
{
    1232:	b08a      	sub	sp, #40	; 0x28
    1234:	4605      	mov	r5, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1236:	f3c3 0308 	ubfx	r3, r3, #0, #9
    123a:	2600      	movs	r6, #0
    123c:	f386 8811 	msr	BASEPRI, r6
    1240:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1244:	f002 407f 	and.w	r0, r2, #4278190080	; 0xff000000
    1248:	f1b0 4f7f 	cmp.w	r0, #4278190080	; 0xff000000
    124c:	d111      	bne.n	1272 <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    124e:	f002 000c 	and.w	r0, r2, #12
    1252:	2808      	cmp	r0, #8
    1254:	d00d      	beq.n	1272 <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    1256:	0710      	lsls	r0, r2, #28
			ptr_esf =  (z_arch_esf_t *)psp;
    1258:	bf4c      	ite	mi
    125a:	460d      	movmi	r5, r1
			*nested_exc = true;
    125c:	2601      	movpl	r6, #1
	*recoverable = false;
    125e:	2200      	movs	r2, #0
	switch (fault) {
    1260:	3b03      	subs	r3, #3
	*recoverable = false;
    1262:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    1266:	2b03      	cmp	r3, #3
    1268:	d84d      	bhi.n	1306 <z_arm_fault+0xda>
    126a:	e8df f003 	tbb	[pc, r3]
    126e:	6504      	.short	0x6504
    1270:	6d69      	.short	0x6d69
		return NULL;
    1272:	4635      	mov	r5, r6
    1274:	e7f3      	b.n	125e <z_arm_fault+0x32>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    1276:	4b38      	ldr	r3, [pc, #224]	; (1358 <z_arm_fault+0x12c>)
    1278:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    127a:	0791      	lsls	r1, r2, #30
    127c:	d443      	bmi.n	1306 <z_arm_fault+0xda>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    127e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    1280:	2a00      	cmp	r2, #0
    1282:	db40      	blt.n	1306 <z_arm_fault+0xda>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    1284:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    1286:	0052      	lsls	r2, r2, #1
    1288:	d53d      	bpl.n	1306 <z_arm_fault+0xda>
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    128a:	695a      	ldr	r2, [r3, #20]
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    128c:	69a9      	ldr	r1, [r5, #24]
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    128e:	f442 7280 	orr.w	r2, r2, #256	; 0x100
    1292:	615a      	str	r2, [r3, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    1294:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1298:	f3bf 8f6f 	isb	sy
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    129c:	695a      	ldr	r2, [r3, #20]
	uint16_t fault_insn = *(ret_addr - 1);
    129e:	f831 1c02 	ldrh.w	r1, [r1, #-2]
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    12a2:	f422 7280 	bic.w	r2, r2, #256	; 0x100
    12a6:	615a      	str	r2, [r3, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    12a8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    12ac:	f3bf 8f6f 	isb	sy
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    12b0:	f64d 7202 	movw	r2, #57090	; 0xdf02
    12b4:	4291      	cmp	r1, r2
    12b6:	d009      	beq.n	12cc <z_arm_fault+0xa0>
		} else if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) != 0) {
    12b8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12ba:	b2d2      	uxtb	r2, r2
    12bc:	b142      	cbz	r2, 12d0 <z_arm_fault+0xa4>
			reason = mem_manage_fault(esf, 1, recoverable);
    12be:	f10d 0207 	add.w	r2, sp, #7
    12c2:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    12c4:	4628      	mov	r0, r5
    12c6:	f7ff ff55 	bl	1174 <mem_manage_fault>
    12ca:	e00a      	b.n	12e2 <z_arm_fault+0xb6>
			reason = esf->basic.r0;
    12cc:	682c      	ldr	r4, [r5, #0]
    12ce:	e01b      	b.n	1308 <z_arm_fault+0xdc>
		} else if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) != 0) {
    12d0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12d2:	f412 4f7f 	tst.w	r2, #65280	; 0xff00
    12d6:	d006      	beq.n	12e6 <z_arm_fault+0xba>
			reason = bus_fault(esf, 1, recoverable);
    12d8:	f10d 0107 	add.w	r1, sp, #7
    12dc:	2001      	movs	r0, #1
    12de:	f7ff ff87 	bl	11f0 <bus_fault.constprop.0>
    12e2:	4604      	mov	r4, r0
    12e4:	e010      	b.n	1308 <z_arm_fault+0xdc>
		} else if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) != 0) {
    12e6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12e8:	f5b2 3f80 	cmp.w	r2, #65536	; 0x10000
    12ec:	d30b      	bcc.n	1306 <z_arm_fault+0xda>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    12ee:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    12f0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    12f2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    12f4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    12f6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    12f8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    12fa:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12fc:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    1300:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    1304:	629a      	str	r2, [r3, #40]	; 0x28
		return NULL;
    1306:	2400      	movs	r4, #0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    1308:	f89d 3007 	ldrb.w	r3, [sp, #7]
    130c:	b993      	cbnz	r3, 1334 <z_arm_fault+0x108>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    130e:	2220      	movs	r2, #32
    1310:	4629      	mov	r1, r5
    1312:	a802      	add	r0, sp, #8
    1314:	f004 fe30 	bl	5f78 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    1318:	9b09      	ldr	r3, [sp, #36]	; 0x24
    131a:	b1be      	cbz	r6, 134c <z_arm_fault+0x120>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    131c:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1320:	b922      	cbnz	r2, 132c <z_arm_fault+0x100>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    1322:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1326:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    132a:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    132c:	a902      	add	r1, sp, #8
    132e:	4620      	mov	r0, r4
    1330:	f004 fdea 	bl	5f08 <z_arm_fatal_error>
}
    1334:	b00a      	add	sp, #40	; 0x28
    1336:	bd70      	pop	{r4, r5, r6, pc}
		reason = mem_manage_fault(esf, 0, recoverable);
    1338:	f10d 0207 	add.w	r2, sp, #7
    133c:	2100      	movs	r1, #0
    133e:	e7c1      	b.n	12c4 <z_arm_fault+0x98>
		reason = bus_fault(esf, 0, recoverable);
    1340:	f10d 0107 	add.w	r1, sp, #7
    1344:	2000      	movs	r0, #0
    1346:	e7ca      	b.n	12de <z_arm_fault+0xb2>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    1348:	4b03      	ldr	r3, [pc, #12]	; (1358 <z_arm_fault+0x12c>)
    134a:	e7d0      	b.n	12ee <z_arm_fault+0xc2>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    134c:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    1350:	f023 0301 	bic.w	r3, r3, #1
    1354:	e7e9      	b.n	132a <z_arm_fault+0xfe>
    1356:	bf00      	nop
    1358:	e000ed00 	.word	0xe000ed00

0000135c <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    135c:	4a02      	ldr	r2, [pc, #8]	; (1368 <z_arm_fault_init+0xc>)
    135e:	6953      	ldr	r3, [r2, #20]
    1360:	f043 0310 	orr.w	r3, r3, #16
    1364:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    1366:	4770      	bx	lr
    1368:	e000ed00 	.word	0xe000ed00

0000136c <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    136c:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    1370:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    1374:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    1376:	4672      	mov	r2, lr
	bl z_arm_fault
    1378:	f7ff ff58 	bl	122c <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    137c:	bd01      	pop	{r0, pc}
    137e:	bf00      	nop

00001380 <z_arm_interrupt_init>:
    1380:	4804      	ldr	r0, [pc, #16]	; (1394 <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    1382:	2300      	movs	r3, #0
    1384:	2120      	movs	r1, #32
    1386:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    1388:	3301      	adds	r3, #1
    138a:	2b30      	cmp	r3, #48	; 0x30
    138c:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    1390:	d1f9      	bne.n	1386 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    1392:	4770      	bx	lr
    1394:	e000e100 	.word	0xe000e100

00001398 <__start>:
    strb r0, [r1]
#endif /* CONFIG_DEBUG_THREAD_INFO */

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    1398:	2000      	movs	r0, #0
    msr CONTROL, r0
    139a:	f380 8814 	msr	CONTROL, r0
    isb
    139e:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_PM_S2RAM)
    bl arch_pm_s2ram_resume
#endif /* CONFIG_PM_S2RAM */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    13a2:	f7ff fda7 	bl	ef4 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    13a6:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    13a8:	490d      	ldr	r1, [pc, #52]	; (13e0 <__start+0x48>)
    str r0, [r1]
    13aa:	6008      	str	r0, [r1, #0]
    dsb
    13ac:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    13b0:	480c      	ldr	r0, [pc, #48]	; (13e4 <__start+0x4c>)
    msr msp, r0
    13b2:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    13b6:	f000 f82b 	bl	1410 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    13ba:	2020      	movs	r0, #32
    msr BASEPRI, r0
    13bc:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    13c0:	4809      	ldr	r0, [pc, #36]	; (13e8 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    13c2:	f44f 6104 	mov.w	r1, #2112	; 0x840
    adds r0, r0, r1
    13c6:	1840      	adds	r0, r0, r1
    msr PSP, r0
    13c8:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    13cc:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    13d0:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    13d2:	4308      	orrs	r0, r1
    msr CONTROL, r0
    13d4:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    13d8:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    13dc:	f7ff fe46 	bl	106c <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    13e0:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    13e4:	20004840 	.word	0x20004840
    ldr r0, =z_interrupt_stacks
    13e8:	20001800 	.word	0x20001800

000013ec <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    13ec:	4907      	ldr	r1, [pc, #28]	; (140c <z_arm_clear_arm_mpu_config+0x20>)
    13ee:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    13f2:	2300      	movs	r3, #0
	int num_regions =
    13f4:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    13f8:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    13fa:	4293      	cmp	r3, r2
    13fc:	db00      	blt.n	1400 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    13fe:	4770      	bx	lr
  MPU->RNR = rnr;
    1400:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    1404:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    1408:	3301      	adds	r3, #1
    140a:	e7f6      	b.n	13fa <z_arm_clear_arm_mpu_config+0xe>
    140c:	e000ed00 	.word	0xe000ed00

00001410 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    1410:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    1412:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    1414:	2300      	movs	r3, #0
    1416:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    141a:	f7ff ffe7 	bl	13ec <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    141e:	4b14      	ldr	r3, [pc, #80]	; (1470 <z_arm_init_arch_hw_at_boot+0x60>)
    1420:	f04f 32ff 	mov.w	r2, #4294967295
    1424:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    1428:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    142c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    1430:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    1434:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    1438:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    143c:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    1440:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    1444:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    1448:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    144c:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    1450:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    1454:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    1458:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    145c:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    1460:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    1464:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    1466:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    146a:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    146e:	bd08      	pop	{r3, pc}
    1470:	e000e100 	.word	0xe000e100

00001474 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1474:	4b02      	ldr	r3, [pc, #8]	; (1480 <z_arm_configure_static_mpu_regions+0xc>)
    1476:	4a03      	ldr	r2, [pc, #12]	; (1484 <z_arm_configure_static_mpu_regions+0x10>)
    1478:	4803      	ldr	r0, [pc, #12]	; (1488 <z_arm_configure_static_mpu_regions+0x14>)
    147a:	2102      	movs	r1, #2
    147c:	f000 b860 	b.w	1540 <arm_core_mpu_configure_static_mpu_regions>
    1480:	20040000 	.word	0x20040000
    1484:	20000000 	.word	0x20000000
    1488:	00006af4 	.word	0x00006af4

0000148c <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    148c:	b5f0      	push	{r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    148e:	4e20      	ldr	r6, [pc, #128]	; (1510 <mpu_configure_regions+0x84>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    1490:	2500      	movs	r5, #0
    1492:	428d      	cmp	r5, r1
    1494:	da39      	bge.n	150a <mpu_configure_regions+0x7e>
		if (regions[i].size == 0U) {
    1496:	6844      	ldr	r4, [r0, #4]
    1498:	b374      	cbz	r4, 14f8 <mpu_configure_regions+0x6c>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    149a:	b153      	cbz	r3, 14b2 <mpu_configure_regions+0x26>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    149c:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    14a0:	ea14 0f0c 	tst.w	r4, ip
    14a4:	d12f      	bne.n	1506 <mpu_configure_regions+0x7a>
		&&
    14a6:	2c1f      	cmp	r4, #31
    14a8:	d92d      	bls.n	1506 <mpu_configure_regions+0x7a>
		((part->start & (part->size - 1U)) == 0U);
    14aa:	6807      	ldr	r7, [r0, #0]
		&&
    14ac:	ea1c 0f07 	tst.w	ip, r7
    14b0:	d129      	bne.n	1506 <mpu_configure_regions+0x7a>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    14b2:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    14b4:	6807      	ldr	r7, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    14b6:	f8d0 c008 	ldr.w	ip, [r0, #8]
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
			return -EINVAL;
		}

		reg_index = mpu_configure_region(reg_index, &regions[i]);
    14ba:	fa5f fe82 	uxtb.w	lr, r2
	if (size <= 32U) {
    14be:	d91e      	bls.n	14fe <mpu_configure_regions+0x72>
	if (size > (1UL << 31)) {
    14c0:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    14c4:	d81d      	bhi.n	1502 <mpu_configure_regions+0x76>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    14c6:	3c01      	subs	r4, #1
    14c8:	fab4 f484 	clz	r4, r4
    14cc:	f1c4 041f 	rsb	r4, r4, #31
    14d0:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    14d2:	f1be 0f07 	cmp.w	lr, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    14d6:	ea4c 0c04 	orr.w	ip, ip, r4
    14da:	d814      	bhi.n	1506 <mpu_configure_regions+0x7a>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    14dc:	f027 041f 	bic.w	r4, r7, #31
				| MPU_RBAR_VALID_Msk | index;
    14e0:	4314      	orrs	r4, r2
    14e2:	f044 0410 	orr.w	r4, r4, #16
    14e6:	f8c6 2098 	str.w	r2, [r6, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    14ea:	f8c6 409c 	str.w	r4, [r6, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    14ee:	f04c 0401 	orr.w	r4, ip, #1
    14f2:	f8c6 40a0 	str.w	r4, [r6, #160]	; 0xa0
		if (reg_index == -EINVAL) {
			return reg_index;
		}

		/* Increment number of programmed MPU indices. */
		reg_index++;
    14f6:	3201      	adds	r2, #1
	for (i = 0; i < regions_num; i++) {
    14f8:	3501      	adds	r5, #1
    14fa:	300c      	adds	r0, #12
    14fc:	e7c9      	b.n	1492 <mpu_configure_regions+0x6>
		return REGION_32B;
    14fe:	2408      	movs	r4, #8
    1500:	e7e7      	b.n	14d2 <mpu_configure_regions+0x46>
		return REGION_4G;
    1502:	243e      	movs	r4, #62	; 0x3e
    1504:	e7e5      	b.n	14d2 <mpu_configure_regions+0x46>
			return -EINVAL;
    1506:	f06f 0215 	mvn.w	r2, #21
	}

	return reg_index;
}
    150a:	4610      	mov	r0, r2
    150c:	bdf0      	pop	{r4, r5, r6, r7, pc}
    150e:	bf00      	nop
    1510:	e000ed00 	.word	0xe000ed00

00001514 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    1514:	4b04      	ldr	r3, [pc, #16]	; (1528 <arm_core_mpu_enable+0x14>)
    1516:	2205      	movs	r2, #5
    1518:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    151c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1520:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1524:	4770      	bx	lr
    1526:	bf00      	nop
    1528:	e000ed00 	.word	0xe000ed00

0000152c <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    152c:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1530:	4b02      	ldr	r3, [pc, #8]	; (153c <arm_core_mpu_disable+0x10>)
    1532:	2200      	movs	r2, #0
    1534:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    1538:	4770      	bx	lr
    153a:	bf00      	nop
    153c:	e000ed00 	.word	0xe000ed00

00001540 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	*static_regions, const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    1540:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    1542:	4c03      	ldr	r4, [pc, #12]	; (1550 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    1544:	2301      	movs	r3, #1
    1546:	7822      	ldrb	r2, [r4, #0]
    1548:	f7ff ffa0 	bl	148c <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    154c:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    154e:	bd10      	pop	{r4, pc}
    1550:	200017f5 	.word	0x200017f5

00001554 <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    1554:	4914      	ldr	r1, [pc, #80]	; (15a8 <z_arm_mpu_init+0x54>)
    1556:	6808      	ldr	r0, [r1, #0]
    1558:	2808      	cmp	r0, #8
{
    155a:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    155c:	d821      	bhi.n	15a2 <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    155e:	f7ff ffe5 	bl	152c <arm_core_mpu_disable>
    1562:	4c12      	ldr	r4, [pc, #72]	; (15ac <z_arm_mpu_init+0x58>)
    1564:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1566:	2200      	movs	r2, #0
    1568:	4290      	cmp	r0, r2
    156a:	f101 010c 	add.w	r1, r1, #12
    156e:	d105      	bne.n	157c <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    1570:	4b0f      	ldr	r3, [pc, #60]	; (15b0 <z_arm_mpu_init+0x5c>)
    1572:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    1574:	f7ff ffce 	bl	1514 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    1578:	2000      	movs	r0, #0
}
    157a:	bd10      	pop	{r4, pc}
    157c:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1580:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    1584:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    1588:	4313      	orrs	r3, r2
    158a:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    158e:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    1592:	f851 3c04 	ldr.w	r3, [r1, #-4]
    1596:	f043 0301 	orr.w	r3, r3, #1
    159a:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    159e:	3201      	adds	r2, #1
    15a0:	e7e2      	b.n	1568 <z_arm_mpu_init+0x14>
		return -1;
    15a2:	f04f 30ff 	mov.w	r0, #4294967295
    15a6:	e7e8      	b.n	157a <z_arm_mpu_init+0x26>
    15a8:	00006b0c 	.word	0x00006b0c
    15ac:	e000ed00 	.word	0xe000ed00
    15b0:	200017f5 	.word	0x200017f5

000015b4 <nordicsemi_nrf52_init>:
	nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
	NVIC_SystemReset();
}

static int nordicsemi_nrf52_init(const struct device *arg)
{
    15b4:	b510      	push	{r4, lr}
	__asm__ volatile(
    15b6:	f04f 0320 	mov.w	r3, #32
    15ba:	f3ef 8011 	mrs	r0, BASEPRI
    15be:	f383 8812 	msr	BASEPRI_MAX, r3
    15c2:	f3bf 8f6f 	isb	sy
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    15c6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    15ca:	2201      	movs	r2, #1
{
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    15cc:	f04f 5180 	mov.w	r1, #268435456	; 0x10000000
    15d0:	f8c3 2578 	str.w	r2, [r3, #1400]	; 0x578
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    15d4:	f8d1 4130 	ldr.w	r4, [r1, #304]	; 0x130
    15d8:	2c08      	cmp	r4, #8
    15da:	d108      	bne.n	15ee <nordicsemi_nrf52_init+0x3a>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    15dc:	f8d1 1134 	ldr.w	r1, [r1, #308]	; 0x134
            {
                switch(var2)
    15e0:	2905      	cmp	r1, #5
    15e2:	d804      	bhi.n	15ee <nordicsemi_nrf52_init+0x3a>
#endif // defined(POWER_RAM_POWER_S0POWER_Msk)

#if NRF_POWER_HAS_DCDCEN_VDDH
NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
{
    if (enable && nrf52_errata_197())
    15e4:	4c07      	ldr	r4, [pc, #28]	; (1604 <nordicsemi_nrf52_init+0x50>)
    15e6:	5c61      	ldrb	r1, [r4, r1]
    15e8:	b109      	cbz	r1, 15ee <nordicsemi_nrf52_init+0x3a>
    {
        // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
        *(volatile uint32_t *)0x40000638ul = 1ul;
    15ea:	f8c3 2638 	str.w	r2, [r3, #1592]	; 0x638
    }
    p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
    15ee:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    15f2:	2201      	movs	r2, #1
    15f4:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
	__asm__ volatile(
    15f8:	f380 8811 	msr	BASEPRI, r0
    15fc:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    1600:	2000      	movs	r0, #0
    1602:	bd10      	pop	{r4, pc}
    1604:	00006e65 	.word	0x00006e65

00001608 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    1608:	b120      	cbz	r0, 1614 <arch_busy_wait+0xc>
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    160a:	4b03      	ldr	r3, [pc, #12]	; (1618 <arch_busy_wait+0x10>)
    160c:	0180      	lsls	r0, r0, #6
    160e:	f043 0301 	orr.w	r3, r3, #1
    1612:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    1614:	4770      	bx	lr
    1616:	bf00      	nop
    1618:	00006a40 	.word	0x00006a40

0000161c <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    161c:	4b08      	ldr	r3, [pc, #32]	; (1640 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    161e:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1620:	1ac3      	subs	r3, r0, r3
{
    1622:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1624:	4907      	ldr	r1, [pc, #28]	; (1644 <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    1626:	109b      	asrs	r3, r3, #2
{
    1628:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    162a:	4359      	muls	r1, r3
    162c:	4806      	ldr	r0, [pc, #24]	; (1648 <onoff_stop+0x2c>)
    162e:	2240      	movs	r2, #64	; 0x40
    1630:	f004 fcd2 	bl	5fd8 <stop>
	notify(mgr, res);
    1634:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1636:	4601      	mov	r1, r0
	notify(mgr, res);
    1638:	4620      	mov	r0, r4
}
    163a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    163e:	4718      	bx	r3
    1640:	200015a4 	.word	0x200015a4
    1644:	b6db6db7 	.word	0xb6db6db7
    1648:	00006814 	.word	0x00006814

0000164c <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    164c:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    164e:	4c0c      	ldr	r4, [pc, #48]	; (1680 <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1650:	4a0c      	ldr	r2, [pc, #48]	; (1684 <onoff_start+0x38>)
    1652:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    1654:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1656:	9300      	str	r3, [sp, #0]
{
    1658:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    165a:	460b      	mov	r3, r1
    165c:	490a      	ldr	r1, [pc, #40]	; (1688 <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    165e:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1660:	4361      	muls	r1, r4
{
    1662:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1664:	4809      	ldr	r0, [pc, #36]	; (168c <onoff_start+0x40>)
    1666:	f004 fce4 	bl	6032 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    166a:	1e01      	subs	r1, r0, #0
    166c:	da05      	bge.n	167a <onoff_start+0x2e>
		notify(mgr, err);
    166e:	4630      	mov	r0, r6
    1670:	462b      	mov	r3, r5
	}
}
    1672:	b002      	add	sp, #8
    1674:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    1678:	4718      	bx	r3
}
    167a:	b002      	add	sp, #8
    167c:	bd70      	pop	{r4, r5, r6, pc}
    167e:	bf00      	nop
    1680:	200015a4 	.word	0x200015a4
    1684:	000060a5 	.word	0x000060a5
    1688:	b6db6db7 	.word	0xb6db6db7
    168c:	00006814 	.word	0x00006814

00001690 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1690:	2200      	movs	r2, #0
{
    1692:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1694:	2101      	movs	r1, #1
{
    1696:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1698:	4610      	mov	r0, r2
    169a:	f7ff fccb 	bl	1034 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    169e:	480f      	ldr	r0, [pc, #60]	; (16dc <clk_init+0x4c>)
    16a0:	f001 fafa 	bl	2c98 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    16a4:	4b0e      	ldr	r3, [pc, #56]	; (16e0 <clk_init+0x50>)
    16a6:	4298      	cmp	r0, r3
    16a8:	d115      	bne.n	16d6 <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    16aa:	f004 ff61 	bl	6570 <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    16ae:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    16b0:	490c      	ldr	r1, [pc, #48]	; (16e4 <clk_init+0x54>)
    16b2:	4630      	mov	r0, r6
    16b4:	f004 fb2b 	bl	5d0e <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    16b8:	2800      	cmp	r0, #0
    16ba:	db0b      	blt.n	16d4 <clk_init+0x44>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    16bc:	2501      	movs	r5, #1
    16be:	6435      	str	r5, [r6, #64]	; 0x40
	struct nrf_clock_control_data *data = dev->data;
    16c0:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    16c2:	4908      	ldr	r1, [pc, #32]	; (16e4 <clk_init+0x54>)
    16c4:	f104 001c 	add.w	r0, r4, #28
    16c8:	f004 fb21 	bl	5d0e <onoff_manager_init>
		if (err < 0) {
    16cc:	2800      	cmp	r0, #0
    16ce:	db01      	blt.n	16d4 <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    16d0:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    16d2:	2000      	movs	r0, #0
}
    16d4:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    16d6:	f06f 0004 	mvn.w	r0, #4
    16da:	e7fb      	b.n	16d4 <clk_init+0x44>
    16dc:	0000171d 	.word	0x0000171d
    16e0:	0bad0000 	.word	0x0bad0000
    16e4:	00006b2c 	.word	0x00006b2c

000016e8 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    16e8:	b570      	push	{r4, r5, r6, lr}
    16ea:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    16ec:	230c      	movs	r3, #12
    16ee:	4809      	ldr	r0, [pc, #36]	; (1714 <clkstarted_handle.constprop.0+0x2c>)
    16f0:	434b      	muls	r3, r1
    16f2:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    16f4:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    16f8:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    16fa:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    16fc:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    16fe:	4418      	add	r0, r3
    1700:	f004 fc57 	bl	5fb2 <set_on_state>
	if (callback) {
    1704:	b12d      	cbz	r5, 1712 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1706:	4632      	mov	r2, r6
    1708:	462b      	mov	r3, r5
    170a:	4803      	ldr	r0, [pc, #12]	; (1718 <clkstarted_handle.constprop.0+0x30>)
}
    170c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    1710:	4718      	bx	r3
}
    1712:	bd70      	pop	{r4, r5, r6, pc}
    1714:	200015a4 	.word	0x200015a4
    1718:	00006814 	.word	0x00006814

0000171c <clock_event_handler>:
	switch (event) {
    171c:	b110      	cbz	r0, 1724 <clock_event_handler+0x8>
    171e:	2801      	cmp	r0, #1
    1720:	d004      	beq.n	172c <clock_event_handler+0x10>
    1722:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    1724:	4b03      	ldr	r3, [pc, #12]	; (1734 <clock_event_handler+0x18>)
    1726:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    1728:	075b      	lsls	r3, r3, #29
    172a:	d101      	bne.n	1730 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    172c:	f7ff bfdc 	b.w	16e8 <clkstarted_handle.constprop.0>
}
    1730:	4770      	bx	lr
    1732:	bf00      	nop
    1734:	200015a4 	.word	0x200015a4

00001738 <generic_hfclk_start>:
{
    1738:	b508      	push	{r3, lr}
	__asm__ volatile(
    173a:	f04f 0320 	mov.w	r3, #32
    173e:	f3ef 8111 	mrs	r1, BASEPRI
    1742:	f383 8812 	msr	BASEPRI_MAX, r3
    1746:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    174a:	4a12      	ldr	r2, [pc, #72]	; (1794 <generic_hfclk_start+0x5c>)
    174c:	6813      	ldr	r3, [r2, #0]
    174e:	f043 0002 	orr.w	r0, r3, #2
    1752:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1754:	07da      	lsls	r2, r3, #31
    1756:	d408      	bmi.n	176a <generic_hfclk_start+0x32>
	__asm__ volatile(
    1758:	f381 8811 	msr	BASEPRI, r1
    175c:	f3bf 8f6f 	isb	sy
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    1760:	2001      	movs	r0, #1
}
    1762:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    1766:	f004 bf10 	b.w	658a <nrfx_clock_start>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    176a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    176e:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1772:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1776:	07d3      	lsls	r3, r2, #31
    1778:	d5ee      	bpl.n	1758 <generic_hfclk_start+0x20>
			set_on_state(get_hf_flags());
    177a:	4807      	ldr	r0, [pc, #28]	; (1798 <generic_hfclk_start+0x60>)
    177c:	f004 fc19 	bl	5fb2 <set_on_state>
    1780:	f381 8811 	msr	BASEPRI, r1
    1784:	f3bf 8f6f 	isb	sy
		clkstarted_handle(CLOCK_DEVICE,
    1788:	2000      	movs	r0, #0
}
    178a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    178e:	f7ff bfab 	b.w	16e8 <clkstarted_handle.constprop.0>
    1792:	bf00      	nop
    1794:	200015f4 	.word	0x200015f4
    1798:	200015e4 	.word	0x200015e4

0000179c <generic_hfclk_stop>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    179c:	4b09      	ldr	r3, [pc, #36]	; (17c4 <generic_hfclk_stop+0x28>)
    179e:	f3bf 8f5b 	dmb	ish
    17a2:	e853 2f00 	ldrex	r2, [r3]
    17a6:	f022 0102 	bic.w	r1, r2, #2
    17aa:	e843 1000 	strex	r0, r1, [r3]
    17ae:	2800      	cmp	r0, #0
    17b0:	d1f7      	bne.n	17a2 <generic_hfclk_stop+0x6>
    17b2:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    17b6:	07d3      	lsls	r3, r2, #31
    17b8:	d402      	bmi.n	17c0 <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    17ba:	2001      	movs	r0, #1
    17bc:	f004 bf21 	b.w	6602 <nrfx_clock_stop>
}
    17c0:	4770      	bx	lr
    17c2:	bf00      	nop
    17c4:	200015f4 	.word	0x200015f4

000017c8 <z_nrf_clock_control_lf_on>:
{
    17c8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    17cc:	4936      	ldr	r1, [pc, #216]	; (18a8 <z_nrf_clock_control_lf_on+0xe0>)
    17ce:	f3bf 8f5b 	dmb	ish
    17d2:	4607      	mov	r7, r0
    17d4:	2201      	movs	r2, #1
    17d6:	e851 3f00 	ldrex	r3, [r1]
    17da:	e841 2000 	strex	r0, r2, [r1]
    17de:	2800      	cmp	r0, #0
    17e0:	d1f9      	bne.n	17d6 <z_nrf_clock_control_lf_on+0xe>
    17e2:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    17e6:	b933      	cbnz	r3, 17f6 <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    17e8:	4930      	ldr	r1, [pc, #192]	; (18ac <z_nrf_clock_control_lf_on+0xe4>)
		err = onoff_request(mgr, &cli);
    17ea:	4831      	ldr	r0, [pc, #196]	; (18b0 <z_nrf_clock_control_lf_on+0xe8>)
    17ec:	604b      	str	r3, [r1, #4]
    17ee:	60cb      	str	r3, [r1, #12]
    17f0:	608a      	str	r2, [r1, #8]
    17f2:	f004 fa9f 	bl	5d34 <onoff_request>
	switch (start_mode) {
    17f6:	1e7b      	subs	r3, r7, #1
    17f8:	2b01      	cmp	r3, #1
    17fa:	d82d      	bhi.n	1858 <z_nrf_clock_control_lf_on+0x90>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    17fc:	2f01      	cmp	r7, #1
    17fe:	d107      	bne.n	1810 <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    1800:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1804:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    1808:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    180c:	2b01      	cmp	r3, #1
    180e:	d023      	beq.n	1858 <z_nrf_clock_control_lf_on+0x90>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1810:	f004 ffa3 	bl	675a <k_is_in_isr>
    1814:	4605      	mov	r5, r0
    1816:	bb08      	cbnz	r0, 185c <z_nrf_clock_control_lf_on+0x94>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    1818:	4b26      	ldr	r3, [pc, #152]	; (18b4 <z_nrf_clock_control_lf_on+0xec>)
    181a:	781b      	ldrb	r3, [r3, #0]
    181c:	b1f3      	cbz	r3, 185c <z_nrf_clock_control_lf_on+0x94>
    p_reg->INTENCLR = mask;
    181e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1822:	2202      	movs	r2, #2
    1824:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    1828:	4606      	mov	r6, r0
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    182a:	f8df 908c 	ldr.w	r9, [pc, #140]	; 18b8 <z_nrf_clock_control_lf_on+0xf0>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    182e:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    p_reg->LFCLKSRC = (uint32_t)(source);
    1832:	f04f 0801 	mov.w	r8, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1836:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    183a:	f8d4 2418 	ldr.w	r2, [r4, #1048]	; 0x418
    183e:	03d2      	lsls	r2, r2, #15
    1840:	d516      	bpl.n	1870 <z_nrf_clock_control_lf_on+0xa8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    1842:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1846:	2b01      	cmp	r3, #1
    1848:	d001      	beq.n	184e <z_nrf_clock_control_lf_on+0x86>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    184a:	2f01      	cmp	r7, #1
    184c:	d110      	bne.n	1870 <z_nrf_clock_control_lf_on+0xa8>
	if (isr_mode) {
    184e:	b32d      	cbz	r5, 189c <z_nrf_clock_control_lf_on+0xd4>
    1850:	f386 8811 	msr	BASEPRI, r6
    1854:	f3bf 8f6f 	isb	sy
}
    1858:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	__asm__ volatile(
    185c:	f04f 0320 	mov.w	r3, #32
    1860:	f3ef 8611 	mrs	r6, BASEPRI
    1864:	f383 8812 	msr	BASEPRI_MAX, r3
    1868:	f3bf 8f6f 	isb	sy
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    186c:	2501      	movs	r5, #1
    186e:	e7dc      	b.n	182a <z_nrf_clock_control_lf_on+0x62>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1870:	4630      	mov	r0, r6
    1872:	f7ff fba5 	bl	fc0 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    1876:	f8d4 3518 	ldr.w	r3, [r4, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    187a:	2b00      	cmp	r3, #0
    187c:	d1db      	bne.n	1836 <z_nrf_clock_control_lf_on+0x6e>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    187e:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    1882:	2a00      	cmp	r2, #0
    1884:	d0d7      	beq.n	1836 <z_nrf_clock_control_lf_on+0x6e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1886:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    188a:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    188e:	f8c4 8518 	str.w	r8, [r4, #1304]	; 0x518
    1892:	f8c9 8180 	str.w	r8, [r9, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1896:	f8c4 8008 	str.w	r8, [r4, #8]
}
    189a:	e7cc      	b.n	1836 <z_nrf_clock_control_lf_on+0x6e>
    p_reg->INTENSET = mask;
    189c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    18a0:	2202      	movs	r2, #2
    18a2:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    18a6:	e7d7      	b.n	1858 <z_nrf_clock_control_lf_on+0x90>
    18a8:	200015a0 	.word	0x200015a0
    18ac:	20001590 	.word	0x20001590
    18b0:	200015c0 	.word	0x200015c0
    18b4:	200017f9 	.word	0x200017f9
    18b8:	e000e100 	.word	0xe000e100

000018bc <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    18bc:	b530      	push	{r4, r5, lr}
	return port->config;
    18be:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    18c0:	7b05      	ldrb	r5, [r0, #12]
    18c2:	f001 041f 	and.w	r4, r1, #31
	nrfx_err_t err;
	uint8_t ch;

	if (mode == GPIO_INT_MODE_DISABLED) {
    18c6:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
{
    18ca:	b085      	sub	sp, #20
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    18cc:	ea44 1445 	orr.w	r4, r4, r5, lsl #5
	if (mode == GPIO_INT_MODE_DISABLED) {
    18d0:	d105      	bne.n	18de <gpio_nrfx_pin_interrupt_configure+0x22>
		nrfx_gpiote_trigger_disable(abs_pin);
    18d2:	4620      	mov	r0, r4
    18d4:	f001 fc64 	bl	31a0 <nrfx_gpiote_trigger_disable>

		return 0;
    18d8:	2000      	movs	r0, #0
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
}
    18da:	b005      	add	sp, #20
    18dc:	bd30      	pop	{r4, r5, pc}
	nrfx_gpiote_trigger_config_t trigger_config = {
    18de:	2500      	movs	r5, #0
	if (mode == GPIO_INT_MODE_LEVEL) {
    18e0:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    18e4:	e9cd 5502 	strd	r5, r5, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    18e8:	d114      	bne.n	1914 <gpio_nrfx_pin_interrupt_configure+0x58>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    18ea:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
	nrfx_gpiote_trigger_config_t trigger_config = {
    18ee:	bf0c      	ite	eq
    18f0:	2304      	moveq	r3, #4
    18f2:	2305      	movne	r3, #5
    18f4:	f88d 3008 	strb.w	r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    18f8:	2300      	movs	r3, #0
    18fa:	4619      	mov	r1, r3
    18fc:	aa02      	add	r2, sp, #8
    18fe:	4620      	mov	r0, r4
    1900:	f001 fa8c 	bl	2e1c <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1904:	4b1f      	ldr	r3, [pc, #124]	; (1984 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    1906:	4298      	cmp	r0, r3
    1908:	d139      	bne.n	197e <gpio_nrfx_pin_interrupt_configure+0xc2>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    190a:	2101      	movs	r1, #1
    190c:	4620      	mov	r0, r4
    190e:	f001 fbff 	bl	3110 <nrfx_gpiote_trigger_enable>
	return 0;
    1912:	e7e1      	b.n	18d8 <gpio_nrfx_pin_interrupt_configure+0x1c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    1914:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    1918:	d026      	beq.n	1968 <gpio_nrfx_pin_interrupt_configure+0xac>
    191a:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    191e:	bf14      	ite	ne
    1920:	2301      	movne	r3, #1
    1922:	2302      	moveq	r3, #2
	nrfx_gpiote_trigger_config_t trigger_config = {
    1924:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    1928:	6883      	ldr	r3, [r0, #8]
    192a:	40cb      	lsrs	r3, r1
    192c:	07d9      	lsls	r1, r3, #31
    192e:	d4e3      	bmi.n	18f8 <gpio_nrfx_pin_interrupt_configure+0x3c>
    1930:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    1934:	d1e0      	bne.n	18f8 <gpio_nrfx_pin_interrupt_configure+0x3c>
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    1936:	0962      	lsrs	r2, r4, #5
        case 1: return NRF_P1;
    1938:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    193a:	f004 031f 	and.w	r3, r4, #31
        case 1: return NRF_P1;
    193e:	4a12      	ldr	r2, [pc, #72]	; (1988 <gpio_nrfx_pin_interrupt_configure+0xcc>)
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    1940:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
        case 1: return NRF_P1;
    1944:	bf18      	it	ne
    1946:	f04f 42a0 	movne.w	r2, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    194a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    194e:	07db      	lsls	r3, r3, #31
    1950:	d4d2      	bmi.n	18f8 <gpio_nrfx_pin_interrupt_configure+0x3c>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1952:	f10d 0507 	add.w	r5, sp, #7
    1956:	4629      	mov	r1, r5
    1958:	4620      	mov	r0, r4
    195a:	f001 fb85 	bl	3068 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    195e:	4b0b      	ldr	r3, [pc, #44]	; (198c <gpio_nrfx_pin_interrupt_configure+0xd0>)
    1960:	4298      	cmp	r0, r3
    1962:	d003      	beq.n	196c <gpio_nrfx_pin_interrupt_configure+0xb0>
		trigger_config.p_in_channel = &ch;
    1964:	9503      	str	r5, [sp, #12]
    1966:	e7c7      	b.n	18f8 <gpio_nrfx_pin_interrupt_configure+0x3c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    1968:	2303      	movs	r3, #3
    196a:	e7db      	b.n	1924 <gpio_nrfx_pin_interrupt_configure+0x68>
			err = nrfx_gpiote_channel_alloc(&ch);
    196c:	4628      	mov	r0, r5
    196e:	f001 fbc9 	bl	3104 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    1972:	4b04      	ldr	r3, [pc, #16]	; (1984 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    1974:	4298      	cmp	r0, r3
    1976:	d0f5      	beq.n	1964 <gpio_nrfx_pin_interrupt_configure+0xa8>
				return -ENOMEM;
    1978:	f06f 000b 	mvn.w	r0, #11
    197c:	e7ad      	b.n	18da <gpio_nrfx_pin_interrupt_configure+0x1e>
		return -EINVAL;
    197e:	f06f 0015 	mvn.w	r0, #21
    1982:	e7aa      	b.n	18da <gpio_nrfx_pin_interrupt_configure+0x1e>
    1984:	0bad0000 	.word	0x0bad0000
    1988:	50000300 	.word	0x50000300
    198c:	0bad0004 	.word	0x0bad0004

00001990 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    1990:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    1992:	f001 fba7 	bl	30e4 <nrfx_gpiote_is_init>
    1996:	4604      	mov	r4, r0
    1998:	b968      	cbnz	r0, 19b6 <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    199a:	f001 fb7b 	bl	3094 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    199e:	4b08      	ldr	r3, [pc, #32]	; (19c0 <gpio_nrfx_init+0x30>)
    19a0:	4298      	cmp	r0, r3
    19a2:	d10a      	bne.n	19ba <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    19a4:	4807      	ldr	r0, [pc, #28]	; (19c4 <gpio_nrfx_init+0x34>)
    19a6:	4621      	mov	r1, r4
    19a8:	f001 fb58 	bl	305c <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    19ac:	4622      	mov	r2, r4
    19ae:	2105      	movs	r1, #5
    19b0:	2006      	movs	r0, #6
    19b2:	f7ff fb3f 	bl	1034 <z_arm_irq_priority_set>
		return 0;
    19b6:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    19b8:	bd10      	pop	{r4, pc}
		return -EIO;
    19ba:	f06f 0004 	mvn.w	r0, #4
    19be:	e7fb      	b.n	19b8 <gpio_nrfx_init+0x28>
    19c0:	0bad0000 	.word	0x0bad0000
    19c4:	000019c9 	.word	0x000019c9

000019c8 <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    19c8:	0942      	lsrs	r2, r0, #5
{
    19ca:	b570      	push	{r4, r5, r6, lr}
    19cc:	4603      	mov	r3, r0
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    19ce:	d002      	beq.n	19d6 <nrfx_gpio_handler+0xe>
    19d0:	2a01      	cmp	r2, #1
    19d2:	d017      	beq.n	1a04 <nrfx_gpio_handler+0x3c>
}
    19d4:	bd70      	pop	{r4, r5, r6, pc}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    19d6:	4e0d      	ldr	r6, [pc, #52]	; (1a0c <nrfx_gpio_handler+0x44>)
	gpio_fire_callbacks(list, port, BIT(pin));
    19d8:	6932      	ldr	r2, [r6, #16]
    19da:	6851      	ldr	r1, [r2, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    19dc:	2900      	cmp	r1, #0
    19de:	d0f9      	beq.n	19d4 <nrfx_gpio_handler+0xc>
    *p_pin = pin_number & 0x1F;
    19e0:	f003 031f 	and.w	r3, r3, #31
    19e4:	2501      	movs	r5, #1
	return node->next;
    19e6:	680c      	ldr	r4, [r1, #0]
    19e8:	409d      	lsls	r5, r3
    19ea:	2900      	cmp	r1, #0
    19ec:	d0f2      	beq.n	19d4 <nrfx_gpio_handler+0xc>
		if (cb->pin_mask & pins) {
    19ee:	688a      	ldr	r2, [r1, #8]
    19f0:	402a      	ands	r2, r5
    19f2:	d002      	beq.n	19fa <nrfx_gpio_handler+0x32>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    19f4:	684b      	ldr	r3, [r1, #4]
    19f6:	4630      	mov	r0, r6
    19f8:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    19fa:	b12c      	cbz	r4, 1a08 <nrfx_gpio_handler+0x40>
    19fc:	6823      	ldr	r3, [r4, #0]
    19fe:	4621      	mov	r1, r4
    1a00:	461c      	mov	r4, r3
    1a02:	e7f2      	b.n	19ea <nrfx_gpio_handler+0x22>
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    1a04:	4e02      	ldr	r6, [pc, #8]	; (1a10 <nrfx_gpio_handler+0x48>)
    1a06:	e7e7      	b.n	19d8 <nrfx_gpio_handler+0x10>
    1a08:	4623      	mov	r3, r4
    1a0a:	e7f8      	b.n	19fe <nrfx_gpio_handler+0x36>
    1a0c:	00006844 	.word	0x00006844
    1a10:	0000682c 	.word	0x0000682c

00001a14 <gpio_nrfx_pin_configure>:
{
    1a14:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	return port->config;
    1a18:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1a1a:	7b3b      	ldrb	r3, [r7, #12]
    1a1c:	f001 051f 	and.w	r5, r1, #31
    1a20:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
{
    1a24:	460e      	mov	r6, r1
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1a26:	4628      	mov	r0, r5
    1a28:	f10d 0103 	add.w	r1, sp, #3
{
    1a2c:	4614      	mov	r4, r2
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1a2e:	f001 fb1b 	bl	3068 <nrfx_gpiote_channel_get>
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    1a32:	f414 3f40 	tst.w	r4, #196608	; 0x30000
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1a36:	4680      	mov	r8, r0
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    1a38:	d10b      	bne.n	1a52 <gpio_nrfx_pin_configure+0x3e>
		(void)nrfx_gpiote_pin_uninit(abs_pin);
    1a3a:	4628      	mov	r0, r5
    1a3c:	f001 fbd8 	bl	31f0 <nrfx_gpiote_pin_uninit>
		if (free_ch) {
    1a40:	4b3d      	ldr	r3, [pc, #244]	; (1b38 <gpio_nrfx_pin_configure+0x124>)
    1a42:	4598      	cmp	r8, r3
    1a44:	d103      	bne.n	1a4e <gpio_nrfx_pin_configure+0x3a>
			err = nrfx_gpiote_channel_free(ch);
    1a46:	f89d 0003 	ldrb.w	r0, [sp, #3]
    1a4a:	f001 fb55 	bl	30f8 <nrfx_gpiote_channel_free>
		return 0;
    1a4e:	2000      	movs	r0, #0
    1a50:	e00c      	b.n	1a6c <gpio_nrfx_pin_configure+0x58>
	nrfx_gpiote_trigger_config_t trigger_config = {
    1a52:	2300      	movs	r3, #0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1a54:	4619      	mov	r1, r3
    1a56:	aa02      	add	r2, sp, #8
    1a58:	4628      	mov	r0, r5
	nrfx_gpiote_trigger_config_t trigger_config = {
    1a5a:	e9cd 3302 	strd	r3, r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1a5e:	f001 f9dd 	bl	2e1c <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1a62:	4b35      	ldr	r3, [pc, #212]	; (1b38 <gpio_nrfx_pin_configure+0x124>)
    1a64:	4298      	cmp	r0, r3
    1a66:	d004      	beq.n	1a72 <gpio_nrfx_pin_configure+0x5e>
		return NRF_GPIO_PIN_PULLUP;
    1a68:	f06f 0015 	mvn.w	r0, #21
}
    1a6c:	b004      	add	sp, #16
    1a6e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (free_ch) {
    1a72:	4580      	cmp	r8, r0
    1a74:	d103      	bne.n	1a7e <gpio_nrfx_pin_configure+0x6a>
		err = nrfx_gpiote_channel_free(ch);
    1a76:	f89d 0003 	ldrb.w	r0, [sp, #3]
    1a7a:	f001 fb3d 	bl	30f8 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    1a7e:	03a3      	lsls	r3, r4, #14
    1a80:	d54b      	bpl.n	1b1a <gpio_nrfx_pin_configure+0x106>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1a82:	f240 3306 	movw	r3, #774	; 0x306
    1a86:	4023      	ands	r3, r4
    1a88:	f5b3 7f83 	cmp.w	r3, #262	; 0x106
    1a8c:	d019      	beq.n	1ac2 <gpio_nrfx_pin_configure+0xae>
    1a8e:	d80c      	bhi.n	1aaa <gpio_nrfx_pin_configure+0x96>
    1a90:	2b06      	cmp	r3, #6
    1a92:	d017      	beq.n	1ac4 <gpio_nrfx_pin_configure+0xb0>
    1a94:	d804      	bhi.n	1aa0 <gpio_nrfx_pin_configure+0x8c>
    1a96:	b1ab      	cbz	r3, 1ac4 <gpio_nrfx_pin_configure+0xb0>
    1a98:	2b02      	cmp	r3, #2
    1a9a:	d1e5      	bne.n	1a68 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0S1;
    1a9c:	2304      	movs	r3, #4
    1a9e:	e011      	b.n	1ac4 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1aa0:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    1aa4:	d1e0      	bne.n	1a68 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_H0S1;
    1aa6:	2301      	movs	r3, #1
    1aa8:	e00c      	b.n	1ac4 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1aaa:	f240 2202 	movw	r2, #514	; 0x202
    1aae:	4293      	cmp	r3, r2
    1ab0:	d027      	beq.n	1b02 <gpio_nrfx_pin_configure+0xee>
    1ab2:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
    1ab6:	d026      	beq.n	1b06 <gpio_nrfx_pin_configure+0xf2>
    1ab8:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    1abc:	d1d4      	bne.n	1a68 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_S0H1;
    1abe:	2302      	movs	r3, #2
    1ac0:	e000      	b.n	1ac4 <gpio_nrfx_pin_configure+0xb0>
		*drive = NRF_GPIO_PIN_H0D1;
    1ac2:	2307      	movs	r3, #7
		nrfx_gpiote_output_config_t output_config = {
    1ac4:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    1ac8:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    1acc:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    1ad0:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    1ad2:	f88d 3005 	strb.w	r3, [sp, #5]
	} else if (flags & GPIO_PULL_DOWN) {
    1ad6:	bf54      	ite	pl
    1ad8:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    1adc:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    1ade:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    1ae0:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    1ae4:	d511      	bpl.n	1b0a <gpio_nrfx_pin_configure+0xf6>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    1ae6:	687a      	ldr	r2, [r7, #4]
    1ae8:	2301      	movs	r3, #1
    1aea:	40b3      	lsls	r3, r6
    p_reg->OUTSET = set_mask;
    1aec:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    1af0:	2200      	movs	r2, #0
    1af2:	a901      	add	r1, sp, #4
    1af4:	4628      	mov	r0, r5
    1af6:	f001 fa3f 	bl	2f78 <nrfx_gpiote_output_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    1afa:	4b0f      	ldr	r3, [pc, #60]	; (1b38 <gpio_nrfx_pin_configure+0x124>)
    1afc:	4298      	cmp	r0, r3
    1afe:	d0a6      	beq.n	1a4e <gpio_nrfx_pin_configure+0x3a>
    1b00:	e7b2      	b.n	1a68 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0H1;
    1b02:	2305      	movs	r3, #5
    1b04:	e7de      	b.n	1ac4 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1b06:	2303      	movs	r3, #3
    1b08:	e7dc      	b.n	1ac4 <gpio_nrfx_pin_configure+0xb0>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    1b0a:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    1b0c:	bf41      	itttt	mi
    1b0e:	2301      	movmi	r3, #1
    1b10:	687a      	ldrmi	r2, [r7, #4]
    1b12:	40b3      	lslmi	r3, r6
    p_reg->OUTCLR = clr_mask;
    1b14:	f8c2 350c 	strmi.w	r3, [r2, #1292]	; 0x50c
}
    1b18:	e7ea      	b.n	1af0 <gpio_nrfx_pin_configure+0xdc>
	if (flags & GPIO_PULL_UP) {
    1b1a:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1b1c:	f04f 0300 	mov.w	r3, #0
	} else if (flags & GPIO_PULL_DOWN) {
    1b20:	bf54      	ite	pl
    1b22:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    1b26:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1b28:	461a      	mov	r2, r3
    1b2a:	a901      	add	r1, sp, #4
    1b2c:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    1b2e:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1b32:	f001 f973 	bl	2e1c <nrfx_gpiote_input_configure>
    1b36:	e7e0      	b.n	1afa <gpio_nrfx_pin_configure+0xe6>
    1b38:	0bad0000 	.word	0x0bad0000

00001b3c <qspi_get_zephyr_ret_code>:
/**
 * @brief Converts NRFX return codes to the zephyr ones
 */
static inline int qspi_get_zephyr_ret_code(nrfx_err_t res)
{
	switch (res) {
    1b3c:	f100 4074 	add.w	r0, r0, #4093640704	; 0xf4000000
    1b40:	f500 00a6 	add.w	r0, r0, #5439488	; 0x530000
    1b44:	280a      	cmp	r0, #10
    1b46:	bf9a      	itte	ls
    1b48:	4b02      	ldrls	r3, [pc, #8]	; (1b54 <qspi_get_zephyr_ret_code+0x18>)
    1b4a:	f933 0010 	ldrshls.w	r0, [r3, r0, lsl #1]
{
    1b4e:	f06f 000f 	mvnhi.w	r0, #15
	case NRFX_ERROR_BUSY:
	case NRFX_ERROR_TIMEOUT:
	default:
		return -EBUSY;
	}
}
    1b52:	4770      	bx	lr
    1b54:	00006dc4 	.word	0x00006dc4

00001b58 <qspi_nor_pages_layout>:

static void qspi_nor_pages_layout(const struct device *dev,
				  const struct flash_pages_layout **layout,
				  size_t *layout_size)
{
	*layout = &dev_layout;
    1b58:	4b02      	ldr	r3, [pc, #8]	; (1b64 <qspi_nor_pages_layout+0xc>)
    1b5a:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    1b5c:	2301      	movs	r3, #1
    1b5e:	6013      	str	r3, [r2, #0]
}
    1b60:	4770      	bx	lr
    1b62:	bf00      	nop
    1b64:	00006c14 	.word	0x00006c14

00001b68 <qspi_flash_get_parameters>:
		.write_block_size = 4,
		.erase_value = 0xff,
	};

	return &qspi_flash_parameters;
}
    1b68:	4800      	ldr	r0, [pc, #0]	; (1b6c <qspi_flash_get_parameters+0x4>)
    1b6a:	4770      	bx	lr
    1b6c:	00006ba8 	.word	0x00006ba8

00001b70 <qspi_device_init>:
{
    1b70:	b510      	push	{r4, lr}
	if (!qspi_initialized) {
    1b72:	4c08      	ldr	r4, [pc, #32]	; (1b94 <qspi_device_init+0x24>)
    1b74:	7823      	ldrb	r3, [r4, #0]
    1b76:	b95b      	cbnz	r3, 1b90 <qspi_device_init+0x20>
		res = nrfx_qspi_init(&dev_config->nrfx_cfg,
    1b78:	6902      	ldr	r2, [r0, #16]
    1b7a:	4907      	ldr	r1, [pc, #28]	; (1b98 <qspi_device_init+0x28>)
    1b7c:	6840      	ldr	r0, [r0, #4]
    1b7e:	f001 fd79 	bl	3674 <nrfx_qspi_init>
		ret = qspi_get_zephyr_ret_code(res);
    1b82:	f7ff ffdb 	bl	1b3c <qspi_get_zephyr_ret_code>
		qspi_initialized = (ret == 0);
    1b86:	fab0 f380 	clz	r3, r0
    1b8a:	095b      	lsrs	r3, r3, #5
    1b8c:	7023      	strb	r3, [r4, #0]
}
    1b8e:	bd10      	pop	{r4, pc}
	int ret = 0;
    1b90:	2000      	movs	r0, #0
	return ret;
    1b92:	e7fc      	b.n	1b8e <qspi_device_init+0x1e>
    1b94:	200017f7 	.word	0x200017f7
    1b98:	0000616f 	.word	0x0000616f

00001b9c <qspi_device_uninit.constprop.0>:
static void qspi_device_uninit(const struct device *dev)
    1b9c:	b510      	push	{r4, lr}
		while (nrfx_qspi_mem_busy_check() != NRFX_SUCCESS) {
    1b9e:	4c08      	ldr	r4, [pc, #32]	; (1bc0 <qspi_device_uninit.constprop.0+0x24>)
    1ba0:	f001 fe88 	bl	38b4 <nrfx_qspi_mem_busy_check>
    1ba4:	42a0      	cmp	r0, r4
    1ba6:	d105      	bne.n	1bb4 <qspi_device_uninit.constprop.0+0x18>
		nrfx_qspi_uninit();
    1ba8:	f001 fea6 	bl	38f8 <nrfx_qspi_uninit>
		qspi_initialized = false;
    1bac:	4b05      	ldr	r3, [pc, #20]	; (1bc4 <qspi_device_uninit.constprop.0+0x28>)
    1bae:	2200      	movs	r2, #0
    1bb0:	701a      	strb	r2, [r3, #0]
}
    1bb2:	bd10      	pop	{r4, pc}
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_BUSY_WAIT);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_busy_wait(usec_to_wait);
    1bb4:	f24c 3050 	movw	r0, #50000	; 0xc350
    1bb8:	f004 fdd5 	bl	6766 <z_impl_k_busy_wait>
}
    1bbc:	e7f0      	b.n	1ba0 <qspi_device_uninit.constprop.0+0x4>
    1bbe:	bf00      	nop
    1bc0:	0bad0000 	.word	0x0bad0000
    1bc4:	200017f7 	.word	0x200017f7

00001bc8 <qspi_wait_for_completion.isra.0>:
	if (res == NRFX_SUCCESS) {
    1bc8:	4b0c      	ldr	r3, [pc, #48]	; (1bfc <qspi_wait_for_completion.isra.0+0x34>)
    1bca:	4299      	cmp	r1, r3
static inline void qspi_wait_for_completion(const struct device *dev,
    1bcc:	b510      	push	{r4, lr}
    1bce:	4604      	mov	r4, r0
	if (res == NRFX_SUCCESS) {
    1bd0:	d10f      	bne.n	1bf2 <qspi_wait_for_completion.isra.0+0x2a>
    1bd2:	f04f 0320 	mov.w	r3, #32
    1bd6:	f3ef 8011 	mrs	r0, BASEPRI
    1bda:	f383 8812 	msr	BASEPRI_MAX, r3
    1bde:	f3bf 8f6f 	isb	sy
		while (!dev_data->ready) {
    1be2:	7823      	ldrb	r3, [r4, #0]
    1be4:	b133      	cbz	r3, 1bf4 <qspi_wait_for_completion.isra.0+0x2c>
		dev_data->ready = false;
    1be6:	2300      	movs	r3, #0
    1be8:	7023      	strb	r3, [r4, #0]
	__asm__ volatile(
    1bea:	f380 8811 	msr	BASEPRI, r0
    1bee:	f3bf 8f6f 	isb	sy
}
    1bf2:	bd10      	pop	{r4, pc}
    1bf4:	f7ff f9e4 	bl	fc0 <arch_cpu_atomic_idle>
    1bf8:	e7eb      	b.n	1bd2 <qspi_wait_for_completion.isra.0+0xa>
    1bfa:	bf00      	nop
    1bfc:	0bad0000 	.word	0x0bad0000

00001c00 <qspi_nor_read>:
{
    1c00:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1c04:	4680      	mov	r8, r0
    1c06:	b085      	sub	sp, #20
    1c08:	460f      	mov	r7, r1
    1c0a:	461c      	mov	r4, r3
	if (!dest) {
    1c0c:	4616      	mov	r6, r2
    1c0e:	2a00      	cmp	r2, #0
    1c10:	f000 8092 	beq.w	1d38 <qspi_nor_read+0x138>
	if (!size) {
    1c14:	2b00      	cmp	r3, #0
    1c16:	f000 808d 	beq.w	1d34 <qspi_nor_read+0x134>
	if (addr < 0 ||
    1c1a:	2900      	cmp	r1, #0
	const struct qspi_nor_config *params = dev->config;
    1c1c:	6842      	ldr	r2, [r0, #4]
	if (addr < 0 ||
    1c1e:	f2c0 808b 	blt.w	1d38 <qspi_nor_read+0x138>
    1c22:	6992      	ldr	r2, [r2, #24]
	    (addr + size) > params->size) {
    1c24:	18cb      	adds	r3, r1, r3
	if (addr < 0 ||
    1c26:	4293      	cmp	r3, r2
    1c28:	f200 8086 	bhi.w	1d38 <qspi_nor_read+0x138>
	int rc = qspi_device_init(dev);
    1c2c:	f7ff ffa0 	bl	1b70 <qspi_device_init>
	if (rc != 0) {
    1c30:	4605      	mov	r5, r0
    1c32:	2800      	cmp	r0, #0
    1c34:	d178      	bne.n	1d28 <qspi_nor_read+0x128>
	if (flash_prefix > size) {
    1c36:	427d      	negs	r5, r7
    1c38:	f005 0503 	and.w	r5, r5, #3
    1c3c:	42a5      	cmp	r5, r4
    1c3e:	bf28      	it	cs
    1c40:	4625      	movcs	r5, r4
	off_t dest_prefix = (WORD_SIZE - (off_t)dptr % WORD_SIZE) % WORD_SIZE;
    1c42:	4273      	negs	r3, r6
    1c44:	f003 0303 	and.w	r3, r3, #3
    1c48:	f006 0903 	and.w	r9, r6, #3
    1c4c:	bf58      	it	pl
    1c4e:	f1c3 0900 	rsbpl	r9, r3, #0
    1c52:	f1c9 0900 	rsb	r9, r9, #0
    1c56:	f009 0903 	and.w	r9, r9, #3
    1c5a:	45a1      	cmp	r9, r4
    1c5c:	bf28      	it	cs
    1c5e:	46a1      	movcs	r9, r4
	off_t flash_suffix = (size - flash_prefix) % WORD_SIZE;
    1c60:	1b63      	subs	r3, r4, r5
			    (size - dest_prefix) % WORD_SIZE;
    1c62:	eba4 0409 	sub.w	r4, r4, r9
    1c66:	f024 0403 	bic.w	r4, r4, #3
	off_t flash_middle = size - flash_prefix - flash_suffix;
    1c6a:	f023 0a03 	bic.w	sl, r3, #3
	if (flash_middle > dest_middle) {
    1c6e:	45a2      	cmp	sl, r4
		flash_suffix = size - flash_prefix - flash_middle;
    1c70:	bfc8      	it	gt
    1c72:	46a2      	movgt	sl, r4
    1c74:	f003 0b03 	and.w	fp, r3, #3
    1c78:	bfc8      	it	gt
    1c7a:	eba3 0b04 	subgt.w	fp, r3, r4
	if (flash_middle != 0) {
    1c7e:	f1ba 0f00 	cmp.w	sl, #0
    1c82:	d018      	beq.n	1cb6 <qspi_nor_read+0xb6>
		res = nrfx_qspi_read(dptr + dest_prefix, flash_middle,
    1c84:	eb06 0309 	add.w	r3, r6, r9
    1c88:	197a      	adds	r2, r7, r5
    1c8a:	4651      	mov	r1, sl
    1c8c:	4618      	mov	r0, r3
    1c8e:	9301      	str	r3, [sp, #4]
    1c90:	f004 fd30 	bl	66f4 <nrfx_qspi_read>
    1c94:	4604      	mov	r4, r0
		qspi_wait_for_completion(dev, res);
    1c96:	4601      	mov	r1, r0
    1c98:	f8d8 0010 	ldr.w	r0, [r8, #16]
    1c9c:	f7ff ff94 	bl	1bc8 <qspi_wait_for_completion.isra.0>
		if (res != NRFX_SUCCESS) {
    1ca0:	4a27      	ldr	r2, [pc, #156]	; (1d40 <qspi_nor_read+0x140>)
    1ca2:	4294      	cmp	r4, r2
    1ca4:	d13c      	bne.n	1d20 <qspi_nor_read+0x120>
		if (flash_prefix != dest_prefix) {
    1ca6:	454d      	cmp	r5, r9
    1ca8:	d005      	beq.n	1cb6 <qspi_nor_read+0xb6>
			memmove(dptr + flash_prefix, dptr + dest_prefix, flash_middle);
    1caa:	9b01      	ldr	r3, [sp, #4]
    1cac:	4652      	mov	r2, sl
    1cae:	4619      	mov	r1, r3
    1cb0:	1970      	adds	r0, r6, r5
    1cb2:	f004 f94a 	bl	5f4a <memmove>
	if (flash_prefix != 0) {
    1cb6:	b1c5      	cbz	r5, 1cea <qspi_nor_read+0xea>
				     (WORD_SIZE - flash_prefix));
    1cb8:	f1c5 0904 	rsb	r9, r5, #4
		res = nrfx_qspi_read(buf, WORD_SIZE, addr -
    1cbc:	eba7 0209 	sub.w	r2, r7, r9
    1cc0:	2104      	movs	r1, #4
    1cc2:	a802      	add	r0, sp, #8
    1cc4:	f004 fd16 	bl	66f4 <nrfx_qspi_read>
    1cc8:	4604      	mov	r4, r0
		qspi_wait_for_completion(dev, res);
    1cca:	4601      	mov	r1, r0
    1ccc:	f8d8 0010 	ldr.w	r0, [r8, #16]
    1cd0:	f7ff ff7a 	bl	1bc8 <qspi_wait_for_completion.isra.0>
		if (res != NRFX_SUCCESS) {
    1cd4:	4b1a      	ldr	r3, [pc, #104]	; (1d40 <qspi_nor_read+0x140>)
    1cd6:	429c      	cmp	r4, r3
    1cd8:	d122      	bne.n	1d20 <qspi_nor_read+0x120>
		memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix);
    1cda:	f109 0308 	add.w	r3, r9, #8
    1cde:	462a      	mov	r2, r5
    1ce0:	eb0d 0103 	add.w	r1, sp, r3
    1ce4:	4630      	mov	r0, r6
    1ce6:	f004 f947 	bl	5f78 <memcpy>
	if (flash_suffix != 0) {
    1cea:	f1bb 0f00 	cmp.w	fp, #0
    1cee:	d016      	beq.n	1d1e <qspi_nor_read+0x11e>
		res = nrfx_qspi_read(buf, WORD_SIZE * 2,
    1cf0:	2108      	movs	r1, #8
				     addr + flash_prefix + flash_middle);
    1cf2:	197a      	adds	r2, r7, r5
		res = nrfx_qspi_read(buf, WORD_SIZE * 2,
    1cf4:	4452      	add	r2, sl
    1cf6:	eb0d 0001 	add.w	r0, sp, r1
    1cfa:	f004 fcfb 	bl	66f4 <nrfx_qspi_read>
    1cfe:	4604      	mov	r4, r0
		qspi_wait_for_completion(dev, res);
    1d00:	4601      	mov	r1, r0
    1d02:	f8d8 0010 	ldr.w	r0, [r8, #16]
    1d06:	f7ff ff5f 	bl	1bc8 <qspi_wait_for_completion.isra.0>
		if (res != NRFX_SUCCESS) {
    1d0a:	4b0d      	ldr	r3, [pc, #52]	; (1d40 <qspi_nor_read+0x140>)
    1d0c:	429c      	cmp	r4, r3
    1d0e:	d107      	bne.n	1d20 <qspi_nor_read+0x120>
		memcpy(dptr + flash_prefix + flash_middle, buf, flash_suffix);
    1d10:	eb0a 0005 	add.w	r0, sl, r5
    1d14:	465a      	mov	r2, fp
    1d16:	a902      	add	r1, sp, #8
    1d18:	4430      	add	r0, r6
    1d1a:	f004 f92d 	bl	5f78 <memcpy>
	return res;
    1d1e:	4c08      	ldr	r4, [pc, #32]	; (1d40 <qspi_nor_read+0x140>)
	rc = qspi_get_zephyr_ret_code(res);
    1d20:	4620      	mov	r0, r4
    1d22:	f7ff ff0b 	bl	1b3c <qspi_get_zephyr_ret_code>
    1d26:	4605      	mov	r5, r0
	qspi_device_uninit(dev);
    1d28:	f7ff ff38 	bl	1b9c <qspi_device_uninit.constprop.0>
}
    1d2c:	4628      	mov	r0, r5
    1d2e:	b005      	add	sp, #20
    1d30:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		return 0;
    1d34:	461d      	mov	r5, r3
    1d36:	e7f9      	b.n	1d2c <qspi_nor_read+0x12c>
		return -EINVAL;
    1d38:	f06f 0515 	mvn.w	r5, #21
    1d3c:	e7f6      	b.n	1d2c <qspi_nor_read+0x12c>
    1d3e:	bf00      	nop
    1d40:	0bad0000 	.word	0x0bad0000

00001d44 <qspi_nor_write>:
{
    1d44:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
    1d48:	4605      	mov	r5, r0
    1d4a:	460e      	mov	r6, r1
    1d4c:	4698      	mov	r8, r3
	if (!src) {
    1d4e:	4617      	mov	r7, r2
    1d50:	2a00      	cmp	r2, #0
    1d52:	d074      	beq.n	1e3e <qspi_nor_write+0xfa>
	if ((size == 0)
    1d54:	2b00      	cmp	r3, #0
    1d56:	d072      	beq.n	1e3e <qspi_nor_write+0xfa>
	    || ((size > 4) && ((size % 4U) != 0))) {
    1d58:	2b04      	cmp	r3, #4
    1d5a:	d902      	bls.n	1d62 <qspi_nor_write+0x1e>
    1d5c:	f013 0f03 	tst.w	r3, #3
    1d60:	d16d      	bne.n	1e3e <qspi_nor_write+0xfa>
	if ((addr % 4U) != 0) {
    1d62:	07b3      	lsls	r3, r6, #30
    1d64:	d16b      	bne.n	1e3e <qspi_nor_write+0xfa>
	if (addr < 0 ||
    1d66:	2e00      	cmp	r6, #0
	const struct qspi_nor_config *params = dev->config;
    1d68:	686a      	ldr	r2, [r5, #4]
	if (addr < 0 ||
    1d6a:	db68      	blt.n	1e3e <qspi_nor_write+0xfa>
    1d6c:	6992      	ldr	r2, [r2, #24]
	    (addr + size) > params->size) {
    1d6e:	eb06 0308 	add.w	r3, r6, r8
	if (addr < 0 ||
    1d72:	4293      	cmp	r3, r2
    1d74:	d863      	bhi.n	1e3e <qspi_nor_write+0xfa>
	int rc = qspi_device_init(dev);
    1d76:	4628      	mov	r0, r5
    1d78:	f7ff fefa 	bl	1b70 <qspi_device_init>
	if (rc != 0) {
    1d7c:	4604      	mov	r4, r0
    1d7e:	b950      	cbnz	r0, 1d96 <qspi_nor_write+0x52>
	res = qspi_nor_write_protection_set(dev, false);
    1d80:	f004 fa45 	bl	620e <qspi_nor_write_protection_set.isra.0>
	if (!res) {
    1d84:	4604      	mov	r4, r0
    1d86:	b160      	cbz	r0, 1da2 <qspi_nor_write+0x5e>
	int res2 = qspi_nor_write_protection_set(dev, true);
    1d88:	2001      	movs	r0, #1
    1d8a:	f004 fa40 	bl	620e <qspi_nor_write_protection_set.isra.0>
	rc = qspi_get_zephyr_ret_code(res);
    1d8e:	4620      	mov	r0, r4
    1d90:	f7ff fed4 	bl	1b3c <qspi_get_zephyr_ret_code>
    1d94:	4604      	mov	r4, r0
	qspi_device_uninit(dev);
    1d96:	f7ff ff01 	bl	1b9c <qspi_device_uninit.constprop.0>
}
    1d9a:	4620      	mov	r0, r4
    1d9c:	b004      	add	sp, #16
    1d9e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		if (size < 4U) {
    1da2:	f1b8 0f03 	cmp.w	r8, #3
    1da6:	d81c      	bhi.n	1de2 <qspi_nor_write+0x9e>
	res = nrfx_qspi_read(buf, sizeof(buf), addr);
    1da8:	4632      	mov	r2, r6
    1daa:	2104      	movs	r1, #4
    1dac:	4668      	mov	r0, sp
    1dae:	f004 fca1 	bl	66f4 <nrfx_qspi_read>
    1db2:	4604      	mov	r4, r0
	qspi_wait_for_completion(dev, res);
    1db4:	4601      	mov	r1, r0
    1db6:	6928      	ldr	r0, [r5, #16]
    1db8:	f7ff ff06 	bl	1bc8 <qspi_wait_for_completion.isra.0>
	if (res == NRFX_SUCCESS) {
    1dbc:	4b21      	ldr	r3, [pc, #132]	; (1e44 <qspi_nor_write+0x100>)
    1dbe:	429c      	cmp	r4, r3
    1dc0:	d132      	bne.n	1e28 <qspi_nor_write+0xe4>
		memcpy(buf, sptr, slen);
    1dc2:	4642      	mov	r2, r8
    1dc4:	4639      	mov	r1, r7
    1dc6:	4668      	mov	r0, sp
    1dc8:	f004 f8d6 	bl	5f78 <memcpy>
		res = nrfx_qspi_write(buf, sizeof(buf), addr);
    1dcc:	4632      	mov	r2, r6
    1dce:	2104      	movs	r1, #4
    1dd0:	4668      	mov	r0, sp
			res = nrfx_qspi_write(src, size, addr);
    1dd2:	f004 fc8c 	bl	66ee <nrfx_qspi_write>
    1dd6:	4604      	mov	r4, r0
			qspi_wait_for_completion(dev, res);
    1dd8:	4601      	mov	r1, r0
    1dda:	6928      	ldr	r0, [r5, #16]
    1ddc:	f7ff fef4 	bl	1bc8 <qspi_wait_for_completion.isra.0>
    1de0:	e022      	b.n	1e28 <qspi_nor_write+0xe4>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
{
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    1de2:	f007 4360 	and.w	r3, r7, #3758096384	; 0xe0000000
		} else if (!nrfx_is_in_ram(src)) {
    1de6:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    1dea:	d024      	beq.n	1e36 <qspi_nor_write+0xf2>
			if (res == NRFX_SUCCESS) {
    1dec:	f8df a054 	ldr.w	sl, [pc, #84]	; 1e44 <qspi_nor_write+0x100>
			size_t len = MIN(slen, sizeof(buf));
    1df0:	f1b8 0f10 	cmp.w	r8, #16
    1df4:	46c1      	mov	r9, r8
    1df6:	bf28      	it	cs
    1df8:	f04f 0910 	movcs.w	r9, #16
			memcpy(buf, sp, len);
    1dfc:	464a      	mov	r2, r9
    1dfe:	4639      	mov	r1, r7
    1e00:	4668      	mov	r0, sp
    1e02:	f004 f8b9 	bl	5f78 <memcpy>
			res = nrfx_qspi_write(buf, sizeof(buf), addr);
    1e06:	4632      	mov	r2, r6
    1e08:	2110      	movs	r1, #16
    1e0a:	4668      	mov	r0, sp
    1e0c:	f004 fc6f 	bl	66ee <nrfx_qspi_write>
    1e10:	4604      	mov	r4, r0
			qspi_wait_for_completion(dev, res);
    1e12:	4601      	mov	r1, r0
    1e14:	6928      	ldr	r0, [r5, #16]
    1e16:	f7ff fed7 	bl	1bc8 <qspi_wait_for_completion.isra.0>
			if (res == NRFX_SUCCESS) {
    1e1a:	4554      	cmp	r4, sl
    1e1c:	d104      	bne.n	1e28 <qspi_nor_write+0xe4>
		while ((slen > 0) && (res == NRFX_SUCCESS)) {
    1e1e:	ebb8 0809 	subs.w	r8, r8, r9
				sp += len;
    1e22:	444f      	add	r7, r9
				addr += len;
    1e24:	444e      	add	r6, r9
		while ((slen > 0) && (res == NRFX_SUCCESS)) {
    1e26:	d1e3      	bne.n	1df0 <qspi_nor_write+0xac>
	int res2 = qspi_nor_write_protection_set(dev, true);
    1e28:	2001      	movs	r0, #1
    1e2a:	f004 f9f0 	bl	620e <qspi_nor_write_protection_set.isra.0>
		res = res2;
    1e2e:	2c00      	cmp	r4, #0
    1e30:	bf08      	it	eq
    1e32:	4604      	moveq	r4, r0
    1e34:	e7ab      	b.n	1d8e <qspi_nor_write+0x4a>
			res = nrfx_qspi_write(src, size, addr);
    1e36:	4632      	mov	r2, r6
    1e38:	4641      	mov	r1, r8
    1e3a:	4638      	mov	r0, r7
    1e3c:	e7c9      	b.n	1dd2 <qspi_nor_write+0x8e>
		return -EINVAL;
    1e3e:	f06f 0415 	mvn.w	r4, #21
    1e42:	e7aa      	b.n	1d9a <qspi_nor_write+0x56>
    1e44:	0bad0000 	.word	0x0bad0000

00001e48 <qspi_nor_erase>:
{
    1e48:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	if (addr < 0 ||
    1e4c:	1e0d      	subs	r5, r1, #0
	const struct qspi_nor_config *params = dev->config;
    1e4e:	f8d0 9004 	ldr.w	r9, [r0, #4]
{
    1e52:	4680      	mov	r8, r0
    1e54:	4617      	mov	r7, r2
	if (addr < 0 ||
    1e56:	db5a      	blt.n	1f0e <qspi_nor_erase+0xc6>
    1e58:	f8d9 3018 	ldr.w	r3, [r9, #24]
	    (addr + size) > params->size) {
    1e5c:	18aa      	adds	r2, r5, r2
	if (addr < 0 ||
    1e5e:	429a      	cmp	r2, r3
    1e60:	d855      	bhi.n	1f0e <qspi_nor_erase+0xc6>
	if ((addr % QSPI_SECTOR_SIZE) != 0) {
    1e62:	f3c5 020b 	ubfx	r2, r5, #0, #12
	if ((size == 0) || (size % QSPI_SECTOR_SIZE) != 0) {
    1e66:	2f00      	cmp	r7, #0
    1e68:	d051      	beq.n	1f0e <qspi_nor_erase+0xc6>
    1e6a:	f3c7 030b 	ubfx	r3, r7, #0, #12
    1e6e:	4313      	orrs	r3, r2
    1e70:	d14d      	bne.n	1f0e <qspi_nor_erase+0xc6>
	rv = qspi_device_init(dev);
    1e72:	f7ff fe7d 	bl	1b70 <qspi_device_init>
	if (rv != 0) {
    1e76:	4604      	mov	r4, r0
    1e78:	b9f0      	cbnz	r0, 1eb8 <qspi_nor_erase+0x70>
	rv = qspi_nor_write_protection_set(dev, false);
    1e7a:	f004 f9c8 	bl	620e <qspi_nor_write_protection_set.isra.0>
	if (rv != 0) {
    1e7e:	4604      	mov	r4, r0
    1e80:	b9d0      	cbnz	r0, 1eb8 <qspi_nor_erase+0x70>
		if (res == NRFX_SUCCESS) {
    1e82:	f8df a094 	ldr.w	sl, [pc, #148]	; 1f18 <qspi_nor_erase+0xd0>
		if (size == params->size) {
    1e86:	f8d9 3018 	ldr.w	r3, [r9, #24]
    1e8a:	42bb      	cmp	r3, r7
    1e8c:	d119      	bne.n	1ec2 <qspi_nor_erase+0x7a>
			res = nrfx_qspi_chip_erase();
    1e8e:	f004 fc34 	bl	66fa <nrfx_qspi_chip_erase>
    1e92:	46bb      	mov	fp, r7
    1e94:	4606      	mov	r6, r0
		qspi_wait_for_completion(dev, res);
    1e96:	f8d8 0010 	ldr.w	r0, [r8, #16]
    1e9a:	4631      	mov	r1, r6
    1e9c:	f7ff fe94 	bl	1bc8 <qspi_wait_for_completion.isra.0>
		if (res == NRFX_SUCCESS) {
    1ea0:	4556      	cmp	r6, sl
    1ea2:	d124      	bne.n	1eee <qspi_nor_erase+0xa6>
	while (size > 0) {
    1ea4:	ebb7 070b 	subs.w	r7, r7, fp
			addr += adj;
    1ea8:	445d      	add	r5, fp
	while (size > 0) {
    1eaa:	d1ec      	bne.n	1e86 <qspi_nor_erase+0x3e>
	int rv2 = qspi_nor_write_protection_set(dev, true);
    1eac:	2001      	movs	r0, #1
    1eae:	f004 f9ae 	bl	620e <qspi_nor_write_protection_set.isra.0>
    1eb2:	2c00      	cmp	r4, #0
    1eb4:	bf08      	it	eq
    1eb6:	4604      	moveq	r4, r0
	qspi_device_uninit(dev);
    1eb8:	f7ff fe70 	bl	1b9c <qspi_device_uninit.constprop.0>
}
    1ebc:	4620      	mov	r0, r4
    1ebe:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
		} else if ((size >= QSPI_BLOCK_SIZE) &&
    1ec2:	f5b7 3f80 	cmp.w	r7, #65536	; 0x10000
    1ec6:	d309      	bcc.n	1edc <qspi_nor_erase+0x94>
			   QSPI_IS_BLOCK_ALIGNED(addr)) {
    1ec8:	b2ab      	uxth	r3, r5
		} else if ((size >= QSPI_BLOCK_SIZE) &&
    1eca:	b9ab      	cbnz	r3, 1ef8 <qspi_nor_erase+0xb0>
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, addr);
    1ecc:	4629      	mov	r1, r5
    1ece:	2001      	movs	r0, #1
    1ed0:	f001 fd66 	bl	39a0 <nrfx_qspi_erase>
			adj = QSPI_BLOCK_SIZE;
    1ed4:	f44f 3b80 	mov.w	fp, #65536	; 0x10000
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, addr);
    1ed8:	4606      	mov	r6, r0
			adj = QSPI_BLOCK_SIZE;
    1eda:	e7dc      	b.n	1e96 <qspi_nor_erase+0x4e>
		} else if ((size >= QSPI_SECTOR_SIZE) &&
    1edc:	f5b7 5f80 	cmp.w	r7, #4096	; 0x1000
    1ee0:	d20a      	bcs.n	1ef8 <qspi_nor_erase+0xb0>
		qspi_wait_for_completion(dev, res);
    1ee2:	490c      	ldr	r1, [pc, #48]	; (1f14 <qspi_nor_erase+0xcc>)
    1ee4:	f8d8 0010 	ldr.w	r0, [r8, #16]
			res = NRFX_ERROR_INVALID_PARAM;
    1ee8:	4e0a      	ldr	r6, [pc, #40]	; (1f14 <qspi_nor_erase+0xcc>)
		qspi_wait_for_completion(dev, res);
    1eea:	f7ff fe6d 	bl	1bc8 <qspi_wait_for_completion.isra.0>
			rv = qspi_get_zephyr_ret_code(res);
    1eee:	4630      	mov	r0, r6
    1ef0:	f7ff fe24 	bl	1b3c <qspi_get_zephyr_ret_code>
    1ef4:	4604      	mov	r4, r0
			break;
    1ef6:	e7d9      	b.n	1eac <qspi_nor_erase+0x64>
			   QSPI_IS_SECTOR_ALIGNED(addr)) {
    1ef8:	f3c5 000b 	ubfx	r0, r5, #0, #12
		} else if ((size >= QSPI_SECTOR_SIZE) &&
    1efc:	2800      	cmp	r0, #0
    1efe:	d1f0      	bne.n	1ee2 <qspi_nor_erase+0x9a>
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, addr);
    1f00:	4629      	mov	r1, r5
    1f02:	f001 fd4d 	bl	39a0 <nrfx_qspi_erase>
			adj = QSPI_SECTOR_SIZE;
    1f06:	f44f 5b80 	mov.w	fp, #4096	; 0x1000
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, addr);
    1f0a:	4606      	mov	r6, r0
			adj = QSPI_SECTOR_SIZE;
    1f0c:	e7c3      	b.n	1e96 <qspi_nor_erase+0x4e>
		return -EINVAL;
    1f0e:	f06f 0415 	mvn.w	r4, #21
    1f12:	e7d3      	b.n	1ebc <qspi_nor_erase+0x74>
    1f14:	0bad0004 	.word	0x0bad0004
    1f18:	0bad0000 	.word	0x0bad0000

00001f1c <qspi_nor_init>:
{
    1f1c:	b570      	push	{r4, r5, r6, lr}
	int ret = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    1f1e:	6843      	ldr	r3, [r0, #4]
    1f20:	6a1d      	ldr	r5, [r3, #32]
{
    1f22:	b086      	sub	sp, #24
    1f24:	4604      	mov	r4, r0
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    1f26:	aa03      	add	r2, sp, #12
    1f28:	2100      	movs	r1, #0
    1f2a:	4628      	mov	r0, r5
    1f2c:	f004 fa0f 	bl	634e <pinctrl_lookup_state>
	if (ret < 0) {
    1f30:	2800      	cmp	r0, #0
    1f32:	db4a      	blt.n	1fca <qspi_nor_init+0xae>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    1f34:	9b03      	ldr	r3, [sp, #12]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    1f36:	682a      	ldr	r2, [r5, #0]
    1f38:	7919      	ldrb	r1, [r3, #4]
    1f3a:	6818      	ldr	r0, [r3, #0]
    1f3c:	f000 fb62 	bl	2604 <pinctrl_configure_pins>
	if (ret < 0) {
    1f40:	2800      	cmp	r0, #0
    1f42:	db42      	blt.n	1fca <qspi_nor_init+0xae>
	IRQ_CONNECT(DT_IRQN(QSPI_NODE), DT_IRQ(QSPI_NODE, priority),
    1f44:	2200      	movs	r2, #0
    1f46:	2101      	movs	r1, #1
    1f48:	2029      	movs	r0, #41	; 0x29
    1f4a:	f7ff f873 	bl	1034 <z_arm_irq_priority_set>
	const struct qspi_nor_config *dev_config = dev->config;
    1f4e:	6865      	ldr	r5, [r4, #4]
	nrfx_err_t res = nrfx_qspi_init(&dev_config->nrfx_cfg,
    1f50:	6922      	ldr	r2, [r4, #16]
    1f52:	4930      	ldr	r1, [pc, #192]	; (2014 <qspi_nor_init+0xf8>)
    1f54:	4628      	mov	r0, r5
    1f56:	f001 fb8d 	bl	3674 <nrfx_qspi_init>
	int ret = qspi_get_zephyr_ret_code(res);
    1f5a:	f7ff fdef 	bl	1b3c <qspi_get_zephyr_ret_code>
	if (ret < 0) {
    1f5e:	2800      	cmp	r0, #0
    1f60:	db33      	blt.n	1fca <qspi_nor_init+0xae>
		bool qe_value = (prot_if->writeoc == NRF_QSPI_WRITEOC_PP4IO) ||
    1f62:	7aeb      	ldrb	r3, [r5, #11]
				(prot_if->readoc == NRF_QSPI_READOC_READ4IO) ||
    1f64:	3b02      	subs	r3, #2
    1f66:	2b01      	cmp	r3, #1
    1f68:	d931      	bls.n	1fce <qspi_nor_init+0xb2>
				(prot_if->writeoc == NRF_QSPI_WRITEOC_PP4O)  ||
    1f6a:	7aad      	ldrb	r5, [r5, #10]
    1f6c:	3d03      	subs	r5, #3
    1f6e:	2d01      	cmp	r5, #1
    1f70:	bf8c      	ite	hi
    1f72:	2500      	movhi	r5, #0
    1f74:	2501      	movls	r5, #1
		ret = qspi_rdsr(dev, sr_num);
    1f76:	f004 f92f 	bl	61d8 <qspi_rdsr.constprop.0.isra.0>
		if (ret < 0) {
    1f7a:	2800      	cmp	r0, #0
    1f7c:	db25      	blt.n	1fca <qspi_nor_init+0xae>
		uint8_t sr = (uint8_t)ret;
    1f7e:	b2c2      	uxtb	r2, r0
		if (qe_state != qe_value) {
    1f80:	f3c0 1080 	ubfx	r0, r0, #6, #1
    1f84:	4285      	cmp	r5, r0
    1f86:	ad01      	add	r5, sp, #4
    1f88:	d123      	bne.n	1fd2 <qspi_nor_init+0xb6>
	qspi_device_uninit(dev);
    1f8a:	f7ff fe07 	bl	1b9c <qspi_device_uninit.constprop.0>
	const struct qspi_cmd cmd = {
    1f8e:	2603      	movs	r6, #3
    1f90:	2300      	movs	r3, #0
    1f92:	e9cd 6302 	strd	r6, r3, [sp, #8]
    1f96:	9304      	str	r3, [sp, #16]
	int ret = qspi_device_init(dev);
    1f98:	4620      	mov	r0, r4
	const struct qspi_cmd cmd = {
    1f9a:	239f      	movs	r3, #159	; 0x9f
	const struct qspi_buf rx_buf = {
    1f9c:	f8cd d004 	str.w	sp, [sp, #4]
	const struct qspi_cmd cmd = {
    1fa0:	f88d 300c 	strb.w	r3, [sp, #12]
    1fa4:	9505      	str	r5, [sp, #20]
	int ret = qspi_device_init(dev);
    1fa6:	f7ff fde3 	bl	1b70 <qspi_device_init>
	if (ret == 0) {
    1faa:	4601      	mov	r1, r0
    1fac:	bb68      	cbnz	r0, 200a <qspi_nor_init+0xee>
		ret = qspi_send_cmd(dev, &cmd, false);
    1fae:	a803      	add	r0, sp, #12
    1fb0:	f004 f8e1 	bl	6176 <qspi_send_cmd.constprop.0>
    1fb4:	4605      	mov	r5, r0
	qspi_device_uninit(dev);
    1fb6:	f7ff fdf1 	bl	1b9c <qspi_device_uninit.constprop.0>
	if (ret != 0) {
    1fba:	bb45      	cbnz	r5, 200e <qspi_nor_init+0xf2>
	if (memcmp(qnc->id, id, SPI_NOR_MAX_ID_LEN) != 0) {
    1fbc:	6860      	ldr	r0, [r4, #4]
    1fbe:	4632      	mov	r2, r6
    1fc0:	4669      	mov	r1, sp
    1fc2:	301c      	adds	r0, #28
    1fc4:	f003 ffb1 	bl	5f2a <memcmp>
    1fc8:	bb08      	cbnz	r0, 200e <qspi_nor_init+0xf2>
}
    1fca:	b006      	add	sp, #24
    1fcc:	bd70      	pop	{r4, r5, r6, pc}
				(prot_if->readoc == NRF_QSPI_READOC_READ4IO) ||
    1fce:	2501      	movs	r5, #1
    1fd0:	e7d1      	b.n	1f76 <qspi_nor_init+0x5a>
	uint8_t sr_array[2] = {0};
    1fd2:	2300      	movs	r3, #0
	const struct qspi_buf sr_buf = {
    1fd4:	2101      	movs	r1, #1
			sr ^= qe_mask;
    1fd6:	f082 0240 	eor.w	r2, r2, #64	; 0x40
	ret = qspi_send_cmd(dev, &cmd, true);
    1fda:	a803      	add	r0, sp, #12
	struct qspi_cmd cmd = {
    1fdc:	e9cd 1302 	strd	r1, r3, [sp, #8]
	uint8_t sr_array[2] = {0};
    1fe0:	f8ad 3000 	strh.w	r3, [sp]
	const struct qspi_buf sr_buf = {
    1fe4:	f8cd d004 	str.w	sp, [sp, #4]
		sr_array[0] = sr_val;
    1fe8:	f88d 2000 	strb.w	r2, [sp]
	struct qspi_cmd cmd = {
    1fec:	9305      	str	r3, [sp, #20]
    1fee:	f88d 100c 	strb.w	r1, [sp, #12]
    1ff2:	9504      	str	r5, [sp, #16]
	ret = qspi_send_cmd(dev, &cmd, true);
    1ff4:	f004 f8bf 	bl	6176 <qspi_send_cmd.constprop.0>
	if (ret == 0) {
    1ff8:	2800      	cmp	r0, #0
    1ffa:	d1e6      	bne.n	1fca <qspi_nor_init+0xae>
		ret = qspi_rdsr(dev, 1);
    1ffc:	f004 f8ec 	bl	61d8 <qspi_rdsr.constprop.0.isra.0>
		 && ((ret & SPI_NOR_WIP_BIT) != 0U));
    2000:	2800      	cmp	r0, #0
    2002:	dbe2      	blt.n	1fca <qspi_nor_init+0xae>
    2004:	07c3      	lsls	r3, r0, #31
    2006:	d4f9      	bmi.n	1ffc <qspi_nor_init+0xe0>
    2008:	e7bf      	b.n	1f8a <qspi_nor_init+0x6e>
	qspi_device_uninit(dev);
    200a:	f7ff fdc7 	bl	1b9c <qspi_device_uninit.constprop.0>
		return -ENODEV;
    200e:	f06f 0012 	mvn.w	r0, #18
    2012:	e7da      	b.n	1fca <qspi_nor_init+0xae>
    2014:	0000616f 	.word	0x0000616f

00002018 <flash_nrf_pages_layout>:

static void flash_nrf_pages_layout(const struct device *dev,
				     const struct flash_pages_layout **layout,
				     size_t *layout_size)
{
	*layout = &dev_layout;
    2018:	4b02      	ldr	r3, [pc, #8]	; (2024 <flash_nrf_pages_layout+0xc>)
    201a:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    201c:	2301      	movs	r3, #1
    201e:	6013      	str	r3, [r2, #0]
}
    2020:	4770      	bx	lr
    2022:	bf00      	nop
    2024:	20001610 	.word	0x20001610

00002028 <flash_nrf_get_parameters>:
flash_nrf_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nrf_parameters;
}
    2028:	4800      	ldr	r0, [pc, #0]	; (202c <flash_nrf_get_parameters+0x4>)
    202a:	4770      	bx	lr
    202c:	00006c30 	.word	0x00006c30

00002030 <nrf_flash_init>:
	.page_layout = flash_nrf_pages_layout,
#endif
};

static int nrf_flash_init(const struct device *dev)
{
    2030:	b510      	push	{r4, lr}
#ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
	nrf_flash_sync_init();
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

#if defined(CONFIG_FLASH_PAGE_LAYOUT)
	dev_layout.pages_count = nrfx_nvmc_flash_page_count_get();
    2032:	f004 fb4a 	bl	66ca <nrfx_nvmc_flash_page_count_get>
    2036:	4c03      	ldr	r4, [pc, #12]	; (2044 <nrf_flash_init+0x14>)
    2038:	6020      	str	r0, [r4, #0]
	dev_layout.pages_size = nrfx_nvmc_flash_page_size_get();
    203a:	f004 fb42 	bl	66c2 <nrfx_nvmc_flash_page_size_get>
    203e:	6060      	str	r0, [r4, #4]
#endif

	return 0;
}
    2040:	2000      	movs	r0, #0
    2042:	bd10      	pop	{r4, pc}
    2044:	20001610 	.word	0x20001610

00002048 <restore_pofwarn.part.0>:
    uint32_t pofcon = p_reg->POFCON;
    2048:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    204c:	f8d2 1510 	ldr.w	r1, [r2, #1296]	; 0x510
    uint32_t pofcon = p_reg->POFCON;
    2050:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
        (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
    2054:	f001 011e 	and.w	r1, r1, #30
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    2058:	f023 031f 	bic.w	r3, r3, #31
    205c:	430b      	orrs	r3, r1
    pofcon |=
    205e:	f043 0301 	orr.w	r3, r3, #1
    p_reg->POFCON = pofcon;
    2062:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510

	if (pofcon_enabled) {
		pof_thr = nrf_power_pofcon_get(NRF_POWER, NULL);

		nrf_power_pofcon_set(NRF_POWER, true, pof_thr);
		pofcon_enabled = false;
    2066:	4b02      	ldr	r3, [pc, #8]	; (2070 <restore_pofwarn.part.0+0x28>)
    2068:	2200      	movs	r2, #0
    206a:	701a      	strb	r2, [r3, #0]
	}
}
    206c:	4770      	bx	lr
    206e:	bf00      	nop
    2070:	200017f8 	.word	0x200017f8

00002074 <suspend_pofwarn>:
    #else
        #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2074:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    2078:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    207c:	2b08      	cmp	r3, #8
    207e:	d120      	bne.n	20c2 <suspend_pofwarn+0x4e>
    uint32_t pofcon = p_reg->POFCON;
    2080:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2084:	f8d2 1510 	ldr.w	r1, [r2, #1296]	; 0x510
	if (enabled) {
    2088:	07cb      	lsls	r3, r1, #31
    208a:	d51a      	bpl.n	20c2 <suspend_pofwarn+0x4e>
    uint32_t pofcon = p_reg->POFCON;
    208c:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
        (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
    2090:	f001 011e 	and.w	r1, r1, #30
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    2094:	f023 031f 	bic.w	r3, r3, #31
    pofcon |=
    2098:	430b      	orrs	r3, r1
    p_reg->POFCON = pofcon;
    209a:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    209e:	f8d2 3108 	ldr.w	r3, [r2, #264]	; 0x108
		if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_POFWARN)) {
    20a2:	b15b      	cbz	r3, 20bc <suspend_pofwarn+0x48>
    uint32_t pofcon = p_reg->POFCON;
    20a4:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    20a8:	f023 031f 	bic.w	r3, r3, #31
    20ac:	430b      	orrs	r3, r1
    pofcon |=
    20ae:	f043 0301 	orr.w	r3, r3, #1
    p_reg->POFCON = pofcon;
    20b2:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			return -ECANCELED;
    20b6:	f06f 008b 	mvn.w	r0, #139	; 0x8b
}
    20ba:	4770      	bx	lr
		pofcon_enabled = enabled;
    20bc:	4b02      	ldr	r3, [pc, #8]	; (20c8 <suspend_pofwarn+0x54>)
    20be:	2201      	movs	r2, #1
    20c0:	701a      	strb	r2, [r3, #0]
		return 0;
    20c2:	2000      	movs	r0, #0
}
    20c4:	4770      	bx	lr
    20c6:	bf00      	nop
    20c8:	200017f8 	.word	0x200017f8

000020cc <flash_nrf_erase>:
{
    20cc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    20d0:	460d      	mov	r5, r1
    20d2:	4616      	mov	r6, r2
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    20d4:	f004 faf5 	bl	66c2 <nrfx_nvmc_flash_page_size_get>
	if (is_regular_addr_valid(addr, size)) {
    20d8:	4631      	mov	r1, r6
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    20da:	4607      	mov	r7, r0
	if (is_regular_addr_valid(addr, size)) {
    20dc:	4628      	mov	r0, r5
    20de:	f004 f8ab 	bl	6238 <is_regular_addr_valid>
    20e2:	b328      	cbz	r0, 2130 <flash_nrf_erase+0x64>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    20e4:	fbb5 f3f7 	udiv	r3, r5, r7
    20e8:	fb07 5313 	mls	r3, r7, r3, r5
    20ec:	bb03      	cbnz	r3, 2130 <flash_nrf_erase+0x64>
    20ee:	fbb6 f4f7 	udiv	r4, r6, r7
    20f2:	fb07 6414 	mls	r4, r7, r4, r6
    20f6:	b9dc      	cbnz	r4, 2130 <flash_nrf_erase+0x64>
		if (!n_pages) {
    20f8:	42b7      	cmp	r7, r6
    20fa:	d813      	bhi.n	2124 <flash_nrf_erase+0x58>
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    20fc:	f004 fae1 	bl	66c2 <nrfx_nvmc_flash_page_size_get>
	if (pofcon_enabled) {
    2100:	f8df 8034 	ldr.w	r8, [pc, #52]	; 2138 <flash_nrf_erase+0x6c>
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2104:	4607      	mov	r7, r0
		if (SUSPEND_POFWARN()) {
    2106:	f7ff ffb5 	bl	2074 <suspend_pofwarn>
    210a:	4604      	mov	r4, r0
    210c:	b968      	cbnz	r0, 212a <flash_nrf_erase+0x5e>
		(void)nrfx_nvmc_page_erase(e_ctx->flash_addr);
    210e:	4628      	mov	r0, r5
    2110:	f001 f97c 	bl	340c <nrfx_nvmc_page_erase>
	if (pofcon_enabled) {
    2114:	f898 3000 	ldrb.w	r3, [r8]
    2118:	b10b      	cbz	r3, 211e <flash_nrf_erase+0x52>
    211a:	f7ff ff95 	bl	2048 <restore_pofwarn.part.0>
	} while (e_ctx->len > 0);
    211e:	1bf6      	subs	r6, r6, r7
    2120:	443d      	add	r5, r7
    2122:	d1f0      	bne.n	2106 <flash_nrf_erase+0x3a>
}
    2124:	4620      	mov	r0, r4
    2126:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			return -ECANCELED;
    212a:	f06f 048b 	mvn.w	r4, #139	; 0x8b
	return ret;
    212e:	e7f9      	b.n	2124 <flash_nrf_erase+0x58>
			return -EINVAL;
    2130:	f06f 0415 	mvn.w	r4, #21
    2134:	e7f6      	b.n	2124 <flash_nrf_erase+0x58>
    2136:	bf00      	nop
    2138:	200017f8 	.word	0x200017f8

0000213c <flash_nrf_write>:
{
    213c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    2140:	460e      	mov	r6, r1
	if (is_regular_addr_valid(addr, len)) {
    2142:	4630      	mov	r0, r6
    2144:	4619      	mov	r1, r3
{
    2146:	4617      	mov	r7, r2
    2148:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    214a:	f004 f875 	bl	6238 <is_regular_addr_valid>
    214e:	b330      	cbz	r0, 219e <flash_nrf_write+0x62>
	if (!is_aligned_32(addr) || (len % sizeof(uint32_t))) {
    2150:	ea46 0504 	orr.w	r5, r6, r4
    2154:	f015 0503 	ands.w	r5, r5, #3
    2158:	d121      	bne.n	219e <flash_nrf_write+0x62>
	if (!len) {
    215a:	b31c      	cbz	r4, 21a4 <flash_nrf_write+0x68>
	if (pofcon_enabled) {
    215c:	f8df 904c 	ldr.w	r9, [pc, #76]	; 21ac <flash_nrf_write+0x70>
	while (w_ctx->len >= sizeof(uint32_t)) {
    2160:	1963      	adds	r3, r4, r5
    2162:	2b03      	cmp	r3, #3
    2164:	eba6 0805 	sub.w	r8, r6, r5
    2168:	d807      	bhi.n	217a <flash_nrf_write+0x3e>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
{
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    216a:	4a0f      	ldr	r2, [pc, #60]	; (21a8 <flash_nrf_write+0x6c>)
    216c:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
	while (!nrfx_nvmc_write_done_check()) {
    2170:	07db      	lsls	r3, r3, #31
    2172:	d5fb      	bpl.n	216c <flash_nrf_write+0x30>
	return FLASH_OP_DONE;
    2174:	2000      	movs	r0, #0
}
    2176:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		if (SUSPEND_POFWARN()) {
    217a:	f7ff ff7b 	bl	2074 <suspend_pofwarn>
    217e:	b958      	cbnz	r0, 2198 <flash_nrf_write+0x5c>
				     UNALIGNED_GET((uint32_t *)w_ctx->data_addr));
    2180:	1b7b      	subs	r3, r7, r5
		nrfx_nvmc_word_write(w_ctx->flash_addr,
    2182:	4640      	mov	r0, r8
    2184:	6819      	ldr	r1, [r3, #0]
    2186:	f001 f961 	bl	344c <nrfx_nvmc_word_write>
	if (pofcon_enabled) {
    218a:	f899 3000 	ldrb.w	r3, [r9]
    218e:	b10b      	cbz	r3, 2194 <flash_nrf_write+0x58>
    2190:	f7ff ff5a 	bl	2048 <restore_pofwarn.part.0>
	w_ctx->len -= shift;
    2194:	3d04      	subs	r5, #4
}
    2196:	e7e3      	b.n	2160 <flash_nrf_write+0x24>
			return -ECANCELED;
    2198:	f06f 008b 	mvn.w	r0, #139	; 0x8b
	return ret;
    219c:	e7eb      	b.n	2176 <flash_nrf_write+0x3a>
		return -EINVAL;
    219e:	f06f 0015 	mvn.w	r0, #21
    21a2:	e7e8      	b.n	2176 <flash_nrf_write+0x3a>
		return 0;
    21a4:	4620      	mov	r0, r4
    21a6:	e7e6      	b.n	2176 <flash_nrf_write+0x3a>
    21a8:	4001e000 	.word	0x4001e000
    21ac:	200017f8 	.word	0x200017f8

000021b0 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    21b0:	b570      	push	{r4, r5, r6, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    21b2:	2301      	movs	r3, #1
    21b4:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    21b6:	4a0e      	ldr	r2, [pc, #56]	; (21f0 <compare_int_lock+0x40>)
    21b8:	f3bf 8f5b 	dmb	ish
    21bc:	43dc      	mvns	r4, r3
    21be:	e852 1f00 	ldrex	r1, [r2]
    21c2:	ea01 0504 	and.w	r5, r1, r4
    21c6:	e842 5600 	strex	r6, r5, [r2]
    21ca:	2e00      	cmp	r6, #0
    21cc:	d1f7      	bne.n	21be <compare_int_lock+0xe>
    21ce:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    21d2:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    21d6:	4082      	lsls	r2, r0
    21d8:	4806      	ldr	r0, [pc, #24]	; (21f4 <compare_int_lock+0x44>)
    21da:	f8c0 2308 	str.w	r2, [r0, #776]	; 0x308
    21de:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    21e2:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    21e6:	420b      	tst	r3, r1
}
    21e8:	bf14      	ite	ne
    21ea:	2001      	movne	r0, #1
    21ec:	2000      	moveq	r0, #0
    21ee:	bd70      	pop	{r4, r5, r6, pc}
    21f0:	2000161c 	.word	0x2000161c
    21f4:	40011000 	.word	0x40011000

000021f8 <compare_int_unlock>:
	return compare_int_lock(chan);
}

static void compare_int_unlock(int32_t chan, bool key)
{
	if (key) {
    21f8:	b311      	cbz	r1, 2240 <compare_int_unlock+0x48>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    21fa:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    21fe:	2301      	movs	r3, #1
    2200:	4a10      	ldr	r2, [pc, #64]	; (2244 <compare_int_unlock+0x4c>)
    2202:	4083      	lsls	r3, r0
    2204:	e852 cf00 	ldrex	ip, [r2]
    2208:	ea4c 0c03 	orr.w	ip, ip, r3
    220c:	e842 c100 	strex	r1, ip, [r2]
    2210:	2900      	cmp	r1, #0
    2212:	d1f7      	bne.n	2204 <compare_int_unlock+0xc>
    2214:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    2218:	4a0b      	ldr	r2, [pc, #44]	; (2248 <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    221a:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    221e:	4083      	lsls	r3, r0
    2220:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    2224:	4b09      	ldr	r3, [pc, #36]	; (224c <compare_int_unlock+0x54>)
    2226:	f3bf 8f5b 	dmb	ish
    222a:	681b      	ldr	r3, [r3, #0]
    222c:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    2230:	40c3      	lsrs	r3, r0
    2232:	07db      	lsls	r3, r3, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2234:	bf42      	ittt	mi
    2236:	4b06      	ldrmi	r3, [pc, #24]	; (2250 <compare_int_unlock+0x58>)
    2238:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    223c:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
			NVIC_SetPendingIRQ(RTC_IRQn);
		}
	}
}
    2240:	4770      	bx	lr
    2242:	bf00      	nop
    2244:	2000161c 	.word	0x2000161c
    2248:	40011000 	.word	0x40011000
    224c:	20001618 	.word	0x20001618
    2250:	e000e100 	.word	0xe000e100

00002254 <z_nrf_rtc_timer_read>:
	compare_int_unlock(chan, key);
}

uint64_t z_nrf_rtc_timer_read(void)
{
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    2254:	4b0d      	ldr	r3, [pc, #52]	; (228c <z_nrf_rtc_timer_read+0x38>)
    2256:	6818      	ldr	r0, [r3, #0]
    2258:	0a01      	lsrs	r1, r0, #8
    225a:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    225c:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    2260:	4b0b      	ldr	r3, [pc, #44]	; (2290 <z_nrf_rtc_timer_read+0x3c>)
    2262:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504

	__DMB();

	uint32_t cntr = counter();

	val += cntr;
    2266:	1818      	adds	r0, r3, r0
    2268:	f141 0100 	adc.w	r1, r1, #0

	if (cntr < OVERFLOW_RISK_RANGE_END) {
    226c:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2270:	d20a      	bcs.n	2288 <z_nrf_rtc_timer_read+0x34>
		 * due to possibility that this code preempted overflow interrupt before final write
		 * of `overflow_cnt`. Update of `anchor` occurs far in time from this moment, so
		 * `anchor` is considered valid and stable. Because of this timing there is no risk
		 * of incorrect `anchor` value caused by non-atomic read of 64-bit `anchor`.
		 */
		if (val < anchor) {
    2272:	4b08      	ldr	r3, [pc, #32]	; (2294 <z_nrf_rtc_timer_read+0x40>)
    2274:	e9d3 2300 	ldrd	r2, r3, [r3]
    2278:	4290      	cmp	r0, r2
    227a:	eb71 0303 	sbcs.w	r3, r1, r3
    227e:	d203      	bcs.n	2288 <z_nrf_rtc_timer_read+0x34>
			/* Unhandled overflow, detected, let's add correction */
			val += COUNTER_SPAN;
    2280:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    2284:	f141 0100 	adc.w	r1, r1, #0
		 * check validity using `anchor`
		 */
	}

	return val;
}
    2288:	4770      	bx	lr
    228a:	bf00      	nop
    228c:	20001620 	.word	0x20001620
    2290:	40011000 	.word	0x40011000
    2294:	20000118 	.word	0x20000118

00002298 <compare_set>:
{
    2298:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    229c:	4614      	mov	r4, r2
    229e:	461d      	mov	r5, r3
    22a0:	4607      	mov	r7, r0
	key = compare_int_lock(chan);
    22a2:	f7ff ff85 	bl	21b0 <compare_int_lock>
    22a6:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    22a8:	f7ff ffd4 	bl	2254 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    22ac:	42a0      	cmp	r0, r4
    22ae:	eb71 0305 	sbcs.w	r3, r1, r5
    22b2:	d27a      	bcs.n	23aa <compare_set+0x112>
		if (target_time - curr_time > COUNTER_SPAN) {
    22b4:	4b46      	ldr	r3, [pc, #280]	; (23d0 <compare_set+0x138>)
    22b6:	1a20      	subs	r0, r4, r0
    22b8:	eb65 0101 	sbc.w	r1, r5, r1
    22bc:	4298      	cmp	r0, r3
    22be:	f171 0100 	sbcs.w	r1, r1, #0
    22c2:	f080 8081 	bcs.w	23c8 <compare_set+0x130>
		if (target_time != cc_data[chan].target_time) {
    22c6:	4b43      	ldr	r3, [pc, #268]	; (23d4 <compare_set+0x13c>)
    22c8:	eb03 1307 	add.w	r3, r3, r7, lsl #4
    22cc:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    22d0:	429d      	cmp	r5, r3
    22d2:	bf08      	it	eq
    22d4:	4294      	cmpeq	r4, r2
    22d6:	d053      	beq.n	2380 <compare_set+0xe8>
    22d8:	ea4f 0a87 	mov.w	sl, r7, lsl #2
    22dc:	f10a 4a80 	add.w	sl, sl, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    22e0:	f107 0950 	add.w	r9, r7, #80	; 0x50
    22e4:	f50a 3a88 	add.w	sl, sl, #69632	; 0x11000
    22e8:	ea4f 0989 	mov.w	r9, r9, lsl #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    22ec:	fa1f f989 	uxth.w	r9, r9
	return absolute_time & COUNTER_MAX;
    22f0:	f024 487f 	bic.w	r8, r4, #4278190080	; 0xff000000
    22f4:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    22f8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    return p_reg->CC[ch];
    22fc:	f8da 0540 	ldr.w	r0, [sl, #1344]	; 0x540
     return p_reg->COUNTER;
    2300:	4a35      	ldr	r2, [pc, #212]	; (23d8 <compare_set+0x140>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2302:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
    2306:	40bb      	lsls	r3, r7
	uint32_t cc_val = abs_val & COUNTER_MAX;
    2308:	4646      	mov	r6, r8
     return p_reg->COUNTER;
    230a:	f8d2 b504 	ldr.w	fp, [r2, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    230e:	eba0 000b 	sub.w	r0, r0, fp
    2312:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2316:	f02b 417f 	bic.w	r1, fp, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    231a:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    231c:	f8ca 1540 	str.w	r1, [sl, #1344]	; 0x540
    2320:	d105      	bne.n	232e <compare_set+0x96>
    2322:	9301      	str	r3, [sp, #4]
	z_impl_k_busy_wait(usec_to_wait);
    2324:	2013      	movs	r0, #19
    2326:	f004 fa1e 	bl	6766 <z_impl_k_busy_wait>
    232a:	4a2b      	ldr	r2, [pc, #172]	; (23d8 <compare_set+0x140>)
    232c:	9b01      	ldr	r3, [sp, #4]
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    232e:	f10b 0c02 	add.w	ip, fp, #2
	return (a - b) & COUNTER_MAX;
    2332:	eba6 000c 	sub.w	r0, r6, ip
    2336:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    233a:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    233e:	bf88      	it	hi
    2340:	4666      	movhi	r6, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2342:	2000      	movs	r0, #0
    2344:	f8c9 0000 	str.w	r0, [r9]
    2348:	f8d9 0000 	ldr.w	r0, [r9]
    p_reg->EVTENSET = mask;
    234c:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2350:	f026 407f 	bic.w	r0, r6, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    2354:	f8ca 0540 	str.w	r0, [sl, #1344]	; 0x540
     return p_reg->COUNTER;
    2358:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	} while ((now2 != now) &&
    235c:	4583      	cmp	fp, r0
    235e:	d006      	beq.n	236e <compare_set+0xd6>
	return (a - b) & COUNTER_MAX;
    2360:	1a30      	subs	r0, r6, r0
    2362:	3802      	subs	r0, #2
    2364:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    2368:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    236c:	d81b      	bhi.n	23a6 <compare_set+0x10e>
	return (a - b) & COUNTER_MAX;
    236e:	eba6 0608 	sub.w	r6, r6, r8
    2372:	f026 467f 	bic.w	r6, r6, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    2376:	1936      	adds	r6, r6, r4
    2378:	f145 0300 	adc.w	r3, r5, #0
    237c:	4634      	mov	r4, r6
    237e:	461d      	mov	r5, r3
	cc_data[chan].target_time = target_time;
    2380:	4914      	ldr	r1, [pc, #80]	; (23d4 <compare_set+0x13c>)
	cc_data[chan].callback = handler;
    2382:	980c      	ldr	r0, [sp, #48]	; 0x30
	cc_data[chan].target_time = target_time;
    2384:	013b      	lsls	r3, r7, #4
    2386:	eb01 1207 	add.w	r2, r1, r7, lsl #4
	cc_data[chan].callback = handler;
    238a:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    238c:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    238e:	6053      	str	r3, [r2, #4]
	cc_data[chan].target_time = target_time;
    2390:	e9c2 4502 	strd	r4, r5, [r2, #8]
	return ret;
    2394:	2400      	movs	r4, #0
	compare_int_unlock(chan, key);
    2396:	4638      	mov	r0, r7
    2398:	9900      	ldr	r1, [sp, #0]
    239a:	f7ff ff2d 	bl	21f8 <compare_int_unlock>
}
    239e:	4620      	mov	r0, r4
    23a0:	b003      	add	sp, #12
    23a2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    23a6:	4630      	mov	r0, r6
    23a8:	e7af      	b.n	230a <compare_set+0x72>
		atomic_or(&force_isr_mask, BIT(chan));
    23aa:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    23ac:	4a0b      	ldr	r2, [pc, #44]	; (23dc <compare_set+0x144>)
    23ae:	f3bf 8f5b 	dmb	ish
    23b2:	40bb      	lsls	r3, r7
    23b4:	e852 0f00 	ldrex	r0, [r2]
    23b8:	4318      	orrs	r0, r3
    23ba:	e842 0100 	strex	r1, r0, [r2]
    23be:	2900      	cmp	r1, #0
    23c0:	d1f8      	bne.n	23b4 <compare_set+0x11c>
    23c2:	f3bf 8f5b 	dmb	ish
    23c6:	e7db      	b.n	2380 <compare_set+0xe8>
			return -EINVAL;
    23c8:	f06f 0415 	mvn.w	r4, #21
    23cc:	e7e3      	b.n	2396 <compare_set+0xfe>
    23ce:	bf00      	nop
    23d0:	01000001 	.word	0x01000001
    23d4:	20000100 	.word	0x20000100
    23d8:	40011000 	.word	0x40011000
    23dc:	20001618 	.word	0x20001618

000023e0 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    23e0:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    23e2:	4b1a      	ldr	r3, [pc, #104]	; (244c <sys_clock_driver_init+0x6c>)
    p_reg->PRESCALER = val;
    23e4:	4d1a      	ldr	r5, [pc, #104]	; (2450 <sys_clock_driver_init+0x70>)
    23e6:	2400      	movs	r4, #0
    23e8:	f04f 30ff 	mov.w	r0, #4294967295
    23ec:	f04f 31ff 	mov.w	r1, #4294967295
    23f0:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    23f4:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    23f8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    23fc:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2400:	4b14      	ldr	r3, [pc, #80]	; (2454 <sys_clock_driver_init+0x74>)
    2402:	2602      	movs	r6, #2
    2404:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    2408:	2101      	movs	r1, #1
    240a:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    240e:	2011      	movs	r0, #17
    2410:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    2414:	4622      	mov	r2, r4
    2416:	f7fe fe0d 	bl	1034 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    241a:	2011      	movs	r0, #17
    241c:	f7fe fdda 	bl	fd4 <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    2420:	4a0d      	ldr	r2, [pc, #52]	; (2458 <sys_clock_driver_init+0x78>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    2422:	2301      	movs	r3, #1
    2424:	60ab      	str	r3, [r5, #8]
    2426:	602b      	str	r3, [r5, #0]
    2428:	6013      	str	r3, [r2, #0]
     return p_reg->COUNTER;
    242a:	f8d5 2504 	ldr.w	r2, [r5, #1284]	; 0x504

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    242e:	4b0b      	ldr	r3, [pc, #44]	; (245c <sys_clock_driver_init+0x7c>)
    2430:	9300      	str	r3, [sp, #0]
    2432:	f502 7280 	add.w	r2, r2, #256	; 0x100
    2436:	4623      	mov	r3, r4
    2438:	9401      	str	r4, [sp, #4]
    243a:	4620      	mov	r0, r4
    243c:	f7ff ff2c 	bl	2298 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    2440:	4630      	mov	r0, r6
    2442:	f7ff f9c1 	bl	17c8 <z_nrf_clock_control_lf_on>

	return 0;
}
    2446:	4620      	mov	r0, r4
    2448:	b002      	add	sp, #8
    244a:	bd70      	pop	{r4, r5, r6, pc}
    244c:	20000100 	.word	0x20000100
    2450:	40011000 	.word	0x40011000
    2454:	e000e100 	.word	0xe000e100
    2458:	2000161c 	.word	0x2000161c
    245c:	00002461 	.word	0x00002461

00002460 <sys_clock_timeout_handler>:
{
    2460:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    2464:	4605      	mov	r5, r0
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2466:	4829      	ldr	r0, [pc, #164]	; (250c <sys_clock_timeout_handler+0xac>)
    2468:	e9d0 1c00 	ldrd	r1, ip, [r0]
    246c:	1a54      	subs	r4, r2, r1
	return absolute_time & COUNTER_MAX;
    246e:	f022 467f 	bic.w	r6, r2, #4278190080	; 0xff000000
	last_count += dticks * CYC_PER_TICK;
    2472:	f024 02ff 	bic.w	r2, r4, #255	; 0xff
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2476:	eb63 070c 	sbc.w	r7, r3, ip
	last_count += dticks * CYC_PER_TICK;
    247a:	1851      	adds	r1, r2, r1
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    247c:	f5a6 1200 	sub.w	r2, r6, #2097152	; 0x200000
	last_count += dticks * CYC_PER_TICK;
    2480:	eb4c 0307 	adc.w	r3, ip, r7
	if (in_anchor_range(cc_value)) {
    2484:	f5b2 0f40 	cmp.w	r2, #12582912	; 0xc00000
	last_count += dticks * CYC_PER_TICK;
    2488:	e9c0 1300 	strd	r1, r3, [r0]
	if (in_anchor_range(cc_value)) {
    248c:	d23a      	bcs.n	2504 <sys_clock_timeout_handler+0xa4>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    248e:	4a20      	ldr	r2, [pc, #128]	; (2510 <sys_clock_timeout_handler+0xb0>)
    2490:	6812      	ldr	r2, [r2, #0]
    2492:	0a10      	lsrs	r0, r2, #8
    2494:	0612      	lsls	r2, r2, #24
    2496:	eb12 0806 	adds.w	r8, r2, r6
    249a:	4a1e      	ldr	r2, [pc, #120]	; (2514 <sys_clock_timeout_handler+0xb4>)
    249c:	f140 0900 	adc.w	r9, r0, #0
    24a0:	e9c2 8900 	strd	r8, r9, [r2]
		return true;
    24a4:	f04f 0801 	mov.w	r8, #1
		compare_set(chan, last_count + CYC_PER_TICK,
    24a8:	f511 7280 	adds.w	r2, r1, #256	; 0x100
    24ac:	f04f 0100 	mov.w	r1, #0
    24b0:	9101      	str	r1, [sp, #4]
    24b2:	4919      	ldr	r1, [pc, #100]	; (2518 <sys_clock_timeout_handler+0xb8>)
    24b4:	9100      	str	r1, [sp, #0]
    24b6:	f143 0300 	adc.w	r3, r3, #0
    24ba:	4628      	mov	r0, r5
    24bc:	f7ff feec 	bl	2298 <compare_set>
	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    24c0:	f5b4 7f80 	cmp.w	r4, #256	; 0x100
    24c4:	f177 0700 	sbcs.w	r7, r7, #0
    24c8:	bf2c      	ite	cs
    24ca:	2001      	movcs	r0, #1
    24cc:	2000      	movcc	r0, #0
    24ce:	f001 fb9f 	bl	3c10 <sys_clock_announce>
    return p_reg->CC[ch];
    24d2:	00ab      	lsls	r3, r5, #2
    24d4:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    24d8:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    24dc:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
	if (cc_value == get_comparator(chan)) {
    24e0:	4296      	cmp	r6, r2
    24e2:	d10c      	bne.n	24fe <sys_clock_timeout_handler+0x9e>
		if (!anchor_updated) {
    24e4:	f1b8 0f00 	cmp.w	r8, #0
    24e8:	d103      	bne.n	24f2 <sys_clock_timeout_handler+0x92>
    p_reg->CC[ch] = cc_val;
    24ea:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    24ee:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    p_reg->EVTENSET = mask;
    24f2:	4a0a      	ldr	r2, [pc, #40]	; (251c <sys_clock_timeout_handler+0xbc>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    24f4:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    24f8:	40ab      	lsls	r3, r5
    24fa:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
}
    24fe:	b003      	add	sp, #12
    2500:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	return false;
    2504:	f04f 0800 	mov.w	r8, #0
    2508:	e7ce      	b.n	24a8 <sys_clock_timeout_handler+0x48>
    250a:	bf00      	nop
    250c:	20000110 	.word	0x20000110
    2510:	20001620 	.word	0x20001620
    2514:	20000118 	.word	0x20000118
    2518:	00002461 	.word	0x00002461
    251c:	40011000 	.word	0x40011000

00002520 <rtc_nrf_isr>:
{
    2520:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    2524:	4c33      	ldr	r4, [pc, #204]	; (25f4 <rtc_nrf_isr+0xd4>)
    2526:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    252a:	079a      	lsls	r2, r3, #30
    252c:	d50b      	bpl.n	2546 <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    252e:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    2532:	b143      	cbz	r3, 2546 <rtc_nrf_isr+0x26>
		overflow_cnt++;
    2534:	4a30      	ldr	r2, [pc, #192]	; (25f8 <rtc_nrf_isr+0xd8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2536:	2300      	movs	r3, #0
    2538:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    253c:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    2540:	6813      	ldr	r3, [r2, #0]
    2542:	3301      	adds	r3, #1
    2544:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    2546:	f04f 0320 	mov.w	r3, #32
    254a:	f3ef 8211 	mrs	r2, BASEPRI
    254e:	f383 8812 	msr	BASEPRI_MAX, r3
    2552:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    2556:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    255a:	03db      	lsls	r3, r3, #15
    255c:	d529      	bpl.n	25b2 <rtc_nrf_isr+0x92>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    255e:	f3bf 8f5b 	dmb	ish
    2562:	4b26      	ldr	r3, [pc, #152]	; (25fc <rtc_nrf_isr+0xdc>)
    2564:	e853 1f00 	ldrex	r1, [r3]
    2568:	f021 0001 	bic.w	r0, r1, #1
    256c:	e843 0500 	strex	r5, r0, [r3]
    2570:	2d00      	cmp	r5, #0
    2572:	d1f7      	bne.n	2564 <rtc_nrf_isr+0x44>
    2574:	f3bf 8f5b 	dmb	ish
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    2578:	b911      	cbnz	r1, 2580 <rtc_nrf_isr+0x60>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    257a:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
    257e:	b1c3      	cbz	r3, 25b2 <rtc_nrf_isr+0x92>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2580:	2500      	movs	r5, #0
    2582:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    2586:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
	__asm__ volatile(
    258a:	f382 8811 	msr	BASEPRI, r2
    258e:	f3bf 8f6f 	isb	sy
		curr_time = z_nrf_rtc_timer_read();
    2592:	f7ff fe5f 	bl	2254 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    2596:	f04f 0320 	mov.w	r3, #32
    259a:	f3ef 8211 	mrs	r2, BASEPRI
    259e:	f383 8812 	msr	BASEPRI_MAX, r3
    25a2:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    25a6:	4b16      	ldr	r3, [pc, #88]	; (2600 <rtc_nrf_isr+0xe0>)
    25a8:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    25ac:	42b0      	cmp	r0, r6
    25ae:	41b9      	sbcs	r1, r7
    25b0:	d206      	bcs.n	25c0 <rtc_nrf_isr+0xa0>
	__asm__ volatile(
    25b2:	f382 8811 	msr	BASEPRI, r2
    25b6:	f3bf 8f6f 	isb	sy
}
    25ba:	b003      	add	sp, #12
    25bc:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    25c0:	f04f 38ff 	mov.w	r8, #4294967295
    25c4:	f04f 39ff 	mov.w	r9, #4294967295
			user_context = cc_data[chan].user_context;
    25c8:	e9d3 1000 	ldrd	r1, r0, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    25cc:	e9c3 8902 	strd	r8, r9, [r3, #8]
			cc_data[chan].callback = NULL;
    25d0:	601d      	str	r5, [r3, #0]
    p_reg->EVTENCLR = mask;
    25d2:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    25d6:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
    25da:	f382 8811 	msr	BASEPRI, r2
    25de:	f3bf 8f6f 	isb	sy
		if (handler) {
    25e2:	2900      	cmp	r1, #0
    25e4:	d0e9      	beq.n	25ba <rtc_nrf_isr+0x9a>
			handler(chan, expire_time, user_context);
    25e6:	9000      	str	r0, [sp, #0]
    25e8:	4632      	mov	r2, r6
    25ea:	463b      	mov	r3, r7
    25ec:	4628      	mov	r0, r5
    25ee:	4788      	blx	r1
}
    25f0:	e7e3      	b.n	25ba <rtc_nrf_isr+0x9a>
    25f2:	bf00      	nop
    25f4:	40011000 	.word	0x40011000
    25f8:	20001620 	.word	0x20001620
    25fc:	20001618 	.word	0x20001618
    2600:	20000100 	.word	0x20000100

00002604 <pinctrl_configure_pins>:
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    2604:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
        case 1: return NRF_P1;
    2608:	4e5a      	ldr	r6, [pc, #360]	; (2774 <pinctrl_configure_pins+0x170>)
    260a:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    260e:	2701      	movs	r7, #1
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    2610:	4281      	cmp	r1, r0
    2612:	d102      	bne.n	261a <pinctrl_configure_pins+0x16>
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
				     drive, NRF_GPIO_PIN_NOSENSE);
		}
	}

	return 0;
    2614:	2000      	movs	r0, #0
}
    2616:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    261a:	6804      	ldr	r4, [r0, #0]
		uint32_t pin = NRF_GET_PIN(pins[i]);
    261c:	f004 037f 	and.w	r3, r4, #127	; 0x7f
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    2620:	f3c4 2543 	ubfx	r5, r4, #9, #4
			pin = 0xFFFFFFFFU;
    2624:	2b7f      	cmp	r3, #127	; 0x7f
		switch (NRF_GET_FUN(pins[i])) {
    2626:	ea4f 4414 	mov.w	r4, r4, lsr #16
			pin = 0xFFFFFFFFU;
    262a:	bf08      	it	eq
    262c:	f04f 33ff 	moveq.w	r3, #4294967295
		switch (NRF_GET_FUN(pins[i])) {
    2630:	2c22      	cmp	r4, #34	; 0x22
    2632:	f200 809b 	bhi.w	276c <pinctrl_configure_pins+0x168>
    2636:	e8df f004 	tbb	[pc, r4]
    263a:	2412      	.short	0x2412
    263c:	402c4429 	.word	0x402c4429
    2640:	99999944 	.word	0x99999944
    2644:	99704799 	.word	0x99704799
    2648:	99999999 	.word	0x99999999
    264c:	99999999 	.word	0x99999999
    2650:	817e7b73 	.word	0x817e7b73
    2654:	84999999 	.word	0x84999999
    2658:	93908d8a 	.word	0x93908d8a
    265c:	96          	.byte	0x96
    265d:	00          	.byte	0x00
			NRF_PSEL_UART(reg, TXD) = pin;
    265e:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    return pin_number >> 5;
    2662:	ea4f 1c53 	mov.w	ip, r3, lsr #5
        case 1: return NRF_P1;
    2666:	f1bc 0f01 	cmp.w	ip, #1
    *p_pin = pin_number & 0x1F;
    266a:	f003 041f 	and.w	r4, r3, #31
        case 1: return NRF_P1;
    266e:	bf14      	ite	ne
    2670:	f04f 4ca0 	movne.w	ip, #1342177280	; 0x50000000
    2674:	46b4      	moveq	ip, r6
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2676:	fa07 f404 	lsl.w	r4, r7, r4
    p_reg->OUTSET = set_mask;
    267a:	f8cc 4508 	str.w	r4, [ip, #1288]	; 0x508
    267e:	2401      	movs	r4, #1
    2680:	e002      	b.n	2688 <pinctrl_configure_pins+0x84>
			NRF_PSEL_UART(reg, RXD) = pin;
    2682:	f8c2 3514 	str.w	r3, [r2, #1300]	; 0x514
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    2686:	2400      	movs	r4, #0
    2688:	46a6      	mov	lr, r4
    268a:	e024      	b.n	26d6 <pinctrl_configure_pins+0xd2>
			NRF_PSEL_UART(reg, RTS) = pin;
    268c:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (write != NO_WRITE) {
    2690:	e7e7      	b.n	2662 <pinctrl_configure_pins+0x5e>
			NRF_PSEL_SPIM(reg, SCK) = pin;
    2692:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    2696:	2400      	movs	r4, #0
    return pin_number >> 5;
    2698:	ea4f 1e53 	mov.w	lr, r3, lsr #5
        case 1: return NRF_P1;
    269c:	f1be 0f01 	cmp.w	lr, #1
    26a0:	bf14      	ite	ne
    26a2:	f04f 4ea0 	movne.w	lr, #1342177280	; 0x50000000
    26a6:	46b6      	moveq	lr, r6
    *p_pin = pin_number & 0x1F;
    26a8:	f003 0c1f 	and.w	ip, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    26ac:	fa07 fc0c 	lsl.w	ip, r7, ip
    p_reg->OUTCLR = clr_mask;
    26b0:	f8ce c50c 	str.w	ip, [lr, #1292]	; 0x50c
    26b4:	f04f 0e01 	mov.w	lr, #1
    26b8:	e00d      	b.n	26d6 <pinctrl_configure_pins+0xd2>
			NRF_PSEL_SPIM(reg, MOSI) = pin;
    26ba:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			pin = 0xFFFFFFFFU;
    26be:	2401      	movs	r4, #1
    26c0:	e7ea      	b.n	2698 <pinctrl_configure_pins+0x94>
			NRF_PSEL_SPIM(reg, MISO) = pin;
    26c2:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			if (write != NO_WRITE) {
    26c6:	e7de      	b.n	2686 <pinctrl_configure_pins+0x82>
			NRF_PSEL_TWIM(reg, SCL) = pin;
    26c8:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (drive == NRF_DRIVE_S0S1) {
    26cc:	2d00      	cmp	r5, #0
    26ce:	d1da      	bne.n	2686 <pinctrl_configure_pins+0x82>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    26d0:	2400      	movs	r4, #0
			dir = NRF_GPIO_PIN_DIR_INPUT;
    26d2:	46a6      	mov	lr, r4
				drive = NRF_DRIVE_S0D1;
    26d4:	2506      	movs	r5, #6
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    26d6:	f850 cb04 	ldr.w	ip, [r0], #4
    26da:	f40c 5800 	and.w	r8, ip, #8192	; 0x2000
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    26de:	f1b8 0f00 	cmp.w	r8, #0
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    26e2:	ea4f 2505 	mov.w	r5, r5, lsl #8
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
    26e6:	f3cc 18c1 	ubfx	r8, ip, #7, #2
    *p_pin = pin_number & 0x1F;
    26ea:	f003 0c1f 	and.w	ip, r3, #31
    return pin_number >> 5;
    26ee:	ea4f 1353 	mov.w	r3, r3, lsr #5
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    26f2:	bf1c      	itt	ne
    26f4:	2401      	movne	r4, #1
    26f6:	f04f 0e00 	movne.w	lr, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    26fa:	ea45 0588 	orr.w	r5, r5, r8, lsl #2
        case 0: return NRF_P0;
    26fe:	2b01      	cmp	r3, #1
    2700:	bf0c      	ite	eq
    2702:	4633      	moveq	r3, r6
    2704:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2708:	ea45 050e 	orr.w	r5, r5, lr
    reg->PIN_CNF[pin_number] = cnf;
    270c:	f50c 7ce0 	add.w	ip, ip, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2710:	ea45 0544 	orr.w	r5, r5, r4, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    2714:	f843 502c 	str.w	r5, [r3, ip, lsl #2]
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    2718:	e77a      	b.n	2610 <pinctrl_configure_pins+0xc>
			NRF_PSEL_TWIM(reg, SDA) = pin;
    271a:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			if (drive == NRF_DRIVE_S0S1) {
    271e:	e7d5      	b.n	26cc <pinctrl_configure_pins+0xc8>
			NRF_PSEL_PWM(reg, OUT[0]) = pin;
    2720:	f8c2 3560 	str.w	r3, [r2, #1376]	; 0x560
			write = NRF_GET_INVERT(pins[i]);
    2724:	6804      	ldr	r4, [r0, #0]
    2726:	f3c4 3480 	ubfx	r4, r4, #14, #1
    if (value == 0)
    272a:	2c00      	cmp	r4, #0
    272c:	d0c7      	beq.n	26be <pinctrl_configure_pins+0xba>
    272e:	e798      	b.n	2662 <pinctrl_configure_pins+0x5e>
			NRF_PSEL_PWM(reg, OUT[1]) = pin;
    2730:	f8c2 3564 	str.w	r3, [r2, #1380]	; 0x564
			write = NRF_GET_INVERT(pins[i]);
    2734:	e7f6      	b.n	2724 <pinctrl_configure_pins+0x120>
			NRF_PSEL_PWM(reg, OUT[2]) = pin;
    2736:	f8c2 3568 	str.w	r3, [r2, #1384]	; 0x568
			write = NRF_GET_INVERT(pins[i]);
    273a:	e7f3      	b.n	2724 <pinctrl_configure_pins+0x120>
			NRF_PSEL_PWM(reg, OUT[3]) = pin;
    273c:	f8c2 356c 	str.w	r3, [r2, #1388]	; 0x56c
    2740:	e7f0      	b.n	2724 <pinctrl_configure_pins+0x120>
			NRF_PSEL_QSPI(reg, SCK) = pin;
    2742:	f8c2 3524 	str.w	r3, [r2, #1316]	; 0x524
			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    2746:	2401      	movs	r4, #1
			dir = NRF_GPIO_PIN_DIR_INPUT;
    2748:	f04f 0e00 	mov.w	lr, #0
    274c:	e7c3      	b.n	26d6 <pinctrl_configure_pins+0xd2>
			NRF_PSEL_QSPI(reg, CSN) = pin;
    274e:	f8c2 3528 	str.w	r3, [r2, #1320]	; 0x528
    2752:	e786      	b.n	2662 <pinctrl_configure_pins+0x5e>
			NRF_PSEL_QSPI(reg, IO0) = pin;
    2754:	f8c2 3530 	str.w	r3, [r2, #1328]	; 0x530
			if (write != NO_WRITE) {
    2758:	e7f5      	b.n	2746 <pinctrl_configure_pins+0x142>
			NRF_PSEL_QSPI(reg, IO1) = pin;
    275a:	f8c2 3534 	str.w	r3, [r2, #1332]	; 0x534
    275e:	e7f2      	b.n	2746 <pinctrl_configure_pins+0x142>
			NRF_PSEL_QSPI(reg, IO2) = pin;
    2760:	f8c2 3538 	str.w	r3, [r2, #1336]	; 0x538
			if (write != NO_WRITE) {
    2764:	e7ef      	b.n	2746 <pinctrl_configure_pins+0x142>
			NRF_PSEL_QSPI(reg, IO3) = pin;
    2766:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
			if (write != NO_WRITE) {
    276a:	e7ec      	b.n	2746 <pinctrl_configure_pins+0x142>
		switch (NRF_GET_FUN(pins[i])) {
    276c:	f06f 0085 	mvn.w	r0, #133	; 0x85
    2770:	e751      	b.n	2616 <pinctrl_configure_pins+0x12>
    2772:	bf00      	nop
    2774:	50000300 	.word	0x50000300

00002778 <find_free_region>:
#include <zephyr/sys/__assert.h>
#include <zephyr/kernel.h>

/* Find the first unused ACL region. */
static int find_free_region(uint32_t *region_idx)
{
    2778:	b530      	push	{r4, r5, lr}
    277a:	490c      	ldr	r1, [pc, #48]	; (27ac <find_free_region+0x34>)
}

NRF_STATIC_INLINE nrf_acl_perm_t nrf_acl_region_perm_get(NRF_ACL_Type const * p_reg,
                                                         uint32_t             region_id)
{
    return (nrf_acl_perm_t)p_reg->ACL[region_id].PERM;
    277c:	4d0c      	ldr	r5, [pc, #48]	; (27b0 <find_free_region+0x38>)
    277e:	680b      	ldr	r3, [r1, #0]
    2780:	4602      	mov	r2, r0
	static uint32_t idx;

	while (nrf_acl_region_perm_get(NRF_ACL, idx) != 0) {
    2782:	2400      	movs	r4, #0
    2784:	eb05 1003 	add.w	r0, r5, r3, lsl #4
    2788:	f8d0 0808 	ldr.w	r0, [r0, #2056]	; 0x808
    278c:	b2c0      	uxtb	r0, r0
    278e:	b918      	cbnz	r0, 2798 <find_free_region+0x20>
    2790:	b104      	cbz	r4, 2794 <find_free_region+0x1c>
    2792:	600b      	str	r3, [r1, #0]
			*region_idx = idx;
			return -ENOSPC;
		}
	}
	*region_idx = idx;
	return 0;
    2794:	2000      	movs	r0, #0
    2796:	e007      	b.n	27a8 <find_free_region+0x30>
		idx++;
    2798:	3301      	adds	r3, #1
		if (idx >= ACL_REGIONS_COUNT) {
    279a:	2b07      	cmp	r3, #7
    279c:	f04f 0401 	mov.w	r4, #1
    27a0:	d9f0      	bls.n	2784 <find_free_region+0xc>
    27a2:	600b      	str	r3, [r1, #0]
			return -ENOSPC;
    27a4:	f06f 001b 	mvn.w	r0, #27
			*region_idx = idx;
    27a8:	6013      	str	r3, [r2, #0]
}
    27aa:	bd30      	pop	{r4, r5, pc}
    27ac:	20001624 	.word	0x20001624
    27b0:	4001e000 	.word	0x4001e000

000027b4 <boot_write_magic>:
    return rc;
}

int
boot_write_magic(const struct flash_area *fap)
{
    27b4:	b530      	push	{r4, r5, lr}
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    27b6:	6881      	ldr	r1, [r0, #8]
{
    27b8:	b085      	sub	sp, #20
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    27ba:	3910      	subs	r1, #16
     * returned by boot_magic_off() is the start of magic which is not the
     * start of the flash write boundary and thus writes to the magic will fail.
     * To account for this change, write to magic is first padded with 0xFF
     * before writing to the trailer.
     */
    pad_off = ALIGN_DOWN(off, BOOT_MAX_ALIGN);
    27bc:	f021 0407 	bic.w	r4, r1, #7
{
    27c0:	4605      	mov	r5, r0

    erased_val = flash_area_erased_val(fap);
    27c2:	f003 fb76 	bl	5eb2 <flash_area_erased_val>

    memset(&magic[0], erased_val, sizeof(magic));
    27c6:	2210      	movs	r2, #16
    erased_val = flash_area_erased_val(fap);
    27c8:	4601      	mov	r1, r0
    memset(&magic[0], erased_val, sizeof(magic));
    27ca:	4668      	mov	r0, sp
    27cc:	f003 fbdf 	bl	5f8e <memset>
    memcpy(&magic[BOOT_MAGIC_ALIGN_SIZE - BOOT_MAGIC_SZ], BOOT_IMG_MAGIC, BOOT_MAGIC_SZ);
    27d0:	4907      	ldr	r1, [pc, #28]	; (27f0 <boot_write_magic+0x3c>)
    27d2:	2210      	movs	r2, #16
    27d4:	4668      	mov	r0, sp
    27d6:	f003 fbcf 	bl	5f78 <memcpy>

    BOOT_LOG_DBG("writing magic; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    rc = flash_area_write(fap, pad_off, &magic[0], BOOT_MAGIC_ALIGN_SIZE);
    27da:	2310      	movs	r3, #16
    27dc:	466a      	mov	r2, sp
    27de:	4621      	mov	r1, r4
    27e0:	4628      	mov	r0, r5
    27e2:	f003 fb34 	bl	5e4e <flash_area_write>
    if (rc != 0) {
        return BOOT_EFLASH;
    }

    return 0;
}
    27e6:	3800      	subs	r0, #0
    27e8:	bf18      	it	ne
    27ea:	2001      	movne	r0, #1
    27ec:	b005      	add	sp, #20
    27ee:	bd30      	pop	{r4, r5, pc}
    27f0:	00006dda 	.word	0x00006dda

000027f4 <boot_read_swap_state>:
{
    27f4:	b530      	push	{r4, r5, lr}
    27f6:	460d      	mov	r5, r1
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    27f8:	6881      	ldr	r1, [r0, #8]
{
    27fa:	b087      	sub	sp, #28
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    27fc:	2310      	movs	r3, #16
    27fe:	aa02      	add	r2, sp, #8
    2800:	3910      	subs	r1, #16
{
    2802:	4604      	mov	r4, r0
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    2804:	f003 fb0e 	bl	5e24 <flash_area_read>
    if (rc < 0) {
    2808:	2800      	cmp	r0, #0
    280a:	da02      	bge.n	2812 <CONFIG_MAIN_STACK_SIZE+0x12>
        return BOOT_EFLASH;
    280c:	2001      	movs	r0, #1
}
    280e:	b007      	add	sp, #28
    2810:	bd30      	pop	{r4, r5, pc}
    if (bootutil_buffer_is_erased(fap, magic, BOOT_MAGIC_SZ)) {
    2812:	2210      	movs	r2, #16
    2814:	a902      	add	r1, sp, #8
    2816:	4620      	mov	r0, r4
    2818:	f003 fe10 	bl	643c <bootutil_buffer_is_erased>
    281c:	2800      	cmp	r0, #0
    281e:	d13a      	bne.n	2896 <CONFIG_MAIN_STACK_SIZE+0x96>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
    2820:	491e      	ldr	r1, [pc, #120]	; (289c <CONFIG_MAIN_STACK_SIZE+0x9c>)
    2822:	2210      	movs	r2, #16
    2824:	a802      	add	r0, sp, #8
    2826:	f003 fb80 	bl	5f2a <memcmp>
    return BOOT_MAGIC_BAD;
    282a:	2800      	cmp	r0, #0
        state->magic = boot_magic_decode(magic);
    282c:	bf0c      	ite	eq
    282e:	2301      	moveq	r3, #1
    2830:	2302      	movne	r3, #2
        state->magic = BOOT_MAGIC_UNSET;
    2832:	702b      	strb	r3, [r5, #0]
    off = boot_swap_info_off(fap);
    2834:	4620      	mov	r0, r4
    2836:	f003 fded 	bl	6414 <boot_swap_info_off>
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    283a:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    283c:	4601      	mov	r1, r0
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    283e:	f10d 0207 	add.w	r2, sp, #7
    2842:	4620      	mov	r0, r4
    2844:	f003 faee 	bl	5e24 <flash_area_read>
    if (rc < 0) {
    2848:	2800      	cmp	r0, #0
    284a:	dbdf      	blt.n	280c <CONFIG_MAIN_STACK_SIZE+0xc>
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    284c:	f89d 3007 	ldrb.w	r3, [sp, #7]
    2850:	f003 020f 	and.w	r2, r3, #15
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    2854:	091b      	lsrs	r3, r3, #4
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    2856:	706a      	strb	r2, [r5, #1]
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    2858:	712b      	strb	r3, [r5, #4]
    if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info) ||
    285a:	2201      	movs	r2, #1
    285c:	f10d 0107 	add.w	r1, sp, #7
    2860:	4620      	mov	r0, r4
    2862:	f003 fdeb 	bl	643c <bootutil_buffer_is_erased>
    2866:	b910      	cbnz	r0, 286e <CONFIG_MAIN_STACK_SIZE+0x6e>
    2868:	786b      	ldrb	r3, [r5, #1]
    286a:	2b04      	cmp	r3, #4
    286c:	d903      	bls.n	2876 <CONFIG_MAIN_STACK_SIZE+0x76>
        state->swap_type = BOOT_SWAP_TYPE_NONE;
    286e:	2301      	movs	r3, #1
    2870:	706b      	strb	r3, [r5, #1]
        state->image_num = 0;
    2872:	2300      	movs	r3, #0
    2874:	712b      	strb	r3, [r5, #4]
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    2876:	68a2      	ldr	r2, [r4, #8]
    2878:	3a18      	subs	r2, #24
    287a:	f022 0207 	bic.w	r2, r2, #7
    return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
    287e:	3a08      	subs	r2, #8
    2880:	1ca9      	adds	r1, r5, #2
    2882:	4620      	mov	r0, r4
    2884:	f003 fded 	bl	6462 <boot_read_flag>
    if (rc) {
    2888:	2800      	cmp	r0, #0
    288a:	d1bf      	bne.n	280c <CONFIG_MAIN_STACK_SIZE+0xc>
    return boot_read_image_ok(fap, &state->image_ok);
    288c:	1ce9      	adds	r1, r5, #3
    288e:	4620      	mov	r0, r4
    2890:	f003 fe40 	bl	6514 <boot_read_image_ok>
    2894:	e7bb      	b.n	280e <CONFIG_MAIN_STACK_SIZE+0xe>
    2896:	2303      	movs	r3, #3
    2898:	e7cb      	b.n	2832 <CONFIG_MAIN_STACK_SIZE+0x32>
    289a:	bf00      	nop
    289c:	00006dda 	.word	0x00006dda

000028a0 <boot_swap_type_multi>:
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
}

int
boot_swap_type_multi(int image_index)
{
    28a0:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}

    rc = BOOT_HOOK_CALL(boot_read_swap_state_primary_slot_hook,
                        BOOT_HOOK_REGULAR, image_index, &primary_slot);
    if (rc == BOOT_HOOK_REGULAR)
    {
        rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    28a2:	2003      	movs	r0, #3
    28a4:	4669      	mov	r1, sp
    28a6:	f003 fe3b 	bl	6520 <boot_read_swap_state_by_id>
                                        &primary_slot);
    }
    if (rc) {
    28aa:	bb98      	cbnz	r0, 2914 <boot_swap_type_multi+0x74>
        return BOOT_SWAP_TYPE_PANIC;
    }

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    28ac:	a902      	add	r1, sp, #8
    28ae:	2001      	movs	r0, #1
    28b0:	f003 fe36 	bl	6520 <boot_read_swap_state_by_id>
                                    &secondary_slot);
    if (rc == BOOT_EFLASH) {
    28b4:	2801      	cmp	r0, #1
    28b6:	d12b      	bne.n	2910 <boot_swap_type_multi+0x70>
        BOOT_LOG_INF("Secondary image of image pair (%d.) "
                     "is unreachable. Treat it as empty", image_index);
        secondary_slot.magic = BOOT_MAGIC_UNSET;
    28b8:	2303      	movs	r3, #3
    28ba:	f88d 3008 	strb.w	r3, [sp, #8]
        secondary_slot.swap_type = BOOT_SWAP_TYPE_NONE;
        secondary_slot.copy_done = BOOT_FLAG_UNSET;
        secondary_slot.image_ok = BOOT_FLAG_UNSET;
    28be:	f88d 300b 	strb.w	r3, [sp, #11]
    }

    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
        table = boot_swap_tables + i;

        if (boot_magic_compatible_check(table->magic_primary_slot,
    28c2:	f89d 5000 	ldrb.w	r5, [sp]
                                        primary_slot.magic) &&
            boot_magic_compatible_check(table->magic_secondary_slot,
    28c6:	f89d 6008 	ldrb.w	r6, [sp, #8]
    28ca:	4a19      	ldr	r2, [pc, #100]	; (2930 <boot_swap_type_multi+0x90>)
    28cc:	2400      	movs	r4, #0
        if (boot_magic_compatible_check(table->magic_primary_slot,
    28ce:	7810      	ldrb	r0, [r2, #0]
    28d0:	4629      	mov	r1, r5
    28d2:	f003 fda5 	bl	6420 <boot_magic_compatible_check>
    28d6:	b318      	cbz	r0, 2920 <boot_swap_type_multi+0x80>
            boot_magic_compatible_check(table->magic_secondary_slot,
    28d8:	7850      	ldrb	r0, [r2, #1]
    28da:	4631      	mov	r1, r6
    28dc:	f003 fda0 	bl	6420 <boot_magic_compatible_check>
                                        primary_slot.magic) &&
    28e0:	b1f0      	cbz	r0, 2920 <boot_swap_type_multi+0x80>
                                        secondary_slot.magic) &&
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    28e2:	7893      	ldrb	r3, [r2, #2]
                                        secondary_slot.magic) &&
    28e4:	2b04      	cmp	r3, #4
    28e6:	d003      	beq.n	28f0 <boot_swap_type_multi+0x50>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    28e8:	f89d 1003 	ldrb.w	r1, [sp, #3]
    28ec:	4299      	cmp	r1, r3
    28ee:	d117      	bne.n	2920 <boot_swap_type_multi+0x80>
                table->image_ok_primary_slot == primary_slot.image_ok) &&
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    28f0:	78d3      	ldrb	r3, [r2, #3]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    28f2:	2b04      	cmp	r3, #4
    28f4:	d003      	beq.n	28fe <boot_swap_type_multi+0x5e>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    28f6:	f89d 100b 	ldrb.w	r1, [sp, #11]
    28fa:	4299      	cmp	r1, r3
    28fc:	d110      	bne.n	2920 <boot_swap_type_multi+0x80>
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    28fe:	7913      	ldrb	r3, [r2, #4]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    2900:	2b04      	cmp	r3, #4
    2902:	d109      	bne.n	2918 <boot_swap_type_multi+0x78>
                table->copy_done_primary_slot == primary_slot.copy_done)) {
            BOOT_LOG_INF("Swap type: %s",
    2904:	7950      	ldrb	r0, [r2, #5]
                         table->swap_type == BOOT_SWAP_TYPE_TEST   ? "test"   :
                         table->swap_type == BOOT_SWAP_TYPE_PERM   ? "perm"   :
                         table->swap_type == BOOT_SWAP_TYPE_REVERT ? "revert" :
                         "BUG; can't happen");
            if (table->swap_type != BOOT_SWAP_TYPE_TEST &&
    2906:	1e83      	subs	r3, r0, #2
    2908:	2b02      	cmp	r3, #2
    290a:	d803      	bhi.n	2914 <boot_swap_type_multi+0x74>
        }
    }

    BOOT_LOG_INF("Swap type: none");
    return BOOT_SWAP_TYPE_NONE;
}
    290c:	b004      	add	sp, #16
    290e:	bd70      	pop	{r4, r5, r6, pc}
    } else if (rc) {
    2910:	2800      	cmp	r0, #0
    2912:	d0d6      	beq.n	28c2 <boot_swap_type_multi+0x22>
        return BOOT_SWAP_TYPE_PANIC;
    2914:	20ff      	movs	r0, #255	; 0xff
    2916:	e7f9      	b.n	290c <boot_swap_type_multi+0x6c>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    2918:	f89d 1002 	ldrb.w	r1, [sp, #2]
    291c:	4299      	cmp	r1, r3
    291e:	d0f1      	beq.n	2904 <boot_swap_type_multi+0x64>
    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
    2920:	3401      	adds	r4, #1
    2922:	2c03      	cmp	r4, #3
    2924:	f102 0206 	add.w	r2, r2, #6
    2928:	d1d1      	bne.n	28ce <boot_swap_type_multi+0x2e>
    return BOOT_SWAP_TYPE_NONE;
    292a:	2001      	movs	r0, #1
    292c:	e7ee      	b.n	290c <boot_swap_type_multi+0x6c>
    292e:	bf00      	nop
    2930:	00006ebd 	.word	0x00006ebd

00002934 <nrf52_errata_103>:
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2934:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    2938:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    293c:	2a08      	cmp	r2, #8
    293e:	d106      	bne.n	294e <nrf52_errata_103+0x1a>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    2940:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                switch(var2)
    2944:	2b05      	cmp	r3, #5
    2946:	d802      	bhi.n	294e <nrf52_errata_103+0x1a>
    2948:	4a02      	ldr	r2, [pc, #8]	; (2954 <nrf52_errata_103+0x20>)
    294a:	5cd0      	ldrb	r0, [r2, r3]
    294c:	4770      	bx	lr
                        return false;
    294e:	2000      	movs	r0, #0
}
    2950:	4770      	bx	lr
    2952:	bf00      	nop
    2954:	00006ed5 	.word	0x00006ed5

00002958 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    2958:	4a02      	ldr	r2, [pc, #8]	; (2964 <nvmc_wait+0xc>)
    295a:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    295e:	2b00      	cmp	r3, #0
    2960:	d0fb      	beq.n	295a <nvmc_wait+0x2>
}
    2962:	4770      	bx	lr
    2964:	4001e000 	.word	0x4001e000

00002968 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    2968:	b510      	push	{r4, lr}
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    296a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    296e:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    2972:	2a08      	cmp	r2, #8
    2974:	d14e      	bne.n	2a14 <SystemInit+0xac>

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
            NRF_CLOCK->EVENTS_DONE = 0;
    2976:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    297a:	2100      	movs	r1, #0
    297c:	f8c2 110c 	str.w	r1, [r2, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    2980:	f8c2 1110 	str.w	r1, [r2, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    2984:	f8c2 1538 	str.w	r1, [r2, #1336]	; 0x538

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    2988:	f502 4240 	add.w	r2, r2, #49152	; 0xc000
    298c:	f8d3 1404 	ldr.w	r1, [r3, #1028]	; 0x404
    2990:	f8c2 1520 	str.w	r1, [r2, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    2994:	f8d3 1408 	ldr.w	r1, [r3, #1032]	; 0x408
    2998:	f8c2 1524 	str.w	r1, [r2, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    299c:	f8d3 140c 	ldr.w	r1, [r3, #1036]	; 0x40c
    29a0:	f8c2 1528 	str.w	r1, [r2, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    29a4:	f8d3 1410 	ldr.w	r1, [r3, #1040]	; 0x410
    29a8:	f8c2 152c 	str.w	r1, [r2, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    29ac:	f8d3 1414 	ldr.w	r1, [r3, #1044]	; 0x414
    29b0:	f8c2 1530 	str.w	r1, [r2, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    29b4:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    29b8:	f8c2 1534 	str.w	r1, [r2, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    29bc:	f8d3 141c 	ldr.w	r1, [r3, #1052]	; 0x41c
    29c0:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    29c4:	f8d3 1420 	ldr.w	r1, [r3, #1056]	; 0x420
    29c8:	f8c2 1544 	str.w	r1, [r2, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    29cc:	f8d3 1424 	ldr.w	r1, [r3, #1060]	; 0x424
    29d0:	f8c2 1548 	str.w	r1, [r2, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    29d4:	f8d3 1428 	ldr.w	r1, [r3, #1064]	; 0x428
    29d8:	f8c2 154c 	str.w	r1, [r2, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    29dc:	f8d3 142c 	ldr.w	r1, [r3, #1068]	; 0x42c
    29e0:	f8c2 1550 	str.w	r1, [r2, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    29e4:	f8d3 1430 	ldr.w	r1, [r3, #1072]	; 0x430
    29e8:	f8c2 1554 	str.w	r1, [r2, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    29ec:	f8d3 1434 	ldr.w	r1, [r3, #1076]	; 0x434
    29f0:	f8c2 1560 	str.w	r1, [r2, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    29f4:	f8d3 1438 	ldr.w	r1, [r3, #1080]	; 0x438
    29f8:	f8c2 1564 	str.w	r1, [r2, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    29fc:	f8d3 143c 	ldr.w	r1, [r3, #1084]	; 0x43c
    2a00:	f8c2 1568 	str.w	r1, [r2, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    2a04:	f8d3 1440 	ldr.w	r1, [r3, #1088]	; 0x440
    2a08:	f8c2 156c 	str.w	r1, [r2, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    2a0c:	f8d3 3444 	ldr.w	r3, [r3, #1092]	; 0x444
    2a10:	f8c2 3570 	str.w	r3, [r2, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_98_ENABLE_WORKAROUND
        /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_98()){
    2a14:	f7ff ff8e 	bl	2934 <nrf52_errata_103>
    2a18:	b118      	cbz	r0, 2a22 <SystemInit+0xba>
            *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
    2a1a:	4b43      	ldr	r3, [pc, #268]	; (2b28 <SystemInit+0x1c0>)
    2a1c:	4a43      	ldr	r2, [pc, #268]	; (2b2c <SystemInit+0x1c4>)
    2a1e:	f8c3 268c 	str.w	r2, [r3, #1676]	; 0x68c
    #endif

    #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
        /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_103()){
    2a22:	f7ff ff87 	bl	2934 <nrf52_errata_103>
    2a26:	b118      	cbz	r0, 2a30 <SystemInit+0xc8>
            NRF_CCM->MAXPACKETSIZE = 0xFBul;
    2a28:	4b41      	ldr	r3, [pc, #260]	; (2b30 <SystemInit+0x1c8>)
    2a2a:	22fb      	movs	r2, #251	; 0xfb
    2a2c:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    #endif

    #if NRF52_ERRATA_115_ENABLE_WORKAROUND
        /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_115()){
    2a30:	f7ff ff80 	bl	2934 <nrf52_errata_103>
    2a34:	b170      	cbz	r0, 2a54 <SystemInit+0xec>
            *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
    2a36:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    2a3a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    2a3e:	f8d1 2ee4 	ldr.w	r2, [r1, #3812]	; 0xee4
    2a42:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    2a46:	f022 020f 	bic.w	r2, r2, #15
    2a4a:	f003 030f 	and.w	r3, r3, #15
    2a4e:	4313      	orrs	r3, r2
    2a50:	f8c1 3ee4 	str.w	r3, [r1, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_120_ENABLE_WORKAROUND
        /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_120()){
    2a54:	f7ff ff6e 	bl	2934 <nrf52_errata_103>
    2a58:	b120      	cbz	r0, 2a64 <SystemInit+0xfc>
            *(volatile uint32_t *)0x40029640ul = 0x200ul;
    2a5a:	4b36      	ldr	r3, [pc, #216]	; (2b34 <SystemInit+0x1cc>)
    2a5c:	f44f 7200 	mov.w	r2, #512	; 0x200
    2a60:	f8c3 2640 	str.w	r2, [r3, #1600]	; 0x640
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2a64:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    2a68:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    2a6c:	2b08      	cmp	r3, #8
    2a6e:	d109      	bne.n	2a84 <SystemInit+0x11c>

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    2a70:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a74:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    2a78:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    2a7a:	bf44      	itt	mi
    2a7c:	f06f 0201 	mvnmi.w	r2, #1
    2a80:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400

    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
     * operations are not used in your code. */
    #if (__FPU_USED == 1)
        SCB->CPACR |= (3UL << 20) | (3UL << 22);
    2a84:	4a2c      	ldr	r2, [pc, #176]	; (2b38 <SystemInit+0x1d0>)
    2a86:	f8d2 3088 	ldr.w	r3, [r2, #136]	; 0x88
    2a8a:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
    2a8e:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
  __ASM volatile ("dsb 0xF":::"memory");
    2a92:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2a96:	f3bf 8f6f 	isb	sy
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2a9a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                        return true;
                }
            }
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    2a9e:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    2aa2:	2a08      	cmp	r2, #8
    2aa4:	d10e      	bne.n	2ac4 <SystemInit+0x15c>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    2aa6:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
            {
                switch(var2)
    2aaa:	2b05      	cmp	r3, #5
    2aac:	d802      	bhi.n	2ab4 <SystemInit+0x14c>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    2aae:	4a23      	ldr	r2, [pc, #140]	; (2b3c <SystemInit+0x1d4>)
    2ab0:	5cd3      	ldrb	r3, [r2, r3]
    2ab2:	b13b      	cbz	r3, 2ac4 <SystemInit+0x15c>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    2ab4:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2ab8:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    2abc:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2ac0:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2ac4:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2ac8:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    2acc:	2a00      	cmp	r2, #0
    2ace:	db03      	blt.n	2ad8 <SystemInit+0x170>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    2ad0:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2ad4:	2b00      	cmp	r3, #0
    2ad6:	da22      	bge.n	2b1e <SystemInit+0x1b6>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2ad8:	4919      	ldr	r1, [pc, #100]	; (2b40 <SystemInit+0x1d8>)
    2ada:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2adc:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2ae0:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2ae4:	2412      	movs	r4, #18
    nvmc_wait();
    2ae6:	f7ff ff37 	bl	2958 <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2aea:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    2aee:	f7ff ff33 	bl	2958 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    2af2:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    2af6:	f7ff ff2f 	bl	2958 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2afa:	2300      	movs	r3, #0
    2afc:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    2b00:	f7ff ff2a 	bl	2958 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    2b04:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2b08:	490b      	ldr	r1, [pc, #44]	; (2b38 <SystemInit+0x1d0>)
    2b0a:	4b0e      	ldr	r3, [pc, #56]	; (2b44 <SystemInit+0x1dc>)
    2b0c:	68ca      	ldr	r2, [r1, #12]
    2b0e:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2b12:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2b14:	60cb      	str	r3, [r1, #12]
    2b16:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2b1a:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2b1c:	e7fd      	b.n	2b1a <SystemInit+0x1b2>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    2b1e:	4b0a      	ldr	r3, [pc, #40]	; (2b48 <SystemInit+0x1e0>)
    2b20:	4a0a      	ldr	r2, [pc, #40]	; (2b4c <SystemInit+0x1e4>)
    2b22:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    2b24:	bd10      	pop	{r4, pc}
    2b26:	bf00      	nop
    2b28:	40005000 	.word	0x40005000
    2b2c:	00038148 	.word	0x00038148
    2b30:	4000f000 	.word	0x4000f000
    2b34:	40029000 	.word	0x40029000
    2b38:	e000ed00 	.word	0xe000ed00
    2b3c:	00006ecf 	.word	0x00006ecf
    2b40:	4001e000 	.word	0x4001e000
    2b44:	05fa0004 	.word	0x05fa0004
    2b48:	2000000c 	.word	0x2000000c
    2b4c:	03d09000 	.word	0x03d09000

00002b50 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    2b50:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    2b52:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    2b54:	6802      	ldr	r2, [r0, #0]
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    2b56:	f3bf 8f5b 	dmb	ish
        idx = 31 - NRF_CLZ(prev_mask);
    2b5a:	fab2 f382 	clz	r3, r2
    2b5e:	f1c3 031f 	rsb	r3, r3, #31
    2b62:	b2db      	uxtb	r3, r3
        new_mask = prev_mask & ~NRFX_BIT(idx);
    2b64:	fa05 f403 	lsl.w	r4, r5, r3
    2b68:	ea22 0404 	bic.w	r4, r2, r4
    2b6c:	e850 6f00 	ldrex	r6, [r0]
    2b70:	4296      	cmp	r6, r2
    2b72:	d104      	bne.n	2b7e <nrfx_flag32_alloc+0x2e>
    2b74:	e840 4c00 	strex	ip, r4, [r0]
    2b78:	f1bc 0f00 	cmp.w	ip, #0
    2b7c:	d1f6      	bne.n	2b6c <nrfx_flag32_alloc+0x1c>
    2b7e:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    2b82:	d1e7      	bne.n	2b54 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
}
    2b84:	4801      	ldr	r0, [pc, #4]	; (2b8c <nrfx_flag32_alloc+0x3c>)
    *p_flag = idx;
    2b86:	700b      	strb	r3, [r1, #0]
}
    2b88:	bd70      	pop	{r4, r5, r6, pc}
    2b8a:	bf00      	nop
    2b8c:	0bad0000 	.word	0x0bad0000

00002b90 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    2b90:	b510      	push	{r4, lr}
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    2b92:	6803      	ldr	r3, [r0, #0]
    2b94:	40cb      	lsrs	r3, r1
    2b96:	07db      	lsls	r3, r3, #31
    2b98:	d414      	bmi.n	2bc4 <nrfx_flag32_free+0x34>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    2b9a:	2301      	movs	r3, #1
    2b9c:	408b      	lsls	r3, r1
        prev_mask = *p_mask;
    2b9e:	6802      	ldr	r2, [r0, #0]
    2ba0:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    2ba4:	ea43 0102 	orr.w	r1, r3, r2
    2ba8:	e850 4f00 	ldrex	r4, [r0]
    2bac:	4294      	cmp	r4, r2
    2bae:	d104      	bne.n	2bba <nrfx_flag32_free+0x2a>
    2bb0:	e840 1c00 	strex	ip, r1, [r0]
    2bb4:	f1bc 0f00 	cmp.w	ip, #0
    2bb8:	d1f6      	bne.n	2ba8 <nrfx_flag32_free+0x18>
    2bba:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    2bbe:	d1ee      	bne.n	2b9e <nrfx_flag32_free+0xe>

    return NRFX_SUCCESS;
    2bc0:	4801      	ldr	r0, [pc, #4]	; (2bc8 <nrfx_flag32_free+0x38>)
}
    2bc2:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    2bc4:	4801      	ldr	r0, [pc, #4]	; (2bcc <nrfx_flag32_free+0x3c>)
    2bc6:	e7fc      	b.n	2bc2 <nrfx_flag32_free+0x32>
    2bc8:	0bad0000 	.word	0x0bad0000
    2bcc:	0bad0004 	.word	0x0bad0004

00002bd0 <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    2bd0:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    2bd2:	4604      	mov	r4, r0
    2bd4:	b118      	cbz	r0, 2bde <clock_stop+0xe>
    2bd6:	2801      	cmp	r0, #1
    2bd8:	d022      	beq.n	2c20 <clock_stop+0x50>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2bda:	b003      	add	sp, #12
    2bdc:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    2bde:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2be2:	2202      	movs	r2, #2
    2be4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2be8:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    2bec:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2bf0:	2201      	movs	r2, #1
    2bf2:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    2bf4:	4607      	mov	r7, r0
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    2bf6:	2301      	movs	r3, #1
    2bf8:	f88d 3007 	strb.w	r3, [sp, #7]
    2bfc:	f242 7510 	movw	r5, #10000	; 0x2710
    2c00:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    2c04:	b1cc      	cbz	r4, 2c3a <clock_stop+0x6a>
    2c06:	2c01      	cmp	r4, #1
    2c08:	d1e7      	bne.n	2bda <clock_stop+0xa>
            if (p_clk_src != NULL)
    2c0a:	b3c7      	cbz	r7, 2c7e <clock_stop+0xae>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2c0c:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    2c10:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    2c14:	703b      	strb	r3, [r7, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2c16:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    2c1a:	03da      	lsls	r2, r3, #15
    2c1c:	d521      	bpl.n	2c62 <clock_stop+0x92>
    2c1e:	e016      	b.n	2c4e <clock_stop+0x7e>
    p_reg->INTENCLR = mask;
    2c20:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2c24:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    2c26:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2c2a:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    2c2e:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2c32:	6058      	str	r0, [r3, #4]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    2c34:	f10d 0707 	add.w	r7, sp, #7
    2c38:	e7dd      	b.n	2bf6 <clock_stop+0x26>
            if (p_clk_src != NULL)
    2c3a:	b1b7      	cbz	r7, 2c6a <clock_stop+0x9a>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2c3c:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    2c40:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    2c44:	603b      	str	r3, [r7, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2c46:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    2c4a:	03d8      	lsls	r0, r3, #15
    2c4c:	d5c5      	bpl.n	2bda <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    2c4e:	f89d 0007 	ldrb.w	r0, [sp, #7]
    2c52:	2801      	cmp	r0, #1
    2c54:	d103      	bne.n	2c5e <clock_stop+0x8e>
    2c56:	f003 fc89 	bl	656c <nrfx_busy_wait>
    2c5a:	3d01      	subs	r5, #1
    2c5c:	d1d2      	bne.n	2c04 <clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    2c5e:	2c01      	cmp	r4, #1
    2c60:	d1bb      	bne.n	2bda <clock_stop+0xa>
            m_clock_cb.hfclk_started = false;
    2c62:	4b0c      	ldr	r3, [pc, #48]	; (2c94 <clock_stop+0xc4>)
    2c64:	2200      	movs	r2, #0
    2c66:	715a      	strb	r2, [r3, #5]
    2c68:	e7b7      	b.n	2bda <clock_stop+0xa>
    2c6a:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    2c6e:	03d9      	lsls	r1, r3, #15
    2c70:	d5b3      	bpl.n	2bda <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    2c72:	2001      	movs	r0, #1
    2c74:	f003 fc7a 	bl	656c <nrfx_busy_wait>
    2c78:	3d01      	subs	r5, #1
    2c7a:	d1f6      	bne.n	2c6a <clock_stop+0x9a>
    2c7c:	e7ad      	b.n	2bda <clock_stop+0xa>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2c7e:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    2c82:	03db      	lsls	r3, r3, #15
    2c84:	d5ed      	bpl.n	2c62 <clock_stop+0x92>
    2c86:	2001      	movs	r0, #1
    2c88:	f003 fc70 	bl	656c <nrfx_busy_wait>
    2c8c:	3d01      	subs	r5, #1
    2c8e:	d1f6      	bne.n	2c7e <clock_stop+0xae>
    2c90:	e7e7      	b.n	2c62 <clock_stop+0x92>
    2c92:	bf00      	nop
    2c94:	20001628 	.word	0x20001628

00002c98 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    2c98:	4b04      	ldr	r3, [pc, #16]	; (2cac <nrfx_clock_init+0x14>)
    2c9a:	791a      	ldrb	r2, [r3, #4]
    2c9c:	b922      	cbnz	r2, 2ca8 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    2c9e:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    2ca0:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    2ca2:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    2ca4:	4802      	ldr	r0, [pc, #8]	; (2cb0 <nrfx_clock_init+0x18>)
    2ca6:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    2ca8:	4802      	ldr	r0, [pc, #8]	; (2cb4 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2caa:	4770      	bx	lr
    2cac:	20001628 	.word	0x20001628
    2cb0:	0bad0000 	.word	0x0bad0000
    2cb4:	0bad000c 	.word	0x0bad000c

00002cb8 <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    2cb8:	b510      	push	{r4, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2cba:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2cbe:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    2cc2:	b16a      	cbz	r2, 2ce0 <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2cc4:	2200      	movs	r2, #0
    2cc6:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    2cca:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    2cce:	2201      	movs	r2, #1
    2cd0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    2cd4:	4b11      	ldr	r3, [pc, #68]	; (2d1c <nrfx_power_clock_irq_handler+0x64>)
    2cd6:	7958      	ldrb	r0, [r3, #5]
    2cd8:	b910      	cbnz	r0, 2ce0 <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    2cda:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    2cdc:	681b      	ldr	r3, [r3, #0]
    2cde:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2ce0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2ce4:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    2ce8:	b172      	cbz	r2, 2d08 <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2cea:	2200      	movs	r2, #0
    2cec:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    2cf0:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2cf4:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2cf8:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    2cfc:	0792      	lsls	r2, r2, #30
    2cfe:	d104      	bne.n	2d0a <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2d00:	2201      	movs	r2, #1
    2d02:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d06:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    2d08:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    2d0a:	2202      	movs	r2, #2
    2d0c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2d10:	4b02      	ldr	r3, [pc, #8]	; (2d1c <nrfx_power_clock_irq_handler+0x64>)
}
    2d12:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2d16:	681b      	ldr	r3, [r3, #0]
    2d18:	2001      	movs	r0, #1
    2d1a:	4718      	bx	r3
    2d1c:	20001628 	.word	0x20001628

00002d20 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    2d20:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    2d22:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    2d26:	095b      	lsrs	r3, r3, #5
        case 0: return NRF_P0;
    2d28:	2b01      	cmp	r3, #1
    *p_pin = pin_number & 0x1F;
    2d2a:	6002      	str	r2, [r0, #0]
}
    2d2c:	4802      	ldr	r0, [pc, #8]	; (2d38 <nrf_gpio_pin_port_decode+0x18>)
    2d2e:	bf18      	it	ne
    2d30:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    2d34:	4770      	bx	lr
    2d36:	bf00      	nop
    2d38:	50000300 	.word	0x50000300

00002d3c <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    2d3c:	4b03      	ldr	r3, [pc, #12]	; (2d4c <pin_in_use_by_te+0x10>)
    2d3e:	3008      	adds	r0, #8
    2d40:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    2d44:	f3c0 1040 	ubfx	r0, r0, #5, #1
    2d48:	4770      	bx	lr
    2d4a:	bf00      	nop
    2d4c:	20000010 	.word	0x20000010

00002d50 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    2d50:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2d52:	f100 0308 	add.w	r3, r0, #8
    2d56:	4c0c      	ldr	r4, [pc, #48]	; (2d88 <call_handler+0x38>)
    2d58:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    2d5c:	05da      	lsls	r2, r3, #23
{
    2d5e:	4605      	mov	r5, r0
    2d60:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2d62:	d507      	bpl.n	2d74 <call_handler+0x24>
    2d64:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    2d68:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    2d6c:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    2d70:	6852      	ldr	r2, [r2, #4]
    2d72:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    2d74:	68a3      	ldr	r3, [r4, #8]
    2d76:	b12b      	cbz	r3, 2d84 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    2d78:	68e2      	ldr	r2, [r4, #12]
    2d7a:	4631      	mov	r1, r6
    2d7c:	4628      	mov	r0, r5
    }
}
    2d7e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    2d82:	4718      	bx	r3
}
    2d84:	bd70      	pop	{r4, r5, r6, pc}
    2d86:	bf00      	nop
    2d88:	20000010 	.word	0x20000010

00002d8c <release_handler>:
{
    2d8c:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2d8e:	4a13      	ldr	r2, [pc, #76]	; (2ddc <release_handler+0x50>)
    2d90:	3008      	adds	r0, #8
    2d92:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    2d96:	05d9      	lsls	r1, r3, #23
    2d98:	d51c      	bpl.n	2dd4 <release_handler+0x48>
    2d9a:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    2d9e:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    2da2:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    2da6:	f102 040e 	add.w	r4, r2, #14
    2daa:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    2dac:	f834 3f02 	ldrh.w	r3, [r4, #2]!
    2db0:	f413 7f80 	tst.w	r3, #256	; 0x100
    2db4:	d003      	beq.n	2dbe <release_handler+0x32>
    2db6:	f3c3 2343 	ubfx	r3, r3, #9, #4
    2dba:	4299      	cmp	r1, r3
    2dbc:	d00a      	beq.n	2dd4 <release_handler+0x48>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    2dbe:	3001      	adds	r0, #1
    2dc0:	2830      	cmp	r0, #48	; 0x30
    2dc2:	d1f3      	bne.n	2dac <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    2dc4:	2300      	movs	r3, #0
    2dc6:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    2dca:	4805      	ldr	r0, [pc, #20]	; (2de0 <release_handler+0x54>)
}
    2dcc:	f85d 4b04 	ldr.w	r4, [sp], #4
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    2dd0:	f7ff bede 	b.w	2b90 <nrfx_flag32_free>
}
    2dd4:	f85d 4b04 	ldr.w	r4, [sp], #4
    2dd8:	4770      	bx	lr
    2dda:	bf00      	nop
    2ddc:	20000010 	.word	0x20000010
    2de0:	20000084 	.word	0x20000084

00002de4 <pin_handler_trigger_uninit>:
{
    2de4:	b538      	push	{r3, r4, r5, lr}
    2de6:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    2de8:	f7ff ffa8 	bl	2d3c <pin_in_use_by_te>
    2dec:	4c09      	ldr	r4, [pc, #36]	; (2e14 <pin_handler_trigger_uninit+0x30>)
    2dee:	f102 0508 	add.w	r5, r2, #8
    2df2:	b140      	cbz	r0, 2e06 <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2df4:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    2df8:	4907      	ldr	r1, [pc, #28]	; (2e18 <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    2dfa:	0b5b      	lsrs	r3, r3, #13
    2dfc:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    2e00:	2000      	movs	r0, #0
    2e02:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    2e06:	4610      	mov	r0, r2
    2e08:	f7ff ffc0 	bl	2d8c <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    2e0c:	2300      	movs	r3, #0
    2e0e:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    2e12:	bd38      	pop	{r3, r4, r5, pc}
    2e14:	20000010 	.word	0x20000010
    2e18:	40006000 	.word	0x40006000

00002e1c <nrfx_gpiote_input_configure>:
{
    2e1c:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    2e20:	4604      	mov	r4, r0
    2e22:	4616      	mov	r6, r2
    2e24:	461d      	mov	r5, r3
    if (p_input_config)
    2e26:	b301      	cbz	r1, 2e6a <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2e28:	4f4e      	ldr	r7, [pc, #312]	; (2f64 <nrfx_gpiote_input_configure+0x148>)
    2e2a:	f100 0808 	add.w	r8, r0, #8
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    2e2e:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    2e32:	079b      	lsls	r3, r3, #30
    2e34:	d502      	bpl.n	2e3c <nrfx_gpiote_input_configure+0x20>
    2e36:	f7ff ff81 	bl	2d3c <pin_in_use_by_te>
    2e3a:	bb10      	cbnz	r0, 2e82 <nrfx_gpiote_input_configure+0x66>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    2e3c:	2300      	movs	r3, #0
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    2e3e:	e9cd 3300 	strd	r3, r3, [sp]
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    2e42:	f88d 300e 	strb.w	r3, [sp, #14]
        nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT;
    2e46:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    2e4a:	f10d 020f 	add.w	r2, sp, #15
    2e4e:	460b      	mov	r3, r1
    2e50:	4620      	mov	r0, r4
    2e52:	f10d 010e 	add.w	r1, sp, #14
    2e56:	f003 fbd6 	bl	6606 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    2e5a:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    2e5e:	f023 0302 	bic.w	r3, r3, #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    2e62:	f043 0301 	orr.w	r3, r3, #1
    2e66:	f827 3018 	strh.w	r3, [r7, r8, lsl #1]
    if (p_trigger_config)
    2e6a:	b346      	cbz	r6, 2ebe <nrfx_gpiote_input_configure+0xa2>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2e6c:	4b3d      	ldr	r3, [pc, #244]	; (2f64 <nrfx_gpiote_input_configure+0x148>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    2e6e:	f896 c000 	ldrb.w	ip, [r6]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    2e72:	6872      	ldr	r2, [r6, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2e74:	f104 0708 	add.w	r7, r4, #8
    2e78:	f833 1017 	ldrh.w	r1, [r3, r7, lsl #1]
        if (pin_is_output(pin))
    2e7c:	0788      	lsls	r0, r1, #30
    2e7e:	d502      	bpl.n	2e86 <nrfx_gpiote_input_configure+0x6a>
            if (use_evt)
    2e80:	b1aa      	cbz	r2, 2eae <nrfx_gpiote_input_configure+0x92>
            return NRFX_ERROR_INVALID_PARAM;
    2e82:	4839      	ldr	r0, [pc, #228]	; (2f68 <nrfx_gpiote_input_configure+0x14c>)
    2e84:	e01d      	b.n	2ec2 <nrfx_gpiote_input_configure+0xa6>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    2e86:	f021 0120 	bic.w	r1, r1, #32
    2e8a:	04c9      	lsls	r1, r1, #19
    2e8c:	0cc9      	lsrs	r1, r1, #19
    2e8e:	f823 1017 	strh.w	r1, [r3, r7, lsl #1]
            if (use_evt)
    2e92:	b162      	cbz	r2, 2eae <nrfx_gpiote_input_configure+0x92>
                if (!edge)
    2e94:	f1bc 0f03 	cmp.w	ip, #3
    2e98:	d8f3      	bhi.n	2e82 <nrfx_gpiote_input_configure+0x66>
                uint8_t ch = *p_trigger_config->p_in_channel;
    2e9a:	6872      	ldr	r2, [r6, #4]
    2e9c:	7816      	ldrb	r6, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    2e9e:	f1bc 0f00 	cmp.w	ip, #0
    2ea2:	d111      	bne.n	2ec8 <nrfx_gpiote_input_configure+0xac>
    2ea4:	4a31      	ldr	r2, [pc, #196]	; (2f6c <nrfx_gpiote_input_configure+0x150>)
    2ea6:	f506 76a2 	add.w	r6, r6, #324	; 0x144
    2eaa:	f842 c026 	str.w	ip, [r2, r6, lsl #2]
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    2eae:	f833 2017 	ldrh.w	r2, [r3, r7, lsl #1]
    2eb2:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    2eb6:	ea42 028c 	orr.w	r2, r2, ip, lsl #2
    2eba:	f823 2017 	strh.w	r2, [r3, r7, lsl #1]
    if (p_handler_config)
    2ebe:	bb45      	cbnz	r5, 2f12 <nrfx_gpiote_input_configure+0xf6>
        err = NRFX_SUCCESS;
    2ec0:	482b      	ldr	r0, [pc, #172]	; (2f70 <nrfx_gpiote_input_configure+0x154>)
}
    2ec2:	b004      	add	sp, #16
    2ec4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    2ec8:	00b2      	lsls	r2, r6, #2
    2eca:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2ece:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    2ed2:	ea41 3146 	orr.w	r1, r1, r6, lsl #13
    2ed6:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    2eda:	f020 0003 	bic.w	r0, r0, #3
    2ede:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    2ee2:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    2ee6:	f420 304f 	bic.w	r0, r0, #211968	; 0x33c00
    2eea:	f420 7040 	bic.w	r0, r0, #768	; 0x300
    2eee:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2ef2:	0220      	lsls	r0, r4, #8
    2ef4:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    2ef8:	f400 507c 	and.w	r0, r0, #16128	; 0x3f00
    2efc:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
    2f00:	ea40 000e 	orr.w	r0, r0, lr
    2f04:	f041 0120 	orr.w	r1, r1, #32
    2f08:	f823 1017 	strh.w	r1, [r3, r7, lsl #1]
    2f0c:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
    2f10:	e7cd      	b.n	2eae <nrfx_gpiote_input_configure+0x92>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    2f12:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    2f16:	4620      	mov	r0, r4
    2f18:	f7ff ff38 	bl	2d8c <release_handler>
    if (!handler)
    2f1c:	2e00      	cmp	r6, #0
    2f1e:	d0cf      	beq.n	2ec0 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    2f20:	4d10      	ldr	r5, [pc, #64]	; (2f64 <nrfx_gpiote_input_configure+0x148>)
    2f22:	e9d5 2300 	ldrd	r2, r3, [r5]
    2f26:	4296      	cmp	r6, r2
    2f28:	d101      	bne.n	2f2e <nrfx_gpiote_input_configure+0x112>
    2f2a:	429f      	cmp	r7, r3
    2f2c:	d018      	beq.n	2f60 <nrfx_gpiote_input_configure+0x144>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    2f2e:	4811      	ldr	r0, [pc, #68]	; (2f74 <nrfx_gpiote_input_configure+0x158>)
    2f30:	f10d 010f 	add.w	r1, sp, #15
    2f34:	f7ff fe0c 	bl	2b50 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    2f38:	4b0d      	ldr	r3, [pc, #52]	; (2f70 <nrfx_gpiote_input_configure+0x154>)
    2f3a:	4298      	cmp	r0, r3
    2f3c:	d1c1      	bne.n	2ec2 <nrfx_gpiote_input_configure+0xa6>
        handler_id = (int32_t)id;
    2f3e:	f89d 200f 	ldrb.w	r2, [sp, #15]
    m_cb.handlers[handler_id].handler = handler;
    2f42:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    2f46:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    2f4a:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    2f4c:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    2f4e:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    2f52:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    2f56:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    2f5a:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    return NRFX_SUCCESS;
    2f5e:	e7af      	b.n	2ec0 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    2f60:	2200      	movs	r2, #0
    2f62:	e7ee      	b.n	2f42 <nrfx_gpiote_input_configure+0x126>
    2f64:	20000010 	.word	0x20000010
    2f68:	0bad0004 	.word	0x0bad0004
    2f6c:	40006000 	.word	0x40006000
    2f70:	0bad0000 	.word	0x0bad0000
    2f74:	20000084 	.word	0x20000084

00002f78 <nrfx_gpiote_output_configure>:
{
    2f78:	b5f0      	push	{r4, r5, r6, r7, lr}
    2f7a:	4604      	mov	r4, r0
    2f7c:	b085      	sub	sp, #20
    2f7e:	4615      	mov	r5, r2
    if (p_config)
    2f80:	b319      	cbz	r1, 2fca <nrfx_gpiote_output_configure+0x52>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2f82:	4e33      	ldr	r6, [pc, #204]	; (3050 <nrfx_gpiote_output_configure+0xd8>)
    2f84:	f100 0708 	add.w	r7, r0, #8
    2f88:	f836 2017 	ldrh.w	r2, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    2f8c:	0793      	lsls	r3, r2, #30
    2f8e:	d403      	bmi.n	2f98 <nrfx_gpiote_output_configure+0x20>
    2f90:	f7ff fed4 	bl	2d3c <pin_in_use_by_te>
    2f94:	2800      	cmp	r0, #0
    2f96:	d158      	bne.n	304a <nrfx_gpiote_output_configure+0xd2>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    2f98:	f012 0f1c 	tst.w	r2, #28
    2f9c:	d002      	beq.n	2fa4 <nrfx_gpiote_output_configure+0x2c>
    2f9e:	784b      	ldrb	r3, [r1, #1]
    2fa0:	2b01      	cmp	r3, #1
    2fa2:	d052      	beq.n	304a <nrfx_gpiote_output_configure+0xd2>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT;
    2fa4:	2301      	movs	r3, #1
    2fa6:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull,
    2faa:	2300      	movs	r3, #0
    2fac:	e9cd 1300 	strd	r1, r3, [sp]
    2fb0:	1c4a      	adds	r2, r1, #1
    2fb2:	1c8b      	adds	r3, r1, #2
    2fb4:	4620      	mov	r0, r4
    2fb6:	f10d 010f 	add.w	r1, sp, #15
    2fba:	f003 fb24 	bl	6606 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    2fbe:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    2fc2:	f043 0303 	orr.w	r3, r3, #3
    2fc6:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_task_config)
    2fca:	b915      	cbnz	r5, 2fd2 <nrfx_gpiote_output_configure+0x5a>
    return NRFX_SUCCESS;
    2fcc:	4821      	ldr	r0, [pc, #132]	; (3054 <nrfx_gpiote_output_configure+0xdc>)
}
    2fce:	b005      	add	sp, #20
    2fd0:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2fd2:	4e1f      	ldr	r6, [pc, #124]	; (3050 <nrfx_gpiote_output_configure+0xd8>)
    2fd4:	f104 0708 	add.w	r7, r4, #8
    2fd8:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    2fdc:	0783      	lsls	r3, r0, #30
    2fde:	d534      	bpl.n	304a <nrfx_gpiote_output_configure+0xd2>
        uint32_t ch = p_task_config->task_ch;
    2fe0:	f895 c000 	ldrb.w	ip, [r5]
    p_reg->CONFIG[idx] = 0;
    2fe4:	4661      	mov	r1, ip
    2fe6:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    2fe8:	f020 0020 	bic.w	r0, r0, #32
    2fec:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    2ff0:	04c0      	lsls	r0, r0, #19
    2ff2:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    2ff6:	0cc0      	lsrs	r0, r0, #19
    2ff8:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    2ffc:	2300      	movs	r3, #0
    2ffe:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    3002:	786a      	ldrb	r2, [r5, #1]
    3004:	2a00      	cmp	r2, #0
    3006:	d0e1      	beq.n	2fcc <nrfx_gpiote_output_configure+0x54>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    3008:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
                                      p_task_config->init_val);
    300c:	78ad      	ldrb	r5, [r5, #2]
    300e:	f423 1399 	bic.w	r3, r3, #1253376	; 0x132000
    3012:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3016:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    301a:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    301e:	0223      	lsls	r3, r4, #8
    3020:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    3024:	0412      	lsls	r2, r2, #16
    3026:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    302a:	ea43 030e 	orr.w	r3, r3, lr
    302e:	4313      	orrs	r3, r2
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    3030:	052a      	lsls	r2, r5, #20
    3032:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3036:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    303a:	4313      	orrs	r3, r2
    303c:	f040 0020 	orr.w	r0, r0, #32
    3040:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3044:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    3048:	e7c0      	b.n	2fcc <nrfx_gpiote_output_configure+0x54>
{
    304a:	4803      	ldr	r0, [pc, #12]	; (3058 <nrfx_gpiote_output_configure+0xe0>)
    304c:	e7bf      	b.n	2fce <nrfx_gpiote_output_configure+0x56>
    304e:	bf00      	nop
    3050:	20000010 	.word	0x20000010
    3054:	0bad0000 	.word	0x0bad0000
    3058:	0bad0004 	.word	0x0bad0004

0000305c <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    305c:	4b01      	ldr	r3, [pc, #4]	; (3064 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    305e:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    3062:	4770      	bx	lr
    3064:	20000010 	.word	0x20000010

00003068 <nrfx_gpiote_channel_get>:
{
    3068:	b508      	push	{r3, lr}
    306a:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    306c:	f7ff fe66 	bl	2d3c <pin_in_use_by_te>
    3070:	b138      	cbz	r0, 3082 <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3072:	4b05      	ldr	r3, [pc, #20]	; (3088 <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    3074:	4805      	ldr	r0, [pc, #20]	; (308c <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3076:	3208      	adds	r2, #8
    3078:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    307c:	0b5b      	lsrs	r3, r3, #13
    307e:	700b      	strb	r3, [r1, #0]
}
    3080:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3082:	4803      	ldr	r0, [pc, #12]	; (3090 <nrfx_gpiote_channel_get+0x28>)
    3084:	e7fc      	b.n	3080 <nrfx_gpiote_channel_get+0x18>
    3086:	bf00      	nop
    3088:	20000010 	.word	0x20000010
    308c:	0bad0000 	.word	0x0bad0000
    3090:	0bad0004 	.word	0x0bad0004

00003094 <nrfx_gpiote_init>:
{
    3094:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    3096:	4c0f      	ldr	r4, [pc, #60]	; (30d4 <nrfx_gpiote_init+0x40>)
    3098:	f894 5078 	ldrb.w	r5, [r4, #120]	; 0x78
    309c:	b9bd      	cbnz	r5, 30ce <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    309e:	2260      	movs	r2, #96	; 0x60
    30a0:	4629      	mov	r1, r5
    30a2:	f104 0010 	add.w	r0, r4, #16
    30a6:	f002 ff72 	bl	5f8e <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    30aa:	2006      	movs	r0, #6
    30ac:	f7fd ff92 	bl	fd4 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    30b0:	4b09      	ldr	r3, [pc, #36]	; (30d8 <nrfx_gpiote_init+0x44>)
    return err_code;
    30b2:	480a      	ldr	r0, [pc, #40]	; (30dc <nrfx_gpiote_init+0x48>)
    30b4:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    30b8:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    30bc:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    30c0:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    30c4:	2301      	movs	r3, #1
    30c6:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    30ca:	6763      	str	r3, [r4, #116]	; 0x74
}
    30cc:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    30ce:	4804      	ldr	r0, [pc, #16]	; (30e0 <nrfx_gpiote_init+0x4c>)
    30d0:	e7fc      	b.n	30cc <nrfx_gpiote_init+0x38>
    30d2:	bf00      	nop
    30d4:	20000010 	.word	0x20000010
    30d8:	40006000 	.word	0x40006000
    30dc:	0bad0000 	.word	0x0bad0000
    30e0:	0bad0005 	.word	0x0bad0005

000030e4 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    30e4:	4b03      	ldr	r3, [pc, #12]	; (30f4 <nrfx_gpiote_is_init+0x10>)
    30e6:	f893 0078 	ldrb.w	r0, [r3, #120]	; 0x78
}
    30ea:	3800      	subs	r0, #0
    30ec:	bf18      	it	ne
    30ee:	2001      	movne	r0, #1
    30f0:	4770      	bx	lr
    30f2:	bf00      	nop
    30f4:	20000010 	.word	0x20000010

000030f8 <nrfx_gpiote_channel_free>:
{
    30f8:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    30fa:	4801      	ldr	r0, [pc, #4]	; (3100 <nrfx_gpiote_channel_free+0x8>)
    30fc:	f7ff bd48 	b.w	2b90 <nrfx_flag32_free>
    3100:	20000080 	.word	0x20000080

00003104 <nrfx_gpiote_channel_alloc>:
{
    3104:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    3106:	4801      	ldr	r0, [pc, #4]	; (310c <nrfx_gpiote_channel_alloc+0x8>)
    3108:	f7ff bd22 	b.w	2b50 <nrfx_flag32_alloc>
    310c:	20000080 	.word	0x20000080

00003110 <nrfx_gpiote_trigger_enable>:
{
    3110:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3112:	4604      	mov	r4, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3114:	f7ff fe12 	bl	2d3c <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3118:	f104 0208 	add.w	r2, r4, #8
    311c:	4b1e      	ldr	r3, [pc, #120]	; (3198 <nrfx_gpiote_trigger_enable+0x88>)
    311e:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3122:	b1e8      	cbz	r0, 3160 <nrfx_gpiote_trigger_enable+0x50>
    3124:	f013 0502 	ands.w	r5, r3, #2
    3128:	d11a      	bne.n	3160 <nrfx_gpiote_trigger_enable+0x50>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    312a:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    312c:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    312e:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    3132:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    3136:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    313a:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    313e:	6005      	str	r5, [r0, #0]
    3140:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    3142:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3146:	f040 0001 	orr.w	r0, r0, #1
    314a:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    314e:	b129      	cbz	r1, 315c <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    3150:	2201      	movs	r2, #1
    3152:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    3156:	4a11      	ldr	r2, [pc, #68]	; (319c <nrfx_gpiote_trigger_enable+0x8c>)
    3158:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    315c:	b003      	add	sp, #12
    315e:	bd30      	pop	{r4, r5, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3160:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    3164:	2b04      	cmp	r3, #4
    3166:	d012      	beq.n	318e <nrfx_gpiote_trigger_enable+0x7e>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    3168:	2b05      	cmp	r3, #5
    316a:	d012      	beq.n	3192 <nrfx_gpiote_trigger_enable+0x82>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    316c:	a801      	add	r0, sp, #4
    316e:	9401      	str	r4, [sp, #4]
    3170:	f7ff fdd6 	bl	2d20 <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3174:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    3176:	f8d0 1510 	ldr.w	r1, [r0, #1296]	; 0x510
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    317a:	40d9      	lsrs	r1, r3
    317c:	f001 0101 	and.w	r1, r1, #1
    3180:	3102      	adds	r1, #2
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    3182:	4620      	mov	r0, r4
}
    3184:	b003      	add	sp, #12
    3186:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    318a:	f003 ba85 	b.w	6698 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    318e:	2103      	movs	r1, #3
    3190:	e7f7      	b.n	3182 <nrfx_gpiote_trigger_enable+0x72>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    3192:	2102      	movs	r1, #2
    3194:	e7f5      	b.n	3182 <nrfx_gpiote_trigger_enable+0x72>
    3196:	bf00      	nop
    3198:	20000010 	.word	0x20000010
    319c:	40006000 	.word	0x40006000

000031a0 <nrfx_gpiote_trigger_disable>:
{
    31a0:	b508      	push	{r3, lr}
    31a2:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    31a4:	f7ff fdca 	bl	2d3c <pin_in_use_by_te>
    31a8:	b1c0      	cbz	r0, 31dc <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    31aa:	f102 0108 	add.w	r1, r2, #8
    31ae:	4b0e      	ldr	r3, [pc, #56]	; (31e8 <nrfx_gpiote_trigger_disable+0x48>)
    31b0:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    31b4:	0799      	lsls	r1, r3, #30
    31b6:	d411      	bmi.n	31dc <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    31b8:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    31ba:	2201      	movs	r2, #1
    31bc:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    31be:	009b      	lsls	r3, r3, #2
    31c0:	490a      	ldr	r1, [pc, #40]	; (31ec <nrfx_gpiote_trigger_disable+0x4c>)
    31c2:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    31c6:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    31ca:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    31ce:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    31d2:	f022 0203 	bic.w	r2, r2, #3
    31d6:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    31da:	bd08      	pop	{r3, pc}
    31dc:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    31e0:	2100      	movs	r1, #0
    31e2:	4610      	mov	r0, r2
    31e4:	f003 ba58 	b.w	6698 <nrf_gpio_cfg_sense_set>
    31e8:	20000010 	.word	0x20000010
    31ec:	40006000 	.word	0x40006000

000031f0 <nrfx_gpiote_pin_uninit>:
{
    31f0:	b513      	push	{r0, r1, r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    31f2:	4b0e      	ldr	r3, [pc, #56]	; (322c <nrfx_gpiote_pin_uninit+0x3c>)
    31f4:	f100 0208 	add.w	r2, r0, #8
{
    31f8:	4604      	mov	r4, r0
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    31fa:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    31fe:	07db      	lsls	r3, r3, #31
    3200:	d511      	bpl.n	3226 <nrfx_gpiote_pin_uninit+0x36>
    nrfx_gpiote_trigger_disable(pin);
    3202:	f7ff ffcd 	bl	31a0 <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    3206:	4620      	mov	r0, r4
    3208:	f7ff fdec 	bl	2de4 <pin_handler_trigger_uninit>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    320c:	a801      	add	r0, sp, #4
    320e:	9401      	str	r4, [sp, #4]
    3210:	f7ff fd86 	bl	2d20 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    3214:	9b01      	ldr	r3, [sp, #4]
    3216:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    321a:	2202      	movs	r2, #2
    321c:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
    nrf_gpio_cfg(
    3220:	4803      	ldr	r0, [pc, #12]	; (3230 <nrfx_gpiote_pin_uninit+0x40>)
}
    3222:	b002      	add	sp, #8
    3224:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3226:	4803      	ldr	r0, [pc, #12]	; (3234 <nrfx_gpiote_pin_uninit+0x44>)
    3228:	e7fb      	b.n	3222 <nrfx_gpiote_pin_uninit+0x32>
    322a:	bf00      	nop
    322c:	20000010 	.word	0x20000010
    3230:	0bad0000 	.word	0x0bad0000
    3234:	0bad0004 	.word	0x0bad0004

00003238 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    3238:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    323c:	4b68      	ldr	r3, [pc, #416]	; (33e0 <nrfx_gpiote_irq_handler+0x1a8>)
    return p_reg->INTENSET & mask;
    323e:	4869      	ldr	r0, [pc, #420]	; (33e4 <nrfx_gpiote_irq_handler+0x1ac>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3240:	4969      	ldr	r1, [pc, #420]	; (33e8 <nrfx_gpiote_irq_handler+0x1b0>)
    uint32_t status = 0;
    3242:	2600      	movs	r6, #0
{
    3244:	b087      	sub	sp, #28
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    3246:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3248:	4634      	mov	r4, r6
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    324a:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    324c:	b135      	cbz	r5, 325c <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    324e:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    3252:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3254:	bf1e      	ittt	ne
    3256:	601c      	strne	r4, [r3, #0]
    3258:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    325a:	4316      	orrne	r6, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    325c:	3304      	adds	r3, #4
    325e:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    3260:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3264:	d1f1      	bne.n	324a <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3266:	f8df 917c 	ldr.w	r9, [pc, #380]	; 33e4 <nrfx_gpiote_irq_handler+0x1ac>
    326a:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    326e:	2b00      	cmp	r3, #0
    3270:	f000 8099 	beq.w	33a6 <nrfx_gpiote_irq_handler+0x16e>
        *p_masks = gpio_regs[i]->LATCH;
    3274:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    3278:	f8d3 2520 	ldr.w	r2, [r3, #1312]	; 0x520
    327c:	9204      	str	r2, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    327e:	f8c3 2520 	str.w	r2, [r3, #1312]	; 0x520
        *p_masks = gpio_regs[i]->LATCH;
    3282:	f8d3 2820 	ldr.w	r2, [r3, #2080]	; 0x820
    3286:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    3288:	f8c3 2820 	str.w	r2, [r3, #2080]	; 0x820
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    328c:	f04f 0800 	mov.w	r8, #0
            while (latch[i])
    3290:	f10d 0a10 	add.w	sl, sp, #16
    3294:	ea4f 1348 	mov.w	r3, r8, lsl #5
    3298:	9300      	str	r3, [sp, #0]
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    329a:	f04f 0b01 	mov.w	fp, #1
    329e:	e049      	b.n	3334 <nrfx_gpiote_irq_handler+0xfc>
                pin += 32 * i;
    32a0:	9b00      	ldr	r3, [sp, #0]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    32a2:	4a52      	ldr	r2, [pc, #328]	; (33ec <nrfx_gpiote_irq_handler+0x1b4>)
                uint32_t pin = NRF_CTZ(latch[i]);
    32a4:	fa94 f4a4 	rbit	r4, r4
    32a8:	fab4 f484 	clz	r4, r4
                pin += 32 * i;
    32ac:	441c      	add	r4, r3
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    32ae:	08e0      	lsrs	r0, r4, #3
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    32b0:	f104 0308 	add.w	r3, r4, #8
    32b4:	9403      	str	r4, [sp, #12]
    32b6:	f832 7013 	ldrh.w	r7, [r2, r3, lsl #1]
    p_mask8[byte_idx] &= ~(1 << bit);
    32ba:	f81a 3000 	ldrb.w	r3, [sl, r0]
    bit = BITMASK_RELBIT_GET(bit);
    32be:	f004 0207 	and.w	r2, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    32c2:	fa0b f202 	lsl.w	r2, fp, r2
    32c6:	ea23 0302 	bic.w	r3, r3, r2
    32ca:	f80a 3000 	strb.w	r3, [sl, r0]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    32ce:	a803      	add	r0, sp, #12
    32d0:	f7ff fd26 	bl	2d20 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    32d4:	9b03      	ldr	r3, [sp, #12]
    32d6:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    32da:	08b9      	lsrs	r1, r7, #2
    32dc:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    32e0:	f3c7 0582 	ubfx	r5, r7, #2, #3
    if (is_level(trigger))
    32e4:	074a      	lsls	r2, r1, #29
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    32e6:	462f      	mov	r7, r5
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    32e8:	f3c3 4301 	ubfx	r3, r3, #16, #2
    if (is_level(trigger))
    32ec:	d52c      	bpl.n	3348 <nrfx_gpiote_irq_handler+0x110>
        call_handler(pin, trigger);
    32ee:	4620      	mov	r0, r4
    32f0:	4639      	mov	r1, r7
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    32f2:	b2dd      	uxtb	r5, r3
    32f4:	f7ff fd2c 	bl	2d50 <call_handler>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    32f8:	a803      	add	r0, sp, #12
    32fa:	9403      	str	r4, [sp, #12]
    32fc:	f7ff fd10 	bl	2d20 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3300:	9b03      	ldr	r3, [sp, #12]
    3302:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3306:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
        if (nrf_gpio_pin_sense_get(pin) == sense)
    330a:	f3c3 4301 	ubfx	r3, r3, #16, #2
    330e:	429d      	cmp	r5, r3
    3310:	d107      	bne.n	3322 <nrfx_gpiote_irq_handler+0xea>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3312:	2100      	movs	r1, #0
    3314:	4620      	mov	r0, r4
    3316:	f003 f9bf 	bl	6698 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    331a:	4629      	mov	r1, r5
    331c:	4620      	mov	r0, r4
    331e:	f003 f9bb 	bl	6698 <nrf_gpio_cfg_sense_set>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3322:	a803      	add	r0, sp, #12
    3324:	9403      	str	r4, [sp, #12]
    3326:	f7ff fcfb 	bl	2d20 <nrf_gpio_pin_port_decode>
    reg->LATCH = (1 << pin_number);
    332a:	9b03      	ldr	r3, [sp, #12]
    332c:	fa0b f303 	lsl.w	r3, fp, r3
    3330:	f8c0 3520 	str.w	r3, [r0, #1312]	; 0x520
            while (latch[i])
    3334:	f85a 4028 	ldr.w	r4, [sl, r8, lsl #2]
    3338:	2c00      	cmp	r4, #0
    333a:	d1b1      	bne.n	32a0 <nrfx_gpiote_irq_handler+0x68>
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    333c:	f1b8 0f00 	cmp.w	r8, #0
    3340:	d11d      	bne.n	337e <nrfx_gpiote_irq_handler+0x146>
    3342:	f04f 0801 	mov.w	r8, #1
    3346:	e7a5      	b.n	3294 <nrfx_gpiote_irq_handler+0x5c>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    3348:	2b02      	cmp	r3, #2
    334a:	d10c      	bne.n	3366 <nrfx_gpiote_irq_handler+0x12e>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    334c:	2103      	movs	r1, #3
    334e:	4620      	mov	r0, r4
    3350:	f003 f9a2 	bl	6698 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    3354:	f005 0305 	and.w	r3, r5, #5
    3358:	2b01      	cmp	r3, #1
    335a:	d1e2      	bne.n	3322 <nrfx_gpiote_irq_handler+0xea>
            call_handler(pin, trigger);
    335c:	4639      	mov	r1, r7
    335e:	4620      	mov	r0, r4
    3360:	f7ff fcf6 	bl	2d50 <call_handler>
    3364:	e7dd      	b.n	3322 <nrfx_gpiote_irq_handler+0xea>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    3366:	2102      	movs	r1, #2
    3368:	4620      	mov	r0, r4
    336a:	9301      	str	r3, [sp, #4]
    336c:	f003 f994 	bl	6698 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    3370:	2d03      	cmp	r5, #3
    3372:	d0f3      	beq.n	335c <nrfx_gpiote_irq_handler+0x124>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    3374:	9b01      	ldr	r3, [sp, #4]
    3376:	2b03      	cmp	r3, #3
    3378:	d1d3      	bne.n	3322 <nrfx_gpiote_irq_handler+0xea>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    337a:	2d02      	cmp	r5, #2
    337c:	e7ed      	b.n	335a <nrfx_gpiote_irq_handler+0x122>
        *p_masks = gpio_regs[i]->LATCH;
    337e:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3382:	f8c9 417c 	str.w	r4, [r9, #380]	; 0x17c
    3386:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
    338a:	4919      	ldr	r1, [pc, #100]	; (33f0 <nrfx_gpiote_irq_handler+0x1b8>)
    338c:	f8d2 3520 	ldr.w	r3, [r2, #1312]	; 0x520
    3390:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    3392:	f8c2 3520 	str.w	r3, [r2, #1312]	; 0x520
        *p_masks = gpio_regs[i]->LATCH;
    3396:	f8d1 2520 	ldr.w	r2, [r1, #1312]	; 0x520
    339a:	9205      	str	r2, [sp, #20]
        if (latch[port_idx])
    339c:	4313      	orrs	r3, r2
        gpio_regs[i]->LATCH = *p_masks;
    339e:	f8c1 2520 	str.w	r2, [r1, #1312]	; 0x520
    33a2:	f47f af73 	bne.w	328c <nrfx_gpiote_irq_handler+0x54>
        mask &= ~NRFX_BIT(ch);
    33a6:	2401      	movs	r4, #1
    while (mask)
    33a8:	b916      	cbnz	r6, 33b0 <nrfx_gpiote_irq_handler+0x178>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    33aa:	b007      	add	sp, #28
    33ac:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t ch = NRF_CTZ(mask);
    33b0:	fa96 f3a6 	rbit	r3, r6
    33b4:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    33b8:	fa04 f203 	lsl.w	r2, r4, r3
    33bc:	009b      	lsls	r3, r3, #2
    33be:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    33c2:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    33c6:	ea26 0602 	bic.w	r6, r6, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    33ca:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    33ce:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    33d2:	f3c0 2005 	ubfx	r0, r0, #8, #6
    33d6:	f3c1 4101 	ubfx	r1, r1, #16, #2
    33da:	f7ff fcb9 	bl	2d50 <call_handler>
    33de:	e7e3      	b.n	33a8 <nrfx_gpiote_irq_handler+0x170>
    33e0:	40006100 	.word	0x40006100
    33e4:	40006000 	.word	0x40006000
    33e8:	40006120 	.word	0x40006120
    33ec:	20000010 	.word	0x20000010
    33f0:	50000300 	.word	0x50000300

000033f4 <nvmc_word_write>:
    33f4:	4a04      	ldr	r2, [pc, #16]	; (3408 <nvmc_word_write+0x14>)
    33f6:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
{
#if defined(NRF9160_XXAA)
    while (!nrf_nvmc_write_ready_check(NRF_NVMC))
    {}
#else
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    33fa:	07db      	lsls	r3, r3, #31
    33fc:	d5fb      	bpl.n	33f6 <nvmc_word_write+0x2>
    {}
#endif

    *(volatile uint32_t *)addr = value;
    33fe:	6001      	str	r1, [r0, #0]
  __ASM volatile ("dmb 0xF":::"memory");
    3400:	f3bf 8f5f 	dmb	sy
    __DMB();
}
    3404:	4770      	bx	lr
    3406:	bf00      	nop
    3408:	4001e000 	.word	0x4001e000

0000340c <nrfx_nvmc_page_erase>:
NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk)
    return p_reg->INFO.CODEPAGESIZE;
#else
    return p_reg->CODEPAGESIZE;
    340c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    3410:	691a      	ldr	r2, [r3, #16]
    return !(addr % flash_page_size_get());
    3412:	fbb0 f3f2 	udiv	r3, r0, r2
    3416:	fb02 0313 	mls	r3, r2, r3, r0

nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
    NRFX_ASSERT(is_valid_address(addr, false));

    if (!is_page_aligned_check(addr))
    341a:	b973      	cbnz	r3, 343a <nrfx_nvmc_page_erase+0x2e>
#endif

NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
                                         nrf_nvmc_mode_t mode)
{
    p_reg->CONFIG = (uint32_t)mode;
    341c:	4b08      	ldr	r3, [pc, #32]	; (3440 <nrfx_nvmc_page_erase+0x34>)
    341e:	2202      	movs	r2, #2
    3420:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    else
    {
        p_reg->ERASEPCR1 = page_addr;
    }
#elif defined(NRF52_SERIES)
    p_reg->ERASEPAGE = page_addr;
    3424:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    3428:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
        return NRFX_ERROR_INVALID_ADDR;
    }

    nvmc_erase_mode_set();
    nrf_nvmc_page_erase_start(NRF_NVMC, addr);
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    342c:	07d2      	lsls	r2, r2, #31
    342e:	d5fb      	bpl.n	3428 <nrfx_nvmc_page_erase+0x1c>
    p_reg->CONFIG = (uint32_t)mode;
    3430:	2200      	movs	r2, #0
    {}
    nvmc_readonly_mode_set();

    return NRFX_SUCCESS;
    3432:	4804      	ldr	r0, [pc, #16]	; (3444 <nrfx_nvmc_page_erase+0x38>)
    3434:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    3438:	4770      	bx	lr
        return NRFX_ERROR_INVALID_ADDR;
    343a:	4803      	ldr	r0, [pc, #12]	; (3448 <nrfx_nvmc_page_erase+0x3c>)
}
    343c:	4770      	bx	lr
    343e:	bf00      	nop
    3440:	4001e000 	.word	0x4001e000
    3444:	0bad0000 	.word	0x0bad0000
    3448:	0bad000a 	.word	0x0bad000a

0000344c <nrfx_nvmc_word_write>:

    nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
}

void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
    344c:	b510      	push	{r4, lr}
    344e:	4c05      	ldr	r4, [pc, #20]	; (3464 <nrfx_nvmc_word_write+0x18>)
    3450:	2301      	movs	r3, #1
    3452:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504
    NRFX_ASSERT(is_valid_address(addr, true));
    NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));

    nvmc_write_mode_set();

    nvmc_word_write(addr, value);
    3456:	f7ff ffcd 	bl	33f4 <nvmc_word_write>
    345a:	2300      	movs	r3, #0
    345c:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504

    nvmc_readonly_mode_set();
}
    3460:	bd10      	pop	{r4, pc}
    3462:	bf00      	nop
    3464:	4001e000 	.word	0x4001e000

00003468 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    3468:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    346a:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    346e:	095b      	lsrs	r3, r3, #5
        case 0: return NRF_P0;
    3470:	2b01      	cmp	r3, #1
    *p_pin = pin_number & 0x1F;
    3472:	6002      	str	r2, [r0, #0]
}
    3474:	4802      	ldr	r0, [pc, #8]	; (3480 <nrf_gpio_pin_port_decode+0x18>)
    3476:	bf18      	it	ne
    3478:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    347c:	4770      	bx	lr
    347e:	bf00      	nop
    3480:	50000300 	.word	0x50000300

00003484 <qspi_xfer>:

static nrfx_err_t qspi_xfer(void *            p_buffer,
                            size_t            length,
                            uint32_t          address,
                            nrfx_qspi_state_t desired_state)
{
    3484:	b570      	push	{r4, r5, r6, lr}
    3486:	f000 4460 	and.w	r4, r0, #3758096384	; 0xe0000000
    NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED);
    NRFX_ASSERT(p_buffer != NULL);

    if (!nrfx_is_in_ram(p_buffer) || !nrfx_is_word_aligned(p_buffer))
    348a:	f1b4 5f00 	cmp.w	r4, #536870912	; 0x20000000
    348e:	d166      	bne.n	355e <qspi_xfer+0xda>
    3490:	0784      	lsls	r4, r0, #30
    3492:	d164      	bne.n	355e <qspi_xfer+0xda>
    {
        return NRFX_ERROR_INVALID_ADDR;
    }

    if ((m_cb.state != NRFX_QSPI_STATE_IDLE) &&
    3494:	4d34      	ldr	r5, [pc, #208]	; (3568 <qspi_xfer+0xe4>)
    3496:	f895 4030 	ldrb.w	r4, [r5, #48]	; 0x30
    349a:	2c01      	cmp	r4, #1
    349c:	d001      	beq.n	34a2 <qspi_xfer+0x1e>
    349e:	429c      	cmp	r4, r3
    34a0:	d15f      	bne.n	3562 <qspi_xfer+0xde>
    {
        return NRFX_ERROR_BUSY;
    }

    bool is_first_buffer = false;
    if (m_cb.handler)
    34a2:	682c      	ldr	r4, [r5, #0]
    34a4:	bb04      	cbnz	r4, 34e8 <qspi_xfer+0x64>
            is_first_buffer = true;
        }
    }

    nrf_qspi_task_t task;
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    34a6:	2b02      	cmp	r3, #2
    34a8:	4b30      	ldr	r3, [pc, #192]	; (356c <qspi_xfer+0xe8>)
NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
                                                 void const    * p_buffer,
                                                 uint32_t        length,
                                                 uint32_t        dest_addr)
{
    p_reg->WRITE.DST = dest_addr;
    34aa:	bf0b      	itete	eq
    34ac:	f8c3 2510 	streq.w	r2, [r3, #1296]	; 0x510
NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
                                                void          * p_buffer,
                                                uint32_t        length,
                                                uint32_t        src_addr)
{
    p_reg->READ.SRC = src_addr;
    34b0:	f8c3 2504 	strne.w	r2, [r3, #1284]	; 0x504
    p_reg->WRITE.SRC = (uint32_t) p_buffer;
    34b4:	f8c3 0514 	streq.w	r0, [r3, #1300]	; 0x514
    p_reg->READ.DST = (uint32_t) p_buffer;
    34b8:	f8c3 0508 	strne.w	r0, [r3, #1288]	; 0x508
    p_reg->WRITE.CNT = length;
    34bc:	bf0b      	itete	eq
    34be:	f8c3 1518 	streq.w	r1, [r3, #1304]	; 0x518
    p_reg->READ.CNT = length;
    34c2:	f8c3 150c 	strne.w	r1, [r3, #1292]	; 0x50c
    {
        nrf_qspi_write_buffer_set(NRF_QSPI, p_buffer, length, address);
        task = NRF_QSPI_TASK_WRITESTART;
    34c6:	2208      	moveq	r2, #8
    }
    else
    {
        nrf_qspi_read_buffer_set(NRF_QSPI, p_buffer, length, address);
        task = NRF_QSPI_TASK_READSTART;
    34c8:	2204      	movne	r2, #4
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    34ca:	2100      	movs	r1, #0
    34cc:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    34d0:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    34d4:	f503 3324 	add.w	r3, r3, #167936	; 0x29000
    34d8:	2201      	movs	r2, #1
    34da:	601a      	str	r2, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    34dc:	4a23      	ldr	r2, [pc, #140]	; (356c <qspi_xfer+0xe8>)
    34de:	f8d2 3100 	ldr.w	r3, [r2, #256]	; 0x100

    if (!m_cb.handler)
    {
        nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
        nrf_qspi_task_trigger(NRF_QSPI, task);
        while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
    34e2:	2b00      	cmp	r3, #0
    34e4:	d0fb      	beq.n	34de <qspi_xfer+0x5a>
    34e6:	e00d      	b.n	3504 <qspi_xfer+0x80>
        if (m_cb.p_buffer_primary)
    34e8:	68ae      	ldr	r6, [r5, #8]
    34ea:	4c20      	ldr	r4, [pc, #128]	; (356c <qspi_xfer+0xe8>)
    34ec:	b166      	cbz	r6, 3508 <qspi_xfer+0x84>
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    34ee:	2b02      	cmp	r3, #2
            m_cb.p_buffer_secondary = p_buffer;
    34f0:	60e8      	str	r0, [r5, #12]
            m_cb.size_secondary     = length;
    34f2:	6169      	str	r1, [r5, #20]
            m_cb.addr_secondary     = address;
    34f4:	61ea      	str	r2, [r5, #28]
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    34f6:	d12b      	bne.n	3550 <qspi_xfer+0xcc>
    p_reg->WRITE.DST = dest_addr;
    34f8:	f8c4 2510 	str.w	r2, [r4, #1296]	; 0x510
    p_reg->WRITE.SRC = (uint32_t) p_buffer;
    34fc:	f8c4 0514 	str.w	r0, [r4, #1300]	; 0x514
    p_reg->WRITE.CNT = length;
    3500:	f8c4 1518 	str.w	r1, [r4, #1304]	; 0x518
        nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
        nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
        nrf_qspi_task_trigger(NRF_QSPI, task);
    }

    return NRFX_SUCCESS;
    3504:	481a      	ldr	r0, [pc, #104]	; (3570 <qspi_xfer+0xec>)
}
    3506:	bd70      	pop	{r4, r5, r6, pc}
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    3508:	2b02      	cmp	r3, #2
            m_cb.state = desired_state;
    350a:	f885 3030 	strb.w	r3, [r5, #48]	; 0x30
        task = NRF_QSPI_TASK_WRITESTART;
    350e:	bf0c      	ite	eq
    3510:	2308      	moveq	r3, #8
        task = NRF_QSPI_TASK_READSTART;
    3512:	2304      	movne	r3, #4
            m_cb.size_primary     = length;
    3514:	6129      	str	r1, [r5, #16]
            m_cb.addr_primary     = address;
    3516:	61aa      	str	r2, [r5, #24]
            m_cb.p_buffer_primary = p_buffer;
    3518:	60a8      	str	r0, [r5, #8]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    351a:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    p_reg->WRITE.DST = dest_addr;
    351e:	bf0b      	itete	eq
    3520:	f8c4 2510 	streq.w	r2, [r4, #1296]	; 0x510
    p_reg->READ.SRC = src_addr;
    3524:	f8c4 2504 	strne.w	r2, [r4, #1284]	; 0x504
    p_reg->WRITE.SRC = (uint32_t) p_buffer;
    3528:	f8c4 0514 	streq.w	r0, [r4, #1300]	; 0x514
    p_reg->READ.DST = (uint32_t) p_buffer;
    352c:	f8c4 0508 	strne.w	r0, [r4, #1288]	; 0x508
    p_reg->WRITE.CNT = length;
    3530:	bf0c      	ite	eq
    3532:	f8c4 1518 	streq.w	r1, [r4, #1304]	; 0x518
    p_reg->READ.CNT = length;
    3536:	f8c4 150c 	strne.w	r1, [r4, #1292]	; 0x50c
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    353a:	490c      	ldr	r1, [pc, #48]	; (356c <qspi_xfer+0xe8>)
    353c:	2200      	movs	r2, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    353e:	f503 3324 	add.w	r3, r3, #167936	; 0x29000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3542:	f8c1 2100 	str.w	r2, [r1, #256]	; 0x100
    p_reg->INTENSET = mask;
    3546:	2201      	movs	r2, #1
    3548:	f8c1 2304 	str.w	r2, [r1, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    354c:	601a      	str	r2, [r3, #0]
}
    354e:	e7d9      	b.n	3504 <qspi_xfer+0x80>
    p_reg->READ.SRC = src_addr;
    3550:	f8c4 2504 	str.w	r2, [r4, #1284]	; 0x504
    p_reg->READ.DST = (uint32_t) p_buffer;
    3554:	f8c4 0508 	str.w	r0, [r4, #1288]	; 0x508
    p_reg->READ.CNT = length;
    3558:	f8c4 150c 	str.w	r1, [r4, #1292]	; 0x50c
    else if (is_first_buffer)
    355c:	e7d2      	b.n	3504 <qspi_xfer+0x80>
        return NRFX_ERROR_INVALID_ADDR;
    355e:	4805      	ldr	r0, [pc, #20]	; (3574 <qspi_xfer+0xf0>)
    3560:	e7d1      	b.n	3506 <qspi_xfer+0x82>
        return NRFX_ERROR_BUSY;
    3562:	4805      	ldr	r0, [pc, #20]	; (3578 <qspi_xfer+0xf4>)
    3564:	e7cf      	b.n	3506 <qspi_xfer+0x82>
    3566:	bf00      	nop
    3568:	20001630 	.word	0x20001630
    356c:	40029000 	.word	0x40029000
    3570:	0bad0000 	.word	0x0bad0000
    3574:	0bad000a 	.word	0x0bad000a
    3578:	0bad000b 	.word	0x0bad000b

0000357c <qspi_ready_wait>:
        nrf_gpio_cfg_default(pins.io3_pin);
    }
}

static nrfx_err_t qspi_ready_wait(void)
{
    357c:	b538      	push	{r3, r4, r5, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    357e:	4d07      	ldr	r5, [pc, #28]	; (359c <qspi_ready_wait+0x20>)
    3580:	2464      	movs	r4, #100	; 0x64
    3582:	f8d5 3100 	ldr.w	r3, [r5, #256]	; 0x100
    bool result;
    NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
    3586:	b933      	cbnz	r3, 3596 <qspi_ready_wait+0x1a>
    3588:	200a      	movs	r0, #10
    358a:	f002 ffef 	bl	656c <nrfx_busy_wait>
    358e:	3c01      	subs	r4, #1
    3590:	d1f7      	bne.n	3582 <qspi_ready_wait+0x6>
                                       QSPI_DEF_WAIT_ATTEMPTS,
                                       QSPI_DEF_WAIT_TIME_US,
                                       result);
    if (!result)
    {
        return NRFX_ERROR_TIMEOUT;
    3592:	4803      	ldr	r0, [pc, #12]	; (35a0 <qspi_ready_wait+0x24>)
    }

    return NRFX_SUCCESS;
}
    3594:	bd38      	pop	{r3, r4, r5, pc}
    return NRFX_SUCCESS;
    3596:	4803      	ldr	r0, [pc, #12]	; (35a4 <qspi_ready_wait+0x28>)
    3598:	e7fc      	b.n	3594 <qspi_ready_wait+0x18>
    359a:	bf00      	nop
    359c:	40029000 	.word	0x40029000
    35a0:	0bad0007 	.word	0x0bad0007
    35a4:	0bad0000 	.word	0x0bad0000

000035a8 <qspi_event_xfer_handle.constprop.0>:
}
#endif

static void qspi_event_xfer_handle(nrfx_qspi_evt_ext_xfer_t * p_xfer)
{
    p_xfer->p_buffer = (uint8_t *)m_cb.p_buffer_primary;
    35a8:	4b08      	ldr	r3, [pc, #32]	; (35cc <qspi_event_xfer_handle.constprop.0+0x24>)
    35aa:	689a      	ldr	r2, [r3, #8]
    35ac:	625a      	str	r2, [r3, #36]	; 0x24
    p_xfer->size     = m_cb.size_primary;
    35ae:	691a      	ldr	r2, [r3, #16]
    35b0:	629a      	str	r2, [r3, #40]	; 0x28
    p_xfer->addr     = m_cb.addr_primary;
    35b2:	699a      	ldr	r2, [r3, #24]
    35b4:	62da      	str	r2, [r3, #44]	; 0x2c
    if (m_cb.p_buffer_secondary)
    35b6:	68da      	ldr	r2, [r3, #12]
    {
        m_cb.p_buffer_primary = m_cb.p_buffer_secondary;
    35b8:	609a      	str	r2, [r3, #8]
    if (m_cb.p_buffer_secondary)
    35ba:	b132      	cbz	r2, 35ca <qspi_event_xfer_handle.constprop.0+0x22>
        m_cb.size_primary     = m_cb.size_secondary;
    35bc:	695a      	ldr	r2, [r3, #20]
    35be:	611a      	str	r2, [r3, #16]
        m_cb.addr_primary     = m_cb.addr_secondary;
    35c0:	69da      	ldr	r2, [r3, #28]
    35c2:	619a      	str	r2, [r3, #24]

        m_cb.p_buffer_secondary = NULL;
    35c4:	2200      	movs	r2, #0
    35c6:	60da      	str	r2, [r3, #12]
    35c8:	4770      	bx	lr
    }
    else
    {
        m_cb.p_buffer_primary = NULL;
    }
}
    35ca:	4770      	bx	lr
    35cc:	20001630 	.word	0x20001630

000035d0 <nrf_qspi_cinstrdata_get.constprop.0>:
        default:
            break;
    }
}

NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
    35d0:	b510      	push	{r4, lr}
                                               nrf_qspi_cinstr_len_t length,
                                               void *                p_rx_data)
{
    uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;

    uint32_t reg1 = p_reg->CINSTRDAT1;
    35d2:	4b0e      	ldr	r3, [pc, #56]	; (360c <nrf_qspi_cinstrdata_get.constprop.0+0x3c>)
    uint32_t reg0 = p_reg->CINSTRDAT0;
    switch (length)
    35d4:	3802      	subs	r0, #2
    uint32_t reg1 = p_reg->CINSTRDAT1;
    35d6:	f8d3 263c 	ldr.w	r2, [r3, #1596]	; 0x63c
    uint32_t reg0 = p_reg->CINSTRDAT0;
    35da:	f8d3 3638 	ldr.w	r3, [r3, #1592]	; 0x638
    switch (length)
    35de:	2807      	cmp	r0, #7
    35e0:	d813      	bhi.n	360a <nrf_qspi_cinstrdata_get.constprop.0+0x3a>
    35e2:	e8df f000 	tbb	[pc, r0]
    35e6:	0f11      	.short	0x0f11
    35e8:	080a0b0d 	.word	0x080a0b0d
    35ec:	0406      	.short	0x0406
    {
        case NRF_QSPI_CINSTR_LEN_9B:
            p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
    35ee:	0e10      	lsrs	r0, r2, #24
    35f0:	71c8      	strb	r0, [r1, #7]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_8B:
            p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
    35f2:	0c10      	lsrs	r0, r2, #16
    35f4:	7188      	strb	r0, [r1, #6]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_7B:
            p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
    35f6:	0a10      	lsrs	r0, r2, #8
    35f8:	7148      	strb	r0, [r1, #5]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_6B:
            p_rx_data_8[4] = (uint8_t)(reg1);
    35fa:	710a      	strb	r2, [r1, #4]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_5B:
            p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
    35fc:	0e1a      	lsrs	r2, r3, #24
    35fe:	70ca      	strb	r2, [r1, #3]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_4B:
            p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
    3600:	0c1a      	lsrs	r2, r3, #16
    3602:	708a      	strb	r2, [r1, #2]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_3B:
            p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
    3604:	0a1a      	lsrs	r2, r3, #8
    3606:	704a      	strb	r2, [r1, #1]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_2B:
            p_rx_data_8[0] = (uint8_t)(reg0);
    3608:	700b      	strb	r3, [r1, #0]
            /* Send only opcode. Case to avoid compiler warnings. */
            break;
        default:
            break;
    }
}
    360a:	bd10      	pop	{r4, pc}
    360c:	40029000 	.word	0x40029000

00003610 <nrf_qspi_cinstrdata_set.constprop.0>:
    switch (length)
    3610:	3802      	subs	r0, #2
    3612:	2807      	cmp	r0, #7
    3614:	d81f      	bhi.n	3656 <nrf_qspi_cinstrdata_set.constprop.0+0x46>
    3616:	e8df f000 	tbb	[pc, r0]
    361a:	2729      	.short	0x2729
    361c:	21231125 	.word	0x21231125
    3620:	041f      	.short	0x041f
            reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
    3622:	79cb      	ldrb	r3, [r1, #7]
    3624:	061b      	lsls	r3, r3, #24
            reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
    3626:	798a      	ldrb	r2, [r1, #6]
    3628:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
            reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
    362c:	794a      	ldrb	r2, [r1, #5]
    362e:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
            reg |= ((uint32_t)p_tx_data_8[4]);
    3632:	790a      	ldrb	r2, [r1, #4]
    3634:	4313      	orrs	r3, r2
            p_reg->CINSTRDAT1 = reg;
    3636:	4a0e      	ldr	r2, [pc, #56]	; (3670 <nrf_qspi_cinstrdata_set.constprop.0+0x60>)
    3638:	f8c2 363c 	str.w	r3, [r2, #1596]	; 0x63c
            reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
    363c:	78cb      	ldrb	r3, [r1, #3]
    363e:	061b      	lsls	r3, r3, #24
            reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
    3640:	788a      	ldrb	r2, [r1, #2]
    3642:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
            reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
    3646:	784a      	ldrb	r2, [r1, #1]
    3648:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
            reg |= ((uint32_t)p_tx_data_8[0]);
    364c:	780a      	ldrb	r2, [r1, #0]
    364e:	4313      	orrs	r3, r2
            p_reg->CINSTRDAT0 = reg;
    3650:	4a07      	ldr	r2, [pc, #28]	; (3670 <nrf_qspi_cinstrdata_set.constprop.0+0x60>)
    3652:	f8c2 3638 	str.w	r3, [r2, #1592]	; 0x638
}
    3656:	4770      	bx	lr
    switch (length)
    3658:	2300      	movs	r3, #0
    365a:	e7e4      	b.n	3626 <nrf_qspi_cinstrdata_set.constprop.0+0x16>
    365c:	2300      	movs	r3, #0
    365e:	e7e5      	b.n	362c <nrf_qspi_cinstrdata_set.constprop.0+0x1c>
    3660:	2300      	movs	r3, #0
    3662:	e7e6      	b.n	3632 <nrf_qspi_cinstrdata_set.constprop.0+0x22>
    3664:	2300      	movs	r3, #0
    3666:	e7eb      	b.n	3640 <nrf_qspi_cinstrdata_set.constprop.0+0x30>
    3668:	2300      	movs	r3, #0
    366a:	e7ec      	b.n	3646 <nrf_qspi_cinstrdata_set.constprop.0+0x36>
    366c:	2300      	movs	r3, #0
    366e:	e7ed      	b.n	364c <nrf_qspi_cinstrdata_set.constprop.0+0x3c>
    3670:	40029000 	.word	0x40029000

00003674 <nrfx_qspi_init>:
{
    3674:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    if (m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED)
    3676:	4e6b      	ldr	r6, [pc, #428]	; (3824 <nrfx_qspi_init+0x1b0>)
    3678:	f896 3030 	ldrb.w	r3, [r6, #48]	; 0x30
{
    367c:	4604      	mov	r4, r0
    367e:	4615      	mov	r5, r2
    if (m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED)
    3680:	2b00      	cmp	r3, #0
    3682:	f040 80ca 	bne.w	381a <nrfx_qspi_init+0x1a6>
    if (p_config->skip_gpio_cfg && p_config->skip_psel_cfg)
    3686:	7cc2      	ldrb	r2, [r0, #19]
    3688:	b11a      	cbz	r2, 3692 <nrfx_qspi_init+0x1e>
    368a:	7d03      	ldrb	r3, [r0, #20]
    368c:	2b00      	cmp	r3, #0
    368e:	f040 8084 	bne.w	379a <nrfx_qspi_init+0x126>
    if ((p_config->pins.sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
    3692:	7923      	ldrb	r3, [r4, #4]
    3694:	2bff      	cmp	r3, #255	; 0xff
    3696:	f000 80c3 	beq.w	3820 <nrfx_qspi_init+0x1ac>
    369a:	7960      	ldrb	r0, [r4, #5]
    369c:	28ff      	cmp	r0, #255	; 0xff
    369e:	f000 80bf 	beq.w	3820 <nrfx_qspi_init+0x1ac>
        (p_config->pins.csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
    36a2:	79a0      	ldrb	r0, [r4, #6]
    36a4:	28ff      	cmp	r0, #255	; 0xff
    36a6:	f000 80bb 	beq.w	3820 <nrfx_qspi_init+0x1ac>
        (p_config->pins.io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
    36aa:	79e0      	ldrb	r0, [r4, #7]
    36ac:	28ff      	cmp	r0, #255	; 0xff
    36ae:	f000 80b7 	beq.w	3820 <nrfx_qspi_init+0x1ac>
    if (!p_config->skip_gpio_cfg)
    36b2:	2a00      	cmp	r2, #0
    36b4:	d142      	bne.n	373c <nrfx_qspi_init+0xc8>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    36b6:	a801      	add	r0, sp, #4
        QSPI_PIN_INIT(p_config->pins.sck_pin);
    36b8:	9301      	str	r3, [sp, #4]
    36ba:	f7ff fed5 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    36be:	9b01      	ldr	r3, [sp, #4]
    36c0:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    36c4:	f240 3702 	movw	r7, #770	; 0x302
    36c8:	f840 7023 	str.w	r7, [r0, r3, lsl #2]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    36cc:	a801      	add	r0, sp, #4
        QSPI_PIN_INIT(p_config->pins.csn_pin);
    36ce:	7963      	ldrb	r3, [r4, #5]
    36d0:	9301      	str	r3, [sp, #4]
    36d2:	f7ff fec9 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    36d6:	9b01      	ldr	r3, [sp, #4]
    36d8:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    36dc:	f840 7023 	str.w	r7, [r0, r3, lsl #2]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    36e0:	a801      	add	r0, sp, #4
        QSPI_PIN_INIT(p_config->pins.io0_pin);
    36e2:	79a3      	ldrb	r3, [r4, #6]
    36e4:	9301      	str	r3, [sp, #4]
    36e6:	f7ff febf 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    36ea:	9b01      	ldr	r3, [sp, #4]
    36ec:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    36f0:	f840 7023 	str.w	r7, [r0, r3, lsl #2]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    36f4:	a801      	add	r0, sp, #4
        QSPI_PIN_INIT(p_config->pins.io1_pin);
    36f6:	79e3      	ldrb	r3, [r4, #7]
    36f8:	9301      	str	r3, [sp, #4]
    36fa:	f7ff feb5 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    36fe:	9b01      	ldr	r3, [sp, #4]
    3700:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3704:	f840 7023 	str.w	r7, [r0, r3, lsl #2]
        if (p_config->pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    3708:	7a23      	ldrb	r3, [r4, #8]
    370a:	2bff      	cmp	r3, #255	; 0xff
    370c:	d008      	beq.n	3720 <nrfx_qspi_init+0xac>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    370e:	a801      	add	r0, sp, #4
            QSPI_PIN_INIT(p_config->pins.io2_pin);
    3710:	9301      	str	r3, [sp, #4]
    3712:	f7ff fea9 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    3716:	9b01      	ldr	r3, [sp, #4]
    3718:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    371c:	f840 7023 	str.w	r7, [r0, r3, lsl #2]
        if (p_config->pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    3720:	7a63      	ldrb	r3, [r4, #9]
    3722:	2bff      	cmp	r3, #255	; 0xff
    3724:	d00a      	beq.n	373c <nrfx_qspi_init+0xc8>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3726:	a801      	add	r0, sp, #4
            QSPI_PIN_INIT(p_config->pins.io3_pin);
    3728:	9301      	str	r3, [sp, #4]
    372a:	f7ff fe9d 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    372e:	9b01      	ldr	r3, [sp, #4]
    3730:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3734:	f240 3202 	movw	r2, #770	; 0x302
    3738:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
    if (!p_config->skip_psel_cfg)
    373c:	7d23      	ldrb	r3, [r4, #20]
    373e:	bb63      	cbnz	r3, 379a <nrfx_qspi_init+0x126>
    p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
    3740:	7923      	ldrb	r3, [r4, #4]
    3742:	2bff      	cmp	r3, #255	; 0xff
    3744:	bf18      	it	ne
    3746:	461a      	movne	r2, r3
    3748:	4b37      	ldr	r3, [pc, #220]	; (3828 <nrfx_qspi_init+0x1b4>)
    374a:	bf08      	it	eq
    374c:	f04f 32ff 	moveq.w	r2, #4294967295
    3750:	f8c3 2524 	str.w	r2, [r3, #1316]	; 0x524
    p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
    3754:	7962      	ldrb	r2, [r4, #5]
    3756:	2aff      	cmp	r2, #255	; 0xff
    3758:	bf08      	it	eq
    375a:	f04f 32ff 	moveq.w	r2, #4294967295
    375e:	f8c3 2528 	str.w	r2, [r3, #1320]	; 0x528
    p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
    3762:	79a2      	ldrb	r2, [r4, #6]
    3764:	2aff      	cmp	r2, #255	; 0xff
    3766:	bf08      	it	eq
    3768:	f04f 32ff 	moveq.w	r2, #4294967295
    376c:	f8c3 2530 	str.w	r2, [r3, #1328]	; 0x530
    p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
    3770:	79e2      	ldrb	r2, [r4, #7]
    3772:	2aff      	cmp	r2, #255	; 0xff
    3774:	bf08      	it	eq
    3776:	f04f 32ff 	moveq.w	r2, #4294967295
    377a:	f8c3 2534 	str.w	r2, [r3, #1332]	; 0x534
    p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
    377e:	7a22      	ldrb	r2, [r4, #8]
    3780:	2aff      	cmp	r2, #255	; 0xff
    3782:	bf08      	it	eq
    3784:	f04f 32ff 	moveq.w	r2, #4294967295
    3788:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
    378c:	7a62      	ldrb	r2, [r4, #9]
    378e:	2aff      	cmp	r2, #255	; 0xff
    3790:	bf08      	it	eq
    3792:	f04f 32ff 	moveq.w	r2, #4294967295
    3796:	f8c3 253c 	str.w	r2, [r3, #1340]	; 0x53c
    p_reg->XIPOFFSET = xip_offset;
    379a:	4a23      	ldr	r2, [pc, #140]	; (3828 <nrfx_qspi_init+0x1b4>)
    nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset);
    379c:	6823      	ldr	r3, [r4, #0]
    379e:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
    config |= ((uint32_t)p_config->addrmode)   << QSPI_IFCONFIG0_ADDRMODE_Pos;
    37a2:	7b23      	ldrb	r3, [r4, #12]
    config |= ((uint32_t)p_config->writeoc)    << QSPI_IFCONFIG0_WRITEOC_Pos;
    37a4:	7ae7      	ldrb	r7, [r4, #11]
    uint32_t config = p_config->readoc;
    37a6:	7aa0      	ldrb	r0, [r4, #10]
    config |= ((uint32_t)p_config->addrmode)   << QSPI_IFCONFIG0_ADDRMODE_Pos;
    37a8:	019b      	lsls	r3, r3, #6
    37aa:	ea43 03c7 	orr.w	r3, r3, r7, lsl #3
    37ae:	4303      	orrs	r3, r0
    config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
    37b0:	7b60      	ldrb	r0, [r4, #13]
    37b2:	ea43 13c0 	orr.w	r3, r3, r0, lsl #7
    p_reg->IFCONFIG0 = config;
    37b6:	f8c2 3544 	str.w	r3, [r2, #1348]	; 0x544
    uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
    37ba:	f8d2 0600 	ldr.w	r0, [r2, #1536]	; 0x600
    config |= p_config->sck_delay;
    37be:	7ba3      	ldrb	r3, [r4, #14]
    uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
    37c0:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    37c4:	f020 00ff 	bic.w	r0, r0, #255	; 0xff
    config |= p_config->sck_delay;
    37c8:	4303      	orrs	r3, r0
    config |= (p_config->dpmen ? 1U : 0U)      << QSPI_IFCONFIG1_DPMEN_Pos;
    37ca:	7be0      	ldrb	r0, [r4, #15]
    37cc:	ea43 6300 	orr.w	r3, r3, r0, lsl #24
    config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
    37d0:	7c20      	ldrb	r0, [r4, #16]
    37d2:	ea43 6340 	orr.w	r3, r3, r0, lsl #25
    config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
    37d6:	7c60      	ldrb	r0, [r4, #17]
    37d8:	ea43 7300 	orr.w	r3, r3, r0, lsl #28
    p_reg->IFCONFIG1 = config;
    37dc:	f8c2 3600 	str.w	r3, [r2, #1536]	; 0x600
    m_cb.skip_gpio_cfg = p_config->skip_gpio_cfg;
    37e0:	7ce3      	ldrb	r3, [r4, #19]
    37e2:	f886 3031 	strb.w	r3, [r6, #49]	; 0x31
    p_reg->INTENCLR = mask;
    37e6:	2301      	movs	r3, #1
    m_cb.p_context = p_context;
    37e8:	e9c6 1500 	strd	r1, r5, [r6]
    37ec:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    if (handler)
    37f0:	b111      	cbz	r1, 37f8 <nrfx_qspi_init+0x184>
        NRFX_IRQ_ENABLE(QSPI_IRQn);
    37f2:	2029      	movs	r0, #41	; 0x29
    37f4:	f7fd fbee 	bl	fd4 <arch_irq_enable>
    p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
    37f8:	4b0b      	ldr	r3, [pc, #44]	; (3828 <nrfx_qspi_init+0x1b4>)
    m_cb.state = NRFX_QSPI_STATE_IDLE;
    37fa:	2201      	movs	r2, #1
    m_cb.p_buffer_primary = NULL;
    37fc:	2100      	movs	r1, #0
    m_cb.p_buffer_secondary = NULL;
    37fe:	e9c6 1102 	strd	r1, r1, [r6, #8]
    m_cb.state = NRFX_QSPI_STATE_IDLE;
    3802:	f886 2030 	strb.w	r2, [r6, #48]	; 0x30
    3806:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    380a:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    380e:	601a      	str	r2, [r3, #0]
}
    3810:	b003      	add	sp, #12
    3812:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
    return qspi_ready_wait();
    3816:	f7ff beb1 	b.w	357c <qspi_ready_wait>
        return NRFX_ERROR_INVALID_STATE;
    381a:	4804      	ldr	r0, [pc, #16]	; (382c <nrfx_qspi_init+0x1b8>)
}
    381c:	b003      	add	sp, #12
    381e:	bdf0      	pop	{r4, r5, r6, r7, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3820:	4803      	ldr	r0, [pc, #12]	; (3830 <nrfx_qspi_init+0x1bc>)
    3822:	e7fb      	b.n	381c <nrfx_qspi_init+0x1a8>
    3824:	20001630 	.word	0x20001630
    3828:	40029000 	.word	0x40029000
    382c:	0bad0005 	.word	0x0bad0005
    3830:	0bad0004 	.word	0x0bad0004

00003834 <nrfx_qspi_cinstr_xfer>:
{
    3834:	b570      	push	{r4, r5, r6, lr}
    3836:	4614      	mov	r4, r2
    if (m_cb.state != NRFX_QSPI_STATE_IDLE)
    3838:	4a19      	ldr	r2, [pc, #100]	; (38a0 <nrfx_qspi_cinstr_xfer+0x6c>)
    383a:	f892 2030 	ldrb.w	r2, [r2, #48]	; 0x30
    383e:	2a01      	cmp	r2, #1
{
    3840:	4605      	mov	r5, r0
    if (m_cb.state != NRFX_QSPI_STATE_IDLE)
    3842:	d12b      	bne.n	389c <nrfx_qspi_cinstr_xfer+0x68>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3844:	4e17      	ldr	r6, [pc, #92]	; (38a4 <nrfx_qspi_cinstr_xfer+0x70>)
    3846:	2200      	movs	r2, #0
    3848:	f8c6 2100 	str.w	r2, [r6, #256]	; 0x100
    if (p_tx_buffer)
    384c:	b111      	cbz	r1, 3854 <nrfx_qspi_cinstr_xfer+0x20>
        nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer);
    384e:	7840      	ldrb	r0, [r0, #1]
    3850:	f7ff fede 	bl	3610 <nrf_qspi_cinstrdata_set.constprop.0>
    p_reg->INTENCLR = mask;
    3854:	2301      	movs	r3, #1
    3856:	f8c6 3308 	str.w	r3, [r6, #776]	; 0x308
NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type *                p_reg,
                                                      nrf_qspi_cinstr_conf_t const * p_config)
{
    p_reg->CINSTRCONF = (((uint32_t)p_config->opcode    << QSPI_CINSTRCONF_OPCODE_Pos) |
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
                         ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
    385a:	78ab      	ldrb	r3, [r5, #2]
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
    385c:	786a      	ldrb	r2, [r5, #1]
                         ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
    385e:	031b      	lsls	r3, r3, #12
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
    3860:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
    p_reg->CINSTRCONF = (((uint32_t)p_config->opcode    << QSPI_CINSTRCONF_OPCODE_Pos) |
    3864:	782a      	ldrb	r2, [r5, #0]
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
    3866:	4313      	orrs	r3, r2
                         ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
    3868:	78ea      	ldrb	r2, [r5, #3]
                         ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
    386a:	ea43 3342 	orr.w	r3, r3, r2, lsl #13
                         ((uint32_t)p_config->wipwait   << QSPI_CINSTRCONF_WIPWAIT_Pos) |
    386e:	792a      	ldrb	r2, [r5, #4]
                         ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
    3870:	ea43 3382 	orr.w	r3, r3, r2, lsl #14
                         ((uint32_t)p_config->wren      << QSPI_CINSTRCONF_WREN_Pos));
    3874:	796a      	ldrb	r2, [r5, #5]
                         ((uint32_t)p_config->wipwait   << QSPI_CINSTRCONF_WIPWAIT_Pos) |
    3876:	ea43 33c2 	orr.w	r3, r3, r2, lsl #15
    p_reg->CINSTRCONF = (((uint32_t)p_config->opcode    << QSPI_CINSTRCONF_OPCODE_Pos) |
    387a:	f8c6 3634 	str.w	r3, [r6, #1588]	; 0x634
    if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
    387e:	f7ff fe7d 	bl	357c <qspi_ready_wait>
    3882:	4b09      	ldr	r3, [pc, #36]	; (38a8 <nrfx_qspi_cinstr_xfer+0x74>)
    3884:	4298      	cmp	r0, r3
    3886:	d008      	beq.n	389a <nrfx_qspi_cinstr_xfer+0x66>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3888:	2300      	movs	r3, #0
    388a:	f8c6 3100 	str.w	r3, [r6, #256]	; 0x100
    if (p_rx_buffer)
    388e:	b11c      	cbz	r4, 3898 <nrfx_qspi_cinstr_xfer+0x64>
        nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer);
    3890:	7868      	ldrb	r0, [r5, #1]
    3892:	4621      	mov	r1, r4
    3894:	f7ff fe9c 	bl	35d0 <nrf_qspi_cinstrdata_get.constprop.0>
        return NRFX_ERROR_BUSY;
    3898:	4804      	ldr	r0, [pc, #16]	; (38ac <nrfx_qspi_cinstr_xfer+0x78>)
}
    389a:	bd70      	pop	{r4, r5, r6, pc}
        return NRFX_ERROR_BUSY;
    389c:	4804      	ldr	r0, [pc, #16]	; (38b0 <nrfx_qspi_cinstr_xfer+0x7c>)
    389e:	e7fc      	b.n	389a <nrfx_qspi_cinstr_xfer+0x66>
    38a0:	20001630 	.word	0x20001630
    38a4:	40029000 	.word	0x40029000
    38a8:	0bad0007 	.word	0x0bad0007
    38ac:	0bad0000 	.word	0x0bad0000
    38b0:	0bad000b 	.word	0x0bad000b

000038b4 <nrfx_qspi_mem_busy_check>:
{
    38b4:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_qspi_cinstr_conf_t const config = {
    38b6:	4a0d      	ldr	r2, [pc, #52]	; (38ec <nrfx_qspi_mem_busy_check+0x38>)
    38b8:	9202      	str	r2, [sp, #8]
    ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
    38ba:	f10d 0207 	add.w	r2, sp, #7
    uint8_t status_value = 0;
    38be:	2300      	movs	r3, #0
    ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
    38c0:	4611      	mov	r1, r2
    38c2:	a802      	add	r0, sp, #8
    uint8_t status_value = 0;
    38c4:	f88d 3007 	strb.w	r3, [sp, #7]
    nrf_qspi_cinstr_conf_t const config = {
    38c8:	f8ad 300c 	strh.w	r3, [sp, #12]
    ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
    38cc:	f7ff ffb2 	bl	3834 <nrfx_qspi_cinstr_xfer>
    if (ret_code != NRFX_SUCCESS)
    38d0:	4b07      	ldr	r3, [pc, #28]	; (38f0 <nrfx_qspi_mem_busy_check+0x3c>)
    38d2:	4298      	cmp	r0, r3
    38d4:	d106      	bne.n	38e4 <nrfx_qspi_mem_busy_check+0x30>
    if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00)
    38d6:	f89d 3007 	ldrb.w	r3, [sp, #7]
        return NRFX_ERROR_BUSY;
    38da:	f013 0f01 	tst.w	r3, #1
    38de:	4b05      	ldr	r3, [pc, #20]	; (38f4 <nrfx_qspi_mem_busy_check+0x40>)
    38e0:	bf18      	it	ne
    38e2:	4618      	movne	r0, r3
}
    38e4:	b005      	add	sp, #20
    38e6:	f85d fb04 	ldr.w	pc, [sp], #4
    38ea:	bf00      	nop
    38ec:	01000205 	.word	0x01000205
    38f0:	0bad0000 	.word	0x0bad0000
    38f4:	0bad000b 	.word	0x0bad000b

000038f8 <nrfx_qspi_uninit>:
{
    38f8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    NRFX_IRQ_DISABLE(QSPI_IRQn);
    38fc:	2029      	movs	r0, #41	; 0x29
    38fe:	f7fd fb77 	bl	ff0 <arch_irq_disable>
                         (QSPI_CINSTRCONF_LFEN_Msk));
}

NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
{
    return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
    3902:	4b24      	ldr	r3, [pc, #144]	; (3994 <nrfx_qspi_uninit+0x9c>)
    if (!m_cb.skip_gpio_cfg)
    3904:	4d24      	ldr	r5, [pc, #144]	; (3998 <nrfx_qspi_uninit+0xa0>)
    3906:	f8d3 2634 	ldr.w	r2, [r3, #1588]	; 0x634
    390a:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
    if (nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI))
    390e:	f5b2 3f80 	cmp.w	r2, #65536	; 0x10000
                                                              bool                  finalize)
{
    uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
    mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);

    p_reg->CINSTRCONF = mask;
    3912:	bf04      	itt	eq
    3914:	4a21      	ldreq	r2, [pc, #132]	; (399c <nrfx_qspi_uninit+0xa4>)
    3916:	f8c3 2634 	streq.w	r2, [r3, #1588]	; 0x634
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    391a:	f04f 5180 	mov.w	r1, #268435456	; 0x10000000
    p_reg->INTENCLR = mask;
    391e:	2201      	movs	r2, #1
    3920:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3924:	611a      	str	r2, [r3, #16]
            if (var1 == 0x08)
    3926:	f8d1 1130 	ldr.w	r1, [r1, #304]	; 0x130
    392a:	2908      	cmp	r1, #8
        *(volatile uint32_t *)0x40029054ul = 1ul;
    392c:	bf08      	it	eq
    392e:	655a      	streq	r2, [r3, #84]	; 0x54
    p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
    3930:	4b18      	ldr	r3, [pc, #96]	; (3994 <nrfx_qspi_uninit+0x9c>)
    3932:	2200      	movs	r2, #0
    3934:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3938:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    if (!m_cb.skip_gpio_cfg)
    393c:	f895 2031 	ldrb.w	r2, [r5, #49]	; 0x31
    3940:	bb1a      	cbnz	r2, 398a <nrfx_qspi_uninit+0x92>
    p_pins->sck_pin = (uint8_t)p_reg->PSEL.SCK;
    3942:	f8d3 0524 	ldr.w	r0, [r3, #1316]	; 0x524
    p_pins->csn_pin = (uint8_t)p_reg->PSEL.CSN;
    3946:	f8d3 8528 	ldr.w	r8, [r3, #1320]	; 0x528
    p_pins->io0_pin = (uint8_t)p_reg->PSEL.IO0;
    394a:	f8d3 7530 	ldr.w	r7, [r3, #1328]	; 0x530
    p_pins->io1_pin = (uint8_t)p_reg->PSEL.IO1;
    394e:	f8d3 6534 	ldr.w	r6, [r3, #1332]	; 0x534
    p_pins->io2_pin = (uint8_t)p_reg->PSEL.IO2;
    3952:	f8d3 4538 	ldr.w	r4, [r3, #1336]	; 0x538
    p_pins->io3_pin = (uint8_t)p_reg->PSEL.IO3;
    3956:	f8d3 153c 	ldr.w	r1, [r3, #1340]	; 0x53c
    nrf_gpio_cfg_default(pins.sck_pin);
    395a:	b2c0      	uxtb	r0, r0
    395c:	f002 feb9 	bl	66d2 <nrf_gpio_cfg_default>
    nrf_gpio_cfg_default(pins.csn_pin);
    3960:	fa5f f088 	uxtb.w	r0, r8
    3964:	f002 feb5 	bl	66d2 <nrf_gpio_cfg_default>
    nrf_gpio_cfg_default(pins.io0_pin);
    3968:	b2f8      	uxtb	r0, r7
    396a:	f002 feb2 	bl	66d2 <nrf_gpio_cfg_default>
    nrf_gpio_cfg_default(pins.io1_pin);
    396e:	b2f0      	uxtb	r0, r6
    3970:	f002 feaf 	bl	66d2 <nrf_gpio_cfg_default>
    if (pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    3974:	b2e0      	uxtb	r0, r4
    3976:	28ff      	cmp	r0, #255	; 0xff
    3978:	b2c9      	uxtb	r1, r1
    397a:	d001      	beq.n	3980 <nrfx_qspi_uninit+0x88>
        nrf_gpio_cfg_default(pins.io2_pin);
    397c:	f002 fea9 	bl	66d2 <nrf_gpio_cfg_default>
    if (pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    3980:	29ff      	cmp	r1, #255	; 0xff
    3982:	d002      	beq.n	398a <nrfx_qspi_uninit+0x92>
        nrf_gpio_cfg_default(pins.io3_pin);
    3984:	4608      	mov	r0, r1
    3986:	f002 fea4 	bl	66d2 <nrf_gpio_cfg_default>
    m_cb.state = NRFX_QSPI_STATE_UNINITIALIZED;
    398a:	2300      	movs	r3, #0
    398c:	f885 3030 	strb.w	r3, [r5, #48]	; 0x30
}
    3990:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3994:	40029000 	.word	0x40029000
    3998:	20001630 	.word	0x20001630
    399c:	00030100 	.word	0x00030100

000039a0 <nrfx_qspi_erase>:
    if (!nrfx_is_word_aligned((void const *)start_address))
    39a0:	078b      	lsls	r3, r1, #30
    39a2:	d121      	bne.n	39e8 <nrfx_qspi_erase+0x48>
    if (m_cb.handler && m_cb.state != NRFX_QSPI_STATE_IDLE)
    39a4:	4a12      	ldr	r2, [pc, #72]	; (39f0 <nrfx_qspi_erase+0x50>)
    39a6:	6813      	ldr	r3, [r2, #0]
    39a8:	b11b      	cbz	r3, 39b2 <nrfx_qspi_erase+0x12>
    39aa:	f892 3030 	ldrb.w	r3, [r2, #48]	; 0x30
    39ae:	2b01      	cmp	r3, #1
    39b0:	d11c      	bne.n	39ec <nrfx_qspi_erase+0x4c>
    m_cb.state = NRFX_QSPI_STATE_ERASE;
    39b2:	2304      	movs	r3, #4
    39b4:	f882 3030 	strb.w	r3, [r2, #48]	; 0x30
    p_reg->ERASE.PTR = erase_addr;
    39b8:	4b0e      	ldr	r3, [pc, #56]	; (39f4 <nrfx_qspi_erase+0x54>)
    39ba:	f8c3 151c 	str.w	r1, [r3, #1308]	; 0x51c
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    39be:	2100      	movs	r1, #0
    p_reg->ERASE.LEN = len;
    39c0:	f8c3 0520 	str.w	r0, [r3, #1312]	; 0x520
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    39c4:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    39c8:	2101      	movs	r1, #1
    39ca:	60d9      	str	r1, [r3, #12]
    if (!m_cb.handler)
    39cc:	6810      	ldr	r0, [r2, #0]
    39ce:	b940      	cbnz	r0, 39e2 <nrfx_qspi_erase+0x42>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    39d0:	f8d3 1100 	ldr.w	r1, [r3, #256]	; 0x100
        while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
    39d4:	2900      	cmp	r1, #0
    39d6:	d0fb      	beq.n	39d0 <nrfx_qspi_erase+0x30>
        m_cb.state = NRFX_QSPI_STATE_IDLE;
    39d8:	2301      	movs	r3, #1
    39da:	f882 3030 	strb.w	r3, [r2, #48]	; 0x30
        return NRFX_ERROR_BUSY;
    39de:	4806      	ldr	r0, [pc, #24]	; (39f8 <nrfx_qspi_erase+0x58>)
    39e0:	4770      	bx	lr
    p_reg->INTENSET = mask;
    39e2:	f8c3 1304 	str.w	r1, [r3, #772]	; 0x304
}
    39e6:	e7fa      	b.n	39de <nrfx_qspi_erase+0x3e>
        return NRFX_ERROR_INVALID_ADDR;
    39e8:	4804      	ldr	r0, [pc, #16]	; (39fc <nrfx_qspi_erase+0x5c>)
    39ea:	4770      	bx	lr
        return NRFX_ERROR_BUSY;
    39ec:	4804      	ldr	r0, [pc, #16]	; (3a00 <nrfx_qspi_erase+0x60>)
}
    39ee:	4770      	bx	lr
    39f0:	20001630 	.word	0x20001630
    39f4:	40029000 	.word	0x40029000
    39f8:	0bad0000 	.word	0x0bad0000
    39fc:	0bad000a 	.word	0x0bad000a
    3a00:	0bad000b 	.word	0x0bad000b

00003a04 <nrfx_qspi_irq_handler>:
            break;
    }
}

void nrfx_qspi_irq_handler(void)
{
    3a04:	b510      	push	{r4, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3a06:	4b17      	ldr	r3, [pc, #92]	; (3a64 <nrfx_qspi_irq_handler+0x60>)
    3a08:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    // Catch Event ready interrupts
    if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
    3a0c:	b1e2      	cbz	r2, 3a48 <nrfx_qspi_irq_handler+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3a0e:	2200      	movs	r2, #0
    switch (m_cb.state)
    3a10:	4c15      	ldr	r4, [pc, #84]	; (3a68 <nrfx_qspi_irq_handler+0x64>)
    3a12:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    3a16:	f894 2030 	ldrb.w	r2, [r4, #48]	; 0x30
    3a1a:	2a03      	cmp	r2, #3
    3a1c:	d015      	beq.n	3a4a <nrfx_qspi_irq_handler+0x46>
    3a1e:	2a04      	cmp	r2, #4
    3a20:	d015      	beq.n	3a4e <nrfx_qspi_irq_handler+0x4a>
    3a22:	2a02      	cmp	r2, #2
    3a24:	d104      	bne.n	3a30 <nrfx_qspi_irq_handler+0x2c>
            p_event->type = NRFX_QSPI_EVENT_WRITE_DONE;
    3a26:	2301      	movs	r3, #1
            p_event->type = NRFX_QSPI_EVENT_READ_DONE;
    3a28:	f884 3020 	strb.w	r3, [r4, #32]
            qspi_event_xfer_handle(&p_event->data.xfer);
    3a2c:	f7ff fdbc 	bl	35a8 <qspi_event_xfer_handle.constprop.0>
    {
        nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);

        qspi_extended_event_process(&m_cb.evt_ext);
        if (!m_cb.p_buffer_primary)
    3a30:	68a3      	ldr	r3, [r4, #8]
    3a32:	b913      	cbnz	r3, 3a3a <nrfx_qspi_irq_handler+0x36>
        {
            m_cb.state = NRFX_QSPI_STATE_IDLE;
    3a34:	2301      	movs	r3, #1
    3a36:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
        }

        m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context);
    3a3a:	e9d4 3100 	ldrd	r3, r1, [r4]
    3a3e:	2000      	movs	r0, #0
    3a40:	4798      	blx	r3
        m_cb.evt_ext.type = NRFX_QSPI_EVENT_NONE;
    3a42:	2300      	movs	r3, #0
    3a44:	f884 3020 	strb.w	r3, [r4, #32]
    }
}
    3a48:	bd10      	pop	{r4, pc}
            p_event->type = NRFX_QSPI_EVENT_READ_DONE;
    3a4a:	2302      	movs	r3, #2
    3a4c:	e7ec      	b.n	3a28 <nrfx_qspi_irq_handler+0x24>
            p_event->type = NRFX_QSPI_EVENT_ERASE_DONE;
    3a4e:	2203      	movs	r2, #3
    3a50:	f884 2020 	strb.w	r2, [r4, #32]
    return p_reg->ERASE.PTR;
    3a54:	f8d3 251c 	ldr.w	r2, [r3, #1308]	; 0x51c
    p_erase->addr = nrf_qspi_erase_ptr_get(NRF_QSPI);
    3a58:	6262      	str	r2, [r4, #36]	; 0x24
    return (nrf_qspi_erase_len_t)p_reg->ERASE.LEN;
    3a5a:	f8d3 3520 	ldr.w	r3, [r3, #1312]	; 0x520
    3a5e:	f884 3028 	strb.w	r3, [r4, #40]	; 0x28
}
    3a62:	e7e5      	b.n	3a30 <nrfx_qspi_irq_handler+0x2c>
    3a64:	40029000 	.word	0x40029000
    3a68:	20001630 	.word	0x20001630

00003a6c <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3a6c:	4b0f      	ldr	r3, [pc, #60]	; (3aac <z_sys_init_run_level+0x40>)
{
    3a6e:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3a70:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    3a74:	3001      	adds	r0, #1
    3a76:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    3a7a:	42a6      	cmp	r6, r4
    3a7c:	d800      	bhi.n	3a80 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    3a7e:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    3a80:	e9d4 3500 	ldrd	r3, r5, [r4]
    3a84:	4628      	mov	r0, r5
    3a86:	4798      	blx	r3
		if (dev != NULL) {
    3a88:	b16d      	cbz	r5, 3aa6 <z_sys_init_run_level+0x3a>
			if (rc != 0) {
    3a8a:	b138      	cbz	r0, 3a9c <z_sys_init_run_level+0x30>
				if (rc < 0) {
    3a8c:	2800      	cmp	r0, #0
    3a8e:	bfb8      	it	lt
    3a90:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    3a92:	68eb      	ldr	r3, [r5, #12]
				if (rc > UINT8_MAX) {
    3a94:	28ff      	cmp	r0, #255	; 0xff
    3a96:	bfa8      	it	ge
    3a98:	20ff      	movge	r0, #255	; 0xff
				dev->state->init_res = rc;
    3a9a:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    3a9c:	68ea      	ldr	r2, [r5, #12]
    3a9e:	7853      	ldrb	r3, [r2, #1]
    3aa0:	f043 0301 	orr.w	r3, r3, #1
    3aa4:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3aa6:	3408      	adds	r4, #8
    3aa8:	e7e7      	b.n	3a7a <z_sys_init_run_level+0xe>
    3aaa:	bf00      	nop
    3aac:	00006c38 	.word	0x00006c38

00003ab0 <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    3ab0:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    3ab2:	4b09      	ldr	r3, [pc, #36]	; (3ad8 <bg_thread_main+0x28>)
    3ab4:	2201      	movs	r2, #1

	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    3ab6:	2003      	movs	r0, #3
	z_sys_post_kernel = true;
    3ab8:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    3aba:	f7ff ffd7 	bl	3a6c <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    3abe:	f002 fe56 	bl	676e <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
    3ac2:	2004      	movs	r0, #4
    3ac4:	f7ff ffd2 	bl	3a6c <z_sys_init_run_level>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    3ac8:	f7fc fb1a 	bl	100 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    3acc:	4a03      	ldr	r2, [pc, #12]	; (3adc <bg_thread_main+0x2c>)
    3ace:	7b13      	ldrb	r3, [r2, #12]
    3ad0:	f023 0301 	bic.w	r3, r3, #1
    3ad4:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    3ad6:	bd08      	pop	{r3, pc}
    3ad8:	200017f9 	.word	0x200017f9
    3adc:	20001664 	.word	0x20001664

00003ae0 <z_bss_zero>:
{
    3ae0:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    3ae2:	4803      	ldr	r0, [pc, #12]	; (3af0 <z_bss_zero+0x10>)
    3ae4:	4a03      	ldr	r2, [pc, #12]	; (3af4 <z_bss_zero+0x14>)
    3ae6:	2100      	movs	r1, #0
    3ae8:	1a12      	subs	r2, r2, r0
    3aea:	f002 fe32 	bl	6752 <z_early_memset>
}
    3aee:	bd08      	pop	{r3, pc}
    3af0:	20000100 	.word	0x20000100
    3af4:	200017fc 	.word	0x200017fc

00003af8 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    3af8:	b508      	push	{r3, lr}
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	/* initialize early init calls */
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    3afa:	2000      	movs	r0, #0
    3afc:	f7ff ffb6 	bl	3a6c <z_sys_init_run_level>
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    3b00:	4b18      	ldr	r3, [pc, #96]	; (3b64 <z_cstart+0x6c>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    3b02:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    3b06:	4c18      	ldr	r4, [pc, #96]	; (3b68 <z_cstart+0x70>)
    3b08:	6963      	ldr	r3, [r4, #20]
    3b0a:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    3b0e:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3b10:	2500      	movs	r5, #0
    3b12:	23e0      	movs	r3, #224	; 0xe0
    3b14:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    3b18:	77e5      	strb	r5, [r4, #31]
    3b1a:	7625      	strb	r5, [r4, #24]
    3b1c:	7665      	strb	r5, [r4, #25]
    3b1e:	76a5      	strb	r5, [r4, #26]
    3b20:	f884 5020 	strb.w	r5, [r4, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    3b24:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3b26:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    3b2a:	6263      	str	r3, [r4, #36]	; 0x24
    3b2c:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    3b30:	f7fd fc14 	bl	135c <z_arm_fault_init>
	z_arm_cpu_idle_init();
    3b34:	f7fd fa3e 	bl	fb4 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    3b38:	f04f 33ff 	mov.w	r3, #4294967295
    3b3c:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    3b3e:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    3b40:	f7fd fd08 	bl	1554 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    3b44:	f7fd fc96 	bl	1474 <z_arm_configure_static_mpu_regions>
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    3b48:	f002 fddb 	bl	6702 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_1);
    3b4c:	2001      	movs	r0, #1
    3b4e:	f7ff ff8d 	bl	3a6c <z_sys_init_run_level>
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    3b52:	2002      	movs	r0, #2
    3b54:	f7ff ff8a 	bl	3a6c <z_sys_init_run_level>
#else
#ifdef ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING
	/* Custom ARCH-specific routine to switch to main()
	 * in the case of no multi-threading.
	 */
	ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING(bg_thread_main,
    3b58:	4804      	ldr	r0, [pc, #16]	; (3b6c <z_cstart+0x74>)
    3b5a:	462b      	mov	r3, r5
    3b5c:	462a      	mov	r2, r5
    3b5e:	4629      	mov	r1, r5
    3b60:	f7fd fad8 	bl	1114 <z_arm_switch_to_main_no_multithreading>
    3b64:	20002040 	.word	0x20002040
    3b68:	e000ed00 	.word	0xe000ed00
    3b6c:	00003ab1 	.word	0x00003ab1

00003b70 <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    3b70:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    3b72:	4806      	ldr	r0, [pc, #24]	; (3b8c <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    3b74:	4a06      	ldr	r2, [pc, #24]	; (3b90 <z_data_copy+0x20>)
    3b76:	4907      	ldr	r1, [pc, #28]	; (3b94 <z_data_copy+0x24>)
    3b78:	1a12      	subs	r2, r2, r0
    3b7a:	f002 fdec 	bl	6756 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    3b7e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    3b82:	4a05      	ldr	r2, [pc, #20]	; (3b98 <z_data_copy+0x28>)
    3b84:	4905      	ldr	r1, [pc, #20]	; (3b9c <z_data_copy+0x2c>)
    3b86:	4806      	ldr	r0, [pc, #24]	; (3ba0 <z_data_copy+0x30>)
    3b88:	f002 bde5 	b.w	6756 <z_early_memcpy>
    3b8c:	20000000 	.word	0x20000000
    3b90:	200000fe 	.word	0x200000fe
    3b94:	00006edc 	.word	0x00006edc
    3b98:	00000000 	.word	0x00000000
    3b9c:	00006edc 	.word	0x00006edc
    3ba0:	20000000 	.word	0x20000000

00003ba4 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    3ba4:	4b03      	ldr	r3, [pc, #12]	; (3bb4 <elapsed+0x10>)
    3ba6:	681b      	ldr	r3, [r3, #0]
    3ba8:	b90b      	cbnz	r3, 3bae <elapsed+0xa>
    3baa:	f002 bbce 	b.w	634a <sys_clock_elapsed>
}
    3bae:	2000      	movs	r0, #0
    3bb0:	4770      	bx	lr
    3bb2:	bf00      	nop
    3bb4:	200016d8 	.word	0x200016d8

00003bb8 <next_timeout>:

static int32_t next_timeout(void)
{
    3bb8:	b510      	push	{r4, lr}
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    3bba:	4b09      	ldr	r3, [pc, #36]	; (3be0 <next_timeout+0x28>)
    3bbc:	681c      	ldr	r4, [r3, #0]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3bbe:	429c      	cmp	r4, r3
    3bc0:	d104      	bne.n	3bcc <next_timeout+0x14>
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3bc2:	f7ff ffef 	bl	3ba4 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
		ret = MAX_WAIT;
    3bc6:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    3bca:	bd10      	pop	{r4, pc}
	int32_t ticks_elapsed = elapsed();
    3bcc:	f7ff ffea 	bl	3ba4 <elapsed>
	if ((to == NULL) ||
    3bd0:	2c00      	cmp	r4, #0
    3bd2:	d0f8      	beq.n	3bc6 <next_timeout+0xe>
		ret = MAX(0, to->dticks - ticks_elapsed);
    3bd4:	68e3      	ldr	r3, [r4, #12]
    3bd6:	1a18      	subs	r0, r3, r0
    3bd8:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
	return ret;
    3bdc:	e7f5      	b.n	3bca <next_timeout+0x12>
    3bde:	bf00      	nop
    3be0:	2000008c 	.word	0x2000008c

00003be4 <remove_timeout>:
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3be4:	b148      	cbz	r0, 3bfa <remove_timeout+0x16>
	return (node == list->tail) ? NULL : node->next;
    3be6:	4b09      	ldr	r3, [pc, #36]	; (3c0c <remove_timeout+0x28>)
    3be8:	685b      	ldr	r3, [r3, #4]
    3bea:	4298      	cmp	r0, r3
    3bec:	d005      	beq.n	3bfa <remove_timeout+0x16>
    3bee:	6803      	ldr	r3, [r0, #0]
	if (next(t) != NULL) {
    3bf0:	b11b      	cbz	r3, 3bfa <remove_timeout+0x16>
		next(t)->dticks += t->dticks;
    3bf2:	68da      	ldr	r2, [r3, #12]
    3bf4:	68c1      	ldr	r1, [r0, #12]
    3bf6:	440a      	add	r2, r1
    3bf8:	60da      	str	r2, [r3, #12]
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
	sys_dnode_t *const next = node->next;
    3bfa:	e9d0 3200 	ldrd	r3, r2, [r0]

	prev->next = next;
    3bfe:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    3c00:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    3c02:	2300      	movs	r3, #0
	node->prev = NULL;
    3c04:	e9c0 3300 	strd	r3, r3, [r0]
}
    3c08:	4770      	bx	lr
    3c0a:	bf00      	nop
    3c0c:	2000008c 	.word	0x2000008c

00003c10 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    3c10:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3c14:	4603      	mov	r3, r0
	__asm__ volatile(
    3c16:	f04f 0220 	mov.w	r2, #32
    3c1a:	f3ef 8511 	mrs	r5, BASEPRI
    3c1e:	f382 8812 	msr	BASEPRI_MAX, r2
    3c22:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    3c26:	4e1f      	ldr	r6, [pc, #124]	; (3ca4 <sys_clock_announce+0x94>)
	return list->head == list;
    3c28:	f8df 8080 	ldr.w	r8, [pc, #128]	; 3cac <sys_clock_announce+0x9c>
    3c2c:	f8d8 0000 	ldr.w	r0, [r8]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    3c30:	491d      	ldr	r1, [pc, #116]	; (3ca8 <sys_clock_announce+0x98>)
	announce_remaining = ticks;
    3c32:	6033      	str	r3, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3c34:	4540      	cmp	r0, r8
		curr_tick += dt;
    3c36:	e9d1 2700 	ldrd	r2, r7, [r1]
    3c3a:	d005      	beq.n	3c48 <sys_clock_announce+0x38>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    3c3c:	b120      	cbz	r0, 3c48 <sys_clock_announce+0x38>
    3c3e:	68c4      	ldr	r4, [r0, #12]
    3c40:	429c      	cmp	r4, r3
    3c42:	dd13      	ble.n	3c6c <sys_clock_announce+0x5c>
		key = k_spin_lock(&timeout_lock);
		announce_remaining -= dt;
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    3c44:	1ae4      	subs	r4, r4, r3
    3c46:	60c4      	str	r4, [r0, #12]
	}

	curr_tick += announce_remaining;
    3c48:	189a      	adds	r2, r3, r2
    3c4a:	eb47 77e3 	adc.w	r7, r7, r3, asr #31
	announce_remaining = 0;
    3c4e:	2400      	movs	r4, #0
	curr_tick += announce_remaining;
    3c50:	e9c1 2700 	strd	r2, r7, [r1]
	announce_remaining = 0;
    3c54:	6034      	str	r4, [r6, #0]

	sys_clock_set_timeout(next_timeout(), false);
    3c56:	f7ff ffaf 	bl	3bb8 <next_timeout>
    3c5a:	4621      	mov	r1, r4
    3c5c:	f002 fb74 	bl	6348 <sys_clock_set_timeout>
	__asm__ volatile(
    3c60:	f385 8811 	msr	BASEPRI, r5
    3c64:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    3c68:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		curr_tick += dt;
    3c6c:	18a2      	adds	r2, r4, r2
		t->dticks = 0;
    3c6e:	f04f 0300 	mov.w	r3, #0
		curr_tick += dt;
    3c72:	eb47 77e4 	adc.w	r7, r7, r4, asr #31
		t->dticks = 0;
    3c76:	60c3      	str	r3, [r0, #12]
		curr_tick += dt;
    3c78:	e9c1 2700 	strd	r2, r7, [r1]
		remove_timeout(t);
    3c7c:	f7ff ffb2 	bl	3be4 <remove_timeout>
    3c80:	f385 8811 	msr	BASEPRI, r5
    3c84:	f3bf 8f6f 	isb	sy
		t->fn(t);
    3c88:	6883      	ldr	r3, [r0, #8]
    3c8a:	4798      	blx	r3
	__asm__ volatile(
    3c8c:	f04f 0320 	mov.w	r3, #32
    3c90:	f3ef 8511 	mrs	r5, BASEPRI
    3c94:	f383 8812 	msr	BASEPRI_MAX, r3
    3c98:	f3bf 8f6f 	isb	sy
		announce_remaining -= dt;
    3c9c:	6833      	ldr	r3, [r6, #0]
    3c9e:	1b1b      	subs	r3, r3, r4
    3ca0:	e7c4      	b.n	3c2c <sys_clock_announce+0x1c>
    3ca2:	bf00      	nop
    3ca4:	200016d8 	.word	0x200016d8
    3ca8:	20000120 	.word	0x20000120
    3cac:	2000008c 	.word	0x2000008c

00003cb0 <nrf_cc3xx_platform_init_no_rng>:
    3cb0:	b510      	push	{r4, lr}
    3cb2:	4c0a      	ldr	r4, [pc, #40]	; (3cdc <nrf_cc3xx_platform_init_no_rng+0x2c>)
    3cb4:	6823      	ldr	r3, [r4, #0]
    3cb6:	b11b      	cbz	r3, 3cc0 <nrf_cc3xx_platform_init_no_rng+0x10>
    3cb8:	2301      	movs	r3, #1
    3cba:	6023      	str	r3, [r4, #0]
    3cbc:	2000      	movs	r0, #0
    3cbe:	bd10      	pop	{r4, pc}
    3cc0:	f000 f852 	bl	3d68 <CC_LibInitNoRng>
    3cc4:	2800      	cmp	r0, #0
    3cc6:	d0f7      	beq.n	3cb8 <nrf_cc3xx_platform_init_no_rng+0x8>
    3cc8:	3801      	subs	r0, #1
    3cca:	2806      	cmp	r0, #6
    3ccc:	d803      	bhi.n	3cd6 <nrf_cc3xx_platform_init_no_rng+0x26>
    3cce:	4b04      	ldr	r3, [pc, #16]	; (3ce0 <nrf_cc3xx_platform_init_no_rng+0x30>)
    3cd0:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    3cd4:	bd10      	pop	{r4, pc}
    3cd6:	4803      	ldr	r0, [pc, #12]	; (3ce4 <nrf_cc3xx_platform_init_no_rng+0x34>)
    3cd8:	bd10      	pop	{r4, pc}
    3cda:	bf00      	nop
    3cdc:	200016dc 	.word	0x200016dc
    3ce0:	00006c50 	.word	0x00006c50
    3ce4:	ffff8ffe 	.word	0xffff8ffe

00003ce8 <nrf_cc3xx_platform_abort>:
    3ce8:	f3bf 8f4f 	dsb	sy
    3cec:	4905      	ldr	r1, [pc, #20]	; (3d04 <nrf_cc3xx_platform_abort+0x1c>)
    3cee:	4b06      	ldr	r3, [pc, #24]	; (3d08 <nrf_cc3xx_platform_abort+0x20>)
    3cf0:	68ca      	ldr	r2, [r1, #12]
    3cf2:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3cf6:	4313      	orrs	r3, r2
    3cf8:	60cb      	str	r3, [r1, #12]
    3cfa:	f3bf 8f4f 	dsb	sy
    3cfe:	bf00      	nop
    3d00:	e7fd      	b.n	3cfe <nrf_cc3xx_platform_abort+0x16>
    3d02:	bf00      	nop
    3d04:	e000ed00 	.word	0xe000ed00
    3d08:	05fa0004 	.word	0x05fa0004

00003d0c <CC_PalAbort>:
    3d0c:	b410      	push	{r4}
    3d0e:	4b0a      	ldr	r3, [pc, #40]	; (3d38 <CC_PalAbort+0x2c>)
    3d10:	490a      	ldr	r1, [pc, #40]	; (3d3c <CC_PalAbort+0x30>)
    3d12:	4c0b      	ldr	r4, [pc, #44]	; (3d40 <CC_PalAbort+0x34>)
    3d14:	f04f 32fe 	mov.w	r2, #4278124286	; 0xfefefefe
    3d18:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    3d1c:	6849      	ldr	r1, [r1, #4]
    3d1e:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    3d22:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    3d26:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    3d2a:	2300      	movs	r3, #0
    3d2c:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    3d30:	f85d 4b04 	ldr.w	r4, [sp], #4
    3d34:	4708      	bx	r1
    3d36:	bf00      	nop
    3d38:	5002b000 	.word	0x5002b000
    3d3c:	20000094 	.word	0x20000094
    3d40:	5002a000 	.word	0x5002a000

00003d44 <nrf_cc3xx_platform_set_abort>:
    3d44:	e9d0 1200 	ldrd	r1, r2, [r0]
    3d48:	4b01      	ldr	r3, [pc, #4]	; (3d50 <nrf_cc3xx_platform_set_abort+0xc>)
    3d4a:	e9c3 1200 	strd	r1, r2, [r3]
    3d4e:	4770      	bx	lr
    3d50:	20000094 	.word	0x20000094

00003d54 <mbedtls_platform_zeroize>:
    3d54:	b138      	cbz	r0, 3d66 <mbedtls_platform_zeroize+0x12>
    3d56:	b131      	cbz	r1, 3d66 <mbedtls_platform_zeroize+0x12>
    3d58:	4401      	add	r1, r0
    3d5a:	2200      	movs	r2, #0
    3d5c:	4603      	mov	r3, r0
    3d5e:	3001      	adds	r0, #1
    3d60:	4288      	cmp	r0, r1
    3d62:	701a      	strb	r2, [r3, #0]
    3d64:	d1fa      	bne.n	3d5c <mbedtls_platform_zeroize+0x8>
    3d66:	4770      	bx	lr

00003d68 <CC_LibInitNoRng>:
    3d68:	b538      	push	{r3, r4, r5, lr}
    3d6a:	f000 f82f 	bl	3dcc <CC_HalInit>
    3d6e:	b120      	cbz	r0, 3d7a <CC_LibInitNoRng+0x12>
    3d70:	2403      	movs	r4, #3
    3d72:	f000 f863 	bl	3e3c <CC_PalTerminate>
    3d76:	4620      	mov	r0, r4
    3d78:	bd38      	pop	{r3, r4, r5, pc}
    3d7a:	f000 f831 	bl	3de0 <CC_PalInit>
    3d7e:	b998      	cbnz	r0, 3da8 <CC_LibInitNoRng+0x40>
    3d80:	f000 f8ac 	bl	3edc <CC_PalPowerSaveModeSelect>
    3d84:	b998      	cbnz	r0, 3dae <CC_LibInitNoRng+0x46>
    3d86:	4d0f      	ldr	r5, [pc, #60]	; (3dc4 <CC_LibInitNoRng+0x5c>)
    3d88:	f8d5 3928 	ldr.w	r3, [r5, #2344]	; 0x928
    3d8c:	0e1b      	lsrs	r3, r3, #24
    3d8e:	2bf0      	cmp	r3, #240	; 0xf0
    3d90:	d108      	bne.n	3da4 <CC_LibInitNoRng+0x3c>
    3d92:	f8d5 2a24 	ldr.w	r2, [r5, #2596]	; 0xa24
    3d96:	4b0c      	ldr	r3, [pc, #48]	; (3dc8 <CC_LibInitNoRng+0x60>)
    3d98:	429a      	cmp	r2, r3
    3d9a:	d00a      	beq.n	3db2 <CC_LibInitNoRng+0x4a>
    3d9c:	2407      	movs	r4, #7
    3d9e:	f000 f817 	bl	3dd0 <CC_HalTerminate>
    3da2:	e7e6      	b.n	3d72 <CC_LibInitNoRng+0xa>
    3da4:	2406      	movs	r4, #6
    3da6:	e7fa      	b.n	3d9e <CC_LibInitNoRng+0x36>
    3da8:	2404      	movs	r4, #4
    3daa:	4620      	mov	r0, r4
    3dac:	bd38      	pop	{r3, r4, r5, pc}
    3dae:	2400      	movs	r4, #0
    3db0:	e7f5      	b.n	3d9e <CC_LibInitNoRng+0x36>
    3db2:	2001      	movs	r0, #1
    3db4:	f000 f892 	bl	3edc <CC_PalPowerSaveModeSelect>
    3db8:	4604      	mov	r4, r0
    3dba:	2800      	cmp	r0, #0
    3dbc:	d1f7      	bne.n	3dae <CC_LibInitNoRng+0x46>
    3dbe:	f8c5 0a0c 	str.w	r0, [r5, #2572]	; 0xa0c
    3dc2:	e7d8      	b.n	3d76 <CC_LibInitNoRng+0xe>
    3dc4:	5002b000 	.word	0x5002b000
    3dc8:	20e00000 	.word	0x20e00000

00003dcc <CC_HalInit>:
    3dcc:	2000      	movs	r0, #0
    3dce:	4770      	bx	lr

00003dd0 <CC_HalTerminate>:
    3dd0:	2000      	movs	r0, #0
    3dd2:	4770      	bx	lr

00003dd4 <CC_HalMaskInterrupt>:
    3dd4:	4b01      	ldr	r3, [pc, #4]	; (3ddc <CC_HalMaskInterrupt+0x8>)
    3dd6:	f8c3 0a04 	str.w	r0, [r3, #2564]	; 0xa04
    3dda:	4770      	bx	lr
    3ddc:	5002b000 	.word	0x5002b000

00003de0 <CC_PalInit>:
    3de0:	b510      	push	{r4, lr}
    3de2:	4811      	ldr	r0, [pc, #68]	; (3e28 <CC_PalInit+0x48>)
    3de4:	f000 f848 	bl	3e78 <CC_PalMutexCreate>
    3de8:	b100      	cbz	r0, 3dec <CC_PalInit+0xc>
    3dea:	bd10      	pop	{r4, pc}
    3dec:	480f      	ldr	r0, [pc, #60]	; (3e2c <CC_PalInit+0x4c>)
    3dee:	f000 f843 	bl	3e78 <CC_PalMutexCreate>
    3df2:	2800      	cmp	r0, #0
    3df4:	d1f9      	bne.n	3dea <CC_PalInit+0xa>
    3df6:	4c0e      	ldr	r4, [pc, #56]	; (3e30 <CC_PalInit+0x50>)
    3df8:	4620      	mov	r0, r4
    3dfa:	f000 f83d 	bl	3e78 <CC_PalMutexCreate>
    3dfe:	2800      	cmp	r0, #0
    3e00:	d1f3      	bne.n	3dea <CC_PalInit+0xa>
    3e02:	4b0c      	ldr	r3, [pc, #48]	; (3e34 <CC_PalInit+0x54>)
    3e04:	480c      	ldr	r0, [pc, #48]	; (3e38 <CC_PalInit+0x58>)
    3e06:	601c      	str	r4, [r3, #0]
    3e08:	f000 f836 	bl	3e78 <CC_PalMutexCreate>
    3e0c:	4601      	mov	r1, r0
    3e0e:	2800      	cmp	r0, #0
    3e10:	d1eb      	bne.n	3dea <CC_PalInit+0xa>
    3e12:	f000 f82d 	bl	3e70 <CC_PalDmaInit>
    3e16:	4604      	mov	r4, r0
    3e18:	b108      	cbz	r0, 3e1e <CC_PalInit+0x3e>
    3e1a:	4620      	mov	r0, r4
    3e1c:	bd10      	pop	{r4, pc}
    3e1e:	f000 f83f 	bl	3ea0 <CC_PalPowerSaveModeInit>
    3e22:	4620      	mov	r0, r4
    3e24:	e7fa      	b.n	3e1c <CC_PalInit+0x3c>
    3e26:	bf00      	nop
    3e28:	200000a8 	.word	0x200000a8
    3e2c:	2000009c 	.word	0x2000009c
    3e30:	200000a4 	.word	0x200000a4
    3e34:	200000ac 	.word	0x200000ac
    3e38:	200000a0 	.word	0x200000a0

00003e3c <CC_PalTerminate>:
    3e3c:	b508      	push	{r3, lr}
    3e3e:	4808      	ldr	r0, [pc, #32]	; (3e60 <CC_PalTerminate+0x24>)
    3e40:	f000 f824 	bl	3e8c <CC_PalMutexDestroy>
    3e44:	4807      	ldr	r0, [pc, #28]	; (3e64 <CC_PalTerminate+0x28>)
    3e46:	f000 f821 	bl	3e8c <CC_PalMutexDestroy>
    3e4a:	4807      	ldr	r0, [pc, #28]	; (3e68 <CC_PalTerminate+0x2c>)
    3e4c:	f000 f81e 	bl	3e8c <CC_PalMutexDestroy>
    3e50:	4806      	ldr	r0, [pc, #24]	; (3e6c <CC_PalTerminate+0x30>)
    3e52:	f000 f81b 	bl	3e8c <CC_PalMutexDestroy>
    3e56:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    3e5a:	f000 b80b 	b.w	3e74 <CC_PalDmaTerminate>
    3e5e:	bf00      	nop
    3e60:	200000a8 	.word	0x200000a8
    3e64:	2000009c 	.word	0x2000009c
    3e68:	200000a4 	.word	0x200000a4
    3e6c:	200000a0 	.word	0x200000a0

00003e70 <CC_PalDmaInit>:
    3e70:	2000      	movs	r0, #0
    3e72:	4770      	bx	lr

00003e74 <CC_PalDmaTerminate>:
    3e74:	4770      	bx	lr
    3e76:	bf00      	nop

00003e78 <CC_PalMutexCreate>:
    3e78:	b508      	push	{r3, lr}
    3e7a:	4b03      	ldr	r3, [pc, #12]	; (3e88 <CC_PalMutexCreate+0x10>)
    3e7c:	6802      	ldr	r2, [r0, #0]
    3e7e:	681b      	ldr	r3, [r3, #0]
    3e80:	6810      	ldr	r0, [r2, #0]
    3e82:	4798      	blx	r3
    3e84:	2000      	movs	r0, #0
    3e86:	bd08      	pop	{r3, pc}
    3e88:	200000b8 	.word	0x200000b8

00003e8c <CC_PalMutexDestroy>:
    3e8c:	b508      	push	{r3, lr}
    3e8e:	4b03      	ldr	r3, [pc, #12]	; (3e9c <CC_PalMutexDestroy+0x10>)
    3e90:	6802      	ldr	r2, [r0, #0]
    3e92:	685b      	ldr	r3, [r3, #4]
    3e94:	6810      	ldr	r0, [r2, #0]
    3e96:	4798      	blx	r3
    3e98:	2000      	movs	r0, #0
    3e9a:	bd08      	pop	{r3, pc}
    3e9c:	200000b8 	.word	0x200000b8

00003ea0 <CC_PalPowerSaveModeInit>:
    3ea0:	b570      	push	{r4, r5, r6, lr}
    3ea2:	4c09      	ldr	r4, [pc, #36]	; (3ec8 <CC_PalPowerSaveModeInit+0x28>)
    3ea4:	4d09      	ldr	r5, [pc, #36]	; (3ecc <CC_PalPowerSaveModeInit+0x2c>)
    3ea6:	6920      	ldr	r0, [r4, #16]
    3ea8:	68ab      	ldr	r3, [r5, #8]
    3eaa:	4798      	blx	r3
    3eac:	b118      	cbz	r0, 3eb6 <CC_PalPowerSaveModeInit+0x16>
    3eae:	4b08      	ldr	r3, [pc, #32]	; (3ed0 <CC_PalPowerSaveModeInit+0x30>)
    3eb0:	4808      	ldr	r0, [pc, #32]	; (3ed4 <CC_PalPowerSaveModeInit+0x34>)
    3eb2:	685b      	ldr	r3, [r3, #4]
    3eb4:	4798      	blx	r3
    3eb6:	4a08      	ldr	r2, [pc, #32]	; (3ed8 <CC_PalPowerSaveModeInit+0x38>)
    3eb8:	68eb      	ldr	r3, [r5, #12]
    3eba:	6920      	ldr	r0, [r4, #16]
    3ebc:	2100      	movs	r1, #0
    3ebe:	6011      	str	r1, [r2, #0]
    3ec0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    3ec4:	4718      	bx	r3
    3ec6:	bf00      	nop
    3ec8:	200000c8 	.word	0x200000c8
    3ecc:	200000b8 	.word	0x200000b8
    3ed0:	20000094 	.word	0x20000094
    3ed4:	00006c6c 	.word	0x00006c6c
    3ed8:	200016e0 	.word	0x200016e0

00003edc <CC_PalPowerSaveModeSelect>:
    3edc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3ede:	4d1a      	ldr	r5, [pc, #104]	; (3f48 <CC_PalPowerSaveModeSelect+0x6c>)
    3ee0:	4e1a      	ldr	r6, [pc, #104]	; (3f4c <CC_PalPowerSaveModeSelect+0x70>)
    3ee2:	4604      	mov	r4, r0
    3ee4:	68b2      	ldr	r2, [r6, #8]
    3ee6:	6928      	ldr	r0, [r5, #16]
    3ee8:	4790      	blx	r2
    3eea:	b9e8      	cbnz	r0, 3f28 <CC_PalPowerSaveModeSelect+0x4c>
    3eec:	4f18      	ldr	r7, [pc, #96]	; (3f50 <CC_PalPowerSaveModeSelect+0x74>)
    3eee:	683b      	ldr	r3, [r7, #0]
    3ef0:	b14c      	cbz	r4, 3f06 <CC_PalPowerSaveModeSelect+0x2a>
    3ef2:	b1a3      	cbz	r3, 3f1e <CC_PalPowerSaveModeSelect+0x42>
    3ef4:	2b01      	cmp	r3, #1
    3ef6:	d019      	beq.n	3f2c <CC_PalPowerSaveModeSelect+0x50>
    3ef8:	3b01      	subs	r3, #1
    3efa:	603b      	str	r3, [r7, #0]
    3efc:	6928      	ldr	r0, [r5, #16]
    3efe:	68f3      	ldr	r3, [r6, #12]
    3f00:	4798      	blx	r3
    3f02:	2000      	movs	r0, #0
    3f04:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3f06:	b943      	cbnz	r3, 3f1a <CC_PalPowerSaveModeSelect+0x3e>
    3f08:	4a12      	ldr	r2, [pc, #72]	; (3f54 <CC_PalPowerSaveModeSelect+0x78>)
    3f0a:	2101      	movs	r1, #1
    3f0c:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    3f10:	4911      	ldr	r1, [pc, #68]	; (3f58 <CC_PalPowerSaveModeSelect+0x7c>)
    3f12:	f8d1 2910 	ldr.w	r2, [r1, #2320]	; 0x910
    3f16:	2a00      	cmp	r2, #0
    3f18:	d1fb      	bne.n	3f12 <CC_PalPowerSaveModeSelect+0x36>
    3f1a:	3301      	adds	r3, #1
    3f1c:	603b      	str	r3, [r7, #0]
    3f1e:	68f3      	ldr	r3, [r6, #12]
    3f20:	6928      	ldr	r0, [r5, #16]
    3f22:	4798      	blx	r3
    3f24:	2000      	movs	r0, #0
    3f26:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3f28:	480c      	ldr	r0, [pc, #48]	; (3f5c <CC_PalPowerSaveModeSelect+0x80>)
    3f2a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3f2c:	4a0a      	ldr	r2, [pc, #40]	; (3f58 <CC_PalPowerSaveModeSelect+0x7c>)
    3f2e:	f8d2 3910 	ldr.w	r3, [r2, #2320]	; 0x910
    3f32:	2b00      	cmp	r3, #0
    3f34:	d1fb      	bne.n	3f2e <CC_PalPowerSaveModeSelect+0x52>
    3f36:	4a07      	ldr	r2, [pc, #28]	; (3f54 <CC_PalPowerSaveModeSelect+0x78>)
    3f38:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    3f3c:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    3f40:	f7ff ff48 	bl	3dd4 <CC_HalMaskInterrupt>
    3f44:	683b      	ldr	r3, [r7, #0]
    3f46:	e7d7      	b.n	3ef8 <CC_PalPowerSaveModeSelect+0x1c>
    3f48:	200000c8 	.word	0x200000c8
    3f4c:	200000b8 	.word	0x200000b8
    3f50:	200016e0 	.word	0x200016e0
    3f54:	5002a000 	.word	0x5002a000
    3f58:	5002b000 	.word	0x5002b000
    3f5c:	ffff8fe9 	.word	0xffff8fe9

00003f60 <mutex_free>:
    3f60:	b510      	push	{r4, lr}
    3f62:	4604      	mov	r4, r0
    3f64:	b150      	cbz	r0, 3f7c <mutex_free+0x1c>
    3f66:	6863      	ldr	r3, [r4, #4]
    3f68:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    3f6c:	d005      	beq.n	3f7a <mutex_free+0x1a>
    3f6e:	4a06      	ldr	r2, [pc, #24]	; (3f88 <mutex_free+0x28>)
    3f70:	4293      	cmp	r3, r2
    3f72:	d002      	beq.n	3f7a <mutex_free+0x1a>
    3f74:	2300      	movs	r3, #0
    3f76:	6023      	str	r3, [r4, #0]
    3f78:	6062      	str	r2, [r4, #4]
    3f7a:	bd10      	pop	{r4, pc}
    3f7c:	4b03      	ldr	r3, [pc, #12]	; (3f8c <mutex_free+0x2c>)
    3f7e:	4804      	ldr	r0, [pc, #16]	; (3f90 <mutex_free+0x30>)
    3f80:	685b      	ldr	r3, [r3, #4]
    3f82:	4798      	blx	r3
    3f84:	e7ef      	b.n	3f66 <mutex_free+0x6>
    3f86:	bf00      	nop
    3f88:	a95c5f2c 	.word	0xa95c5f2c
    3f8c:	20000094 	.word	0x20000094
    3f90:	00006c8c 	.word	0x00006c8c

00003f94 <mutex_lock>:
    3f94:	b1c8      	cbz	r0, 3fca <mutex_lock+0x36>
    3f96:	6843      	ldr	r3, [r0, #4]
    3f98:	4a0d      	ldr	r2, [pc, #52]	; (3fd0 <mutex_lock+0x3c>)
    3f9a:	4293      	cmp	r3, r2
    3f9c:	d013      	beq.n	3fc6 <mutex_lock+0x32>
    3f9e:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    3fa2:	d00e      	beq.n	3fc2 <mutex_lock+0x2e>
    3fa4:	2301      	movs	r3, #1
    3fa6:	e850 2f00 	ldrex	r2, [r0]
    3faa:	4619      	mov	r1, r3
    3fac:	e840 1c00 	strex	ip, r1, [r0]
    3fb0:	f09c 0f00 	teq	ip, #0
    3fb4:	d1f7      	bne.n	3fa6 <mutex_lock+0x12>
    3fb6:	2a01      	cmp	r2, #1
    3fb8:	d0f5      	beq.n	3fa6 <mutex_lock+0x12>
    3fba:	f3bf 8f5f 	dmb	sy
    3fbe:	2000      	movs	r0, #0
    3fc0:	4770      	bx	lr
    3fc2:	4804      	ldr	r0, [pc, #16]	; (3fd4 <mutex_lock+0x40>)
    3fc4:	4770      	bx	lr
    3fc6:	4804      	ldr	r0, [pc, #16]	; (3fd8 <mutex_lock+0x44>)
    3fc8:	4770      	bx	lr
    3fca:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    3fce:	4770      	bx	lr
    3fd0:	a95c5f2c 	.word	0xa95c5f2c
    3fd4:	ffff8fe9 	.word	0xffff8fe9
    3fd8:	ffff8fea 	.word	0xffff8fea

00003fdc <mutex_unlock>:
    3fdc:	b180      	cbz	r0, 4000 <mutex_unlock+0x24>
    3fde:	6843      	ldr	r3, [r0, #4]
    3fe0:	4a09      	ldr	r2, [pc, #36]	; (4008 <mutex_unlock+0x2c>)
    3fe2:	4293      	cmp	r3, r2
    3fe4:	d00a      	beq.n	3ffc <mutex_unlock+0x20>
    3fe6:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    3fea:	d005      	beq.n	3ff8 <mutex_unlock+0x1c>
    3fec:	f3bf 8f5f 	dmb	sy
    3ff0:	2300      	movs	r3, #0
    3ff2:	6003      	str	r3, [r0, #0]
    3ff4:	4618      	mov	r0, r3
    3ff6:	4770      	bx	lr
    3ff8:	4804      	ldr	r0, [pc, #16]	; (400c <mutex_unlock+0x30>)
    3ffa:	4770      	bx	lr
    3ffc:	4804      	ldr	r0, [pc, #16]	; (4010 <mutex_unlock+0x34>)
    3ffe:	4770      	bx	lr
    4000:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    4004:	4770      	bx	lr
    4006:	bf00      	nop
    4008:	a95c5f2c 	.word	0xa95c5f2c
    400c:	ffff8fe9 	.word	0xffff8fe9
    4010:	ffff8fea 	.word	0xffff8fea

00004014 <mutex_init>:
    4014:	b510      	push	{r4, lr}
    4016:	4604      	mov	r4, r0
    4018:	b120      	cbz	r0, 4024 <mutex_init+0x10>
    401a:	4b04      	ldr	r3, [pc, #16]	; (402c <mutex_init+0x18>)
    401c:	6063      	str	r3, [r4, #4]
    401e:	2200      	movs	r2, #0
    4020:	6022      	str	r2, [r4, #0]
    4022:	bd10      	pop	{r4, pc}
    4024:	4802      	ldr	r0, [pc, #8]	; (4030 <mutex_init+0x1c>)
    4026:	f7ff fe71 	bl	3d0c <CC_PalAbort>
    402a:	e7f6      	b.n	401a <mutex_init+0x6>
    402c:	3a00003a 	.word	0x3a00003a
    4030:	00006cb4 	.word	0x00006cb4

00004034 <verify_context_ecdsa_verify_secp256r1>:
    4034:	b130      	cbz	r0, 4044 <verify_context_ecdsa_verify_secp256r1+0x10>
    4036:	6802      	ldr	r2, [r0, #0]
    4038:	4b03      	ldr	r3, [pc, #12]	; (4048 <verify_context_ecdsa_verify_secp256r1+0x14>)
    403a:	4804      	ldr	r0, [pc, #16]	; (404c <verify_context_ecdsa_verify_secp256r1+0x18>)
    403c:	429a      	cmp	r2, r3
    403e:	bf08      	it	eq
    4040:	2000      	moveq	r0, #0
    4042:	4770      	bx	lr
    4044:	4802      	ldr	r0, [pc, #8]	; (4050 <verify_context_ecdsa_verify_secp256r1+0x1c>)
    4046:	4770      	bx	lr
    4048:	bbaa55dd 	.word	0xbbaa55dd
    404c:	00f00882 	.word	0x00f00882
    4050:	00f00871 	.word	0x00f00871

00004054 <nrf_cc310_bl_ecdsa_verify_init_secp256r1>:
    4054:	b538      	push	{r3, r4, r5, lr}
    4056:	460d      	mov	r5, r1
    4058:	4604      	mov	r4, r0
    405a:	b1b0      	cbz	r0, 408a <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x36>
    405c:	22a0      	movs	r2, #160	; 0xa0
    405e:	2100      	movs	r1, #0
    4060:	3004      	adds	r0, #4
    4062:	f002 fb9f 	bl	67a4 <SaSi_PalMemSet>
    4066:	b195      	cbz	r5, 408e <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x3a>
    4068:	2208      	movs	r2, #8
    406a:	4629      	mov	r1, r5
    406c:	f104 0064 	add.w	r0, r4, #100	; 0x64
    4070:	f002 fb9e 	bl	67b0 <CRYS_COMMON_ReverseMemcpy32>
    4074:	2208      	movs	r2, #8
    4076:	f105 0120 	add.w	r1, r5, #32
    407a:	f104 0084 	add.w	r0, r4, #132	; 0x84
    407e:	f002 fb97 	bl	67b0 <CRYS_COMMON_ReverseMemcpy32>
    4082:	4b04      	ldr	r3, [pc, #16]	; (4094 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x40>)
    4084:	6023      	str	r3, [r4, #0]
    4086:	2000      	movs	r0, #0
    4088:	bd38      	pop	{r3, r4, r5, pc}
    408a:	4803      	ldr	r0, [pc, #12]	; (4098 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x44>)
    408c:	e7fc      	b.n	4088 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x34>
    408e:	4803      	ldr	r0, [pc, #12]	; (409c <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x48>)
    4090:	e7fa      	b.n	4088 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x34>
    4092:	bf00      	nop
    4094:	bbaa55dd 	.word	0xbbaa55dd
    4098:	00f00871 	.word	0x00f00871
    409c:	00f00883 	.word	0x00f00883

000040a0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1>:
    40a0:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    40a4:	4605      	mov	r5, r0
    40a6:	460e      	mov	r6, r1
    40a8:	4699      	mov	r9, r3
    40aa:	4611      	mov	r1, r2
    40ac:	f7ff ffc2 	bl	4034 <verify_context_ecdsa_verify_secp256r1>
    40b0:	4604      	mov	r4, r0
    40b2:	2800      	cmp	r0, #0
    40b4:	f040 8084 	bne.w	41c0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    40b8:	2e00      	cmp	r6, #0
    40ba:	f000 8085 	beq.w	41c8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x128>
    40be:	2900      	cmp	r1, #0
    40c0:	f000 8084 	beq.w	41cc <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x12c>
    40c4:	f1b9 0f20 	cmp.w	r9, #32
    40c8:	f040 8082 	bne.w	41d0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x130>
    40cc:	f105 0444 	add.w	r4, r5, #68	; 0x44
    40d0:	2208      	movs	r2, #8
    40d2:	f105 0804 	add.w	r8, r5, #4
    40d6:	4620      	mov	r0, r4
    40d8:	f002 fb6a 	bl	67b0 <CRYS_COMMON_ReverseMemcpy32>
    40dc:	f105 0724 	add.w	r7, r5, #36	; 0x24
    40e0:	2208      	movs	r2, #8
    40e2:	4631      	mov	r1, r6
    40e4:	4640      	mov	r0, r8
    40e6:	f002 fb63 	bl	67b0 <CRYS_COMMON_ReverseMemcpy32>
    40ea:	f106 0120 	add.w	r1, r6, #32
    40ee:	2208      	movs	r2, #8
    40f0:	4638      	mov	r0, r7
    40f2:	f002 fb5d 	bl	67b0 <CRYS_COMMON_ReverseMemcpy32>
    40f6:	a902      	add	r1, sp, #8
    40f8:	f44f 7080 	mov.w	r0, #256	; 0x100
    40fc:	f841 9d04 	str.w	r9, [r1, #-4]!
    4100:	f002 fb4a 	bl	6798 <PkaInitAndMutexLock>
    4104:	2800      	cmp	r0, #0
    4106:	d165      	bne.n	41d4 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x134>
    4108:	4a33      	ldr	r2, [pc, #204]	; (41d8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x138>)
    410a:	f44f 7380 	mov.w	r3, #256	; 0x100
    410e:	6013      	str	r3, [r2, #0]
    4110:	2101      	movs	r1, #1
    4112:	6093      	str	r3, [r2, #8]
    4114:	2308      	movs	r3, #8
    4116:	4a31      	ldr	r2, [pc, #196]	; (41dc <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x13c>)
    4118:	f000 fb2e 	bl	4778 <PkaCopyDataIntoPkaReg>
    411c:	2101      	movs	r1, #1
    411e:	4608      	mov	r0, r1
    4120:	2305      	movs	r3, #5
    4122:	4a2f      	ldr	r2, [pc, #188]	; (41e0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x140>)
    4124:	f000 fb28 	bl	4778 <PkaCopyDataIntoPkaReg>
    4128:	2308      	movs	r3, #8
    412a:	4642      	mov	r2, r8
    412c:	2101      	movs	r1, #1
    412e:	201c      	movs	r0, #28
    4130:	f000 fb22 	bl	4778 <PkaCopyDataIntoPkaReg>
    4134:	2308      	movs	r3, #8
    4136:	463a      	mov	r2, r7
    4138:	2101      	movs	r1, #1
    413a:	2003      	movs	r0, #3
    413c:	f000 fb1c 	bl	4778 <PkaCopyDataIntoPkaReg>
    4140:	4622      	mov	r2, r4
    4142:	2308      	movs	r3, #8
    4144:	2101      	movs	r1, #1
    4146:	2002      	movs	r0, #2
    4148:	f000 fb16 	bl	4778 <PkaCopyDataIntoPkaReg>
    414c:	2308      	movs	r3, #8
    414e:	4a25      	ldr	r2, [pc, #148]	; (41e4 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x144>)
    4150:	2101      	movs	r1, #1
    4152:	201a      	movs	r0, #26
    4154:	f000 fb10 	bl	4778 <PkaCopyDataIntoPkaReg>
    4158:	2305      	movs	r3, #5
    415a:	4a23      	ldr	r2, [pc, #140]	; (41e8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x148>)
    415c:	2101      	movs	r1, #1
    415e:	201b      	movs	r0, #27
    4160:	f000 fb0a 	bl	4778 <PkaCopyDataIntoPkaReg>
    4164:	2308      	movs	r3, #8
    4166:	4a21      	ldr	r2, [pc, #132]	; (41ec <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x14c>)
    4168:	2101      	movs	r1, #1
    416a:	2014      	movs	r0, #20
    416c:	f000 fb04 	bl	4778 <PkaCopyDataIntoPkaReg>
    4170:	2308      	movs	r3, #8
    4172:	4a1f      	ldr	r2, [pc, #124]	; (41f0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x150>)
    4174:	2101      	movs	r1, #1
    4176:	2015      	movs	r0, #21
    4178:	f000 fafe 	bl	4778 <PkaCopyDataIntoPkaReg>
    417c:	2308      	movs	r3, #8
    417e:	f105 0264 	add.w	r2, r5, #100	; 0x64
    4182:	2101      	movs	r1, #1
    4184:	2016      	movs	r0, #22
    4186:	f000 faf7 	bl	4778 <PkaCopyDataIntoPkaReg>
    418a:	2308      	movs	r3, #8
    418c:	f105 0284 	add.w	r2, r5, #132	; 0x84
    4190:	2101      	movs	r1, #1
    4192:	2017      	movs	r0, #23
    4194:	f000 faf0 	bl	4778 <PkaCopyDataIntoPkaReg>
    4198:	2308      	movs	r3, #8
    419a:	4a16      	ldr	r2, [pc, #88]	; (41f4 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x154>)
    419c:	2101      	movs	r1, #1
    419e:	200b      	movs	r0, #11
    41a0:	f000 faea 	bl	4778 <PkaCopyDataIntoPkaReg>
    41a4:	f000 fb44 	bl	4830 <PkaEcdsaVerify>
    41a8:	4604      	mov	r4, r0
    41aa:	9801      	ldr	r0, [sp, #4]
    41ac:	f000 fad2 	bl	4754 <PkaFinishAndMutexUnlock>
    41b0:	4b11      	ldr	r3, [pc, #68]	; (41f8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x158>)
    41b2:	2c00      	cmp	r4, #0
    41b4:	bf18      	it	ne
    41b6:	461c      	movne	r4, r3
    41b8:	21a4      	movs	r1, #164	; 0xa4
    41ba:	4628      	mov	r0, r5
    41bc:	f002 faf4 	bl	67a8 <SaSi_PalMemSetZero>
    41c0:	4620      	mov	r0, r4
    41c2:	b003      	add	sp, #12
    41c4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    41c8:	4c0c      	ldr	r4, [pc, #48]	; (41fc <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x15c>)
    41ca:	e7f9      	b.n	41c0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    41cc:	4c0c      	ldr	r4, [pc, #48]	; (4200 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x160>)
    41ce:	e7f7      	b.n	41c0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    41d0:	4c0c      	ldr	r4, [pc, #48]	; (4204 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x164>)
    41d2:	e7f5      	b.n	41c0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    41d4:	4c08      	ldr	r4, [pc, #32]	; (41f8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x158>)
    41d6:	e7ef      	b.n	41b8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x118>
    41d8:	5002b090 	.word	0x5002b090
    41dc:	00006d18 	.word	0x00006d18
    41e0:	00006d90 	.word	0x00006d90
    41e4:	00006cd8 	.word	0x00006cd8
    41e8:	00006d7c 	.word	0x00006d7c
    41ec:	00006d3c 	.word	0x00006d3c
    41f0:	00006d5c 	.word	0x00006d5c
    41f4:	00006cf8 	.word	0x00006cf8
    41f8:	00f00884 	.word	0x00f00884
    41fc:	00f00876 	.word	0x00f00876
    4200:	00f00880 	.word	0x00f00880
    4204:	00f00881 	.word	0x00f00881

00004208 <set_digest_in_hw_sha256>:
    4208:	4b0c      	ldr	r3, [pc, #48]	; (423c <set_digest_in_hw_sha256+0x34>)
    420a:	69c2      	ldr	r2, [r0, #28]
    420c:	601a      	str	r2, [r3, #0]
    420e:	6982      	ldr	r2, [r0, #24]
    4210:	f843 2c04 	str.w	r2, [r3, #-4]
    4214:	6942      	ldr	r2, [r0, #20]
    4216:	f843 2c08 	str.w	r2, [r3, #-8]
    421a:	6902      	ldr	r2, [r0, #16]
    421c:	f843 2c0c 	str.w	r2, [r3, #-12]
    4220:	68c2      	ldr	r2, [r0, #12]
    4222:	f843 2c10 	str.w	r2, [r3, #-16]
    4226:	6882      	ldr	r2, [r0, #8]
    4228:	f843 2c14 	str.w	r2, [r3, #-20]
    422c:	6842      	ldr	r2, [r0, #4]
    422e:	f843 2c18 	str.w	r2, [r3, #-24]
    4232:	6802      	ldr	r2, [r0, #0]
    4234:	f843 2c1c 	str.w	r2, [r3, #-28]
    4238:	4770      	bx	lr
    423a:	bf00      	nop
    423c:	5002b65c 	.word	0x5002b65c

00004240 <read_digest_in_hw_sha256>:
    4240:	4b0c      	ldr	r3, [pc, #48]	; (4274 <read_digest_in_hw_sha256+0x34>)
    4242:	681b      	ldr	r3, [r3, #0]
    4244:	61c3      	str	r3, [r0, #28]
    4246:	4b0c      	ldr	r3, [pc, #48]	; (4278 <read_digest_in_hw_sha256+0x38>)
    4248:	681b      	ldr	r3, [r3, #0]
    424a:	6183      	str	r3, [r0, #24]
    424c:	4b0b      	ldr	r3, [pc, #44]	; (427c <read_digest_in_hw_sha256+0x3c>)
    424e:	681b      	ldr	r3, [r3, #0]
    4250:	6143      	str	r3, [r0, #20]
    4252:	4b0b      	ldr	r3, [pc, #44]	; (4280 <read_digest_in_hw_sha256+0x40>)
    4254:	681b      	ldr	r3, [r3, #0]
    4256:	6103      	str	r3, [r0, #16]
    4258:	4b0a      	ldr	r3, [pc, #40]	; (4284 <read_digest_in_hw_sha256+0x44>)
    425a:	681b      	ldr	r3, [r3, #0]
    425c:	60c3      	str	r3, [r0, #12]
    425e:	4b0a      	ldr	r3, [pc, #40]	; (4288 <read_digest_in_hw_sha256+0x48>)
    4260:	681b      	ldr	r3, [r3, #0]
    4262:	6083      	str	r3, [r0, #8]
    4264:	4b09      	ldr	r3, [pc, #36]	; (428c <read_digest_in_hw_sha256+0x4c>)
    4266:	681b      	ldr	r3, [r3, #0]
    4268:	6043      	str	r3, [r0, #4]
    426a:	4b09      	ldr	r3, [pc, #36]	; (4290 <read_digest_in_hw_sha256+0x50>)
    426c:	681b      	ldr	r3, [r3, #0]
    426e:	6003      	str	r3, [r0, #0]
    4270:	4770      	bx	lr
    4272:	bf00      	nop
    4274:	5002b65c 	.word	0x5002b65c
    4278:	5002b658 	.word	0x5002b658
    427c:	5002b654 	.word	0x5002b654
    4280:	5002b650 	.word	0x5002b650
    4284:	5002b64c 	.word	0x5002b64c
    4288:	5002b648 	.word	0x5002b648
    428c:	5002b644 	.word	0x5002b644
    4290:	5002b640 	.word	0x5002b640

00004294 <verify_context_hash_sha256>:
    4294:	b130      	cbz	r0, 42a4 <verify_context_hash_sha256+0x10>
    4296:	6802      	ldr	r2, [r0, #0]
    4298:	4b03      	ldr	r3, [pc, #12]	; (42a8 <verify_context_hash_sha256+0x14>)
    429a:	4804      	ldr	r0, [pc, #16]	; (42ac <verify_context_hash_sha256+0x18>)
    429c:	429a      	cmp	r2, r3
    429e:	bf08      	it	eq
    42a0:	2000      	moveq	r0, #0
    42a2:	4770      	bx	lr
    42a4:	4802      	ldr	r0, [pc, #8]	; (42b0 <verify_context_hash_sha256+0x1c>)
    42a6:	4770      	bx	lr
    42a8:	bbaa55dd 	.word	0xbbaa55dd
    42ac:	00f00202 	.word	0x00f00202
    42b0:	00f00200 	.word	0x00f00200

000042b4 <nrf_cc310_bl_hash_sha256_init>:
    42b4:	b538      	push	{r3, r4, r5, lr}
    42b6:	4604      	mov	r4, r0
    42b8:	b168      	cbz	r0, 42d6 <nrf_cc310_bl_hash_sha256_init+0x22>
    42ba:	1d05      	adds	r5, r0, #4
    42bc:	2170      	movs	r1, #112	; 0x70
    42be:	4628      	mov	r0, r5
    42c0:	f002 fa72 	bl	67a8 <SaSi_PalMemSetZero>
    42c4:	4628      	mov	r0, r5
    42c6:	2220      	movs	r2, #32
    42c8:	4904      	ldr	r1, [pc, #16]	; (42dc <nrf_cc310_bl_hash_sha256_init+0x28>)
    42ca:	f002 fa69 	bl	67a0 <SaSi_PalMemCopy>
    42ce:	4b04      	ldr	r3, [pc, #16]	; (42e0 <nrf_cc310_bl_hash_sha256_init+0x2c>)
    42d0:	6023      	str	r3, [r4, #0]
    42d2:	2000      	movs	r0, #0
    42d4:	bd38      	pop	{r3, r4, r5, pc}
    42d6:	4803      	ldr	r0, [pc, #12]	; (42e4 <nrf_cc310_bl_hash_sha256_init+0x30>)
    42d8:	e7fc      	b.n	42d4 <nrf_cc310_bl_hash_sha256_init+0x20>
    42da:	bf00      	nop
    42dc:	00006da4 	.word	0x00006da4
    42e0:	bbaa55dd 	.word	0xbbaa55dd
    42e4:	00f00200 	.word	0x00f00200

000042e8 <nrf_cc310_bl_hash_sha256_update>:
    42e8:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    42ec:	4b28      	ldr	r3, [pc, #160]	; (4390 <nrf_cc310_bl_hash_sha256_update+0xa8>)
    42ee:	4604      	mov	r4, r0
    42f0:	460e      	mov	r6, r1
    42f2:	4615      	mov	r5, r2
    42f4:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    42f6:	b085      	sub	sp, #20
    42f8:	466f      	mov	r7, sp
    42fa:	e887 000f 	stmia.w	r7, {r0, r1, r2, r3}
    42fe:	b92d      	cbnz	r5, 430c <nrf_cc310_bl_hash_sha256_update+0x24>
    4300:	f04f 0900 	mov.w	r9, #0
    4304:	4648      	mov	r0, r9
    4306:	b005      	add	sp, #20
    4308:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    430c:	4620      	mov	r0, r4
    430e:	f7ff ffc1 	bl	4294 <verify_context_hash_sha256>
    4312:	4681      	mov	r9, r0
    4314:	2800      	cmp	r0, #0
    4316:	d1f5      	bne.n	4304 <nrf_cc310_bl_hash_sha256_update+0x1c>
    4318:	1d23      	adds	r3, r4, #4
    431a:	9301      	str	r3, [sp, #4]
    431c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    431e:	bba3      	cbnz	r3, 438a <nrf_cc310_bl_hash_sha256_update+0xa2>
    4320:	6f23      	ldr	r3, [r4, #112]	; 0x70
    4322:	b18b      	cbz	r3, 4348 <nrf_cc310_bl_hash_sha256_update+0x60>
    4324:	f1c3 0840 	rsb	r8, r3, #64	; 0x40
    4328:	45a8      	cmp	r8, r5
    432a:	bf28      	it	cs
    432c:	46a8      	movcs	r8, r5
    432e:	f104 0030 	add.w	r0, r4, #48	; 0x30
    4332:	4631      	mov	r1, r6
    4334:	4418      	add	r0, r3
    4336:	4642      	mov	r2, r8
    4338:	f002 fa32 	bl	67a0 <SaSi_PalMemCopy>
    433c:	6f23      	ldr	r3, [r4, #112]	; 0x70
    433e:	4443      	add	r3, r8
    4340:	4446      	add	r6, r8
    4342:	6723      	str	r3, [r4, #112]	; 0x70
    4344:	eba5 0508 	sub.w	r5, r5, r8
    4348:	6f22      	ldr	r2, [r4, #112]	; 0x70
    434a:	2a40      	cmp	r2, #64	; 0x40
    434c:	d106      	bne.n	435c <nrf_cc310_bl_hash_sha256_update+0x74>
    434e:	f104 0130 	add.w	r1, r4, #48	; 0x30
    4352:	4638      	mov	r0, r7
    4354:	f000 fbae 	bl	4ab4 <nrf_cc310_bl_hash_update_internal>
    4358:	2300      	movs	r3, #0
    435a:	6723      	str	r3, [r4, #112]	; 0x70
    435c:	f005 083f 	and.w	r8, r5, #63	; 0x3f
    4360:	f035 053f 	bics.w	r5, r5, #63	; 0x3f
    4364:	d005      	beq.n	4372 <nrf_cc310_bl_hash_sha256_update+0x8a>
    4366:	4631      	mov	r1, r6
    4368:	462a      	mov	r2, r5
    436a:	4638      	mov	r0, r7
    436c:	f000 fba2 	bl	4ab4 <nrf_cc310_bl_hash_update_internal>
    4370:	442e      	add	r6, r5
    4372:	f1b8 0f00 	cmp.w	r8, #0
    4376:	d0c3      	beq.n	4300 <nrf_cc310_bl_hash_sha256_update+0x18>
    4378:	4642      	mov	r2, r8
    437a:	4631      	mov	r1, r6
    437c:	f104 0030 	add.w	r0, r4, #48	; 0x30
    4380:	f002 fa0e 	bl	67a0 <SaSi_PalMemCopy>
    4384:	f8c4 8070 	str.w	r8, [r4, #112]	; 0x70
    4388:	e7bc      	b.n	4304 <nrf_cc310_bl_hash_sha256_update+0x1c>
    438a:	f8df 9008 	ldr.w	r9, [pc, #8]	; 4394 <nrf_cc310_bl_hash_sha256_update+0xac>
    438e:	e7b9      	b.n	4304 <nrf_cc310_bl_hash_sha256_update+0x1c>
    4390:	00006a30 	.word	0x00006a30
    4394:	00f0020c 	.word	0x00f0020c

00004398 <nrf_cc310_bl_hash_sha256_finalize>:
    4398:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    439c:	4b14      	ldr	r3, [pc, #80]	; (43f0 <nrf_cc310_bl_hash_sha256_finalize+0x58>)
    439e:	4604      	mov	r4, r0
    43a0:	460e      	mov	r6, r1
    43a2:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    43a4:	466f      	mov	r7, sp
    43a6:	e887 000f 	stmia.w	r7, {r0, r1, r2, r3}
    43aa:	4620      	mov	r0, r4
    43ac:	f7ff ff72 	bl	4294 <verify_context_hash_sha256>
    43b0:	4680      	mov	r8, r0
    43b2:	b9b0      	cbnz	r0, 43e2 <nrf_cc310_bl_hash_sha256_finalize+0x4a>
    43b4:	b1ce      	cbz	r6, 43ea <nrf_cc310_bl_hash_sha256_finalize+0x52>
    43b6:	6a63      	ldr	r3, [r4, #36]	; 0x24
    43b8:	1d25      	adds	r5, r4, #4
    43ba:	9501      	str	r5, [sp, #4]
    43bc:	b93b      	cbnz	r3, 43ce <nrf_cc310_bl_hash_sha256_finalize+0x36>
    43be:	2301      	movs	r3, #1
    43c0:	6263      	str	r3, [r4, #36]	; 0x24
    43c2:	6f22      	ldr	r2, [r4, #112]	; 0x70
    43c4:	f104 0130 	add.w	r1, r4, #48	; 0x30
    43c8:	4638      	mov	r0, r7
    43ca:	f000 fb73 	bl	4ab4 <nrf_cc310_bl_hash_update_internal>
    43ce:	462b      	mov	r3, r5
    43d0:	3e04      	subs	r6, #4
    43d2:	3424      	adds	r4, #36	; 0x24
    43d4:	f853 2b04 	ldr.w	r2, [r3], #4
    43d8:	ba12      	rev	r2, r2
    43da:	42a3      	cmp	r3, r4
    43dc:	f846 2f04 	str.w	r2, [r6, #4]!
    43e0:	d1f8      	bne.n	43d4 <nrf_cc310_bl_hash_sha256_finalize+0x3c>
    43e2:	4640      	mov	r0, r8
    43e4:	b004      	add	sp, #16
    43e6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    43ea:	f8df 8008 	ldr.w	r8, [pc, #8]	; 43f4 <nrf_cc310_bl_hash_sha256_finalize+0x5c>
    43ee:	e7f8      	b.n	43e2 <nrf_cc310_bl_hash_sha256_finalize+0x4a>
    43f0:	00006a30 	.word	0x00006a30
    43f4:	00f00205 	.word	0x00f00205

000043f8 <nrf_cc310_bl_init>:
    43f8:	4b08      	ldr	r3, [pc, #32]	; (441c <nrf_cc310_bl_init+0x24>)
    43fa:	681b      	ldr	r3, [r3, #0]
    43fc:	0e1b      	lsrs	r3, r3, #24
    43fe:	2bf0      	cmp	r3, #240	; 0xf0
    4400:	d108      	bne.n	4414 <nrf_cc310_bl_init+0x1c>
    4402:	4b07      	ldr	r3, [pc, #28]	; (4420 <nrf_cc310_bl_init+0x28>)
    4404:	681a      	ldr	r2, [r3, #0]
    4406:	4b07      	ldr	r3, [pc, #28]	; (4424 <nrf_cc310_bl_init+0x2c>)
    4408:	429a      	cmp	r2, r3
    440a:	d105      	bne.n	4418 <nrf_cc310_bl_init+0x20>
    440c:	4b06      	ldr	r3, [pc, #24]	; (4428 <nrf_cc310_bl_init+0x30>)
    440e:	2000      	movs	r0, #0
    4410:	6018      	str	r0, [r3, #0]
    4412:	4770      	bx	lr
    4414:	2005      	movs	r0, #5
    4416:	4770      	bx	lr
    4418:	2006      	movs	r0, #6
    441a:	4770      	bx	lr
    441c:	5002b928 	.word	0x5002b928
    4420:	5002ba24 	.word	0x5002ba24
    4424:	20e00000 	.word	0x20e00000
    4428:	5002ba0c 	.word	0x5002ba0c

0000442c <PkaSetRegsMapTab>:
    442c:	2200      	movs	r2, #0
    442e:	b530      	push	{r4, r5, lr}
    4430:	0049      	lsls	r1, r1, #1
    4432:	4613      	mov	r3, r2
    4434:	3802      	subs	r0, #2
    4436:	f640 75fc 	movw	r5, #4092	; 0xffc
    443a:	f102 54a0 	add.w	r4, r2, #335544320	; 0x14000000
    443e:	f504 442c 	add.w	r4, r4, #44032	; 0xac00
    4442:	00a4      	lsls	r4, r4, #2
    4444:	4290      	cmp	r0, r2
    4446:	f102 0201 	add.w	r2, r2, #1
    444a:	bfca      	itet	gt
    444c:	6023      	strgt	r3, [r4, #0]
    444e:	6025      	strle	r5, [r4, #0]
    4450:	185b      	addgt	r3, r3, r1
    4452:	2a1e      	cmp	r2, #30
    4454:	d1f1      	bne.n	443a <PkaSetRegsMapTab+0xe>
    4456:	4a04      	ldr	r2, [pc, #16]	; (4468 <PkaSetRegsMapTab+0x3c>)
    4458:	6013      	str	r3, [r2, #0]
    445a:	440b      	add	r3, r1
    445c:	6053      	str	r3, [r2, #4]
    445e:	4b03      	ldr	r3, [pc, #12]	; (446c <PkaSetRegsMapTab+0x40>)
    4460:	4a03      	ldr	r2, [pc, #12]	; (4470 <PkaSetRegsMapTab+0x44>)
    4462:	601a      	str	r2, [r3, #0]
    4464:	bd30      	pop	{r4, r5, pc}
    4466:	bf00      	nop
    4468:	5002b078 	.word	0x5002b078
    446c:	5002b084 	.word	0x5002b084
    4470:	000ff820 	.word	0x000ff820

00004474 <PkaGetRegEffectiveSizeInBits>:
    4474:	b530      	push	{r4, r5, lr}
    4476:	4b1e      	ldr	r3, [pc, #120]	; (44f0 <PkaGetRegEffectiveSizeInBits+0x7c>)
    4478:	b085      	sub	sp, #20
    447a:	461a      	mov	r2, r3
    447c:	6819      	ldr	r1, [r3, #0]
    447e:	9100      	str	r1, [sp, #0]
    4480:	9900      	ldr	r1, [sp, #0]
    4482:	07cc      	lsls	r4, r1, #31
    4484:	d5fa      	bpl.n	447c <PkaGetRegEffectiveSizeInBits+0x8>
    4486:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    448a:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    448e:	0080      	lsls	r0, r0, #2
    4490:	6801      	ldr	r1, [r0, #0]
    4492:	6813      	ldr	r3, [r2, #0]
    4494:	9301      	str	r3, [sp, #4]
    4496:	9b01      	ldr	r3, [sp, #4]
    4498:	07d8      	lsls	r0, r3, #31
    449a:	d5fa      	bpl.n	4492 <PkaGetRegEffectiveSizeInBits+0x1e>
    449c:	4b15      	ldr	r3, [pc, #84]	; (44f4 <PkaGetRegEffectiveSizeInBits+0x80>)
    449e:	4c16      	ldr	r4, [pc, #88]	; (44f8 <PkaGetRegEffectiveSizeInBits+0x84>)
    44a0:	6818      	ldr	r0, [r3, #0]
    44a2:	4d16      	ldr	r5, [pc, #88]	; (44fc <PkaGetRegEffectiveSizeInBits+0x88>)
    44a4:	301f      	adds	r0, #31
    44a6:	2320      	movs	r3, #32
    44a8:	fb90 f0f3 	sdiv	r0, r0, r3
    44ac:	3801      	subs	r0, #1
    44ae:	2800      	cmp	r0, #0
    44b0:	da10      	bge.n	44d4 <PkaGetRegEffectiveSizeInBits+0x60>
    44b2:	2300      	movs	r3, #0
    44b4:	3001      	adds	r0, #1
    44b6:	0140      	lsls	r0, r0, #5
    44b8:	b153      	cbz	r3, 44d0 <PkaGetRegEffectiveSizeInBits+0x5c>
    44ba:	f1a0 0120 	sub.w	r1, r0, #32
    44be:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    44c2:	4213      	tst	r3, r2
    44c4:	d104      	bne.n	44d0 <PkaGetRegEffectiveSizeInBits+0x5c>
    44c6:	3801      	subs	r0, #1
    44c8:	4288      	cmp	r0, r1
    44ca:	ea4f 0252 	mov.w	r2, r2, lsr #1
    44ce:	d1f8      	bne.n	44c2 <PkaGetRegEffectiveSizeInBits+0x4e>
    44d0:	b005      	add	sp, #20
    44d2:	bd30      	pop	{r4, r5, pc}
    44d4:	6813      	ldr	r3, [r2, #0]
    44d6:	9303      	str	r3, [sp, #12]
    44d8:	9b03      	ldr	r3, [sp, #12]
    44da:	07db      	lsls	r3, r3, #31
    44dc:	d5fa      	bpl.n	44d4 <PkaGetRegEffectiveSizeInBits+0x60>
    44de:	1843      	adds	r3, r0, r1
    44e0:	6023      	str	r3, [r4, #0]
    44e2:	682b      	ldr	r3, [r5, #0]
    44e4:	9302      	str	r3, [sp, #8]
    44e6:	9b02      	ldr	r3, [sp, #8]
    44e8:	2b00      	cmp	r3, #0
    44ea:	d1e3      	bne.n	44b4 <PkaGetRegEffectiveSizeInBits+0x40>
    44ec:	3801      	subs	r0, #1
    44ee:	e7de      	b.n	44ae <PkaGetRegEffectiveSizeInBits+0x3a>
    44f0:	5002b0b4 	.word	0x5002b0b4
    44f4:	5002b0ac 	.word	0x5002b0ac
    44f8:	5002b0e4 	.word	0x5002b0e4
    44fc:	5002b0dc 	.word	0x5002b0dc

00004500 <PkaGetNextMsBit>:
    4500:	b5f0      	push	{r4, r5, r6, r7, lr}
    4502:	681d      	ldr	r5, [r3, #0]
    4504:	b085      	sub	sp, #20
    4506:	f001 041f 	and.w	r4, r1, #31
    450a:	b90d      	cbnz	r5, 4510 <PkaGetNextMsBit+0x10>
    450c:	2c1f      	cmp	r4, #31
    450e:	d125      	bne.n	455c <PkaGetNextMsBit+0x5c>
    4510:	4d15      	ldr	r5, [pc, #84]	; (4568 <PkaGetNextMsBit+0x68>)
    4512:	462e      	mov	r6, r5
    4514:	682f      	ldr	r7, [r5, #0]
    4516:	9701      	str	r7, [sp, #4]
    4518:	9f01      	ldr	r7, [sp, #4]
    451a:	07ff      	lsls	r7, r7, #31
    451c:	d5fa      	bpl.n	4514 <PkaGetNextMsBit+0x14>
    451e:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    4522:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    4526:	0080      	lsls	r0, r0, #2
    4528:	6800      	ldr	r0, [r0, #0]
    452a:	6835      	ldr	r5, [r6, #0]
    452c:	9503      	str	r5, [sp, #12]
    452e:	9d03      	ldr	r5, [sp, #12]
    4530:	07ed      	lsls	r5, r5, #31
    4532:	d5fa      	bpl.n	452a <PkaGetNextMsBit+0x2a>
    4534:	4d0d      	ldr	r5, [pc, #52]	; (456c <PkaGetNextMsBit+0x6c>)
    4536:	eb00 1061 	add.w	r0, r0, r1, asr #5
    453a:	6028      	str	r0, [r5, #0]
    453c:	480c      	ldr	r0, [pc, #48]	; (4570 <PkaGetNextMsBit+0x70>)
    453e:	6800      	ldr	r0, [r0, #0]
    4540:	9002      	str	r0, [sp, #8]
    4542:	2c1f      	cmp	r4, #31
    4544:	bf18      	it	ne
    4546:	43c9      	mvnne	r1, r1
    4548:	9802      	ldr	r0, [sp, #8]
    454a:	bf0f      	iteee	eq
    454c:	6010      	streq	r0, [r2, #0]
    454e:	f001 011f 	andne.w	r1, r1, #31
    4552:	fa00 f101 	lslne.w	r1, r0, r1
    4556:	6011      	strne	r1, [r2, #0]
    4558:	2100      	movs	r1, #0
    455a:	6019      	str	r1, [r3, #0]
    455c:	6810      	ldr	r0, [r2, #0]
    455e:	0043      	lsls	r3, r0, #1
    4560:	0fc0      	lsrs	r0, r0, #31
    4562:	6013      	str	r3, [r2, #0]
    4564:	b005      	add	sp, #20
    4566:	bdf0      	pop	{r4, r5, r6, r7, pc}
    4568:	5002b0b4 	.word	0x5002b0b4
    456c:	5002b0e4 	.word	0x5002b0e4
    4570:	5002b0dc 	.word	0x5002b0dc

00004574 <PkaSetRegsSizesTab>:
    4574:	4b0c      	ldr	r3, [pc, #48]	; (45a8 <PkaSetRegsSizesTab+0x34>)
    4576:	6018      	str	r0, [r3, #0]
    4578:	303f      	adds	r0, #63	; 0x3f
    457a:	f020 003f 	bic.w	r0, r0, #63	; 0x3f
    457e:	0189      	lsls	r1, r1, #6
    4580:	3040      	adds	r0, #64	; 0x40
    4582:	6058      	str	r0, [r3, #4]
    4584:	6099      	str	r1, [r3, #8]
    4586:	60d9      	str	r1, [r3, #12]
    4588:	6119      	str	r1, [r3, #16]
    458a:	6159      	str	r1, [r3, #20]
    458c:	6199      	str	r1, [r3, #24]
    458e:	331c      	adds	r3, #28
    4590:	4806      	ldr	r0, [pc, #24]	; (45ac <PkaSetRegsSizesTab+0x38>)
    4592:	6019      	str	r1, [r3, #0]
    4594:	b082      	sub	sp, #8
    4596:	6802      	ldr	r2, [r0, #0]
    4598:	9201      	str	r2, [sp, #4]
    459a:	9a01      	ldr	r2, [sp, #4]
    459c:	07d2      	lsls	r2, r2, #31
    459e:	d5fa      	bpl.n	4596 <PkaSetRegsSizesTab+0x22>
    45a0:	6019      	str	r1, [r3, #0]
    45a2:	b002      	add	sp, #8
    45a4:	4770      	bx	lr
    45a6:	bf00      	nop
    45a8:	5002b090 	.word	0x5002b090
    45ac:	5002b0b4 	.word	0x5002b0b4

000045b0 <PkaInitPka>:
    45b0:	b538      	push	{r3, r4, r5, lr}
    45b2:	f1a0 0320 	sub.w	r3, r0, #32
    45b6:	f5b3 6f42 	cmp.w	r3, #3104	; 0xc20
    45ba:	4605      	mov	r5, r0
    45bc:	d82c      	bhi.n	4618 <PkaInitPka+0x68>
    45be:	288f      	cmp	r0, #143	; 0x8f
    45c0:	d826      	bhi.n	4610 <PkaInitPka+0x60>
    45c2:	f100 0347 	add.w	r3, r0, #71	; 0x47
    45c6:	f100 0466 	add.w	r4, r0, #102	; 0x66
    45ca:	06db      	lsls	r3, r3, #27
    45cc:	ea4f 1454 	mov.w	r4, r4, lsr #5
    45d0:	d000      	beq.n	45d4 <PkaInitPka+0x24>
    45d2:	3401      	adds	r4, #1
    45d4:	0164      	lsls	r4, r4, #5
    45d6:	343f      	adds	r4, #63	; 0x3f
    45d8:	09a4      	lsrs	r4, r4, #6
    45da:	3401      	adds	r4, #1
    45dc:	b111      	cbz	r1, 45e4 <PkaInitPka+0x34>
    45de:	42a1      	cmp	r1, r4
    45e0:	d31a      	bcc.n	4618 <PkaInitPka+0x68>
    45e2:	460c      	mov	r4, r1
    45e4:	00e3      	lsls	r3, r4, #3
    45e6:	f44f 5080 	mov.w	r0, #4096	; 0x1000
    45ea:	fbb0 f0f3 	udiv	r0, r0, r3
    45ee:	2820      	cmp	r0, #32
    45f0:	bf28      	it	cs
    45f2:	2020      	movcs	r0, #32
    45f4:	b102      	cbz	r2, 45f8 <PkaInitPka+0x48>
    45f6:	6010      	str	r0, [r2, #0]
    45f8:	4b08      	ldr	r3, [pc, #32]	; (461c <PkaInitPka+0x6c>)
    45fa:	2201      	movs	r2, #1
    45fc:	601a      	str	r2, [r3, #0]
    45fe:	4621      	mov	r1, r4
    4600:	f7ff ff14 	bl	442c <PkaSetRegsMapTab>
    4604:	4628      	mov	r0, r5
    4606:	4621      	mov	r1, r4
    4608:	f7ff ffb4 	bl	4574 <PkaSetRegsSizesTab>
    460c:	2000      	movs	r0, #0
    460e:	bd38      	pop	{r3, r4, r5, pc}
    4610:	f100 041f 	add.w	r4, r0, #31
    4614:	0964      	lsrs	r4, r4, #5
    4616:	e7dd      	b.n	45d4 <PkaInitPka+0x24>
    4618:	4801      	ldr	r0, [pc, #4]	; (4620 <PkaInitPka+0x70>)
    461a:	e7f8      	b.n	460e <PkaInitPka+0x5e>
    461c:	5002b81c 	.word	0x5002b81c
    4620:	00f02122 	.word	0x00f02122

00004624 <PkaClearBlockOfRegs>:
    4624:	b5f0      	push	{r4, r5, r6, r7, lr}
    4626:	4b45      	ldr	r3, [pc, #276]	; (473c <PkaClearBlockOfRegs+0x118>)
    4628:	b089      	sub	sp, #36	; 0x24
    462a:	461d      	mov	r5, r3
    462c:	681c      	ldr	r4, [r3, #0]
    462e:	9401      	str	r4, [sp, #4]
    4630:	9c01      	ldr	r4, [sp, #4]
    4632:	07e4      	lsls	r4, r4, #31
    4634:	d5fa      	bpl.n	462c <PkaClearBlockOfRegs+0x8>
    4636:	4b42      	ldr	r3, [pc, #264]	; (4740 <PkaClearBlockOfRegs+0x11c>)
    4638:	f8df e10c 	ldr.w	lr, [pc, #268]	; 4748 <PkaClearBlockOfRegs+0x124>
    463c:	f8df c10c 	ldr.w	ip, [pc, #268]	; 474c <PkaClearBlockOfRegs+0x128>
    4640:	4413      	add	r3, r2
    4642:	009b      	lsls	r3, r3, #2
    4644:	2400      	movs	r4, #0
    4646:	681a      	ldr	r2, [r3, #0]
    4648:	180b      	adds	r3, r1, r0
    464a:	2b1e      	cmp	r3, #30
    464c:	bf88      	it	hi
    464e:	f1c0 011e 	rsbhi	r1, r0, #30
    4652:	321f      	adds	r2, #31
    4654:	180b      	adds	r3, r1, r0
    4656:	0952      	lsrs	r2, r2, #5
    4658:	4353      	muls	r3, r2
    465a:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    465e:	bf82      	ittt	hi
    4660:	f44f 6180 	movhi.w	r1, #1024	; 0x400
    4664:	fbb1 f1f2 	udivhi	r1, r1, r2
    4668:	1a09      	subhi	r1, r1, r0
    466a:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    466e:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    4672:	4627      	mov	r7, r4
    4674:	42a1      	cmp	r1, r4
    4676:	dc33      	bgt.n	46e0 <PkaClearBlockOfRegs+0xbc>
    4678:	682b      	ldr	r3, [r5, #0]
    467a:	9304      	str	r3, [sp, #16]
    467c:	9b04      	ldr	r3, [sp, #16]
    467e:	07db      	lsls	r3, r3, #31
    4680:	d5fa      	bpl.n	4678 <PkaClearBlockOfRegs+0x54>
    4682:	4b30      	ldr	r3, [pc, #192]	; (4744 <PkaClearBlockOfRegs+0x120>)
    4684:	681b      	ldr	r3, [r3, #0]
    4686:	6829      	ldr	r1, [r5, #0]
    4688:	9105      	str	r1, [sp, #20]
    468a:	9905      	ldr	r1, [sp, #20]
    468c:	07cf      	lsls	r7, r1, #31
    468e:	d5fa      	bpl.n	4686 <PkaClearBlockOfRegs+0x62>
    4690:	4c2d      	ldr	r4, [pc, #180]	; (4748 <PkaClearBlockOfRegs+0x124>)
    4692:	492e      	ldr	r1, [pc, #184]	; (474c <PkaClearBlockOfRegs+0x128>)
    4694:	6023      	str	r3, [r4, #0]
    4696:	2300      	movs	r3, #0
    4698:	461e      	mov	r6, r3
    469a:	4293      	cmp	r3, r2
    469c:	f103 0001 	add.w	r0, r3, #1
    46a0:	d140      	bne.n	4724 <PkaClearBlockOfRegs+0x100>
    46a2:	f020 0201 	bic.w	r2, r0, #1
    46a6:	4829      	ldr	r0, [pc, #164]	; (474c <PkaClearBlockOfRegs+0x128>)
    46a8:	4619      	mov	r1, r3
    46aa:	2600      	movs	r6, #0
    46ac:	428a      	cmp	r2, r1
    46ae:	d83c      	bhi.n	472a <PkaClearBlockOfRegs+0x106>
    46b0:	6829      	ldr	r1, [r5, #0]
    46b2:	9106      	str	r1, [sp, #24]
    46b4:	9906      	ldr	r1, [sp, #24]
    46b6:	07ce      	lsls	r6, r1, #31
    46b8:	d5fa      	bpl.n	46b0 <PkaClearBlockOfRegs+0x8c>
    46ba:	4925      	ldr	r1, [pc, #148]	; (4750 <PkaClearBlockOfRegs+0x12c>)
    46bc:	6809      	ldr	r1, [r1, #0]
    46be:	6828      	ldr	r0, [r5, #0]
    46c0:	9007      	str	r0, [sp, #28]
    46c2:	9807      	ldr	r0, [sp, #28]
    46c4:	07c0      	lsls	r0, r0, #31
    46c6:	d5fa      	bpl.n	46be <PkaClearBlockOfRegs+0x9a>
    46c8:	6021      	str	r1, [r4, #0]
    46ca:	4820      	ldr	r0, [pc, #128]	; (474c <PkaClearBlockOfRegs+0x128>)
    46cc:	2100      	movs	r1, #0
    46ce:	460c      	mov	r4, r1
    46d0:	428b      	cmp	r3, r1
    46d2:	d12d      	bne.n	4730 <PkaClearBlockOfRegs+0x10c>
    46d4:	491d      	ldr	r1, [pc, #116]	; (474c <PkaClearBlockOfRegs+0x128>)
    46d6:	2000      	movs	r0, #0
    46d8:	429a      	cmp	r2, r3
    46da:	d82c      	bhi.n	4736 <PkaClearBlockOfRegs+0x112>
    46dc:	b009      	add	sp, #36	; 0x24
    46de:	bdf0      	pop	{r4, r5, r6, r7, pc}
    46e0:	682b      	ldr	r3, [r5, #0]
    46e2:	9302      	str	r3, [sp, #8]
    46e4:	9b02      	ldr	r3, [sp, #8]
    46e6:	07db      	lsls	r3, r3, #31
    46e8:	d5fa      	bpl.n	46e0 <PkaClearBlockOfRegs+0xbc>
    46ea:	1903      	adds	r3, r0, r4
    46ec:	009b      	lsls	r3, r3, #2
    46ee:	681b      	ldr	r3, [r3, #0]
    46f0:	682e      	ldr	r6, [r5, #0]
    46f2:	9603      	str	r6, [sp, #12]
    46f4:	9e03      	ldr	r6, [sp, #12]
    46f6:	07f6      	lsls	r6, r6, #31
    46f8:	d5fa      	bpl.n	46f0 <PkaClearBlockOfRegs+0xcc>
    46fa:	f8ce 3000 	str.w	r3, [lr]
    46fe:	2300      	movs	r3, #0
    4700:	4293      	cmp	r3, r2
    4702:	f103 0301 	add.w	r3, r3, #1
    4706:	d106      	bne.n	4716 <PkaClearBlockOfRegs+0xf2>
    4708:	4616      	mov	r6, r2
    470a:	f023 0301 	bic.w	r3, r3, #1
    470e:	42b3      	cmp	r3, r6
    4710:	d804      	bhi.n	471c <PkaClearBlockOfRegs+0xf8>
    4712:	3401      	adds	r4, #1
    4714:	e7ae      	b.n	4674 <PkaClearBlockOfRegs+0x50>
    4716:	f8cc 7000 	str.w	r7, [ip]
    471a:	e7f1      	b.n	4700 <PkaClearBlockOfRegs+0xdc>
    471c:	f8cc 7000 	str.w	r7, [ip]
    4720:	3601      	adds	r6, #1
    4722:	e7f4      	b.n	470e <PkaClearBlockOfRegs+0xea>
    4724:	600e      	str	r6, [r1, #0]
    4726:	4603      	mov	r3, r0
    4728:	e7b7      	b.n	469a <PkaClearBlockOfRegs+0x76>
    472a:	6006      	str	r6, [r0, #0]
    472c:	3101      	adds	r1, #1
    472e:	e7bd      	b.n	46ac <PkaClearBlockOfRegs+0x88>
    4730:	6004      	str	r4, [r0, #0]
    4732:	3101      	adds	r1, #1
    4734:	e7cc      	b.n	46d0 <PkaClearBlockOfRegs+0xac>
    4736:	6008      	str	r0, [r1, #0]
    4738:	3301      	adds	r3, #1
    473a:	e7cd      	b.n	46d8 <PkaClearBlockOfRegs+0xb4>
    473c:	5002b0b4 	.word	0x5002b0b4
    4740:	1400ac24 	.word	0x1400ac24
    4744:	5002b07c 	.word	0x5002b07c
    4748:	5002b0d4 	.word	0x5002b0d4
    474c:	5002b0d8 	.word	0x5002b0d8
    4750:	5002b078 	.word	0x5002b078

00004754 <PkaFinishAndMutexUnlock>:
    4754:	b508      	push	{r3, lr}
    4756:	b140      	cbz	r0, 476a <PkaFinishAndMutexUnlock+0x16>
    4758:	2820      	cmp	r0, #32
    475a:	4601      	mov	r1, r0
    475c:	f04f 0207 	mov.w	r2, #7
    4760:	bf28      	it	cs
    4762:	2120      	movcs	r1, #32
    4764:	2000      	movs	r0, #0
    4766:	f7ff ff5d 	bl	4624 <PkaClearBlockOfRegs>
    476a:	4b02      	ldr	r3, [pc, #8]	; (4774 <PkaFinishAndMutexUnlock+0x20>)
    476c:	2200      	movs	r2, #0
    476e:	601a      	str	r2, [r3, #0]
    4770:	bd08      	pop	{r3, pc}
    4772:	bf00      	nop
    4774:	5002b81c 	.word	0x5002b81c

00004778 <PkaCopyDataIntoPkaReg>:
    4778:	b5f0      	push	{r4, r5, r6, r7, lr}
    477a:	4d29      	ldr	r5, [pc, #164]	; (4820 <PkaCopyDataIntoPkaReg+0xa8>)
    477c:	b085      	sub	sp, #20
    477e:	462c      	mov	r4, r5
    4780:	682e      	ldr	r6, [r5, #0]
    4782:	9600      	str	r6, [sp, #0]
    4784:	9e00      	ldr	r6, [sp, #0]
    4786:	07f6      	lsls	r6, r6, #31
    4788:	d5fa      	bpl.n	4780 <PkaCopyDataIntoPkaReg+0x8>
    478a:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    478e:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    4792:	0080      	lsls	r0, r0, #2
    4794:	6805      	ldr	r5, [r0, #0]
    4796:	6820      	ldr	r0, [r4, #0]
    4798:	9001      	str	r0, [sp, #4]
    479a:	9801      	ldr	r0, [sp, #4]
    479c:	07c7      	lsls	r7, r0, #31
    479e:	d5fa      	bpl.n	4796 <PkaCopyDataIntoPkaReg+0x1e>
    47a0:	4820      	ldr	r0, [pc, #128]	; (4824 <PkaCopyDataIntoPkaReg+0xac>)
    47a2:	4f21      	ldr	r7, [pc, #132]	; (4828 <PkaCopyDataIntoPkaReg+0xb0>)
    47a4:	6005      	str	r5, [r0, #0]
    47a6:	eb02 0683 	add.w	r6, r2, r3, lsl #2
    47aa:	42b2      	cmp	r2, r6
    47ac:	d129      	bne.n	4802 <PkaCopyDataIntoPkaReg+0x8a>
    47ae:	1c5a      	adds	r2, r3, #1
    47b0:	4e1d      	ldr	r6, [pc, #116]	; (4828 <PkaCopyDataIntoPkaReg+0xb0>)
    47b2:	f022 0201 	bic.w	r2, r2, #1
    47b6:	2700      	movs	r7, #0
    47b8:	429a      	cmp	r2, r3
    47ba:	d827      	bhi.n	480c <PkaCopyDataIntoPkaReg+0x94>
    47bc:	6823      	ldr	r3, [r4, #0]
    47be:	9302      	str	r3, [sp, #8]
    47c0:	9b02      	ldr	r3, [sp, #8]
    47c2:	07de      	lsls	r6, r3, #31
    47c4:	d5fa      	bpl.n	47bc <PkaCopyDataIntoPkaReg+0x44>
    47c6:	4b19      	ldr	r3, [pc, #100]	; (482c <PkaCopyDataIntoPkaReg+0xb4>)
    47c8:	440b      	add	r3, r1
    47ca:	009b      	lsls	r3, r3, #2
    47cc:	681b      	ldr	r3, [r3, #0]
    47ce:	331f      	adds	r3, #31
    47d0:	095b      	lsrs	r3, r3, #5
    47d2:	429a      	cmp	r2, r3
    47d4:	d213      	bcs.n	47fe <PkaCopyDataIntoPkaReg+0x86>
    47d6:	6821      	ldr	r1, [r4, #0]
    47d8:	9103      	str	r1, [sp, #12]
    47da:	9903      	ldr	r1, [sp, #12]
    47dc:	07c9      	lsls	r1, r1, #31
    47de:	d5fa      	bpl.n	47d6 <PkaCopyDataIntoPkaReg+0x5e>
    47e0:	4415      	add	r5, r2
    47e2:	2100      	movs	r1, #0
    47e4:	1a9b      	subs	r3, r3, r2
    47e6:	4a10      	ldr	r2, [pc, #64]	; (4828 <PkaCopyDataIntoPkaReg+0xb0>)
    47e8:	6005      	str	r5, [r0, #0]
    47ea:	4608      	mov	r0, r1
    47ec:	428b      	cmp	r3, r1
    47ee:	d810      	bhi.n	4812 <PkaCopyDataIntoPkaReg+0x9a>
    47f0:	1c5a      	adds	r2, r3, #1
    47f2:	490d      	ldr	r1, [pc, #52]	; (4828 <PkaCopyDataIntoPkaReg+0xb0>)
    47f4:	f022 0201 	bic.w	r2, r2, #1
    47f8:	2000      	movs	r0, #0
    47fa:	429a      	cmp	r2, r3
    47fc:	d80c      	bhi.n	4818 <PkaCopyDataIntoPkaReg+0xa0>
    47fe:	b005      	add	sp, #20
    4800:	bdf0      	pop	{r4, r5, r6, r7, pc}
    4802:	f852 cb04 	ldr.w	ip, [r2], #4
    4806:	f8c7 c000 	str.w	ip, [r7]
    480a:	e7ce      	b.n	47aa <PkaCopyDataIntoPkaReg+0x32>
    480c:	6037      	str	r7, [r6, #0]
    480e:	3301      	adds	r3, #1
    4810:	e7d2      	b.n	47b8 <PkaCopyDataIntoPkaReg+0x40>
    4812:	6010      	str	r0, [r2, #0]
    4814:	3101      	adds	r1, #1
    4816:	e7e9      	b.n	47ec <PkaCopyDataIntoPkaReg+0x74>
    4818:	6008      	str	r0, [r1, #0]
    481a:	3301      	adds	r3, #1
    481c:	e7ed      	b.n	47fa <PkaCopyDataIntoPkaReg+0x82>
    481e:	bf00      	nop
    4820:	5002b0b4 	.word	0x5002b0b4
    4824:	5002b0d4 	.word	0x5002b0d4
    4828:	5002b0d8 	.word	0x5002b0d8
    482c:	1400ac24 	.word	0x1400ac24

00004830 <PkaEcdsaVerify>:
    4830:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4834:	4b81      	ldr	r3, [pc, #516]	; (4a3c <PkaEcdsaVerify+0x20c>)
    4836:	681d      	ldr	r5, [r3, #0]
    4838:	6898      	ldr	r0, [r3, #8]
    483a:	3320      	adds	r3, #32
    483c:	b0a0      	sub	sp, #128	; 0x80
    483e:	461e      	mov	r6, r3
    4840:	681a      	ldr	r2, [r3, #0]
    4842:	9201      	str	r2, [sp, #4]
    4844:	9a01      	ldr	r2, [sp, #4]
    4846:	07d7      	lsls	r7, r2, #31
    4848:	d5fa      	bpl.n	4840 <PkaEcdsaVerify+0x10>
    484a:	4b7d      	ldr	r3, [pc, #500]	; (4a40 <PkaEcdsaVerify+0x210>)
    484c:	4a7d      	ldr	r2, [pc, #500]	; (4a44 <PkaEcdsaVerify+0x214>)
    484e:	601a      	str	r2, [r3, #0]
    4850:	6832      	ldr	r2, [r6, #0]
    4852:	9202      	str	r2, [sp, #8]
    4854:	9a02      	ldr	r2, [sp, #8]
    4856:	07d4      	lsls	r4, r2, #31
    4858:	d5fa      	bpl.n	4850 <PkaEcdsaVerify+0x20>
    485a:	4a7b      	ldr	r2, [pc, #492]	; (4a48 <PkaEcdsaVerify+0x218>)
    485c:	601a      	str	r2, [r3, #0]
    485e:	4a7b      	ldr	r2, [pc, #492]	; (4a4c <PkaEcdsaVerify+0x21c>)
    4860:	4614      	mov	r4, r2
    4862:	6811      	ldr	r1, [r2, #0]
    4864:	9103      	str	r1, [sp, #12]
    4866:	9903      	ldr	r1, [sp, #12]
    4868:	07c9      	lsls	r1, r1, #31
    486a:	d5fa      	bpl.n	4862 <PkaEcdsaVerify+0x32>
    486c:	4a78      	ldr	r2, [pc, #480]	; (4a50 <PkaEcdsaVerify+0x220>)
    486e:	6811      	ldr	r1, [r2, #0]
    4870:	f3c1 2140 	ubfx	r1, r1, #9, #1
    4874:	6837      	ldr	r7, [r6, #0]
    4876:	9704      	str	r7, [sp, #16]
    4878:	9f04      	ldr	r7, [sp, #16]
    487a:	07ff      	lsls	r7, r7, #31
    487c:	d5fa      	bpl.n	4874 <PkaEcdsaVerify+0x44>
    487e:	4f75      	ldr	r7, [pc, #468]	; (4a54 <PkaEcdsaVerify+0x224>)
    4880:	601f      	str	r7, [r3, #0]
    4882:	6827      	ldr	r7, [r4, #0]
    4884:	9705      	str	r7, [sp, #20]
    4886:	9f05      	ldr	r7, [sp, #20]
    4888:	07ff      	lsls	r7, r7, #31
    488a:	d5fa      	bpl.n	4882 <PkaEcdsaVerify+0x52>
    488c:	6817      	ldr	r7, [r2, #0]
    488e:	2900      	cmp	r1, #0
    4890:	f000 80cf 	beq.w	4a32 <PkaEcdsaVerify+0x202>
    4894:	05b9      	lsls	r1, r7, #22
    4896:	f140 80cc 	bpl.w	4a32 <PkaEcdsaVerify+0x202>
    489a:	6831      	ldr	r1, [r6, #0]
    489c:	9106      	str	r1, [sp, #24]
    489e:	9906      	ldr	r1, [sp, #24]
    48a0:	07cf      	lsls	r7, r1, #31
    48a2:	d5fa      	bpl.n	489a <PkaEcdsaVerify+0x6a>
    48a4:	496c      	ldr	r1, [pc, #432]	; (4a58 <PkaEcdsaVerify+0x228>)
    48a6:	6019      	str	r1, [r3, #0]
    48a8:	6821      	ldr	r1, [r4, #0]
    48aa:	9107      	str	r1, [sp, #28]
    48ac:	9907      	ldr	r1, [sp, #28]
    48ae:	07c9      	lsls	r1, r1, #31
    48b0:	d5fa      	bpl.n	48a8 <PkaEcdsaVerify+0x78>
    48b2:	6811      	ldr	r1, [r2, #0]
    48b4:	f3c1 2140 	ubfx	r1, r1, #9, #1
    48b8:	6837      	ldr	r7, [r6, #0]
    48ba:	9708      	str	r7, [sp, #32]
    48bc:	9f08      	ldr	r7, [sp, #32]
    48be:	07ff      	lsls	r7, r7, #31
    48c0:	d5fa      	bpl.n	48b8 <PkaEcdsaVerify+0x88>
    48c2:	4f66      	ldr	r7, [pc, #408]	; (4a5c <PkaEcdsaVerify+0x22c>)
    48c4:	601f      	str	r7, [r3, #0]
    48c6:	6827      	ldr	r7, [r4, #0]
    48c8:	9709      	str	r7, [sp, #36]	; 0x24
    48ca:	9f09      	ldr	r7, [sp, #36]	; 0x24
    48cc:	07ff      	lsls	r7, r7, #31
    48ce:	d5fa      	bpl.n	48c6 <PkaEcdsaVerify+0x96>
    48d0:	6812      	ldr	r2, [r2, #0]
    48d2:	2900      	cmp	r1, #0
    48d4:	f000 80af 	beq.w	4a36 <PkaEcdsaVerify+0x206>
    48d8:	0591      	lsls	r1, r2, #22
    48da:	f140 80ac 	bpl.w	4a36 <PkaEcdsaVerify+0x206>
    48de:	6832      	ldr	r2, [r6, #0]
    48e0:	920a      	str	r2, [sp, #40]	; 0x28
    48e2:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    48e4:	07d2      	lsls	r2, r2, #31
    48e6:	d5fa      	bpl.n	48de <PkaEcdsaVerify+0xae>
    48e8:	4a56      	ldr	r2, [pc, #344]	; (4a44 <PkaEcdsaVerify+0x214>)
    48ea:	601a      	str	r2, [r3, #0]
    48ec:	6832      	ldr	r2, [r6, #0]
    48ee:	920b      	str	r2, [sp, #44]	; 0x2c
    48f0:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    48f2:	07d7      	lsls	r7, r2, #31
    48f4:	d5fa      	bpl.n	48ec <PkaEcdsaVerify+0xbc>
    48f6:	4a5a      	ldr	r2, [pc, #360]	; (4a60 <PkaEcdsaVerify+0x230>)
    48f8:	601a      	str	r2, [r3, #0]
    48fa:	6831      	ldr	r1, [r6, #0]
    48fc:	910c      	str	r1, [sp, #48]	; 0x30
    48fe:	990c      	ldr	r1, [sp, #48]	; 0x30
    4900:	07cc      	lsls	r4, r1, #31
    4902:	d5fa      	bpl.n	48fa <PkaEcdsaVerify+0xca>
    4904:	4957      	ldr	r1, [pc, #348]	; (4a64 <PkaEcdsaVerify+0x234>)
    4906:	6019      	str	r1, [r3, #0]
    4908:	6831      	ldr	r1, [r6, #0]
    490a:	910d      	str	r1, [sp, #52]	; 0x34
    490c:	990d      	ldr	r1, [sp, #52]	; 0x34
    490e:	07c9      	lsls	r1, r1, #31
    4910:	d5fa      	bpl.n	4908 <PkaEcdsaVerify+0xd8>
    4912:	4955      	ldr	r1, [pc, #340]	; (4a68 <PkaEcdsaVerify+0x238>)
    4914:	6019      	str	r1, [r3, #0]
    4916:	6831      	ldr	r1, [r6, #0]
    4918:	910e      	str	r1, [sp, #56]	; 0x38
    491a:	990e      	ldr	r1, [sp, #56]	; 0x38
    491c:	07cf      	lsls	r7, r1, #31
    491e:	d5fa      	bpl.n	4916 <PkaEcdsaVerify+0xe6>
    4920:	4952      	ldr	r1, [pc, #328]	; (4a6c <PkaEcdsaVerify+0x23c>)
    4922:	6019      	str	r1, [r3, #0]
    4924:	6831      	ldr	r1, [r6, #0]
    4926:	910f      	str	r1, [sp, #60]	; 0x3c
    4928:	990f      	ldr	r1, [sp, #60]	; 0x3c
    492a:	07cc      	lsls	r4, r1, #31
    492c:	d5fa      	bpl.n	4924 <PkaEcdsaVerify+0xf4>
    492e:	4950      	ldr	r1, [pc, #320]	; (4a70 <PkaEcdsaVerify+0x240>)
    4930:	6019      	str	r1, [r3, #0]
    4932:	4b50      	ldr	r3, [pc, #320]	; (4a74 <PkaEcdsaVerify+0x244>)
    4934:	461e      	mov	r6, r3
    4936:	6819      	ldr	r1, [r3, #0]
    4938:	9110      	str	r1, [sp, #64]	; 0x40
    493a:	9910      	ldr	r1, [sp, #64]	; 0x40
    493c:	07c9      	lsls	r1, r1, #31
    493e:	d5fa      	bpl.n	4936 <PkaEcdsaVerify+0x106>
    4940:	4c3f      	ldr	r4, [pc, #252]	; (4a40 <PkaEcdsaVerify+0x210>)
    4942:	4b4d      	ldr	r3, [pc, #308]	; (4a78 <PkaEcdsaVerify+0x248>)
    4944:	6023      	str	r3, [r4, #0]
    4946:	6833      	ldr	r3, [r6, #0]
    4948:	9311      	str	r3, [sp, #68]	; 0x44
    494a:	9b11      	ldr	r3, [sp, #68]	; 0x44
    494c:	07db      	lsls	r3, r3, #31
    494e:	d5fa      	bpl.n	4946 <PkaEcdsaVerify+0x116>
    4950:	4b4a      	ldr	r3, [pc, #296]	; (4a7c <PkaEcdsaVerify+0x24c>)
    4952:	6023      	str	r3, [r4, #0]
    4954:	6833      	ldr	r3, [r6, #0]
    4956:	9312      	str	r3, [sp, #72]	; 0x48
    4958:	9b12      	ldr	r3, [sp, #72]	; 0x48
    495a:	07df      	lsls	r7, r3, #31
    495c:	d5fa      	bpl.n	4954 <PkaEcdsaVerify+0x124>
    495e:	4b48      	ldr	r3, [pc, #288]	; (4a80 <PkaEcdsaVerify+0x250>)
    4960:	6023      	str	r3, [r4, #0]
    4962:	4b3a      	ldr	r3, [pc, #232]	; (4a4c <PkaEcdsaVerify+0x21c>)
    4964:	4698      	mov	r8, r3
    4966:	6819      	ldr	r1, [r3, #0]
    4968:	9113      	str	r1, [sp, #76]	; 0x4c
    496a:	9913      	ldr	r1, [sp, #76]	; 0x4c
    496c:	07c9      	lsls	r1, r1, #31
    496e:	d5fa      	bpl.n	4966 <PkaEcdsaVerify+0x136>
    4970:	4f32      	ldr	r7, [pc, #200]	; (4a3c <PkaEcdsaVerify+0x20c>)
    4972:	6038      	str	r0, [r7, #0]
    4974:	6833      	ldr	r3, [r6, #0]
    4976:	9314      	str	r3, [sp, #80]	; 0x50
    4978:	9b14      	ldr	r3, [sp, #80]	; 0x50
    497a:	07db      	lsls	r3, r3, #31
    497c:	d5fa      	bpl.n	4974 <PkaEcdsaVerify+0x144>
    497e:	6022      	str	r2, [r4, #0]
    4980:	6833      	ldr	r3, [r6, #0]
    4982:	9315      	str	r3, [sp, #84]	; 0x54
    4984:	9b15      	ldr	r3, [sp, #84]	; 0x54
    4986:	07d8      	lsls	r0, r3, #31
    4988:	d5fa      	bpl.n	4980 <PkaEcdsaVerify+0x150>
    498a:	4b3e      	ldr	r3, [pc, #248]	; (4a84 <PkaEcdsaVerify+0x254>)
    498c:	6023      	str	r3, [r4, #0]
    498e:	6833      	ldr	r3, [r6, #0]
    4990:	9316      	str	r3, [sp, #88]	; 0x58
    4992:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4994:	07d9      	lsls	r1, r3, #31
    4996:	d5fa      	bpl.n	498e <PkaEcdsaVerify+0x15e>
    4998:	4b3b      	ldr	r3, [pc, #236]	; (4a88 <PkaEcdsaVerify+0x258>)
    499a:	6023      	str	r3, [r4, #0]
    499c:	6833      	ldr	r3, [r6, #0]
    499e:	9317      	str	r3, [sp, #92]	; 0x5c
    49a0:	9b17      	ldr	r3, [sp, #92]	; 0x5c
    49a2:	07da      	lsls	r2, r3, #31
    49a4:	d5fa      	bpl.n	499c <PkaEcdsaVerify+0x16c>
    49a6:	4b39      	ldr	r3, [pc, #228]	; (4a8c <PkaEcdsaVerify+0x25c>)
    49a8:	6023      	str	r3, [r4, #0]
    49aa:	6833      	ldr	r3, [r6, #0]
    49ac:	9318      	str	r3, [sp, #96]	; 0x60
    49ae:	9b18      	ldr	r3, [sp, #96]	; 0x60
    49b0:	07db      	lsls	r3, r3, #31
    49b2:	d5fa      	bpl.n	49aa <PkaEcdsaVerify+0x17a>
    49b4:	4b36      	ldr	r3, [pc, #216]	; (4a90 <PkaEcdsaVerify+0x260>)
    49b6:	6023      	str	r3, [r4, #0]
    49b8:	6833      	ldr	r3, [r6, #0]
    49ba:	9319      	str	r3, [sp, #100]	; 0x64
    49bc:	9b19      	ldr	r3, [sp, #100]	; 0x64
    49be:	07d8      	lsls	r0, r3, #31
    49c0:	d5fa      	bpl.n	49b8 <PkaEcdsaVerify+0x188>
    49c2:	4b34      	ldr	r3, [pc, #208]	; (4a94 <PkaEcdsaVerify+0x264>)
    49c4:	6023      	str	r3, [r4, #0]
    49c6:	6833      	ldr	r3, [r6, #0]
    49c8:	931a      	str	r3, [sp, #104]	; 0x68
    49ca:	9b1a      	ldr	r3, [sp, #104]	; 0x68
    49cc:	07d9      	lsls	r1, r3, #31
    49ce:	d5fa      	bpl.n	49c6 <PkaEcdsaVerify+0x196>
    49d0:	4b31      	ldr	r3, [pc, #196]	; (4a98 <PkaEcdsaVerify+0x268>)
    49d2:	6023      	str	r3, [r4, #0]
    49d4:	6833      	ldr	r3, [r6, #0]
    49d6:	931b      	str	r3, [sp, #108]	; 0x6c
    49d8:	9b1b      	ldr	r3, [sp, #108]	; 0x6c
    49da:	07da      	lsls	r2, r3, #31
    49dc:	d5fa      	bpl.n	49d4 <PkaEcdsaVerify+0x1a4>
    49de:	4b2f      	ldr	r3, [pc, #188]	; (4a9c <PkaEcdsaVerify+0x26c>)
    49e0:	6023      	str	r3, [r4, #0]
    49e2:	f000 fc1d 	bl	5220 <PkaSum2ScalarMullt>
    49e6:	bb08      	cbnz	r0, 4a2c <PkaEcdsaVerify+0x1fc>
    49e8:	f8d8 3000 	ldr.w	r3, [r8]
    49ec:	931c      	str	r3, [sp, #112]	; 0x70
    49ee:	9b1c      	ldr	r3, [sp, #112]	; 0x70
    49f0:	07db      	lsls	r3, r3, #31
    49f2:	d5f9      	bpl.n	49e8 <PkaEcdsaVerify+0x1b8>
    49f4:	603d      	str	r5, [r7, #0]
    49f6:	6833      	ldr	r3, [r6, #0]
    49f8:	931d      	str	r3, [sp, #116]	; 0x74
    49fa:	9b1d      	ldr	r3, [sp, #116]	; 0x74
    49fc:	07d9      	lsls	r1, r3, #31
    49fe:	d5fa      	bpl.n	49f6 <PkaEcdsaVerify+0x1c6>
    4a00:	4b27      	ldr	r3, [pc, #156]	; (4aa0 <PkaEcdsaVerify+0x270>)
    4a02:	6023      	str	r3, [r4, #0]
    4a04:	6833      	ldr	r3, [r6, #0]
    4a06:	931e      	str	r3, [sp, #120]	; 0x78
    4a08:	9b1e      	ldr	r3, [sp, #120]	; 0x78
    4a0a:	07da      	lsls	r2, r3, #31
    4a0c:	d5fa      	bpl.n	4a04 <PkaEcdsaVerify+0x1d4>
    4a0e:	4b25      	ldr	r3, [pc, #148]	; (4aa4 <PkaEcdsaVerify+0x274>)
    4a10:	6023      	str	r3, [r4, #0]
    4a12:	f8d8 3000 	ldr.w	r3, [r8]
    4a16:	931f      	str	r3, [sp, #124]	; 0x7c
    4a18:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
    4a1a:	07db      	lsls	r3, r3, #31
    4a1c:	d5f9      	bpl.n	4a12 <PkaEcdsaVerify+0x1e2>
    4a1e:	4b0c      	ldr	r3, [pc, #48]	; (4a50 <PkaEcdsaVerify+0x220>)
    4a20:	681b      	ldr	r3, [r3, #0]
    4a22:	f413 5f80 	tst.w	r3, #4096	; 0x1000
    4a26:	4b20      	ldr	r3, [pc, #128]	; (4aa8 <PkaEcdsaVerify+0x278>)
    4a28:	bf08      	it	eq
    4a2a:	4618      	moveq	r0, r3
    4a2c:	b020      	add	sp, #128	; 0x80
    4a2e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4a32:	481e      	ldr	r0, [pc, #120]	; (4aac <PkaEcdsaVerify+0x27c>)
    4a34:	e7fa      	b.n	4a2c <PkaEcdsaVerify+0x1fc>
    4a36:	481e      	ldr	r0, [pc, #120]	; (4ab0 <PkaEcdsaVerify+0x280>)
    4a38:	e7f8      	b.n	4a2c <PkaEcdsaVerify+0x1fc>
    4a3a:	bf00      	nop
    4a3c:	5002b090 	.word	0x5002b090
    4a40:	5002b080 	.word	0x5002b080
    4a44:	51021000 	.word	0x51021000
    4a48:	29721fc0 	.word	0x29721fc0
    4a4c:	5002b0b4 	.word	0x5002b0b4
    4a50:	5002b088 	.word	0x5002b088
    4a54:	2901cfc0 	.word	0x2901cfc0
    4a58:	290e1fc0 	.word	0x290e1fc0
    4a5c:	29003fc0 	.word	0x29003fc0
    4a60:	49020140 	.word	0x49020140
    4a64:	a8843100 	.word	0xa8843100
    4a68:	49160000 	.word	0x49160000
    4a6c:	a1080140 	.word	0xa1080140
    4a70:	88084480 	.word	0x88084480
    4a74:	5002b0b0 	.word	0x5002b0b0
    4a78:	887044c0 	.word	0x887044c0
    4a7c:	417a0780 	.word	0x417a0780
    4a80:	417e07c0 	.word	0x417e07c0
    4a84:	496a0000 	.word	0x496a0000
    4a88:	49160680 	.word	0x49160680
    4a8c:	496e0040 	.word	0x496e0040
    4a90:	21000200 	.word	0x21000200
    4a94:	21208200 	.word	0x21208200
    4a98:	21208240 	.word	0x21208240
    4a9c:	21248280 	.word	0x21248280
    4aa0:	a161a140 	.word	0xa161a140
    4aa4:	5161c800 	.word	0x5161c800
    4aa8:	00f10803 	.word	0x00f10803
    4aac:	00f10801 	.word	0x00f10801
    4ab0:	00f10802 	.word	0x00f10802

00004ab4 <nrf_cc310_bl_hash_update_internal>:
    4ab4:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4ab8:	4b31      	ldr	r3, [pc, #196]	; (4b80 <nrf_cc310_bl_hash_update_internal+0xcc>)
    4aba:	6844      	ldr	r4, [r0, #4]
    4abc:	4680      	mov	r8, r0
    4abe:	4692      	mov	sl, r2
    4ac0:	4699      	mov	r9, r3
    4ac2:	681a      	ldr	r2, [r3, #0]
    4ac4:	2a00      	cmp	r2, #0
    4ac6:	d1fc      	bne.n	4ac2 <nrf_cc310_bl_hash_update_internal+0xe>
    4ac8:	4b2e      	ldr	r3, [pc, #184]	; (4b84 <nrf_cc310_bl_hash_update_internal+0xd0>)
    4aca:	469b      	mov	fp, r3
    4acc:	681a      	ldr	r2, [r3, #0]
    4ace:	2a00      	cmp	r2, #0
    4ad0:	d1fc      	bne.n	4acc <nrf_cc310_bl_hash_update_internal+0x18>
    4ad2:	f04f 30ff 	mov.w	r0, #4294967295
    4ad6:	9101      	str	r1, [sp, #4]
    4ad8:	f000 fc94 	bl	5404 <SaSi_HalClearInterruptBit>
    4adc:	2080      	movs	r0, #128	; 0x80
    4ade:	f000 fc97 	bl	5410 <SaSi_HalMaskInterrupt>
    4ae2:	4d29      	ldr	r5, [pc, #164]	; (4b88 <nrf_cc310_bl_hash_update_internal+0xd4>)
    4ae4:	4a29      	ldr	r2, [pc, #164]	; (4b8c <nrf_cc310_bl_hash_update_internal+0xd8>)
    4ae6:	4f2a      	ldr	r7, [pc, #168]	; (4b90 <nrf_cc310_bl_hash_update_internal+0xdc>)
    4ae8:	4e2a      	ldr	r6, [pc, #168]	; (4b94 <nrf_cc310_bl_hash_update_internal+0xe0>)
    4aea:	2301      	movs	r3, #1
    4aec:	2007      	movs	r0, #7
    4aee:	602b      	str	r3, [r5, #0]
    4af0:	f5a2 729e 	sub.w	r2, r2, #316	; 0x13c
    4af4:	f8c2 013c 	str.w	r0, [r2, #316]	; 0x13c
    4af8:	6013      	str	r3, [r2, #0]
    4afa:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4afc:	603b      	str	r3, [r7, #0]
    4afe:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    4b00:	6033      	str	r3, [r6, #0]
    4b02:	f8d8 3000 	ldr.w	r3, [r8]
    4b06:	f842 3c04 	str.w	r3, [r2, #-4]
    4b0a:	f8d8 3008 	ldr.w	r3, [r8, #8]
    4b0e:	4620      	mov	r0, r4
    4b10:	4798      	blx	r3
    4b12:	9901      	ldr	r1, [sp, #4]
    4b14:	f8d9 3000 	ldr.w	r3, [r9]
    4b18:	2b00      	cmp	r3, #0
    4b1a:	d1fb      	bne.n	4b14 <nrf_cc310_bl_hash_update_internal+0x60>
    4b1c:	f1ba 0f00 	cmp.w	sl, #0
    4b20:	d120      	bne.n	4b64 <nrf_cc310_bl_hash_update_internal+0xb0>
    4b22:	4b1d      	ldr	r3, [pc, #116]	; (4b98 <nrf_cc310_bl_hash_update_internal+0xe4>)
    4b24:	2204      	movs	r2, #4
    4b26:	601a      	str	r2, [r3, #0]
    4b28:	f8d9 3000 	ldr.w	r3, [r9]
    4b2c:	2b00      	cmp	r3, #0
    4b2e:	d1fb      	bne.n	4b28 <nrf_cc310_bl_hash_update_internal+0x74>
    4b30:	f8db a000 	ldr.w	sl, [fp]
    4b34:	f1ba 0f00 	cmp.w	sl, #0
    4b38:	d1fa      	bne.n	4b30 <nrf_cc310_bl_hash_update_internal+0x7c>
    4b3a:	f8d8 300c 	ldr.w	r3, [r8, #12]
    4b3e:	4620      	mov	r0, r4
    4b40:	4798      	blx	r3
    4b42:	683b      	ldr	r3, [r7, #0]
    4b44:	6263      	str	r3, [r4, #36]	; 0x24
    4b46:	6833      	ldr	r3, [r6, #0]
    4b48:	62a3      	str	r3, [r4, #40]	; 0x28
    4b4a:	4b14      	ldr	r3, [pc, #80]	; (4b9c <nrf_cc310_bl_hash_update_internal+0xe8>)
    4b4c:	f8c3 a000 	str.w	sl, [r3]
    4b50:	f8c3 a144 	str.w	sl, [r3, #324]	; 0x144
    4b54:	f8d9 3000 	ldr.w	r3, [r9]
    4b58:	2b00      	cmp	r3, #0
    4b5a:	d1fb      	bne.n	4b54 <nrf_cc310_bl_hash_update_internal+0xa0>
    4b5c:	602b      	str	r3, [r5, #0]
    4b5e:	b003      	add	sp, #12
    4b60:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4b64:	6a23      	ldr	r3, [r4, #32]
    4b66:	2b01      	cmp	r3, #1
    4b68:	bf04      	itt	eq
    4b6a:	4a0c      	ldreq	r2, [pc, #48]	; (4b9c <nrf_cc310_bl_hash_update_internal+0xe8>)
    4b6c:	6013      	streq	r3, [r2, #0]
    4b6e:	4b0c      	ldr	r3, [pc, #48]	; (4ba0 <nrf_cc310_bl_hash_update_internal+0xec>)
    4b70:	2040      	movs	r0, #64	; 0x40
    4b72:	6019      	str	r1, [r3, #0]
    4b74:	f8c3 a004 	str.w	sl, [r3, #4]
    4b78:	f000 fc50 	bl	541c <SaSi_HalWaitInterrupt>
    4b7c:	e7d4      	b.n	4b28 <nrf_cc310_bl_hash_update_internal+0x74>
    4b7e:	bf00      	nop
    4b80:	5002b910 	.word	0x5002b910
    4b84:	5002bc20 	.word	0x5002bc20
    4b88:	5002b818 	.word	0x5002b818
    4b8c:	5002b900 	.word	0x5002b900
    4b90:	5002b7cc 	.word	0x5002b7cc
    4b94:	5002b7d0 	.word	0x5002b7d0
    4b98:	5002b7c8 	.word	0x5002b7c8
    4b9c:	5002b684 	.word	0x5002b684
    4ba0:	5002bc28 	.word	0x5002bc28

00004ba4 <PkaDoubleMdf2Mdf>:
    4ba4:	b510      	push	{r4, lr}
    4ba6:	4b54      	ldr	r3, [pc, #336]	; (4cf8 <PkaDoubleMdf2Mdf+0x154>)
    4ba8:	b098      	sub	sp, #96	; 0x60
    4baa:	4619      	mov	r1, r3
    4bac:	681a      	ldr	r2, [r3, #0]
    4bae:	9201      	str	r2, [sp, #4]
    4bb0:	9a01      	ldr	r2, [sp, #4]
    4bb2:	07d2      	lsls	r2, r2, #31
    4bb4:	d5fa      	bpl.n	4bac <PkaDoubleMdf2Mdf+0x8>
    4bb6:	4b51      	ldr	r3, [pc, #324]	; (4cfc <PkaDoubleMdf2Mdf+0x158>)
    4bb8:	4a51      	ldr	r2, [pc, #324]	; (4d00 <PkaDoubleMdf2Mdf+0x15c>)
    4bba:	601a      	str	r2, [r3, #0]
    4bbc:	680a      	ldr	r2, [r1, #0]
    4bbe:	9202      	str	r2, [sp, #8]
    4bc0:	9a02      	ldr	r2, [sp, #8]
    4bc2:	07d4      	lsls	r4, r2, #31
    4bc4:	d5fa      	bpl.n	4bbc <PkaDoubleMdf2Mdf+0x18>
    4bc6:	4a4f      	ldr	r2, [pc, #316]	; (4d04 <PkaDoubleMdf2Mdf+0x160>)
    4bc8:	601a      	str	r2, [r3, #0]
    4bca:	680a      	ldr	r2, [r1, #0]
    4bcc:	9203      	str	r2, [sp, #12]
    4bce:	9a03      	ldr	r2, [sp, #12]
    4bd0:	07d0      	lsls	r0, r2, #31
    4bd2:	d5fa      	bpl.n	4bca <PkaDoubleMdf2Mdf+0x26>
    4bd4:	484c      	ldr	r0, [pc, #304]	; (4d08 <PkaDoubleMdf2Mdf+0x164>)
    4bd6:	6018      	str	r0, [r3, #0]
    4bd8:	680a      	ldr	r2, [r1, #0]
    4bda:	9204      	str	r2, [sp, #16]
    4bdc:	9a04      	ldr	r2, [sp, #16]
    4bde:	07d2      	lsls	r2, r2, #31
    4be0:	d5fa      	bpl.n	4bd8 <PkaDoubleMdf2Mdf+0x34>
    4be2:	4a4a      	ldr	r2, [pc, #296]	; (4d0c <PkaDoubleMdf2Mdf+0x168>)
    4be4:	601a      	str	r2, [r3, #0]
    4be6:	680a      	ldr	r2, [r1, #0]
    4be8:	9205      	str	r2, [sp, #20]
    4bea:	9a05      	ldr	r2, [sp, #20]
    4bec:	07d4      	lsls	r4, r2, #31
    4bee:	d5fa      	bpl.n	4be6 <PkaDoubleMdf2Mdf+0x42>
    4bf0:	4a47      	ldr	r2, [pc, #284]	; (4d10 <PkaDoubleMdf2Mdf+0x16c>)
    4bf2:	601a      	str	r2, [r3, #0]
    4bf4:	680a      	ldr	r2, [r1, #0]
    4bf6:	9206      	str	r2, [sp, #24]
    4bf8:	9a06      	ldr	r2, [sp, #24]
    4bfa:	07d2      	lsls	r2, r2, #31
    4bfc:	d5fa      	bpl.n	4bf4 <PkaDoubleMdf2Mdf+0x50>
    4bfe:	4a45      	ldr	r2, [pc, #276]	; (4d14 <PkaDoubleMdf2Mdf+0x170>)
    4c00:	601a      	str	r2, [r3, #0]
    4c02:	680a      	ldr	r2, [r1, #0]
    4c04:	9207      	str	r2, [sp, #28]
    4c06:	9a07      	ldr	r2, [sp, #28]
    4c08:	07d4      	lsls	r4, r2, #31
    4c0a:	d5fa      	bpl.n	4c02 <PkaDoubleMdf2Mdf+0x5e>
    4c0c:	4a42      	ldr	r2, [pc, #264]	; (4d18 <PkaDoubleMdf2Mdf+0x174>)
    4c0e:	601a      	str	r2, [r3, #0]
    4c10:	680a      	ldr	r2, [r1, #0]
    4c12:	9208      	str	r2, [sp, #32]
    4c14:	9a08      	ldr	r2, [sp, #32]
    4c16:	07d2      	lsls	r2, r2, #31
    4c18:	d5fa      	bpl.n	4c10 <PkaDoubleMdf2Mdf+0x6c>
    4c1a:	4a40      	ldr	r2, [pc, #256]	; (4d1c <PkaDoubleMdf2Mdf+0x178>)
    4c1c:	601a      	str	r2, [r3, #0]
    4c1e:	680a      	ldr	r2, [r1, #0]
    4c20:	9209      	str	r2, [sp, #36]	; 0x24
    4c22:	9a09      	ldr	r2, [sp, #36]	; 0x24
    4c24:	07d4      	lsls	r4, r2, #31
    4c26:	d5fa      	bpl.n	4c1e <PkaDoubleMdf2Mdf+0x7a>
    4c28:	4a3d      	ldr	r2, [pc, #244]	; (4d20 <PkaDoubleMdf2Mdf+0x17c>)
    4c2a:	601a      	str	r2, [r3, #0]
    4c2c:	680a      	ldr	r2, [r1, #0]
    4c2e:	920a      	str	r2, [sp, #40]	; 0x28
    4c30:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    4c32:	07d2      	lsls	r2, r2, #31
    4c34:	d5fa      	bpl.n	4c2c <PkaDoubleMdf2Mdf+0x88>
    4c36:	4a3b      	ldr	r2, [pc, #236]	; (4d24 <PkaDoubleMdf2Mdf+0x180>)
    4c38:	601a      	str	r2, [r3, #0]
    4c3a:	680a      	ldr	r2, [r1, #0]
    4c3c:	920b      	str	r2, [sp, #44]	; 0x2c
    4c3e:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    4c40:	07d4      	lsls	r4, r2, #31
    4c42:	d5fa      	bpl.n	4c3a <PkaDoubleMdf2Mdf+0x96>
    4c44:	4a38      	ldr	r2, [pc, #224]	; (4d28 <PkaDoubleMdf2Mdf+0x184>)
    4c46:	601a      	str	r2, [r3, #0]
    4c48:	680a      	ldr	r2, [r1, #0]
    4c4a:	920c      	str	r2, [sp, #48]	; 0x30
    4c4c:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    4c4e:	07d2      	lsls	r2, r2, #31
    4c50:	d5fa      	bpl.n	4c48 <PkaDoubleMdf2Mdf+0xa4>
    4c52:	4a36      	ldr	r2, [pc, #216]	; (4d2c <PkaDoubleMdf2Mdf+0x188>)
    4c54:	601a      	str	r2, [r3, #0]
    4c56:	680a      	ldr	r2, [r1, #0]
    4c58:	920d      	str	r2, [sp, #52]	; 0x34
    4c5a:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    4c5c:	07d4      	lsls	r4, r2, #31
    4c5e:	d5fa      	bpl.n	4c56 <PkaDoubleMdf2Mdf+0xb2>
    4c60:	4a33      	ldr	r2, [pc, #204]	; (4d30 <PkaDoubleMdf2Mdf+0x18c>)
    4c62:	601a      	str	r2, [r3, #0]
    4c64:	680a      	ldr	r2, [r1, #0]
    4c66:	920e      	str	r2, [sp, #56]	; 0x38
    4c68:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    4c6a:	07d2      	lsls	r2, r2, #31
    4c6c:	d5fa      	bpl.n	4c64 <PkaDoubleMdf2Mdf+0xc0>
    4c6e:	4a31      	ldr	r2, [pc, #196]	; (4d34 <PkaDoubleMdf2Mdf+0x190>)
    4c70:	601a      	str	r2, [r3, #0]
    4c72:	680a      	ldr	r2, [r1, #0]
    4c74:	920f      	str	r2, [sp, #60]	; 0x3c
    4c76:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    4c78:	07d4      	lsls	r4, r2, #31
    4c7a:	d5fa      	bpl.n	4c72 <PkaDoubleMdf2Mdf+0xce>
    4c7c:	4a2e      	ldr	r2, [pc, #184]	; (4d38 <PkaDoubleMdf2Mdf+0x194>)
    4c7e:	601a      	str	r2, [r3, #0]
    4c80:	680a      	ldr	r2, [r1, #0]
    4c82:	9210      	str	r2, [sp, #64]	; 0x40
    4c84:	9a10      	ldr	r2, [sp, #64]	; 0x40
    4c86:	07d2      	lsls	r2, r2, #31
    4c88:	d5fa      	bpl.n	4c80 <PkaDoubleMdf2Mdf+0xdc>
    4c8a:	4a2c      	ldr	r2, [pc, #176]	; (4d3c <PkaDoubleMdf2Mdf+0x198>)
    4c8c:	601a      	str	r2, [r3, #0]
    4c8e:	4b1a      	ldr	r3, [pc, #104]	; (4cf8 <PkaDoubleMdf2Mdf+0x154>)
    4c90:	4619      	mov	r1, r3
    4c92:	681c      	ldr	r4, [r3, #0]
    4c94:	9411      	str	r4, [sp, #68]	; 0x44
    4c96:	9c11      	ldr	r4, [sp, #68]	; 0x44
    4c98:	07e4      	lsls	r4, r4, #31
    4c9a:	d5fa      	bpl.n	4c92 <PkaDoubleMdf2Mdf+0xee>
    4c9c:	4b17      	ldr	r3, [pc, #92]	; (4cfc <PkaDoubleMdf2Mdf+0x158>)
    4c9e:	6018      	str	r0, [r3, #0]
    4ca0:	6808      	ldr	r0, [r1, #0]
    4ca2:	9012      	str	r0, [sp, #72]	; 0x48
    4ca4:	9812      	ldr	r0, [sp, #72]	; 0x48
    4ca6:	07c4      	lsls	r4, r0, #31
    4ca8:	d5fa      	bpl.n	4ca0 <PkaDoubleMdf2Mdf+0xfc>
    4caa:	601a      	str	r2, [r3, #0]
    4cac:	680a      	ldr	r2, [r1, #0]
    4cae:	9213      	str	r2, [sp, #76]	; 0x4c
    4cb0:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    4cb2:	07d0      	lsls	r0, r2, #31
    4cb4:	d5fa      	bpl.n	4cac <PkaDoubleMdf2Mdf+0x108>
    4cb6:	4a12      	ldr	r2, [pc, #72]	; (4d00 <PkaDoubleMdf2Mdf+0x15c>)
    4cb8:	601a      	str	r2, [r3, #0]
    4cba:	680a      	ldr	r2, [r1, #0]
    4cbc:	9214      	str	r2, [sp, #80]	; 0x50
    4cbe:	9a14      	ldr	r2, [sp, #80]	; 0x50
    4cc0:	07d2      	lsls	r2, r2, #31
    4cc2:	d5fa      	bpl.n	4cba <PkaDoubleMdf2Mdf+0x116>
    4cc4:	4a1e      	ldr	r2, [pc, #120]	; (4d40 <PkaDoubleMdf2Mdf+0x19c>)
    4cc6:	601a      	str	r2, [r3, #0]
    4cc8:	680a      	ldr	r2, [r1, #0]
    4cca:	9215      	str	r2, [sp, #84]	; 0x54
    4ccc:	9a15      	ldr	r2, [sp, #84]	; 0x54
    4cce:	07d4      	lsls	r4, r2, #31
    4cd0:	d5fa      	bpl.n	4cc8 <PkaDoubleMdf2Mdf+0x124>
    4cd2:	4a1c      	ldr	r2, [pc, #112]	; (4d44 <PkaDoubleMdf2Mdf+0x1a0>)
    4cd4:	601a      	str	r2, [r3, #0]
    4cd6:	680a      	ldr	r2, [r1, #0]
    4cd8:	9216      	str	r2, [sp, #88]	; 0x58
    4cda:	9a16      	ldr	r2, [sp, #88]	; 0x58
    4cdc:	07d0      	lsls	r0, r2, #31
    4cde:	d5fa      	bpl.n	4cd6 <PkaDoubleMdf2Mdf+0x132>
    4ce0:	4a19      	ldr	r2, [pc, #100]	; (4d48 <PkaDoubleMdf2Mdf+0x1a4>)
    4ce2:	601a      	str	r2, [r3, #0]
    4ce4:	680a      	ldr	r2, [r1, #0]
    4ce6:	9217      	str	r2, [sp, #92]	; 0x5c
    4ce8:	9a17      	ldr	r2, [sp, #92]	; 0x5c
    4cea:	07d2      	lsls	r2, r2, #31
    4cec:	d5fa      	bpl.n	4ce4 <PkaDoubleMdf2Mdf+0x140>
    4cee:	4a17      	ldr	r2, [pc, #92]	; (4d4c <PkaDoubleMdf2Mdf+0x1a8>)
    4cf0:	601a      	str	r2, [r3, #0]
    4cf2:	b018      	add	sp, #96	; 0x60
    4cf4:	bd10      	pop	{r4, pc}
    4cf6:	bf00      	nop
    4cf8:	5002b0b0 	.word	0x5002b0b0
    4cfc:	5002b080 	.word	0x5002b080
    4d00:	21659300 	.word	0x21659300
    4d04:	90310400 	.word	0x90310400
    4d08:	90659640 	.word	0x90659640
    4d0c:	21618300 	.word	0x21618300
    4d10:	2130c300 	.word	0x2130c300
    4d14:	9064c300 	.word	0x9064c300
    4d18:	90618100 	.word	0x90618100
    4d1c:	21104600 	.word	0x21104600
    4d20:	21118100 	.word	0x21118100
    4d24:	21444100 	.word	0x21444100
    4d28:	2920c300 	.word	0x2920c300
    4d2c:	c810460c 	.word	0xc810460c
    4d30:	21318600 	.word	0x21318600
    4d34:	2160c300 	.word	0x2160c300
    4d38:	2928c140 	.word	0x2928c140
    4d3c:	21659640 	.word	0x21659640
    4d40:	90311300 	.word	0x90311300
    4d44:	29259640 	.word	0x29259640
    4d48:	c8144659 	.word	0xc8144659
    4d4c:	49320440 	.word	0x49320440

00004d50 <PkaDoubleMdf2Jcb>:
    4d50:	b510      	push	{r4, lr}
    4d52:	4b49      	ldr	r3, [pc, #292]	; (4e78 <PkaDoubleMdf2Jcb+0x128>)
    4d54:	b094      	sub	sp, #80	; 0x50
    4d56:	4619      	mov	r1, r3
    4d58:	681a      	ldr	r2, [r3, #0]
    4d5a:	9200      	str	r2, [sp, #0]
    4d5c:	9a00      	ldr	r2, [sp, #0]
    4d5e:	07d2      	lsls	r2, r2, #31
    4d60:	d5fa      	bpl.n	4d58 <PkaDoubleMdf2Jcb+0x8>
    4d62:	4b46      	ldr	r3, [pc, #280]	; (4e7c <PkaDoubleMdf2Jcb+0x12c>)
    4d64:	4a46      	ldr	r2, [pc, #280]	; (4e80 <PkaDoubleMdf2Jcb+0x130>)
    4d66:	601a      	str	r2, [r3, #0]
    4d68:	680a      	ldr	r2, [r1, #0]
    4d6a:	9201      	str	r2, [sp, #4]
    4d6c:	9a01      	ldr	r2, [sp, #4]
    4d6e:	07d4      	lsls	r4, r2, #31
    4d70:	d5fa      	bpl.n	4d68 <PkaDoubleMdf2Jcb+0x18>
    4d72:	4a44      	ldr	r2, [pc, #272]	; (4e84 <PkaDoubleMdf2Jcb+0x134>)
    4d74:	601a      	str	r2, [r3, #0]
    4d76:	680a      	ldr	r2, [r1, #0]
    4d78:	9202      	str	r2, [sp, #8]
    4d7a:	9a02      	ldr	r2, [sp, #8]
    4d7c:	07d0      	lsls	r0, r2, #31
    4d7e:	d5fa      	bpl.n	4d76 <PkaDoubleMdf2Jcb+0x26>
    4d80:	4841      	ldr	r0, [pc, #260]	; (4e88 <PkaDoubleMdf2Jcb+0x138>)
    4d82:	6018      	str	r0, [r3, #0]
    4d84:	680a      	ldr	r2, [r1, #0]
    4d86:	9203      	str	r2, [sp, #12]
    4d88:	9a03      	ldr	r2, [sp, #12]
    4d8a:	07d2      	lsls	r2, r2, #31
    4d8c:	d5fa      	bpl.n	4d84 <PkaDoubleMdf2Jcb+0x34>
    4d8e:	4a3f      	ldr	r2, [pc, #252]	; (4e8c <PkaDoubleMdf2Jcb+0x13c>)
    4d90:	601a      	str	r2, [r3, #0]
    4d92:	680a      	ldr	r2, [r1, #0]
    4d94:	9204      	str	r2, [sp, #16]
    4d96:	9a04      	ldr	r2, [sp, #16]
    4d98:	07d4      	lsls	r4, r2, #31
    4d9a:	d5fa      	bpl.n	4d92 <PkaDoubleMdf2Jcb+0x42>
    4d9c:	4a3c      	ldr	r2, [pc, #240]	; (4e90 <PkaDoubleMdf2Jcb+0x140>)
    4d9e:	601a      	str	r2, [r3, #0]
    4da0:	680a      	ldr	r2, [r1, #0]
    4da2:	9205      	str	r2, [sp, #20]
    4da4:	9a05      	ldr	r2, [sp, #20]
    4da6:	07d2      	lsls	r2, r2, #31
    4da8:	d5fa      	bpl.n	4da0 <PkaDoubleMdf2Jcb+0x50>
    4daa:	4a3a      	ldr	r2, [pc, #232]	; (4e94 <PkaDoubleMdf2Jcb+0x144>)
    4dac:	601a      	str	r2, [r3, #0]
    4dae:	680a      	ldr	r2, [r1, #0]
    4db0:	9206      	str	r2, [sp, #24]
    4db2:	9a06      	ldr	r2, [sp, #24]
    4db4:	07d4      	lsls	r4, r2, #31
    4db6:	d5fa      	bpl.n	4dae <PkaDoubleMdf2Jcb+0x5e>
    4db8:	4a37      	ldr	r2, [pc, #220]	; (4e98 <PkaDoubleMdf2Jcb+0x148>)
    4dba:	601a      	str	r2, [r3, #0]
    4dbc:	680a      	ldr	r2, [r1, #0]
    4dbe:	9207      	str	r2, [sp, #28]
    4dc0:	9a07      	ldr	r2, [sp, #28]
    4dc2:	07d2      	lsls	r2, r2, #31
    4dc4:	d5fa      	bpl.n	4dbc <PkaDoubleMdf2Jcb+0x6c>
    4dc6:	4a35      	ldr	r2, [pc, #212]	; (4e9c <PkaDoubleMdf2Jcb+0x14c>)
    4dc8:	601a      	str	r2, [r3, #0]
    4dca:	680a      	ldr	r2, [r1, #0]
    4dcc:	9208      	str	r2, [sp, #32]
    4dce:	9a08      	ldr	r2, [sp, #32]
    4dd0:	07d4      	lsls	r4, r2, #31
    4dd2:	d5fa      	bpl.n	4dca <PkaDoubleMdf2Jcb+0x7a>
    4dd4:	4a32      	ldr	r2, [pc, #200]	; (4ea0 <PkaDoubleMdf2Jcb+0x150>)
    4dd6:	601a      	str	r2, [r3, #0]
    4dd8:	680a      	ldr	r2, [r1, #0]
    4dda:	9209      	str	r2, [sp, #36]	; 0x24
    4ddc:	9a09      	ldr	r2, [sp, #36]	; 0x24
    4dde:	07d2      	lsls	r2, r2, #31
    4de0:	d5fa      	bpl.n	4dd8 <PkaDoubleMdf2Jcb+0x88>
    4de2:	4a30      	ldr	r2, [pc, #192]	; (4ea4 <PkaDoubleMdf2Jcb+0x154>)
    4de4:	601a      	str	r2, [r3, #0]
    4de6:	680a      	ldr	r2, [r1, #0]
    4de8:	920a      	str	r2, [sp, #40]	; 0x28
    4dea:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    4dec:	07d4      	lsls	r4, r2, #31
    4dee:	d5fa      	bpl.n	4de6 <PkaDoubleMdf2Jcb+0x96>
    4df0:	4a2d      	ldr	r2, [pc, #180]	; (4ea8 <PkaDoubleMdf2Jcb+0x158>)
    4df2:	601a      	str	r2, [r3, #0]
    4df4:	680a      	ldr	r2, [r1, #0]
    4df6:	920b      	str	r2, [sp, #44]	; 0x2c
    4df8:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    4dfa:	07d2      	lsls	r2, r2, #31
    4dfc:	d5fa      	bpl.n	4df4 <PkaDoubleMdf2Jcb+0xa4>
    4dfe:	4a2b      	ldr	r2, [pc, #172]	; (4eac <PkaDoubleMdf2Jcb+0x15c>)
    4e00:	601a      	str	r2, [r3, #0]
    4e02:	680a      	ldr	r2, [r1, #0]
    4e04:	920c      	str	r2, [sp, #48]	; 0x30
    4e06:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    4e08:	07d4      	lsls	r4, r2, #31
    4e0a:	d5fa      	bpl.n	4e02 <PkaDoubleMdf2Jcb+0xb2>
    4e0c:	4a28      	ldr	r2, [pc, #160]	; (4eb0 <PkaDoubleMdf2Jcb+0x160>)
    4e0e:	601a      	str	r2, [r3, #0]
    4e10:	680a      	ldr	r2, [r1, #0]
    4e12:	920d      	str	r2, [sp, #52]	; 0x34
    4e14:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    4e16:	07d2      	lsls	r2, r2, #31
    4e18:	d5fa      	bpl.n	4e10 <PkaDoubleMdf2Jcb+0xc0>
    4e1a:	4a26      	ldr	r2, [pc, #152]	; (4eb4 <PkaDoubleMdf2Jcb+0x164>)
    4e1c:	601a      	str	r2, [r3, #0]
    4e1e:	680a      	ldr	r2, [r1, #0]
    4e20:	920e      	str	r2, [sp, #56]	; 0x38
    4e22:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    4e24:	07d4      	lsls	r4, r2, #31
    4e26:	d5fa      	bpl.n	4e1e <PkaDoubleMdf2Jcb+0xce>
    4e28:	4a23      	ldr	r2, [pc, #140]	; (4eb8 <PkaDoubleMdf2Jcb+0x168>)
    4e2a:	601a      	str	r2, [r3, #0]
    4e2c:	680a      	ldr	r2, [r1, #0]
    4e2e:	920f      	str	r2, [sp, #60]	; 0x3c
    4e30:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    4e32:	07d2      	lsls	r2, r2, #31
    4e34:	d5fa      	bpl.n	4e2c <PkaDoubleMdf2Jcb+0xdc>
    4e36:	4a21      	ldr	r2, [pc, #132]	; (4ebc <PkaDoubleMdf2Jcb+0x16c>)
    4e38:	601a      	str	r2, [r3, #0]
    4e3a:	4b0f      	ldr	r3, [pc, #60]	; (4e78 <PkaDoubleMdf2Jcb+0x128>)
    4e3c:	4619      	mov	r1, r3
    4e3e:	681c      	ldr	r4, [r3, #0]
    4e40:	9410      	str	r4, [sp, #64]	; 0x40
    4e42:	9c10      	ldr	r4, [sp, #64]	; 0x40
    4e44:	07e4      	lsls	r4, r4, #31
    4e46:	d5fa      	bpl.n	4e3e <PkaDoubleMdf2Jcb+0xee>
    4e48:	4b0c      	ldr	r3, [pc, #48]	; (4e7c <PkaDoubleMdf2Jcb+0x12c>)
    4e4a:	6018      	str	r0, [r3, #0]
    4e4c:	6808      	ldr	r0, [r1, #0]
    4e4e:	9011      	str	r0, [sp, #68]	; 0x44
    4e50:	9811      	ldr	r0, [sp, #68]	; 0x44
    4e52:	07c4      	lsls	r4, r0, #31
    4e54:	d5fa      	bpl.n	4e4c <PkaDoubleMdf2Jcb+0xfc>
    4e56:	601a      	str	r2, [r3, #0]
    4e58:	680a      	ldr	r2, [r1, #0]
    4e5a:	9212      	str	r2, [sp, #72]	; 0x48
    4e5c:	9a12      	ldr	r2, [sp, #72]	; 0x48
    4e5e:	07d0      	lsls	r0, r2, #31
    4e60:	d5fa      	bpl.n	4e58 <PkaDoubleMdf2Jcb+0x108>
    4e62:	4a17      	ldr	r2, [pc, #92]	; (4ec0 <PkaDoubleMdf2Jcb+0x170>)
    4e64:	601a      	str	r2, [r3, #0]
    4e66:	680a      	ldr	r2, [r1, #0]
    4e68:	9213      	str	r2, [sp, #76]	; 0x4c
    4e6a:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    4e6c:	07d2      	lsls	r2, r2, #31
    4e6e:	d5fa      	bpl.n	4e66 <PkaDoubleMdf2Jcb+0x116>
    4e70:	4a14      	ldr	r2, [pc, #80]	; (4ec4 <PkaDoubleMdf2Jcb+0x174>)
    4e72:	601a      	str	r2, [r3, #0]
    4e74:	b014      	add	sp, #80	; 0x50
    4e76:	bd10      	pop	{r4, pc}
    4e78:	5002b0b0 	.word	0x5002b0b0
    4e7c:	5002b080 	.word	0x5002b080
    4e80:	21659080 	.word	0x21659080
    4e84:	90090400 	.word	0x90090400
    4e88:	90659640 	.word	0x90659640
    4e8c:	21618080 	.word	0x21618080
    4e90:	21082080 	.word	0x21082080
    4e94:	90642080 	.word	0x90642080
    4e98:	90618100 	.word	0x90618100
    4e9c:	21104600 	.word	0x21104600
    4ea0:	21118100 	.word	0x21118100
    4ea4:	21444100 	.word	0x21444100
    4ea8:	29202080 	.word	0x29202080
    4eac:	c8104602 	.word	0xc8104602
    4eb0:	21098600 	.word	0x21098600
    4eb4:	21602080 	.word	0x21602080
    4eb8:	29282140 	.word	0x29282140
    4ebc:	21659640 	.word	0x21659640
    4ec0:	29259640 	.word	0x29259640
    4ec4:	c8144659 	.word	0xc8144659

00004ec8 <PkaAddJcbAfn2Mdf>:
    4ec8:	b510      	push	{r4, lr}
    4eca:	4b50      	ldr	r3, [pc, #320]	; (500c <PkaAddJcbAfn2Mdf+0x144>)
    4ecc:	b096      	sub	sp, #88	; 0x58
    4ece:	461c      	mov	r4, r3
    4ed0:	681a      	ldr	r2, [r3, #0]
    4ed2:	9201      	str	r2, [sp, #4]
    4ed4:	9a01      	ldr	r2, [sp, #4]
    4ed6:	07d2      	lsls	r2, r2, #31
    4ed8:	d5fa      	bpl.n	4ed0 <PkaAddJcbAfn2Mdf+0x8>
    4eda:	4b4d      	ldr	r3, [pc, #308]	; (5010 <PkaAddJcbAfn2Mdf+0x148>)
    4edc:	4a4d      	ldr	r2, [pc, #308]	; (5014 <PkaAddJcbAfn2Mdf+0x14c>)
    4ede:	601a      	str	r2, [r3, #0]
    4ee0:	6822      	ldr	r2, [r4, #0]
    4ee2:	9202      	str	r2, [sp, #8]
    4ee4:	9a02      	ldr	r2, [sp, #8]
    4ee6:	07d2      	lsls	r2, r2, #31
    4ee8:	d5fa      	bpl.n	4ee0 <PkaAddJcbAfn2Mdf+0x18>
    4eea:	4a4b      	ldr	r2, [pc, #300]	; (5018 <PkaAddJcbAfn2Mdf+0x150>)
    4eec:	601a      	str	r2, [r3, #0]
    4eee:	4a4b      	ldr	r2, [pc, #300]	; (501c <PkaAddJcbAfn2Mdf+0x154>)
    4ef0:	ea42 4080 	orr.w	r0, r2, r0, lsl #18
    4ef4:	6822      	ldr	r2, [r4, #0]
    4ef6:	9203      	str	r2, [sp, #12]
    4ef8:	9a03      	ldr	r2, [sp, #12]
    4efa:	07d2      	lsls	r2, r2, #31
    4efc:	d5fa      	bpl.n	4ef4 <PkaAddJcbAfn2Mdf+0x2c>
    4efe:	6018      	str	r0, [r3, #0]
    4f00:	6822      	ldr	r2, [r4, #0]
    4f02:	9204      	str	r2, [sp, #16]
    4f04:	9a04      	ldr	r2, [sp, #16]
    4f06:	07d0      	lsls	r0, r2, #31
    4f08:	d5fa      	bpl.n	4f00 <PkaAddJcbAfn2Mdf+0x38>
    4f0a:	4a45      	ldr	r2, [pc, #276]	; (5020 <PkaAddJcbAfn2Mdf+0x158>)
    4f0c:	601a      	str	r2, [r3, #0]
    4f0e:	f5a2 0280 	sub.w	r2, r2, #4194304	; 0x400000
    4f12:	ea42 4181 	orr.w	r1, r2, r1, lsl #18
    4f16:	6822      	ldr	r2, [r4, #0]
    4f18:	9205      	str	r2, [sp, #20]
    4f1a:	9a05      	ldr	r2, [sp, #20]
    4f1c:	07d2      	lsls	r2, r2, #31
    4f1e:	d5fa      	bpl.n	4f16 <PkaAddJcbAfn2Mdf+0x4e>
    4f20:	6019      	str	r1, [r3, #0]
    4f22:	6822      	ldr	r2, [r4, #0]
    4f24:	9206      	str	r2, [sp, #24]
    4f26:	9a06      	ldr	r2, [sp, #24]
    4f28:	07d0      	lsls	r0, r2, #31
    4f2a:	d5fa      	bpl.n	4f22 <PkaAddJcbAfn2Mdf+0x5a>
    4f2c:	4a3d      	ldr	r2, [pc, #244]	; (5024 <PkaAddJcbAfn2Mdf+0x15c>)
    4f2e:	601a      	str	r2, [r3, #0]
    4f30:	6822      	ldr	r2, [r4, #0]
    4f32:	9207      	str	r2, [sp, #28]
    4f34:	9a07      	ldr	r2, [sp, #28]
    4f36:	07d1      	lsls	r1, r2, #31
    4f38:	d5fa      	bpl.n	4f30 <PkaAddJcbAfn2Mdf+0x68>
    4f3a:	4a3b      	ldr	r2, [pc, #236]	; (5028 <PkaAddJcbAfn2Mdf+0x160>)
    4f3c:	601a      	str	r2, [r3, #0]
    4f3e:	6822      	ldr	r2, [r4, #0]
    4f40:	9208      	str	r2, [sp, #32]
    4f42:	9a08      	ldr	r2, [sp, #32]
    4f44:	07d2      	lsls	r2, r2, #31
    4f46:	d5fa      	bpl.n	4f3e <PkaAddJcbAfn2Mdf+0x76>
    4f48:	4a38      	ldr	r2, [pc, #224]	; (502c <PkaAddJcbAfn2Mdf+0x164>)
    4f4a:	601a      	str	r2, [r3, #0]
    4f4c:	6822      	ldr	r2, [r4, #0]
    4f4e:	9209      	str	r2, [sp, #36]	; 0x24
    4f50:	9a09      	ldr	r2, [sp, #36]	; 0x24
    4f52:	07d0      	lsls	r0, r2, #31
    4f54:	d5fa      	bpl.n	4f4c <PkaAddJcbAfn2Mdf+0x84>
    4f56:	4a36      	ldr	r2, [pc, #216]	; (5030 <PkaAddJcbAfn2Mdf+0x168>)
    4f58:	601a      	str	r2, [r3, #0]
    4f5a:	6822      	ldr	r2, [r4, #0]
    4f5c:	920a      	str	r2, [sp, #40]	; 0x28
    4f5e:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    4f60:	07d1      	lsls	r1, r2, #31
    4f62:	d5fa      	bpl.n	4f5a <PkaAddJcbAfn2Mdf+0x92>
    4f64:	4a33      	ldr	r2, [pc, #204]	; (5034 <PkaAddJcbAfn2Mdf+0x16c>)
    4f66:	601a      	str	r2, [r3, #0]
    4f68:	6822      	ldr	r2, [r4, #0]
    4f6a:	920b      	str	r2, [sp, #44]	; 0x2c
    4f6c:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    4f6e:	07d2      	lsls	r2, r2, #31
    4f70:	d5fa      	bpl.n	4f68 <PkaAddJcbAfn2Mdf+0xa0>
    4f72:	4a31      	ldr	r2, [pc, #196]	; (5038 <PkaAddJcbAfn2Mdf+0x170>)
    4f74:	601a      	str	r2, [r3, #0]
    4f76:	6822      	ldr	r2, [r4, #0]
    4f78:	920c      	str	r2, [sp, #48]	; 0x30
    4f7a:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    4f7c:	07d0      	lsls	r0, r2, #31
    4f7e:	d5fa      	bpl.n	4f76 <PkaAddJcbAfn2Mdf+0xae>
    4f80:	4a2e      	ldr	r2, [pc, #184]	; (503c <PkaAddJcbAfn2Mdf+0x174>)
    4f82:	601a      	str	r2, [r3, #0]
    4f84:	6822      	ldr	r2, [r4, #0]
    4f86:	920d      	str	r2, [sp, #52]	; 0x34
    4f88:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    4f8a:	07d1      	lsls	r1, r2, #31
    4f8c:	d5fa      	bpl.n	4f84 <PkaAddJcbAfn2Mdf+0xbc>
    4f8e:	4a2c      	ldr	r2, [pc, #176]	; (5040 <PkaAddJcbAfn2Mdf+0x178>)
    4f90:	601a      	str	r2, [r3, #0]
    4f92:	6822      	ldr	r2, [r4, #0]
    4f94:	920e      	str	r2, [sp, #56]	; 0x38
    4f96:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    4f98:	07d2      	lsls	r2, r2, #31
    4f9a:	d5fa      	bpl.n	4f92 <PkaAddJcbAfn2Mdf+0xca>
    4f9c:	4a29      	ldr	r2, [pc, #164]	; (5044 <PkaAddJcbAfn2Mdf+0x17c>)
    4f9e:	601a      	str	r2, [r3, #0]
    4fa0:	6822      	ldr	r2, [r4, #0]
    4fa2:	920f      	str	r2, [sp, #60]	; 0x3c
    4fa4:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    4fa6:	07d0      	lsls	r0, r2, #31
    4fa8:	d5fa      	bpl.n	4fa0 <PkaAddJcbAfn2Mdf+0xd8>
    4faa:	4a27      	ldr	r2, [pc, #156]	; (5048 <PkaAddJcbAfn2Mdf+0x180>)
    4fac:	601a      	str	r2, [r3, #0]
    4fae:	6821      	ldr	r1, [r4, #0]
    4fb0:	9110      	str	r1, [sp, #64]	; 0x40
    4fb2:	9910      	ldr	r1, [sp, #64]	; 0x40
    4fb4:	07c9      	lsls	r1, r1, #31
    4fb6:	d5fa      	bpl.n	4fae <PkaAddJcbAfn2Mdf+0xe6>
    4fb8:	601a      	str	r2, [r3, #0]
    4fba:	4b14      	ldr	r3, [pc, #80]	; (500c <PkaAddJcbAfn2Mdf+0x144>)
    4fbc:	461a      	mov	r2, r3
    4fbe:	6819      	ldr	r1, [r3, #0]
    4fc0:	9111      	str	r1, [sp, #68]	; 0x44
    4fc2:	9911      	ldr	r1, [sp, #68]	; 0x44
    4fc4:	07c8      	lsls	r0, r1, #31
    4fc6:	d5fa      	bpl.n	4fbe <PkaAddJcbAfn2Mdf+0xf6>
    4fc8:	4b11      	ldr	r3, [pc, #68]	; (5010 <PkaAddJcbAfn2Mdf+0x148>)
    4fca:	4920      	ldr	r1, [pc, #128]	; (504c <PkaAddJcbAfn2Mdf+0x184>)
    4fcc:	6019      	str	r1, [r3, #0]
    4fce:	6811      	ldr	r1, [r2, #0]
    4fd0:	9112      	str	r1, [sp, #72]	; 0x48
    4fd2:	9912      	ldr	r1, [sp, #72]	; 0x48
    4fd4:	07c9      	lsls	r1, r1, #31
    4fd6:	d5fa      	bpl.n	4fce <PkaAddJcbAfn2Mdf+0x106>
    4fd8:	491d      	ldr	r1, [pc, #116]	; (5050 <PkaAddJcbAfn2Mdf+0x188>)
    4fda:	6019      	str	r1, [r3, #0]
    4fdc:	6811      	ldr	r1, [r2, #0]
    4fde:	9113      	str	r1, [sp, #76]	; 0x4c
    4fe0:	9913      	ldr	r1, [sp, #76]	; 0x4c
    4fe2:	07cc      	lsls	r4, r1, #31
    4fe4:	d5fa      	bpl.n	4fdc <PkaAddJcbAfn2Mdf+0x114>
    4fe6:	490b      	ldr	r1, [pc, #44]	; (5014 <PkaAddJcbAfn2Mdf+0x14c>)
    4fe8:	6019      	str	r1, [r3, #0]
    4fea:	6811      	ldr	r1, [r2, #0]
    4fec:	9114      	str	r1, [sp, #80]	; 0x50
    4fee:	9914      	ldr	r1, [sp, #80]	; 0x50
    4ff0:	07c8      	lsls	r0, r1, #31
    4ff2:	d5fa      	bpl.n	4fea <PkaAddJcbAfn2Mdf+0x122>
    4ff4:	4917      	ldr	r1, [pc, #92]	; (5054 <PkaAddJcbAfn2Mdf+0x18c>)
    4ff6:	6019      	str	r1, [r3, #0]
    4ff8:	6811      	ldr	r1, [r2, #0]
    4ffa:	9115      	str	r1, [sp, #84]	; 0x54
    4ffc:	9915      	ldr	r1, [sp, #84]	; 0x54
    4ffe:	07c9      	lsls	r1, r1, #31
    5000:	d5fa      	bpl.n	4ff8 <PkaAddJcbAfn2Mdf+0x130>
    5002:	4a15      	ldr	r2, [pc, #84]	; (5058 <PkaAddJcbAfn2Mdf+0x190>)
    5004:	601a      	str	r2, [r3, #0]
    5006:	b016      	add	sp, #88	; 0x58
    5008:	bd10      	pop	{r4, pc}
    500a:	bf00      	nop
    500c:	5002b0b0 	.word	0x5002b0b0
    5010:	5002b080 	.word	0x5002b080
    5014:	90410440 	.word	0x90410440
    5018:	29298600 	.word	0x29298600
    501c:	c80110d8 	.word	0xc80110d8
    5020:	90411440 	.word	0x90411440
    5024:	29211440 	.word	0x29211440
    5028:	21651440 	.word	0x21651440
    502c:	90403400 	.word	0x90403400
    5030:	900c3100 	.word	0x900c3100
    5034:	900c40c0 	.word	0x900c40c0
    5038:	292030c0 	.word	0x292030c0
    503c:	900d9640 	.word	0x900d9640
    5040:	90604100 	.word	0x90604100
    5044:	c8451603 	.word	0xc8451603
    5048:	21118600 	.word	0x21118600
    504c:	21604100 	.word	0x21604100
    5050:	c8444659 	.word	0xc8444659
    5054:	90451440 	.word	0x90451440
    5058:	902d1440 	.word	0x902d1440

0000505c <PkaJcb2Afn>:
    505c:	b570      	push	{r4, r5, r6, lr}
    505e:	4826      	ldr	r0, [pc, #152]	; (50f8 <PkaJcb2Afn+0x9c>)
    5060:	b088      	sub	sp, #32
    5062:	4605      	mov	r5, r0
    5064:	6804      	ldr	r4, [r0, #0]
    5066:	9400      	str	r4, [sp, #0]
    5068:	9c00      	ldr	r4, [sp, #0]
    506a:	07e6      	lsls	r6, r4, #31
    506c:	d5fa      	bpl.n	5064 <PkaJcb2Afn+0x8>
    506e:	4823      	ldr	r0, [pc, #140]	; (50fc <PkaJcb2Afn+0xa0>)
    5070:	4c23      	ldr	r4, [pc, #140]	; (5100 <PkaJcb2Afn+0xa4>)
    5072:	6004      	str	r4, [r0, #0]
    5074:	4c23      	ldr	r4, [pc, #140]	; (5104 <PkaJcb2Afn+0xa8>)
    5076:	ea44 4383 	orr.w	r3, r4, r3, lsl #18
    507a:	682c      	ldr	r4, [r5, #0]
    507c:	9401      	str	r4, [sp, #4]
    507e:	9c01      	ldr	r4, [sp, #4]
    5080:	07e4      	lsls	r4, r4, #31
    5082:	d5fa      	bpl.n	507a <PkaJcb2Afn+0x1e>
    5084:	6003      	str	r3, [r0, #0]
    5086:	0193      	lsls	r3, r2, #6
    5088:	ea43 4282 	orr.w	r2, r3, r2, lsl #18
    508c:	f042 4410 	orr.w	r4, r2, #2415919104	; 0x90000000
    5090:	f444 44c0 	orr.w	r4, r4, #24576	; 0x6000
    5094:	682b      	ldr	r3, [r5, #0]
    5096:	9302      	str	r3, [sp, #8]
    5098:	9b02      	ldr	r3, [sp, #8]
    509a:	07de      	lsls	r6, r3, #31
    509c:	d5fa      	bpl.n	5094 <PkaJcb2Afn+0x38>
    509e:	6004      	str	r4, [r0, #0]
    50a0:	682b      	ldr	r3, [r5, #0]
    50a2:	9303      	str	r3, [sp, #12]
    50a4:	9b03      	ldr	r3, [sp, #12]
    50a6:	07db      	lsls	r3, r3, #31
    50a8:	d5fa      	bpl.n	50a0 <PkaJcb2Afn+0x44>
    50aa:	4b17      	ldr	r3, [pc, #92]	; (5108 <PkaJcb2Afn+0xac>)
    50ac:	6003      	str	r3, [r0, #0]
    50ae:	018b      	lsls	r3, r1, #6
    50b0:	ea43 4181 	orr.w	r1, r3, r1, lsl #18
    50b4:	f041 4310 	orr.w	r3, r1, #2415919104	; 0x90000000
    50b8:	f443 43c0 	orr.w	r3, r3, #24576	; 0x6000
    50bc:	682e      	ldr	r6, [r5, #0]
    50be:	9604      	str	r6, [sp, #16]
    50c0:	9e04      	ldr	r6, [sp, #16]
    50c2:	07f6      	lsls	r6, r6, #31
    50c4:	d5fa      	bpl.n	50bc <PkaJcb2Afn+0x60>
    50c6:	6003      	str	r3, [r0, #0]
    50c8:	682b      	ldr	r3, [r5, #0]
    50ca:	9305      	str	r3, [sp, #20]
    50cc:	9b05      	ldr	r3, [sp, #20]
    50ce:	07de      	lsls	r6, r3, #31
    50d0:	d5fa      	bpl.n	50c8 <PkaJcb2Afn+0x6c>
    50d2:	6004      	str	r4, [r0, #0]
    50d4:	f041 4158 	orr.w	r1, r1, #3623878656	; 0xd8000000
    50d8:	682b      	ldr	r3, [r5, #0]
    50da:	9306      	str	r3, [sp, #24]
    50dc:	9b06      	ldr	r3, [sp, #24]
    50de:	07dc      	lsls	r4, r3, #31
    50e0:	d5fa      	bpl.n	50d8 <PkaJcb2Afn+0x7c>
    50e2:	6001      	str	r1, [r0, #0]
    50e4:	f042 4258 	orr.w	r2, r2, #3623878656	; 0xd8000000
    50e8:	682b      	ldr	r3, [r5, #0]
    50ea:	9307      	str	r3, [sp, #28]
    50ec:	9b07      	ldr	r3, [sp, #28]
    50ee:	07db      	lsls	r3, r3, #31
    50f0:	d5fa      	bpl.n	50e8 <PkaJcb2Afn+0x8c>
    50f2:	6002      	str	r2, [r0, #0]
    50f4:	b008      	add	sp, #32
    50f6:	bd70      	pop	{r4, r5, r6, pc}
    50f8:	5002b0b0 	.word	0x5002b0b0
    50fc:	5002b080 	.word	0x5002b080
    5100:	290221c0 	.word	0x290221c0
    5104:	98007180 	.word	0x98007180
    5108:	90186180 	.word	0x90186180

0000510c <PkaAddAff>:
    510c:	4b35      	ldr	r3, [pc, #212]	; (51e4 <PkaAddAff+0xd8>)
    510e:	b08e      	sub	sp, #56	; 0x38
    5110:	4619      	mov	r1, r3
    5112:	681a      	ldr	r2, [r3, #0]
    5114:	9200      	str	r2, [sp, #0]
    5116:	9a00      	ldr	r2, [sp, #0]
    5118:	07d2      	lsls	r2, r2, #31
    511a:	d5fa      	bpl.n	5112 <PkaAddAff+0x6>
    511c:	4b32      	ldr	r3, [pc, #200]	; (51e8 <PkaAddAff+0xdc>)
    511e:	4a33      	ldr	r2, [pc, #204]	; (51ec <PkaAddAff+0xe0>)
    5120:	601a      	str	r2, [r3, #0]
    5122:	680a      	ldr	r2, [r1, #0]
    5124:	9201      	str	r2, [sp, #4]
    5126:	9a01      	ldr	r2, [sp, #4]
    5128:	07d0      	lsls	r0, r2, #31
    512a:	d5fa      	bpl.n	5122 <PkaAddAff+0x16>
    512c:	4a30      	ldr	r2, [pc, #192]	; (51f0 <PkaAddAff+0xe4>)
    512e:	601a      	str	r2, [r3, #0]
    5130:	680a      	ldr	r2, [r1, #0]
    5132:	9202      	str	r2, [sp, #8]
    5134:	9a02      	ldr	r2, [sp, #8]
    5136:	07d2      	lsls	r2, r2, #31
    5138:	d5fa      	bpl.n	5130 <PkaAddAff+0x24>
    513a:	4a2e      	ldr	r2, [pc, #184]	; (51f4 <PkaAddAff+0xe8>)
    513c:	601a      	str	r2, [r3, #0]
    513e:	680a      	ldr	r2, [r1, #0]
    5140:	9203      	str	r2, [sp, #12]
    5142:	9a03      	ldr	r2, [sp, #12]
    5144:	07d0      	lsls	r0, r2, #31
    5146:	d5fa      	bpl.n	513e <PkaAddAff+0x32>
    5148:	4a2b      	ldr	r2, [pc, #172]	; (51f8 <PkaAddAff+0xec>)
    514a:	601a      	str	r2, [r3, #0]
    514c:	680a      	ldr	r2, [r1, #0]
    514e:	9204      	str	r2, [sp, #16]
    5150:	9a04      	ldr	r2, [sp, #16]
    5152:	07d2      	lsls	r2, r2, #31
    5154:	d5fa      	bpl.n	514c <PkaAddAff+0x40>
    5156:	4a29      	ldr	r2, [pc, #164]	; (51fc <PkaAddAff+0xf0>)
    5158:	601a      	str	r2, [r3, #0]
    515a:	680a      	ldr	r2, [r1, #0]
    515c:	9205      	str	r2, [sp, #20]
    515e:	9a05      	ldr	r2, [sp, #20]
    5160:	07d0      	lsls	r0, r2, #31
    5162:	d5fa      	bpl.n	515a <PkaAddAff+0x4e>
    5164:	4a26      	ldr	r2, [pc, #152]	; (5200 <PkaAddAff+0xf4>)
    5166:	601a      	str	r2, [r3, #0]
    5168:	680a      	ldr	r2, [r1, #0]
    516a:	9206      	str	r2, [sp, #24]
    516c:	9a06      	ldr	r2, [sp, #24]
    516e:	07d2      	lsls	r2, r2, #31
    5170:	d5fa      	bpl.n	5168 <PkaAddAff+0x5c>
    5172:	4a24      	ldr	r2, [pc, #144]	; (5204 <PkaAddAff+0xf8>)
    5174:	601a      	str	r2, [r3, #0]
    5176:	680a      	ldr	r2, [r1, #0]
    5178:	9207      	str	r2, [sp, #28]
    517a:	9a07      	ldr	r2, [sp, #28]
    517c:	07d0      	lsls	r0, r2, #31
    517e:	d5fa      	bpl.n	5176 <PkaAddAff+0x6a>
    5180:	4a21      	ldr	r2, [pc, #132]	; (5208 <PkaAddAff+0xfc>)
    5182:	601a      	str	r2, [r3, #0]
    5184:	680a      	ldr	r2, [r1, #0]
    5186:	9208      	str	r2, [sp, #32]
    5188:	9a08      	ldr	r2, [sp, #32]
    518a:	07d2      	lsls	r2, r2, #31
    518c:	d5fa      	bpl.n	5184 <PkaAddAff+0x78>
    518e:	4a1f      	ldr	r2, [pc, #124]	; (520c <PkaAddAff+0x100>)
    5190:	601a      	str	r2, [r3, #0]
    5192:	680a      	ldr	r2, [r1, #0]
    5194:	9209      	str	r2, [sp, #36]	; 0x24
    5196:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5198:	07d0      	lsls	r0, r2, #31
    519a:	d5fa      	bpl.n	5192 <PkaAddAff+0x86>
    519c:	4a1c      	ldr	r2, [pc, #112]	; (5210 <PkaAddAff+0x104>)
    519e:	601a      	str	r2, [r3, #0]
    51a0:	680a      	ldr	r2, [r1, #0]
    51a2:	920a      	str	r2, [sp, #40]	; 0x28
    51a4:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    51a6:	07d2      	lsls	r2, r2, #31
    51a8:	d5fa      	bpl.n	51a0 <PkaAddAff+0x94>
    51aa:	4a1a      	ldr	r2, [pc, #104]	; (5214 <PkaAddAff+0x108>)
    51ac:	601a      	str	r2, [r3, #0]
    51ae:	6808      	ldr	r0, [r1, #0]
    51b0:	900b      	str	r0, [sp, #44]	; 0x2c
    51b2:	980b      	ldr	r0, [sp, #44]	; 0x2c
    51b4:	07c0      	lsls	r0, r0, #31
    51b6:	d5fa      	bpl.n	51ae <PkaAddAff+0xa2>
    51b8:	601a      	str	r2, [r3, #0]
    51ba:	680a      	ldr	r2, [r1, #0]
    51bc:	920c      	str	r2, [sp, #48]	; 0x30
    51be:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    51c0:	07d0      	lsls	r0, r2, #31
    51c2:	d5fa      	bpl.n	51ba <PkaAddAff+0xae>
    51c4:	4a14      	ldr	r2, [pc, #80]	; (5218 <PkaAddAff+0x10c>)
    51c6:	601a      	str	r2, [r3, #0]
    51c8:	680a      	ldr	r2, [r1, #0]
    51ca:	920d      	str	r2, [sp, #52]	; 0x34
    51cc:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    51ce:	07d2      	lsls	r2, r2, #31
    51d0:	d5fa      	bpl.n	51c8 <PkaAddAff+0xbc>
    51d2:	4a12      	ldr	r2, [pc, #72]	; (521c <PkaAddAff+0x110>)
    51d4:	601a      	str	r2, [r3, #0]
    51d6:	210e      	movs	r1, #14
    51d8:	230d      	movs	r3, #13
    51da:	220f      	movs	r2, #15
    51dc:	2000      	movs	r0, #0
    51de:	b00e      	add	sp, #56	; 0x38
    51e0:	f7ff bf3c 	b.w	505c <PkaJcb2Afn>
    51e4:	5002b0b0 	.word	0x5002b0b0
    51e8:	5002b080 	.word	0x5002b080
    51ec:	29014380 	.word	0x29014380
    51f0:	21396340 	.word	0x21396340
    51f4:	29017080 	.word	0x29017080
    51f8:	21542080 	.word	0x21542080
    51fc:	9034d100 	.word	0x9034d100
    5200:	903440c0 	.word	0x903440c0
    5204:	292030c0 	.word	0x292030c0
    5208:	900d53c0 	.word	0x900d53c0
    520c:	90384100 	.word	0x90384100
    5210:	c8082383 	.word	0xc8082383
    5214:	2110e380 	.word	0x2110e380
    5218:	21384100 	.word	0x21384100
    521c:	c80843cf 	.word	0xc80843cf

00005220 <PkaSum2ScalarMullt>:
    5220:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5224:	2301      	movs	r3, #1
    5226:	b092      	sub	sp, #72	; 0x48
    5228:	e9cd 3303 	strd	r3, r3, [sp, #12]
    522c:	4b62      	ldr	r3, [pc, #392]	; (53b8 <PkaSum2ScalarMullt+0x198>)
    522e:	461d      	mov	r5, r3
    5230:	681a      	ldr	r2, [r3, #0]
    5232:	9205      	str	r2, [sp, #20]
    5234:	9a05      	ldr	r2, [sp, #20]
    5236:	07d2      	lsls	r2, r2, #31
    5238:	d5fa      	bpl.n	5230 <PkaSum2ScalarMullt+0x10>
    523a:	4c60      	ldr	r4, [pc, #384]	; (53bc <PkaSum2ScalarMullt+0x19c>)
    523c:	4b60      	ldr	r3, [pc, #384]	; (53c0 <PkaSum2ScalarMullt+0x1a0>)
    523e:	6023      	str	r3, [r4, #0]
    5240:	4b60      	ldr	r3, [pc, #384]	; (53c4 <PkaSum2ScalarMullt+0x1a4>)
    5242:	4619      	mov	r1, r3
    5244:	681a      	ldr	r2, [r3, #0]
    5246:	9206      	str	r2, [sp, #24]
    5248:	9a06      	ldr	r2, [sp, #24]
    524a:	07d7      	lsls	r7, r2, #31
    524c:	d5fa      	bpl.n	5244 <PkaSum2ScalarMullt+0x24>
    524e:	4b5e      	ldr	r3, [pc, #376]	; (53c8 <PkaSum2ScalarMullt+0x1a8>)
    5250:	681a      	ldr	r2, [r3, #0]
    5252:	04d6      	lsls	r6, r2, #19
    5254:	f100 80a8 	bmi.w	53a8 <PkaSum2ScalarMullt+0x188>
    5258:	682a      	ldr	r2, [r5, #0]
    525a:	9207      	str	r2, [sp, #28]
    525c:	9a07      	ldr	r2, [sp, #28]
    525e:	07d0      	lsls	r0, r2, #31
    5260:	d5fa      	bpl.n	5258 <PkaSum2ScalarMullt+0x38>
    5262:	4a5a      	ldr	r2, [pc, #360]	; (53cc <PkaSum2ScalarMullt+0x1ac>)
    5264:	6022      	str	r2, [r4, #0]
    5266:	680a      	ldr	r2, [r1, #0]
    5268:	9208      	str	r2, [sp, #32]
    526a:	9a08      	ldr	r2, [sp, #32]
    526c:	07d2      	lsls	r2, r2, #31
    526e:	d5fa      	bpl.n	5266 <PkaSum2ScalarMullt+0x46>
    5270:	681e      	ldr	r6, [r3, #0]
    5272:	f3c6 3600 	ubfx	r6, r6, #12, #1
    5276:	2e00      	cmp	r6, #0
    5278:	f040 8098 	bne.w	53ac <PkaSum2ScalarMullt+0x18c>
    527c:	2012      	movs	r0, #18
    527e:	f7ff f8f9 	bl	4474 <PkaGetRegEffectiveSizeInBits>
    5282:	4607      	mov	r7, r0
    5284:	2013      	movs	r0, #19
    5286:	f7ff f8f5 	bl	4474 <PkaGetRegEffectiveSizeInBits>
    528a:	4287      	cmp	r7, r0
    528c:	bf8c      	ite	hi
    528e:	2012      	movhi	r0, #18
    5290:	2013      	movls	r0, #19
    5292:	f7ff f8ef 	bl	4474 <PkaGetRegEffectiveSizeInBits>
    5296:	1e47      	subs	r7, r0, #1
    5298:	f7ff ff38 	bl	510c <PkaAddAff>
    529c:	ab03      	add	r3, sp, #12
    529e:	aa01      	add	r2, sp, #4
    52a0:	4639      	mov	r1, r7
    52a2:	2012      	movs	r0, #18
    52a4:	f7ff f92c 	bl	4500 <PkaGetNextMsBit>
    52a8:	ab04      	add	r3, sp, #16
    52aa:	4680      	mov	r8, r0
    52ac:	aa02      	add	r2, sp, #8
    52ae:	4639      	mov	r1, r7
    52b0:	2013      	movs	r0, #19
    52b2:	f7ff f925 	bl	4500 <PkaGetNextMsBit>
    52b6:	eb00 0048 	add.w	r0, r0, r8, lsl #1
    52ba:	2802      	cmp	r0, #2
    52bc:	d032      	beq.n	5324 <PkaSum2ScalarMullt+0x104>
    52be:	2803      	cmp	r0, #3
    52c0:	d03e      	beq.n	5340 <PkaSum2ScalarMullt+0x120>
    52c2:	2801      	cmp	r0, #1
    52c4:	d174      	bne.n	53b0 <PkaSum2ScalarMullt+0x190>
    52c6:	682b      	ldr	r3, [r5, #0]
    52c8:	9309      	str	r3, [sp, #36]	; 0x24
    52ca:	9b09      	ldr	r3, [sp, #36]	; 0x24
    52cc:	07db      	lsls	r3, r3, #31
    52ce:	d5fa      	bpl.n	52c6 <PkaSum2ScalarMullt+0xa6>
    52d0:	4b3f      	ldr	r3, [pc, #252]	; (53d0 <PkaSum2ScalarMullt+0x1b0>)
    52d2:	6023      	str	r3, [r4, #0]
    52d4:	682b      	ldr	r3, [r5, #0]
    52d6:	930a      	str	r3, [sp, #40]	; 0x28
    52d8:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    52da:	07d8      	lsls	r0, r3, #31
    52dc:	d5fa      	bpl.n	52d4 <PkaSum2ScalarMullt+0xb4>
    52de:	4b3d      	ldr	r3, [pc, #244]	; (53d4 <PkaSum2ScalarMullt+0x1b4>)
    52e0:	6023      	str	r3, [r4, #0]
    52e2:	682b      	ldr	r3, [r5, #0]
    52e4:	930f      	str	r3, [sp, #60]	; 0x3c
    52e6:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    52e8:	07d9      	lsls	r1, r3, #31
    52ea:	d5fa      	bpl.n	52e2 <PkaSum2ScalarMullt+0xc2>
    52ec:	4b3a      	ldr	r3, [pc, #232]	; (53d8 <PkaSum2ScalarMullt+0x1b8>)
    52ee:	6023      	str	r3, [r4, #0]
    52f0:	682b      	ldr	r3, [r5, #0]
    52f2:	9310      	str	r3, [sp, #64]	; 0x40
    52f4:	9b10      	ldr	r3, [sp, #64]	; 0x40
    52f6:	07da      	lsls	r2, r3, #31
    52f8:	d5fa      	bpl.n	52f0 <PkaSum2ScalarMullt+0xd0>
    52fa:	4b38      	ldr	r3, [pc, #224]	; (53dc <PkaSum2ScalarMullt+0x1bc>)
    52fc:	6023      	str	r3, [r4, #0]
    52fe:	682b      	ldr	r3, [r5, #0]
    5300:	9311      	str	r3, [sp, #68]	; 0x44
    5302:	9b11      	ldr	r3, [sp, #68]	; 0x44
    5304:	07db      	lsls	r3, r3, #31
    5306:	d5fa      	bpl.n	52fe <PkaSum2ScalarMullt+0xde>
    5308:	4b35      	ldr	r3, [pc, #212]	; (53e0 <PkaSum2ScalarMullt+0x1c0>)
    530a:	6023      	str	r3, [r4, #0]
    530c:	3f01      	subs	r7, #1
    530e:	d525      	bpl.n	535c <PkaSum2ScalarMullt+0x13c>
    5310:	2310      	movs	r3, #16
    5312:	2219      	movs	r2, #25
    5314:	2118      	movs	r1, #24
    5316:	2000      	movs	r0, #0
    5318:	f7ff fea0 	bl	505c <PkaJcb2Afn>
    531c:	4630      	mov	r0, r6
    531e:	b012      	add	sp, #72	; 0x48
    5320:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5324:	682b      	ldr	r3, [r5, #0]
    5326:	930b      	str	r3, [sp, #44]	; 0x2c
    5328:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
    532a:	07d9      	lsls	r1, r3, #31
    532c:	d5fa      	bpl.n	5324 <PkaSum2ScalarMullt+0x104>
    532e:	4b2d      	ldr	r3, [pc, #180]	; (53e4 <PkaSum2ScalarMullt+0x1c4>)
    5330:	6023      	str	r3, [r4, #0]
    5332:	682b      	ldr	r3, [r5, #0]
    5334:	930c      	str	r3, [sp, #48]	; 0x30
    5336:	9b0c      	ldr	r3, [sp, #48]	; 0x30
    5338:	07da      	lsls	r2, r3, #31
    533a:	d5fa      	bpl.n	5332 <PkaSum2ScalarMullt+0x112>
    533c:	4b2a      	ldr	r3, [pc, #168]	; (53e8 <PkaSum2ScalarMullt+0x1c8>)
    533e:	e7cf      	b.n	52e0 <PkaSum2ScalarMullt+0xc0>
    5340:	682b      	ldr	r3, [r5, #0]
    5342:	930d      	str	r3, [sp, #52]	; 0x34
    5344:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    5346:	07db      	lsls	r3, r3, #31
    5348:	d5fa      	bpl.n	5340 <PkaSum2ScalarMullt+0x120>
    534a:	4b28      	ldr	r3, [pc, #160]	; (53ec <PkaSum2ScalarMullt+0x1cc>)
    534c:	6023      	str	r3, [r4, #0]
    534e:	682b      	ldr	r3, [r5, #0]
    5350:	930e      	str	r3, [sp, #56]	; 0x38
    5352:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    5354:	07d8      	lsls	r0, r3, #31
    5356:	d5fa      	bpl.n	534e <PkaSum2ScalarMullt+0x12e>
    5358:	4b25      	ldr	r3, [pc, #148]	; (53f0 <PkaSum2ScalarMullt+0x1d0>)
    535a:	e7c1      	b.n	52e0 <PkaSum2ScalarMullt+0xc0>
    535c:	ab03      	add	r3, sp, #12
    535e:	aa01      	add	r2, sp, #4
    5360:	4639      	mov	r1, r7
    5362:	2012      	movs	r0, #18
    5364:	f7ff f8cc 	bl	4500 <PkaGetNextMsBit>
    5368:	ab04      	add	r3, sp, #16
    536a:	4604      	mov	r4, r0
    536c:	aa02      	add	r2, sp, #8
    536e:	4639      	mov	r1, r7
    5370:	2013      	movs	r0, #19
    5372:	f7ff f8c5 	bl	4500 <PkaGetNextMsBit>
    5376:	eb10 0444 	adds.w	r4, r0, r4, lsl #1
    537a:	d102      	bne.n	5382 <PkaSum2ScalarMullt+0x162>
    537c:	f7ff fc12 	bl	4ba4 <PkaDoubleMdf2Mdf>
    5380:	e7c4      	b.n	530c <PkaSum2ScalarMullt+0xec>
    5382:	f7ff fce5 	bl	4d50 <PkaDoubleMdf2Jcb>
    5386:	2c02      	cmp	r4, #2
    5388:	d008      	beq.n	539c <PkaSum2ScalarMullt+0x17c>
    538a:	2c03      	cmp	r4, #3
    538c:	d009      	beq.n	53a2 <PkaSum2ScalarMullt+0x182>
    538e:	2c01      	cmp	r4, #1
    5390:	d110      	bne.n	53b4 <PkaSum2ScalarMullt+0x194>
    5392:	2117      	movs	r1, #23
    5394:	2016      	movs	r0, #22
    5396:	f7ff fd97 	bl	4ec8 <PkaAddJcbAfn2Mdf>
    539a:	e7b7      	b.n	530c <PkaSum2ScalarMullt+0xec>
    539c:	2115      	movs	r1, #21
    539e:	2014      	movs	r0, #20
    53a0:	e7f9      	b.n	5396 <PkaSum2ScalarMullt+0x176>
    53a2:	210f      	movs	r1, #15
    53a4:	200e      	movs	r0, #14
    53a6:	e7f6      	b.n	5396 <PkaSum2ScalarMullt+0x176>
    53a8:	4e12      	ldr	r6, [pc, #72]	; (53f4 <PkaSum2ScalarMullt+0x1d4>)
    53aa:	e7b7      	b.n	531c <PkaSum2ScalarMullt+0xfc>
    53ac:	4e12      	ldr	r6, [pc, #72]	; (53f8 <PkaSum2ScalarMullt+0x1d8>)
    53ae:	e7b5      	b.n	531c <PkaSum2ScalarMullt+0xfc>
    53b0:	4e12      	ldr	r6, [pc, #72]	; (53fc <PkaSum2ScalarMullt+0x1dc>)
    53b2:	e7b3      	b.n	531c <PkaSum2ScalarMullt+0xfc>
    53b4:	4e12      	ldr	r6, [pc, #72]	; (5400 <PkaSum2ScalarMullt+0x1e0>)
    53b6:	e7b1      	b.n	531c <PkaSum2ScalarMullt+0xfc>
    53b8:	5002b0b0 	.word	0x5002b0b0
    53bc:	5002b080 	.word	0x5002b080
    53c0:	514a0800 	.word	0x514a0800
    53c4:	5002b0b4 	.word	0x5002b0b4
    53c8:	5002b088 	.word	0x5002b088
    53cc:	514e0800 	.word	0x514e0800
    53d0:	495a0600 	.word	0x495a0600
    53d4:	495e0640 	.word	0x495e0640
    53d8:	41420400 	.word	0x41420400
    53dc:	49421400 	.word	0x49421400
    53e0:	492e0440 	.word	0x492e0440
    53e4:	49520600 	.word	0x49520600
    53e8:	49560640 	.word	0x49560640
    53ec:	493a0600 	.word	0x493a0600
    53f0:	493e0640 	.word	0x493e0640
    53f4:	00f10806 	.word	0x00f10806
    53f8:	00f10807 	.word	0x00f10807
    53fc:	00f10804 	.word	0x00f10804
    5400:	00f10805 	.word	0x00f10805

00005404 <SaSi_HalClearInterruptBit>:
    5404:	4b01      	ldr	r3, [pc, #4]	; (540c <SaSi_HalClearInterruptBit+0x8>)
    5406:	6018      	str	r0, [r3, #0]
    5408:	4770      	bx	lr
    540a:	bf00      	nop
    540c:	5002ba08 	.word	0x5002ba08

00005410 <SaSi_HalMaskInterrupt>:
    5410:	4b01      	ldr	r3, [pc, #4]	; (5418 <SaSi_HalMaskInterrupt+0x8>)
    5412:	6018      	str	r0, [r3, #0]
    5414:	4770      	bx	lr
    5416:	bf00      	nop
    5418:	5002ba04 	.word	0x5002ba04

0000541c <SaSi_HalWaitInterrupt>:
    541c:	4a03      	ldr	r2, [pc, #12]	; (542c <SaSi_HalWaitInterrupt+0x10>)
    541e:	6813      	ldr	r3, [r2, #0]
    5420:	4218      	tst	r0, r3
    5422:	d0fc      	beq.n	541e <SaSi_HalWaitInterrupt+0x2>
    5424:	4a02      	ldr	r2, [pc, #8]	; (5430 <SaSi_HalWaitInterrupt+0x14>)
    5426:	6010      	str	r0, [r2, #0]
    5428:	4618      	mov	r0, r3
    542a:	4770      	bx	lr
    542c:	5002ba00 	.word	0x5002ba00
    5430:	5002ba08 	.word	0x5002ba08

00005434 <flash_device_base>:
    if (fd_id != FLASH_DEVICE_ID) {
    5434:	b908      	cbnz	r0, 543a <flash_device_base+0x6>
    *ret = FLASH_DEVICE_BASE;
    5436:	6008      	str	r0, [r1, #0]
    return 0;
    5438:	4770      	bx	lr
        return -EINVAL;
    543a:	f06f 0015 	mvn.w	r0, #21
}
    543e:	4770      	bx	lr

00005440 <flash_area_id_from_multi_image_slot>:
    switch (slot) {
    5440:	4608      	mov	r0, r1
    5442:	b129      	cbz	r1, 5450 <flash_area_id_from_multi_image_slot+0x10>
    return -EINVAL; /* flash_area_open will fail on that */
    5444:	2901      	cmp	r1, #1
    5446:	bf0c      	ite	eq
    5448:	4608      	moveq	r0, r1
    544a:	f06f 0015 	mvnne.w	r0, #21
    544e:	4770      	bx	lr
    case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
    5450:	2003      	movs	r0, #3
}
    5452:	4770      	bx	lr

00005454 <flash_area_get_device_id>:

uint8_t flash_area_get_device_id(const struct flash_area *fa)
{
	(void)fa;
	return FLASH_DEVICE_ID;
}
    5454:	2000      	movs	r0, #0
    5456:	4770      	bx	lr

00005458 <os_heap_init>:
    mbedtls_memory_buffer_alloc_init(mempool, sizeof(mempool));
}
#else
void os_heap_init(void)
{
}
    5458:	4770      	bx	lr

0000545a <bootutil_tlv_iter_begin>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_begin(struct image_tlv_iter *it, const struct image_header *hdr,
                        const struct flash_area *fap, uint16_t type, bool prot)
{
    545a:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    545e:	460e      	mov	r6, r1
    5460:	4617      	mov	r7, r2
    5462:	4699      	mov	r9, r3
    uint32_t off_;
    struct image_tlv_info info;

    if (it == NULL || hdr == NULL || fap == NULL) {
    5464:	4604      	mov	r4, r0
    5466:	b928      	cbnz	r0, 5474 <bootutil_tlv_iter_begin+0x1a>
        return -1;
    5468:	f04f 38ff 	mov.w	r8, #4294967295
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    // position on first TLV
    it->tlv_off = off_ + sizeof(info);
    return 0;
}
    546c:	4640      	mov	r0, r8
    546e:	b003      	add	sp, #12
    5470:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || hdr == NULL || fap == NULL) {
    5474:	2900      	cmp	r1, #0
    5476:	d0f7      	beq.n	5468 <bootutil_tlv_iter_begin+0xe>
    5478:	2a00      	cmp	r2, #0
    547a:	d0f5      	beq.n	5468 <bootutil_tlv_iter_begin+0xe>
    off_ = BOOT_TLV_OFF(hdr);
    547c:	68cb      	ldr	r3, [r1, #12]
    547e:	890d      	ldrh	r5, [r1, #8]
    5480:	441d      	add	r5, r3
    if (LOAD_IMAGE_DATA(hdr, fap, off_, &info, sizeof(info))) {
    5482:	2304      	movs	r3, #4
    5484:	eb0d 0203 	add.w	r2, sp, r3
    5488:	4629      	mov	r1, r5
    548a:	4638      	mov	r0, r7
    548c:	f000 fcca 	bl	5e24 <flash_area_read>
    5490:	4680      	mov	r8, r0
    5492:	2800      	cmp	r0, #0
    5494:	d1e8      	bne.n	5468 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5496:	f8bd 1004 	ldrh.w	r1, [sp, #4]
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    549a:	8973      	ldrh	r3, [r6, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    549c:	f646 1208 	movw	r2, #26888	; 0x6908
    54a0:	4291      	cmp	r1, r2
    54a2:	d125      	bne.n	54f0 <bootutil_tlv_iter_begin+0x96>
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    54a4:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    54a8:	4299      	cmp	r1, r3
    54aa:	d1dd      	bne.n	5468 <bootutil_tlv_iter_begin+0xe>
        if (LOAD_IMAGE_DATA(hdr, fap, off_ + info.it_tlv_tot,
    54ac:	2304      	movs	r3, #4
    54ae:	eb0d 0203 	add.w	r2, sp, r3
    54b2:	4429      	add	r1, r5
    54b4:	4638      	mov	r0, r7
    54b6:	f000 fcb5 	bl	5e24 <flash_area_read>
    54ba:	2800      	cmp	r0, #0
    54bc:	d1d4      	bne.n	5468 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    54be:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    54c2:	f646 1307 	movw	r3, #26887	; 0x6907
    54c6:	429a      	cmp	r2, r3
    54c8:	d1ce      	bne.n	5468 <bootutil_tlv_iter_begin+0xe>
    it->fap = fap;
    54ca:	e9c4 6700 	strd	r6, r7, [r4]
    it->prot = prot;
    54ce:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
    it->type = type;
    54d2:	f8a4 9008 	strh.w	r9, [r4, #8]
    it->prot = prot;
    54d6:	72a3      	strb	r3, [r4, #10]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    54d8:	8973      	ldrh	r3, [r6, #10]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    54da:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    54de:	442b      	add	r3, r5
    54e0:	60e3      	str	r3, [r4, #12]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    54e2:	8973      	ldrh	r3, [r6, #10]
    54e4:	4413      	add	r3, r2
    54e6:	442b      	add	r3, r5
    it->tlv_off = off_ + sizeof(info);
    54e8:	3504      	adds	r5, #4
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    54ea:	6163      	str	r3, [r4, #20]
    it->tlv_off = off_ + sizeof(info);
    54ec:	6125      	str	r5, [r4, #16]
    return 0;
    54ee:	e7bd      	b.n	546c <bootutil_tlv_iter_begin+0x12>
    } else if (hdr->ih_protect_tlv_size != 0) {
    54f0:	2b00      	cmp	r3, #0
    54f2:	d0e4      	beq.n	54be <bootutil_tlv_iter_begin+0x64>
    54f4:	e7b8      	b.n	5468 <bootutil_tlv_iter_begin+0xe>

000054f6 <bootutil_tlv_iter_next>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off, uint16_t *len,
                       uint16_t *type)
{
    54f6:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    54fa:	460e      	mov	r6, r1
    54fc:	4617      	mov	r7, r2
    54fe:	461d      	mov	r5, r3
    struct image_tlv tlv;
    int rc;

    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    5500:	4604      	mov	r4, r0
    5502:	b920      	cbnz	r0, 550e <bootutil_tlv_iter_next+0x18>
        return -1;
    5504:	f04f 30ff 	mov.w	r0, #4294967295

        it->tlv_off += sizeof(tlv) + tlv.it_len;
    }

    return 1;
}
    5508:	b002      	add	sp, #8
    550a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    550e:	6803      	ldr	r3, [r0, #0]
    5510:	2b00      	cmp	r3, #0
    5512:	d0f7      	beq.n	5504 <bootutil_tlv_iter_next+0xe>
    5514:	6843      	ldr	r3, [r0, #4]
    5516:	2b00      	cmp	r3, #0
    5518:	d0f4      	beq.n	5504 <bootutil_tlv_iter_next+0xe>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    551a:	f64f 78ff 	movw	r8, #65535	; 0xffff
    while (it->tlv_off < it->tlv_end) {
    551e:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    5522:	429a      	cmp	r2, r3
    5524:	d216      	bcs.n	5554 <bootutil_tlv_iter_next+0x5e>
        if (it->hdr->ih_protect_tlv_size > 0 && it->tlv_off == it->prot_end) {
    5526:	6823      	ldr	r3, [r4, #0]
    5528:	895b      	ldrh	r3, [r3, #10]
    552a:	b123      	cbz	r3, 5536 <bootutil_tlv_iter_next+0x40>
    552c:	68e3      	ldr	r3, [r4, #12]
    552e:	4293      	cmp	r3, r2
            it->tlv_off += sizeof(struct image_tlv_info);
    5530:	bf04      	itt	eq
    5532:	3304      	addeq	r3, #4
    5534:	6123      	streq	r3, [r4, #16]
        rc = LOAD_IMAGE_DATA(it->hdr, it->fap, it->tlv_off, &tlv, sizeof tlv);
    5536:	2304      	movs	r3, #4
    5538:	6921      	ldr	r1, [r4, #16]
    553a:	6860      	ldr	r0, [r4, #4]
    553c:	eb0d 0203 	add.w	r2, sp, r3
    5540:	f000 fc70 	bl	5e24 <flash_area_read>
        if (rc) {
    5544:	2800      	cmp	r0, #0
    5546:	d1dd      	bne.n	5504 <bootutil_tlv_iter_next+0xe>
        if (it->prot && it->tlv_off >= it->prot_end) {
    5548:	7aa3      	ldrb	r3, [r4, #10]
    554a:	b12b      	cbz	r3, 5558 <bootutil_tlv_iter_next+0x62>
    554c:	e9d4 3203 	ldrd	r3, r2, [r4, #12]
    5550:	429a      	cmp	r2, r3
    5552:	d301      	bcc.n	5558 <bootutil_tlv_iter_next+0x62>
            return 1;
    5554:	2001      	movs	r0, #1
    5556:	e7d7      	b.n	5508 <bootutil_tlv_iter_next+0x12>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    5558:	8923      	ldrh	r3, [r4, #8]
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    555a:	f8bd 1006 	ldrh.w	r1, [sp, #6]
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    555e:	4543      	cmp	r3, r8
    5560:	f101 0204 	add.w	r2, r1, #4
    5564:	d003      	beq.n	556e <bootutil_tlv_iter_next+0x78>
    5566:	f8bd c004 	ldrh.w	ip, [sp, #4]
    556a:	459c      	cmp	ip, r3
    556c:	d10b      	bne.n	5586 <bootutil_tlv_iter_next+0x90>
            if (type != NULL) {
    556e:	b115      	cbz	r5, 5576 <bootutil_tlv_iter_next+0x80>
                *type = tlv.it_type;
    5570:	f8bd 3004 	ldrh.w	r3, [sp, #4]
    5574:	802b      	strh	r3, [r5, #0]
            *off = it->tlv_off + sizeof(tlv);
    5576:	6923      	ldr	r3, [r4, #16]
    5578:	3304      	adds	r3, #4
    557a:	6033      	str	r3, [r6, #0]
            *len = tlv.it_len;
    557c:	8039      	strh	r1, [r7, #0]
            it->tlv_off += sizeof(tlv) + tlv.it_len;
    557e:	6923      	ldr	r3, [r4, #16]
    5580:	4413      	add	r3, r2
    5582:	6123      	str	r3, [r4, #16]
            return 0;
    5584:	e7c0      	b.n	5508 <bootutil_tlv_iter_next+0x12>
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    5586:	6923      	ldr	r3, [r4, #16]
    5588:	4413      	add	r3, r2
    558a:	6123      	str	r3, [r4, #16]
    558c:	e7c7      	b.n	551e <bootutil_tlv_iter_next+0x28>

0000558e <bootutil_read_bigint>:
{
    558e:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5590:	460c      	mov	r4, r1
    5592:	4606      	mov	r6, r0
    5594:	4611      	mov	r1, r2
    if (mbedtls_asn1_get_tag(cp, end, &len, MBEDTLS_ASN1_INTEGER)) {
    5596:	2302      	movs	r3, #2
    5598:	aa01      	add	r2, sp, #4
    559a:	4620      	mov	r0, r4
    559c:	f000 fad9 	bl	5b52 <mbedtls_asn1_get_tag>
    55a0:	4605      	mov	r5, r0
    55a2:	b9e8      	cbnz	r0, 55e0 <bootutil_read_bigint+0x52>
    if (len >= NUM_ECC_BYTES) {
    55a4:	9a01      	ldr	r2, [sp, #4]
    55a6:	2a1f      	cmp	r2, #31
    55a8:	d90e      	bls.n	55c8 <bootutil_read_bigint+0x3a>
        memcpy(i, *cp + len - NUM_ECC_BYTES, NUM_ECC_BYTES);
    55aa:	6823      	ldr	r3, [r4, #0]
    55ac:	f1a2 0120 	sub.w	r1, r2, #32
    55b0:	4419      	add	r1, r3
    55b2:	2220      	movs	r2, #32
    55b4:	4630      	mov	r0, r6
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    55b6:	f000 fcdf 	bl	5f78 <memcpy>
    *cp += len;
    55ba:	6823      	ldr	r3, [r4, #0]
    55bc:	9a01      	ldr	r2, [sp, #4]
    55be:	4413      	add	r3, r2
    55c0:	6023      	str	r3, [r4, #0]
}
    55c2:	4628      	mov	r0, r5
    55c4:	b002      	add	sp, #8
    55c6:	bd70      	pop	{r4, r5, r6, pc}
        memset(i, 0, NUM_ECC_BYTES - len);
    55c8:	4601      	mov	r1, r0
    55ca:	f1c2 0220 	rsb	r2, r2, #32
    55ce:	4630      	mov	r0, r6
    55d0:	f000 fcdd 	bl	5f8e <memset>
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    55d4:	9a01      	ldr	r2, [sp, #4]
    55d6:	6821      	ldr	r1, [r4, #0]
    55d8:	f1c2 0020 	rsb	r0, r2, #32
    55dc:	4430      	add	r0, r6
    55de:	e7ea      	b.n	55b6 <bootutil_read_bigint+0x28>
        return -3;
    55e0:	f06f 0502 	mvn.w	r5, #2
    55e4:	e7ed      	b.n	55c2 <bootutil_read_bigint+0x34>

000055e6 <boot_fih_memequal>:
    return memcmp(s1, s2, n);
    55e6:	f000 bca0 	b.w	5f2a <memcmp>

000055ea <boot_trailer_sz>:
    return BOOT_STATUS_MAX_ENTRIES * boot_status_entry_sz(min_write_sz);
    55ea:	f44f 7340 	mov.w	r3, #768	; 0x300
    55ee:	4358      	muls	r0, r3
}
    55f0:	3030      	adds	r0, #48	; 0x30
    55f2:	4770      	bx	lr

000055f4 <boot_status_entries>:
    if (flash_area_get_id(fap) == FLASH_AREA_IMAGE_PRIMARY(image_index) ||
    55f4:	780b      	ldrb	r3, [r1, #0]
    55f6:	f003 03fd 	and.w	r3, r3, #253	; 0xfd
    return -1;
    55fa:	2b01      	cmp	r3, #1
}
    55fc:	bf0c      	ite	eq
    55fe:	f44f 7040 	moveq.w	r0, #768	; 0x300
    5602:	f04f 30ff 	movne.w	r0, #4294967295
    5606:	4770      	bx	lr

00005608 <boot_status_off>:
{
    5608:	b510      	push	{r4, lr}
    560a:	4604      	mov	r4, r0
    elem_sz = flash_area_align(fap);
    560c:	f000 fc4a 	bl	5ea4 <flash_area_align>
    return flash_area_get_size(fap) - off_from_end;
    5610:	68a3      	ldr	r3, [r4, #8]
}
    5612:	f44f 7240 	mov.w	r2, #768	; 0x300
    return flash_area_get_size(fap) - off_from_end;
    5616:	3b30      	subs	r3, #48	; 0x30
}
    5618:	fb02 3010 	mls	r0, r2, r0, r3
    561c:	bd10      	pop	{r4, pc}

0000561e <boot_write_copy_done>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    561e:	6881      	ldr	r1, [r0, #8]
    5620:	3918      	subs	r1, #24
    5622:	f021 0107 	bic.w	r1, r1, #7

    off = boot_copy_done_off(fap);
    BOOT_LOG_DBG("writing copy_done; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    5626:	2201      	movs	r2, #1
    5628:	3908      	subs	r1, #8
    562a:	f000 bf62 	b.w	64f2 <boot_write_trailer_flag>

0000562e <boot_write_swap_size>:
}

int
boot_write_swap_size(const struct flash_area *fap, uint32_t swap_size)
{
    562e:	b513      	push	{r0, r1, r4, lr}
    5630:	4604      	mov	r4, r0
    5632:	9101      	str	r1, [sp, #4]
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
    5634:	f000 feee 	bl	6414 <boot_swap_info_off>

    off = boot_swap_size_off(fap);
    BOOT_LOG_DBG("writing swap_size; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)flash_area_get_off(fap) + off);
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_size, 4);
    5638:	2304      	movs	r3, #4
    563a:	f1a0 0108 	sub.w	r1, r0, #8
    563e:	eb0d 0203 	add.w	r2, sp, r3
    5642:	4620      	mov	r0, r4
    5644:	f000 ff29 	bl	649a <boot_write_trailer>
}
    5648:	b002      	add	sp, #8
    564a:	bd10      	pop	{r4, pc}

0000564c <bootutil_max_image_size>:
    return 0;
}
#endif

uint32_t bootutil_max_image_size(const struct flash_area *fap)
{
    564c:	b507      	push	{r0, r1, r2, lr}
#if defined(MCUBOOT_SWAP_USING_SCRATCH)
    return boot_status_off(fap);
#elif defined(MCUBOOT_SWAP_USING_MOVE)
    struct flash_sector sector;
    /* get the last sector offset */
    int rc = flash_area_sector_from_off(boot_status_off(fap), &sector);
    564e:	f7ff ffdb 	bl	5608 <boot_status_off>
    5652:	4669      	mov	r1, sp
    5654:	f7fa fd9a 	bl	18c <flash_area_sector_from_off>
    if (rc) {
    5658:	b918      	cbnz	r0, 5662 <bootutil_max_image_size+0x16>
    565a:	9800      	ldr	r0, [sp, #0]
#elif defined(MCUBOOT_DIRECT_XIP)
    return boot_swap_info_off(fap);
#elif defined(MCUBOOT_RAM_LOAD)
    return boot_swap_info_off(fap);
#endif
}
    565c:	b003      	add	sp, #12
    565e:	f85d fb04 	ldr.w	pc, [sp], #4
        return 0; /* Returning of zero here should cause any check which uses
    5662:	2000      	movs	r0, #0
    5664:	e7fa      	b.n	565c <bootutil_max_image_size+0x10>

00005666 <boot_read_image_headers>:
{
    5666:	b570      	push	{r4, r5, r6, lr}
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5668:	4613      	mov	r3, r2
{
    566a:	460e      	mov	r6, r1
    566c:	4615      	mov	r5, r2
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    566e:	2100      	movs	r1, #0
    5670:	4602      	mov	r2, r0
{
    5672:	4604      	mov	r4, r0
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5674:	f7fb f964 	bl	940 <boot_read_image_header>
        if (rc != 0) {
    5678:	b950      	cbnz	r0, 5690 <boot_read_image_headers+0x2a>
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    567a:	462b      	mov	r3, r5
    567c:	f104 022c 	add.w	r2, r4, #44	; 0x2c
    5680:	2101      	movs	r1, #1
    5682:	4620      	mov	r0, r4
    5684:	f7fb f95c 	bl	940 <boot_read_image_header>
        if (rc != 0) {
    5688:	b110      	cbz	r0, 5690 <boot_read_image_headers+0x2a>
                return 0;
    568a:	2e00      	cmp	r6, #0
    568c:	bf08      	it	eq
    568e:	2000      	moveq	r0, #0
}
    5690:	bd70      	pop	{r4, r5, r6, pc}

00005692 <boot_read_image_size.constprop.0.isra.0>:
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    5692:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5694:	4604      	mov	r4, r0
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    5696:	2000      	movs	r0, #0
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    5698:	460d      	mov	r5, r1
    569a:	4616      	mov	r6, r2
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    569c:	f7ff fed0 	bl	5440 <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
    56a0:	4669      	mov	r1, sp
    56a2:	b2c0      	uxtb	r0, r0
    56a4:	f7fb fc28 	bl	ef8 <flash_area_open>
    if (rc != 0) {
    56a8:	bb30      	cbnz	r0, 56f8 <boot_read_image_size.constprop.0.isra.0+0x66>
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    56aa:	232c      	movs	r3, #44	; 0x2c
    56ac:	fb03 4405 	mla	r4, r3, r5, r4
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    56b0:	9800      	ldr	r0, [sp, #0]
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    56b2:	68e3      	ldr	r3, [r4, #12]
    56b4:	8925      	ldrh	r5, [r4, #8]
    56b6:	441d      	add	r5, r3
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    56b8:	2304      	movs	r3, #4
    56ba:	eb0d 0203 	add.w	r2, sp, r3
    56be:	4629      	mov	r1, r5
    56c0:	f000 fbb0 	bl	5e24 <flash_area_read>
    56c4:	b9c0      	cbnz	r0, 56f8 <boot_read_image_size.constprop.0.isra.0+0x66>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    56c6:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    protect_tlv_size = boot_img_hdr(state, slot)->ih_protect_tlv_size;
    56ca:	8964      	ldrh	r4, [r4, #10]
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    56cc:	9800      	ldr	r0, [sp, #0]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    56ce:	f646 1308 	movw	r3, #26888	; 0x6908
    56d2:	429a      	cmp	r2, r3
    56d4:	d115      	bne.n	5702 <boot_read_image_size.constprop.0.isra.0+0x70>
        if (protect_tlv_size != info.it_tlv_tot) {
    56d6:	f8bd 3006 	ldrh.w	r3, [sp, #6]
    56da:	429c      	cmp	r4, r3
    56dc:	d10c      	bne.n	56f8 <boot_read_image_size.constprop.0.isra.0+0x66>
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    56de:	2304      	movs	r3, #4
    56e0:	eb0d 0203 	add.w	r2, sp, r3
    56e4:	1961      	adds	r1, r4, r5
    56e6:	f000 fb9d 	bl	5e24 <flash_area_read>
    56ea:	b928      	cbnz	r0, 56f8 <boot_read_image_size.constprop.0.isra.0+0x66>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    56ec:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    56f0:	f646 1307 	movw	r3, #26887	; 0x6907
    56f4:	429a      	cmp	r2, r3
    56f6:	d007      	beq.n	5708 <boot_read_image_size.constprop.0.isra.0+0x76>
    flash_area_close(fap);
    56f8:	9800      	ldr	r0, [sp, #0]
    56fa:	f000 fb92 	bl	5e22 <flash_area_close>
}
    56fe:	b002      	add	sp, #8
    5700:	bd70      	pop	{r4, r5, r6, pc}
    } else if (protect_tlv_size != 0) {
    5702:	2c00      	cmp	r4, #0
    5704:	d0f2      	beq.n	56ec <boot_read_image_size.constprop.0.isra.0+0x5a>
    5706:	e7f7      	b.n	56f8 <boot_read_image_size.constprop.0.isra.0+0x66>
    *size = off + protect_tlv_size + info.it_tlv_tot;
    5708:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    570c:	4421      	add	r1, r4
    570e:	4429      	add	r1, r5
    5710:	6031      	str	r1, [r6, #0]
    rc = 0;
    5712:	e7f1      	b.n	56f8 <boot_read_image_size.constprop.0.isra.0+0x66>

00005714 <boot_read_sectors>:
{
    5714:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5716:	4604      	mov	r4, r0
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5718:	6a42      	ldr	r2, [r0, #36]	; 0x24
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    571a:	f44f 7580 	mov.w	r5, #256	; 0x100
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    571e:	a901      	add	r1, sp, #4
    5720:	2003      	movs	r0, #3
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    5722:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5724:	f7fb fc10 	bl	f48 <flash_area_get_sectors>
    if (rc != 0) {
    5728:	b958      	cbnz	r0, 5742 <boot_read_sectors+0x2e>
    *out_num_sectors = num_sectors;
    572a:	9b01      	ldr	r3, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    572c:	6d22      	ldr	r2, [r4, #80]	; 0x50
    *out_num_sectors = num_sectors;
    572e:	62a3      	str	r3, [r4, #40]	; 0x28
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5730:	a901      	add	r1, sp, #4
    5732:	2001      	movs	r0, #1
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    5734:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5736:	f7fb fc07 	bl	f48 <flash_area_get_sectors>
    if (rc != 0) {
    573a:	4605      	mov	r5, r0
    573c:	b128      	cbz	r0, 574a <boot_read_sectors+0x36>
        return BOOT_EFLASH_SEC;
    573e:	2509      	movs	r5, #9
    5740:	e000      	b.n	5744 <boot_read_sectors+0x30>
        return BOOT_EFLASH;
    5742:	2501      	movs	r5, #1
}
    5744:	4628      	mov	r0, r5
    5746:	b003      	add	sp, #12
    5748:	bd30      	pop	{r4, r5, pc}
    *out_num_sectors = num_sectors;
    574a:	9b01      	ldr	r3, [sp, #4]
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    574c:	6a20      	ldr	r0, [r4, #32]
    *out_num_sectors = num_sectors;
    574e:	6563      	str	r3, [r4, #84]	; 0x54
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    5750:	f000 fba8 	bl	5ea4 <flash_area_align>
    BOOT_WRITE_SZ(state) = boot_write_sz(state);
    5754:	65e0      	str	r0, [r4, #92]	; 0x5c
    return 0;
    5756:	e7f5      	b.n	5744 <boot_read_sectors+0x30>

00005758 <boot_status_reset>:
    bs->idx = BOOT_STATUS_IDX_0;
    5758:	2301      	movs	r3, #1
    575a:	6003      	str	r3, [r0, #0]
    bs->state = BOOT_STATUS_STATE_0;
    575c:	f103 2301 	add.w	r3, r3, #16777472	; 0x1000100
    5760:	6043      	str	r3, [r0, #4]
    bs->swap_size = 0;
    5762:	2300      	movs	r3, #0
    bs->source = 0;
    5764:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    5768:	4770      	bx	lr

0000576a <boot_status_is_reset>:
            bs->idx == BOOT_STATUS_IDX_0 &&
    576a:	7943      	ldrb	r3, [r0, #5]
    576c:	2b01      	cmp	r3, #1
    576e:	d107      	bne.n	5780 <boot_status_is_reset+0x16>
    return (bs->op == BOOT_STATUS_OP_MOVE &&
    5770:	6803      	ldr	r3, [r0, #0]
    5772:	2b01      	cmp	r3, #1
    5774:	d104      	bne.n	5780 <boot_status_is_reset+0x16>
            bs->idx == BOOT_STATUS_IDX_0 &&
    5776:	7900      	ldrb	r0, [r0, #4]
    5778:	1e43      	subs	r3, r0, #1
    577a:	4258      	negs	r0, r3
    577c:	4158      	adcs	r0, r3
    577e:	4770      	bx	lr
    5780:	2000      	movs	r0, #0
}
    5782:	4770      	bx	lr

00005784 <boot_write_status>:
{
    5784:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    5786:	4606      	mov	r6, r0
    5788:	460d      	mov	r5, r1
    rc = flash_area_open(area_id, &fap);
    578a:	2003      	movs	r0, #3
    578c:	a901      	add	r1, sp, #4
    578e:	f7fb fbb3 	bl	ef8 <flash_area_open>
    if (rc != 0) {
    5792:	bb38      	cbnz	r0, 57e4 <boot_write_status+0x60>
    off = boot_status_off(fap) +
    5794:	9801      	ldr	r0, [sp, #4]
    5796:	f7ff ff37 	bl	5608 <boot_status_off>
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    579a:	6df1      	ldr	r1, [r6, #92]	; 0x5c
    off = boot_status_off(fap) +
    579c:	4604      	mov	r4, r0
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    579e:	4628      	mov	r0, r5
    57a0:	f000 f933 	bl	5a0a <boot_status_internal_off>
    off = boot_status_off(fap) +
    57a4:	4404      	add	r4, r0
    align = flash_area_align(fap);
    57a6:	9801      	ldr	r0, [sp, #4]
    57a8:	f000 fb7c 	bl	5ea4 <flash_area_align>
    57ac:	4606      	mov	r6, r0
    erased_val = flash_area_erased_val(fap);
    57ae:	9801      	ldr	r0, [sp, #4]
    57b0:	f000 fb7f 	bl	5eb2 <flash_area_erased_val>
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    57b4:	2208      	movs	r2, #8
    erased_val = flash_area_erased_val(fap);
    57b6:	4601      	mov	r1, r0
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    57b8:	eb0d 0002 	add.w	r0, sp, r2
    57bc:	f000 fbe7 	bl	5f8e <memset>
    buf[0] = bs->state;
    57c0:	792b      	ldrb	r3, [r5, #4]
    57c2:	f88d 3008 	strb.w	r3, [sp, #8]
    rc = flash_area_write(fap, off, buf, align);
    57c6:	4621      	mov	r1, r4
    57c8:	9801      	ldr	r0, [sp, #4]
    57ca:	4633      	mov	r3, r6
    57cc:	aa02      	add	r2, sp, #8
    57ce:	f000 fb3e 	bl	5e4e <flash_area_write>
    if (rc != 0) {
    57d2:	1e04      	subs	r4, r0, #0
    flash_area_close(fap);
    57d4:	9801      	ldr	r0, [sp, #4]
    if (rc != 0) {
    57d6:	bf18      	it	ne
    57d8:	2401      	movne	r4, #1
    flash_area_close(fap);
    57da:	f000 fb22 	bl	5e22 <flash_area_close>
}
    57de:	4620      	mov	r0, r4
    57e0:	b004      	add	sp, #16
    57e2:	bd70      	pop	{r4, r5, r6, pc}
        return BOOT_EFLASH;
    57e4:	2401      	movs	r4, #1
    57e6:	e7fa      	b.n	57de <boot_write_status+0x5a>

000057e8 <boot_erase_region>:
    return flash_area_erase(fap, off, sz);
    57e8:	f000 bb46 	b.w	5e78 <flash_area_erase>

000057ec <swap_erase_trailer_sectors>:

#if defined(MCUBOOT_SWAP_USING_SCRATCH) || defined(MCUBOOT_SWAP_USING_MOVE)
int
swap_erase_trailer_sectors(const struct boot_loader_state *state,
                           const struct flash_area *fap)
{
    57ec:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    57f0:	460e      	mov	r6, r1
    int rc;

    BOOT_LOG_DBG("erasing trailer; fa_id=%d", flash_area_get_id(fap));

    image_index = BOOT_CURR_IMG(state);
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    57f2:	2100      	movs	r1, #0
{
    57f4:	4607      	mov	r7, r0
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    57f6:	4608      	mov	r0, r1
    57f8:	f7ff fe22 	bl	5440 <flash_area_id_from_multi_image_slot>
            BOOT_PRIMARY_SLOT);
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    57fc:	2101      	movs	r1, #1
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    57fe:	4604      	mov	r4, r0
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    5800:	2000      	movs	r0, #0
    5802:	f7ff fe1d 	bl	5440 <flash_area_id_from_multi_image_slot>
            BOOT_SECONDARY_SLOT);

    if (flash_area_get_id(fap) == fa_id_primary) {
    5806:	7833      	ldrb	r3, [r6, #0]
    5808:	42a3      	cmp	r3, r4
    580a:	d020      	beq.n	584e <swap_erase_trailer_sectors+0x62>
        slot = BOOT_PRIMARY_SLOT;
    } else if (flash_area_get_id(fap) == fa_id_secondary) {
    580c:	4283      	cmp	r3, r0
    580e:	d120      	bne.n	5852 <swap_erase_trailer_sectors+0x66>
        slot = BOOT_SECONDARY_SLOT;
    5810:	2501      	movs	r5, #1
    return BOOT_IMG(state, slot).num_sectors;
    5812:	232c      	movs	r3, #44	; 0x2c
    5814:	fb03 7505 	mla	r5, r3, r5, r7
        return BOOT_EFLASH;
    }

    /* delete starting from last sector and moving to beginning */
    sector = boot_img_num_sectors(state, slot) - 1;
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    5818:	6df8      	ldr	r0, [r7, #92]	; 0x5c
    sector = boot_img_num_sectors(state, slot) - 1;
    581a:	6aac      	ldr	r4, [r5, #40]	; 0x28
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    581c:	f7ff fee5 	bl	55ea <boot_trailer_sz>
    sector = boot_img_num_sectors(state, slot) - 1;
    5820:	3c01      	subs	r4, #1
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    5822:	4680      	mov	r8, r0
    total_sz = 0;
    5824:	2700      	movs	r7, #0
    return flash_sector_get_size(&BOOT_IMG(state, slot).sectors[sector]);
    5826:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    5828:	eb03 02c4 	add.w	r2, r3, r4, lsl #3
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    582c:	f853 1034 	ldr.w	r1, [r3, r4, lsl #3]
	return fs->fs_size;
    5830:	f8d2 9004 	ldr.w	r9, [r2, #4]
    5834:	681b      	ldr	r3, [r3, #0]
    do {
        sz = boot_img_sector_size(state, slot, sector);
        off = boot_img_sector_off(state, slot, sector);
        rc = boot_erase_region(fap, off, sz);
    5836:	464a      	mov	r2, r9
    5838:	1ac9      	subs	r1, r1, r3
    583a:	4630      	mov	r0, r6
        assert(rc == 0);

        sector--;
        total_sz += sz;
    583c:	444f      	add	r7, r9
        rc = boot_erase_region(fap, off, sz);
    583e:	f7ff ffd3 	bl	57e8 <boot_erase_region>
    } while (total_sz < trailer_sz);
    5842:	45b8      	cmp	r8, r7
        sector--;
    5844:	f104 34ff 	add.w	r4, r4, #4294967295
    } while (total_sz < trailer_sz);
    5848:	d8ed      	bhi.n	5826 <swap_erase_trailer_sectors+0x3a>

    return rc;
}
    584a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        slot = BOOT_PRIMARY_SLOT;
    584e:	2500      	movs	r5, #0
    5850:	e7df      	b.n	5812 <swap_erase_trailer_sectors+0x26>
        return BOOT_EFLASH;
    5852:	2001      	movs	r0, #1
    5854:	e7f9      	b.n	584a <swap_erase_trailer_sectors+0x5e>

00005856 <swap_status_init>:

int
swap_status_init(const struct boot_loader_state *state,
                 const struct flash_area *fap,
                 const struct boot_status *bs)
{
    5856:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5858:	4615      	mov	r5, r2
    585a:	460c      	mov	r4, r1

    image_index = BOOT_CURR_IMG(state);

    BOOT_LOG_DBG("initializing status; fa_id=%d", flash_area_get_id(fap));

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    585c:	2001      	movs	r0, #1
    585e:	4669      	mov	r1, sp
    5860:	f000 fe5e 	bl	6520 <boot_read_swap_state_by_id>
            &swap_state);
    assert(rc == 0);

    if (bs->swap_type != BOOT_SWAP_TYPE_NONE) {
    5864:	79e9      	ldrb	r1, [r5, #7]
    5866:	2901      	cmp	r1, #1
    5868:	d003      	beq.n	5872 <swap_status_init+0x1c>
        rc = boot_write_swap_info(fap, bs->swap_type, image_index);
    586a:	2200      	movs	r2, #0
    586c:	4620      	mov	r0, r4
    586e:	f000 fe6b 	bl	6548 <boot_write_swap_info>
        assert(rc == 0);
    }

    if (swap_state.image_ok == BOOT_FLAG_SET) {
    5872:	f89d 3003 	ldrb.w	r3, [sp, #3]
    5876:	2b01      	cmp	r3, #1
    5878:	d102      	bne.n	5880 <swap_status_init+0x2a>
        rc = boot_write_image_ok(fap);
    587a:	4620      	mov	r0, r4
    587c:	f000 fe43 	bl	6506 <boot_write_image_ok>
        assert(rc == 0);
    }

    rc = boot_write_swap_size(fap, bs->swap_size);
    5880:	68a9      	ldr	r1, [r5, #8]
    5882:	4620      	mov	r0, r4
    5884:	f7ff fed3 	bl	562e <boot_write_swap_size>

    rc = boot_write_enc_key(fap, 1, bs);
    assert(rc == 0);
#endif

    rc = boot_write_magic(fap);
    5888:	4620      	mov	r0, r4
    588a:	f7fc ff93 	bl	27b4 <boot_write_magic>
    assert(rc == 0);

    return 0;
}
    588e:	2000      	movs	r0, #0
    5890:	b003      	add	sp, #12
    5892:	bd30      	pop	{r4, r5, pc}

00005894 <swap_read_status>:

int
swap_read_status(struct boot_loader_state *state, struct boot_status *bs)
{
    5894:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5896:	460d      	mov	r5, r1
    5898:	4606      	mov	r6, r0
    uint32_t off;
    uint8_t swap_info;
    int area_id;
    int rc;

    bs->source = swap_status_source(state);
    589a:	f000 f8f2 	bl	5a82 <swap_status_source>
    589e:	4604      	mov	r4, r0
    58a0:	60e8      	str	r0, [r5, #12]
    switch (bs->source) {
    58a2:	b358      	cbz	r0, 58fc <swap_read_status+0x68>
    58a4:	2802      	cmp	r0, #2
    58a6:	d12e      	bne.n	5906 <swap_read_status+0x72>
    default:
        assert(0);
        return BOOT_EBADARGS;
    }

    rc = flash_area_open(area_id, &fap);
    58a8:	a901      	add	r1, sp, #4
    58aa:	2003      	movs	r0, #3
    58ac:	f7fb fb24 	bl	ef8 <flash_area_open>
    if (rc != 0) {
    58b0:	bb58      	cbnz	r0, 590a <swap_read_status+0x76>
        return BOOT_EFLASH;
    }

    rc = swap_read_status_bytes(fap, state, bs);
    58b2:	9801      	ldr	r0, [sp, #4]
    58b4:	462a      	mov	r2, r5
    58b6:	4631      	mov	r1, r6
    58b8:	f000 f859 	bl	596e <swap_read_status_bytes>
    if (rc == 0) {
    58bc:	4604      	mov	r4, r0
    58be:	b9d0      	cbnz	r0, 58f6 <swap_read_status+0x62>
        off = boot_swap_info_off(fap);
    58c0:	9801      	ldr	r0, [sp, #4]
    58c2:	f000 fda7 	bl	6414 <boot_swap_info_off>
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    58c6:	2301      	movs	r3, #1
        off = boot_swap_info_off(fap);
    58c8:	4601      	mov	r1, r0
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    58ca:	f10d 0203 	add.w	r2, sp, #3
    58ce:	9801      	ldr	r0, [sp, #4]
    58d0:	f000 faa8 	bl	5e24 <flash_area_read>
        if (rc != 0) {
    58d4:	4604      	mov	r4, r0
    58d6:	b9a0      	cbnz	r0, 5902 <swap_read_status+0x6e>
            rc = BOOT_EFLASH;
            goto done;
        }

        if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info)) {
    58d8:	9801      	ldr	r0, [sp, #4]
    58da:	2201      	movs	r2, #1
    58dc:	f10d 0103 	add.w	r1, sp, #3
    58e0:	f000 fdac 	bl	643c <bootutil_buffer_is_erased>
    58e4:	b110      	cbz	r0, 58ec <swap_read_status+0x58>
            BOOT_SET_SWAP_INFO(swap_info, 0, BOOT_SWAP_TYPE_NONE);
    58e6:	2301      	movs	r3, #1
    58e8:	f88d 3003 	strb.w	r3, [sp, #3]
            rc = 0;
        }

        /* Extract the swap type info */
        bs->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    58ec:	f89d 3003 	ldrb.w	r3, [sp, #3]
    58f0:	f003 030f 	and.w	r3, r3, #15
    58f4:	71eb      	strb	r3, [r5, #7]
    }

done:
    flash_area_close(fap);
    58f6:	9801      	ldr	r0, [sp, #4]
    58f8:	f000 fa93 	bl	5e22 <flash_area_close>

    return rc;
}
    58fc:	4620      	mov	r0, r4
    58fe:	b002      	add	sp, #8
    5900:	bd70      	pop	{r4, r5, r6, pc}
            rc = BOOT_EFLASH;
    5902:	2401      	movs	r4, #1
    5904:	e7f7      	b.n	58f6 <swap_read_status+0x62>
    switch (bs->source) {
    5906:	2407      	movs	r4, #7
    5908:	e7f8      	b.n	58fc <swap_read_status+0x68>
        return BOOT_EFLASH;
    590a:	2401      	movs	r4, #1
    590c:	e7f6      	b.n	58fc <swap_read_status+0x68>

0000590e <swap_set_copy_done>:

int
swap_set_copy_done(uint8_t image_index)
{
    590e:	b513      	push	{r0, r1, r4, lr}
    const struct flash_area *fap;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    5910:	2003      	movs	r0, #3
    5912:	a901      	add	r1, sp, #4
    5914:	f7fb faf0 	bl	ef8 <flash_area_open>
            &fap);
    if (rc != 0) {
    5918:	b948      	cbnz	r0, 592e <swap_set_copy_done+0x20>
        return BOOT_EFLASH;
    }

    rc = boot_write_copy_done(fap);
    591a:	9801      	ldr	r0, [sp, #4]
    591c:	f7ff fe7f 	bl	561e <boot_write_copy_done>
    5920:	4604      	mov	r4, r0
    flash_area_close(fap);
    5922:	9801      	ldr	r0, [sp, #4]
    5924:	f000 fa7d 	bl	5e22 <flash_area_close>
    return rc;
}
    5928:	4620      	mov	r0, r4
    592a:	b002      	add	sp, #8
    592c:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    592e:	2401      	movs	r4, #1
    5930:	e7fa      	b.n	5928 <swap_set_copy_done+0x1a>

00005932 <swap_set_image_ok>:

int
swap_set_image_ok(uint8_t image_index)
{
    5932:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    const struct flash_area *fap;
    struct boot_swap_state state;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    5934:	2003      	movs	r0, #3
    5936:	a901      	add	r1, sp, #4
    5938:	f7fb fade 	bl	ef8 <flash_area_open>
            &fap);
    if (rc != 0) {
    593c:	b9a8      	cbnz	r0, 596a <swap_set_image_ok+0x38>
        return BOOT_EFLASH;
    }

    rc = boot_read_swap_state(fap, &state);
    593e:	9801      	ldr	r0, [sp, #4]
    5940:	a902      	add	r1, sp, #8
    5942:	f7fc ff57 	bl	27f4 <boot_read_swap_state>
    if (rc != 0) {
    5946:	4604      	mov	r4, r0
    5948:	b968      	cbnz	r0, 5966 <swap_set_image_ok+0x34>
        rc = BOOT_EFLASH;
        goto out;
    }

    if (state.image_ok == BOOT_FLAG_UNSET) {
    594a:	f89d 300b 	ldrb.w	r3, [sp, #11]
    594e:	2b03      	cmp	r3, #3
    5950:	d103      	bne.n	595a <swap_set_image_ok+0x28>
        rc = boot_write_image_ok(fap);
    5952:	9801      	ldr	r0, [sp, #4]
    5954:	f000 fdd7 	bl	6506 <boot_write_image_ok>
    5958:	4604      	mov	r4, r0
    }

out:
    flash_area_close(fap);
    595a:	9801      	ldr	r0, [sp, #4]
    595c:	f000 fa61 	bl	5e22 <flash_area_close>
    return rc;
}
    5960:	4620      	mov	r0, r4
    5962:	b004      	add	sp, #16
    5964:	bd10      	pop	{r4, pc}
        rc = BOOT_EFLASH;
    5966:	2401      	movs	r4, #1
    5968:	e7f7      	b.n	595a <swap_set_image_ok+0x28>
        return BOOT_EFLASH;
    596a:	2401      	movs	r4, #1
    596c:	e7f8      	b.n	5960 <swap_set_image_ok+0x2e>

0000596e <swap_read_status_bytes>:
{
    596e:	e92d 47f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, r9, sl, lr}
    5972:	4607      	mov	r7, r0
    5974:	460c      	mov	r4, r1
    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
    5976:	4601      	mov	r1, r0
    5978:	2000      	movs	r0, #0
{
    597a:	4616      	mov	r6, r2
    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
    597c:	f7ff fe3a 	bl	55f4 <boot_status_entries>
    if (max_entries < 0) {
    5980:	1e05      	subs	r5, r0, #0
    5982:	db3e      	blt.n	5a02 <swap_read_status_bytes+0x94>
    off = boot_status_off(fap);
    5984:	4638      	mov	r0, r7
    write_sz = BOOT_WRITE_SZ(state);
    5986:	6de4      	ldr	r4, [r4, #92]	; 0x5c
    off = boot_status_off(fap);
    5988:	f7ff fe3e 	bl	5608 <boot_status_off>
    for (i = max_entries; i > 0; i--) {
    598c:	fa5f f984 	uxtb.w	r9, r4
    5990:	1e6b      	subs	r3, r5, #1
    5992:	fb09 0803 	mla	r8, r9, r3, r0
    found_idx = -1;
    5996:	f04f 34ff 	mov.w	r4, #4294967295
    for (i = max_entries; i > 0; i--) {
    599a:	b965      	cbnz	r5, 59b6 <swap_read_status_bytes+0x48>
    if (found_idx == -1) {
    599c:	1c63      	adds	r3, r4, #1
    599e:	d006      	beq.n	59ae <swap_read_status_bytes+0x40>
    } else if (found_idx < move_entries) {
    59a0:	2cff      	cmp	r4, #255	; 0xff
    59a2:	dc22      	bgt.n	59ea <swap_read_status_bytes+0x7c>
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
    59a4:	3401      	adds	r4, #1
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
    59a6:	f240 1301 	movw	r3, #257	; 0x101
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
    59aa:	6034      	str	r4, [r6, #0]
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
    59ac:	80b3      	strh	r3, [r6, #4]
}
    59ae:	4628      	mov	r0, r5
    59b0:	b002      	add	sp, #8
    59b2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
        rc = flash_area_read(fap, off + (i - 1) * write_sz, &status, 1);
    59b6:	2301      	movs	r3, #1
    59b8:	f10d 0207 	add.w	r2, sp, #7
    59bc:	4641      	mov	r1, r8
    59be:	4638      	mov	r0, r7
    59c0:	f000 fa30 	bl	5e24 <flash_area_read>
        if (rc < 0) {
    59c4:	2800      	cmp	r0, #0
        rc = flash_area_read(fap, off + (i - 1) * write_sz, &status, 1);
    59c6:	f105 3aff 	add.w	sl, r5, #4294967295
        if (rc < 0) {
    59ca:	db1c      	blt.n	5a06 <swap_read_status_bytes+0x98>
        if (bootutil_buffer_is_erased(fap, &status, 1)) {
    59cc:	2201      	movs	r2, #1
    59ce:	f10d 0107 	add.w	r1, sp, #7
    59d2:	4638      	mov	r0, r7
    59d4:	f000 fd32 	bl	643c <bootutil_buffer_is_erased>
    59d8:	b918      	cbnz	r0, 59e2 <swap_read_status_bytes+0x74>
            if (found_idx == -1) {
    59da:	f1b4 3fff 	cmp.w	r4, #4294967295
    59de:	bf08      	it	eq
    59e0:	462c      	moveq	r4, r5
    59e2:	eba8 0809 	sub.w	r8, r8, r9
    59e6:	4655      	mov	r5, sl
    59e8:	e7d7      	b.n	599a <swap_read_status_bytes+0x2c>
        bs->op = BOOT_STATUS_OP_SWAP;
    59ea:	2302      	movs	r3, #2
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
    59ec:	f5a4 7480 	sub.w	r4, r4, #256	; 0x100
        bs->op = BOOT_STATUS_OP_SWAP;
    59f0:	7173      	strb	r3, [r6, #5]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
    59f2:	1063      	asrs	r3, r4, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    59f4:	f004 0401 	and.w	r4, r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
    59f8:	3301      	adds	r3, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    59fa:	3401      	adds	r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
    59fc:	6033      	str	r3, [r6, #0]
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    59fe:	7134      	strb	r4, [r6, #4]
    5a00:	e7d5      	b.n	59ae <swap_read_status_bytes+0x40>
        return BOOT_EBADARGS;
    5a02:	2507      	movs	r5, #7
    5a04:	e7d3      	b.n	59ae <swap_read_status_bytes+0x40>
            return BOOT_EFLASH;
    5a06:	2501      	movs	r5, #1
    5a08:	e7d1      	b.n	59ae <swap_read_status_bytes+0x40>

00005a0a <boot_status_internal_off>:
{
    5a0a:	b510      	push	{r4, lr}
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    5a0c:	7943      	ldrb	r3, [r0, #5]
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    5a0e:	7902      	ldrb	r2, [r0, #4]
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    5a10:	2b01      	cmp	r3, #1
               0 : (BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT * elem_sz)) +
    5a12:	bf14      	ite	ne
    5a14:	020b      	lslne	r3, r1, #8
    5a16:	2300      	moveq	r3, #0
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    5a18:	f102 32ff 	add.w	r2, r2, #4294967295
    off = ((bs->op == BOOT_STATUS_OP_MOVE) ?
    5a1c:	fb01 3302 	mla	r3, r1, r2, r3
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    5a20:	6802      	ldr	r2, [r0, #0]
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    5a22:	bf14      	ite	ne
    5a24:	004c      	lslne	r4, r1, #1
    5a26:	460c      	moveq	r4, r1
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    5a28:	3a01      	subs	r2, #1
}
    5a2a:	fb04 3002 	mla	r0, r4, r2, r3
    5a2e:	bd10      	pop	{r4, pc}

00005a30 <boot_slots_compatible>:
{
    5a30:	b530      	push	{r4, r5, lr}
    return BOOT_IMG(state, slot).num_sectors;
    5a32:	6a82      	ldr	r2, [r0, #40]	; 0x28
    5a34:	6d44      	ldr	r4, [r0, #84]	; 0x54
    if ((num_sectors_pri != num_sectors_sec) &&
    5a36:	4294      	cmp	r4, r2
    5a38:	d002      	beq.n	5a40 <boot_slots_compatible+0x10>
            (num_sectors_pri != (num_sectors_sec + 1))) {
    5a3a:	1c63      	adds	r3, r4, #1
    if ((num_sectors_pri != num_sectors_sec) &&
    5a3c:	4293      	cmp	r3, r2
    5a3e:	d11c      	bne.n	5a7a <boot_slots_compatible+0x4a>
    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
    5a40:	f5b2 7f80 	cmp.w	r2, #256	; 0x100
    5a44:	d819      	bhi.n	5a7a <boot_slots_compatible+0x4a>
    for (i = 0; i < num_sectors_sec; i++) {
    5a46:	2300      	movs	r3, #0
    size_t sector_sz_pri = 0;
    5a48:	4619      	mov	r1, r3
    for (i = 0; i < num_sectors_sec; i++) {
    5a4a:	42a3      	cmp	r3, r4
    5a4c:	d109      	bne.n	5a62 <boot_slots_compatible+0x32>
    if (num_sectors_pri > num_sectors_sec) {
    5a4e:	4293      	cmp	r3, r2
    5a50:	d215      	bcs.n	5a7e <boot_slots_compatible+0x4e>
    5a52:	6a42      	ldr	r2, [r0, #36]	; 0x24
    5a54:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
        if (sector_sz_pri != boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i)) {
    5a58:	6858      	ldr	r0, [r3, #4]
    5a5a:	1a43      	subs	r3, r0, r1
    5a5c:	4258      	negs	r0, r3
    5a5e:	4158      	adcs	r0, r3
}
    5a60:	bd30      	pop	{r4, r5, pc}
    5a62:	6a41      	ldr	r1, [r0, #36]	; 0x24
    5a64:	6d05      	ldr	r5, [r0, #80]	; 0x50
    5a66:	eb01 01c3 	add.w	r1, r1, r3, lsl #3
    5a6a:	eb05 05c3 	add.w	r5, r5, r3, lsl #3
    5a6e:	6849      	ldr	r1, [r1, #4]
        if (sector_sz_pri != sector_sz_sec) {
    5a70:	686d      	ldr	r5, [r5, #4]
    5a72:	428d      	cmp	r5, r1
    5a74:	d101      	bne.n	5a7a <boot_slots_compatible+0x4a>
    for (i = 0; i < num_sectors_sec; i++) {
    5a76:	3301      	adds	r3, #1
    5a78:	e7e7      	b.n	5a4a <boot_slots_compatible+0x1a>
        return 0;
    5a7a:	2000      	movs	r0, #0
    5a7c:	e7f0      	b.n	5a60 <boot_slots_compatible+0x30>
    return 1;
    5a7e:	2001      	movs	r0, #1
    5a80:	e7ee      	b.n	5a60 <boot_slots_compatible+0x30>

00005a82 <swap_status_source>:
{
    5a82:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    5a84:	2003      	movs	r0, #3
    5a86:	4669      	mov	r1, sp
    5a88:	f000 fd4a 	bl	6520 <boot_read_swap_state_by_id>
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    5a8c:	a902      	add	r1, sp, #8
    5a8e:	2001      	movs	r0, #1
    5a90:	f000 fd46 	bl	6520 <boot_read_swap_state_by_id>
    if (state_primary_slot.magic == BOOT_MAGIC_GOOD &&
    5a94:	f89d 3000 	ldrb.w	r3, [sp]
    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
    5a98:	f89d 0008 	ldrb.w	r0, [sp, #8]
    if (state_primary_slot.magic == BOOT_MAGIC_GOOD &&
    5a9c:	2b01      	cmp	r3, #1
    5a9e:	d10a      	bne.n	5ab6 <swap_status_source+0x34>
    5aa0:	f89d 3002 	ldrb.w	r3, [sp, #2]
    5aa4:	2b03      	cmp	r3, #3
    5aa6:	d106      	bne.n	5ab6 <swap_status_source+0x34>
            state_primary_slot.copy_done == BOOT_FLAG_UNSET &&
    5aa8:	3801      	subs	r0, #1
    5aaa:	bf18      	it	ne
    5aac:	2001      	movne	r0, #1
    5aae:	0040      	lsls	r0, r0, #1
}
    5ab0:	b005      	add	sp, #20
    5ab2:	f85d fb04 	ldr.w	pc, [sp], #4
    return BOOT_STATUS_SOURCE_NONE;
    5ab6:	2000      	movs	r0, #0
    5ab8:	e7fa      	b.n	5ab0 <swap_status_source+0x2e>

00005aba <mbedtls_asn1_get_len>:
 * ASN.1 DER decoding routines
 */
int mbedtls_asn1_get_len( unsigned char **p,
                  const unsigned char *end,
                  size_t *len )
{
    5aba:	b570      	push	{r4, r5, r6, lr}
    if( ( end - *p ) < 1 )
    5abc:	6803      	ldr	r3, [r0, #0]
    5abe:	1acd      	subs	r5, r1, r3
    5ac0:	2d00      	cmp	r5, #0
    5ac2:	dc02      	bgt.n	5aca <mbedtls_asn1_get_len+0x10>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    5ac4:	f06f 005f 	mvn.w	r0, #95	; 0x5f

    if( *len > (size_t) ( end - *p ) )
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    return( 0 );
}
    5ac8:	bd70      	pop	{r4, r5, r6, pc}
    if( ( **p & 0x80 ) == 0 )
    5aca:	f993 6000 	ldrsb.w	r6, [r3]
    5ace:	781c      	ldrb	r4, [r3, #0]
    5ad0:	2e00      	cmp	r6, #0
    5ad2:	db0a      	blt.n	5aea <mbedtls_asn1_get_len+0x30>
        *len = *(*p)++;
    5ad4:	1c5c      	adds	r4, r3, #1
    5ad6:	6004      	str	r4, [r0, #0]
    5ad8:	781b      	ldrb	r3, [r3, #0]
    5ada:	6013      	str	r3, [r2, #0]
    if( *len > (size_t) ( end - *p ) )
    5adc:	6803      	ldr	r3, [r0, #0]
    5ade:	1ac9      	subs	r1, r1, r3
    5ae0:	6813      	ldr	r3, [r2, #0]
    5ae2:	428b      	cmp	r3, r1
    5ae4:	d8ee      	bhi.n	5ac4 <mbedtls_asn1_get_len+0xa>
    return( 0 );
    5ae6:	2000      	movs	r0, #0
    5ae8:	e7ee      	b.n	5ac8 <mbedtls_asn1_get_len+0xe>
        switch( **p & 0x7F )
    5aea:	f004 047f 	and.w	r4, r4, #127	; 0x7f
    5aee:	3c01      	subs	r4, #1
    5af0:	2c03      	cmp	r4, #3
    5af2:	d82b      	bhi.n	5b4c <mbedtls_asn1_get_len+0x92>
    5af4:	e8df f004 	tbb	[pc, r4]
    5af8:	21140a02 	.word	0x21140a02
            if( ( end - *p ) < 2 )
    5afc:	2d01      	cmp	r5, #1
    5afe:	d0e1      	beq.n	5ac4 <mbedtls_asn1_get_len+0xa>
            *len = (*p)[1];
    5b00:	785b      	ldrb	r3, [r3, #1]
    5b02:	6013      	str	r3, [r2, #0]
            (*p) += 2;
    5b04:	6803      	ldr	r3, [r0, #0]
    5b06:	3302      	adds	r3, #2
            (*p) += 5;
    5b08:	6003      	str	r3, [r0, #0]
            break;
    5b0a:	e7e7      	b.n	5adc <mbedtls_asn1_get_len+0x22>
            if( ( end - *p ) < 3 )
    5b0c:	2d02      	cmp	r5, #2
    5b0e:	ddd9      	ble.n	5ac4 <mbedtls_asn1_get_len+0xa>
            *len = ( (size_t)(*p)[1] << 8 ) | (*p)[2];
    5b10:	f8b3 3001 	ldrh.w	r3, [r3, #1]
    5b14:	ba5b      	rev16	r3, r3
    5b16:	b29b      	uxth	r3, r3
    5b18:	6013      	str	r3, [r2, #0]
            (*p) += 3;
    5b1a:	6803      	ldr	r3, [r0, #0]
    5b1c:	3303      	adds	r3, #3
    5b1e:	e7f3      	b.n	5b08 <mbedtls_asn1_get_len+0x4e>
            if( ( end - *p ) < 4 )
    5b20:	2d03      	cmp	r5, #3
    5b22:	ddcf      	ble.n	5ac4 <mbedtls_asn1_get_len+0xa>
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    5b24:	789c      	ldrb	r4, [r3, #2]
            *len = ( (size_t)(*p)[1] << 16 ) |
    5b26:	785d      	ldrb	r5, [r3, #1]
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    5b28:	78db      	ldrb	r3, [r3, #3]
    5b2a:	0224      	lsls	r4, r4, #8
            *len = ( (size_t)(*p)[1] << 16 ) |
    5b2c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    5b30:	4323      	orrs	r3, r4
            *len = ( (size_t)(*p)[1] << 16 ) |
    5b32:	6013      	str	r3, [r2, #0]
            (*p) += 4;
    5b34:	6803      	ldr	r3, [r0, #0]
    5b36:	3304      	adds	r3, #4
    5b38:	e7e6      	b.n	5b08 <mbedtls_asn1_get_len+0x4e>
            if( ( end - *p ) < 5 )
    5b3a:	2d04      	cmp	r5, #4
    5b3c:	ddc2      	ble.n	5ac4 <mbedtls_asn1_get_len+0xa>
            *len = ( (size_t)(*p)[1] << 24 ) | ( (size_t)(*p)[2] << 16 ) |
    5b3e:	f8d3 3001 	ldr.w	r3, [r3, #1]
    5b42:	ba1b      	rev	r3, r3
    5b44:	6013      	str	r3, [r2, #0]
            (*p) += 5;
    5b46:	6803      	ldr	r3, [r0, #0]
    5b48:	3305      	adds	r3, #5
    5b4a:	e7dd      	b.n	5b08 <mbedtls_asn1_get_len+0x4e>
        switch( **p & 0x7F )
    5b4c:	f06f 0063 	mvn.w	r0, #99	; 0x63
    5b50:	e7ba      	b.n	5ac8 <mbedtls_asn1_get_len+0xe>

00005b52 <mbedtls_asn1_get_tag>:

int mbedtls_asn1_get_tag( unsigned char **p,
                  const unsigned char *end,
                  size_t *len, int tag )
{
    5b52:	b470      	push	{r4, r5, r6}
    if( ( end - *p ) < 1 )
    5b54:	6804      	ldr	r4, [r0, #0]
    5b56:	1b0e      	subs	r6, r1, r4
    5b58:	2e00      	cmp	r6, #0
    5b5a:	dd07      	ble.n	5b6c <mbedtls_asn1_get_tag+0x1a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( **p != tag )
    5b5c:	7826      	ldrb	r6, [r4, #0]
    5b5e:	429e      	cmp	r6, r3
    5b60:	d108      	bne.n	5b74 <mbedtls_asn1_get_tag+0x22>
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );

    (*p)++;
    5b62:	3401      	adds	r4, #1
    5b64:	6004      	str	r4, [r0, #0]

    return( mbedtls_asn1_get_len( p, end, len ) );
}
    5b66:	bc70      	pop	{r4, r5, r6}
    return( mbedtls_asn1_get_len( p, end, len ) );
    5b68:	f7ff bfa7 	b.w	5aba <mbedtls_asn1_get_len>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    5b6c:	f06f 005f 	mvn.w	r0, #95	; 0x5f
}
    5b70:	bc70      	pop	{r4, r5, r6}
    5b72:	4770      	bx	lr
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );
    5b74:	f06f 0061 	mvn.w	r0, #97	; 0x61
    5b78:	e7fa      	b.n	5b70 <mbedtls_asn1_get_tag+0x1e>

00005b7a <mbedtls_asn1_get_bitstring_null>:
/*
 * Get a bit string without unused bits
 */
int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end,
                             size_t *len )
{
    5b7a:	b538      	push	{r3, r4, r5, lr}
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;

    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    5b7c:	2303      	movs	r3, #3
{
    5b7e:	4604      	mov	r4, r0
    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    5b80:	f7ff ffe7 	bl	5b52 <mbedtls_asn1_get_tag>
    5b84:	b918      	cbnz	r0, 5b8e <mbedtls_asn1_get_bitstring_null+0x14>
        return( ret );

    if( *len == 0 )
    5b86:	6813      	ldr	r3, [r2, #0]
    5b88:	b913      	cbnz	r3, 5b90 <mbedtls_asn1_get_bitstring_null+0x16>
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    5b8a:	f06f 0067 	mvn.w	r0, #103	; 0x67
    if( **p != 0 )
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    ++( *p );

    return( 0 );
}
    5b8e:	bd38      	pop	{r3, r4, r5, pc}
    --( *len );
    5b90:	3b01      	subs	r3, #1
    5b92:	6013      	str	r3, [r2, #0]
    if( **p != 0 )
    5b94:	6823      	ldr	r3, [r4, #0]
    5b96:	781a      	ldrb	r2, [r3, #0]
    5b98:	2a00      	cmp	r2, #0
    5b9a:	d1f6      	bne.n	5b8a <mbedtls_asn1_get_bitstring_null+0x10>
    ++( *p );
    5b9c:	3301      	adds	r3, #1
    5b9e:	6023      	str	r3, [r4, #0]
    return( 0 );
    5ba0:	e7f5      	b.n	5b8e <mbedtls_asn1_get_bitstring_null+0x14>

00005ba2 <mbedtls_asn1_get_alg>:
}

int mbedtls_asn1_get_alg( unsigned char **p,
                  const unsigned char *end,
                  mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params )
{
    5ba2:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    5ba6:	4690      	mov	r8, r2
    5ba8:	461f      	mov	r7, r3
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
    size_t len;

    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    5baa:	aa01      	add	r2, sp, #4
    5bac:	2330      	movs	r3, #48	; 0x30
{
    5bae:	4605      	mov	r5, r0
    5bb0:	460e      	mov	r6, r1
    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    5bb2:	f7ff ffce 	bl	5b52 <mbedtls_asn1_get_tag>
    5bb6:	4604      	mov	r4, r0
    5bb8:	b9f0      	cbnz	r0, 5bf8 <mbedtls_asn1_get_alg+0x56>
            MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 )
        return( ret );

    if( ( end - *p ) < 1 )
    5bba:	682b      	ldr	r3, [r5, #0]
    5bbc:	1af6      	subs	r6, r6, r3
    5bbe:	2e00      	cmp	r6, #0
    5bc0:	dd34      	ble.n	5c2c <mbedtls_asn1_get_alg+0x8a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    alg->tag = **p;
    5bc2:	4642      	mov	r2, r8
    5bc4:	781b      	ldrb	r3, [r3, #0]
    5bc6:	f842 3b04 	str.w	r3, [r2], #4
    end = *p + len;
    5bca:	9b01      	ldr	r3, [sp, #4]
    5bcc:	682e      	ldr	r6, [r5, #0]
    5bce:	441e      	add	r6, r3

    if( ( ret = mbedtls_asn1_get_tag( p, end, &alg->len, MBEDTLS_ASN1_OID ) ) != 0 )
    5bd0:	4631      	mov	r1, r6
    5bd2:	2306      	movs	r3, #6
    5bd4:	4628      	mov	r0, r5
    5bd6:	f7ff ffbc 	bl	5b52 <mbedtls_asn1_get_tag>
    5bda:	4604      	mov	r4, r0
    5bdc:	b960      	cbnz	r0, 5bf8 <mbedtls_asn1_get_alg+0x56>
        return( ret );

    alg->p = *p;
    5bde:	682b      	ldr	r3, [r5, #0]
    *p += alg->len;
    5be0:	f8d8 2004 	ldr.w	r2, [r8, #4]
    alg->p = *p;
    5be4:	f8c8 3008 	str.w	r3, [r8, #8]
    *p += alg->len;
    5be8:	1899      	adds	r1, r3, r2

    if( *p == end )
    5bea:	42b1      	cmp	r1, r6
    *p += alg->len;
    5bec:	6029      	str	r1, [r5, #0]
    if( *p == end )
    5bee:	d107      	bne.n	5c00 <mbedtls_asn1_get_alg+0x5e>
    {
        mbedtls_platform_zeroize( params, sizeof(mbedtls_asn1_buf) );
    5bf0:	210c      	movs	r1, #12
    5bf2:	4638      	mov	r0, r7
    5bf4:	f7fe f8ae 	bl	3d54 <mbedtls_platform_zeroize>

    if( *p != end )
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );

    return( 0 );
}
    5bf8:	4620      	mov	r0, r4
    5bfa:	b002      	add	sp, #8
    5bfc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    params->tag = **p;
    5c00:	5c9b      	ldrb	r3, [r3, r2]
    5c02:	463a      	mov	r2, r7
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    5c04:	4631      	mov	r1, r6
    params->tag = **p;
    5c06:	f842 3b04 	str.w	r3, [r2], #4
    (*p)++;
    5c0a:	682b      	ldr	r3, [r5, #0]
    5c0c:	3301      	adds	r3, #1
    5c0e:	602b      	str	r3, [r5, #0]
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    5c10:	4628      	mov	r0, r5
    5c12:	f7ff ff52 	bl	5aba <mbedtls_asn1_get_len>
    5c16:	b960      	cbnz	r0, 5c32 <mbedtls_asn1_get_alg+0x90>
    params->p = *p;
    5c18:	682b      	ldr	r3, [r5, #0]
    *p += params->len;
    5c1a:	687a      	ldr	r2, [r7, #4]
    params->p = *p;
    5c1c:	60bb      	str	r3, [r7, #8]
    *p += params->len;
    5c1e:	4413      	add	r3, r2
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    5c20:	42b3      	cmp	r3, r6
    *p += params->len;
    5c22:	602b      	str	r3, [r5, #0]
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    5c24:	bf18      	it	ne
    5c26:	f06f 0465 	mvnne.w	r4, #101	; 0x65
    5c2a:	e7e5      	b.n	5bf8 <mbedtls_asn1_get_alg+0x56>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    5c2c:	f06f 045f 	mvn.w	r4, #95	; 0x5f
    5c30:	e7e2      	b.n	5bf8 <mbedtls_asn1_get_alg+0x56>
    5c32:	4604      	mov	r4, r0
    5c34:	e7e0      	b.n	5bf8 <mbedtls_asn1_get_alg+0x56>

00005c36 <cc310_sha256_update>:
{
    5c36:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    5c38:	f1b1 5f00 	cmp.w	r1, #536870912	; 0x20000000
{
    5c3c:	af00      	add	r7, sp, #0
    5c3e:	4605      	mov	r5, r0
    5c40:	4614      	mov	r4, r2
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    5c42:	d210      	bcs.n	5c66 <cc310_sha256_update+0x30>
        uint8_t stack_buffer[data_len];
    5c44:	1dd3      	adds	r3, r2, #7
    5c46:	f023 0307 	bic.w	r3, r3, #7
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    5c4a:	466e      	mov	r6, sp
        uint8_t stack_buffer[data_len];
    5c4c:	ebad 0d03 	sub.w	sp, sp, r3
        memcpy(stack_buffer, data, block_len);
    5c50:	4668      	mov	r0, sp
    5c52:	f000 f991 	bl	5f78 <memcpy>
        nrf_cc310_bl_hash_sha256_update(ctx, stack_buffer, block_len);
    5c56:	4669      	mov	r1, sp
    5c58:	4622      	mov	r2, r4
    5c5a:	4628      	mov	r0, r5
    5c5c:	f7fe fb44 	bl	42e8 <nrf_cc310_bl_hash_sha256_update>
    5c60:	46b5      	mov	sp, r6
};
    5c62:	46bd      	mov	sp, r7
    5c64:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        nrf_cc310_bl_hash_sha256_update(ctx, data, data_len);
    5c66:	f7fe fb3f 	bl	42e8 <nrf_cc310_bl_hash_sha256_update>
};
    5c6a:	e7fa      	b.n	5c62 <cc310_sha256_update+0x2c>

00005c6c <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5c6c:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    5c6e:	f013 0307 	ands.w	r3, r3, #7
    5c72:	d105      	bne.n	5c80 <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    5c74:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    5c76:	2b00      	cmp	r3, #0
    5c78:	bf0c      	ite	eq
    5c7a:	2000      	moveq	r0, #0
    5c7c:	2003      	movne	r0, #3
    5c7e:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    5c80:	2b02      	cmp	r3, #2
    5c82:	d105      	bne.n	5c90 <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    5c84:	8b40      	ldrh	r0, [r0, #26]
    5c86:	fab0 f080 	clz	r0, r0
    5c8a:	0940      	lsrs	r0, r0, #5
    5c8c:	0080      	lsls	r0, r0, #2
    5c8e:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    5c90:	2b01      	cmp	r3, #1
    5c92:	d105      	bne.n	5ca0 <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    5c94:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    5c96:	2b00      	cmp	r3, #0
    5c98:	bf0c      	ite	eq
    5c9a:	2000      	moveq	r0, #0
    5c9c:	2005      	movne	r0, #5
    5c9e:	4770      	bx	lr
	int evt = EVT_NOP;
    5ca0:	2000      	movs	r0, #0
}
    5ca2:	4770      	bx	lr

00005ca4 <validate_args>:
{
    5ca4:	b510      	push	{r4, lr}
    5ca6:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    5ca8:	b100      	cbz	r0, 5cac <validate_args+0x8>
    5caa:	b911      	cbnz	r1, 5cb2 <validate_args+0xe>
		return -EINVAL;
    5cac:	f06f 0015 	mvn.w	r0, #21
}
    5cb0:	bd10      	pop	{r4, pc}
	int rv = sys_notify_validate(&cli->notify);
    5cb2:	1d08      	adds	r0, r1, #4
    5cb4:	f000 f896 	bl	5de4 <sys_notify_validate>
	if ((rv == 0)
    5cb8:	2800      	cmp	r0, #0
    5cba:	d1f9      	bne.n	5cb0 <validate_args+0xc>
	    && ((cli->notify.flags
    5cbc:	68a3      	ldr	r3, [r4, #8]
    5cbe:	2b03      	cmp	r3, #3
    5cc0:	d9f6      	bls.n	5cb0 <validate_args+0xc>
    5cc2:	e7f3      	b.n	5cac <validate_args+0x8>

00005cc4 <notify_one>:
{
    5cc4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5cc8:	460d      	mov	r5, r1
    5cca:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5ccc:	4619      	mov	r1, r3
    5cce:	1d28      	adds	r0, r5, #4
{
    5cd0:	4690      	mov	r8, r2
    5cd2:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5cd4:	f000 f897 	bl	5e06 <sys_notify_finalize>
	if (cb) {
    5cd8:	4604      	mov	r4, r0
    5cda:	b138      	cbz	r0, 5cec <notify_one+0x28>
		cb(mgr, cli, state, res);
    5cdc:	4633      	mov	r3, r6
    5cde:	4642      	mov	r2, r8
    5ce0:	4629      	mov	r1, r5
    5ce2:	4638      	mov	r0, r7
    5ce4:	46a4      	mov	ip, r4
}
    5ce6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    5cea:	4760      	bx	ip
}
    5cec:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005cf0 <transition_complete>:
{
    5cf0:	b410      	push	{r4}
    5cf2:	f04f 0420 	mov.w	r4, #32
    5cf6:	f3ef 8211 	mrs	r2, BASEPRI
    5cfa:	f384 8812 	msr	BASEPRI_MAX, r4
    5cfe:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    5d02:	6141      	str	r1, [r0, #20]
}
    5d04:	f85d 4b04 	ldr.w	r4, [sp], #4
	process_event(mgr, EVT_COMPLETE, key);
    5d08:	2101      	movs	r1, #1
    5d0a:	f7fa bfe5 	b.w	cd8 <process_event>

00005d0e <onoff_manager_init>:
{
    5d0e:	b538      	push	{r3, r4, r5, lr}
    5d10:	460c      	mov	r4, r1
	if ((mgr == NULL)
    5d12:	4605      	mov	r5, r0
    5d14:	b158      	cbz	r0, 5d2e <onoff_manager_init+0x20>
	    || (transitions == NULL)
    5d16:	b151      	cbz	r1, 5d2e <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    5d18:	680b      	ldr	r3, [r1, #0]
    5d1a:	b143      	cbz	r3, 5d2e <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    5d1c:	684b      	ldr	r3, [r1, #4]
    5d1e:	b133      	cbz	r3, 5d2e <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5d20:	221c      	movs	r2, #28
    5d22:	2100      	movs	r1, #0
    5d24:	f000 f933 	bl	5f8e <memset>
    5d28:	612c      	str	r4, [r5, #16]
	return 0;
    5d2a:	2000      	movs	r0, #0
}
    5d2c:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    5d2e:	f06f 0015 	mvn.w	r0, #21
    5d32:	e7fb      	b.n	5d2c <onoff_manager_init+0x1e>

00005d34 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5d34:	b570      	push	{r4, r5, r6, lr}
    5d36:	4605      	mov	r5, r0
    5d38:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5d3a:	f7ff ffb3 	bl	5ca4 <validate_args>

	if (rv < 0) {
    5d3e:	1e04      	subs	r4, r0, #0
    5d40:	db15      	blt.n	5d6e <onoff_request+0x3a>
    5d42:	f04f 0320 	mov.w	r3, #32
    5d46:	f3ef 8211 	mrs	r2, BASEPRI
    5d4a:	f383 8812 	msr	BASEPRI_MAX, r3
    5d4e:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    5d52:	8b6b      	ldrh	r3, [r5, #26]
    5d54:	8b2c      	ldrh	r4, [r5, #24]
    5d56:	f64f 71ff 	movw	r1, #65535	; 0xffff
    5d5a:	428b      	cmp	r3, r1
    5d5c:	f004 0407 	and.w	r4, r4, #7
    5d60:	d107      	bne.n	5d72 <onoff_request+0x3e>
	__asm__ volatile(
    5d62:	f382 8811 	msr	BASEPRI, r2
    5d66:	f3bf 8f6f 	isb	sy
		rv = -EAGAIN;
    5d6a:	f06f 040a 	mvn.w	r4, #10
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    5d6e:	4620      	mov	r0, r4
    5d70:	bd70      	pop	{r4, r5, r6, pc}
	if (state == ONOFF_STATE_ON) {
    5d72:	2c02      	cmp	r4, #2
    5d74:	d10c      	bne.n	5d90 <onoff_request+0x5c>
		mgr->refs += 1U;
    5d76:	3301      	adds	r3, #1
    5d78:	836b      	strh	r3, [r5, #26]
    5d7a:	f382 8811 	msr	BASEPRI, r2
    5d7e:	f3bf 8f6f 	isb	sy
			notify_one(mgr, cli, state, 0);
    5d82:	2300      	movs	r3, #0
    5d84:	4622      	mov	r2, r4
    5d86:	4631      	mov	r1, r6
    5d88:	4628      	mov	r0, r5
    5d8a:	f7ff ff9b 	bl	5cc4 <notify_one>
    5d8e:	e7ee      	b.n	5d6e <onoff_request+0x3a>
	} else if ((state == ONOFF_STATE_OFF)
    5d90:	2c06      	cmp	r4, #6
    5d92:	d814      	bhi.n	5dbe <onoff_request+0x8a>
    5d94:	e8df f004 	tbb	[pc, r4]
    5d98:	13131304 	.word	0x13131304
    5d9c:	1a04      	.short	0x1a04
    5d9e:	04          	.byte	0x04
    5d9f:	00          	.byte	0x00
	parent->next = child;
    5da0:	2300      	movs	r3, #0
    5da2:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    5da4:	686b      	ldr	r3, [r5, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    5da6:	b93b      	cbnz	r3, 5db8 <onoff_request+0x84>
	list->head = node;
    5da8:	e9c5 6600 	strd	r6, r6, [r5]
	if (start) {
    5dac:	b9ac      	cbnz	r4, 5dda <onoff_request+0xa6>
		process_event(mgr, EVT_RECHECK, key);
    5dae:	2102      	movs	r1, #2
    5db0:	4628      	mov	r0, r5
    5db2:	f7fa ff91 	bl	cd8 <process_event>
    5db6:	e7da      	b.n	5d6e <onoff_request+0x3a>
	parent->next = child;
    5db8:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5dba:	606e      	str	r6, [r5, #4]
}
    5dbc:	e7f6      	b.n	5dac <onoff_request+0x78>
    5dbe:	f382 8811 	msr	BASEPRI, r2
    5dc2:	f3bf 8f6f 	isb	sy
		rv = -EIO;
    5dc6:	f06f 0404 	mvn.w	r4, #4
    5dca:	e7d0      	b.n	5d6e <onoff_request+0x3a>
    5dcc:	f382 8811 	msr	BASEPRI, r2
    5dd0:	f3bf 8f6f 	isb	sy
    5dd4:	f06f 0485 	mvn.w	r4, #133	; 0x85
    5dd8:	e7c9      	b.n	5d6e <onoff_request+0x3a>
    5dda:	f382 8811 	msr	BASEPRI, r2
    5dde:	f3bf 8f6f 	isb	sy
		if (notify) {
    5de2:	e7c4      	b.n	5d6e <onoff_request+0x3a>

00005de4 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5de4:	4603      	mov	r3, r0
    5de6:	b158      	cbz	r0, 5e00 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5de8:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    5dea:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5dee:	2a01      	cmp	r2, #1
    5df0:	d003      	beq.n	5dfa <sys_notify_validate+0x16>
    5df2:	2a03      	cmp	r2, #3
    5df4:	d104      	bne.n	5e00 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5df6:	6802      	ldr	r2, [r0, #0]
    5df8:	b112      	cbz	r2, 5e00 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5dfa:	2000      	movs	r0, #0
    5dfc:	6098      	str	r0, [r3, #8]
    5dfe:	4770      	bx	lr
    5e00:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5e04:	4770      	bx	lr

00005e06 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5e06:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    5e08:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    5e0a:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    5e0e:	2a03      	cmp	r2, #3
    5e10:	f04f 0200 	mov.w	r2, #0
{
    5e14:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5e16:	bf0c      	ite	eq
    5e18:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    5e1a:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    5e1c:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5e1e:	4770      	bx	lr

00005e20 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_META, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_WARN_DEPRECATED, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_ENFORCE_ZEPHYR_STDINT, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    5e20:	4770      	bx	lr

00005e22 <flash_area_close>:

void flash_area_close(const struct flash_area *fa)
{
	/* nothing to do for now */
}
    5e22:	4770      	bx	lr

00005e24 <flash_area_read>:


static inline bool is_in_flash_area_bounds(const struct flash_area *fa,
					   off_t off, size_t len)
{
	return (off >= 0) && ((off + len) <= fa->fa_size);
    5e24:	2900      	cmp	r1, #0

int flash_area_read(const struct flash_area *fa, off_t off, void *dst,
		    size_t len)
{
    5e26:	b430      	push	{r4, r5}
    5e28:	4604      	mov	r4, r0
    5e2a:	4618      	mov	r0, r3
    5e2c:	db0b      	blt.n	5e46 <flash_area_read+0x22>
    5e2e:	68a5      	ldr	r5, [r4, #8]
    5e30:	4408      	add	r0, r1
    5e32:	42a8      	cmp	r0, r5
    5e34:	d807      	bhi.n	5e46 <flash_area_read+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_read(fa->fa_dev, fa->fa_off + off, dst, len);
    5e36:	68e0      	ldr	r0, [r4, #12]
    5e38:	6864      	ldr	r4, [r4, #4]
    5e3a:	4421      	add	r1, r4
				    size_t len)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->read(dev, offset, data, len);
    5e3c:	6884      	ldr	r4, [r0, #8]
    5e3e:	6824      	ldr	r4, [r4, #0]
    5e40:	46a4      	mov	ip, r4
}
    5e42:	bc30      	pop	{r4, r5}
    5e44:	4760      	bx	ip
    5e46:	f06f 0015 	mvn.w	r0, #21
    5e4a:	bc30      	pop	{r4, r5}
    5e4c:	4770      	bx	lr

00005e4e <flash_area_write>:
    5e4e:	2900      	cmp	r1, #0

int flash_area_write(const struct flash_area *fa, off_t off, const void *src,
		     size_t len)
{
    5e50:	b430      	push	{r4, r5}
    5e52:	4604      	mov	r4, r0
    5e54:	4618      	mov	r0, r3
    5e56:	db0b      	blt.n	5e70 <flash_area_write+0x22>
    5e58:	68a5      	ldr	r5, [r4, #8]
    5e5a:	4408      	add	r0, r1
    5e5c:	42a8      	cmp	r0, r5
    5e5e:	d807      	bhi.n	5e70 <flash_area_write+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_write(fa->fa_dev, fa->fa_off + off, (void *)src, len);
    5e60:	68e0      	ldr	r0, [r4, #12]
    5e62:	6864      	ldr	r4, [r4, #4]
    5e64:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->write(dev, offset, data, len);
    5e66:	6884      	ldr	r4, [r0, #8]
    5e68:	6864      	ldr	r4, [r4, #4]
    5e6a:	46a4      	mov	ip, r4
}
    5e6c:	bc30      	pop	{r4, r5}
    5e6e:	4760      	bx	ip
    5e70:	f06f 0015 	mvn.w	r0, #21
    5e74:	bc30      	pop	{r4, r5}
    5e76:	4770      	bx	lr

00005e78 <flash_area_erase>:
    5e78:	2900      	cmp	r1, #0

int flash_area_erase(const struct flash_area *fa, off_t off, size_t len)
{
    5e7a:	4603      	mov	r3, r0
    5e7c:	b410      	push	{r4}
    5e7e:	4610      	mov	r0, r2
    5e80:	db0b      	blt.n	5e9a <flash_area_erase+0x22>
    5e82:	689c      	ldr	r4, [r3, #8]
    5e84:	4408      	add	r0, r1
    5e86:	42a0      	cmp	r0, r4
    5e88:	d807      	bhi.n	5e9a <flash_area_erase+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_erase(fa->fa_dev, fa->fa_off + off, len);
    5e8a:	68d8      	ldr	r0, [r3, #12]
    5e8c:	685b      	ldr	r3, [r3, #4]
    5e8e:	4419      	add	r1, r3
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->erase(dev, offset, size);
    5e90:	6883      	ldr	r3, [r0, #8]
}
    5e92:	f85d 4b04 	ldr.w	r4, [sp], #4
    5e96:	689b      	ldr	r3, [r3, #8]
    5e98:	4718      	bx	r3
    5e9a:	f06f 0015 	mvn.w	r0, #21
    5e9e:	f85d 4b04 	ldr.w	r4, [sp], #4
    5ea2:	4770      	bx	lr

00005ea4 <flash_area_align>:

uint32_t flash_area_align(const struct flash_area *fa)
{
    5ea4:	b508      	push	{r3, lr}
	return flash_get_write_block_size(fa->fa_dev);
    5ea6:	68c0      	ldr	r0, [r0, #12]
static inline size_t z_impl_flash_get_write_block_size(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev)->write_block_size;
    5ea8:	6883      	ldr	r3, [r0, #8]
    5eaa:	68db      	ldr	r3, [r3, #12]
    5eac:	4798      	blx	r3
}
    5eae:	6800      	ldr	r0, [r0, #0]
    5eb0:	bd08      	pop	{r3, pc}

00005eb2 <flash_area_erased_val>:
{
	return fa->fa_dev;
}

uint8_t flash_area_erased_val(const struct flash_area *fa)
{
    5eb2:	b508      	push	{r3, lr}
	const struct flash_parameters *param;

	param = flash_get_parameters(fa->fa_dev);
    5eb4:	68c0      	ldr	r0, [r0, #12]
static inline const struct flash_parameters *z_impl_flash_get_parameters(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev);
    5eb6:	6883      	ldr	r3, [r0, #8]
    5eb8:	68db      	ldr	r3, [r3, #12]
    5eba:	4798      	blx	r3

	return param->erase_value;
}
    5ebc:	7900      	ldrb	r0, [r0, #4]
    5ebe:	bd08      	pop	{r3, pc}

00005ec0 <get_sectors_cb>:
{
    5ec0:	b570      	push	{r4, r5, r6, lr}
	if (info->start_offset < data->area_off) {
    5ec2:	684c      	ldr	r4, [r1, #4]
    5ec4:	6803      	ldr	r3, [r0, #0]
    5ec6:	42a3      	cmp	r3, r4
    5ec8:	d201      	bcs.n	5ece <get_sectors_cb+0xe>
		*bail_value = true;
    5eca:	2001      	movs	r0, #1
}
    5ecc:	bd70      	pop	{r4, r5, r6, pc}
	} else if (info->start_offset >= data->area_off + data->area_len) {
    5ece:	688a      	ldr	r2, [r1, #8]
    5ed0:	4422      	add	r2, r4
    5ed2:	4293      	cmp	r3, r2
    5ed4:	d301      	bcc.n	5eda <get_sectors_cb+0x1a>
		*bail_value = false;
    5ed6:	2000      	movs	r0, #0
    5ed8:	e7f8      	b.n	5ecc <get_sectors_cb+0xc>
	} else if (data->ret_idx >= data->ret_len) {
    5eda:	e9d1 2503 	ldrd	r2, r5, [r1, #12]
    5ede:	694e      	ldr	r6, [r1, #20]
    5ee0:	42b5      	cmp	r5, r6
    5ee2:	d303      	bcc.n	5eec <get_sectors_cb+0x2c>
		data->status = -ENOMEM;
    5ee4:	f06f 030b 	mvn.w	r3, #11
    5ee8:	618b      	str	r3, [r1, #24]
		return true;
    5eea:	e7f4      	b.n	5ed6 <get_sectors_cb+0x16>
	ret[data->ret_idx].fs_off = info->start_offset - data->area_off;
    5eec:	1b1b      	subs	r3, r3, r4
    5eee:	f842 3035 	str.w	r3, [r2, r5, lsl #3]
	ret[data->ret_idx].fs_size = info->size;
    5ef2:	6843      	ldr	r3, [r0, #4]
    5ef4:	6908      	ldr	r0, [r1, #16]
    5ef6:	eb02 02c0 	add.w	r2, r2, r0, lsl #3
    5efa:	6053      	str	r3, [r2, #4]
	data->ret_idx++;
    5efc:	690b      	ldr	r3, [r1, #16]
    5efe:	3301      	adds	r3, #1
    5f00:	610b      	str	r3, [r1, #16]
	return true;
    5f02:	e7e2      	b.n	5eca <get_sectors_cb+0xa>

00005f04 <abort_function>:
	while(1);
    5f04:	e7fe      	b.n	5f04 <abort_function>

00005f06 <nrf_cc3xx_platform_mutex_init>:
/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
	// No thread-safe mutexes are required
}
    5f06:	4770      	bx	lr

00005f08 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    5f08:	f000 bc13 	b.w	6732 <z_fatal_error>

00005f0c <z_do_kernel_oops>:
 *
 * @param esf exception frame
 * @param callee_regs Callee-saved registers (R4-R11)
 */
void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs)
{
    5f0c:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    5f0e:	6800      	ldr	r0, [r0, #0]
    5f10:	f000 bc0f 	b.w	6732 <z_fatal_error>

00005f14 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    5f14:	2100      	movs	r1, #0
    5f16:	2001      	movs	r0, #1
    5f18:	f7ff bff6 	b.w	5f08 <z_arm_fatal_error>

00005f1c <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    5f1c:	b508      	push	{r3, lr}
	handler();
    5f1e:	f7fb f8a1 	bl	1064 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    5f22:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    5f26:	f7fb b923 	b.w	1170 <z_arm_exc_exit>

00005f2a <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    5f2a:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    5f2c:	b15a      	cbz	r2, 5f46 <memcmp+0x1c>
    5f2e:	3901      	subs	r1, #1
    5f30:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    5f32:	f810 2b01 	ldrb.w	r2, [r0], #1
    5f36:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    5f3a:	42a0      	cmp	r0, r4
    5f3c:	d001      	beq.n	5f42 <memcmp+0x18>
    5f3e:	429a      	cmp	r2, r3
    5f40:	d0f7      	beq.n	5f32 <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    5f42:	1ad0      	subs	r0, r2, r3
}
    5f44:	bd10      	pop	{r4, pc}
		return 0;
    5f46:	4610      	mov	r0, r2
    5f48:	e7fc      	b.n	5f44 <memcmp+0x1a>

00005f4a <memmove>:
void *memmove(void *d, const void *s, size_t n)
{
	char *dest = d;
	const char *src  = s;

	if ((size_t) (dest - src) < n) {
    5f4a:	1a43      	subs	r3, r0, r1
    5f4c:	4293      	cmp	r3, r2
{
    5f4e:	b510      	push	{r4, lr}
    5f50:	eb00 0302 	add.w	r3, r0, r2
	if ((size_t) (dest - src) < n) {
    5f54:	d308      	bcc.n	5f68 <memmove+0x1e>
    5f56:	3901      	subs	r1, #1
	char *dest = d;
    5f58:	4602      	mov	r2, r0
			n--;
			dest[n] = src[n];
		}
	} else {
		/* It is safe to perform a forward-copy */
		while (n > 0) {
    5f5a:	429a      	cmp	r2, r3
    5f5c:	d00b      	beq.n	5f76 <memmove+0x2c>
			*dest = *src;
    5f5e:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    5f62:	f802 4b01 	strb.w	r4, [r2], #1
			dest++;
			src++;
			n--;
    5f66:	e7f8      	b.n	5f5a <memmove+0x10>
    5f68:	440a      	add	r2, r1
			dest[n] = src[n];
    5f6a:	f812 4d01 	ldrb.w	r4, [r2, #-1]!
    5f6e:	f803 4d01 	strb.w	r4, [r3, #-1]!
		while (n > 0) {
    5f72:	428a      	cmp	r2, r1
    5f74:	d1f9      	bne.n	5f6a <memmove+0x20>
		}
	}

	return d;
}
    5f76:	bd10      	pop	{r4, pc}

00005f78 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    5f78:	b510      	push	{r4, lr}
    5f7a:	1e43      	subs	r3, r0, #1
    5f7c:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    5f7e:	4291      	cmp	r1, r2
    5f80:	d100      	bne.n	5f84 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    5f82:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    5f84:	f811 4b01 	ldrb.w	r4, [r1], #1
    5f88:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    5f8c:	e7f7      	b.n	5f7e <memcpy+0x6>

00005f8e <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    5f8e:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    5f90:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    5f92:	4603      	mov	r3, r0
	while (n > 0) {
    5f94:	4293      	cmp	r3, r2
    5f96:	d100      	bne.n	5f9a <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    5f98:	4770      	bx	lr
		*(d_byte++) = c_byte;
    5f9a:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5f9e:	e7f9      	b.n	5f94 <memset+0x6>

00005fa0 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    5fa0:	6903      	ldr	r3, [r0, #16]
    5fa2:	b2c9      	uxtb	r1, r1
    5fa4:	220c      	movs	r2, #12
    5fa6:	fb01 3302 	mla	r3, r1, r2, r3
    5faa:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
    5fac:	f000 0007 	and.w	r0, r0, #7
    5fb0:	4770      	bx	lr

00005fb2 <set_on_state>:
	__asm__ volatile(
    5fb2:	f04f 0320 	mov.w	r3, #32
    5fb6:	f3ef 8211 	mrs	r2, BASEPRI
    5fba:	f383 8812 	msr	BASEPRI_MAX, r3
    5fbe:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    5fc2:	6803      	ldr	r3, [r0, #0]
    5fc4:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    5fc8:	f043 0302 	orr.w	r3, r3, #2
    5fcc:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    5fce:	f382 8811 	msr	BASEPRI, r2
    5fd2:	f3bf 8f6f 	isb	sy
}
    5fd6:	4770      	bx	lr

00005fd8 <stop>:
{
    5fd8:	b570      	push	{r4, r5, r6, lr}
    5fda:	b2c9      	uxtb	r1, r1
	struct nrf_clock_control_data *data = dev->data;
    5fdc:	6903      	ldr	r3, [r0, #16]
	__asm__ volatile(
    5fde:	f04f 0420 	mov.w	r4, #32
    5fe2:	f3ef 8511 	mrs	r5, BASEPRI
    5fe6:	f384 8812 	msr	BASEPRI_MAX, r4
    5fea:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    5fee:	260c      	movs	r6, #12
    5ff0:	fb06 3401 	mla	r4, r6, r1, r3
    5ff4:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    5ff6:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    5ffa:	d008      	beq.n	600e <stop+0x36>
    5ffc:	42a2      	cmp	r2, r4
    5ffe:	d006      	beq.n	600e <stop+0x36>
	__asm__ volatile(
    6000:	f385 8811 	msr	BASEPRI, r5
    6004:	f3bf 8f6f 	isb	sy
		err = -EPERM;
    6008:	f04f 30ff 	mov.w	r0, #4294967295
}
    600c:	bd70      	pop	{r4, r5, r6, pc}
		*flags = CLOCK_CONTROL_STATUS_OFF;
    600e:	fb06 3301 	mla	r3, r6, r1, r3
    6012:	2201      	movs	r2, #1
    6014:	641a      	str	r2, [r3, #64]	; 0x40
    6016:	f385 8811 	msr	BASEPRI, r5
    601a:	f3bf 8f6f 	isb	sy
	get_sub_config(dev, type)->stop();
    601e:	6843      	ldr	r3, [r0, #4]
    6020:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
    6024:	685b      	ldr	r3, [r3, #4]
    6026:	4798      	blx	r3
	return 0;
    6028:	2000      	movs	r0, #0
    602a:	e7ef      	b.n	600c <stop+0x34>

0000602c <api_stop>:
	return stop(dev, subsys, CTX_API);
    602c:	2280      	movs	r2, #128	; 0x80
    602e:	f7ff bfd3 	b.w	5fd8 <stop>

00006032 <async_start>:
{
    6032:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6034:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    6036:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    6038:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    603a:	f04f 0520 	mov.w	r5, #32
    603e:	f3ef 8611 	mrs	r6, BASEPRI
    6042:	f385 8812 	msr	BASEPRI_MAX, r5
    6046:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    604a:	250c      	movs	r5, #12
    604c:	fb05 4401 	mla	r4, r5, r1, r4
    6050:	6c25      	ldr	r5, [r4, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    6052:	f005 0c07 	and.w	ip, r5, #7
    6056:	f1bc 0f01 	cmp.w	ip, #1
    605a:	d10c      	bne.n	6076 <async_start+0x44>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    605c:	6427      	str	r7, [r4, #64]	; 0x40
	__asm__ volatile(
    605e:	f386 8811 	msr	BASEPRI, r6
    6062:	f3bf 8f6f 	isb	sy
	subdata->user_data = user_data;
    6066:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    606a:	6843      	ldr	r3, [r0, #4]
    606c:	f853 3031 	ldr.w	r3, [r3, r1, lsl #3]
    6070:	4798      	blx	r3
	return 0;
    6072:	2000      	movs	r0, #0
}
    6074:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    6076:	f005 05c0 	and.w	r5, r5, #192	; 0xc0
	} else if (current_ctx != ctx) {
    607a:	42af      	cmp	r7, r5
    607c:	f386 8811 	msr	BASEPRI, r6
    6080:	f3bf 8f6f 	isb	sy
		err = -EALREADY;
    6084:	bf0c      	ite	eq
    6086:	f06f 0077 	mvneq.w	r0, #119	; 0x77
		err = -EPERM;
    608a:	f04f 30ff 	movne.w	r0, #4294967295
    608e:	e7f1      	b.n	6074 <async_start+0x42>

00006090 <api_start>:
{
    6090:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    6092:	2480      	movs	r4, #128	; 0x80
    6094:	9400      	str	r4, [sp, #0]
    6096:	f7ff ffcc 	bl	6032 <async_start>
}
    609a:	b002      	add	sp, #8
    609c:	bd10      	pop	{r4, pc}

0000609e <api_blocking_start>:
}
    609e:	f06f 0085 	mvn.w	r0, #133	; 0x85
    60a2:	4770      	bx	lr

000060a4 <onoff_started_callback>:
{
    60a4:	b410      	push	{r4}
	return &data->mgr[type];
    60a6:	6900      	ldr	r0, [r0, #16]
    60a8:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    60aa:	241c      	movs	r4, #28
    60ac:	fb03 0004 	mla	r0, r3, r4, r0
    60b0:	2100      	movs	r1, #0
}
    60b2:	f85d 4b04 	ldr.w	r4, [sp], #4
	notify(mgr, 0);
    60b6:	4710      	bx	r2

000060b8 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    60b8:	2000      	movs	r0, #0
    60ba:	f000 ba66 	b.w	658a <nrfx_clock_start>

000060be <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    60be:	2000      	movs	r0, #0
    60c0:	f000 ba9f 	b.w	6602 <nrfx_clock_stop>

000060c4 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    60c4:	6843      	ldr	r3, [r0, #4]
    60c6:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    60c8:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    60cc:	600b      	str	r3, [r1, #0]
}
    60ce:	2000      	movs	r0, #0
    60d0:	4770      	bx	lr

000060d2 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    60d2:	6843      	ldr	r3, [r0, #4]
    60d4:	685b      	ldr	r3, [r3, #4]
	const uint32_t set_mask = value & mask;
    60d6:	ea02 0001 	and.w	r0, r2, r1
	const uint32_t clear_mask = (~set_mask) & mask;
    60da:	ea21 0102 	bic.w	r1, r1, r2
    p_reg->OUTSET = set_mask;
    60de:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    60e2:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    60e6:	2000      	movs	r0, #0
    60e8:	4770      	bx	lr

000060ea <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    60ea:	6843      	ldr	r3, [r0, #4]
    60ec:	685b      	ldr	r3, [r3, #4]
}
    60ee:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    60f0:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    60f4:	4770      	bx	lr

000060f6 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    60f6:	6843      	ldr	r3, [r0, #4]
    60f8:	685b      	ldr	r3, [r3, #4]
}
    60fa:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    60fc:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    6100:	4770      	bx	lr

00006102 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6102:	6843      	ldr	r3, [r0, #4]
    6104:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    6106:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	const uint32_t set_mask = value & mask;
    610a:	ea21 0003 	bic.w	r0, r1, r3
	const uint32_t clear_mask = (~value) & mask;
    610e:	400b      	ands	r3, r1
    p_reg->OUTSET = set_mask;
    6110:	f8c2 0508 	str.w	r0, [r2, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    6114:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
}
    6118:	2000      	movs	r0, #0
    611a:	4770      	bx	lr

0000611c <gpio_nrfx_manage_callback>:
{
    611c:	b510      	push	{r4, lr}
	return port->data;
    611e:	6903      	ldr	r3, [r0, #16]
	return list->head;
    6120:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    6122:	b1f8      	cbz	r0, 6164 <gpio_nrfx_manage_callback+0x48>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6124:	4288      	cmp	r0, r1
    6126:	d119      	bne.n	615c <gpio_nrfx_manage_callback+0x40>
Z_GENLIST_REMOVE(slist, snode)
    6128:	689c      	ldr	r4, [r3, #8]
	return node->next;
    612a:	6808      	ldr	r0, [r1, #0]
	list->head = node;
    612c:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    612e:	42a1      	cmp	r1, r4
    6130:	d100      	bne.n	6134 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    6132:	6098      	str	r0, [r3, #8]
	parent->next = child;
    6134:	2000      	movs	r0, #0
    6136:	6008      	str	r0, [r1, #0]
	if (set) {
    6138:	b12a      	cbz	r2, 6146 <gpio_nrfx_manage_callback+0x2a>
	return list->head;
    613a:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    613c:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    613e:	689a      	ldr	r2, [r3, #8]
	list->head = node;
    6140:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    6142:	b902      	cbnz	r2, 6146 <gpio_nrfx_manage_callback+0x2a>
	list->tail = node;
    6144:	6099      	str	r1, [r3, #8]
	return 0;
    6146:	2000      	movs	r0, #0
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    6148:	e010      	b.n	616c <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    614a:	4281      	cmp	r1, r0
    614c:	d106      	bne.n	615c <gpio_nrfx_manage_callback+0x40>
	return node->next;
    614e:	6808      	ldr	r0, [r1, #0]
	parent->next = child;
    6150:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    6152:	6898      	ldr	r0, [r3, #8]
    6154:	4281      	cmp	r1, r0
    6156:	d1ed      	bne.n	6134 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    6158:	609c      	str	r4, [r3, #8]
}
    615a:	e7eb      	b.n	6134 <gpio_nrfx_manage_callback+0x18>
	return node->next;
    615c:	4604      	mov	r4, r0
    615e:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6160:	2800      	cmp	r0, #0
    6162:	d1f2      	bne.n	614a <gpio_nrfx_manage_callback+0x2e>
			if (!set) {
    6164:	2a00      	cmp	r2, #0
    6166:	d1e8      	bne.n	613a <gpio_nrfx_manage_callback+0x1e>
				return -EINVAL;
    6168:	f06f 0015 	mvn.w	r0, #21
}
    616c:	bd10      	pop	{r4, pc}

0000616e <qspi_handler>:
	if (event == NRFX_QSPI_EVENT_DONE) {
    616e:	b908      	cbnz	r0, 6174 <qspi_handler+0x6>
	dev_data->ready = true;
    6170:	2301      	movs	r3, #1
    6172:	700b      	strb	r3, [r1, #0]
}
    6174:	4770      	bx	lr

00006176 <qspi_send_cmd.constprop.0>:
static int qspi_send_cmd(const struct device *dev, const struct qspi_cmd *cmd,
    6176:	b537      	push	{r0, r1, r2, r4, r5, lr}
    6178:	460d      	mov	r5, r1
	if (cmd->tx_buf) {
    617a:	6841      	ldr	r1, [r0, #4]
    617c:	b311      	cbz	r1, 61c4 <qspi_send_cmd.constprop.0+0x4e>
		tx_buf = cmd->tx_buf->buf;
    617e:	e9d1 1300 	ldrd	r1, r3, [r1]
	if (cmd->rx_buf) {
    6182:	6884      	ldr	r4, [r0, #8]
    6184:	b304      	cbz	r4, 61c8 <qspi_send_cmd.constprop.0+0x52>
		rx_len = cmd->rx_buf->len;
    6186:	e9d4 2400 	ldrd	r2, r4, [r4]
	if ((rx_len != 0) && (tx_len != 0)) {
    618a:	b1f4      	cbz	r4, 61ca <qspi_send_cmd.constprop.0+0x54>
    618c:	b1eb      	cbz	r3, 61ca <qspi_send_cmd.constprop.0+0x54>
		if (rx_len != tx_len) {
    618e:	429c      	cmp	r4, r3
    6190:	d11e      	bne.n	61d0 <qspi_send_cmd.constprop.0+0x5a>
		xfer_len += tx_len;
    6192:	3301      	adds	r3, #1
	if (xfer_len > NRF_QSPI_CINSTR_LEN_9B) {
    6194:	2b09      	cmp	r3, #9
    6196:	d81b      	bhi.n	61d0 <qspi_send_cmd.constprop.0+0x5a>
	nrf_qspi_cinstr_conf_t cinstr_cfg = {
    6198:	7800      	ldrb	r0, [r0, #0]
    619a:	f88d 3001 	strb.w	r3, [sp, #1]
    619e:	f240 1301 	movw	r3, #257	; 0x101
    61a2:	f88d 0000 	strb.w	r0, [sp]
    61a6:	f8ad 3002 	strh.w	r3, [sp, #2]
	int res = nrfx_qspi_cinstr_xfer(&cinstr_cfg, tx_buf, rx_buf);
    61aa:	4668      	mov	r0, sp
	nrf_qspi_cinstr_conf_t cinstr_cfg = {
    61ac:	2300      	movs	r3, #0
    61ae:	f88d 3004 	strb.w	r3, [sp, #4]
    61b2:	f88d 5005 	strb.w	r5, [sp, #5]
	int res = nrfx_qspi_cinstr_xfer(&cinstr_cfg, tx_buf, rx_buf);
    61b6:	f7fd fb3d 	bl	3834 <nrfx_qspi_cinstr_xfer>
}
    61ba:	b003      	add	sp, #12
    61bc:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
	return qspi_get_zephyr_ret_code(res);
    61c0:	f7fb bcbc 	b.w	1b3c <qspi_get_zephyr_ret_code>
	size_t tx_len = 0;
    61c4:	460b      	mov	r3, r1
    61c6:	e7dc      	b.n	6182 <qspi_send_cmd.constprop.0+0xc>
	void *rx_buf = NULL;
    61c8:	4622      	mov	r2, r4
		xfer_len += tx_len + rx_len;
    61ca:	3301      	adds	r3, #1
    61cc:	4423      	add	r3, r4
    61ce:	e7e1      	b.n	6194 <qspi_send_cmd.constprop.0+0x1e>
}
    61d0:	f06f 0015 	mvn.w	r0, #21
    61d4:	b003      	add	sp, #12
    61d6:	bd30      	pop	{r4, r5, pc}

000061d8 <qspi_rdsr.constprop.0.isra.0>:
static int qspi_rdsr(const struct device *dev, uint8_t sr_num)
    61d8:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	uint8_t sr = 0xFF;
    61da:	23ff      	movs	r3, #255	; 0xff
    61dc:	f88d 3003 	strb.w	r3, [sp, #3]
	const struct qspi_buf sr_buf = {
    61e0:	f10d 0303 	add.w	r3, sp, #3
	struct qspi_cmd cmd = {
    61e4:	2100      	movs	r1, #0
	const struct qspi_buf sr_buf = {
    61e6:	9301      	str	r3, [sp, #4]
	struct qspi_cmd cmd = {
    61e8:	2301      	movs	r3, #1
    61ea:	e9cd 3102 	strd	r3, r1, [sp, #8]
    61ee:	2305      	movs	r3, #5
    61f0:	f88d 300c 	strb.w	r3, [sp, #12]
	int ret = qspi_send_cmd(dev, &cmd, false);
    61f4:	a803      	add	r0, sp, #12
	struct qspi_cmd cmd = {
    61f6:	ab01      	add	r3, sp, #4
    61f8:	9104      	str	r1, [sp, #16]
    61fa:	9305      	str	r3, [sp, #20]
	int ret = qspi_send_cmd(dev, &cmd, false);
    61fc:	f7ff ffbb 	bl	6176 <qspi_send_cmd.constprop.0>
	return (ret < 0) ? ret : sr;
    6200:	2800      	cmp	r0, #0
    6202:	bfa8      	it	ge
    6204:	f89d 0003 	ldrbge.w	r0, [sp, #3]
}
    6208:	b007      	add	sp, #28
    620a:	f85d fb04 	ldr.w	pc, [sp], #4

0000620e <qspi_nor_write_protection_set.isra.0>:
static int qspi_nor_write_protection_set(const struct device *dev,
    620e:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct qspi_cmd cmd = {
    6210:	2100      	movs	r1, #0
    6212:	4288      	cmp	r0, r1
    6214:	bf0c      	ite	eq
    6216:	2306      	moveq	r3, #6
    6218:	2304      	movne	r3, #4
	if (qspi_send_cmd(dev, &cmd, false) != 0) {
    621a:	a801      	add	r0, sp, #4
	struct qspi_cmd cmd = {
    621c:	e9cd 1101 	strd	r1, r1, [sp, #4]
    6220:	9103      	str	r1, [sp, #12]
    6222:	f88d 3004 	strb.w	r3, [sp, #4]
	if (qspi_send_cmd(dev, &cmd, false) != 0) {
    6226:	f7ff ffa6 	bl	6176 <qspi_send_cmd.constprop.0>
		ret = -EIO;
    622a:	2800      	cmp	r0, #0
}
    622c:	bf18      	it	ne
    622e:	f06f 0004 	mvnne.w	r0, #4
    6232:	b005      	add	sp, #20
    6234:	f85d fb04 	ldr.w	pc, [sp], #4

00006238 <is_regular_addr_valid>:
{
    6238:	b538      	push	{r3, r4, r5, lr}
    623a:	4605      	mov	r5, r0
    623c:	460c      	mov	r4, r1
	return is_within_bounds(addr, len, 0, nrfx_nvmc_flash_size_get());
    623e:	f000 fa3a 	bl	66b6 <nrfx_nvmc_flash_size_get>
			(addr < (boundary_start + boundary_size)) &&
    6242:	2d00      	cmp	r5, #0
    6244:	db07      	blt.n	6256 <is_regular_addr_valid+0x1e>
	return (addr >= boundary_start &&
    6246:	42a8      	cmp	r0, r5
    6248:	d905      	bls.n	6256 <is_regular_addr_valid+0x1e>
			(len <= (boundary_start + boundary_size - addr)));
    624a:	1b40      	subs	r0, r0, r5
			(addr < (boundary_start + boundary_size)) &&
    624c:	4284      	cmp	r4, r0
    624e:	bf8c      	ite	hi
    6250:	2000      	movhi	r0, #0
    6252:	2001      	movls	r0, #1
}
    6254:	bd38      	pop	{r3, r4, r5, pc}
			(addr < (boundary_start + boundary_size)) &&
    6256:	2000      	movs	r0, #0
    6258:	e7fc      	b.n	6254 <is_regular_addr_valid+0x1c>

0000625a <flash_nrf_read>:
{
    625a:	b570      	push	{r4, r5, r6, lr}
    625c:	460d      	mov	r5, r1
	if (is_regular_addr_valid(addr, len)) {
    625e:	4628      	mov	r0, r5
    6260:	4619      	mov	r1, r3
{
    6262:	4616      	mov	r6, r2
    6264:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    6266:	f7ff ffe7 	bl	6238 <is_regular_addr_valid>
    626a:	b138      	cbz	r0, 627c <flash_nrf_read+0x22>
	if (!len) {
    626c:	b124      	cbz	r4, 6278 <flash_nrf_read+0x1e>
	memcpy(data, (void *)addr, len);
    626e:	4622      	mov	r2, r4
    6270:	4629      	mov	r1, r5
    6272:	4630      	mov	r0, r6
    6274:	f7ff fe80 	bl	5f78 <memcpy>
		return 0;
    6278:	2000      	movs	r0, #0
}
    627a:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    627c:	f06f 0015 	mvn.w	r0, #21
    6280:	e7fb      	b.n	627a <flash_nrf_read+0x20>

00006282 <flash_get_page_info>:

#include <zephyr/drivers/flash.h>

static int flash_get_page_info(const struct device *dev, off_t offs,
			       uint32_t index, struct flash_pages_info *info)
{
    6282:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    6286:	461c      	mov	r4, r3
    6288:	4690      	mov	r8, r2
	const struct flash_driver_api *api = dev->api;
	const struct flash_pages_layout *layout;
	size_t layout_size;
	uint32_t index_jmp;

	info->start_offset = 0;
    628a:	2300      	movs	r3, #0
	const struct flash_driver_api *api = dev->api;
    628c:	6882      	ldr	r2, [r0, #8]
	info->start_offset = 0;
    628e:	6023      	str	r3, [r4, #0]
	info->index = 0U;
    6290:	60a3      	str	r3, [r4, #8]

	api->page_layout(dev, &layout, &layout_size);
    6292:	6913      	ldr	r3, [r2, #16]
{
    6294:	460d      	mov	r5, r1
	api->page_layout(dev, &layout, &layout_size);
    6296:	aa01      	add	r2, sp, #4
    6298:	4669      	mov	r1, sp
    629a:	4798      	blx	r3

	while (layout_size--) {
    629c:	9b01      	ldr	r3, [sp, #4]
    629e:	1e5a      	subs	r2, r3, #1
    62a0:	9201      	str	r2, [sp, #4]
    62a2:	b923      	cbnz	r3, 62ae <flash_get_page_info+0x2c>
		}

		layout++;
	}

	return -EINVAL; /* page at offs or idx doesn't exist */
    62a4:	f06f 0015 	mvn.w	r0, #21
}
    62a8:	b002      	add	sp, #8
    62aa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		info->size = layout->pages_size;
    62ae:	9800      	ldr	r0, [sp, #0]
			index_jmp = index - info->index;
    62b0:	68a2      	ldr	r2, [r4, #8]
		info->size = layout->pages_size;
    62b2:	6847      	ldr	r7, [r0, #4]
			index_jmp = (offs - info->start_offset) / info->size;
    62b4:	6821      	ldr	r1, [r4, #0]
		info->size = layout->pages_size;
    62b6:	6067      	str	r7, [r4, #4]
		if (offs == 0) {
    62b8:	b985      	cbnz	r5, 62dc <flash_get_page_info+0x5a>
			index_jmp = index - info->index;
    62ba:	eba8 0302 	sub.w	r3, r8, r2
		index_jmp = MIN(index_jmp, layout->pages_count);
    62be:	6806      	ldr	r6, [r0, #0]
    62c0:	42b3      	cmp	r3, r6
    62c2:	bf28      	it	cs
    62c4:	4633      	movcs	r3, r6
		info->index += index_jmp;
    62c6:	441a      	add	r2, r3
		info->start_offset += (index_jmp * info->size);
    62c8:	fb03 1107 	mla	r1, r3, r7, r1
    62cc:	6021      	str	r1, [r4, #0]
		info->index += index_jmp;
    62ce:	60a2      	str	r2, [r4, #8]
		if (index_jmp < layout->pages_count) {
    62d0:	6802      	ldr	r2, [r0, #0]
    62d2:	429a      	cmp	r2, r3
    62d4:	d806      	bhi.n	62e4 <flash_get_page_info+0x62>
		layout++;
    62d6:	3008      	adds	r0, #8
    62d8:	9000      	str	r0, [sp, #0]
    62da:	e7df      	b.n	629c <flash_get_page_info+0x1a>
			index_jmp = (offs - info->start_offset) / info->size;
    62dc:	1a6b      	subs	r3, r5, r1
    62de:	fbb3 f3f7 	udiv	r3, r3, r7
    62e2:	e7ec      	b.n	62be <flash_get_page_info+0x3c>
			return 0;
    62e4:	2000      	movs	r0, #0
    62e6:	e7df      	b.n	62a8 <flash_get_page_info+0x26>

000062e8 <z_impl_flash_get_page_info_by_offs>:

int z_impl_flash_get_page_info_by_offs(const struct device *dev, off_t offs,
				       struct flash_pages_info *info)
{
    62e8:	4613      	mov	r3, r2
	return flash_get_page_info(dev, offs, 0U, info);
    62ea:	2200      	movs	r2, #0
    62ec:	f7ff bfc9 	b.w	6282 <flash_get_page_info>

000062f0 <flash_page_foreach>:
	return count;
}

void flash_page_foreach(const struct device *dev, flash_page_cb cb,
			void *data)
{
    62f0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	const struct flash_pages_layout *layout;
	struct flash_pages_info page_info;
	size_t block, num_blocks, page = 0, i;
	off_t off = 0;

	api->page_layout(dev, &layout, &num_blocks);
    62f4:	6883      	ldr	r3, [r0, #8]
{
    62f6:	b086      	sub	sp, #24
	api->page_layout(dev, &layout, &num_blocks);
    62f8:	691b      	ldr	r3, [r3, #16]
{
    62fa:	4688      	mov	r8, r1
    62fc:	4691      	mov	r9, r2
	api->page_layout(dev, &layout, &num_blocks);
    62fe:	a901      	add	r1, sp, #4
    6300:	aa02      	add	r2, sp, #8
    6302:	4798      	blx	r3
	off_t off = 0;
    6304:	2400      	movs	r4, #0
	size_t block, num_blocks, page = 0, i;
    6306:	46a2      	mov	sl, r4

	for (block = 0; block < num_blocks; block++) {
    6308:	4625      	mov	r5, r4
    630a:	9b02      	ldr	r3, [sp, #8]
    630c:	42ab      	cmp	r3, r5
    630e:	d802      	bhi.n	6316 <flash_page_foreach+0x26>

			off += page_info.size;
			page++;
		}
	}
}
    6310:	b006      	add	sp, #24
    6312:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		const struct flash_pages_layout *l = &layout[block];
    6316:	9f01      	ldr	r7, [sp, #4]
    6318:	eb07 07c5 	add.w	r7, r7, r5, lsl #3
		for (i = 0; i < l->pages_count; i++) {
    631c:	2600      	movs	r6, #0
		page_info.size = l->pages_size;
    631e:	687b      	ldr	r3, [r7, #4]
    6320:	9304      	str	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    6322:	683a      	ldr	r2, [r7, #0]
    6324:	42b2      	cmp	r2, r6
    6326:	eb0a 0306 	add.w	r3, sl, r6
    632a:	d802      	bhi.n	6332 <flash_page_foreach+0x42>
	for (block = 0; block < num_blocks; block++) {
    632c:	3501      	adds	r5, #1
    632e:	469a      	mov	sl, r3
    6330:	e7eb      	b.n	630a <flash_page_foreach+0x1a>
			page_info.start_offset = off;
    6332:	9403      	str	r4, [sp, #12]
			page_info.index = page;
    6334:	9305      	str	r3, [sp, #20]
			if (!cb(&page_info, data)) {
    6336:	4649      	mov	r1, r9
    6338:	a803      	add	r0, sp, #12
    633a:	47c0      	blx	r8
    633c:	2800      	cmp	r0, #0
    633e:	d0e7      	beq.n	6310 <flash_page_foreach+0x20>
			off += page_info.size;
    6340:	9b04      	ldr	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    6342:	3601      	adds	r6, #1
			off += page_info.size;
    6344:	441c      	add	r4, r3
		for (i = 0; i < l->pages_count; i++) {
    6346:	e7ec      	b.n	6322 <flash_page_foreach+0x32>

00006348 <sys_clock_set_timeout>:
}
    6348:	4770      	bx	lr

0000634a <sys_clock_elapsed>:
}
    634a:	2000      	movs	r0, #0
    634c:	4770      	bx	lr

0000634e <pinctrl_lookup_state>:

#include <zephyr/drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    634e:	b570      	push	{r4, r5, r6, lr}
	*state = &config->states[0];
    6350:	6843      	ldr	r3, [r0, #4]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    6352:	f06f 4660 	mvn.w	r6, #3758096384	; 0xe0000000
	*state = &config->states[0];
    6356:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    6358:	7a05      	ldrb	r5, [r0, #8]
    635a:	6844      	ldr	r4, [r0, #4]
    635c:	4435      	add	r5, r6
    635e:	eb04 04c5 	add.w	r4, r4, r5, lsl #3
    6362:	42a3      	cmp	r3, r4
    6364:	d902      	bls.n	636c <pinctrl_lookup_state+0x1e>
		}

		(*state)++;
	}

	return -ENOENT;
    6366:	f06f 0001 	mvn.w	r0, #1
}
    636a:	bd70      	pop	{r4, r5, r6, pc}
		if (id == (*state)->id) {
    636c:	795c      	ldrb	r4, [r3, #5]
    636e:	428c      	cmp	r4, r1
    6370:	d001      	beq.n	6376 <pinctrl_lookup_state+0x28>
		(*state)++;
    6372:	3308      	adds	r3, #8
    6374:	e7ef      	b.n	6356 <pinctrl_lookup_state+0x8>
			return 0;
    6376:	2000      	movs	r0, #0
    6378:	e7f7      	b.n	636a <pinctrl_lookup_state+0x1c>

0000637a <fprotect_set_permission>:

static int fprotect_set_permission(uint32_t start, size_t length,
				   size_t permission)
{
    637a:	b573      	push	{r0, r1, r4, r5, r6, lr}
    637c:	4605      	mov	r5, r0
	__ASSERT_NO_MSG(nrf_ficr_codepagesize_get(NRF_FICR) ==
			CONFIG_FPROTECT_BLOCK_SIZE);

	uint32_t region_idx;
	int result = find_free_region(&region_idx);
    637e:	a801      	add	r0, sp, #4
{
    6380:	460c      	mov	r4, r1
    6382:	4616      	mov	r6, r2
	int result = find_free_region(&region_idx);
    6384:	f7fc f9f8 	bl	2778 <find_free_region>

	if (result != 0) {
    6388:	bb70      	cbnz	r0, 63e8 <fprotect_set_permission+0x6e>
    638a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    638e:	6919      	ldr	r1, [r3, #16]
		return result;
	}

	if (start % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    6390:	fbb5 f2f1 	udiv	r2, r5, r1
    6394:	fb01 5212 	mls	r2, r1, r2, r5
    6398:	bb42      	cbnz	r2, 63ec <fprotect_set_permission+0x72>
    639a:	6919      	ldr	r1, [r3, #16]
	    length % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    639c:	fbb4 f2f1 	udiv	r2, r4, r1
    63a0:	fb01 4212 	mls	r2, r1, r2, r4
	if (start % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    63a4:	bb12      	cbnz	r2, 63ec <fprotect_set_permission+0x72>
    63a6:	691a      	ldr	r2, [r3, #16]
NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk)
    return p_reg->INFO.CODESIZE;
#else
    return p_reg->CODESIZE;
    63a8:	695b      	ldr	r3, [r3, #20]
	    length > NRF_ACL_REGION_SIZE_MAX || length == 0) {
    63aa:	4353      	muls	r3, r2
	    length % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    63ac:	42a3      	cmp	r3, r4
    63ae:	d31d      	bcc.n	63ec <fprotect_set_permission+0x72>
	    length > NRF_ACL_REGION_SIZE_MAX || length == 0) {
    63b0:	b1e4      	cbz	r4, 63ec <fprotect_set_permission+0x72>
		return -EINVAL;
	}

	nrf_acl_region_set(NRF_ACL, region_idx, start, length, permission);
    63b2:	9b01      	ldr	r3, [sp, #4]
    p_reg->ACL[region_id].ADDR = address;
    63b4:	011b      	lsls	r3, r3, #4
    63b6:	f103 4180 	add.w	r1, r3, #1073741824	; 0x40000000
    63ba:	f501 31f0 	add.w	r1, r1, #122880	; 0x1e000
    63be:	f8c1 5800 	str.w	r5, [r1, #2048]	; 0x800
    p_reg->ACL[region_id].SIZE = size;
    63c2:	f8c1 4804 	str.w	r4, [r1, #2052]	; 0x804
    p_reg->ACL[region_id].PERM = perm;
    63c6:	f8c1 6808 	str.w	r6, [r1, #2056]	; 0x808
    return (uint32_t)p_reg->ACL[region_id].ADDR;
    63ca:	f8d1 2800 	ldr.w	r2, [r1, #2048]	; 0x800

	if ((nrf_acl_region_address_get(NRF_ACL, region_idx) != start)
    63ce:	4295      	cmp	r5, r2
    63d0:	d10f      	bne.n	63f2 <fprotect_set_permission+0x78>
    return (size_t)p_reg->ACL[region_id].SIZE;
    63d2:	f8d1 2804 	ldr.w	r2, [r1, #2052]	; 0x804
		|| (nrf_acl_region_size_get(NRF_ACL, region_idx) != length)
    63d6:	4294      	cmp	r4, r2
    63d8:	d10b      	bne.n	63f2 <fprotect_set_permission+0x78>
    return (nrf_acl_perm_t)p_reg->ACL[region_id].PERM;
    63da:	f8d1 3808 	ldr.w	r3, [r1, #2056]	; 0x808
		|| (nrf_acl_region_perm_get(NRF_ACL, region_idx) != permission)) {
    63de:	b2db      	uxtb	r3, r3
		return -EFAULT;
    63e0:	42b3      	cmp	r3, r6
    63e2:	bf18      	it	ne
    63e4:	f06f 000d 	mvnne.w	r0, #13
	}

	return 0;
}
    63e8:	b002      	add	sp, #8
    63ea:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    63ec:	f06f 0015 	mvn.w	r0, #21
    63f0:	e7fa      	b.n	63e8 <fprotect_set_permission+0x6e>
		return -EFAULT;
    63f2:	f06f 000d 	mvn.w	r0, #13
    63f6:	e7f7      	b.n	63e8 <fprotect_set_permission+0x6e>

000063f8 <fprotect_area>:
	return 0;
}

int fprotect_area(uint32_t start, size_t length)
{
	return fprotect_set_permission(start, length,
    63f8:	2202      	movs	r2, #2
    63fa:	f7ff bfbe 	b.w	637a <fprotect_set_permission>

000063fe <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    63fe:	f7fd bc57 	b.w	3cb0 <nrf_cc3xx_platform_init_no_rng>

00006402 <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    6402:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    6404:	f7fa fdd0 	bl	fa8 <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    6408:	f7ff fd7d 	bl	5f06 <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    640c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    6410:	f7fd bc4e 	b.w	3cb0 <nrf_cc3xx_platform_init_no_rng>

00006414 <boot_swap_info_off>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6414:	6880      	ldr	r0, [r0, #8]
    6416:	3818      	subs	r0, #24
    6418:	f020 0007 	bic.w	r0, r0, #7
}
    641c:	3810      	subs	r0, #16
    641e:	4770      	bx	lr

00006420 <boot_magic_compatible_check>:
    switch (tbl_val) {
    6420:	2804      	cmp	r0, #4
    6422:	d009      	beq.n	6438 <boot_magic_compatible_check+0x18>
    6424:	2805      	cmp	r0, #5
    6426:	d103      	bne.n	6430 <boot_magic_compatible_check+0x10>
        return val != BOOT_MAGIC_GOOD;
    6428:	1e48      	subs	r0, r1, #1
    642a:	bf18      	it	ne
    642c:	2001      	movne	r0, #1
    642e:	4770      	bx	lr
        return tbl_val == val;
    6430:	1a43      	subs	r3, r0, r1
    6432:	4258      	negs	r0, r3
    6434:	4158      	adcs	r0, r3
    6436:	4770      	bx	lr
    switch (tbl_val) {
    6438:	2001      	movs	r0, #1
}
    643a:	4770      	bx	lr

0000643c <bootutil_buffer_is_erased>:
{
    643c:	b538      	push	{r3, r4, r5, lr}
    643e:	4615      	mov	r5, r2
    if (buffer == NULL || len == 0) {
    6440:	460c      	mov	r4, r1
    6442:	b161      	cbz	r1, 645e <bootutil_buffer_is_erased+0x22>
    6444:	b15a      	cbz	r2, 645e <bootutil_buffer_is_erased+0x22>
    erased_val = flash_area_erased_val(area);
    6446:	f7ff fd34 	bl	5eb2 <flash_area_erased_val>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    644a:	4425      	add	r5, r4
    644c:	4621      	mov	r1, r4
        if (u8b[i] != erased_val) {
    644e:	f811 3b01 	ldrb.w	r3, [r1], #1
    6452:	4283      	cmp	r3, r0
    6454:	d103      	bne.n	645e <bootutil_buffer_is_erased+0x22>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    6456:	42a9      	cmp	r1, r5
    6458:	d1f9      	bne.n	644e <bootutil_buffer_is_erased+0x12>
    return true;
    645a:	2001      	movs	r0, #1
}
    645c:	bd38      	pop	{r3, r4, r5, pc}
        return false;
    645e:	2000      	movs	r0, #0
    6460:	e7fc      	b.n	645c <bootutil_buffer_is_erased+0x20>

00006462 <boot_read_flag>:
{
    6462:	b538      	push	{r3, r4, r5, lr}
    6464:	460c      	mov	r4, r1
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6466:	2301      	movs	r3, #1
{
    6468:	4611      	mov	r1, r2
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    646a:	4622      	mov	r2, r4
{
    646c:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    646e:	f7ff fcd9 	bl	5e24 <flash_area_read>
    if (rc < 0) {
    6472:	2800      	cmp	r0, #0
    6474:	db0f      	blt.n	6496 <boot_read_flag+0x34>
    if (bootutil_buffer_is_erased(fap, flag, sizeof *flag)) {
    6476:	2201      	movs	r2, #1
    6478:	4621      	mov	r1, r4
    647a:	4628      	mov	r0, r5
    647c:	f7ff ffde 	bl	643c <bootutil_buffer_is_erased>
    6480:	b938      	cbnz	r0, 6492 <boot_read_flag+0x30>
    if (flag != BOOT_FLAG_SET) {
    6482:	7823      	ldrb	r3, [r4, #0]
    return BOOT_FLAG_SET;
    6484:	2b01      	cmp	r3, #1
        *flag = boot_flag_decode(*flag);
    6486:	bf14      	ite	ne
    6488:	2302      	movne	r3, #2
    648a:	2301      	moveq	r3, #1
    648c:	7023      	strb	r3, [r4, #0]
    648e:	2000      	movs	r0, #0
}
    6490:	bd38      	pop	{r3, r4, r5, pc}
    6492:	2303      	movs	r3, #3
    6494:	e7fa      	b.n	648c <boot_read_flag+0x2a>
        return BOOT_EFLASH;
    6496:	2001      	movs	r0, #1
    6498:	e7fa      	b.n	6490 <boot_read_flag+0x2e>

0000649a <boot_write_trailer>:
{
    649a:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    649e:	461d      	mov	r5, r3
    64a0:	4606      	mov	r6, r0
    64a2:	460f      	mov	r7, r1
    64a4:	4690      	mov	r8, r2
    align = flash_area_align(fap);
    64a6:	f7ff fcfd 	bl	5ea4 <flash_area_align>
    align = ALIGN_UP(inlen, align);
    64aa:	1e6c      	subs	r4, r5, #1
    64ac:	4404      	add	r4, r0
    64ae:	4240      	negs	r0, r0
    64b0:	4004      	ands	r4, r0
    if (align > BOOT_MAX_ALIGN) {
    64b2:	2c08      	cmp	r4, #8
    64b4:	d81a      	bhi.n	64ec <boot_write_trailer+0x52>
    erased_val = flash_area_erased_val(fap);
    64b6:	4630      	mov	r0, r6
    64b8:	f7ff fcfb 	bl	5eb2 <flash_area_erased_val>
    memcpy(buf, inbuf, inlen);
    64bc:	462a      	mov	r2, r5
    erased_val = flash_area_erased_val(fap);
    64be:	4681      	mov	r9, r0
    memcpy(buf, inbuf, inlen);
    64c0:	4641      	mov	r1, r8
    64c2:	4668      	mov	r0, sp
    64c4:	f7ff fd58 	bl	5f78 <memcpy>
    memset(&buf[inlen], erased_val, align - inlen);
    64c8:	1b62      	subs	r2, r4, r5
    64ca:	4649      	mov	r1, r9
    64cc:	eb0d 0005 	add.w	r0, sp, r5
    64d0:	f7ff fd5d 	bl	5f8e <memset>
    rc = flash_area_write(fap, off, buf, align);
    64d4:	4623      	mov	r3, r4
    64d6:	466a      	mov	r2, sp
    64d8:	4639      	mov	r1, r7
    64da:	4630      	mov	r0, r6
    64dc:	f7ff fcb7 	bl	5e4e <flash_area_write>
    if (rc != 0) {
    64e0:	3800      	subs	r0, #0
    64e2:	bf18      	it	ne
    64e4:	2001      	movne	r0, #1
}
    64e6:	b003      	add	sp, #12
    64e8:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        return -1;
    64ec:	f04f 30ff 	mov.w	r0, #4294967295
    64f0:	e7f9      	b.n	64e6 <boot_write_trailer+0x4c>

000064f2 <boot_write_trailer_flag>:
{
    64f2:	b507      	push	{r0, r1, r2, lr}
    return boot_write_trailer(fap, off, buf, 1);
    64f4:	2301      	movs	r3, #1
    const uint8_t buf[1] = { flag_val };
    64f6:	f88d 2004 	strb.w	r2, [sp, #4]
    return boot_write_trailer(fap, off, buf, 1);
    64fa:	aa01      	add	r2, sp, #4
    64fc:	f7ff ffcd 	bl	649a <boot_write_trailer>
}
    6500:	b003      	add	sp, #12
    6502:	f85d fb04 	ldr.w	pc, [sp], #4

00006506 <boot_write_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6506:	6881      	ldr	r1, [r0, #8]
    6508:	3918      	subs	r1, #24
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    650a:	2201      	movs	r2, #1
    650c:	f021 0107 	bic.w	r1, r1, #7
    6510:	f7ff bfef 	b.w	64f2 <boot_write_trailer_flag>

00006514 <boot_read_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6514:	6882      	ldr	r2, [r0, #8]
    6516:	3a18      	subs	r2, #24
    return boot_read_flag(fap, image_ok, boot_image_ok_off(fap));
    6518:	f022 0207 	bic.w	r2, r2, #7
    651c:	f7ff bfa1 	b.w	6462 <boot_read_flag>

00006520 <boot_read_swap_state_by_id>:
{
    6520:	b513      	push	{r0, r1, r4, lr}
    6522:	460c      	mov	r4, r1
    rc = flash_area_open(flash_area_id, &fap);
    6524:	b2c0      	uxtb	r0, r0
    6526:	a901      	add	r1, sp, #4
    6528:	f7fa fce6 	bl	ef8 <flash_area_open>
    if (rc != 0) {
    652c:	b950      	cbnz	r0, 6544 <boot_read_swap_state_by_id+0x24>
    rc = boot_read_swap_state(fap, state);
    652e:	4621      	mov	r1, r4
    6530:	9801      	ldr	r0, [sp, #4]
    6532:	f7fc f95f 	bl	27f4 <boot_read_swap_state>
    6536:	4604      	mov	r4, r0
    flash_area_close(fap);
    6538:	9801      	ldr	r0, [sp, #4]
    653a:	f7ff fc72 	bl	5e22 <flash_area_close>
}
    653e:	4620      	mov	r0, r4
    6540:	b002      	add	sp, #8
    6542:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    6544:	2401      	movs	r4, #1
    6546:	e7fa      	b.n	653e <boot_read_swap_state_by_id+0x1e>

00006548 <boot_write_swap_info>:
{
    6548:	b513      	push	{r0, r1, r4, lr}
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    654a:	ea41 1102 	orr.w	r1, r1, r2, lsl #4
{
    654e:	4604      	mov	r4, r0
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    6550:	f88d 1007 	strb.w	r1, [sp, #7]
    off = boot_swap_info_off(fap);
    6554:	f7ff ff5e 	bl	6414 <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    6558:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    655a:	4601      	mov	r1, r0
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    655c:	f10d 0207 	add.w	r2, sp, #7
    6560:	4620      	mov	r0, r4
    6562:	f7ff ff9a 	bl	649a <boot_write_trailer>
}
    6566:	b002      	add	sp, #8
    6568:	bd10      	pop	{r4, pc}

0000656a <nrfx_isr>:
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    656a:	4700      	bx	r0

0000656c <nrfx_busy_wait>:
    656c:	f000 b8fb 	b.w	6766 <z_impl_k_busy_wait>

00006570 <nrfx_clock_enable>:
{
    6570:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    6572:	2000      	movs	r0, #0
    6574:	f7fa fd50 	bl	1018 <arch_irq_is_enabled>
    6578:	b908      	cbnz	r0, 657e <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    657a:	f7fa fd2b 	bl	fd4 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    657e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6582:	2200      	movs	r2, #0
    6584:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    6588:	bd08      	pop	{r3, pc}

0000658a <nrfx_clock_start>:
{
    658a:	b508      	push	{r3, lr}
    switch (domain)
    658c:	b110      	cbz	r0, 6594 <nrfx_clock_start+0xa>
    658e:	2801      	cmp	r0, #1
    6590:	d02c      	beq.n	65ec <nrfx_clock_start+0x62>
}
    6592:	bd08      	pop	{r3, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    6594:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    6598:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    659c:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    65a0:	03c8      	lsls	r0, r1, #15
    65a2:	d40b      	bmi.n	65bc <nrfx_clock_start+0x32>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    65a4:	f8d2 3414 	ldr.w	r3, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    65a8:	07d9      	lsls	r1, r3, #31
    65aa:	d50f      	bpl.n	65cc <nrfx_clock_start+0x42>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    65ac:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    65b0:	079b      	lsls	r3, r3, #30
    65b2:	d408      	bmi.n	65c6 <nrfx_clock_start+0x3c>
    p_reg->INTENSET = mask;
    65b4:	2302      	movs	r3, #2
    65b6:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    65ba:	e7ea      	b.n	6592 <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    65bc:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    65c0:	2b01      	cmp	r3, #1
    65c2:	d004      	beq.n	65ce <nrfx_clock_start+0x44>
    65c4:	b113      	cbz	r3, 65cc <nrfx_clock_start+0x42>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    65c6:	2000      	movs	r0, #0
    65c8:	f7fc fb02 	bl	2bd0 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    65cc:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    65ce:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    65d2:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    65d6:	2300      	movs	r3, #0
    65d8:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    65dc:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    65e0:	2302      	movs	r3, #2
    65e2:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    65e6:	2301      	movs	r3, #1
    65e8:	6093      	str	r3, [r2, #8]
}
    65ea:	e7d2      	b.n	6592 <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    65ec:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    65f0:	2200      	movs	r2, #0
    65f2:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    65f6:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    65fa:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    65fe:	6018      	str	r0, [r3, #0]
}
    6600:	e7c7      	b.n	6592 <nrfx_clock_start+0x8>

00006602 <nrfx_clock_stop>:
    clock_stop(domain);
    6602:	f7fc bae5 	b.w	2bd0 <clock_stop>

00006606 <nrf_gpio_reconfigure>:
{
    6606:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    6608:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    660a:	a801      	add	r0, sp, #4
{
    660c:	e9dd 4708 	ldrd	r4, r7, [sp, #32]
    6610:	4616      	mov	r6, r2
    6612:	461d      	mov	r5, r3
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6614:	f7fc fb84 	bl	2d20 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6618:	9b01      	ldr	r3, [sp, #4]
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    661a:	f1b6 0c00 	subs.w	ip, r6, #0
    661e:	bf18      	it	ne
    6620:	f04f 0c01 	movne.w	ip, #1
    6624:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6628:	1e0b      	subs	r3, r1, #0
    662a:	bf18      	it	ne
    662c:	2301      	movne	r3, #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    662e:	2d00      	cmp	r5, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6630:	ea43 034c 	orr.w	r3, r3, ip, lsl #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6634:	bf14      	ite	ne
    6636:	f04f 0c0c 	movne.w	ip, #12
    663a:	f04f 0c00 	moveq.w	ip, #0
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    663e:	2c00      	cmp	r4, #0
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    6640:	ea43 030c 	orr.w	r3, r3, ip
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    6644:	bf14      	ite	ne
    6646:	f44f 6ce0 	movne.w	ip, #1792	; 0x700
    664a:	f04f 0c00 	moveq.w	ip, #0
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    664e:	2f00      	cmp	r7, #0
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6650:	ea43 030c 	orr.w	r3, r3, ip
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6654:	f8d0 2700 	ldr.w	r2, [r0, #1792]	; 0x700
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    6658:	bf14      	ite	ne
    665a:	f44f 3c40 	movne.w	ip, #196608	; 0x30000
    665e:	f04f 0c00 	moveq.w	ip, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6662:	ea43 030c 	orr.w	r3, r3, ip
    cnf &= ~to_update;
    6666:	ea22 0303 	bic.w	r3, r2, r3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    666a:	b101      	cbz	r1, 666e <nrf_gpio_reconfigure+0x68>
    666c:	7809      	ldrb	r1, [r1, #0]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    666e:	b10e      	cbz	r6, 6674 <nrf_gpio_reconfigure+0x6e>
    6670:	7836      	ldrb	r6, [r6, #0]
    6672:	0076      	lsls	r6, r6, #1
    6674:	4319      	orrs	r1, r3
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    6676:	b10d      	cbz	r5, 667c <nrf_gpio_reconfigure+0x76>
    6678:	782d      	ldrb	r5, [r5, #0]
    667a:	00ad      	lsls	r5, r5, #2
    667c:	4331      	orrs	r1, r6
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    667e:	b10c      	cbz	r4, 6684 <nrf_gpio_reconfigure+0x7e>
    6680:	7824      	ldrb	r4, [r4, #0]
    6682:	0224      	lsls	r4, r4, #8
    6684:	4329      	orrs	r1, r5
           ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
    6686:	b10f      	cbz	r7, 668c <nrf_gpio_reconfigure+0x86>
    6688:	783f      	ldrb	r7, [r7, #0]
    668a:	043f      	lsls	r7, r7, #16
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    668c:	430c      	orrs	r4, r1
    668e:	433c      	orrs	r4, r7
    reg->PIN_CNF[pin_number] = cnf;
    6690:	f8c0 4700 	str.w	r4, [r0, #1792]	; 0x700
}
    6694:	b003      	add	sp, #12
    6696:	bdf0      	pop	{r4, r5, r6, r7, pc}

00006698 <nrf_gpio_cfg_sense_set>:
{
    6698:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    669a:	f10d 030f 	add.w	r3, sp, #15
    669e:	9301      	str	r3, [sp, #4]
    66a0:	2300      	movs	r3, #0
{
    66a2:	f88d 100f 	strb.w	r1, [sp, #15]
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    66a6:	9300      	str	r3, [sp, #0]
    66a8:	461a      	mov	r2, r3
    66aa:	4619      	mov	r1, r3
    66ac:	f7ff ffab 	bl	6606 <nrf_gpio_reconfigure>
}
    66b0:	b005      	add	sp, #20
    66b2:	f85d fb04 	ldr.w	pc, [sp], #4

000066b6 <nrfx_nvmc_flash_size_get>:
    return p_reg->CODEPAGESIZE;
    66b6:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    66ba:	691a      	ldr	r2, [r3, #16]
    return p_reg->CODESIZE;
    66bc:	6958      	ldr	r0, [r3, #20]
}

uint32_t nrfx_nvmc_flash_size_get(void)
{
    return flash_total_size_get();
}
    66be:	4350      	muls	r0, r2
    66c0:	4770      	bx	lr

000066c2 <nrfx_nvmc_flash_page_size_get>:
    return p_reg->CODEPAGESIZE;
    66c2:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    66c6:	6918      	ldr	r0, [r3, #16]

uint32_t nrfx_nvmc_flash_page_size_get(void)
{
    return flash_page_size_get();
}
    66c8:	4770      	bx	lr

000066ca <nrfx_nvmc_flash_page_count_get>:
    return p_reg->CODESIZE;
    66ca:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    66ce:	6958      	ldr	r0, [r3, #20]

uint32_t nrfx_nvmc_flash_page_count_get(void)
{
    return flash_page_count_get();
}
    66d0:	4770      	bx	lr

000066d2 <nrf_gpio_cfg_default>:
{
    66d2:	b507      	push	{r0, r1, r2, lr}
    66d4:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    66d6:	a801      	add	r0, sp, #4
    66d8:	f7fc fec6 	bl	3468 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    66dc:	9b01      	ldr	r3, [sp, #4]
    66de:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    66e2:	2202      	movs	r2, #2
    66e4:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
}
    66e8:	b003      	add	sp, #12
    66ea:	f85d fb04 	ldr.w	pc, [sp], #4

000066ee <nrfx_qspi_write>:
    return qspi_xfer((void *)p_tx_buffer, tx_buffer_length, dst_address, NRFX_QSPI_STATE_WRITE);
    66ee:	2302      	movs	r3, #2
    66f0:	f7fc bec8 	b.w	3484 <qspi_xfer>

000066f4 <nrfx_qspi_read>:
    return qspi_xfer((void *)p_rx_buffer, rx_buffer_length, src_address, NRFX_QSPI_STATE_READ);
    66f4:	2303      	movs	r3, #3
    66f6:	f7fc bec5 	b.w	3484 <qspi_xfer>

000066fa <nrfx_qspi_chip_erase>:
    return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0);
    66fa:	2100      	movs	r1, #0
    66fc:	2002      	movs	r0, #2
    66fe:	f7fd b94f 	b.w	39a0 <nrfx_qspi_erase>

00006702 <z_device_state_init>:

	while (dev < __device_end) {
		z_object_init(dev);
		++dev;
	}
}
    6702:	4770      	bx	lr

00006704 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    6704:	b140      	cbz	r0, 6718 <z_device_is_ready+0x14>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    6706:	68c3      	ldr	r3, [r0, #12]
    6708:	7858      	ldrb	r0, [r3, #1]
    670a:	f010 0001 	ands.w	r0, r0, #1
    670e:	bf1e      	ittt	ne
    6710:	7818      	ldrbne	r0, [r3, #0]
    6712:	fab0 f080 	clzne	r0, r0
    6716:	0940      	lsrne	r0, r0, #5
}
    6718:	4770      	bx	lr

0000671a <arch_system_halt>:
	__asm__ volatile(
    671a:	f04f 0220 	mov.w	r2, #32
    671e:	f3ef 8311 	mrs	r3, BASEPRI
    6722:	f382 8812 	msr	BASEPRI_MAX, r2
    6726:	f3bf 8f6f 	isb	sy
	/* TODO: What's the best way to totally halt the system if SMP
	 * is enabled?
	 */

	(void)arch_irq_lock();
	for (;;) {
    672a:	e7fe      	b.n	672a <arch_system_halt+0x10>

0000672c <k_sys_fatal_error_handler>:
/* LCOV_EXCL_STOP */

/* LCOV_EXCL_START */
__weak void k_sys_fatal_error_handler(unsigned int reason,
				      const z_arch_esf_t *esf)
{
    672c:	b508      	push	{r3, lr}
	ARG_UNUSED(esf);

	LOG_PANIC();
	LOG_ERR("Halting system");
	arch_system_halt(reason);
    672e:	f7ff fff4 	bl	671a <arch_system_halt>

00006732 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    6732:	b510      	push	{r4, lr}
    6734:	f04f 0320 	mov.w	r3, #32
    6738:	f3ef 8411 	mrs	r4, BASEPRI
    673c:	f383 8812 	msr	BASEPRI_MAX, r3
    6740:	f3bf 8f6f 	isb	sy

#ifndef CONFIG_XTENSA
	coredump(reason, esf, thread);
#endif

	k_sys_fatal_error_handler(reason, esf);
    6744:	f7ff fff2 	bl	672c <k_sys_fatal_error_handler>
	__asm__ volatile(
    6748:	f384 8811 	msr	BASEPRI, r4
    674c:	f3bf 8f6f 	isb	sy
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    6750:	bd10      	pop	{r4, pc}

00006752 <z_early_memset>:
	(void) memset(dst, c, n);
    6752:	f7ff bc1c 	b.w	5f8e <memset>

00006756 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    6756:	f7ff bc0f 	b.w	5f78 <memcpy>

0000675a <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    675a:	f3ef 8005 	mrs	r0, IPSR
}

bool k_is_in_isr(void)
{
	return arch_is_in_isr();
}
    675e:	3800      	subs	r0, #0
    6760:	bf18      	it	ne
    6762:	2001      	movne	r0, #1
    6764:	4770      	bx	lr

00006766 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    6766:	b108      	cbz	r0, 676c <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    6768:	f7fa bf4e 	b.w	1608 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    676c:	4770      	bx	lr

0000676e <boot_banner>:
#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */

#if CONFIG_BOOT_BANNER
	printk("*** Booting Zephyr OS build " BANNER_VERSION BANNER_POSTFIX " ***\n");
#endif /* CONFIG_BOOT_BANNER */
}
    676e:	4770      	bx	lr

00006770 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    6770:	4770      	bx	lr

00006772 <nrf_cc310_bl_ecdsa_verify_secp256r1>:
    6772:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6776:	9f06      	ldr	r7, [sp, #24]
    6778:	4604      	mov	r4, r0
    677a:	4615      	mov	r5, r2
    677c:	461e      	mov	r6, r3
    677e:	f7fd fc69 	bl	4054 <nrf_cc310_bl_ecdsa_verify_init_secp256r1>
    6782:	b938      	cbnz	r0, 6794 <nrf_cc310_bl_ecdsa_verify_secp256r1+0x22>
    6784:	463b      	mov	r3, r7
    6786:	4632      	mov	r2, r6
    6788:	4629      	mov	r1, r5
    678a:	4620      	mov	r0, r4
    678c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    6790:	f7fd bc86 	b.w	40a0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1>
    6794:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006798 <PkaInitAndMutexLock>:
    6798:	460a      	mov	r2, r1
    679a:	2100      	movs	r1, #0
    679c:	f7fd bf08 	b.w	45b0 <PkaInitPka>

000067a0 <SaSi_PalMemCopy>:
    67a0:	f7ff bbea 	b.w	5f78 <memcpy>

000067a4 <SaSi_PalMemSet>:
    67a4:	f7ff bbf3 	b.w	5f8e <memset>

000067a8 <SaSi_PalMemSetZero>:
    67a8:	460a      	mov	r2, r1
    67aa:	2100      	movs	r1, #0
    67ac:	f7ff bbef 	b.w	5f8e <memset>

000067b0 <CRYS_COMMON_ReverseMemcpy32>:
    67b0:	eb01 0282 	add.w	r2, r1, r2, lsl #2
    67b4:	3804      	subs	r0, #4
    67b6:	428a      	cmp	r2, r1
    67b8:	d101      	bne.n	67be <CRYS_COMMON_ReverseMemcpy32+0xe>
    67ba:	2000      	movs	r0, #0
    67bc:	4770      	bx	lr
    67be:	f852 3d04 	ldr.w	r3, [r2, #-4]!
    67c2:	ba1b      	rev	r3, r3
    67c4:	f840 3f04 	str.w	r3, [r0, #4]!
    67c8:	e7f5      	b.n	67b6 <CRYS_COMMON_ReverseMemcpy32+0x6>
	...
