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macros_armv4.h
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27 
28 #ifndef SILK_MACROS_ARMv4_H
29 #define SILK_MACROS_ARMv4_H
30 
31 /* This macro only avoids the undefined behaviour from a left shift of
32  a negative value. It should only be used in macros that can't include
33  SigProc_FIX.h. In other cases, use silk_LSHIFT32(). */
34 #define SAFE_SHL(a,b) ((opus_int32)((opus_uint32)(a) << (b)))
35 
36 /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */
37 #undef silk_SMULWB
38 static OPUS_INLINE opus_int32 silk_SMULWB_armv4(opus_int32 a, opus_int16 b)
39 {
40  unsigned rd_lo;
41  int rd_hi;
42 
43 #if defined( __CC_ARM )
44  __asm{ SMULL rd_lo, rd_hi, a, (SAFE_SHL(b,16)) }
45 #elif defined( __ICCARM__ )
46  __asm(
47  "smull %0, %1, %2, %3\n\t"
48  : "=&r"(rd_lo), "=&r"(rd_hi)
49  : "r"(a), "r"(SAFE_SHL(b,16))
50  );
51  (void)(rd_lo);
52 #else
53  __asm__(
54  "#silk_SMULWB\n\t"
55  "smull %0, %1, %2, %3\n\t"
56  : "=&r"(rd_lo), "=&r"(rd_hi)
57  : "%r"(a), "r"(SAFE_SHL(b,16))
58  );
59 #endif
60 
61  return rd_hi;
62 }
63 #define silk_SMULWB(a, b) (silk_SMULWB_armv4(a, b))
64 
65 /* a32 + (b32 * (opus_int32)((opus_int16)(c32))) >> 16 output have to be 32bit int */
66 #undef silk_SMLAWB
67 #define silk_SMLAWB(a, b, c) ((a) + silk_SMULWB(b, c))
68 
69 /* (a32 * (b32 >> 16)) >> 16 */
70 #undef silk_SMULWT
71 static OPUS_INLINE opus_int32 silk_SMULWT_armv4(opus_int32 a, opus_int32 b)
72 {
73  unsigned rd_lo;
74  int rd_hi;
75 
76 #if defined( __CC_ARM )
77  __asm{ SMULL rd_lo, rd_hi, a, (b&~0xFFFF) }
78 #elif defined( __ICCARM__ )
79  __asm(
80  "smull %0, %1, %2, %3\n\t"
81  : "=&r"(rd_lo), "=&r"(rd_hi)
82  : "r"(a), "r"(b&~0xFFFF)
83  );
84  (void)(rd_lo);
85 #else
86  __asm__(
87  "#silk_SMULWT\n\t"
88  "smull %0, %1, %2, %3\n\t"
89  : "=&r"(rd_lo), "=&r"(rd_hi)
90  : "%r"(a), "r"(b&~0xFFFF)
91  );
92 #endif
93 
94  return rd_hi;
95 }
96 #define silk_SMULWT(a, b) (silk_SMULWT_armv4(a, b))
97 
98 /* a32 + (b32 * (c32 >> 16)) >> 16 */
99 #undef silk_SMLAWT
100 #define silk_SMLAWT(a, b, c) ((a) + silk_SMULWT(b, c))
101 
102 /* (a32 * b32) >> 16 */
103 #undef silk_SMULWW
104 static OPUS_INLINE opus_int32 silk_SMULWW_armv4(opus_int32 a, opus_int32 b)
105 {
106  unsigned rd_lo;
107  int rd_hi;
108 
109 #if defined( __CC_ARM )
110  __asm{ SMULL rd_lo, rd_hi, a, b }
111 #elif defined( __ICCARM__ )
112  __asm(
113  "smull %0, %1, %2, %3\n\t"
114  : "=&r"(rd_lo), "=&r"(rd_hi)
115  : "r"(a), "r"(b)
116  );
117 #else
118  __asm__(
119  "#silk_SMULWW\n\t"
120  "smull %0, %1, %2, %3\n\t"
121  : "=&r"(rd_lo), "=&r"(rd_hi)
122  : "%r"(a), "r"(b)
123  );
124 #endif
125  return SAFE_SHL(rd_hi,16)+(rd_lo>>16);
126 }
127 #define silk_SMULWW(a, b) (silk_SMULWW_armv4(a, b))
128 
129 #undef silk_SMLAWW
130 static OPUS_INLINE opus_int32 silk_SMLAWW_armv4(opus_int32 a, opus_int32 b,
131  opus_int32 c)
132 {
133  unsigned rd_lo;
134  int rd_hi;
135 
136 #if defined( __CC_ARM )
137  __asm{ SMULL rd_lo, rd_hi, b, c }
138 #elif defined( __ICCARM__ )
139  __asm(
140  "smull %0, %1, %2, %3\n\t"
141  : "=&r"(rd_lo), "=&r"(rd_hi)
142  : "r"(b), "r"(c)
143  );
144 #else
145  __asm__(
146  "#silk_SMLAWW\n\t"
147  "smull %0, %1, %2, %3\n\t"
148  : "=&r"(rd_lo), "=&r"(rd_hi)
149  : "%r"(b), "r"(c)
150  );
151 #endif
152 
153  return a+SAFE_SHL(rd_hi,16)+(rd_lo>>16);
154 }
155 #define silk_SMLAWW(a, b, c) (silk_SMLAWW_armv4(a, b, c))
156 
157 #undef SAFE_SHL
158 
159 #endif /* SILK_MACROS_ARMv4_H */