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nrf_nvic.h
1 /*
2  * Copyright (c) 2016 - 2017, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without modification,
6  * are permitted provided that the following conditions are met:
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8  * 1. Redistributions of source code must retain the above copyright notice, this
9  * list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form, except as embedded into a Nordic
12  * Semiconductor ASA integrated circuit in a product or a software update for
13  * such product, must reproduce the above copyright notice, this list of
14  * conditions and the following disclaimer in the documentation and/or other
15  * materials provided with the distribution.
16  *
17  * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * 4. This software, with or without modification, must only be used with a
22  * Nordic Semiconductor ASA integrated circuit.
23  *
24  * 5. Any software provided in binary form under this license must not be reverse
25  * engineered, decompiled, modified and/or disassembled.
26  *
27  * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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36  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
55 #ifndef NRF_NVIC_H__
56 #define NRF_NVIC_H__
57 
58 #include <stdint.h>
59 #include "nrf.h"
60 
61 #include "nrf_error_soc.h"
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
73 #define __NRF_NVIC_NVMC_IRQn (30)
75 #define __NRF_NVIC_ISER_COUNT (2)
78 #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
79  (1U << POWER_CLOCK_IRQn) \
80  | (1U << RADIO_IRQn) \
81  | (1U << RTC0_IRQn) \
82  | (1U << TIMER0_IRQn) \
83  | (1U << RNG_IRQn) \
84  | (1U << ECB_IRQn) \
85  | (1U << CCM_AAR_IRQn) \
86  | (1U << TEMP_IRQn) \
87  | (1U << __NRF_NVIC_NVMC_IRQn) \
88  | (1U << (uint32_t)SWI5_EGU5_IRQn) \
89  ))
90 
92 #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0)
93 
95 #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
96 
98 #define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1)
99 
108 typedef struct
109 {
110  uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT];
111  uint32_t volatile __cr_flag;
113 
117 
127 __STATIC_INLINE int __sd_nvic_irq_disable(void);
128 
131 __STATIC_INLINE void __sd_nvic_irq_enable(void);
132 
138 __STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn);
139 
145 __STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority);
146 
163 __STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn);
164 
175 __STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn);
176 
188 __STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq);
189 
200 __STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn);
201 
212 __STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn);
213 
227 __STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority);
228 
240 __STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority);
241 
247 __STATIC_INLINE uint32_t sd_nvic_SystemReset(void);
248 
260 __STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region);
261 
271 __STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region);
272 
275 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
276 
277 __STATIC_INLINE int __sd_nvic_irq_disable(void)
278 {
279  int pm = __get_PRIMASK();
280  __disable_irq();
281  return pm;
282 }
283 
284 __STATIC_INLINE void __sd_nvic_irq_enable(void)
285 {
286  __enable_irq();
287 }
288 
289 __STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn)
290 {
291  if (IRQn < 32)
292  {
293  return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0;
294  }
295  else if (IRQn < 64)
296  {
297  return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0;
298  }
299  else
300  {
301  return 1;
302  }
303 }
304 
305 __STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority)
306 {
307  if(priority >= (1 << __NVIC_PRIO_BITS))
308  {
309  return 0;
310  }
311  if( priority == 0
312  || priority == 1
313  || priority == 4
314  )
315  {
316  return 0;
317  }
318  return 1;
319 }
320 
321 
322 __STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn)
323 {
324  if (!__sd_nvic_app_accessible_irq(IRQn))
325  {
327  }
328  if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn)))
329  {
331  }
332 
333  if (nrf_nvic_state.__cr_flag)
334  {
335  nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));
336  }
337  else
338  {
339  NVIC_EnableIRQ(IRQn);
340  }
341  return NRF_SUCCESS;
342 }
343 
344 __STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn)
345 {
346  if (!__sd_nvic_app_accessible_irq(IRQn))
347  {
349  }
350 
351  if (nrf_nvic_state.__cr_flag)
352  {
353  nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F));
354  }
355  else
356  {
357  NVIC_DisableIRQ(IRQn);
358  }
359 
360  return NRF_SUCCESS;
361 }
362 
363 __STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)
364 {
366  {
367  *p_pending_irq = NVIC_GetPendingIRQ(IRQn);
368  return NRF_SUCCESS;
369  }
370  else
371  {
373  }
374 }
375 
376 __STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn)
377 {
379  {
380  NVIC_SetPendingIRQ(IRQn);
381  return NRF_SUCCESS;
382  }
383  else
384  {
386  }
387 }
388 
389 __STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)
390 {
392  {
393  NVIC_ClearPendingIRQ(IRQn);
394  return NRF_SUCCESS;
395  }
396  else
397  {
399  }
400 }
401 
402 __STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority)
403 {
404  if (!__sd_nvic_app_accessible_irq(IRQn))
405  {
407  }
408 
410  {
412  }
413 
414  NVIC_SetPriority(IRQn, (uint32_t)priority);
415  return NRF_SUCCESS;
416 }
417 
418 __STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority)
419 {
421  {
422  *p_priority = (NVIC_GetPriority(IRQn) & 0xFF);
423  return NRF_SUCCESS;
424  }
425  else
426  {
428  }
429 }
430 
431 __STATIC_INLINE uint32_t sd_nvic_SystemReset(void)
432 {
433  NVIC_SystemReset();
435 }
436 
437 __STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)
438 {
439  int was_masked = __sd_nvic_irq_disable();
440  if (!nrf_nvic_state.__cr_flag)
441  {
442  nrf_nvic_state.__cr_flag = 1;
443  nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
444  NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
445  nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 );
446  NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1;
447  *p_is_nested_critical_region = 0;
448  }
449  else
450  {
451  *p_is_nested_critical_region = 1;
452  }
453  if (!was_masked)
454  {
456  }
457  return NRF_SUCCESS;
458 }
459 
460 __STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)
461 {
462  if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0))
463  {
464  int was_masked = __sd_nvic_irq_disable();
465  NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
466  NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
467  nrf_nvic_state.__cr_flag = 0;
468  if (!was_masked)
469  {
471  }
472  }
473 
474  return NRF_SUCCESS;
475 }
476 
477 #endif /* SUPPRESS_INLINE_IMPLEMENTATION */
478 
479 #ifdef __cplusplus
480 }
481 #endif
482 
483 #endif // NRF_NVIC_H__
484