
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
	return cb(str, strl, ctx);
}

int cbvprintf_package(void *packaged, size_t len, uint32_t flags,
		      const char *fmt, va_list ap)
{
   0:	00 59 00 20 7d 27 00 00 e7 8d 00 00 51 27 00 00     .Y. }'......Q'..
	bool rws_pos_en = !!(flags & CBPRINTF_PACKAGE_ADD_RW_STR_POS);
	/* Get number of first read only strings present in the string.
	 * There is always at least 1 (fmt) but flags can indicate more, e.g
	 * fixed prefix appended to all strings.
	 */
	int fros_cnt = 1 + Z_CBPRINTF_PACKAGE_FIRST_RO_STR_CNT_GET(flags);
  10:	51 27 00 00 51 27 00 00 51 27 00 00 00 00 00 00     Q'..Q'..Q'......
	...

	/*
	 * Otherwise we must ensure we can store at least
	 * the pointer to the format string itself.
	 */
	if (buf0 != NULL && BUF_OFFSET + sizeof(char *) > len) {
  2c:	91 21 00 00 51 27 00 00 00 00 00 00 01 21 00 00     .!..Q'.......!..
		buf += len % CBPRINTF_PACKAGE_ALIGNMENT;
  3c:	51 27 00 00                                         Q'..

00000040 <_irq_vector_table>:
		len = CBPRINTF_PACKAGE_ALIGNMENT - (len % CBPRINTF_PACKAGE_ALIGNMENT);
  40:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
	int arg_idx	      = -1; /* Argument index. Preincremented thus starting from -1.*/
  50:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..

		/* copy va_list data over to our buffer */
		if (is_str_arg) {
			s = va_arg(ap, char *);
process_string:
			if (buf0 != NULL) {
  60:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
#else
	#define RO_START 0
	#define RO_END 0
#endif

	return (((const char *)addr >= (const char *)RO_START) &&
  70:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
			bool do_ro = !!(flags & CBPRINTF_PACKAGE_ADD_RO_STR_POS);

			if (is_ro && !do_ro) {
				/* nothing to do */
			} else {
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
  80:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
					__ASSERT(false, "String with too many arguments");
					return -EINVAL;
				}

				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
  90:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
				if (buf0 != NULL) {
					/*
					 * Remember string pointer location.
					 * We will append non-ro strings later.
					 */
					str_ptr_pos[s_idx] = s_ptr_idx;
  a0:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
					if (is_ro) {
						/* flag read-only string. */
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
						s_ro_cnt++;
					} else {
						s_rw_cnt++;
  b0:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
			switch (*fmt) {
  c0:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
  d0:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
  e0:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..
  f0:	01 23 00 00 01 23 00 00 01 23 00 00 01 23 00 00     .#...#...#...#..

Disassembly of section text:

00000100 <__aeabi_uldivmod>:
     100:	b953      	cbnz	r3, 118 <__aeabi_uldivmod+0x18>
     102:	b94a      	cbnz	r2, 118 <__aeabi_uldivmod+0x18>
     104:	2900      	cmp	r1, #0
     106:	bf08      	it	eq
     108:	2800      	cmpeq	r0, #0
     10a:	bf1c      	itt	ne
     10c:	f04f 31ff 	movne.w	r1, #4294967295
     110:	f04f 30ff 	movne.w	r0, #4294967295
     114:	f000 b80c 	b.w	130 <__aeabi_idiv0>
     118:	f1ad 0c08 	sub.w	ip, sp, #8
     11c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
				align = VA_STACK_ALIGN(void *);
     120:	f000 f808 	bl	134 <__udivmoddi4>
			switch (*fmt) {
     124:	f8dd e004 	ldr.w	lr, [sp, #4]
     128:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     12c:	b004      	add	sp, #16
     12e:	4770      	bx	lr

00000130 <__aeabi_idiv0>:
     130:	4770      	bx	lr
     132:	bf00      	nop

00000134 <__udivmoddi4>:
     134:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     138:	4686      	mov	lr, r0
     13a:	468c      	mov	ip, r1
     13c:	4608      	mov	r0, r1
     13e:	9e08      	ldr	r6, [sp, #32]
     140:	4615      	mov	r5, r2
     142:	4674      	mov	r4, lr
		buf = (void *) ROUND_UP(buf, align);
     144:	4619      	mov	r1, r3
     146:	2b00      	cmp	r3, #0
     148:	f040 80c2 	bne.w	2d0 <__data_size+0xa4>
     14c:	4285      	cmp	r5, r0
     14e:	fab2 f282 	clz	r2, r2
		if (buf0 != NULL && BUF_OFFSET + size > len) {
     152:	d945      	bls.n	1e0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x73>
     154:	b14a      	cbz	r2, 16a <CONFIG_IDLE_STACK_SIZE+0x2a>
     156:	f1c2 0320 	rsb	r3, r2, #32
     15a:	fa00 fc02 	lsl.w	ip, r0, r2
     15e:	fa2e f303 	lsr.w	r3, lr, r3
		if (is_str_arg) {
     162:	4095      	lsls	r5, r2
				s_idx++;
			}
			buf += sizeof(char *);

			is_str_arg = false;
		} else if (size == sizeof(int)) {
     164:	ea43 0c0c 	orr.w	ip, r3, ip
			int v = va_arg(ap, int);
     168:	4094      	lsls	r4, r2
     16a:	ea4f 4e15 	mov.w	lr, r5, lsr #16

			if (buf0 != NULL) {
				*(int *)buf = v;
			}
			buf += sizeof(int);
     16e:	b2a8      	uxth	r0, r5
     170:	fbbc f8fe 	udiv	r8, ip, lr
				arg_idx--;
     174:	0c23      	lsrs	r3, r4, #16
     176:	fb0e cc18 	mls	ip, lr, r8, ip
				parsing = false;
     17a:	fb08 f900 	mul.w	r9, r8, r0
				continue;
     17e:	ea43 430c 	orr.w	r3, r3, ip, lsl #16
				if (fmt[-1] == 'l') {
     182:	4599      	cmp	r9, r3
     184:	d928      	bls.n	1d8 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x6b>
     186:	18eb      	adds	r3, r5, r3
					if (fmt[-2] == 'l') {
     188:	f108 37ff 	add.w	r7, r8, #4294967295
     18c:	d204      	bcs.n	198 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x2b>
     18e:	4599      	cmp	r9, r3
				parsing = false;
     190:	d902      	bls.n	198 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x2b>
					if (fmt[-2] == 'l') {
     192:	f1a8 0702 	sub.w	r7, r8, #2
						align = VA_STACK_ALIGN(long long);
     196:	442b      	add	r3, r5
				size = sizeof(void *);
     198:	eba3 0309 	sub.w	r3, r3, r9
					v.ld = va_arg(ap, long double);
     19c:	b2a4      	uxth	r4, r4
     19e:	fbb3 fcfe 	udiv	ip, r3, lr
     1a2:	fb0e 331c 	mls	r3, lr, ip, r3
     1a6:	fb0c f000 	mul.w	r0, ip, r0
				buf = (void *) ROUND_UP(buf, align);
     1aa:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
				if (buf0 != NULL) {
     1ae:	42a0      	cmp	r0, r4
					if (BUF_OFFSET + size > len) {
     1b0:	d914      	bls.n	1dc <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x6f>
     1b2:	192c      	adds	r4, r5, r4
     1b4:	f10c 33ff 	add.w	r3, ip, #4294967295
     1b8:	d204      	bcs.n	1c4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x57>
						*(long double *)buf = v.ld;
     1ba:	42a0      	cmp	r0, r4
     1bc:	d902      	bls.n	1c4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x57>
				buf += size;
     1be:	f1ac 0302 	sub.w	r3, ip, #2
				parsing = false;
     1c2:	442c      	add	r4, r5
			switch (*fmt) {
     1c4:	1a24      	subs	r4, r4, r0
     1c6:	ea43 4007 	orr.w	r0, r3, r7, lsl #16
			if (*++fmt == '\0') {
     1ca:	b11e      	cbz	r6, 1d4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x67>
     1cc:	40d4      	lsrs	r4, r2
     1ce:	2300      	movs	r3, #0
     1d0:	6034      	str	r4, [r6, #0]
			if (!parsing) {
     1d2:	6073      	str	r3, [r6, #4]
     1d4:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1d8:	4647      	mov	r7, r8
				if (*fmt == '%') {
     1da:	e7dd      	b.n	198 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x2b>
     1dc:	4663      	mov	r3, ip
					arg_idx++;
     1de:	e7f1      	b.n	1c4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x57>
     1e0:	bb92      	cbnz	r2, 248 <__data_size+0x1c>
     1e2:	1b43      	subs	r3, r0, r5
					parsing = true;
     1e4:	2101      	movs	r1, #1
     1e6:	ea4f 4e15 	mov.w	lr, r5, lsr #16
				align = VA_STACK_ALIGN(size_t);
     1ea:	b2af      	uxth	r7, r5
     1ec:	fbb3 fcfe 	udiv	ip, r3, lr
			switch (*fmt) {
     1f0:	0c20      	lsrs	r0, r4, #16
     1f2:	fb0e 331c 	mls	r3, lr, ip, r3
				parsing = false;
     1f6:	fb0c f807 	mul.w	r8, ip, r7

			if (buf0 != NULL) {
				*(long *)buf = v;
			}
			buf += sizeof(long);
		} else if (size == sizeof(long long)) {
     1fa:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
					return -EINVAL;
     1fe:	4598      	cmp	r8, r3
     200:	d962      	bls.n	2c8 <__data_size+0x9c>
			long long v = va_arg(ap, long long);
     202:	18eb      	adds	r3, r5, r3
     204:	f10c 30ff 	add.w	r0, ip, #4294967295
     208:	d204      	bcs.n	214 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x14>
     20a:	4598      	cmp	r8, r3
     20c:	d902      	bls.n	214 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x14>

			if (buf0 != NULL) {
				if (Z_CBPRINTF_VA_STACK_LL_DBL_MEMCPY) {
					memcpy(buf, &v, sizeof(long long));
				} else {
					*(long long *)buf = v;
     20e:	f1ac 0002 	sub.w	r0, ip, #2
				}
			}
			buf += sizeof(long long);
     212:	442b      	add	r3, r5
     214:	eba3 0308 	sub.w	r3, r3, r8
		if (is_str_arg) {
     218:	b2a4      	uxth	r4, r4
		} else if (size == sizeof(int)) {
     21a:	fbb3 fcfe 	udiv	ip, r3, lr
			int v = va_arg(ap, int);
     21e:	fb0e 331c 	mls	r3, lr, ip, r3
			if (buf0 != NULL) {
     222:	fb0c f707 	mul.w	r7, ip, r7
		} else if (size == sizeof(long long)) {
     226:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
			long long v = va_arg(ap, long long);
     22a:	42a7      	cmp	r7, r4
     22c:	d94e      	bls.n	2cc <__data_size+0xa0>
     22e:	192c      	adds	r4, r5, r4
     230:	f10c 33ff 	add.w	r3, ip, #4294967295
			if (buf0 != NULL) {
     234:	d204      	bcs.n	240 <__data_size+0x14>
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     236:	42a7      	cmp	r7, r4
     238:	d902      	bls.n	240 <__data_size+0x14>
     23a:	f1ac 0302 	sub.w	r3, ip, #2
			s = va_arg(ap, char *);
     23e:	442c      	add	r4, r5
     240:	1be4      	subs	r4, r4, r7
     242:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
			if (is_ro && !do_ro) {
     246:	e7c0      	b.n	1ca <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x5d>
     248:	f1c2 0320 	rsb	r3, r2, #32
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     24c:	fa20 f103 	lsr.w	r1, r0, r3
     250:	4095      	lsls	r5, r2
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     252:	4090      	lsls	r0, r2
     254:	fa2e f303 	lsr.w	r3, lr, r3
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     258:	4303      	orrs	r3, r0
     25a:	ea4f 4e15 	mov.w	lr, r5, lsr #16
				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
     25e:	b2af      	uxth	r7, r5
				if (buf0 != NULL) {
     260:	fbb1 fcfe 	udiv	ip, r1, lr
					str_ptr_pos[s_idx] = s_ptr_idx;
     264:	fb0e 101c 	mls	r0, lr, ip, r1
     268:	0c19      	lsrs	r1, r3, #16
     26a:	fb0c f807 	mul.w	r8, ip, r7
     26e:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
					str_ptr_arg[s_idx] = arg_idx;
     272:	4588      	cmp	r8, r1
     274:	fa04 f402 	lsl.w	r4, r4, r2
					if (is_ro) {
     278:	d922      	bls.n	2c0 <__data_size+0x94>
     27a:	1869      	adds	r1, r5, r1
     27c:	f10c 30ff 	add.w	r0, ip, #4294967295
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
     280:	d204      	bcs.n	28c <__data_size+0x60>
     282:	4588      	cmp	r8, r1
     284:	d902      	bls.n	28c <__data_size+0x60>
						s_ro_cnt++;
     286:	f1ac 0002 	sub.w	r0, ip, #2
				s_idx++;
     28a:	4429      	add	r1, r5
					if (BUF_OFFSET + size > len) {
     28c:	eba1 0108 	sub.w	r1, r1, r8
			buf += sizeof(char *);
     290:	b29b      	uxth	r3, r3
					if (BUF_OFFSET + size > len) {
     292:	fbb1 fcfe 	udiv	ip, r1, lr
			switch (*fmt) {
     296:	fb0e 111c 	mls	r1, lr, ip, r1
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     29a:	fb0c f707 	mul.w	r7, ip, r7
     29e:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
				} else if (is_ro) {
     2a2:	429f      	cmp	r7, r3
     2a4:	d90e      	bls.n	2c4 <__data_size+0x98>
					len += 1;
     2a6:	18eb      	adds	r3, r5, r3
     2a8:	f10c 31ff 	add.w	r1, ip, #4294967295
					len += 2;
     2ac:	d204      	bcs.n	2b8 <__data_size+0x8c>
				} else if (rws_pos_en) {
     2ae:	429f      	cmp	r7, r3
     2b0:	d902      	bls.n	2b8 <__data_size+0x8c>
					len += strlen(s) + 1 + 1;
     2b2:	f1ac 0102 	sub.w	r1, ip, #2
     2b6:	442b      	add	r3, r5
     2b8:	1bdb      	subs	r3, r3, r7
     2ba:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     2be:	e792      	b.n	1e6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x79>
     2c0:	4660      	mov	r0, ip
     2c2:	e7e3      	b.n	28c <__data_size+0x60>
	 * We remember the size of the argument list as a multiple of
	 * sizeof(int) and limit it to a 8-bit field. That means 1020 bytes
	 * worth of va_list, or about 127 arguments on a 64-bit system
	 * (twice that on 32-bit systems). That ought to be good enough.
	 */
	if (BUF_OFFSET / sizeof(int) > 255) {
     2c4:	4661      	mov	r1, ip
     2c6:	e7f7      	b.n	2b8 <__data_size+0x8c>
     2c8:	4660      	mov	r0, ip
     2ca:	e7a3      	b.n	214 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x14>

	/*
	 * If all we wanted was to count required buffer size
	 * then we have it now.
	 */
	if (buf0 == NULL) {
     2cc:	4663      	mov	r3, ip
		return BUF_OFFSET + len - CBPRINTF_PACKAGE_ALIGNMENT;
     2ce:	e7b7      	b.n	240 <__data_size+0x14>
     2d0:	4283      	cmp	r3, r0
     2d2:	d906      	bls.n	2e2 <__data_size+0xb6>
     2d4:	b916      	cbnz	r6, 2dc <__data_size+0xb0>
     2d6:	2100      	movs	r1, #0
     2d8:	4608      	mov	r0, r1
     2da:	e77b      	b.n	1d4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x67>
     2dc:	e9c6 e000 	strd	lr, r0, [r6]
	*(char **)buf0 = NULL;

	/* Record end of argument list. */
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);

	if (rws_pos_en) {
     2e0:	e7f9      	b.n	2d6 <__data_size+0xaa>
	*(char **)buf0 = NULL;
     2e2:	fab3 f783 	clz	r7, r3
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);
     2e6:	b98f      	cbnz	r7, 30c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xc>
		/* Strings are appended, update location counter. */
		pkg_hdr->desc.str_cnt = 0;
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2e8:	4283      	cmp	r3, r0
     2ea:	d301      	bcc.n	2f0 <__data_size+0xc4>
	if (rws_pos_en) {
     2ec:	4572      	cmp	r2, lr
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2ee:	d808      	bhi.n	302 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x2>
		/* Strings are appended, update append counter. */
		pkg_hdr->desc.str_cnt = s_rw_cnt;
		pkg_hdr->desc.rw_str_cnt = 0;
	}

	pkg_hdr->desc.ro_str_cnt = s_ro_cnt;
     2f0:	ebbe 0402 	subs.w	r4, lr, r2
#ifdef CONFIG_CBPRINTF_PACKAGE_HEADER_STORE_CREATION_FLAGS
	pkg_hdr->desc.pkg_flags = flags;
#endif

	/* Store strings pointer locations of read only strings. */
	if (s_ro_cnt) {
     2f4:	eb60 0303 	sbc.w	r3, r0, r3
     2f8:	2001      	movs	r0, #1
     2fa:	469c      	mov	ip, r3
		for (i = 0; i < s_idx; i++) {
     2fc:	b91e      	cbnz	r6, 306 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6>
			}

			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;

			/* make sure it fits */
			if (BUF_OFFSET + 1 > len) {
     2fe:	2100      	movs	r1, #0
     300:	e768      	b.n	1d4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x67>
		for (i = 0; i < s_idx; i++) {
     302:	4638      	mov	r0, r7
     304:	e7fa      	b.n	2fc <__data_size+0xd0>
			/* find the string length including terminating '\0' */
			size = strlen(s) + 1;
		}

		/* make sure it fits */
		if (BUF_OFFSET + 1 + size > len) {
     306:	e9c6 4c00 	strd	r4, ip, [r6]
     30a:	e7f8      	b.n	2fe <__data_size+0xd2>
     30c:	f1c7 0c20 	rsb	ip, r7, #32
			*buf++ = str_ptr_arg[i];
     310:	40bb      	lsls	r3, r7
		if (BUF_OFFSET + 1 + size > len) {
     312:	fa22 f40c 	lsr.w	r4, r2, ip
			*buf++ = str_ptr_arg[i];
     316:	431c      	orrs	r4, r3
	for (i = 0; i < s_idx; i++) {
     318:	fa2e f10c 	lsr.w	r1, lr, ip
	/*
	 * TODO: remove pointers for appended strings since they're useless.
	 * TODO: explore leveraging same mechanism to remove alignment padding
	 */

	return BUF_OFFSET;
     31c:	fa20 f30c 	lsr.w	r3, r0, ip
		pkg_hdr->desc.str_cnt = s_rw_cnt;
     320:	40b8      	lsls	r0, r7
		pkg_hdr->desc.rw_str_cnt = 0;
     322:	4301      	orrs	r1, r0
			if (!(str_ptr_pos[i] & STR_POS_RO_FLAG)) {
     324:	ea4f 4914 	mov.w	r9, r4, lsr #16
     328:	fa0e f507 	lsl.w	r5, lr, r7
			if (BUF_OFFSET + 1 > len) {
     32c:	fbb3 f8f9 	udiv	r8, r3, r9
     330:	fa1f fe84 	uxth.w	lr, r4
			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;
     334:	fb09 3018 	mls	r0, r9, r8, r3
			if (BUF_OFFSET + 1 > len) {
     338:	0c0b      	lsrs	r3, r1, #16
			*buf++ = pos;
     33a:	fb08 fa0e 	mul.w	sl, r8, lr
		for (i = 0; i < s_idx; i++) {
     33e:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
		if (s_ro_cnt && str_ptr_pos[i] & STR_POS_RO_FLAG) {
     342:	459a      	cmp	sl, r3
     344:	fa02 f207 	lsl.w	r2, r2, r7
     348:	d940      	bls.n	3cc <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xcc>
     34a:	18e3      	adds	r3, r4, r3
     34c:	f108 30ff 	add.w	r0, r8, #4294967295
		if (rws_pos_en) {
     350:	d204      	bcs.n	35c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x5c>
     352:	459a      	cmp	sl, r3
			*buf++ = str_ptr_arg[i];
     354:	d902      	bls.n	35c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x5c>
     356:	f1a8 0002 	sub.w	r0, r8, #2
     35a:	4423      	add	r3, r4
			size = 0;
     35c:	eba3 030a 	sub.w	r3, r3, sl
		if (BUF_OFFSET + 1 + size > len) {
     360:	b289      	uxth	r1, r1
     362:	fbb3 f8f9 	udiv	r8, r3, r9
     366:	fb09 3318 	mls	r3, r9, r8, r3
		*buf++ = str_ptr_pos[i];
     36a:	fb08 fe0e 	mul.w	lr, r8, lr
     36e:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
		memcpy(buf, s, size);
     372:	458e      	cmp	lr, r1
     374:	d92c      	bls.n	3d0 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xd0>
     376:	1861      	adds	r1, r4, r1
     378:	f108 33ff 	add.w	r3, r8, #4294967295
		buf += size;
     37c:	d204      	bcs.n	388 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x88>
     37e:	458e      	cmp	lr, r1
	for (i = 0; i < s_idx; i++) {
     380:	d902      	bls.n	388 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x88>
     382:	f1a8 0302 	sub.w	r3, r8, #2
     386:	4421      	add	r1, r4
     388:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
			s = *(char **)(buf0 + str_ptr_pos[i] * sizeof(int));
     38c:	fba0 9802 	umull	r9, r8, r0, r2
     390:	eba1 010e 	sub.w	r1, r1, lr
			*(char **)(buf0 + str_ptr_pos[i] * sizeof(int)) = NULL;
     394:	4541      	cmp	r1, r8
     396:	46ce      	mov	lr, r9
     398:	4643      	mov	r3, r8
			size = strlen(s) + 1;
     39a:	d302      	bcc.n	3a2 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xa2>
     39c:	d106      	bne.n	3ac <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xac>
     39e:	454d      	cmp	r5, r9
     3a0:	d204      	bcs.n	3ac <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xac>
     3a2:	ebb9 0e02 	subs.w	lr, r9, r2
		return -EFAULT;
     3a6:	eb68 0304 	sbc.w	r3, r8, r4
     3aa:	3801      	subs	r0, #1
     3ac:	2e00      	cmp	r6, #0
     3ae:	d0a6      	beq.n	2fe <__data_size+0xd2>
     3b0:	ebb5 020e 	subs.w	r2, r5, lr
     3b4:	eb61 0103 	sbc.w	r1, r1, r3
     3b8:	fa01 fc0c 	lsl.w	ip, r1, ip
     3bc:	fa22 f307 	lsr.w	r3, r2, r7
     3c0:	ea4c 0303 	orr.w	r3, ip, r3
     3c4:	40f9      	lsrs	r1, r7
     3c6:	e9c6 3100 	strd	r3, r1, [r6]
     3ca:	e798      	b.n	2fe <__data_size+0xd2>
     3cc:	4640      	mov	r0, r8
     3ce:	e7c5      	b.n	35c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x5c>
     3d0:	4643      	mov	r3, r8
     3d2:	e7d9      	b.n	388 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x88>

000003d4 <main>:
    return (bool)pin_active;
}
#endif

void main(void)
{
     3d4:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
}

NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type *        p_reg,
                                                  nrf_wdt_rr_register_t rr_register)
{
    p_reg->RR[rr_register] = NRF_WDT_RR_VALUE;
     3d6:	4b26      	ldr	r3, [pc, #152]	; (470 <FIH_LABEL_FIH_CALL_END_224+0x64>)
     3d8:	4a26      	ldr	r2, [pc, #152]	; (474 <FIH_LABEL_FIH_CALL_END_224+0x68>)
     3da:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
    fih_int fih_rc = FIH_FAILURE;

    MCUBOOT_WATCHDOG_FEED();

#if !defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Starting bootloader");
     3de:	4826      	ldr	r0, [pc, #152]	; (478 <FIH_LABEL_FIH_CALL_END_224+0x6c>)
     3e0:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
     3e4:	2149      	movs	r1, #73	; 0x49
     3e6:	f8c3 2608 	str.w	r2, [r3, #1544]	; 0x608
     3ea:	f8c3 260c 	str.w	r2, [r3, #1548]	; 0x60c
     3ee:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
     3f2:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
     3f6:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
     3fa:	f8c3 261c 	str.w	r2, [r3, #1564]	; 0x61c
     3fe:	f008 fc68 	bl	8cd2 <z_log_minimal_printk>
#ifdef CONFIG_MCUBOOT_INDICATION_LED
    /* LED init */
    led_init();
#endif

    os_heap_init();
     402:	f008 f807 	bl	8414 <os_heap_init>

00000406 <FIH_LABEL_FIH_CALL_START_212>:
    rc = boot_console_init();
    int timeout_in_ms = CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT;
    uint32_t start = k_uptime_get_32();
#endif

    FIH_CALL(boot_go, fih_rc, &rsp);
     406:	a801      	add	r0, sp, #4
     408:	f000 fc6c 	bl	ce4 <boot_go>

0000040c <FIH_LABEL_FIH_CALL_END_224>:
        timeout_in_ms = 1;
    }
    boot_serial_check_start(&boot_funcs,timeout_in_ms);
#endif

    if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     40c:	4b1b      	ldr	r3, [pc, #108]	; (47c <FIH_LABEL_FIH_CALL_END_224+0x70>)
     40e:	681b      	ldr	r3, [r3, #0]
     410:	4283      	cmp	r3, r0
     412:	d004      	beq.n	41e <FIH_LABEL_FIH_CALL_END_224+0x12>
        BOOT_LOG_ERR("Unable to find bootable image");
     414:	481a      	ldr	r0, [pc, #104]	; (480 <FIH_LABEL_FIH_CALL_END_224+0x74>)
     416:	2145      	movs	r1, #69	; 0x45
     418:	f008 fc5b 	bl	8cd2 <z_log_minimal_printk>

        mcuboot_status_change(MCUBOOT_STATUS_NO_BOOTABLE_IMAGE_FOUND);

        FIH_PANIC;
     41c:	e7fe      	b.n	41c <FIH_LABEL_FIH_CALL_END_224+0x10>
    }

    BOOT_LOG_INF("Bootloader chainload address offset: 0x%x",
     41e:	9a03      	ldr	r2, [sp, #12]
     420:	4818      	ldr	r0, [pc, #96]	; (484 <FIH_LABEL_FIH_CALL_END_224+0x78>)
     422:	2149      	movs	r1, #73	; 0x49
     424:	f008 fc55 	bl	8cd2 <z_log_minimal_printk>
                 rsp.br_image_off);

#if defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Jumping to the image slot");
#else
    BOOT_LOG_INF("Jumping to the first image slot");
     428:	4817      	ldr	r0, [pc, #92]	; (488 <FIH_LABEL_FIH_CALL_END_224+0x7c>)
     42a:	2149      	movs	r1, #73	; 0x49
     42c:	f008 fc51 	bl	8cd2 <z_log_minimal_printk>
    rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
     430:	4669      	mov	r1, sp
     432:	f89d 0008 	ldrb.w	r0, [sp, #8]
     436:	f000 f82b 	bl	490 <flash_device_base>
    vt = (struct arm_vector_table *)(flash_base +
     43a:	9b00      	ldr	r3, [sp, #0]
     43c:	9c03      	ldr	r4, [sp, #12]
     43e:	441c      	add	r4, r3
                                     rsp->br_hdr->ih_hdr_size);
     440:	9b01      	ldr	r3, [sp, #4]
     442:	891d      	ldrh	r5, [r3, #8]
    nrf_cleanup_peripheral();
     444:	f000 ff3a 	bl	12bc <nrf_cleanup_peripheral>
                                     rsp->br_image_off +
     448:	1966      	adds	r6, r4, r5
		:
		: "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	unsigned int tmp;

	__asm__ volatile(
     44a:	f04f 0220 	mov.w	r2, #32
     44e:	f3ef 8311 	mrs	r3, BASEPRI
     452:	f382 8812 	msr	BASEPRI_MAX, r2
     456:	f3bf 8f6f 	isb	sy
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
     45a:	5963      	ldr	r3, [r4, r5]
     45c:	f383 8808 	msr	MSP, r3
    ((void (*)(void))vt->reset)();
     460:	6873      	ldr	r3, [r6, #4]
     462:	4798      	blx	r3

    do_boot(&rsp);

    mcuboot_status_change(MCUBOOT_STATUS_BOOT_FAILED);

    BOOT_LOG_ERR("Never should get here");
     464:	4809      	ldr	r0, [pc, #36]	; (48c <FIH_LABEL_FIH_CALL_END_224+0x80>)
     466:	2145      	movs	r1, #69	; 0x45
     468:	f008 fc33 	bl	8cd2 <z_log_minimal_printk>
    while (1)
     46c:	e7fe      	b.n	46c <FIH_LABEL_FIH_CALL_END_224+0x60>
     46e:	bf00      	nop
     470:	40010000 	.word	0x40010000
     474:	6e524635 	.word	0x6e524635
     478:	0000a5dc 	.word	0x0000a5dc
     47c:	20000438 	.word	0x20000438
     480:	0000a5f5 	.word	0x0000a5f5
     484:	0000a618 	.word	0x0000a618
     488:	0000a647 	.word	0x0000a647
     48c:	0000a66c 	.word	0x0000a66c

00000490 <flash_device_base>:
#endif

static const struct device *flash_dev = DEVICE_DT_GET(FLASH_DEVICE_NODE);

int flash_device_base(uint8_t fd_id, uintptr_t *ret)
{
     490:	b508      	push	{r3, lr}
    if (fd_id != FLASH_DEVICE_ID) {
     492:	4602      	mov	r2, r0
     494:	b138      	cbz	r0, 4a6 <flash_device_base+0x16>
        BOOT_LOG_ERR("invalid flash ID %d; expected %d",
     496:	4805      	ldr	r0, [pc, #20]	; (4ac <flash_device_base+0x1c>)
     498:	2300      	movs	r3, #0
     49a:	2145      	movs	r1, #69	; 0x45
     49c:	f008 fc19 	bl	8cd2 <z_log_minimal_printk>
                     fd_id, FLASH_DEVICE_ID);
        return -EINVAL;
     4a0:	f06f 0015 	mvn.w	r0, #21
    }
    *ret = FLASH_DEVICE_BASE;
    return 0;
}
     4a4:	bd08      	pop	{r3, pc}
    *ret = FLASH_DEVICE_BASE;
     4a6:	6008      	str	r0, [r1, #0]
    return 0;
     4a8:	e7fc      	b.n	4a4 <flash_device_base+0x14>
     4aa:	bf00      	nop
     4ac:	0000a68f 	.word	0x0000a68f

000004b0 <flash_area_sector_from_off>:
    return -EINVAL;
}
#endif

int flash_area_sector_from_off(off_t off, struct flash_sector *sector)
{
     4b0:	b51f      	push	{r0, r1, r2, r3, r4, lr}
     4b2:	460c      	mov	r4, r1
		union { uintptr_t x; struct flash_pages_info * val; } parm2 = { .val = info };
		return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS);
	}
#endif
	compiler_barrier();
	return z_impl_flash_get_page_info_by_offs(dev, offset, info);
     4b4:	4601      	mov	r1, r0
     4b6:	aa01      	add	r2, sp, #4
     4b8:	4804      	ldr	r0, [pc, #16]	; (4cc <flash_area_sector_from_off+0x1c>)
     4ba:	f008 ffec 	bl	9496 <z_impl_flash_get_page_info_by_offs>
    int rc;
    struct flash_pages_info page;

    rc = flash_get_page_info_by_offs(flash_dev, off, &page);
    if (rc) {
     4be:	b918      	cbnz	r0, 4c8 <flash_area_sector_from_off+0x18>
        return rc;
    }

    sector->fs_off = page.start_offset;
     4c0:	9b01      	ldr	r3, [sp, #4]
     4c2:	6023      	str	r3, [r4, #0]
    sector->fs_size = page.size;
     4c4:	9b02      	ldr	r3, [sp, #8]
     4c6:	6063      	str	r3, [r4, #4]

    return rc;
}
     4c8:	b004      	add	sp, #16
     4ca:	bd10      	pop	{r4, pc}
     4cc:	00009e7c 	.word	0x00009e7c

000004d0 <bootutil_img_validate>:
fih_int
bootutil_img_validate(struct enc_key_data *enc_state, int image_index,
                      struct image_header *hdr, const struct flash_area *fap,
                      uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *seed,
                      int seed_len, uint8_t *out_hash)
{
     4d0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     4d4:	461e      	mov	r6, r3
     4d6:	b0db      	sub	sp, #364	; 0x16c
    uint32_t off;
    uint16_t len;
    uint16_t type;
    int sha256_valid = 0;
#ifdef EXPECTED_SIG_TLV
    fih_int valid_signature = FIH_FAILURE;
     4d8:	4b82      	ldr	r3, [pc, #520]	; (6e4 <FIH_LABEL_FIH_CALL_END_1006+0x20>)
{
     4da:	f8dd b1a0 	ldr.w	fp, [sp, #416]	; 0x1a0
    fih_int valid_signature = FIH_FAILURE;
     4de:	f8d3 8000 	ldr.w	r8, [r3]
{
     4e2:	e9dd 5766 	ldrd	r5, r7, [sp, #408]	; 0x198
     4e6:	4614      	mov	r4, r2
}

/* Enable and disable cc310 to reduce power consumption */
static inline void cc310_sha256_init(nrf_cc310_bl_hash_context_sha256_t * ctx)
{
    cc310_init();
     4e8:	f000 feb2 	bl	1250 <cc310_init>
    NRF_CRYPTOCELL->ENABLE=1;
     4ec:	4b7e      	ldr	r3, [pc, #504]	; (6e8 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     4ee:	2201      	movs	r2, #1
     4f0:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    nrf_cc310_enable();
    nrf_cc310_bl_hash_sha256_init(ctx);
     4f4:	a83a      	add	r0, sp, #232	; 0xe8
     4f6:	f006 fec1 	bl	727c <nrf_cc310_bl_hash_sha256_init>
    if (seed && (seed_len > 0)) {
     4fa:	b135      	cbz	r5, 50a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x22>
     4fc:	2f00      	cmp	r7, #0
     4fe:	dd04      	ble.n	50a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x22>

static inline int bootutil_sha256_update(bootutil_sha256_context *ctx,
                                          const void *data,
                                          uint32_t data_len)
{
    cc310_sha256_update(ctx, data, data_len);
     500:	463a      	mov	r2, r7
     502:	4629      	mov	r1, r5
     504:	a83a      	add	r0, sp, #232	; 0xe8
     506:	f008 fad5 	bl	8ab4 <cc310_sha256_update>
    size += hdr->ih_protect_tlv_size;
     50a:	8963      	ldrh	r3, [r4, #10]
    size = hdr_size = hdr->ih_hdr_size;
     50c:	8927      	ldrh	r7, [r4, #8]
     50e:	441f      	add	r7, r3
    size += hdr->ih_protect_tlv_size;
     510:	68e3      	ldr	r3, [r4, #12]
    for (off = 0; off < size; off += blk_sz) {
     512:	f04f 0900 	mov.w	r9, #0
    size += hdr->ih_protect_tlv_size;
     516:	441f      	add	r7, r3
    for (off = 0; off < size; off += blk_sz) {
     518:	454f      	cmp	r7, r9
     51a:	d825      	bhi.n	568 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x80>
}

static inline void cc310_sha256_finalize(bootutil_sha256_context *ctx,
                                          uint8_t *output)
{
    nrf_cc310_bl_hash_sha256_finalize(ctx,
     51c:	a90d      	add	r1, sp, #52	; 0x34
     51e:	a83a      	add	r0, sp, #232	; 0xe8
     520:	f006 ff1e 	bl	7360 <nrf_cc310_bl_hash_sha256_finalize>
    NRF_CRYPTOCELL->ENABLE=0;
     524:	4b70      	ldr	r3, [pc, #448]	; (6e8 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     526:	2200      	movs	r2, #0
     528:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
     52c:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
            tmp_buf_sz, hash, seed, seed_len);
    if (rc) {
        goto out;
    }

    if (out_hash) {
     530:	f1bb 0f00 	cmp.w	fp, #0
     534:	d004      	beq.n	540 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x58>
        memcpy(out_hash, hash, 32);
     536:	2220      	movs	r2, #32
     538:	a90d      	add	r1, sp, #52	; 0x34
     53a:	4658      	mov	r0, fp
     53c:	f008 fc7b 	bl	8e36 <memcpy>
    }

    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
     540:	2300      	movs	r3, #0
     542:	9300      	str	r3, [sp, #0]
     544:	4632      	mov	r2, r6
     546:	f64f 73ff 	movw	r3, #65535	; 0xffff
     54a:	4621      	mov	r1, r4
     54c:	a807      	add	r0, sp, #28
     54e:	f007 ff62 	bl	8416 <bootutil_tlv_iter_begin>
    if (rc) {
     552:	4605      	mov	r5, r0
     554:	b9d0      	cbnz	r0, 58c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa4>
        goto out;
    }

    if (it.tlv_end > bootutil_max_image_size(fap)) {
     556:	4630      	mov	r0, r6
     558:	9c0c      	ldr	r4, [sp, #48]	; 0x30
     55a:	f000 f983 	bl	864 <bootutil_max_image_size>
     55e:	4284      	cmp	r4, r0
     560:	d91f      	bls.n	5a2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xba>
        rc = -1;
     562:	f04f 35ff 	mov.w	r5, #4294967295
     566:	e011      	b.n	58c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa4>
        if (blk_sz > tmp_buf_sz) {
     568:	9b65      	ldr	r3, [sp, #404]	; 0x194
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     56a:	9a64      	ldr	r2, [sp, #400]	; 0x190
        blk_sz = size - off;
     56c:	eba7 0a09 	sub.w	sl, r7, r9
     570:	459a      	cmp	sl, r3
     572:	bf28      	it	cs
     574:	469a      	movcs	sl, r3
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     576:	4653      	mov	r3, sl
     578:	4649      	mov	r1, r9
     57a:	4630      	mov	r0, r6
     57c:	f008 fbb7 	bl	8cee <flash_area_read>
        if (rc) {
     580:	4605      	mov	r5, r0
     582:	b138      	cbz	r0, 594 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xac>
     584:	4b58      	ldr	r3, [pc, #352]	; (6e8 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     586:	2200      	movs	r2, #0
     588:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     58c:	4628      	mov	r0, r5
     58e:	b05b      	add	sp, #364	; 0x16c
     590:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     594:	9964      	ldr	r1, [sp, #400]	; 0x190
     596:	4652      	mov	r2, sl
     598:	a83a      	add	r0, sp, #232	; 0xe8
     59a:	f008 fa8b 	bl	8ab4 <cc310_sha256_update>
    for (off = 0; off < size; off += blk_sz) {
     59e:	44d1      	add	r9, sl
     5a0:	e7ba      	b.n	518 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x30>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     5a2:	f8df b150 	ldr.w	fp, [pc, #336]	; 6f4 <FIH_LABEL_FIH_CALL_END_1006+0x30>
     5a6:	f8df 9140 	ldr.w	r9, [pc, #320]	; 6e8 <FIH_LABEL_FIH_CALL_END_1006+0x24>
    int key_id = -1;
     5aa:	f04f 37ff 	mov.w	r7, #4294967295
        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
     5ae:	f10d 0316 	add.w	r3, sp, #22
     5b2:	aa05      	add	r2, sp, #20
     5b4:	a906      	add	r1, sp, #24
     5b6:	a807      	add	r0, sp, #28
     5b8:	f007 ff7b 	bl	84b2 <bootutil_tlv_iter_next>
        if (rc < 0) {
     5bc:	1e04      	subs	r4, r0, #0
     5be:	f2c0 808f 	blt.w	6e0 <FIH_LABEL_FIH_CALL_END_1006+0x1c>
        } else if (rc > 0) {
     5c2:	f040 8082 	bne.w	6ca <FIH_LABEL_FIH_CALL_END_1006+0x6>
        if (type == IMAGE_TLV_SHA256) {
     5c6:	f8bd a016 	ldrh.w	sl, [sp, #22]
     5ca:	f1ba 0f10 	cmp.w	sl, #16
     5ce:	d118      	bne.n	602 <FIH_LABEL_FIH_CALL_END_689+0xc>
            if (len != sizeof(hash)) {
     5d0:	f8bd 5014 	ldrh.w	r5, [sp, #20]
     5d4:	2d20      	cmp	r5, #32
     5d6:	d1c4      	bne.n	562 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x7a>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, sizeof(hash));
     5d8:	9906      	ldr	r1, [sp, #24]
     5da:	462b      	mov	r3, r5
     5dc:	aa3a      	add	r2, sp, #232	; 0xe8
     5de:	4630      	mov	r0, r6
     5e0:	f008 fb85 	bl	8cee <flash_area_read>
            if (rc) {
     5e4:	4604      	mov	r4, r0
     5e6:	2800      	cmp	r0, #0
     5e8:	d17a      	bne.n	6e0 <FIH_LABEL_FIH_CALL_END_1006+0x1c>

000005ea <FIH_LABEL_FIH_CALL_START_672>:
            FIH_CALL(boot_fih_memequal, fih_rc, hash, buf, sizeof(hash));
     5ea:	462a      	mov	r2, r5
     5ec:	a93a      	add	r1, sp, #232	; 0xe8
     5ee:	a80d      	add	r0, sp, #52	; 0x34
     5f0:	f007 ffd7 	bl	85a2 <boot_fih_memequal>
     5f4:	4605      	mov	r5, r0

000005f6 <FIH_LABEL_FIH_CALL_END_689>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     5f6:	4b3d      	ldr	r3, [pc, #244]	; (6ec <FIH_LABEL_FIH_CALL_END_1006+0x28>)
     5f8:	681b      	ldr	r3, [r3, #0]
     5fa:	4283      	cmp	r3, r0
     5fc:	d1c6      	bne.n	58c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa4>
            sha256_valid = 1;
     5fe:	2501      	movs	r5, #1
     600:	e7d5      	b.n	5ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc6>
        } else if (type == IMAGE_TLV_KEYHASH) {
     602:	f1ba 0f01 	cmp.w	sl, #1
     606:	d13e      	bne.n	686 <FIH_LABEL_FIH_CALL_END_689+0x90>
            if (len > 32) {
     608:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     60c:	2b20      	cmp	r3, #32
     60e:	d8a8      	bhi.n	562 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x7a>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     610:	9906      	ldr	r1, [sp, #24]
     612:	aa3a      	add	r2, sp, #232	; 0xe8
     614:	4630      	mov	r0, r6
     616:	f008 fb6a 	bl	8cee <flash_area_read>
            if (rc) {
     61a:	4604      	mov	r4, r0
     61c:	2800      	cmp	r0, #0
     61e:	d15f      	bne.n	6e0 <FIH_LABEL_FIH_CALL_END_1006+0x1c>
            key_id = bootutil_find_key(buf, len);
     620:	f89d 3014 	ldrb.w	r3, [sp, #20]
     624:	9302      	str	r3, [sp, #8]
    if (keyhash_len > 32) {
     626:	2b20      	cmp	r3, #32
     628:	d809      	bhi.n	63e <FIH_LABEL_FIH_CALL_END_689+0x48>
    for (i = 0; i < bootutil_key_cnt; i++) {
     62a:	f8db 3000 	ldr.w	r3, [fp]
     62e:	4f30      	ldr	r7, [pc, #192]	; (6f0 <FIH_LABEL_FIH_CALL_END_1006+0x2c>)
     630:	9303      	str	r3, [sp, #12]
     632:	9b03      	ldr	r3, [sp, #12]
     634:	429c      	cmp	r4, r3
     636:	db05      	blt.n	644 <FIH_LABEL_FIH_CALL_END_689+0x4e>
     638:	2300      	movs	r3, #0
     63a:	f8c9 3500 	str.w	r3, [r9, #1280]	; 0x500
        return -1;
     63e:	f04f 34ff 	mov.w	r4, #4294967295
     642:	e01c      	b.n	67e <FIH_LABEL_FIH_CALL_END_689+0x88>
    cc310_init();
     644:	f000 fe04 	bl	1250 <cc310_init>
    NRF_CRYPTOCELL->ENABLE=1;
     648:	f8c9 a500 	str.w	sl, [r9, #1280]	; 0x500
    nrf_cc310_bl_hash_sha256_init(ctx);
     64c:	a81d      	add	r0, sp, #116	; 0x74
     64e:	f006 fe15 	bl	727c <nrf_cc310_bl_hash_sha256_init>
        bootutil_sha256_update(&sha256_ctx, key->key, *key->len);
     652:	687a      	ldr	r2, [r7, #4]
     654:	f857 1b08 	ldr.w	r1, [r7], #8
     658:	6812      	ldr	r2, [r2, #0]
     65a:	a81d      	add	r0, sp, #116	; 0x74
     65c:	f008 fa2a 	bl	8ab4 <cc310_sha256_update>
    nrf_cc310_bl_hash_sha256_finalize(ctx,
     660:	a915      	add	r1, sp, #84	; 0x54
     662:	a81d      	add	r0, sp, #116	; 0x74
     664:	f006 fe7c 	bl	7360 <nrf_cc310_bl_hash_sha256_finalize>
    NRF_CRYPTOCELL->ENABLE=0;
     668:	2200      	movs	r2, #0
     66a:	f8c9 2500 	str.w	r2, [r9, #1280]	; 0x500
        if (!memcmp(hash, keyhash, keyhash_len)) {
     66e:	9a02      	ldr	r2, [sp, #8]
     670:	a93a      	add	r1, sp, #232	; 0xe8
     672:	a815      	add	r0, sp, #84	; 0x54
     674:	f008 fbcf 	bl	8e16 <memcmp>
     678:	b918      	cbnz	r0, 682 <FIH_LABEL_FIH_CALL_END_689+0x8c>
     67a:	f8c9 0500 	str.w	r0, [r9, #1280]	; 0x500
            key_id = bootutil_find_key(buf, len);
     67e:	4627      	mov	r7, r4
     680:	e795      	b.n	5ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc6>
    for (i = 0; i < bootutil_key_cnt; i++) {
     682:	3401      	adds	r4, #1
     684:	e7d5      	b.n	632 <FIH_LABEL_FIH_CALL_END_689+0x3c>
        } else if (type == EXPECTED_SIG_TLV) {
     686:	f1ba 0f22 	cmp.w	sl, #34	; 0x22
     68a:	d190      	bne.n	5ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc6>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     68c:	1c7b      	adds	r3, r7, #1
     68e:	d08e      	beq.n	5ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc6>
     690:	f8db 3000 	ldr.w	r3, [fp]
     694:	42bb      	cmp	r3, r7
     696:	dd15      	ble.n	6c4 <FIH_LABEL_FIH_CALL_END_1006>
            if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {
     698:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     69c:	2b80      	cmp	r3, #128	; 0x80
     69e:	f63f af60 	bhi.w	562 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x7a>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     6a2:	9906      	ldr	r1, [sp, #24]
     6a4:	aa3a      	add	r2, sp, #232	; 0xe8
     6a6:	4630      	mov	r0, r6
     6a8:	f008 fb21 	bl	8cee <flash_area_read>
            if (rc) {
     6ac:	4604      	mov	r4, r0
     6ae:	b9b8      	cbnz	r0, 6e0 <FIH_LABEL_FIH_CALL_END_1006+0x1c>

000006b0 <FIH_LABEL_FIH_CALL_START_985>:
            FIH_CALL(bootutil_verify_sig, valid_signature, hash, sizeof(hash),
     6b0:	b2ff      	uxtb	r7, r7
     6b2:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     6b6:	9700      	str	r7, [sp, #0]
     6b8:	aa3a      	add	r2, sp, #232	; 0xe8
     6ba:	2120      	movs	r1, #32
     6bc:	a80d      	add	r0, sp, #52	; 0x34
     6be:	f000 f81b 	bl	6f8 <bootutil_verify_sig>
     6c2:	4680      	mov	r8, r0

000006c4 <FIH_LABEL_FIH_CALL_END_1006>:
            key_id = -1;
     6c4:	f04f 37ff 	mov.w	r7, #4294967295
     6c8:	e771      	b.n	5ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc6>
    if (rc) {
     6ca:	b145      	cbz	r5, 6de <FIH_LABEL_FIH_CALL_END_1006+0x1a>
    fih_rc = fih_int_encode_zero_equality(fih_not_eq(valid_signature,
     6cc:	4b07      	ldr	r3, [pc, #28]	; (6ec <FIH_LABEL_FIH_CALL_END_1006+0x28>)
 * value that is not FIH_SUCCESS
 */
__attribute__((always_inline)) inline
fih_int fih_int_encode_zero_equality(int x)
{
    if (x) {
     6ce:	681b      	ldr	r3, [r3, #0]
     6d0:	4543      	cmp	r3, r8
        return FIH_FAILURE;
     6d2:	bf1c      	itt	ne
     6d4:	4b03      	ldrne	r3, [pc, #12]	; (6e4 <FIH_LABEL_FIH_CALL_END_1006+0x20>)
     6d6:	f8d3 8000 	ldrne.w	r8, [r3]
        return -1;
     6da:	4645      	mov	r5, r8
     6dc:	e756      	b.n	58c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa4>
    rc = !sha256_valid;
     6de:	2401      	movs	r4, #1
        return -1;
     6e0:	4625      	mov	r5, r4
     6e2:	e753      	b.n	58c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa4>
     6e4:	20000000 	.word	0x20000000
     6e8:	5002a000 	.word	0x5002a000
     6ec:	20000438 	.word	0x20000438
     6f0:	0000a12c 	.word	0x0000a12c
     6f4:	0000a128 	.word	0x0000a128

000006f8 <bootutil_verify_sig>:
#endif /* not MCUBOOT_ECDSA_NEED_ASN1_SIG */

int
bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen,
  uint8_t key_id)
{
     6f8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     6fc:	b096      	sub	sp, #88	; 0x58
     6fe:	4617      	mov	r7, r2
     700:	461d      	mov	r5, r3
     702:	f89d 2070 	ldrb.w	r2, [sp, #112]	; 0x70

#ifndef MCUBOOT_ECDSA_NEED_ASN1_SIG
    uint8_t signature[2 * NUM_ECC_BYTES];
#endif

    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     706:	4b35      	ldr	r3, [pc, #212]	; (7dc <bootutil_verify_sig+0xe4>)
{
     708:	460e      	mov	r6, r1
    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     70a:	f853 1032 	ldr.w	r1, [r3, r2, lsl #3]
     70e:	9101      	str	r1, [sp, #4]
    end = pubkey + *bootutil_keys[key_id].len;
     710:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
{
     714:	4680      	mov	r8, r0
    end = pubkey + *bootutil_keys[key_id].len;
     716:	685b      	ldr	r3, [r3, #4]
     718:	6818      	ldr	r0, [r3, #0]
    if (mbedtls_asn1_get_tag(cp, end, &len,
     71a:	aa02      	add	r2, sp, #8
     71c:	4401      	add	r1, r0
     71e:	2330      	movs	r3, #48	; 0x30
     720:	a801      	add	r0, sp, #4
     722:	f008 f955 	bl	89d0 <mbedtls_asn1_get_tag>
     726:	b120      	cbz	r0, 732 <bootutil_verify_sig+0x3a>
    rc = bootutil_parse_eckey(&ctx, &pubkey, end);
#else
    rc = bootutil_import_key(&pubkey, end);
#endif
    if (rc) {
        return -1;
     728:	f04f 30ff 	mov.w	r0, #4294967295
#endif /* CY_MBEDTLS_HW_ACCELERATION */

    bootutil_ecdsa_p256_drop(&ctx);

    return rc;
}
     72c:	b016      	add	sp, #88	; 0x58
     72e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    end = *cp + len;
     732:	e9dd 4301 	ldrd	r4, r3, [sp, #4]
     736:	441c      	add	r4, r3
    if (mbedtls_asn1_get_alg(cp, end, &alg, &param)) {
     738:	aa03      	add	r2, sp, #12
     73a:	ab06      	add	r3, sp, #24
     73c:	4621      	mov	r1, r4
     73e:	a801      	add	r0, sp, #4
     740:	f008 f96e 	bl	8a20 <mbedtls_asn1_get_alg>
     744:	2800      	cmp	r0, #0
     746:	d1ef      	bne.n	728 <bootutil_verify_sig+0x30>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     748:	9a04      	ldr	r2, [sp, #16]
     74a:	2a07      	cmp	r2, #7
     74c:	d1ec      	bne.n	728 <bootutil_verify_sig+0x30>
        memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
     74e:	4924      	ldr	r1, [pc, #144]	; (7e0 <bootutil_verify_sig+0xe8>)
     750:	9805      	ldr	r0, [sp, #20]
     752:	f008 fb60 	bl	8e16 <memcmp>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     756:	2800      	cmp	r0, #0
     758:	d1e6      	bne.n	728 <bootutil_verify_sig+0x30>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     75a:	9a07      	ldr	r2, [sp, #28]
     75c:	2a08      	cmp	r2, #8
     75e:	d1e3      	bne.n	728 <bootutil_verify_sig+0x30>
        memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
     760:	4920      	ldr	r1, [pc, #128]	; (7e4 <bootutil_verify_sig+0xec>)
     762:	9808      	ldr	r0, [sp, #32]
     764:	f008 fb57 	bl	8e16 <memcmp>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     768:	2800      	cmp	r0, #0
     76a:	d1dd      	bne.n	728 <bootutil_verify_sig+0x30>
    if (mbedtls_asn1_get_bitstring_null(cp, end, &len)) {
     76c:	aa02      	add	r2, sp, #8
     76e:	4621      	mov	r1, r4
     770:	a801      	add	r0, sp, #4
     772:	f008 f941 	bl	89f8 <mbedtls_asn1_get_bitstring_null>
     776:	2800      	cmp	r0, #0
     778:	d1d6      	bne.n	728 <bootutil_verify_sig+0x30>
    if (*cp + len != end) {
     77a:	e9dd 3201 	ldrd	r3, r2, [sp, #4]
     77e:	4413      	add	r3, r2
     780:	429c      	cmp	r4, r3
     782:	d1d1      	bne.n	728 <bootutil_verify_sig+0x30>
    if (len != 2 * NUM_ECC_BYTES + 1) {
     784:	2a41      	cmp	r2, #65	; 0x41
     786:	d1cf      	bne.n	728 <bootutil_verify_sig+0x30>
    rc = bootutil_decode_sig(signature, sig, sig + slen);
     788:	443d      	add	r5, r7
    rc = mbedtls_asn1_get_tag(&cp, end, &len,
     78a:	2330      	movs	r3, #48	; 0x30
     78c:	aa03      	add	r2, sp, #12
     78e:	4629      	mov	r1, r5
     790:	a802      	add	r0, sp, #8
     792:	9702      	str	r7, [sp, #8]
     794:	f008 f91c 	bl	89d0 <mbedtls_asn1_get_tag>
    if (rc) {
     798:	2800      	cmp	r0, #0
     79a:	d1c5      	bne.n	728 <bootutil_verify_sig+0x30>
    if (cp + len > end) {
     79c:	e9dd 3202 	ldrd	r3, r2, [sp, #8]
     7a0:	4413      	add	r3, r2
     7a2:	429d      	cmp	r5, r3
     7a4:	d3c0      	bcc.n	728 <bootutil_verify_sig+0x30>
    rc = bootutil_read_bigint(signature, &cp, end);
     7a6:	462a      	mov	r2, r5
     7a8:	a902      	add	r1, sp, #8
     7aa:	a806      	add	r0, sp, #24
     7ac:	f007 fecd 	bl	854a <bootutil_read_bigint>
    if (rc) {
     7b0:	2800      	cmp	r0, #0
     7b2:	d1b9      	bne.n	728 <bootutil_verify_sig+0x30>
    rc = bootutil_read_bigint(signature + NUM_ECC_BYTES, &cp, end);
     7b4:	462a      	mov	r2, r5
     7b6:	a902      	add	r1, sp, #8
     7b8:	a80e      	add	r0, sp, #56	; 0x38
     7ba:	f007 fec6 	bl	854a <bootutil_read_bigint>
    if (rc) {
     7be:	2800      	cmp	r0, #0
     7c0:	d1b2      	bne.n	728 <bootutil_verify_sig+0x30>
    if (hlen != NUM_ECC_BYTES) {
     7c2:	2e20      	cmp	r6, #32
     7c4:	d1b0      	bne.n	728 <bootutil_verify_sig+0x30>
    rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, signature,
     7c6:	9901      	ldr	r1, [sp, #4]
    (void)ctx;
    (void)pk_len;
    (void)sig_len;

    /* Only support uncompressed keys. */
    if (pk[0] != 0x04) {
     7c8:	780b      	ldrb	r3, [r1, #0]
     7ca:	2b04      	cmp	r3, #4
     7cc:	d1ac      	bne.n	728 <bootutil_verify_sig+0x30>
        return -1;
    }
    pk++;

    return cc310_ecdsa_verify_secp256r1(hash, pk, sig, BOOTUTIL_CRYPTO_ECDSA_P256_HASH_SIZE);
     7ce:	4633      	mov	r3, r6
     7d0:	aa06      	add	r2, sp, #24
     7d2:	3101      	adds	r1, #1
     7d4:	4640      	mov	r0, r8
     7d6:	f000 fd53 	bl	1280 <cc310_ecdsa_verify_secp256r1>
     7da:	e7a7      	b.n	72c <bootutil_verify_sig+0x34>
     7dc:	0000a12c 	.word	0x0000a12c
     7e0:	0000a6be 	.word	0x0000a6be
     7e4:	0000a6b5 	.word	0x0000a6b5

000007e8 <boot_read_swap_size>:
    return -1;
}

int
boot_read_swap_size(int image_index, uint32_t *swap_size)
{
     7e8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     7ec:	b086      	sub	sp, #24
    uint8_t areas[2] = {
     7ee:	2303      	movs	r3, #3
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     7f0:	f8df 806c 	ldr.w	r8, [pc, #108]	; 860 <CONFIG_ISR_STACK_SIZE+0x60>
    uint8_t areas[2] = {
     7f4:	f8ad 3000 	strh.w	r3, [sp]
{
     7f8:	460d      	mov	r5, r1
     7fa:	466f      	mov	r7, sp
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     7fc:	2600      	movs	r6, #0
        rc = flash_area_open(areas[i], fap);
     7fe:	f817 0b01 	ldrb.w	r0, [r7], #1
     802:	a901      	add	r1, sp, #4
     804:	f001 f8e8 	bl	19d8 <flash_area_open>
        if (rc != 0) {
     808:	4604      	mov	r4, r0
     80a:	b9a0      	cbnz	r0, 836 <CONFIG_ISR_STACK_SIZE+0x36>
        off = boot_magic_off(*fap);
     80c:	9801      	ldr	r0, [sp, #4]
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
     80e:	6881      	ldr	r1, [r0, #8]
        rc = flash_area_read(*fap, off, magic, BOOT_MAGIC_SZ);
     810:	2310      	movs	r3, #16
     812:	aa02      	add	r2, sp, #8
     814:	3910      	subs	r1, #16
     816:	f008 fa6a 	bl	8cee <flash_area_read>
     81a:	4604      	mov	r4, r0
        flash_area_close(*fap);
     81c:	9801      	ldr	r0, [sp, #4]
     81e:	f008 fa65 	bl	8cec <flash_area_close>
        if (rc != 0) {
     822:	b944      	cbnz	r4, 836 <CONFIG_ISR_STACK_SIZE+0x36>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     824:	2210      	movs	r2, #16
     826:	4641      	mov	r1, r8
     828:	a802      	add	r0, sp, #8
     82a:	f008 faf4 	bl	8e16 <memcmp>
     82e:	b140      	cbz	r0, 842 <CONFIG_ISR_STACK_SIZE+0x42>
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     830:	b12e      	cbz	r6, 83e <CONFIG_ISR_STACK_SIZE+0x3e>
    return -1;
     832:	f04f 34ff 	mov.w	r4, #4294967295
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
        flash_area_close(fap);
    }

    return rc;
}
     836:	4620      	mov	r0, r4
     838:	b006      	add	sp, #24
     83a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     83e:	2601      	movs	r6, #1
     840:	e7dd      	b.n	7fe <boot_read_swap_size+0x16>
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
     842:	9801      	ldr	r0, [sp, #4]
     844:	f008 ff03 	bl	964e <boot_swap_info_off>
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
     848:	2304      	movs	r3, #4
     84a:	f1a0 0108 	sub.w	r1, r0, #8
     84e:	462a      	mov	r2, r5
     850:	9801      	ldr	r0, [sp, #4]
     852:	f008 fa4c 	bl	8cee <flash_area_read>
     856:	4604      	mov	r4, r0
        flash_area_close(fap);
     858:	9801      	ldr	r0, [sp, #4]
     85a:	f008 fa47 	bl	8cec <flash_area_close>
     85e:	e7ea      	b.n	836 <CONFIG_ISR_STACK_SIZE+0x36>
     860:	0000a5cc 	.word	0x0000a5cc

00000864 <bootutil_max_image_size>:
    return 0;
}
#endif

uint32_t bootutil_max_image_size(const struct flash_area *fap)
{
     864:	b507      	push	{r0, r1, r2, lr}
#if defined(MCUBOOT_SWAP_USING_SCRATCH)
    return boot_status_off(fap);
#elif defined(MCUBOOT_SWAP_USING_MOVE)
    struct flash_sector sector;
    /* get the last sector offset */
    int rc = flash_area_sector_from_off(boot_status_off(fap), &sector);
     866:	f007 fead 	bl	85c4 <boot_status_off>
     86a:	4669      	mov	r1, sp
     86c:	f7ff fe20 	bl	4b0 <flash_area_sector_from_off>
    if (rc) {
     870:	b138      	cbz	r0, 882 <__z_interrupt_stack_SIZEOF+0x2>
        BOOT_LOG_ERR("Unable to determine flash sector of the image trailer");
     872:	4805      	ldr	r0, [pc, #20]	; (888 <__z_interrupt_stack_SIZEOF+0x8>)
     874:	2145      	movs	r1, #69	; 0x45
     876:	f008 fa2c 	bl	8cd2 <z_log_minimal_printk>
        return 0; /* Returning of zero here should cause any check which uses
     87a:	2000      	movs	r0, #0
#elif defined(MCUBOOT_DIRECT_XIP)
    return boot_swap_info_off(fap);
#elif defined(MCUBOOT_RAM_LOAD)
    return boot_swap_info_off(fap);
#endif
}
     87c:	b003      	add	sp, #12
     87e:	f85d fb04 	ldr.w	pc, [sp], #4
 */
uint8_t flash_area_erased_val(const struct flash_area *fap);

static inline uint32_t flash_sector_get_off(const struct flash_sector *fs)
{
	return fs->fs_off;
     882:	9800      	ldr	r0, [sp, #0]
    return flash_sector_get_off(&sector);
     884:	e7fa      	b.n	87c <bootutil_max_image_size+0x18>
     886:	bf00      	nop
     888:	0000a6c6 	.word	0x0000a6c6

0000088c <boot_validate_slot.isra.0>:
 *         FIH_SUCCESS                      if image was successfully validated
 *         1 (or its fih_int encoded form)  if no bootloable image was found
 *         FIH_FAILURE                      on any errors
 */
static fih_int
boot_validate_slot(struct boot_loader_state *state, int slot,
     88c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
                   struct boot_status *bs)
{
    const struct flash_area *fap;
    struct image_header *hdr;
    int area_id;
    fih_int fih_rc = FIH_FAILURE;
     890:	4b35      	ldr	r3, [pc, #212]	; (968 <FIH_LABEL_FIH_CALL_END_437+0x76>)
boot_validate_slot(struct boot_loader_state *state, int slot,
     892:	b088      	sub	sp, #32
     894:	4606      	mov	r6, r0
    int rc;

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     896:	2000      	movs	r0, #0
boot_validate_slot(struct boot_loader_state *state, int slot,
     898:	460c      	mov	r4, r1
    fih_int fih_rc = FIH_FAILURE;
     89a:	681d      	ldr	r5, [r3, #0]
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     89c:	f007 fdae 	bl	83fc <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     8a0:	a906      	add	r1, sp, #24
     8a2:	b2c0      	uxtb	r0, r0
     8a4:	f001 f898 	bl	19d8 <flash_area_open>
    if (rc != 0) {
     8a8:	2800      	cmp	r0, #0
     8aa:	d157      	bne.n	95c <FIH_LABEL_FIH_CALL_END_437+0x6a>
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     8ac:	4621      	mov	r1, r4
     8ae:	f007 fda5 	bl	83fc <flash_area_id_from_multi_image_slot>
     ((swap_type) == BOOT_SWAP_TYPE_PERM))

static inline struct image_header*
boot_img_hdr(struct boot_loader_state *state, size_t slot)
{
    return &BOOT_IMG(state, slot).hdr;
     8b2:	252c      	movs	r5, #44	; 0x2c
    rc = flash_area_open(area_id, &fap);
     8b4:	a907      	add	r1, sp, #28
     8b6:	b2c0      	uxtb	r0, r0
     8b8:	fb05 6504 	mla	r5, r5, r4, r6
     8bc:	f001 f88c 	bl	19d8 <flash_area_open>
    if (rc != 0) {
     8c0:	2800      	cmp	r0, #0
     8c2:	d033      	beq.n	92c <FIH_LABEL_FIH_CALL_END_437+0x3a>
        FIH_RET(fih_rc);
    }

    hdr = boot_img_hdr(state, slot);
    if (boot_check_header_erased(state, slot) == 0 ||
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     8c4:	272c      	movs	r7, #44	; 0x2c
     8c6:	4367      	muls	r7, r4
     8c8:	eb06 0807 	add.w	r8, r6, r7
#endif
    BOOT_HOOK_CALL_FIH(boot_image_check_hook, fih_int_encode(BOOT_HOOK_REGULAR),
                       fih_rc, BOOT_CURR_IMG(state), slot);
    if (fih_eq(fih_rc, fih_int_encode(BOOT_HOOK_REGULAR)))
    {
        FIH_CALL(boot_image_check, fih_rc, state, hdr, fap, bs);
     8cc:	9b06      	ldr	r3, [sp, #24]
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     8ce:	f8d8 1010 	ldr.w	r1, [r8, #16]
    if (boot_check_header_erased(state, slot) == 0 ||
     8d2:	f011 0110 	ands.w	r1, r1, #16
     8d6:	d138      	bne.n	94a <FIH_LABEL_FIH_CALL_END_437+0x58>

000008d8 <FIH_LABEL_FIH_CALL_START_388>:
    FIH_CALL(bootutil_img_validate, fih_rc, BOOT_CURR_ENC(state), image_index,
     8d8:	f44f 7280 	mov.w	r2, #256	; 0x100
     8dc:	9201      	str	r2, [sp, #4]
     8de:	4a23      	ldr	r2, [pc, #140]	; (96c <FIH_LABEL_FIH_CALL_END_437+0x7a>)
     8e0:	9200      	str	r2, [sp, #0]
     8e2:	e9cd 1103 	strd	r1, r1, [sp, #12]
     8e6:	462a      	mov	r2, r5
     8e8:	9102      	str	r1, [sp, #8]
     8ea:	4608      	mov	r0, r1
     8ec:	f7ff fdf0 	bl	4d0 <bootutil_img_validate>
     8f0:	4605      	mov	r5, r0

000008f2 <FIH_LABEL_FIH_CALL_END_437>:
    if (hdr->ih_magic != IMAGE_MAGIC) {
     8f2:	4b1f      	ldr	r3, [pc, #124]	; (970 <FIH_LABEL_FIH_CALL_END_437+0x7e>)
     8f4:	59f2      	ldr	r2, [r6, r7]
    }
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     8f6:	9806      	ldr	r0, [sp, #24]
    if (hdr->ih_magic != IMAGE_MAGIC) {
     8f8:	429a      	cmp	r2, r3
     8fa:	d10c      	bne.n	916 <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (!boot_u32_safe_add(&size, hdr->ih_img_size, hdr->ih_hdr_size)) {
     8fc:	f8d8 200c 	ldr.w	r2, [r8, #12]
     900:	f8b8 3008 	ldrh.w	r3, [r8, #8]
    if (a > UINT32_MAX - b) {
     904:	189b      	adds	r3, r3, r2
     906:	d206      	bcs.n	916 <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (size >= flash_area_get_size(fap)) {
     908:	6882      	ldr	r2, [r0, #8]
     90a:	4293      	cmp	r3, r2
     90c:	d203      	bcs.n	916 <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     90e:	4b19      	ldr	r3, [pc, #100]	; (974 <FIH_LABEL_FIH_CALL_END_437+0x82>)
     910:	681b      	ldr	r3, [r3, #0]
     912:	42ab      	cmp	r3, r5
     914:	d01f      	beq.n	956 <FIH_LABEL_FIH_CALL_END_437+0x64>
        if ((slot != BOOT_PRIMARY_SLOT) || ARE_SLOTS_EQUIVALENT()) {
     916:	b32c      	cbz	r4, 964 <FIH_LABEL_FIH_CALL_END_437+0x72>
            flash_area_erase(fap, 0, flash_area_get_size(fap));
     918:	6882      	ldr	r2, [r0, #8]
     91a:	2100      	movs	r1, #0
     91c:	f008 fa11 	bl	8d42 <flash_area_erase>
            /* Image is invalid, erase it to prevent further unnecessary
             * attempts to validate and boot it.
             */
        }
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     920:	4a15      	ldr	r2, [pc, #84]	; (978 <FIH_LABEL_FIH_CALL_END_437+0x86>)
     922:	4816      	ldr	r0, [pc, #88]	; (97c <FIH_LABEL_FIH_CALL_END_437+0x8a>)
     924:	2145      	movs	r1, #69	; 0x45
     926:	f008 f9d4 	bl	8cd2 <z_log_minimal_printk>
                     (slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
#endif
        fih_rc = fih_int_encode(1);
        goto out;
     92a:	e013      	b.n	954 <FIH_LABEL_FIH_CALL_END_437+0x62>
    erased_val = flash_area_erased_val(fap);
     92c:	9807      	ldr	r0, [sp, #28]
     92e:	f008 fa25 	bl	8d7c <flash_area_erased_val>
     932:	4607      	mov	r7, r0
    flash_area_close(fap);
     934:	9807      	ldr	r0, [sp, #28]
     936:	f008 f9d9 	bl	8cec <flash_area_close>
    for (i = 0; i < len; i++) {
     93a:	1e6b      	subs	r3, r5, #1
     93c:	1cea      	adds	r2, r5, #3
        if (val != p[i]) {
     93e:	f813 1f01 	ldrb.w	r1, [r3, #1]!
     942:	42b9      	cmp	r1, r7
     944:	d1be      	bne.n	8c4 <boot_validate_slot.isra.0+0x38>
    for (i = 0; i < len; i++) {
     946:	4293      	cmp	r3, r2
     948:	d1f9      	bne.n	93e <FIH_LABEL_FIH_CALL_END_437+0x4c>
        if (slot != BOOT_PRIMARY_SLOT) {
     94a:	b11c      	cbz	r4, 954 <FIH_LABEL_FIH_CALL_END_437+0x62>
            swap_erase_trailer_sectors(state, fap);
     94c:	9906      	ldr	r1, [sp, #24]
     94e:	4630      	mov	r0, r6
     950:	f007 ff1d 	bl	878e <swap_erase_trailer_sectors>
        fih_rc = fih_int_encode(1);
     954:	2501      	movs	r5, #1
        }
    }
#endif

out:
    flash_area_close(fap);
     956:	9806      	ldr	r0, [sp, #24]
     958:	f008 f9c8 	bl	8cec <flash_area_close>

    FIH_RET(fih_rc);
}
     95c:	4628      	mov	r0, r5
     95e:	b008      	add	sp, #32
     960:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     964:	4a06      	ldr	r2, [pc, #24]	; (980 <FIH_LABEL_FIH_CALL_END_437+0x8e>)
     966:	e7dc      	b.n	922 <FIH_LABEL_FIH_CALL_END_437+0x30>
     968:	20000000 	.word	0x20000000
     96c:	200021b8 	.word	0x200021b8
     970:	96f3b83d 	.word	0x96f3b83d
     974:	20000438 	.word	0x20000438
     978:	0000a709 	.word	0x0000a709
     97c:	0000a713 	.word	0x0000a713
     980:	0000a701 	.word	0x0000a701

00000984 <boot_swap_image>:
 *
 * @return                      0 on success; nonzero on failure.
 */
static int
boot_swap_image(struct boot_loader_state *state, struct boot_status *bs)
{
     984:	b573      	push	{r0, r1, r4, r5, r6, lr}
     986:	460d      	mov	r5, r1
     988:	4604      	mov	r4, r0
    uint8_t image_index;
    int rc;

    /* FIXME: just do this if asked by user? */

    size = copy_size = 0;
     98a:	2100      	movs	r1, #0
    image_index = BOOT_CURR_IMG(state);

    if (boot_status_is_reset(bs)) {
     98c:	4628      	mov	r0, r5
    size = copy_size = 0;
     98e:	e9cd 1100 	strd	r1, r1, [sp]
    if (boot_status_is_reset(bs)) {
     992:	f007 febb 	bl	870c <boot_status_is_reset>
     996:	b330      	cbz	r0, 9e6 <boot_swap_image+0x62>
        /*
         * No swap ever happened, so need to find the largest image which
         * will be used to determine the amount of sectors to swap.
         */
        hdr = boot_img_hdr(state, BOOT_PRIMARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     998:	4e16      	ldr	r6, [pc, #88]	; (9f4 <boot_swap_image+0x70>)
     99a:	6823      	ldr	r3, [r4, #0]
     99c:	42b3      	cmp	r3, r6
     99e:	d103      	bne.n	9a8 <boot_swap_image+0x24>
            rc = boot_read_image_size(state, BOOT_PRIMARY_SLOT, &copy_size);
     9a0:	aa01      	add	r2, sp, #4
     9a2:	4620      	mov	r0, r4
     9a4:	f007 fe46 	bl	8634 <boot_read_image_size.constprop.0.isra.0>
            memset(bs->enckey[0], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        hdr = boot_img_hdr(state, BOOT_SECONDARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     9a8:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     9aa:	42b3      	cmp	r3, r6
     9ac:	d104      	bne.n	9b8 <boot_swap_image+0x34>
            rc = boot_read_image_size(state, BOOT_SECONDARY_SLOT, &size);
     9ae:	466a      	mov	r2, sp
     9b0:	2101      	movs	r1, #1
     9b2:	4620      	mov	r0, r4
     9b4:	f007 fe3e 	bl	8634 <boot_read_image_size.constprop.0.isra.0>
        } else {
            memset(bs->enckey[1], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        if (size > copy_size) {
     9b8:	e9dd 3200 	ldrd	r3, r2, [sp]
     9bc:	4293      	cmp	r3, r2
            copy_size = size;
     9be:	bf88      	it	hi
     9c0:	9301      	strhi	r3, [sp, #4]
        }

        bs->swap_size = copy_size;
     9c2:	9b01      	ldr	r3, [sp, #4]
     9c4:	60ab      	str	r3, [r5, #8]
            }
        }
#endif
    }

    swap_run(state, bs, copy_size);
     9c6:	9a01      	ldr	r2, [sp, #4]
     9c8:	4629      	mov	r1, r5
     9ca:	4620      	mov	r0, r4
     9cc:	f000 fb36 	bl	103c <swap_run>

#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
    extern int boot_status_fails;
    if (boot_status_fails > 0) {
     9d0:	4b09      	ldr	r3, [pc, #36]	; (9f8 <boot_swap_image+0x74>)
     9d2:	681a      	ldr	r2, [r3, #0]
     9d4:	2a00      	cmp	r2, #0
     9d6:	dd03      	ble.n	9e0 <boot_swap_image+0x5c>
        BOOT_LOG_WRN("%d status write fails performing the swap",
     9d8:	4808      	ldr	r0, [pc, #32]	; (9fc <boot_swap_image+0x78>)
     9da:	2157      	movs	r1, #87	; 0x57
     9dc:	f008 f979 	bl	8cd2 <z_log_minimal_printk>
#endif
    rc = BOOT_HOOK_CALL(boot_copy_region_post_hook, 0, BOOT_CURR_IMG(state),
                        BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT), size);

    return 0;
}
     9e0:	2000      	movs	r0, #0
     9e2:	b002      	add	sp, #8
     9e4:	bd70      	pop	{r4, r5, r6, pc}
        rc = boot_read_swap_size(image_index, &bs->swap_size);
     9e6:	f105 0108 	add.w	r1, r5, #8
     9ea:	f7ff fefd 	bl	7e8 <boot_read_swap_size>
        copy_size = bs->swap_size;
     9ee:	68ab      	ldr	r3, [r5, #8]
     9f0:	9301      	str	r3, [sp, #4]
     9f2:	e7e8      	b.n	9c6 <boot_swap_image+0x42>
     9f4:	96f3b83d 	.word	0x96f3b83d
     9f8:	2000189c 	.word	0x2000189c
     9fc:	0000a73b 	.word	0x0000a73b

00000a00 <boot_copy_region>:
{
     a00:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     a04:	f8df b078 	ldr.w	fp, [pc, #120]	; a80 <boot_copy_region+0x80>
     a08:	4c1b      	ldr	r4, [pc, #108]	; (a78 <boot_copy_region+0x78>)
     a0a:	4d1c      	ldr	r5, [pc, #112]	; (a7c <boot_copy_region+0x7c>)
{
     a0c:	4688      	mov	r8, r1
     a0e:	4691      	mov	r9, r2
     a10:	469a      	mov	sl, r3
    bytes_copied = 0;
     a12:	2600      	movs	r6, #0
    while (bytes_copied < sz) {
     a14:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
     a16:	429e      	cmp	r6, r3
     a18:	d301      	bcc.n	a1e <boot_copy_region+0x1e>
    return 0;
     a1a:	2000      	movs	r0, #0
     a1c:	e00f      	b.n	a3e <boot_copy_region+0x3e>
        if (sz - bytes_copied > sizeof buf) {
     a1e:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     a20:	4a17      	ldr	r2, [pc, #92]	; (a80 <boot_copy_region+0x80>)
        if (sz - bytes_copied > sizeof buf) {
     a22:	1b9f      	subs	r7, r3, r6
     a24:	f5b7 6f80 	cmp.w	r7, #1024	; 0x400
     a28:	bf28      	it	cs
     a2a:	f44f 6780 	movcs.w	r7, #1024	; 0x400
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     a2e:	463b      	mov	r3, r7
     a30:	eb06 010a 	add.w	r1, r6, sl
     a34:	4640      	mov	r0, r8
     a36:	f008 f95a 	bl	8cee <flash_area_read>
        if (rc != 0) {
     a3a:	b110      	cbz	r0, a42 <boot_copy_region+0x42>
            return BOOT_EFLASH;
     a3c:	2001      	movs	r0, #1
}
     a3e:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_write(fap_dst, off_dst + bytes_copied, buf, chunk_sz);
     a42:	990a      	ldr	r1, [sp, #40]	; 0x28
     a44:	463b      	mov	r3, r7
     a46:	465a      	mov	r2, fp
     a48:	1871      	adds	r1, r6, r1
     a4a:	4648      	mov	r0, r9
     a4c:	f008 f964 	bl	8d18 <flash_area_write>
        if (rc != 0) {
     a50:	2800      	cmp	r0, #0
     a52:	d1f3      	bne.n	a3c <boot_copy_region+0x3c>
     a54:	f8c4 5600 	str.w	r5, [r4, #1536]	; 0x600
        bytes_copied += chunk_sz;
     a58:	443e      	add	r6, r7
     a5a:	f8c4 5604 	str.w	r5, [r4, #1540]	; 0x604
     a5e:	f8c4 5608 	str.w	r5, [r4, #1544]	; 0x608
     a62:	f8c4 560c 	str.w	r5, [r4, #1548]	; 0x60c
     a66:	f8c4 5610 	str.w	r5, [r4, #1552]	; 0x610
     a6a:	f8c4 5614 	str.w	r5, [r4, #1556]	; 0x614
     a6e:	f8c4 5618 	str.w	r5, [r4, #1560]	; 0x618
     a72:	f8c4 561c 	str.w	r5, [r4, #1564]	; 0x61c
        MCUBOOT_WATCHDOG_FEED();
     a76:	e7cd      	b.n	a14 <boot_copy_region+0x14>
     a78:	40010000 	.word	0x40010000
     a7c:	6e524635 	.word	0x6e524635
     a80:	2000143c 	.word	0x2000143c

00000a84 <context_boot_go>:
#endif
}

fih_int
context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
{
     a84:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
        boot_enc_zeroize(BOOT_CURR_ENC(state));
#endif

        image_index = BOOT_CURR_IMG(state);

        BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors =
     a88:	4b8f      	ldr	r3, [pc, #572]	; (cc8 <FIH_LABEL_FIH_CALL_END_2278+0x40>)
     a8a:	6243      	str	r3, [r0, #36]	; 0x24
{
     a8c:	460e      	mov	r6, r1
            primary_slot_sectors[image_index];
        BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors =
     a8e:	4b8f      	ldr	r3, [pc, #572]	; (ccc <FIH_LABEL_FIH_CALL_END_2278+0x44>)
     a90:	6503      	str	r3, [r0, #80]	; 0x50

        /* Open primary and secondary image areas for the duration
         * of this call.
         */
        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     a92:	2100      	movs	r1, #0
{
     a94:	4604      	mov	r4, r0
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     a96:	4608      	mov	r0, r1
     a98:	f007 fcb0 	bl	83fc <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     a9c:	f104 0120 	add.w	r1, r4, #32
     aa0:	b2c0      	uxtb	r0, r0
     aa2:	f000 ff99 	bl	19d8 <flash_area_open>
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     aa6:	2101      	movs	r1, #1
     aa8:	2000      	movs	r0, #0
     aaa:	f007 fca7 	bl	83fc <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     aae:	f104 014c 	add.w	r1, r4, #76	; 0x4c
     ab2:	b2c0      	uxtb	r0, r0
     ab4:	f000 ff90 	bl	19d8 <flash_area_open>
     ab8:	4605      	mov	r5, r0
    rc = boot_read_sectors(state);
     aba:	4620      	mov	r0, r4
     abc:	f007 fdfb 	bl	86b6 <boot_read_sectors>
    if (rc != 0) {
     ac0:	4607      	mov	r7, r0
     ac2:	b968      	cbnz	r0, ae0 <context_boot_go+0x5c>
    rc = boot_read_image_headers(state, false, NULL);
     ac4:	2200      	movs	r2, #0
     ac6:	4611      	mov	r1, r2
     ac8:	4620      	mov	r0, r4
     aca:	f007 fd9d 	bl	8608 <boot_read_image_headers>
    if (rc != 0) {
     ace:	4607      	mov	r7, r0
     ad0:	b308      	cbz	r0, b16 <context_boot_go+0x92>
        BOOT_LOG_WRN("Failed reading image headers; Image=%u",
     ad2:	487f      	ldr	r0, [pc, #508]	; (cd0 <FIH_LABEL_FIH_CALL_END_2278+0x48>)
     ad4:	2200      	movs	r2, #0
     ad6:	2157      	movs	r1, #87	; 0x57
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     ad8:	f008 f8fb 	bl	8cd2 <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     adc:	2301      	movs	r3, #1
     ade:	e090      	b.n	c02 <FIH_LABEL_FIH_CALL_END_2027+0xe>
        BOOT_LOG_WRN("Failed reading sectors; BOOT_MAX_IMG_SECTORS=%d"
     ae0:	487c      	ldr	r0, [pc, #496]	; (cd4 <FIH_LABEL_FIH_CALL_END_2278+0x4c>)
     ae2:	f44f 7280 	mov.w	r2, #256	; 0x100
     ae6:	2157      	movs	r1, #87	; 0x57
     ae8:	f008 f8f3 	bl	8cd2 <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     aec:	2301      	movs	r3, #1
        if (rc == BOOT_EFLASH)
     aee:	429f      	cmp	r7, r3
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     af0:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        if (rc == BOOT_EFLASH)
     af4:	d1e6      	bne.n	ac4 <context_boot_go+0x40>
#endif

        /* Determine swap type and complete swap if it has been aborted. */
        boot_prepare_image_for_update(state, &bs);

        if (BOOT_IS_UPGRADE(BOOT_SWAP_TYPE(state))) {
     af6:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
        /* Indicate that swap is not aborted */
        boot_status_reset(&bs);
#endif /* (BOOT_IMAGE_NUMBER > 1) */

        /* Set the previously determined swap type */
        bs.swap_type = BOOT_SWAP_TYPE(state);
     afa:	f88d 3007 	strb.w	r3, [sp, #7]

        switch (BOOT_SWAP_TYPE(state)) {
     afe:	2b04      	cmp	r3, #4
     b00:	f200 8082 	bhi.w	c08 <FIH_LABEL_FIH_CALL_END_2027+0x14>
     b04:	2b01      	cmp	r3, #1
     b06:	f200 8085 	bhi.w	c14 <FIH_LABEL_FIH_CALL_END_2027+0x20>
     b0a:	f000 809c 	beq.w	c46 <FIH_LABEL_FIH_CALL_END_2027+0x52>
            }
#endif /* !MCUBOOT_OVERWRITE_ONLY */
            break;

        default:
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b0e:	23ff      	movs	r3, #255	; 0xff
     b10:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     b14:	e097      	b.n	c46 <FIH_LABEL_FIH_CALL_END_2027+0x52>
    if (boot_slots_compatible(state)) {
     b16:	4620      	mov	r0, r4
     b18:	f000 f9a6 	bl	e68 <boot_slots_compatible>
     b1c:	2800      	cmp	r0, #0
     b1e:	d0dd      	beq.n	adc <context_boot_go+0x58>
        boot_status_reset(bs);
     b20:	4668      	mov	r0, sp
     b22:	f007 fdea 	bl	86fa <boot_status_reset>
        rc = swap_read_status(state, bs);
     b26:	4669      	mov	r1, sp
     b28:	4620      	mov	r0, r4
     b2a:	f007 fe85 	bl	8838 <swap_read_status>
        if (rc != 0) {
     b2e:	b118      	cbz	r0, b38 <context_boot_go+0xb4>
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     b30:	4869      	ldr	r0, [pc, #420]	; (cd8 <FIH_LABEL_FIH_CALL_END_2278+0x50>)
     b32:	463a      	mov	r2, r7
     b34:	2157      	movs	r1, #87	; 0x57
     b36:	e7cf      	b.n	ad8 <context_boot_go+0x54>
        rc = boot_read_image_headers(state, !boot_status_is_reset(bs), bs);
     b38:	4668      	mov	r0, sp
     b3a:	f007 fde7 	bl	870c <boot_status_is_reset>
     b3e:	f080 0101 	eor.w	r1, r0, #1
     b42:	466a      	mov	r2, sp
     b44:	b2c9      	uxtb	r1, r1
     b46:	4620      	mov	r0, r4
     b48:	f007 fd5e 	bl	8608 <boot_read_image_headers>
        if (rc != 0) {
     b4c:	4602      	mov	r2, r0
     b4e:	2800      	cmp	r0, #0
     b50:	d1bf      	bne.n	ad2 <context_boot_go+0x4e>
        if (!boot_status_is_reset(bs)) {
     b52:	4668      	mov	r0, sp
     b54:	f007 fdda 	bl	870c <boot_status_is_reset>
     b58:	4607      	mov	r7, r0
     b5a:	bb60      	cbnz	r0, bb6 <context_boot_go+0x132>
    rc = boot_swap_image(state, bs);
     b5c:	4669      	mov	r1, sp
     b5e:	4620      	mov	r0, r4
     b60:	f7ff ff10 	bl	984 <boot_swap_image>
    BOOT_SWAP_TYPE(state) = bs->swap_type;
     b64:	f89d 3007 	ldrb.w	r3, [sp, #7]
     b68:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (bs->swap_type == BOOT_SWAP_TYPE_REVERT ||
     b6c:	3b03      	subs	r3, #3
     b6e:	2b01      	cmp	r3, #1
     b70:	d806      	bhi.n	b80 <context_boot_go+0xfc>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     b72:	4638      	mov	r0, r7
     b74:	f007 feaf 	bl	88d6 <swap_set_image_ok>
        if (rc != 0) {
     b78:	b110      	cbz	r0, b80 <context_boot_go+0xfc>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b7a:	23ff      	movs	r3, #255	; 0xff
     b7c:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (BOOT_IS_UPGRADE(bs->swap_type)) {
     b80:	f89d 3007 	ldrb.w	r3, [sp, #7]
     b84:	3b02      	subs	r3, #2
     b86:	2b02      	cmp	r3, #2
     b88:	d80b      	bhi.n	ba2 <context_boot_go+0x11e>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     b8a:	2000      	movs	r0, #0
     b8c:	f007 fe91 	bl	88b2 <swap_set_copy_done>
        if (rc != 0) {
     b90:	b138      	cbz	r0, ba2 <context_boot_go+0x11e>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b92:	23ff      	movs	r3, #255	; 0xff
     b94:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        BOOT_LOG_ERR("panic!");
     b98:	4850      	ldr	r0, [pc, #320]	; (cdc <FIH_LABEL_FIH_CALL_END_2278+0x54>)
     b9a:	2145      	movs	r1, #69	; 0x45
     b9c:	f008 f899 	bl	8cd2 <z_log_minimal_printk>
        while (1) {}
     ba0:	e7fe      	b.n	ba0 <context_boot_go+0x11c>
    if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     ba2:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     ba6:	2bff      	cmp	r3, #255	; 0xff
     ba8:	d0f6      	beq.n	b98 <context_boot_go+0x114>
            rc = boot_read_image_headers(state, false, bs);
     baa:	466a      	mov	r2, sp
     bac:	2100      	movs	r1, #0
     bae:	4620      	mov	r0, r4
     bb0:	f007 fd2a 	bl	8608 <boot_read_image_headers>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     bb4:	e792      	b.n	adc <context_boot_go+0x58>
            if (bs->swap_type == BOOT_SWAP_TYPE_NONE) {
     bb6:	f89d 8007 	ldrb.w	r8, [sp, #7]
     bba:	f1b8 0f01 	cmp.w	r8, #1
     bbe:	d115      	bne.n	bec <FIH_LABEL_FIH_CALL_START_2012>
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     bc0:	4610      	mov	r0, r2
     bc2:	f003 fe75 	bl	48b0 <boot_swap_type_multi>
    if (BOOT_IS_UPGRADE(swap_type)) {
     bc6:	1e83      	subs	r3, r0, #2
     bc8:	2b02      	cmp	r3, #2
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     bca:	4607      	mov	r7, r0
    if (BOOT_IS_UPGRADE(swap_type)) {
     bcc:	d80b      	bhi.n	be6 <FIH_LABEL_FIH_CALL_END_1976+0x10>

00000bce <FIH_LABEL_FIH_CALL_START_1961>:
        FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_SECONDARY_SLOT, bs);
     bce:	4641      	mov	r1, r8
     bd0:	4620      	mov	r0, r4
     bd2:	f7ff fe5b 	bl	88c <boot_validate_slot.isra.0>

00000bd6 <FIH_LABEL_FIH_CALL_END_1976>:
        if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     bd6:	4b42      	ldr	r3, [pc, #264]	; (ce0 <FIH_LABEL_FIH_CALL_END_2278+0x58>)
     bd8:	681b      	ldr	r3, [r3, #0]
     bda:	4298      	cmp	r0, r3
     bdc:	d003      	beq.n	be6 <FIH_LABEL_FIH_CALL_END_1976+0x10>
                swap_type = BOOT_SWAP_TYPE_NONE;
     bde:	2801      	cmp	r0, #1
     be0:	bf14      	ite	ne
     be2:	2705      	movne	r7, #5
     be4:	2701      	moveq	r7, #1
                BOOT_SWAP_TYPE(state) = boot_validated_swap_type(state, bs);
     be6:	f884 7058 	strb.w	r7, [r4, #88]	; 0x58
     bea:	e784      	b.n	af6 <context_boot_go+0x72>

00000bec <FIH_LABEL_FIH_CALL_START_2012>:
                FIH_CALL(boot_validate_slot, fih_rc,
     bec:	2101      	movs	r1, #1
     bee:	4620      	mov	r0, r4
     bf0:	f7ff fe4c 	bl	88c <boot_validate_slot.isra.0>

00000bf4 <FIH_LABEL_FIH_CALL_END_2027>:
                if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     bf4:	4b3a      	ldr	r3, [pc, #232]	; (ce0 <FIH_LABEL_FIH_CALL_END_2278+0x58>)
     bf6:	681b      	ldr	r3, [r3, #0]
     bf8:	4298      	cmp	r0, r3
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     bfa:	bf0c      	ite	eq
     bfc:	f89d 3007 	ldrbeq.w	r3, [sp, #7]
                    BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
     c00:	2305      	movne	r3, #5
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     c02:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     c06:	e776      	b.n	af6 <context_boot_go+0x72>
        switch (BOOT_SWAP_TYPE(state)) {
     c08:	2b05      	cmp	r3, #5
     c0a:	d180      	bne.n	b0e <context_boot_go+0x8a>
            rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     c0c:	2000      	movs	r0, #0
     c0e:	f007 fe62 	bl	88d6 <swap_set_image_ok>
     c12:	e013      	b.n	c3c <FIH_LABEL_FIH_CALL_END_2027+0x48>
        rc = boot_swap_image(state, bs);
     c14:	4669      	mov	r1, sp
     c16:	4620      	mov	r0, r4
     c18:	f7ff feb4 	bl	984 <boot_swap_image>
    swap_type = BOOT_SWAP_TYPE(state);
     c1c:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     c20:	1eda      	subs	r2, r3, #3
     c22:	2a01      	cmp	r2, #1
        rc = boot_swap_image(state, bs);
     c24:	4605      	mov	r5, r0
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     c26:	d80c      	bhi.n	c42 <FIH_LABEL_FIH_CALL_END_2027+0x4e>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     c28:	2000      	movs	r0, #0
     c2a:	f007 fe54 	bl	88d6 <swap_set_image_ok>
        if (rc != 0) {
     c2e:	4605      	mov	r5, r0
     c30:	2800      	cmp	r0, #0
     c32:	f47f af6c 	bne.w	b0e <context_boot_go+0x8a>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     c36:	2000      	movs	r0, #0
     c38:	f007 fe3b 	bl	88b2 <swap_set_copy_done>
            if (rc != 0) {
     c3c:	4605      	mov	r5, r0
     c3e:	b110      	cbz	r0, c46 <FIH_LABEL_FIH_CALL_END_2027+0x52>
     c40:	e765      	b.n	b0e <context_boot_go+0x8a>
    if (BOOT_IS_UPGRADE(swap_type)) {
     c42:	2b02      	cmp	r3, #2
     c44:	d0f7      	beq.n	c36 <FIH_LABEL_FIH_CALL_END_2027+0x42>
        }

        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     c46:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     c4a:	2bff      	cmp	r3, #255	; 0xff
     c4c:	d104      	bne.n	c58 <FIH_LABEL_FIH_CALL_END_2027+0x64>
            BOOT_LOG_ERR("panic!");
     c4e:	4823      	ldr	r0, [pc, #140]	; (cdc <FIH_LABEL_FIH_CALL_END_2278+0x54>)
     c50:	2145      	movs	r1, #69	; 0x45
     c52:	f008 f83e 	bl	8cd2 <z_log_minimal_printk>
            assert(0);

            /* Loop forever... */
            FIH_PANIC;
     c56:	e7fe      	b.n	c56 <FIH_LABEL_FIH_CALL_END_2027+0x62>
#if BOOT_IMAGE_NUMBER > 1
        if (state->img_mask[BOOT_CURR_IMG(state)]) {
            continue;
        }
#endif
        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE) {
     c58:	2b01      	cmp	r3, #1
     c5a:	d010      	beq.n	c7e <FIH_LABEL_FIH_CALL_START_2263>
            /* Attempt to read an image header from each slot. Ensure that image
             * headers in slots are aligned with headers in boot_data.
             */
            rc = boot_read_image_headers(state, false, &bs);
     c5c:	466a      	mov	r2, sp
     c5e:	2100      	movs	r1, #0
     c60:	4620      	mov	r0, r4
     c62:	f007 fcd1 	bl	8608 <boot_read_image_headers>
            if (rc != 0) {
     c66:	4605      	mov	r5, r0
     c68:	b148      	cbz	r0, c7e <FIH_LABEL_FIH_CALL_START_2263>
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     c6a:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     c6c:	f008 f83e 	bl	8cec <flash_area_close>
     c70:	6a20      	ldr	r0, [r4, #32]
     c72:	f008 f83b 	bl	8cec <flash_area_close>
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     c76:	4628      	mov	r0, r5
     c78:	b004      	add	sp, #16
     c7a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00000c7e <FIH_LABEL_FIH_CALL_START_2263>:
            FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_PRIMARY_SLOT, NULL);
     c7e:	2100      	movs	r1, #0
     c80:	4620      	mov	r0, r4
     c82:	f7ff fe03 	bl	88c <boot_validate_slot.isra.0>
     c86:	4607      	mov	r7, r0

00000c88 <FIH_LABEL_FIH_CALL_END_2278>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     c88:	f8df 8054 	ldr.w	r8, [pc, #84]	; ce0 <FIH_LABEL_FIH_CALL_END_2278+0x58>
     c8c:	f8d8 3000 	ldr.w	r3, [r8]
     c90:	4298      	cmp	r0, r3
     c92:	d10f      	bne.n	cb4 <FIH_LABEL_FIH_CALL_END_2278+0x2c>
    memset(&bs, 0, sizeof(struct boot_status));
     c94:	2210      	movs	r2, #16
     c96:	2100      	movs	r1, #0
     c98:	4668      	mov	r0, sp
     c9a:	f008 f8d7 	bl	8e4c <memset>
    rsp->br_flash_dev_id = flash_area_get_device_id(BOOT_IMG_AREA(state, active_slot));
     c9e:	6a20      	ldr	r0, [r4, #32]
     ca0:	f007 fbb6 	bl	8410 <flash_area_get_device_id>
     ca4:	7130      	strb	r0, [r6, #4]
	return (uint32_t)fa->fa_off;
     ca6:	6a23      	ldr	r3, [r4, #32]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     ca8:	685b      	ldr	r3, [r3, #4]
    rsp->br_hdr = boot_img_hdr(state, active_slot);
     caa:	6034      	str	r4, [r6, #0]
    fih_rc = FIH_SUCCESS;
     cac:	f8d8 5000 	ldr.w	r5, [r8]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     cb0:	60b3      	str	r3, [r6, #8]
    fih_rc = FIH_SUCCESS;
     cb2:	e7da      	b.n	c6a <FIH_LABEL_FIH_CALL_END_2027+0x76>
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     cb4:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     cb6:	f008 f819 	bl	8cec <flash_area_close>
     cba:	6a20      	ldr	r0, [r4, #32]
     cbc:	f008 f816 	bl	8cec <flash_area_close>
    if (rc) {
     cc0:	2d00      	cmp	r5, #0
     cc2:	bf08      	it	eq
     cc4:	463d      	moveq	r5, r7
     cc6:	e7d6      	b.n	c76 <FIH_LABEL_FIH_CALL_END_2027+0x82>
     cc8:	20000c3c 	.word	0x20000c3c
     ccc:	2000043c 	.word	0x2000043c
     cd0:	0000a7ac 	.word	0x0000a7ac
     cd4:	0000a76a 	.word	0x0000a76a
     cd8:	0000a7d8 	.word	0x0000a7d8
     cdc:	0000a802 	.word	0x0000a802
     ce0:	20000438 	.word	0x20000438

00000ce4 <boot_go>:
 *
 * @return                      FIH_SUCCESS on success; nonzero on failure.
 */
fih_int
boot_go(struct boot_rsp *rsp)
{
     ce4:	b538      	push	{r3, r4, r5, lr}
void boot_state_clear(struct boot_loader_state *state)
{
    if (state != NULL) {
        memset(state, 0, sizeof(struct boot_loader_state));
    } else {
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     ce6:	4d06      	ldr	r5, [pc, #24]	; (d00 <FIH_LABEL_FIH_CALL_END_2900+0x4>)
{
     ce8:	4604      	mov	r4, r0
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     cea:	2260      	movs	r2, #96	; 0x60
     cec:	2100      	movs	r1, #0
     cee:	4628      	mov	r0, r5
     cf0:	f008 f8ac 	bl	8e4c <memset>

00000cf4 <FIH_LABEL_FIH_CALL_START_2886>:
    FIH_CALL(context_boot_go, fih_rc, &boot_data, rsp);
     cf4:	4621      	mov	r1, r4
     cf6:	4628      	mov	r0, r5
     cf8:	f7ff fec4 	bl	a84 <context_boot_go>

00000cfc <FIH_LABEL_FIH_CALL_END_2900>:
}
     cfc:	bd38      	pop	{r3, r4, r5, pc}
     cfe:	bf00      	nop
     d00:	2000183c 	.word	0x2000183c

00000d04 <boot_read_image_header>:
static uint32_t g_last_idx = UINT32_MAX;

int
boot_read_image_header(struct boot_loader_state *state, int slot,
                       struct image_header *out_hdr, struct boot_status *bs)
{
     d04:	b573      	push	{r0, r1, r4, r5, r6, lr}
     d06:	4616      	mov	r6, r2
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    off = 0;
    if (bs) {
     d08:	461d      	mov	r5, r3
     d0a:	b143      	cbz	r3, d1e <boot_read_image_header+0x1a>
        sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
        if (bs->op == BOOT_STATUS_OP_MOVE) {
     d0c:	795b      	ldrb	r3, [r3, #5]
     d0e:	2b01      	cmp	r3, #1
     d10:	d107      	bne.n	d22 <boot_read_image_header+0x1e>
            if (slot == 0 && bs->idx > g_last_idx) {
     d12:	b921      	cbnz	r1, d1e <boot_read_image_header+0x1a>
     d14:	4b20      	ldr	r3, [pc, #128]	; (d98 <boot_read_image_header+0x94>)
     d16:	682a      	ldr	r2, [r5, #0]
     d18:	681b      	ldr	r3, [r3, #0]
     d1a:	429a      	cmp	r2, r3
     d1c:	d817      	bhi.n	d4e <boot_read_image_header+0x4a>
    off = 0;
     d1e:	2400      	movs	r4, #0
     d20:	e018      	b.n	d54 <boot_read_image_header+0x50>
                /* second sector */
                off = sz;
            }
        } else if (bs->op == BOOT_STATUS_OP_SWAP) {
     d22:	2b02      	cmp	r3, #2
     d24:	d1fb      	bne.n	d1e <boot_read_image_header+0x1a>
            if (bs->idx > 1 && bs->idx <= g_last_idx) {
     d26:	682b      	ldr	r3, [r5, #0]
     d28:	2b01      	cmp	r3, #1
     d2a:	d907      	bls.n	d3c <boot_read_image_header+0x38>
     d2c:	4a1a      	ldr	r2, [pc, #104]	; (d98 <boot_read_image_header+0x94>)
     d2e:	6812      	ldr	r2, [r2, #0]
     d30:	4293      	cmp	r3, r2
     d32:	d8f4      	bhi.n	d1e <boot_read_image_header+0x1a>
                if (slot == 0) {
     d34:	fab1 f181 	clz	r1, r1
     d38:	0949      	lsrs	r1, r1, #5
     d3a:	e7f0      	b.n	d1e <boot_read_image_header+0x1a>
                    slot = 1;
                } else {
                    slot = 0;
                }
            } else if (bs->idx == 1) {
     d3c:	d1ef      	bne.n	d1e <boot_read_image_header+0x1a>
                if (slot == 0) {
     d3e:	b131      	cbz	r1, d4e <boot_read_image_header+0x4a>
                    off = sz;
                }
                if (slot == 1 && bs->state == 2) {
     d40:	2901      	cmp	r1, #1
     d42:	d1ec      	bne.n	d1e <boot_read_image_header+0x1a>
     d44:	7929      	ldrb	r1, [r5, #4]
     d46:	3902      	subs	r1, #2
     d48:	bf18      	it	ne
     d4a:	2101      	movne	r1, #1
     d4c:	e7e7      	b.n	d1e <boot_read_image_header+0x1a>
}

static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
{
	return fs->fs_size;
     d4e:	6a43      	ldr	r3, [r0, #36]	; 0x24
     d50:	685c      	ldr	r4, [r3, #4]
     d52:	2100      	movs	r1, #0
                }
            }
        }
    }

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     d54:	2000      	movs	r0, #0
     d56:	f007 fb51 	bl	83fc <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     d5a:	a901      	add	r1, sp, #4
     d5c:	b2c0      	uxtb	r0, r0
     d5e:	f000 fe3b 	bl	19d8 <flash_area_open>
    if (rc != 0) {
     d62:	b130      	cbz	r0, d72 <boot_read_image_header+0x6e>
        rc = BOOT_EFLASH;
     d64:	2401      	movs	r4, #1
    }

    rc = 0;

done:
    flash_area_close(fap);
     d66:	9801      	ldr	r0, [sp, #4]
     d68:	f007 ffc0 	bl	8cec <flash_area_close>
    return rc;
}
     d6c:	4620      	mov	r0, r4
     d6e:	b002      	add	sp, #8
     d70:	bd70      	pop	{r4, r5, r6, pc}
    rc = flash_area_read(fap, off, out_hdr, sizeof *out_hdr);
     d72:	4621      	mov	r1, r4
     d74:	9801      	ldr	r0, [sp, #4]
     d76:	2320      	movs	r3, #32
     d78:	4632      	mov	r2, r6
     d7a:	f007 ffb8 	bl	8cee <flash_area_read>
    if (rc != 0) {
     d7e:	4604      	mov	r4, r0
     d80:	2800      	cmp	r0, #0
     d82:	d1ef      	bne.n	d64 <boot_read_image_header+0x60>
    if (bs != NULL && out_hdr->ih_magic != IMAGE_MAGIC) {
     d84:	2d00      	cmp	r5, #0
     d86:	d0ee      	beq.n	d66 <boot_read_image_header+0x62>
     d88:	6834      	ldr	r4, [r6, #0]
     d8a:	4b04      	ldr	r3, [pc, #16]	; (d9c <boot_read_image_header+0x98>)
     d8c:	1ae4      	subs	r4, r4, r3
     d8e:	bf18      	it	ne
     d90:	f04f 34ff 	movne.w	r4, #4294967295
     d94:	e7e7      	b.n	d66 <boot_read_image_header+0x62>
     d96:	bf00      	nop
     d98:	20000004 	.word	0x20000004
     d9c:	96f3b83d 	.word	0x96f3b83d

00000da0 <swap_read_status_bytes>:

int
swap_read_status_bytes(const struct flash_area *fap,
        struct boot_loader_state *state, struct boot_status *bs)
{
     da0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     da4:	4607      	mov	r7, r0
     da6:	b085      	sub	sp, #20
     da8:	460c      	mov	r4, r1
    int rc;
    int last_rc;
    int erased_sections;
    int i;

    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     daa:	4601      	mov	r1, r0
     dac:	2000      	movs	r0, #0
{
     dae:	4616      	mov	r6, r2
    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     db0:	f007 fbfe 	bl	85b0 <boot_status_entries>
    if (max_entries < 0) {
     db4:	1e05      	subs	r5, r0, #0
     db6:	db51      	blt.n	e5c <swap_read_status_bytes+0xbc>
    erased_sections = 0;
    found_idx = -1;
    /* skip erased sectors at the end */
    last_rc = 1;
    write_sz = BOOT_WRITE_SZ(state);
    off = boot_status_off(fap);
     db8:	4638      	mov	r0, r7
    write_sz = BOOT_WRITE_SZ(state);
     dba:	6de4      	ldr	r4, [r4, #92]	; 0x5c
    off = boot_status_off(fap);
     dbc:	f007 fc02 	bl	85c4 <boot_status_off>
    for (i = max_entries; i > 0; i--) {
     dc0:	fa5f f984 	uxtb.w	r9, r4
     dc4:	1e6b      	subs	r3, r5, #1
     dc6:	fb09 0803 	mla	r8, r9, r3, r0
    erased_sections = 0;
     dca:	f04f 0a00 	mov.w	sl, #0
    last_rc = 1;
     dce:	f04f 0b01 	mov.w	fp, #1
    found_idx = -1;
     dd2:	f04f 34ff 	mov.w	r4, #4294967295
    for (i = max_entries; i > 0; i--) {
     dd6:	b99d      	cbnz	r5, e00 <swap_read_status_bytes+0x60>
            }
        }
        last_rc = rc;
    }

    if (erased_sections > 1) {
     dd8:	f1ba 0f01 	cmp.w	sl, #1
     ddc:	dd03      	ble.n	de6 <swap_read_status_bytes+0x46>
        /* This means there was an error writing status on the last
         * swap. Tell user and move on to validation!
         */
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Detected inconsistent status!");
     dde:	4821      	ldr	r0, [pc, #132]	; (e64 <swap_read_status_bytes+0xc4>)
     de0:	2145      	movs	r1, #69	; 0x45
     de2:	f007 ff76 	bl	8cd2 <z_log_minimal_printk>
        assert(0);
#endif
    }

    move_entries = BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT;
    if (found_idx == -1) {
     de6:	1c63      	adds	r3, r4, #1
     de8:	d006      	beq.n	df8 <swap_read_status_bytes+0x58>
        /* no swap status found; nothing to do */
    } else if (found_idx < move_entries) {
     dea:	2cff      	cmp	r4, #255	; 0xff
     dec:	dc2a      	bgt.n	e44 <swap_read_status_bytes+0xa4>
        bs->op = BOOT_STATUS_OP_MOVE;
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     dee:	3401      	adds	r4, #1
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     df0:	f240 1301 	movw	r3, #257	; 0x101
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     df4:	6034      	str	r4, [r6, #0]
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     df6:	80b3      	strh	r3, [r6, #4]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    }

    return 0;
}
     df8:	4628      	mov	r0, r5
     dfa:	b005      	add	sp, #20
     dfc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_read(fap, off + (i - 1) * write_sz, &status, 1);
     e00:	1e6b      	subs	r3, r5, #1
     e02:	9300      	str	r3, [sp, #0]
     e04:	f10d 020f 	add.w	r2, sp, #15
     e08:	2301      	movs	r3, #1
     e0a:	4641      	mov	r1, r8
     e0c:	4638      	mov	r0, r7
     e0e:	f007 ff6e 	bl	8cee <flash_area_read>
        if (rc < 0) {
     e12:	1e03      	subs	r3, r0, #0
     e14:	9301      	str	r3, [sp, #4]
     e16:	db23      	blt.n	e60 <swap_read_status_bytes+0xc0>
        if (bootutil_buffer_is_erased(fap, &status, 1)) {
     e18:	2201      	movs	r2, #1
     e1a:	f10d 010f 	add.w	r1, sp, #15
     e1e:	4638      	mov	r0, r7
     e20:	f008 fc29 	bl	9676 <bootutil_buffer_is_erased>
     e24:	9b01      	ldr	r3, [sp, #4]
     e26:	b140      	cbz	r0, e3a <swap_read_status_bytes+0x9a>
            if (rc != last_rc) {
     e28:	455b      	cmp	r3, fp
     e2a:	d001      	beq.n	e30 <swap_read_status_bytes+0x90>
                erased_sections++;
     e2c:	f10a 0a01 	add.w	sl, sl, #1
            if (found_idx == -1) {
     e30:	9d00      	ldr	r5, [sp, #0]
     e32:	eba8 0809 	sub.w	r8, r8, r9
     e36:	469b      	mov	fp, r3
     e38:	e7cd      	b.n	dd6 <swap_read_status_bytes+0x36>
     e3a:	f1b4 3fff 	cmp.w	r4, #4294967295
     e3e:	bf08      	it	eq
     e40:	462c      	moveq	r4, r5
     e42:	e7f5      	b.n	e30 <swap_read_status_bytes+0x90>
        bs->op = BOOT_STATUS_OP_SWAP;
     e44:	2302      	movs	r3, #2
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e46:	f5a4 7480 	sub.w	r4, r4, #256	; 0x100
        bs->op = BOOT_STATUS_OP_SWAP;
     e4a:	7173      	strb	r3, [r6, #5]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e4c:	1063      	asrs	r3, r4, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e4e:	f004 0401 	and.w	r4, r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e52:	3301      	adds	r3, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e54:	3401      	adds	r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e56:	6033      	str	r3, [r6, #0]
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e58:	7134      	strb	r4, [r6, #4]
     e5a:	e7cd      	b.n	df8 <swap_read_status_bytes+0x58>
        return BOOT_EBADARGS;
     e5c:	2507      	movs	r5, #7
     e5e:	e7cb      	b.n	df8 <swap_read_status_bytes+0x58>
            return BOOT_EFLASH;
     e60:	2501      	movs	r5, #1
     e62:	e7c9      	b.n	df8 <swap_read_status_bytes+0x58>
     e64:	0000a80e 	.word	0x0000a80e

00000e68 <boot_slots_compatible>:
    return off;
}

int
boot_slots_compatible(struct boot_loader_state *state)
{
     e68:	b538      	push	{r3, r4, r5, lr}
}

static inline size_t
boot_img_num_sectors(const struct boot_loader_state *state, size_t slot)
{
    return BOOT_IMG(state, slot).num_sectors;
     e6a:	6a81      	ldr	r1, [r0, #40]	; 0x28
     e6c:	6d42      	ldr	r2, [r0, #84]	; 0x54
    size_t sector_sz_sec = 0;
    size_t i;

    num_sectors_pri = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT);
    num_sectors_sec = boot_img_num_sectors(state, BOOT_SECONDARY_SLOT);
    if ((num_sectors_pri != num_sectors_sec) &&
     e6e:	4291      	cmp	r1, r2
     e70:	d008      	beq.n	e84 <boot_slots_compatible+0x1c>
            (num_sectors_pri != (num_sectors_sec + 1))) {
     e72:	1c53      	adds	r3, r2, #1
    if ((num_sectors_pri != num_sectors_sec) &&
     e74:	428b      	cmp	r3, r1
     e76:	d005      	beq.n	e84 <boot_slots_compatible+0x1c>
        BOOT_LOG_WRN("Cannot upgrade: not a compatible amount of sectors");
     e78:	4814      	ldr	r0, [pc, #80]	; (ecc <boot_slots_compatible+0x64>)
     e7a:	2157      	movs	r1, #87	; 0x57
        return 0;
    }

    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
     e7c:	f007 ff29 	bl	8cd2 <z_log_minimal_printk>
        return 0;
     e80:	2000      	movs	r0, #0
        }
    }

    return 1;
#endif /* PM_S1_ADDRESS */
}
     e82:	bd38      	pop	{r3, r4, r5, pc}
    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
     e84:	f5b1 7f80 	cmp.w	r1, #256	; 0x100
     e88:	d91c      	bls.n	ec4 <boot_slots_compatible+0x5c>
        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
     e8a:	4811      	ldr	r0, [pc, #68]	; (ed0 <boot_slots_compatible+0x68>)
     e8c:	2157      	movs	r1, #87	; 0x57
     e8e:	e7f5      	b.n	e7c <boot_slots_compatible+0x14>
     e90:	6a44      	ldr	r4, [r0, #36]	; 0x24
     e92:	6d05      	ldr	r5, [r0, #80]	; 0x50
     e94:	eb04 04c3 	add.w	r4, r4, r3, lsl #3
     e98:	eb05 05c3 	add.w	r5, r5, r3, lsl #3
     e9c:	6864      	ldr	r4, [r4, #4]
        if (sector_sz_pri != sector_sz_sec) {
     e9e:	686d      	ldr	r5, [r5, #4]
     ea0:	42ac      	cmp	r4, r5
     ea2:	d002      	beq.n	eaa <boot_slots_compatible+0x42>
            BOOT_LOG_WRN("Cannot upgrade: not same sector layout");
     ea4:	480b      	ldr	r0, [pc, #44]	; (ed4 <boot_slots_compatible+0x6c>)
     ea6:	2157      	movs	r1, #87	; 0x57
     ea8:	e7e8      	b.n	e7c <boot_slots_compatible+0x14>
    for (i = 0; i < num_sectors_sec; i++) {
     eaa:	3301      	adds	r3, #1
     eac:	429a      	cmp	r2, r3
     eae:	d1ef      	bne.n	e90 <boot_slots_compatible+0x28>
    if (num_sectors_pri > num_sectors_sec) {
     eb0:	4291      	cmp	r1, r2
     eb2:	d905      	bls.n	ec0 <boot_slots_compatible+0x58>
     eb4:	6a43      	ldr	r3, [r0, #36]	; 0x24
     eb6:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
        if (sector_sz_pri != boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i)) {
     eba:	685b      	ldr	r3, [r3, #4]
     ebc:	42a3      	cmp	r3, r4
     ebe:	d1f1      	bne.n	ea4 <boot_slots_compatible+0x3c>
    return 1;
     ec0:	2001      	movs	r0, #1
     ec2:	e7de      	b.n	e82 <boot_slots_compatible+0x1a>
    for (i = 0; i < num_sectors_sec; i++) {
     ec4:	2300      	movs	r3, #0
    size_t sector_sz_pri = 0;
     ec6:	461c      	mov	r4, r3
     ec8:	e7f0      	b.n	eac <boot_slots_compatible+0x44>
     eca:	bf00      	nop
     ecc:	0000a831 	.word	0x0000a831
     ed0:	0000a869 	.word	0x0000a869
     ed4:	0000a898 	.word	0x0000a898

00000ed8 <swap_status_source>:
                 (state)->copy_done,                                \
                 (state)->image_ok)

int
swap_status_source(struct boot_loader_state *state)
{
     ed8:	b500      	push	{lr}
     eda:	b089      	sub	sp, #36	; 0x24
    (void)state;
#endif

    image_index = BOOT_CURR_IMG(state);

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
     edc:	a904      	add	r1, sp, #16
     ede:	2003      	movs	r0, #3
     ee0:	f008 fc3b 	bl	975a <boot_read_swap_state_by_id>
            &state_primary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
     ee4:	f89d 2010 	ldrb.w	r2, [sp, #16]
     ee8:	2a01      	cmp	r2, #1
     eea:	d041      	beq.n	f70 <swap_status_source+0x98>
     eec:	4b25      	ldr	r3, [pc, #148]	; (f84 <swap_status_source+0xac>)
     eee:	4926      	ldr	r1, [pc, #152]	; (f88 <swap_status_source+0xb0>)
     ef0:	2a03      	cmp	r2, #3
     ef2:	bf08      	it	eq
     ef4:	460b      	moveq	r3, r1
     ef6:	f89d 2013 	ldrb.w	r2, [sp, #19]
     efa:	9202      	str	r2, [sp, #8]
     efc:	f89d 2012 	ldrb.w	r2, [sp, #18]
     f00:	9201      	str	r2, [sp, #4]
     f02:	f89d 2011 	ldrb.w	r2, [sp, #17]
     f06:	4821      	ldr	r0, [pc, #132]	; (f8c <swap_status_source+0xb4>)
     f08:	9200      	str	r2, [sp, #0]
     f0a:	2149      	movs	r1, #73	; 0x49
     f0c:	4a20      	ldr	r2, [pc, #128]	; (f90 <swap_status_source+0xb8>)
     f0e:	f007 fee0 	bl	8cd2 <z_log_minimal_printk>

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
     f12:	a906      	add	r1, sp, #24
     f14:	2001      	movs	r0, #1
     f16:	f008 fc20 	bl	975a <boot_read_swap_state_by_id>
            &state_secondary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
     f1a:	f89d 2018 	ldrb.w	r2, [sp, #24]
     f1e:	2a01      	cmp	r2, #1
     f20:	d028      	beq.n	f74 <swap_status_source+0x9c>
     f22:	4b18      	ldr	r3, [pc, #96]	; (f84 <swap_status_source+0xac>)
     f24:	4918      	ldr	r1, [pc, #96]	; (f88 <swap_status_source+0xb0>)
     f26:	2a03      	cmp	r2, #3
     f28:	bf08      	it	eq
     f2a:	460b      	moveq	r3, r1
     f2c:	f89d 201b 	ldrb.w	r2, [sp, #27]
     f30:	9202      	str	r2, [sp, #8]
     f32:	f89d 201a 	ldrb.w	r2, [sp, #26]
     f36:	9201      	str	r2, [sp, #4]
     f38:	f89d 2019 	ldrb.w	r2, [sp, #25]
     f3c:	9200      	str	r2, [sp, #0]
     f3e:	4813      	ldr	r0, [pc, #76]	; (f8c <swap_status_source+0xb4>)
     f40:	4a14      	ldr	r2, [pc, #80]	; (f94 <swap_status_source+0xbc>)
     f42:	2149      	movs	r1, #73	; 0x49
     f44:	f007 fec5 	bl	8cd2 <z_log_minimal_printk>

    if (state_primary_slot.magic == BOOT_MAGIC_GOOD &&
     f48:	f89d 3010 	ldrb.w	r3, [sp, #16]
     f4c:	2b01      	cmp	r3, #1
     f4e:	d113      	bne.n	f78 <swap_status_source+0xa0>
     f50:	f89d 3012 	ldrb.w	r3, [sp, #18]
     f54:	2b03      	cmp	r3, #3
     f56:	d10f      	bne.n	f78 <swap_status_source+0xa0>
            state_primary_slot.copy_done == BOOT_FLAG_UNSET &&
     f58:	f89d 3018 	ldrb.w	r3, [sp, #24]
     f5c:	2b01      	cmp	r3, #1
     f5e:	d00b      	beq.n	f78 <swap_status_source+0xa0>
            state_secondary_slot.magic != BOOT_MAGIC_GOOD) {

        source = BOOT_STATUS_SOURCE_PRIMARY_SLOT;

        BOOT_LOG_INF("Boot source: primary slot");
     f60:	480d      	ldr	r0, [pc, #52]	; (f98 <swap_status_source+0xc0>)
     f62:	2149      	movs	r1, #73	; 0x49
     f64:	f007 feb5 	bl	8cd2 <z_log_minimal_printk>
        return source;
     f68:	2002      	movs	r0, #2
    }

    BOOT_LOG_INF("Boot source: none");
    return BOOT_STATUS_SOURCE_NONE;
}
     f6a:	b009      	add	sp, #36	; 0x24
     f6c:	f85d fb04 	ldr.w	pc, [sp], #4
    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
     f70:	4b0a      	ldr	r3, [pc, #40]	; (f9c <swap_status_source+0xc4>)
     f72:	e7c0      	b.n	ef6 <swap_status_source+0x1e>
    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
     f74:	4b09      	ldr	r3, [pc, #36]	; (f9c <swap_status_source+0xc4>)
     f76:	e7d9      	b.n	f2c <swap_status_source+0x54>
    BOOT_LOG_INF("Boot source: none");
     f78:	4809      	ldr	r0, [pc, #36]	; (fa0 <swap_status_source+0xc8>)
     f7a:	2149      	movs	r1, #73	; 0x49
     f7c:	f007 fea9 	bl	8cd2 <z_log_minimal_printk>
    return BOOT_STATUS_SOURCE_NONE;
     f80:	2000      	movs	r0, #0
     f82:	e7f2      	b.n	f6a <swap_status_source+0x92>
     f84:	0000a8c4 	.word	0x0000a8c4
     f88:	0000a8cd 	.word	0x0000a8cd
     f8c:	0000a8e1 	.word	0x0000a8e1
     f90:	0000a8d3 	.word	0x0000a8d3
     f94:	0000a922 	.word	0x0000a922
     f98:	0000a932 	.word	0x0000a932
     f9c:	0000a8c8 	.word	0x0000a8c8
     fa0:	0000a951 	.word	0x0000a951

00000fa4 <fixup_revert>:
 * upgrade (by initializing the secondary slot).
 */
void
fixup_revert(const struct boot_loader_state *state, struct boot_status *bs,
        const struct flash_area *fap_sec)
{
     fa4:	b570      	push	{r4, r5, r6, lr}
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    /* No fixup required */
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     fa6:	684b      	ldr	r3, [r1, #4]
{
     fa8:	4614      	mov	r4, r2
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     faa:	4a1e      	ldr	r2, [pc, #120]	; (1024 <CONFIG_FPROTECT_BLOCK_SIZE+0x24>)
     fac:	f003 23ff 	and.w	r3, r3, #4278255360	; 0xff00ff00
     fb0:	4293      	cmp	r3, r2
{
     fb2:	b086      	sub	sp, #24
     fb4:	4606      	mov	r6, r0
     fb6:	460d      	mov	r5, r1
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     fb8:	d12f      	bne.n	101a <CONFIG_FPROTECT_BLOCK_SIZE+0x1a>
        bs->op != BOOT_STATUS_OP_MOVE ||
     fba:	680b      	ldr	r3, [r1, #0]
     fbc:	2b01      	cmp	r3, #1
     fbe:	d12c      	bne.n	101a <CONFIG_FPROTECT_BLOCK_SIZE+0x1a>
        bs->idx != BOOT_STATUS_IDX_0) {
        return;
    }

    rc = boot_read_swap_state(fap_sec, &swap_state);
     fc0:	a904      	add	r1, sp, #16
     fc2:	4620      	mov	r0, r4
     fc4:	f003 fc1e 	bl	4804 <boot_read_swap_state>
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
     fc8:	f89d 2010 	ldrb.w	r2, [sp, #16]
     fcc:	2a01      	cmp	r2, #1
     fce:	d026      	beq.n	101e <CONFIG_FPROTECT_BLOCK_SIZE+0x1e>
     fd0:	4b15      	ldr	r3, [pc, #84]	; (1028 <CONFIG_FPROTECT_BLOCK_SIZE+0x28>)
     fd2:	4916      	ldr	r1, [pc, #88]	; (102c <CONFIG_FPROTECT_BLOCK_SIZE+0x2c>)
     fd4:	2a03      	cmp	r2, #3
     fd6:	bf08      	it	eq
     fd8:	460b      	moveq	r3, r1
     fda:	f89d 2013 	ldrb.w	r2, [sp, #19]
     fde:	9202      	str	r2, [sp, #8]
     fe0:	f89d 2012 	ldrb.w	r2, [sp, #18]
     fe4:	9201      	str	r2, [sp, #4]
     fe6:	f89d 2011 	ldrb.w	r2, [sp, #17]
     fea:	9200      	str	r2, [sp, #0]
     fec:	4810      	ldr	r0, [pc, #64]	; (1030 <CONFIG_FPROTECT_BLOCK_SIZE+0x30>)
     fee:	4a11      	ldr	r2, [pc, #68]	; (1034 <CONFIG_FPROTECT_BLOCK_SIZE+0x34>)
     ff0:	2149      	movs	r1, #73	; 0x49
     ff2:	f007 fe6e 	bl	8cd2 <z_log_minimal_printk>

    if (swap_state.magic == BOOT_MAGIC_UNSET) {
     ff6:	f89d 3010 	ldrb.w	r3, [sp, #16]
     ffa:	2b03      	cmp	r3, #3
     ffc:	d10d      	bne.n	101a <CONFIG_FPROTECT_BLOCK_SIZE+0x1a>
        rc = swap_erase_trailer_sectors(state, fap_sec);
     ffe:	4621      	mov	r1, r4
    1000:	4630      	mov	r0, r6
    1002:	f007 fbc4 	bl	878e <swap_erase_trailer_sectors>
        assert(rc == 0);

        rc = boot_write_image_ok(fap_sec);
    1006:	4620      	mov	r0, r4
    1008:	f008 fb9a 	bl	9740 <boot_write_image_ok>
        assert(rc == 0);

        rc = boot_write_swap_size(fap_sec, bs->swap_size);
    100c:	68a9      	ldr	r1, [r5, #8]
    100e:	4620      	mov	r0, r4
    1010:	f007 faeb 	bl	85ea <boot_write_swap_size>
        assert(rc == 0);

        rc = boot_write_magic(fap_sec);
    1014:	4620      	mov	r0, r4
    1016:	f003 fbd5 	bl	47c4 <boot_write_magic>
        assert(rc == 0);
    }
}
    101a:	b006      	add	sp, #24
    101c:	bd70      	pop	{r4, r5, r6, pc}
    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
    101e:	4b06      	ldr	r3, [pc, #24]	; (1038 <CONFIG_FPROTECT_BLOCK_SIZE+0x38>)
    1020:	e7db      	b.n	fda <fixup_revert+0x36>
    1022:	bf00      	nop
    1024:	04000100 	.word	0x04000100
    1028:	0000a8c4 	.word	0x0000a8c4
    102c:	0000a8cd 	.word	0x0000a8cd
    1030:	0000a8e1 	.word	0x0000a8e1
    1034:	0000a922 	.word	0x0000a922
    1038:	0000a8c8 	.word	0x0000a8c8

0000103c <swap_run>:

void
swap_run(struct boot_loader_state *state, struct boot_status *bs,
         uint32_t copy_size)
{
    103c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1040:	4605      	mov	r5, r0
    1042:	b089      	sub	sp, #36	; 0x24
    uint8_t image_index;
    const struct flash_area *fap_pri;
    const struct flash_area *fap_sec;
    int rc;

    BOOT_LOG_INF("Starting swap using move algorithm.");
    1044:	487d      	ldr	r0, [pc, #500]	; (123c <swap_run+0x200>)
{
    1046:	460c      	mov	r4, r1
    BOOT_LOG_INF("Starting swap using move algorithm.");
    1048:	2149      	movs	r1, #73	; 0x49
{
    104a:	4617      	mov	r7, r2
    BOOT_LOG_INF("Starting swap using move algorithm.");
    104c:	f007 fe41 	bl	8cd2 <z_log_minimal_printk>
    1050:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    1052:	2201      	movs	r2, #1
    1054:	685e      	ldr	r6, [r3, #4]

    sz = 0;
    1056:	2300      	movs	r3, #0
    g_last_idx = 0;

    sector_sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
    while (1) {
        sz += sector_sz;
    1058:	4433      	add	r3, r6
        /* Skip to next sector because all sectors will be moved up. */
        g_last_idx++;
        if (sz >= copy_size) {
    105a:	42bb      	cmp	r3, r7
    105c:	4611      	mov	r1, r2
    105e:	f102 0201 	add.w	r2, r2, #1
    1062:	d3f9      	bcc.n	1058 <swap_run+0x1c>
    1064:	4f76      	ldr	r7, [pc, #472]	; (1240 <swap_run+0x204>)
    }

    /*
     * When starting a new swap upgrade, check that there is enough space.
     */
    if (boot_status_is_reset(bs)) {
    1066:	4620      	mov	r0, r4
    1068:	6039      	str	r1, [r7, #0]
    106a:	f007 fb4f 	bl	870c <boot_status_is_reset>
    106e:	b308      	cbz	r0, 10b4 <swap_run+0x78>
        sz = 0;
        trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    1070:	6de8      	ldr	r0, [r5, #92]	; 0x5c
    1072:	f007 fa98 	bl	85a6 <boot_trailer_sz>
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
    1076:	6aab      	ldr	r3, [r5, #40]	; 0x28
    1078:	f103 38ff 	add.w	r8, r3, #4294967295
        sz = 0;
    107c:	2300      	movs	r3, #0

        while (1) {
            sz += sector_sz;
    107e:	4433      	add	r3, r6
            if  (sz >= trailer_sz) {
    1080:	4283      	cmp	r3, r0
    1082:	d202      	bcs.n	108a <swap_run+0x4e>
                break;
            }
            first_trailer_idx--;
    1084:	f108 38ff 	add.w	r8, r8, #4294967295
            sz += sector_sz;
    1088:	e7f9      	b.n	107e <swap_run+0x42>
        }

        if (g_last_idx >= first_trailer_idx) {
    108a:	683b      	ldr	r3, [r7, #0]
    108c:	4543      	cmp	r3, r8
    108e:	d311      	bcc.n	10b4 <swap_run+0x78>
            BOOT_LOG_WRN("Not enough free space to run swap upgrade");
    1090:	486c      	ldr	r0, [pc, #432]	; (1244 <swap_run+0x208>)
    1092:	2157      	movs	r1, #87	; 0x57
    1094:	f007 fe1d 	bl	8cd2 <z_log_minimal_printk>
            BOOT_LOG_WRN("required %d bytes but only %d are available",
    1098:	683a      	ldr	r2, [r7, #0]
    109a:	486b      	ldr	r0, [pc, #428]	; (1248 <swap_run+0x20c>)
    109c:	fb08 f306 	mul.w	r3, r8, r6
    10a0:	fb02 6206 	mla	r2, r2, r6, r6
    10a4:	2157      	movs	r1, #87	; 0x57
    10a6:	f007 fe14 	bl	8cd2 <z_log_minimal_printk>
                         (g_last_idx + 1) * sector_sz ,
                         first_trailer_idx * sector_sz);
            bs->swap_type = BOOT_SWAP_TYPE_NONE;
    10aa:	2301      	movs	r3, #1
    10ac:	71e3      	strb	r3, [r4, #7]
        idx++;
    }

    flash_area_close(fap_pri);
    flash_area_close(fap_sec);
}
    10ae:	b009      	add	sp, #36	; 0x24
    10b0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index), &fap_pri);
    10b4:	a906      	add	r1, sp, #24
    10b6:	2003      	movs	r0, #3
    10b8:	f000 fc8e 	bl	19d8 <flash_area_open>
    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index), &fap_sec);
    10bc:	a907      	add	r1, sp, #28
    10be:	2001      	movs	r0, #1
    10c0:	f000 fc8a 	bl	19d8 <flash_area_open>
    fixup_revert(state, bs, fap_sec);
    10c4:	9a07      	ldr	r2, [sp, #28]
    10c6:	4621      	mov	r1, r4
    10c8:	4628      	mov	r0, r5
    10ca:	f7ff ff6b 	bl	fa4 <fixup_revert>
    if (bs->op == BOOT_STATUS_OP_MOVE) {
    10ce:	7963      	ldrb	r3, [r4, #5]
    10d0:	2b01      	cmp	r3, #1
    10d2:	d10b      	bne.n	10ec <swap_run+0xb0>
        idx = g_last_idx;
    10d4:	f8d7 8000 	ldr.w	r8, [r7]
    BOOT_STATUS_ASSERT(rc == 0);
    10d8:	f8df b170 	ldr.w	fp, [pc, #368]	; 124c <swap_run+0x210>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    10dc:	683b      	ldr	r3, [r7, #0]
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    10de:	f8dd 9018 	ldr.w	r9, [sp, #24]
        while (idx > 0) {
    10e2:	f1b8 0f00 	cmp.w	r8, #0
    10e6:	d111      	bne.n	110c <swap_run+0xd0>
        bs->idx = BOOT_STATUS_IDX_0;
    10e8:	2301      	movs	r3, #1
    10ea:	6023      	str	r3, [r4, #0]
    bs->op = BOOT_STATUS_OP_SWAP;
    10ec:	2302      	movs	r3, #2
    10ee:	7163      	strb	r3, [r4, #5]
    idx = 1;
    10f0:	f04f 0801 	mov.w	r8, #1
    while (idx <= g_last_idx) {
    10f4:	683b      	ldr	r3, [r7, #0]
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    10f6:	f8dd a018 	ldr.w	sl, [sp, #24]
    while (idx <= g_last_idx) {
    10fa:	4598      	cmp	r8, r3
    10fc:	d949      	bls.n	1192 <swap_run+0x156>
    flash_area_close(fap_pri);
    10fe:	4650      	mov	r0, sl
    1100:	f007 fdf4 	bl	8cec <flash_area_close>
    flash_area_close(fap_sec);
    1104:	9807      	ldr	r0, [sp, #28]
    1106:	f007 fdf1 	bl	8cec <flash_area_close>
    110a:	e7d0      	b.n	10ae <swap_run+0x72>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    110c:	6822      	ldr	r2, [r4, #0]
    110e:	3301      	adds	r3, #1
    1110:	1a9b      	subs	r3, r3, r2
    1112:	4598      	cmp	r8, r3
    1114:	d83a      	bhi.n	118c <swap_run+0x150>

static inline uint32_t
boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
                    size_t sector)
{
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    1116:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	return fs->fs_off;
    1118:	6819      	ldr	r1, [r3, #0]
    111a:	f853 0038 	ldr.w	r0, [r3, r8, lsl #3]
    111e:	eb03 03c8 	add.w	r3, r3, r8, lsl #3
    if (bs->idx == BOOT_STATUS_IDX_0) {
    1122:	2a01      	cmp	r2, #1
    1124:	f853 3c08 	ldr.w	r3, [r3, #-8]
    1128:	eba3 0301 	sub.w	r3, r3, r1
    112c:	eba0 0a01 	sub.w	sl, r0, r1
    1130:	9304      	str	r3, [sp, #16]
    1132:	d111      	bne.n	1158 <swap_run+0x11c>
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    1134:	9b07      	ldr	r3, [sp, #28]
    1136:	9303      	str	r3, [sp, #12]
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
    1138:	68e3      	ldr	r3, [r4, #12]
    113a:	2b02      	cmp	r3, #2
    113c:	d008      	beq.n	1150 <swap_run+0x114>
            rc = swap_erase_trailer_sectors(state, fap_pri);
    113e:	4649      	mov	r1, r9
    1140:	4628      	mov	r0, r5
    1142:	f007 fb24 	bl	878e <swap_erase_trailer_sectors>
            rc = swap_status_init(state, fap_pri, bs);
    1146:	4622      	mov	r2, r4
    1148:	4649      	mov	r1, r9
    114a:	4628      	mov	r0, r5
    114c:	f007 fb55 	bl	87fa <swap_status_init>
        rc = swap_erase_trailer_sectors(state, fap_sec);
    1150:	9903      	ldr	r1, [sp, #12]
    1152:	4628      	mov	r0, r5
    1154:	f007 fb1b 	bl	878e <swap_erase_trailer_sectors>
    rc = boot_erase_region(fap_pri, new_off, sz);
    1158:	4632      	mov	r2, r6
    115a:	4651      	mov	r1, sl
    115c:	4648      	mov	r0, r9
    115e:	f007 fb14 	bl	878a <boot_erase_region>
    rc = boot_copy_region(state, fap_pri, fap_pri, old_off, new_off, sz);
    1162:	9b04      	ldr	r3, [sp, #16]
    1164:	464a      	mov	r2, r9
    1166:	4649      	mov	r1, r9
    1168:	e9cd a600 	strd	sl, r6, [sp]
    116c:	4628      	mov	r0, r5
    116e:	f7ff fc47 	bl	a00 <boot_copy_region>
    rc = boot_write_status(state, bs);
    1172:	4621      	mov	r1, r4
    1174:	4628      	mov	r0, r5
    1176:	f007 fad6 	bl	8726 <boot_write_status>
    bs->idx++;
    117a:	6823      	ldr	r3, [r4, #0]
    117c:	3301      	adds	r3, #1
    117e:	6023      	str	r3, [r4, #0]
    BOOT_STATUS_ASSERT(rc == 0);
    1180:	b120      	cbz	r0, 118c <swap_run+0x150>
    1182:	f8db 3000 	ldr.w	r3, [fp]
    1186:	3301      	adds	r3, #1
    1188:	f8cb 3000 	str.w	r3, [fp]
            idx--;
    118c:	f108 38ff 	add.w	r8, r8, #4294967295
    1190:	e7a4      	b.n	10dc <swap_run+0xa0>
        if (idx >= bs->idx) {
    1192:	6823      	ldr	r3, [r4, #0]
    1194:	4598      	cmp	r8, r3
    1196:	d34e      	bcc.n	1236 <swap_run+0x1fa>
    1198:	6a6a      	ldr	r2, [r5, #36]	; 0x24
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    119a:	f8dd b01c 	ldr.w	fp, [sp, #28]
    119e:	f852 1038 	ldr.w	r1, [r2, r8, lsl #3]
    11a2:	9104      	str	r1, [sp, #16]
    11a4:	ea4f 03c8 	mov.w	r3, r8, lsl #3
    11a8:	3b08      	subs	r3, #8
    11aa:	6811      	ldr	r1, [r2, #0]
    11ac:	9103      	str	r1, [sp, #12]
    11ae:	58d1      	ldr	r1, [r2, r3]
    11b0:	6d2a      	ldr	r2, [r5, #80]	; 0x50
    11b2:	58d0      	ldr	r0, [r2, r3]
    11b4:	6813      	ldr	r3, [r2, #0]
    11b6:	eba0 0903 	sub.w	r9, r0, r3
    if (bs->state == BOOT_STATUS_STATE_0) {
    11ba:	7923      	ldrb	r3, [r4, #4]
    11bc:	2b01      	cmp	r3, #1
    11be:	d138      	bne.n	1232 <swap_run+0x1f6>
    11c0:	9b03      	ldr	r3, [sp, #12]
        rc = boot_erase_region(fap_pri, pri_off, sz);
    11c2:	4632      	mov	r2, r6
    11c4:	1ac9      	subs	r1, r1, r3
    11c6:	4650      	mov	r0, sl
    11c8:	9105      	str	r1, [sp, #20]
    11ca:	f007 fade 	bl	878a <boot_erase_region>
        rc = boot_copy_region(state, fap_sec, fap_pri, sec_off, pri_off, sz);
    11ce:	9905      	ldr	r1, [sp, #20]
    11d0:	9100      	str	r1, [sp, #0]
    11d2:	464b      	mov	r3, r9
    11d4:	4652      	mov	r2, sl
    11d6:	4659      	mov	r1, fp
    11d8:	9601      	str	r6, [sp, #4]
    11da:	4628      	mov	r0, r5
    11dc:	f7ff fc10 	bl	a00 <boot_copy_region>
        rc = boot_write_status(state, bs);
    11e0:	4621      	mov	r1, r4
    11e2:	4628      	mov	r0, r5
    11e4:	f007 fa9f 	bl	8726 <boot_write_status>
        bs->state = BOOT_STATUS_STATE_1;
    11e8:	2302      	movs	r3, #2
    11ea:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    11ec:	b118      	cbz	r0, 11f6 <swap_run+0x1ba>
    11ee:	4a17      	ldr	r2, [pc, #92]	; (124c <swap_run+0x210>)
    11f0:	6813      	ldr	r3, [r2, #0]
    11f2:	3301      	adds	r3, #1
    11f4:	6013      	str	r3, [r2, #0]
        rc = boot_erase_region(fap_sec, sec_off, sz);
    11f6:	4632      	mov	r2, r6
    11f8:	4649      	mov	r1, r9
    11fa:	4658      	mov	r0, fp
    11fc:	f007 fac5 	bl	878a <boot_erase_region>
        rc = boot_copy_region(state, fap_pri, fap_sec, pri_up_off, sec_off, sz);
    1200:	e9dd 2303 	ldrd	r2, r3, [sp, #12]
    1204:	4651      	mov	r1, sl
    1206:	1a9b      	subs	r3, r3, r2
    1208:	e9cd 9600 	strd	r9, r6, [sp]
    120c:	465a      	mov	r2, fp
    120e:	4628      	mov	r0, r5
    1210:	f7ff fbf6 	bl	a00 <boot_copy_region>
        rc = boot_write_status(state, bs);
    1214:	4621      	mov	r1, r4
    1216:	4628      	mov	r0, r5
    1218:	f007 fa85 	bl	8726 <boot_write_status>
        bs->idx++;
    121c:	6823      	ldr	r3, [r4, #0]
    121e:	3301      	adds	r3, #1
    1220:	6023      	str	r3, [r4, #0]
        bs->state = BOOT_STATUS_STATE_0;
    1222:	2301      	movs	r3, #1
    1224:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    1226:	b130      	cbz	r0, 1236 <swap_run+0x1fa>
    1228:	4a08      	ldr	r2, [pc, #32]	; (124c <swap_run+0x210>)
    122a:	6813      	ldr	r3, [r2, #0]
    122c:	3301      	adds	r3, #1
    122e:	6013      	str	r3, [r2, #0]
    1230:	e001      	b.n	1236 <swap_run+0x1fa>
    if (bs->state == BOOT_STATUS_STATE_1) {
    1232:	2b02      	cmp	r3, #2
    1234:	d0df      	beq.n	11f6 <swap_run+0x1ba>
        idx++;
    1236:	f108 0801 	add.w	r8, r8, #1
    123a:	e75b      	b.n	10f4 <swap_run+0xb8>
    123c:	0000a968 	.word	0x0000a968
    1240:	20000004 	.word	0x20000004
    1244:	0000a991 	.word	0x0000a991
    1248:	0000a9c0 	.word	0x0000a9c0
    124c:	2000189c 	.word	0x2000189c

00001250 <cc310_init>:
 */

#include "cc310_glue.h"

int cc310_init(void)
{
    1250:	b570      	push	{r4, r5, r6, lr}
    /* Only initialize once */
    static bool initialized;

    if (!initialized) {
    1252:	4d09      	ldr	r5, [pc, #36]	; (1278 <cc310_init+0x28>)
    1254:	782b      	ldrb	r3, [r5, #0]
    1256:	b10b      	cbz	r3, 125c <cc310_init+0xc>
        }
        initialized = true;
        nrf_cc310_disable();
    }

    return 0;
    1258:	2000      	movs	r0, #0
}
    125a:	bd70      	pop	{r4, r5, r6, pc}
    NRF_CRYPTOCELL->ENABLE=1;
    125c:	4c07      	ldr	r4, [pc, #28]	; (127c <cc310_init+0x2c>)
    125e:	2601      	movs	r6, #1
    1260:	f8c4 6500 	str.w	r6, [r4, #1280]	; 0x500
        if (nrf_cc310_bl_init() != 0) {
    1264:	f006 f8ac 	bl	73c0 <nrf_cc310_bl_init>
    1268:	b918      	cbnz	r0, 1272 <cc310_init+0x22>
        initialized = true;
    126a:	702e      	strb	r6, [r5, #0]
    NRF_CRYPTOCELL->ENABLE=0;
    126c:	f8c4 0500 	str.w	r0, [r4, #1280]	; 0x500
}
    1270:	e7f2      	b.n	1258 <cc310_init+0x8>
            return -1;
    1272:	f04f 30ff 	mov.w	r0, #4294967295
    1276:	e7f0      	b.n	125a <cc310_init+0xa>
    1278:	200022b8 	.word	0x200022b8
    127c:	5002a000 	.word	0x5002a000

00001280 <cc310_ecdsa_verify_secp256r1>:

int cc310_ecdsa_verify_secp256r1(uint8_t *hash,
                                 uint8_t *public_key,
                                 uint8_t *signature,
                                 size_t hash_len)
{
    1280:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    NRF_CRYPTOCELL->ENABLE=1;
    1284:	f8df 8030 	ldr.w	r8, [pc, #48]	; 12b8 <cc310_ecdsa_verify_secp256r1+0x38>
    1288:	b0ac      	sub	sp, #176	; 0xb0
    128a:	461f      	mov	r7, r3
    128c:	4606      	mov	r6, r0
    128e:	460c      	mov	r4, r1
    1290:	4615      	mov	r5, r2
        int rc;
        nrf_cc310_bl_ecdsa_verify_context_secp256r1_t ctx;
        cc310_init();
    1292:	f7ff ffdd 	bl	1250 <cc310_init>
    1296:	2301      	movs	r3, #1
    1298:	f8c8 3500 	str.w	r3, [r8, #1280]	; 0x500
        nrf_cc310_enable();
        rc = nrf_cc310_bl_ecdsa_verify_secp256r1(&ctx,
    129c:	462a      	mov	r2, r5
    129e:	4633      	mov	r3, r6
    12a0:	9700      	str	r7, [sp, #0]
    12a2:	4621      	mov	r1, r4
    12a4:	a803      	add	r0, sp, #12
    12a6:	f008 fd3d 	bl	9d24 <nrf_cc310_bl_ecdsa_verify_secp256r1>
    NRF_CRYPTOCELL->ENABLE=0;
    12aa:	2300      	movs	r3, #0
    12ac:	f8c8 3500 	str.w	r3, [r8, #1280]	; 0x500
                                                 (nrf_cc310_bl_ecc_signature_secp256r1_t  *) signature,
                                                 hash,
                                                 hash_len);
        nrf_cc310_disable();
        return rc;
}
    12b0:	b02c      	add	sp, #176	; 0xb0
    12b2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    12b6:	bf00      	nop
    12b8:	5002a000 	.word	0x5002a000

000012bc <nrf_cleanup_peripheral>:
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12bc:	4a16      	ldr	r2, [pc, #88]	; (1318 <nrf_cleanup_peripheral+0x5c>)
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    12be:	f04f 33ff 	mov.w	r3, #4294967295
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12c2:	2101      	movs	r1, #1
    12c4:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    12c6:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    12ca:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12ce:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    12d2:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    12d4:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    12d8:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12dc:	f502 3298 	add.w	r2, r2, #77824	; 0x13000
    12e0:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    12e2:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    12e6:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
}

NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
{
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    12ea:	f5a2 3208 	sub.w	r2, r2, #139264	; 0x22000
    12ee:	2100      	movs	r1, #0
    12f0:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    12f4:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    12f8:	f502 3218 	add.w	r2, r2, #155648	; 0x26000
    12fc:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    1300:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    }
}

NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
{
    p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
    1304:	f5a2 4210 	sub.w	r2, r2, #36864	; 0x9000
    1308:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    130c:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1310:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
#endif
#if defined(NRF_DPPIC)
    nrf_dppi_channels_disable_all(NRF_DPPIC);
#endif
    nrf_cleanup_clock();
}
    1314:	4770      	bx	lr
    1316:	bf00      	nop
    1318:	4000b000 	.word	0x4000b000

0000131c <char_out>:
}

static int char_out(int c, void *ctx_p)
{
	(void) ctx_p;
	return _char_out(c);
    131c:	4b01      	ldr	r3, [pc, #4]	; (1324 <char_out+0x8>)
    131e:	681b      	ldr	r3, [r3, #0]
    1320:	4718      	bx	r3
    1322:	bf00      	nop
    1324:	20000008 	.word	0x20000008

00001328 <__printk_hook_install>:
	_char_out = fn;
    1328:	4b01      	ldr	r3, [pc, #4]	; (1330 <__printk_hook_install+0x8>)
    132a:	6018      	str	r0, [r3, #0]
}
    132c:	4770      	bx	lr
    132e:	bf00      	nop
    1330:	20000008 	.word	0x20000008

00001334 <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
    1334:	b507      	push	{r0, r1, r2, lr}
    1336:	460b      	mov	r3, r1
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap);
#else
static inline
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap)
{
	return z_cbvprintf_impl(out, ctx, format, ap, 0);
    1338:	2100      	movs	r1, #0
    133a:	4602      	mov	r2, r0
    133c:	9100      	str	r1, [sp, #0]
    133e:	4803      	ldr	r0, [pc, #12]	; (134c <vprintk+0x18>)
    1340:	f000 f914 	bl	156c <z_cbvprintf_impl>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
    1344:	b003      	add	sp, #12
    1346:	f85d fb04 	ldr.w	pc, [sp], #4
    134a:	bf00      	nop
    134c:	0000131d 	.word	0x0000131d

00001350 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
    1350:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1354:	8b05      	ldrh	r5, [r0, #24]
{
    1356:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
    1358:	0728      	lsls	r0, r5, #28
{
    135a:	4690      	mov	r8, r2
	if (processing) {
    135c:	d411      	bmi.n	1382 <process_event+0x32>

	sys_slist_init(&clients);
	do {
		onoff_transition_fn transit = NULL;

		if (evt == EVT_RECHECK) {
    135e:	2902      	cmp	r1, #2
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1360:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
    1364:	f040 80cd 	bne.w	1502 <process_event+0x1b2>
			evt = process_recheck(mgr);
    1368:	4620      	mov	r0, r4
    136a:	f007 fbd7 	bl	8b1c <process_recheck>
		}

		if (evt == EVT_NOP) {
    136e:	b178      	cbz	r0, 1390 <process_event+0x40>
			break;
		}

		res = 0;
		if (evt == EVT_COMPLETE) {
    1370:	3801      	subs	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1372:	8b21      	ldrh	r1, [r4, #24]
    1374:	2804      	cmp	r0, #4
    1376:	d811      	bhi.n	139c <process_event+0x4c>
    1378:	e8df f000 	tbb	[pc, r0]
    137c:	856d10c3 	.word	0x856d10c3
    1380:	95          	.byte	0x95
    1381:	00          	.byte	0x00
		if (evt == EVT_COMPLETE) {
    1382:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
    1384:	bf0c      	ite	eq
    1386:	f045 0510 	orreq.w	r5, r5, #16
			mgr->flags |= ONOFF_FLAG_RECHECK;
    138a:	f045 0520 	orrne.w	r5, r5, #32
    138e:	8325      	strh	r5, [r4, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    1390:	f388 8811 	msr	BASEPRI, r8
    1394:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
    1398:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    139c:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    13a0:	45aa      	cmp	sl, r5
    13a2:	f000 80a6 	beq.w	14f2 <process_event+0x1a2>
	 * a memory barrier when used like this, and we don't have a
	 * Zephyr framework for that.
	 */
	atomic_clear(&l->locked);
#endif
	arch_irq_unlock(key.key);
    13a6:	2700      	movs	r7, #0
    13a8:	46b9      	mov	r9, r7
    13aa:	463e      	mov	r6, r7
    13ac:	68a3      	ldr	r3, [r4, #8]
    13ae:	2b00      	cmp	r3, #0
    13b0:	f000 80bd 	beq.w	152e <process_event+0x1de>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    13b4:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    13b8:	8321      	strh	r1, [r4, #24]
    13ba:	f388 8811 	msr	BASEPRI, r8
    13be:	f3bf 8f6f 	isb	sy
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    13c2:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    13c4:	2900      	cmp	r1, #0
    13c6:	f000 80bb 	beq.w	1540 <process_event+0x1f0>
	return node->next;
    13ca:	680d      	ldr	r5, [r1, #0]
    13cc:	2900      	cmp	r1, #0
    13ce:	f000 80b7 	beq.w	1540 <process_event+0x1f0>
		mon->callback(mgr, mon, state, res);
    13d2:	f8d1 8004 	ldr.w	r8, [r1, #4]
    13d6:	4633      	mov	r3, r6
    13d8:	4652      	mov	r2, sl
    13da:	4620      	mov	r0, r4
    13dc:	47c0      	blx	r8
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    13de:	2d00      	cmp	r5, #0
    13e0:	d076      	beq.n	14d0 <process_event+0x180>
    13e2:	682b      	ldr	r3, [r5, #0]
    13e4:	4629      	mov	r1, r5
    13e6:	461d      	mov	r5, r3
    13e8:	e7f0      	b.n	13cc <process_event+0x7c>
    13ea:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    13ee:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    13f0:	2a01      	cmp	r2, #1
    13f2:	d81b      	bhi.n	142c <process_event+0xdc>
	list->head = NULL;
    13f4:	2200      	movs	r2, #0
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    13f6:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
    13fa:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
    13fc:	6827      	ldr	r7, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    13fe:	b289      	uxth	r1, r1
	list->tail = NULL;
    1400:	e9c4 2200 	strd	r2, r2, [r4]
		if (state == ONOFF_STATE_TO_ON) {
    1404:	d109      	bne.n	141a <process_event+0xca>
    1406:	463b      	mov	r3, r7
    1408:	e003      	b.n	1412 <process_event+0xc2>
				mgr->refs += 1U;
    140a:	8b62      	ldrh	r2, [r4, #26]
    140c:	3201      	adds	r2, #1
    140e:	8362      	strh	r2, [r4, #26]
	return node->next;
    1410:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    1412:	2b00      	cmp	r3, #0
    1414:	d1f9      	bne.n	140a <process_event+0xba>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1416:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
    141a:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    141c:	4620      	mov	r0, r4
    141e:	f007 fb7d 	bl	8b1c <process_recheck>
    1422:	2800      	cmp	r0, #0
    1424:	d07b      	beq.n	151e <process_event+0x1ce>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    1426:	f041 0120 	orr.w	r1, r1, #32
    142a:	e077      	b.n	151c <process_event+0x1cc>
	} else if (state == ONOFF_STATE_TO_OFF) {
    142c:	2b04      	cmp	r3, #4
    142e:	d10a      	bne.n	1446 <process_event+0xf6>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1430:	f021 0107 	bic.w	r1, r1, #7
    1434:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
    1436:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    1438:	4620      	mov	r0, r4
    143a:	f007 fb6f 	bl	8b1c <process_recheck>
    143e:	b110      	cbz	r0, 1446 <process_event+0xf6>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    1440:	f041 0120 	orr.w	r1, r1, #32
    1444:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    1446:	8b21      	ldrh	r1, [r4, #24]
    1448:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    144c:	45aa      	cmp	sl, r5
    144e:	d050      	beq.n	14f2 <process_event+0x1a2>
    1450:	2700      	movs	r7, #0
		onoff_transition_fn transit = NULL;
    1452:	46b9      	mov	r9, r7
    1454:	e7aa      	b.n	13ac <process_event+0x5c>
			transit = mgr->transitions->start;
    1456:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1458:	f021 0107 	bic.w	r1, r1, #7
    145c:	f041 0106 	orr.w	r1, r1, #6
				   && !sys_slist_is_empty(&mgr->monitors);
    1460:	2d06      	cmp	r5, #6
			transit = mgr->transitions->start;
    1462:	f8d3 9000 	ldr.w	r9, [r3]
	mgr->flags = (state & ONOFF_STATE_MASK)
    1466:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
    1468:	d12d      	bne.n	14c6 <process_event+0x176>
		    || (transit != NULL)) {
    146a:	f1b9 0f00 	cmp.w	r9, #0
    146e:	d040      	beq.n	14f2 <process_event+0x1a2>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    1470:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    1474:	8321      	strh	r1, [r4, #24]
    1476:	f388 8811 	msr	BASEPRI, r8
    147a:	f3bf 8f6f 	isb	sy
				transit(mgr, transition_complete);
    147e:	493a      	ldr	r1, [pc, #232]	; (1568 <process_event+0x218>)
    1480:	4620      	mov	r0, r4
    1482:	47c8      	blx	r9
    1484:	e029      	b.n	14da <process_event+0x18a>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1486:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->stop;
    148a:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    148c:	f041 0104 	orr.w	r1, r1, #4
    1490:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
    1492:	2d04      	cmp	r5, #4
			transit = mgr->transitions->stop;
    1494:	f8d3 9004 	ldr.w	r9, [r3, #4]
	mgr->flags = (state & ONOFF_STATE_MASK)
    1498:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
    149a:	d0e6      	beq.n	146a <process_event+0x11a>
    149c:	2700      	movs	r7, #0
		res = 0;
    149e:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    14a0:	f04f 0a04 	mov.w	sl, #4
    14a4:	e782      	b.n	13ac <process_event+0x5c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    14a6:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->reset;
    14aa:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    14ac:	f041 0105 	orr.w	r1, r1, #5
    14b0:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
    14b2:	2d05      	cmp	r5, #5
			transit = mgr->transitions->reset;
    14b4:	f8d3 9008 	ldr.w	r9, [r3, #8]
	mgr->flags = (state & ONOFF_STATE_MASK)
    14b8:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
    14ba:	d0d6      	beq.n	146a <process_event+0x11a>
    14bc:	2700      	movs	r7, #0
		res = 0;
    14be:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    14c0:	f04f 0a05 	mov.w	sl, #5
    14c4:	e772      	b.n	13ac <process_event+0x5c>
				   && !sys_slist_is_empty(&mgr->monitors);
    14c6:	2700      	movs	r7, #0
		res = 0;
    14c8:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    14ca:	f04f 0a06 	mov.w	sl, #6
    14ce:	e76d      	b.n	13ac <process_event+0x5c>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    14d0:	462b      	mov	r3, r5
    14d2:	e787      	b.n	13e4 <process_event+0x94>
			if (transit != NULL) {
    14d4:	f1b9 0f00 	cmp.w	r9, #0
    14d8:	d1d1      	bne.n	147e <process_event+0x12e>
	__asm__ volatile(
    14da:	f04f 0320 	mov.w	r3, #32
    14de:	f3ef 8811 	mrs	r8, BASEPRI
    14e2:	f383 8812 	msr	BASEPRI_MAX, r3
    14e6:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    14ea:	8b23      	ldrh	r3, [r4, #24]
    14ec:	f023 0308 	bic.w	r3, r3, #8
    14f0:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
    14f2:	8b25      	ldrh	r5, [r4, #24]
    14f4:	06ea      	lsls	r2, r5, #27
    14f6:	d52e      	bpl.n	1556 <process_event+0x206>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    14f8:	f025 0310 	bic.w	r3, r5, #16
    14fc:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
    14fe:	f005 0507 	and.w	r5, r5, #7
			res = mgr->last_res;
    1502:	6966      	ldr	r6, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1504:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
    1506:	2e00      	cmp	r6, #0
    1508:	f6bf af6f 	bge.w	13ea <process_event+0x9a>
	list->head = NULL;
    150c:	2300      	movs	r3, #0
		*clients = mgr->clients;
    150e:	6827      	ldr	r7, [r4, #0]
	list->tail = NULL;
    1510:	e9c4 3300 	strd	r3, r3, [r4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1514:	f021 0107 	bic.w	r1, r1, #7
    1518:	f041 0101 	orr.w	r1, r1, #1
			mgr->flags |= ONOFF_FLAG_RECHECK;
    151c:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    151e:	8b21      	ldrh	r1, [r4, #24]
    1520:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    1524:	45aa      	cmp	sl, r5
    1526:	f04f 0900 	mov.w	r9, #0
    152a:	f47f af3f 	bne.w	13ac <process_event+0x5c>
		    || !sys_slist_is_empty(&clients)
    152e:	2f00      	cmp	r7, #0
    1530:	d09b      	beq.n	146a <process_event+0x11a>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    1532:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    1536:	8321      	strh	r1, [r4, #24]
	__asm__ volatile(
    1538:	f388 8811 	msr	BASEPRI, r8
    153c:	f3bf 8f6f 	isb	sy
			if (!sys_slist_is_empty(&clients)) {
    1540:	2f00      	cmp	r7, #0
    1542:	d0c7      	beq.n	14d4 <process_event+0x184>
	return node->next;
    1544:	683d      	ldr	r5, [r7, #0]
		notify_one(mgr, cli, state, res);
    1546:	4639      	mov	r1, r7
    1548:	4633      	mov	r3, r6
    154a:	4652      	mov	r2, sl
    154c:	4620      	mov	r0, r4
    154e:	f007 fb11 	bl	8b74 <notify_one>
	list->head = node;
    1552:	462f      	mov	r7, r5
	while (!sys_slist_is_empty(list)) {
    1554:	e7f4      	b.n	1540 <process_event+0x1f0>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    1556:	06ab      	lsls	r3, r5, #26
    1558:	f57f af1a 	bpl.w	1390 <process_event+0x40>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    155c:	f025 0320 	bic.w	r3, r5, #32
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    1560:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
    1562:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
    1566:	e6ff      	b.n	1368 <process_event+0x18>
    1568:	00008ba1 	.word	0x00008ba1

0000156c <z_cbvprintf_impl>:
 *
 * @return printed byte count if CONFIG_CBPRINTF_LIBC_SUBSTS is set
 */
int z_cbvprintf_impl(cbprintf_cb out, void *ctx, const char *fmt,
		     va_list ap, uint32_t flags)
{
    156c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1570:	b08d      	sub	sp, #52	; 0x34
    1572:	461d      	mov	r5, r3

	const bool tagged_ap = (flags & Z_CBVPRINTF_PROCESS_FLAG_TAGGED_ARGS)
			       == Z_CBVPRINTF_PROCESS_FLAG_TAGGED_ARGS;

	/* we pre-increment in the loop  afterwards */
	fmt--;
    1574:	1e53      	subs	r3, r2, #1
{
    1576:	4682      	mov	sl, r0
    1578:	9101      	str	r1, [sp, #4]
	fmt--;
    157a:	9303      	str	r3, [sp, #12]
	size_t count = 0;
    157c:	f04f 0900 	mov.w	r9, #0

start:
	while (*++fmt != '%') {
    1580:	9b03      	ldr	r3, [sp, #12]
    1582:	7858      	ldrb	r0, [r3, #1]
    1584:	2825      	cmp	r0, #37	; 0x25
    1586:	f103 0401 	add.w	r4, r3, #1
    158a:	d119      	bne.n	15c0 <z_cbvprintf_impl+0x54>
	prefix = "";
	padding_mode = 0;
	length_mod = 0;
	special = 0;

	for (fmt++ ; ; fmt++) {
    158c:	461e      	mov	r6, r3
	special = 0;
    158e:	2000      	movs	r0, #0
	precision = -1;
    1590:	f04f 38ff 	mov.w	r8, #4294967295
	for (fmt++ ; ; fmt++) {
    1594:	3602      	adds	r6, #2
	length_mod = 0;
    1596:	4603      	mov	r3, r0
	padding_mode = 0;
    1598:	9002      	str	r0, [sp, #8]
	min_width = -1;
    159a:	4644      	mov	r4, r8
		switch (*fmt) {
    159c:	7831      	ldrb	r1, [r6, #0]
    159e:	9603      	str	r6, [sp, #12]
    15a0:	2939      	cmp	r1, #57	; 0x39
    15a2:	d854      	bhi.n	164e <z_cbvprintf_impl+0xe2>
    15a4:	291f      	cmp	r1, #31
    15a6:	d814      	bhi.n	15d2 <z_cbvprintf_impl+0x66>
    15a8:	2900      	cmp	r1, #0
    15aa:	f000 81ed 	beq.w	1988 <z_cbvprintf_impl+0x41c>
			precision = 0;
			break;
		}

		default:
			OUTC('%');
    15ae:	9901      	ldr	r1, [sp, #4]
    15b0:	2025      	movs	r0, #37	; 0x25
    15b2:	47d0      	blx	sl
			OUTC(*fmt);
    15b4:	9901      	ldr	r1, [sp, #4]
    15b6:	7830      	ldrb	r0, [r6, #0]
    15b8:	47d0      	blx	sl
    15ba:	f109 0902 	add.w	r9, r9, #2
			goto start;
    15be:	e7df      	b.n	1580 <z_cbvprintf_impl+0x14>
		if (*fmt == '\0') {
    15c0:	2800      	cmp	r0, #0
    15c2:	f000 81e1 	beq.w	1988 <z_cbvprintf_impl+0x41c>
		OUTC(*fmt);
    15c6:	9901      	ldr	r1, [sp, #4]
    15c8:	47d0      	blx	sl
    15ca:	f109 0901 	add.w	r9, r9, #1
	while (*++fmt != '%') {
    15ce:	9403      	str	r4, [sp, #12]
    15d0:	e7d6      	b.n	1580 <z_cbvprintf_impl+0x14>
		switch (*fmt) {
    15d2:	f1a1 0220 	sub.w	r2, r1, #32
    15d6:	2a19      	cmp	r2, #25
    15d8:	d8e9      	bhi.n	15ae <z_cbvprintf_impl+0x42>
    15da:	a701      	add	r7, pc, #4	; (adr r7, 15e0 <z_cbvprintf_impl+0x74>)
    15dc:	f857 f022 	ldr.w	pc, [r7, r2, lsl #2]
    15e0:	00001649 	.word	0x00001649
    15e4:	000015af 	.word	0x000015af
    15e8:	000015af 	.word	0x000015af
    15ec:	00001649 	.word	0x00001649
    15f0:	000015af 	.word	0x000015af
    15f4:	000016c9 	.word	0x000016c9
    15f8:	000015af 	.word	0x000015af
    15fc:	000015af 	.word	0x000015af
    1600:	000015af 	.word	0x000015af
    1604:	000015af 	.word	0x000015af
    1608:	00001715 	.word	0x00001715
    160c:	00001649 	.word	0x00001649
    1610:	000015af 	.word	0x000015af
    1614:	00001729 	.word	0x00001729
    1618:	000016d5 	.word	0x000016d5
    161c:	000015af 	.word	0x000015af
    1620:	000016e3 	.word	0x000016e3
    1624:	00001703 	.word	0x00001703
    1628:	00001703 	.word	0x00001703
    162c:	00001703 	.word	0x00001703
    1630:	00001703 	.word	0x00001703
    1634:	00001703 	.word	0x00001703
    1638:	00001703 	.word	0x00001703
    163c:	00001703 	.word	0x00001703
    1640:	00001703 	.word	0x00001703
    1644:	00001703 	.word	0x00001703
    1648:	4608      	mov	r0, r1
    164a:	3601      	adds	r6, #1
    164c:	e7a6      	b.n	159c <z_cbvprintf_impl+0x30>
    164e:	2958      	cmp	r1, #88	; 0x58
    1650:	f000 80eb 	beq.w	182a <z_cbvprintf_impl+0x2be>
    1654:	f1a1 0263 	sub.w	r2, r1, #99	; 0x63
    1658:	b2d7      	uxtb	r7, r2
    165a:	2f17      	cmp	r7, #23
    165c:	d8a7      	bhi.n	15ae <z_cbvprintf_impl+0x42>
    165e:	2a17      	cmp	r2, #23
    1660:	d8a5      	bhi.n	15ae <z_cbvprintf_impl+0x42>
    1662:	a701      	add	r7, pc, #4	; (adr r7, 1668 <z_cbvprintf_impl+0xfc>)
    1664:	f857 f022 	ldr.w	pc, [r7, r2, lsl #2]
    1668:	000018d1 	.word	0x000018d1
    166c:	0000174f 	.word	0x0000174f
    1670:	000015af 	.word	0x000015af
    1674:	000015af 	.word	0x000015af
    1678:	000015af 	.word	0x000015af
    167c:	0000172f 	.word	0x0000172f
    1680:	0000174f 	.word	0x0000174f
    1684:	000015af 	.word	0x000015af
    1688:	000015af 	.word	0x000015af
    168c:	0000172f 	.word	0x0000172f
    1690:	000015af 	.word	0x000015af
    1694:	000015af 	.word	0x000015af
    1698:	000015af 	.word	0x000015af
    169c:	00001805 	.word	0x00001805
    16a0:	000015af 	.word	0x000015af
    16a4:	000015af 	.word	0x000015af
    16a8:	000018a5 	.word	0x000018a5
    16ac:	000015af 	.word	0x000015af
    16b0:	0000174f 	.word	0x0000174f
    16b4:	000015af 	.word	0x000015af
    16b8:	000015af 	.word	0x000015af
    16bc:	00001805 	.word	0x00001805
    16c0:	000015af 	.word	0x000015af
    16c4:	0000172f 	.word	0x0000172f
			OUTC('%');
    16c8:	9901      	ldr	r1, [sp, #4]
    16ca:	2025      	movs	r0, #37	; 0x25
    16cc:	47d0      	blx	sl
    16ce:	f109 0901 	add.w	r9, r9, #1
			goto start;
    16d2:	e755      	b.n	1580 <z_cbvprintf_impl+0x14>
			padding_mode &= (char)~PAD_ZERO;
    16d4:	9a02      	ldr	r2, [sp, #8]
    16d6:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
    16da:	9202      	str	r2, [sp, #8]
			precision = 0;
    16dc:	f04f 0800 	mov.w	r8, #0
			continue;
    16e0:	e7b3      	b.n	164a <z_cbvprintf_impl+0xde>
			if (min_width < 0 && precision < 0 && !padding_mode) {
    16e2:	2c00      	cmp	r4, #0
    16e4:	da0d      	bge.n	1702 <z_cbvprintf_impl+0x196>
    16e6:	f1b8 0f00 	cmp.w	r8, #0
    16ea:	da0d      	bge.n	1708 <z_cbvprintf_impl+0x19c>
    16ec:	9a02      	ldr	r2, [sp, #8]
    16ee:	2a00      	cmp	r2, #0
    16f0:	f000 8142 	beq.w	1978 <z_cbvprintf_impl+0x40c>
				if (min_width < 0) {
    16f4:	ea24 74e4 	bic.w	r4, r4, r4, asr #31
				min_width = 10 * min_width + *fmt - '0';
    16f8:	220a      	movs	r2, #10
    16fa:	fb02 1404 	mla	r4, r2, r4, r1
    16fe:	3c30      	subs	r4, #48	; 0x30
    1700:	e7a3      	b.n	164a <z_cbvprintf_impl+0xde>
			if (precision >= 0) {
    1702:	f1b8 0f00 	cmp.w	r8, #0
    1706:	dbf5      	blt.n	16f4 <z_cbvprintf_impl+0x188>
				precision = 10 * precision + *fmt - '0';
    1708:	220a      	movs	r2, #10
    170a:	fb02 1208 	mla	r2, r2, r8, r1
    170e:	f1a2 0830 	sub.w	r8, r2, #48	; 0x30
    1712:	e79a      	b.n	164a <z_cbvprintf_impl+0xde>
			if (precision >= 0) {
    1714:	f1b8 0f00 	cmp.w	r8, #0
				precision = va_arg(ap, int);
    1718:	f855 2b04 	ldr.w	r2, [r5], #4
			if (precision >= 0) {
    171c:	f280 812e 	bge.w	197c <z_cbvprintf_impl+0x410>
				if (min_width < 0) {
    1720:	2a00      	cmp	r2, #0
    1722:	f280 812d 	bge.w	1980 <z_cbvprintf_impl+0x414>
					min_width = -min_width;
    1726:	4254      	negs	r4, r2
		switch (*fmt) {
    1728:	2202      	movs	r2, #2
				padding_mode = PAD_ZERO;
    172a:	9202      	str	r2, [sp, #8]
    172c:	e78d      	b.n	164a <z_cbvprintf_impl+0xde>
			if (*fmt == 'h' && length_mod == 'h') {
    172e:	2968      	cmp	r1, #104	; 0x68
    1730:	d103      	bne.n	173a <z_cbvprintf_impl+0x1ce>
    1732:	2b68      	cmp	r3, #104	; 0x68
    1734:	d106      	bne.n	1744 <z_cbvprintf_impl+0x1d8>
				length_mod = 'H';
    1736:	2348      	movs	r3, #72	; 0x48
    1738:	e787      	b.n	164a <z_cbvprintf_impl+0xde>
			} else if (*fmt == 'l' && length_mod == 'l') {
    173a:	296c      	cmp	r1, #108	; 0x6c
    173c:	d102      	bne.n	1744 <z_cbvprintf_impl+0x1d8>
    173e:	2b6c      	cmp	r3, #108	; 0x6c
    1740:	f000 8120 	beq.w	1984 <z_cbvprintf_impl+0x418>
			} else if (length_mod == '\0') {
    1744:	2b00      	cmp	r3, #0
    1746:	f47f af32 	bne.w	15ae <z_cbvprintf_impl+0x42>
		switch (*fmt) {
    174a:	460b      	mov	r3, r1
    174c:	e77d      	b.n	164a <z_cbvprintf_impl+0xde>
			if (length_mod == 'z') {
    174e:	2b7a      	cmp	r3, #122	; 0x7a
    1750:	d106      	bne.n	1760 <z_cbvprintf_impl+0x1f4>
			} else if (*fmt == 'u') {
    1752:	2975      	cmp	r1, #117	; 0x75
				precision = va_arg(ap, int);
    1754:	f855 6b04 	ldr.w	r6, [r5], #4
			} else if (*fmt == 'u') {
    1758:	d114      	bne.n	1784 <z_cbvprintf_impl+0x218>
				d = va_arg(ap, unsigned int);
    175a:	f04f 0b00 	mov.w	fp, #0
			if (*fmt != 'u' && (int_value_type)d < 0) {
    175e:	e00c      	b.n	177a <z_cbvprintf_impl+0x20e>
			} else if (length_mod == 'l') {
    1760:	2b6c      	cmp	r3, #108	; 0x6c
    1762:	d0f6      	beq.n	1752 <z_cbvprintf_impl+0x1e6>
			} else if (length_mod == 'L') {
    1764:	2b4c      	cmp	r3, #76	; 0x4c
    1766:	d1f4      	bne.n	1752 <z_cbvprintf_impl+0x1e6>
					unsigned long long llu =
    1768:	3507      	adds	r5, #7
    176a:	f025 0307 	bic.w	r3, r5, #7
				if (*fmt == 'u') {
    176e:	2975      	cmp	r1, #117	; 0x75
					unsigned long long llu =
    1770:	e9d3 6b00 	ldrd	r6, fp, [r3]
    1774:	f103 0508 	add.w	r5, r3, #8
				if (*fmt == 'u') {
    1778:	d106      	bne.n	1788 <z_cbvprintf_impl+0x21c>
			} else if (special == ' ') {
    177a:	2820      	cmp	r0, #32
    177c:	d13b      	bne.n	17f6 <z_cbvprintf_impl+0x28a>
				prefix = " ";
    177e:	4f84      	ldr	r7, [pc, #528]	; (1990 <z_cbvprintf_impl+0x424>)
				min_width--;
    1780:	3c01      	subs	r4, #1
    1782:	e009      	b.n	1798 <z_cbvprintf_impl+0x22c>
				d = va_arg(ap, int);
    1784:	ea4f 7be6 	mov.w	fp, r6, asr #31
			if (*fmt != 'u' && (int_value_type)d < 0) {
    1788:	f1bb 0f00 	cmp.w	fp, #0
    178c:	daf5      	bge.n	177a <z_cbvprintf_impl+0x20e>
				d = -d;
    178e:	4276      	negs	r6, r6
				prefix = "-";
    1790:	4f80      	ldr	r7, [pc, #512]	; (1994 <z_cbvprintf_impl+0x428>)
				d = -d;
    1792:	eb6b 0b4b 	sbc.w	fp, fp, fp, lsl #1
				min_width--;
    1796:	3c01      	subs	r4, #1
	int i = 0;
    1798:	f10d 032d 	add.w	r3, sp, #45	; 0x2d
    179c:	9305      	str	r3, [sp, #20]
    179e:	2300      	movs	r3, #0
    17a0:	9304      	str	r3, [sp, #16]
		unsigned int c = num % base;
    17a2:	4630      	mov	r0, r6
    17a4:	4659      	mov	r1, fp
    17a6:	220a      	movs	r2, #10
    17a8:	2300      	movs	r3, #0
    17aa:	f7fe fca9 	bl	100 <__aeabi_uldivmod>
    17ae:	9b04      	ldr	r3, [sp, #16]
    17b0:	468e      	mov	lr, r1
		buftop[--i] = c + '0';
    17b2:	1e59      	subs	r1, r3, #1
    17b4:	9104      	str	r1, [sp, #16]
    17b6:	9905      	ldr	r1, [sp, #20]
    17b8:	3230      	adds	r2, #48	; 0x30
    17ba:	46b4      	mov	ip, r6
    17bc:	f801 2d01 	strb.w	r2, [r1, #-1]!
	} while (num);
    17c0:	f1bc 0f0a 	cmp.w	ip, #10
    17c4:	465a      	mov	r2, fp
    17c6:	f172 0200 	sbcs.w	r2, r2, #0
		buftop[--i] = c + '0';
    17ca:	9105      	str	r1, [sp, #20]
		num /= base;
    17cc:	4606      	mov	r6, r0
    17ce:	46f3      	mov	fp, lr
	} while (num);
    17d0:	d2e7      	bcs.n	17a2 <z_cbvprintf_impl+0x236>
	return -i;
    17d2:	f1c3 0b01 	rsb	fp, r3, #1
			data = buf + sizeof(buf) - data_len;
    17d6:	3330      	adds	r3, #48	; 0x30
			data = buf + sizeof(buf) - data_len;
    17d8:	eb0d 0603 	add.w	r6, sp, r3
		}

		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    17dc:	f1b8 0f00 	cmp.w	r8, #0
			data = buf + sizeof(buf) - data_len;
    17e0:	f1a6 0604 	sub.w	r6, r6, #4
		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    17e4:	da6d      	bge.n	18c2 <z_cbvprintf_impl+0x356>
    17e6:	9b02      	ldr	r3, [sp, #8]
    17e8:	07d9      	lsls	r1, r3, #31
    17ea:	d47c      	bmi.n	18e6 <z_cbvprintf_impl+0x37a>
			precision = min_width;
		}
		min_width -= data_len;
		precision -= data_len;
    17ec:	eba8 030b 	sub.w	r3, r8, fp
		min_width -= data_len;
    17f0:	eba4 040b 	sub.w	r4, r4, fp
    17f4:	e013      	b.n	181e <z_cbvprintf_impl+0x2b2>
			} else if (special == '+') {
    17f6:	282b      	cmp	r0, #43	; 0x2b
				prefix = "+";
    17f8:	bf0a      	itet	eq
    17fa:	4f67      	ldreq	r7, [pc, #412]	; (1998 <z_cbvprintf_impl+0x42c>)
	prefix = "";
    17fc:	4f67      	ldrne	r7, [pc, #412]	; (199c <z_cbvprintf_impl+0x430>)
				min_width--;
    17fe:	f104 34ff 	addeq.w	r4, r4, #4294967295
    1802:	e7c9      	b.n	1798 <z_cbvprintf_impl+0x22c>
			if (*fmt == 'p') {
    1804:	2970      	cmp	r1, #112	; 0x70
    1806:	d10f      	bne.n	1828 <z_cbvprintf_impl+0x2bc>
				x = (uintptr_t)va_arg(ap, void *);
    1808:	f855 2b04 	ldr.w	r2, [r5], #4
    180c:	2300      	movs	r3, #0
				if (x == (uint_value_type)0) {
    180e:	b9fa      	cbnz	r2, 1850 <z_cbvprintf_impl+0x2e4>
					data = "(nil)";
    1810:	4e63      	ldr	r6, [pc, #396]	; (19a0 <z_cbvprintf_impl+0x434>)
		min_width -= data_len;
    1812:	3c05      	subs	r4, #5
		precision -= data_len;
    1814:	f06f 0304 	mvn.w	r3, #4
					data_len = 5;
    1818:	f04f 0b05 	mov.w	fp, #5
	prefix = "";
    181c:	4f5f      	ldr	r7, [pc, #380]	; (199c <z_cbvprintf_impl+0x430>)
		if (precision > 0) {
			min_width -= precision;
		}

		if (!(padding_mode & PAD_TAIL)) {
    181e:	9a02      	ldr	r2, [sp, #8]
    1820:	0792      	lsls	r2, r2, #30
    1822:	d46f      	bmi.n	1904 <z_cbvprintf_impl+0x398>
    1824:	46a0      	mov	r8, r4
    1826:	e065      	b.n	18f4 <z_cbvprintf_impl+0x388>
		switch (*fmt) {
    1828:	2178      	movs	r1, #120	; 0x78
			} else if (length_mod == 'l') {
    182a:	2b6c      	cmp	r3, #108	; 0x6c
    182c:	d103      	bne.n	1836 <z_cbvprintf_impl+0x2ca>
				x = va_arg(ap, unsigned int);
    182e:	f855 2b04 	ldr.w	r2, [r5], #4
    1832:	2300      	movs	r3, #0
    1834:	e008      	b.n	1848 <z_cbvprintf_impl+0x2dc>
			} else if (length_mod == 'L') {
    1836:	2b4c      	cmp	r3, #76	; 0x4c
    1838:	d1f9      	bne.n	182e <z_cbvprintf_impl+0x2c2>
				unsigned long long llx =
    183a:	3507      	adds	r5, #7
    183c:	f025 0307 	bic.w	r3, r5, #7
    1840:	461d      	mov	r5, r3
    1842:	685b      	ldr	r3, [r3, #4]
    1844:	f855 2b08 	ldr.w	r2, [r5], #8
			if (special == '#') {
    1848:	2823      	cmp	r0, #35	; 0x23
    184a:	d125      	bne.n	1898 <z_cbvprintf_impl+0x32c>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    184c:	0688      	lsls	r0, r1, #26
    184e:	d521      	bpl.n	1894 <z_cbvprintf_impl+0x328>
    1850:	4f54      	ldr	r7, [pc, #336]	; (19a4 <z_cbvprintf_impl+0x438>)
				min_width -= 2;
    1852:	3c02      	subs	r4, #2
			data_len = convert_value(x, 16, ALPHA(*fmt),
    1854:	f001 0160 	and.w	r1, r1, #96	; 0x60
    1858:	f1a1 0b39 	sub.w	fp, r1, #57	; 0x39
	int i = 0;
    185c:	f10d 0e2d 	add.w	lr, sp, #45	; 0x2d
    1860:	2600      	movs	r6, #0
		unsigned int c = num % base;
    1862:	f002 010f 	and.w	r1, r2, #15
		if (c >= 10) {
    1866:	2909      	cmp	r1, #9
			c += alpha;
    1868:	bf88      	it	hi
    186a:	4459      	addhi	r1, fp
		buftop[--i] = c + '0';
    186c:	3130      	adds	r1, #48	; 0x30
    186e:	f80e 1d01 	strb.w	r1, [lr, #-1]!
	} while (num);
    1872:	2a10      	cmp	r2, #16
		num /= base;
    1874:	ea4f 1112 	mov.w	r1, r2, lsr #4
    1878:	ea41 7103 	orr.w	r1, r1, r3, lsl #28
    187c:	ea4f 1013 	mov.w	r0, r3, lsr #4
	} while (num);
    1880:	f173 0300 	sbcs.w	r3, r3, #0
		buftop[--i] = c + '0';
    1884:	f106 3cff 	add.w	ip, r6, #4294967295
	} while (num);
    1888:	d208      	bcs.n	189c <z_cbvprintf_impl+0x330>
	return -i;
    188a:	f1c6 0b01 	rsb	fp, r6, #1
			data = buf + sizeof(buf) - data_len;
    188e:	f106 0330 	add.w	r3, r6, #48	; 0x30
    1892:	e7a1      	b.n	17d8 <z_cbvprintf_impl+0x26c>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    1894:	4f44      	ldr	r7, [pc, #272]	; (19a8 <z_cbvprintf_impl+0x43c>)
    1896:	e7dc      	b.n	1852 <z_cbvprintf_impl+0x2e6>
	prefix = "";
    1898:	4f40      	ldr	r7, [pc, #256]	; (199c <z_cbvprintf_impl+0x430>)
    189a:	e7db      	b.n	1854 <z_cbvprintf_impl+0x2e8>
		buftop[--i] = c + '0';
    189c:	4666      	mov	r6, ip
		num /= base;
    189e:	460a      	mov	r2, r1
    18a0:	4603      	mov	r3, r0
    18a2:	e7de      	b.n	1862 <z_cbvprintf_impl+0x2f6>
			data = va_arg(ap, char *);
    18a4:	f855 6b04 	ldr.w	r6, [r5], #4
			data_len = strlen(data);
    18a8:	4630      	mov	r0, r6
    18aa:	f007 faad 	bl	8e08 <strlen>
			if (precision >= 0 && data_len > precision) {
    18ae:	f1b8 0f00 	cmp.w	r8, #0
			data_len = strlen(data);
    18b2:	4683      	mov	fp, r0
			if (precision >= 0 && data_len > precision) {
    18b4:	db02      	blt.n	18bc <z_cbvprintf_impl+0x350>
    18b6:	4540      	cmp	r0, r8
    18b8:	bfa8      	it	ge
    18ba:	46c3      	movge	fp, r8
	prefix = "";
    18bc:	4f37      	ldr	r7, [pc, #220]	; (199c <z_cbvprintf_impl+0x430>)
			precision = 0;
    18be:	f04f 0800 	mov.w	r8, #0
		precision -= data_len;
    18c2:	eba8 030b 	sub.w	r3, r8, fp
		if (precision > 0) {
    18c6:	2b00      	cmp	r3, #0
    18c8:	dd92      	ble.n	17f0 <z_cbvprintf_impl+0x284>
			min_width -= precision;
    18ca:	eba4 0408 	sub.w	r4, r4, r8
    18ce:	e7a6      	b.n	181e <z_cbvprintf_impl+0x2b2>
			buf[0] = c;
    18d0:	f855 3b04 	ldr.w	r3, [r5], #4
    18d4:	f88d 3018 	strb.w	r3, [sp, #24]
		min_width -= data_len;
    18d8:	3c01      	subs	r4, #1
		precision -= data_len;
    18da:	f04f 33ff 	mov.w	r3, #4294967295
			data_len = 1;
    18de:	f04f 0b01 	mov.w	fp, #1
			data = buf;
    18e2:	ae06      	add	r6, sp, #24
    18e4:	e79a      	b.n	181c <z_cbvprintf_impl+0x2b0>
    18e6:	46a0      	mov	r8, r4
    18e8:	e7eb      	b.n	18c2 <z_cbvprintf_impl+0x356>
    18ea:	9302      	str	r3, [sp, #8]
			while (--min_width >= 0) {
				OUTC(' ');
    18ec:	9901      	ldr	r1, [sp, #4]
    18ee:	2020      	movs	r0, #32
    18f0:	47d0      	blx	sl
    18f2:	9b02      	ldr	r3, [sp, #8]
			while (--min_width >= 0) {
    18f4:	f1b8 0801 	subs.w	r8, r8, #1
    18f8:	d5f7      	bpl.n	18ea <z_cbvprintf_impl+0x37e>
    18fa:	ea24 72e4 	bic.w	r2, r4, r4, asr #31
    18fe:	3c01      	subs	r4, #1
    1900:	4491      	add	r9, r2
    1902:	1aa4      	subs	r4, r4, r2
    1904:	46b8      	mov	r8, r7
    1906:	e006      	b.n	1916 <z_cbvprintf_impl+0x3aa>
    1908:	9304      	str	r3, [sp, #16]
    190a:	9202      	str	r2, [sp, #8]
			}
		}
		while (*prefix) {
			OUTC(*prefix++);
    190c:	9901      	ldr	r1, [sp, #4]
    190e:	47d0      	blx	sl
    1910:	9a02      	ldr	r2, [sp, #8]
    1912:	9b04      	ldr	r3, [sp, #16]
    1914:	4690      	mov	r8, r2
		while (*prefix) {
    1916:	4642      	mov	r2, r8
    1918:	f812 0b01 	ldrb.w	r0, [r2], #1
    191c:	2800      	cmp	r0, #0
    191e:	d1f3      	bne.n	1908 <z_cbvprintf_impl+0x39c>
    1920:	461a      	mov	r2, r3
		}
		while (--precision >= 0) {
    1922:	3a01      	subs	r2, #1
    1924:	d515      	bpl.n	1952 <z_cbvprintf_impl+0x3e6>
    1926:	2b00      	cmp	r3, #0
    1928:	bfac      	ite	ge
    192a:	ebc7 0703 	rsbge	r7, r7, r3
    192e:	427f      	neglt	r7, r7
    1930:	465b      	mov	r3, fp
			OUTC('0');
		}
		while (--data_len >= 0) {
    1932:	3b01      	subs	r3, #1
    1934:	d515      	bpl.n	1962 <z_cbvprintf_impl+0x3f6>
    1936:	f1bb 0f00 	cmp.w	fp, #0
    193a:	bfa8      	it	ge
    193c:	445f      	addge	r7, fp
    193e:	444f      	add	r7, r9
    1940:	4626      	mov	r6, r4
			OUTC(*data++);
		}
		while (--min_width >= 0) {
    1942:	3e01      	subs	r6, #1
    1944:	d514      	bpl.n	1970 <z_cbvprintf_impl+0x404>
    1946:	2c00      	cmp	r4, #0
    1948:	bfa8      	it	ge
    194a:	193f      	addge	r7, r7, r4
    194c:	eb07 0908 	add.w	r9, r7, r8
    1950:	e616      	b.n	1580 <z_cbvprintf_impl+0x14>
    1952:	9304      	str	r3, [sp, #16]
    1954:	9202      	str	r2, [sp, #8]
			OUTC('0');
    1956:	9901      	ldr	r1, [sp, #4]
    1958:	2030      	movs	r0, #48	; 0x30
    195a:	47d0      	blx	sl
    195c:	9b04      	ldr	r3, [sp, #16]
    195e:	9a02      	ldr	r2, [sp, #8]
    1960:	e7df      	b.n	1922 <z_cbvprintf_impl+0x3b6>
    1962:	9302      	str	r3, [sp, #8]
			OUTC(*data++);
    1964:	9901      	ldr	r1, [sp, #4]
    1966:	f816 0b01 	ldrb.w	r0, [r6], #1
    196a:	47d0      	blx	sl
    196c:	9b02      	ldr	r3, [sp, #8]
    196e:	e7e0      	b.n	1932 <z_cbvprintf_impl+0x3c6>
			OUTC(' ');
    1970:	9901      	ldr	r1, [sp, #4]
    1972:	2020      	movs	r0, #32
    1974:	47d0      	blx	sl
    1976:	e7e4      	b.n	1942 <z_cbvprintf_impl+0x3d6>
				padding_mode = PAD_ZERO;
    1978:	2201      	movs	r2, #1
    197a:	e6d6      	b.n	172a <z_cbvprintf_impl+0x1be>
				precision = va_arg(ap, int);
    197c:	4690      	mov	r8, r2
    197e:	e664      	b.n	164a <z_cbvprintf_impl+0xde>
    1980:	4614      	mov	r4, r2
    1982:	e662      	b.n	164a <z_cbvprintf_impl+0xde>
				length_mod = 'L';
    1984:	234c      	movs	r3, #76	; 0x4c
    1986:	e660      	b.n	164a <z_cbvprintf_impl+0xde>
		}

		goto start;
	}
}
    1988:	4648      	mov	r0, r9
    198a:	b00d      	add	sp, #52	; 0x34
    198c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1990:	0000aeb4 	.word	0x0000aeb4
    1994:	0000aa5d 	.word	0x0000aa5d
    1998:	0000aa5f 	.word	0x0000aa5f
    199c:	0000b29c 	.word	0x0000b29c
    19a0:	0000aa67 	.word	0x0000aa67
    19a4:	0000aa61 	.word	0x0000aa61
    19a8:	0000aa64 	.word	0x0000aa64

000019ac <sys_reboot>:
#include <zephyr/sys/printk.h>

extern void sys_arch_reboot(int type);

FUNC_NORETURN void sys_reboot(int type)
{
    19ac:	b508      	push	{r3, lr}
	__asm__ volatile(
    19ae:	f04f 0220 	mov.w	r2, #32
    19b2:	f3ef 8311 	mrs	r3, BASEPRI
    19b6:	f382 8812 	msr	BASEPRI_MAX, r2
    19ba:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
	sys_clock_disable();

	sys_arch_reboot(type);
    19be:	f001 f871 	bl	2aa4 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
    19c2:	4803      	ldr	r0, [pc, #12]	; (19d0 <sys_reboot+0x24>)
    19c4:	f007 f893 	bl	8aee <printk>
 * @note In some architectures, before returning, the function unmasks interrupts
 * unconditionally.
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
    19c8:	f000 fa88 	bl	1edc <arch_cpu_idle>
    19cc:	e7fc      	b.n	19c8 <sys_reboot+0x1c>
    19ce:	bf00      	nop
    19d0:	0000aa6d 	.word	0x0000aa6d

000019d4 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    19d4:	f002 bffc 	b.w	49d0 <SystemInit>

000019d8 <flash_area_open>:
		user_cb(&flash_map[i], user_data);
	}
}

int flash_area_open(uint8_t id, const struct flash_area **fap)
{
    19d8:	b570      	push	{r4, r5, r6, lr}
	const struct flash_area *area;

	if (flash_map == NULL) {
    19da:	4b11      	ldr	r3, [pc, #68]	; (1a20 <flash_area_open+0x48>)
    19dc:	681c      	ldr	r4, [r3, #0]
{
    19de:	460d      	mov	r5, r1
	if (flash_map == NULL) {
    19e0:	b1dc      	cbz	r4, 1a1a <flash_area_open+0x42>
extern const struct flash_area *flash_map;
extern const int flash_map_entries;

static inline struct flash_area const *get_flash_area_from_id(int idx)
{
	for (int i = 0; i < flash_map_entries; i++) {
    19e2:	4b10      	ldr	r3, [pc, #64]	; (1a24 <flash_area_open+0x4c>)
    19e4:	6819      	ldr	r1, [r3, #0]
    19e6:	2300      	movs	r3, #0
    19e8:	428b      	cmp	r3, r1
    19ea:	db02      	blt.n	19f2 <flash_area_open+0x1a>
		return -EACCES;
	}

	area = get_flash_area_from_id(id);
	if (area == NULL) {
		return -ENOENT;
    19ec:	f06f 0001 	mvn.w	r0, #1
	}

	*fap = area;

	return 0;
}
    19f0:	bd70      	pop	{r4, r5, r6, pc}
		if (flash_map[i].fa_id == idx) {
    19f2:	4622      	mov	r2, r4
    19f4:	f812 6b10 	ldrb.w	r6, [r2], #16
    19f8:	4286      	cmp	r6, r0
    19fa:	d002      	beq.n	1a02 <flash_area_open+0x2a>
	for (int i = 0; i < flash_map_entries; i++) {
    19fc:	3301      	adds	r3, #1
    19fe:	4614      	mov	r4, r2
    1a00:	e7f2      	b.n	19e8 <flash_area_open+0x10>
	if (!area->fa_dev || !device_is_ready(area->fa_dev)) {
    1a02:	68e0      	ldr	r0, [r4, #12]
    1a04:	b910      	cbnz	r0, 1a0c <flash_area_open+0x34>
		return -ENODEV;
    1a06:	f06f 0012 	mvn.w	r0, #18
    1a0a:	e7f1      	b.n	19f0 <flash_area_open+0x18>
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
    1a0c:	f008 f81b 	bl	9a46 <z_device_is_ready>
	if (!area->fa_dev || !device_is_ready(area->fa_dev)) {
    1a10:	2800      	cmp	r0, #0
    1a12:	d0f8      	beq.n	1a06 <flash_area_open+0x2e>
	*fap = area;
    1a14:	602c      	str	r4, [r5, #0]
	return 0;
    1a16:	2000      	movs	r0, #0
    1a18:	e7ea      	b.n	19f0 <flash_area_open+0x18>
		return -EACCES;
    1a1a:	f06f 000c 	mvn.w	r0, #12
    1a1e:	e7e7      	b.n	19f0 <flash_area_open+0x18>
    1a20:	20000010 	.word	0x20000010
    1a24:	0000a138 	.word	0x0000a138

00001a28 <flash_area_get_sectors>:

	return true;
}

int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
{
    1a28:	b570      	push	{r4, r5, r6, lr}
    1a2a:	b088      	sub	sp, #32
    1a2c:	4605      	mov	r5, r0
    1a2e:	460c      	mov	r4, r1
	int rc = flash_area_open(idx, &fa);
    1a30:	b2c0      	uxtb	r0, r0
    1a32:	4669      	mov	r1, sp
{
    1a34:	4616      	mov	r6, r2
	int rc = flash_area_open(idx, &fa);
    1a36:	f7ff ffcf 	bl	19d8 <flash_area_open>
	if (rc < 0 || fa == NULL) {
    1a3a:	2800      	cmp	r0, #0
    1a3c:	db1b      	blt.n	1a76 <flash_area_get_sectors+0x4e>
    1a3e:	9800      	ldr	r0, [sp, #0]
    1a40:	b1c8      	cbz	r0, 1a76 <flash_area_get_sectors+0x4e>
	cb_data->area_off = fa->fa_off;
    1a42:	6843      	ldr	r3, [r0, #4]
    1a44:	9302      	str	r3, [sp, #8]
	cb_data->area_len = fa->fa_size;
    1a46:	6883      	ldr	r3, [r0, #8]
	cb_data->ret_len = *cnt;
    1a48:	6822      	ldr	r2, [r4, #0]
	cb_data->area_idx = idx;
    1a4a:	9501      	str	r5, [sp, #4]
	cb_data->ret = ret;
    1a4c:	e9cd 3603 	strd	r3, r6, [sp, #12]
	cb_data->ret_idx = 0U;
    1a50:	2300      	movs	r3, #0
	cb_data->status = 0;
    1a52:	e9cd 2306 	strd	r2, r3, [sp, #24]
	cb_data->ret_idx = 0U;
    1a56:	9305      	str	r3, [sp, #20]
	flash_dev = fa->fa_dev;
    1a58:	68c5      	ldr	r5, [r0, #12]
	flash_area_close(fa);
    1a5a:	f007 f947 	bl	8cec <flash_area_close>
	if (flash_dev == NULL) {
    1a5e:	b16d      	cbz	r5, 1a7c <flash_area_get_sectors+0x54>
	flash_page_foreach(flash_dev, cb, cb_data);
    1a60:	4628      	mov	r0, r5
    1a62:	4908      	ldr	r1, [pc, #32]	; (1a84 <flash_area_get_sectors+0x5c>)
    1a64:	aa01      	add	r2, sp, #4
    1a66:	f007 fd1a 	bl	949e <flash_page_foreach>
	if (cb_data->status == 0) {
    1a6a:	9807      	ldr	r0, [sp, #28]
    1a6c:	b908      	cbnz	r0, 1a72 <flash_area_get_sectors+0x4a>
		*cnt = cb_data->ret_idx;
    1a6e:	9b05      	ldr	r3, [sp, #20]
    1a70:	6023      	str	r3, [r4, #0]
	struct layout_data data;

	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
}
    1a72:	b008      	add	sp, #32
    1a74:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    1a76:	f06f 0015 	mvn.w	r0, #21
    1a7a:	e7fa      	b.n	1a72 <flash_area_get_sectors+0x4a>
		return -ENODEV;
    1a7c:	f06f 0012 	mvn.w	r0, #18
	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
    1a80:	e7f7      	b.n	1a72 <flash_area_get_sectors+0x4a>
    1a82:	bf00      	nop
    1a84:	00008d8b 	.word	0x00008d8b

00001a88 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
    1a88:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    1a8c:	4605      	mov	r5, r0
    1a8e:	f04f 0320 	mov.w	r3, #32
    1a92:	f3ef 8611 	mrs	r6, BASEPRI
    1a96:	f383 8812 	msr	BASEPRI_MAX, r3
    1a9a:	f3bf 8f6f 	isb	sy
	return list->head;
    1a9e:	4b0e      	ldr	r3, [pc, #56]	; (1ad8 <pm_state_notify+0x50>)
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_cpus_pm_state[_current_cpu->id].state);
    1aa0:	4f0e      	ldr	r7, [pc, #56]	; (1adc <pm_state_notify+0x54>)
    1aa2:	681c      	ldr	r4, [r3, #0]
    1aa4:	f8df 8038 	ldr.w	r8, [pc, #56]	; 1ae0 <pm_state_notify+0x58>
    1aa8:	f04f 090c 	mov.w	r9, #12
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1aac:	b92c      	cbnz	r4, 1aba <pm_state_notify+0x32>
	__asm__ volatile(
    1aae:	f386 8811 	msr	BASEPRI, r6
    1ab2:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
    1ab6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			callback = notifier->state_exit;
    1aba:	e9d4 2301 	ldrd	r2, r3, [r4, #4]
			callback = notifier->state_entry;
    1abe:	2d00      	cmp	r5, #0
    1ac0:	bf18      	it	ne
    1ac2:	4613      	movne	r3, r2
		if (callback) {
    1ac4:	b12b      	cbz	r3, 1ad2 <pm_state_notify+0x4a>
			callback(z_cpus_pm_state[_current_cpu->id].state);
    1ac6:	f898 2014 	ldrb.w	r2, [r8, #20]
    1aca:	fb09 f202 	mul.w	r2, r9, r2
    1ace:	5cb8      	ldrb	r0, [r7, r2]
    1ad0:	4798      	blx	r3
	return node->next;
    1ad2:	6824      	ldr	r4, [r4, #0]
    1ad4:	e7ea      	b.n	1aac <pm_state_notify+0x24>
    1ad6:	bf00      	nop
    1ad8:	200018b8 	.word	0x200018b8
    1adc:	200018ac 	.word	0x200018ac
    1ae0:	20001fa0 	.word	0x20001fa0

00001ae4 <pm_system_resume>:

void pm_system_resume(void)
{
    1ae4:	b570      	push	{r4, r5, r6, lr}
	uint8_t id = CURRENT_CPU;
    1ae6:	4b19      	ldr	r3, [pc, #100]	; (1b4c <pm_system_resume+0x68>)
    1ae8:	7d1c      	ldrb	r4, [r3, #20]
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    1aea:	f3bf 8f5b 	dmb	ish
 *
 * @return true if the bit was set, false if it wasn't.
 */
static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
    1aee:	f004 031f 	and.w	r3, r4, #31
    1af2:	2201      	movs	r2, #1
    1af4:	409a      	lsls	r2, r3
    1af6:	4b16      	ldr	r3, [pc, #88]	; (1b50 <pm_system_resume+0x6c>)
	atomic_val_t old;

	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    1af8:	0961      	lsrs	r1, r4, #5
    1afa:	eb03 0381 	add.w	r3, r3, r1, lsl #2
    1afe:	43d0      	mvns	r0, r2
    1b00:	e853 1f00 	ldrex	r1, [r3]
    1b04:	ea01 0500 	and.w	r5, r1, r0
    1b08:	e843 5600 	strex	r6, r5, [r3]
    1b0c:	2e00      	cmp	r6, #0
    1b0e:	d1f7      	bne.n	1b00 <pm_system_resume+0x1c>
    1b10:	f3bf 8f5b 	dmb	ish
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
    1b14:	420a      	tst	r2, r1
    1b16:	d013      	beq.n	1b40 <pm_system_resume+0x5c>
	if (pm_state_exit_post_ops != NULL) {
    1b18:	4b0e      	ldr	r3, [pc, #56]	; (1b54 <pm_system_resume+0x70>)
    1b1a:	4d0f      	ldr	r5, [pc, #60]	; (1b58 <pm_system_resume+0x74>)
    1b1c:	b18b      	cbz	r3, 1b42 <pm_system_resume+0x5e>
		pm_state_exit_post_ops(info->state, info->substate_id);
    1b1e:	230c      	movs	r3, #12
    1b20:	4363      	muls	r3, r4
    1b22:	18ea      	adds	r2, r5, r3
    1b24:	5ce8      	ldrb	r0, [r5, r3]
    1b26:	7851      	ldrb	r1, [r2, #1]
    1b28:	f007 f9a8 	bl	8e7c <pm_state_exit_post_ops>
		pm_exit_pos_ops(&z_cpus_pm_state[id]);
		pm_state_notify(false);
    1b2c:	2000      	movs	r0, #0
    1b2e:	f7ff ffab 	bl	1a88 <pm_state_notify>
		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE,
    1b32:	230c      	movs	r3, #12
    1b34:	435c      	muls	r4, r3
    1b36:	192a      	adds	r2, r5, r4
    1b38:	2300      	movs	r3, #0
    1b3a:	512b      	str	r3, [r5, r4]
    1b3c:	e9c2 3301 	strd	r3, r3, [r2, #4]
			0, 0};
	}
}
    1b40:	bd70      	pop	{r4, r5, r6, pc}
    1b42:	f383 8811 	msr	BASEPRI, r3
    1b46:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    1b4a:	e7ef      	b.n	1b2c <pm_system_resume+0x48>
    1b4c:	20001fa0 	.word	0x20001fa0
    1b50:	200018c0 	.word	0x200018c0
    1b54:	00008e7d 	.word	0x00008e7d
    1b58:	200018ac 	.word	0x200018ac

00001b5c <pm_system_suspend>:

	return true;
}

bool pm_system_suspend(int32_t ticks)
{
    1b5c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint8_t id = CURRENT_CPU;
    1b60:	4b35      	ldr	r3, [pc, #212]	; (1c38 <pm_system_suspend+0xdc>)
{
    1b62:	4607      	mov	r7, r0
	uint8_t id = CURRENT_CPU;
    1b64:	7d1d      	ldrb	r5, [r3, #20]
	__asm__ volatile(
    1b66:	f04f 0320 	mov.w	r3, #32
    1b6a:	f3ef 8811 	mrs	r8, BASEPRI
    1b6e:	f383 8812 	msr	BASEPRI_MAX, r3
    1b72:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key;

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	key = k_spin_lock(&pm_forced_state_lock);
	if (z_cpus_pm_forced_state[id].state != PM_STATE_ACTIVE) {
    1b76:	240c      	movs	r4, #12
    1b78:	4b30      	ldr	r3, [pc, #192]	; (1c3c <pm_system_suspend+0xe0>)
    1b7a:	4e31      	ldr	r6, [pc, #196]	; (1c40 <pm_system_suspend+0xe4>)
    1b7c:	436c      	muls	r4, r5
    1b7e:	191a      	adds	r2, r3, r4
    1b80:	5d19      	ldrb	r1, [r3, r4]
    1b82:	2900      	cmp	r1, #0
    1b84:	d04c      	beq.n	1c20 <pm_system_suspend+0xc4>
		z_cpus_pm_state[id] = z_cpus_pm_forced_state[id];
    1b86:	ca07      	ldmia	r2, {r0, r1, r2}
    1b88:	eb06 0c04 	add.w	ip, r6, r4
    1b8c:	e88c 0007 	stmia.w	ip, {r0, r1, r2}
		z_cpus_pm_forced_state[id].state = PM_STATE_ACTIVE;
    1b90:	2200      	movs	r2, #0
    1b92:	551a      	strb	r2, [r3, r4]
	__asm__ volatile(
    1b94:	f388 8811 	msr	BASEPRI, r8
    1b98:	f3bf 8f6f 	isb	sy
			z_cpus_pm_state[id] = *info;
		}
	}
	k_spin_unlock(&pm_forced_state_lock, key);

	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
    1b9c:	230c      	movs	r3, #12
    1b9e:	436b      	muls	r3, r5
    1ba0:	18f2      	adds	r2, r6, r3
    1ba2:	5cf0      	ldrb	r0, [r6, r3]
    1ba4:	2800      	cmp	r0, #0
    1ba6:	d039      	beq.n	1c1c <pm_system_suspend+0xc0>
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);
		return false;
	}

	if (ticks != K_TICKS_FOREVER) {
    1ba8:	1c7b      	adds	r3, r7, #1
    1baa:	d010      	beq.n	1bce <pm_system_suspend+0x72>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    1bac:	f8d2 c008 	ldr.w	ip, [r2, #8]
    1bb0:	4c24      	ldr	r4, [pc, #144]	; (1c44 <pm_system_suspend+0xe8>)
    1bb2:	4a25      	ldr	r2, [pc, #148]	; (1c48 <pm_system_suspend+0xec>)
    1bb4:	f44f 4000 	mov.w	r0, #32768	; 0x8000
    1bb8:	2100      	movs	r1, #0
    1bba:	fbec 4100 	umlal	r4, r1, ip, r0
    1bbe:	2300      	movs	r3, #0
    1bc0:	4620      	mov	r0, r4
    1bc2:	f7fe fa9d 	bl	100 <__aeabi_uldivmod>
		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		z_set_timeout_expiry(ticks -
    1bc6:	2101      	movs	r1, #1
    1bc8:	1a38      	subs	r0, r7, r0
    1bca:	f008 f886 	bl	9cda <z_set_timeout_expiry>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    1bce:	f004 fd7f 	bl	66d0 <k_sched_lock>
	pm_stats_start();
	/* Enter power state */
	pm_state_notify(true);
    1bd2:	2001      	movs	r0, #1
    1bd4:	f7ff ff58 	bl	1a88 <pm_state_notify>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    1bd8:	f3bf 8f5b 	dmb	ish
    1bdc:	4b1b      	ldr	r3, [pc, #108]	; (1c4c <pm_system_suspend+0xf0>)
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);

	(void)atomic_or(ATOMIC_ELEM(target, bit), mask);
    1bde:	096a      	lsrs	r2, r5, #5
    1be0:	eb03 0382 	add.w	r3, r3, r2, lsl #2
	atomic_val_t mask = ATOMIC_MASK(bit);
    1be4:	f005 011f 	and.w	r1, r5, #31
    1be8:	2201      	movs	r2, #1
    1bea:	408a      	lsls	r2, r1
    1bec:	e853 0f00 	ldrex	r0, [r3]
    1bf0:	4310      	orrs	r0, r2
    1bf2:	e843 0100 	strex	r1, r0, [r3]
    1bf6:	2900      	cmp	r1, #0
    1bf8:	d1f8      	bne.n	1bec <pm_system_suspend+0x90>
    1bfa:	f3bf 8f5b 	dmb	ish
	if (pm_state_set != NULL) {
    1bfe:	4b14      	ldr	r3, [pc, #80]	; (1c50 <pm_system_suspend+0xf4>)
    1c00:	b13b      	cbz	r3, 1c12 <pm_system_suspend+0xb6>
		pm_state_set(info->state, info->substate_id);
    1c02:	230c      	movs	r3, #12
    1c04:	fb03 f005 	mul.w	r0, r3, r5
    1c08:	1833      	adds	r3, r6, r0
    1c0a:	5c30      	ldrb	r0, [r6, r0]
    1c0c:	7859      	ldrb	r1, [r3, #1]
    1c0e:	f007 f929 	bl	8e64 <pm_state_set>
	if (atomic_add(&z_cpus_active, 1) == 0) {
		pm_resume_devices();
	}
#endif
	pm_stats_update(z_cpus_pm_state[id].state);
	pm_system_resume();
    1c12:	f7ff ff67 	bl	1ae4 <pm_system_resume>
	k_sched_unlock();
    1c16:	f004 fd6f 	bl	66f8 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);

	return true;
    1c1a:	2001      	movs	r0, #1
}
    1c1c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		info = pm_policy_next_state(id, ticks);
    1c20:	4601      	mov	r1, r0
    1c22:	4628      	mov	r0, r5
    1c24:	f000 f816 	bl	1c54 <pm_policy_next_state>
		if (info != NULL) {
    1c28:	2800      	cmp	r0, #0
    1c2a:	d0b3      	beq.n	1b94 <pm_system_suspend+0x38>
			z_cpus_pm_state[id] = *info;
    1c2c:	c807      	ldmia	r0, {r0, r1, r2}
    1c2e:	4434      	add	r4, r6
    1c30:	e884 0007 	stmia.w	r4, {r0, r1, r2}
    1c34:	e7ae      	b.n	1b94 <pm_system_suspend+0x38>
    1c36:	bf00      	nop
    1c38:	20001fa0 	.word	0x20001fa0
    1c3c:	200018a0 	.word	0x200018a0
    1c40:	200018ac 	.word	0x200018ac
    1c44:	000f423f 	.word	0x000f423f
    1c48:	000f4240 	.word	0x000f4240
    1c4c:	200018c0 	.word	0x200018c0
    1c50:	00008e65 	.word	0x00008e65

00001c54 <pm_policy_next_state>:
	}
}

#ifdef CONFIG_PM_POLICY_DEFAULT
const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
{
    1c54:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1c58:	b085      	sub	sp, #20
    1c5a:	460e      	mov	r6, r1
	uint8_t num_cpu_states;
	const struct pm_state_info *cpu_states;

	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
    1c5c:	a903      	add	r1, sp, #12
    1c5e:	f000 f843 	bl	1ce8 <pm_state_cpu_get_all>

		min_residency = k_us_to_ticks_ceil32(state->min_residency_us);
		exit_latency = k_us_to_ticks_ceil32(state->exit_latency_us);

		/* skip state if it brings too much latency */
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    1c62:	4b1e      	ldr	r3, [pc, #120]	; (1cdc <pm_policy_next_state+0x88>)
    1c64:	9d03      	ldr	r5, [sp, #12]
    1c66:	f8d3 a000 	ldr.w	sl, [r3]
    1c6a:	f8df 8078 	ldr.w	r8, [pc, #120]	; 1ce4 <pm_policy_next_state+0x90>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    1c6e:	1e43      	subs	r3, r0, #1
    1c70:	b21b      	sxth	r3, r3
    1c72:	eb03 0343 	add.w	r3, r3, r3, lsl #1
	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
    1c76:	4604      	mov	r4, r0
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    1c78:	eb05 0583 	add.w	r5, r5, r3, lsl #2
    1c7c:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    1c80:	f04f 0b00 	mov.w	fp, #0
    1c84:	b924      	cbnz	r4, 1c90 <pm_policy_next_state+0x3c>
		    (ticks >= (min_residency + exit_latency))) {
			return state;
		}
	}

	return NULL;
    1c86:	46a1      	mov	r9, r4
}
    1c88:	4648      	mov	r0, r9
    1c8a:	b005      	add	sp, #20
    1c8c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1c90:	6868      	ldr	r0, [r5, #4]
    1c92:	4a13      	ldr	r2, [pc, #76]	; (1ce0 <pm_policy_next_state+0x8c>)
    1c94:	46c4      	mov	ip, r8
    1c96:	4659      	mov	r1, fp
    1c98:	fbe0 c107 	umlal	ip, r1, r0, r7
    1c9c:	2300      	movs	r3, #0
    1c9e:	4660      	mov	r0, ip
    1ca0:	f7fe fa2e 	bl	100 <__aeabi_uldivmod>
    1ca4:	9001      	str	r0, [sp, #4]
    1ca6:	68a8      	ldr	r0, [r5, #8]
    1ca8:	4a0d      	ldr	r2, [pc, #52]	; (1ce0 <pm_policy_next_state+0x8c>)
    1caa:	46c4      	mov	ip, r8
    1cac:	4659      	mov	r1, fp
    1cae:	fbe0 c107 	umlal	ip, r1, r0, r7
    1cb2:	2300      	movs	r3, #0
    1cb4:	4660      	mov	r0, ip
    1cb6:	f7fe fa23 	bl	100 <__aeabi_uldivmod>
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    1cba:	f1ba 3fff 	cmp.w	sl, #4294967295
		const struct pm_state_info *state = &cpu_states[i];
    1cbe:	46a9      	mov	r9, r5
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    1cc0:	d001      	beq.n	1cc6 <pm_policy_next_state+0x72>
    1cc2:	4582      	cmp	sl, r0
    1cc4:	d905      	bls.n	1cd2 <pm_policy_next_state+0x7e>
		if ((ticks == K_TICKS_FOREVER) ||
    1cc6:	1c73      	adds	r3, r6, #1
    1cc8:	d0de      	beq.n	1c88 <pm_policy_next_state+0x34>
		    (ticks >= (min_residency + exit_latency))) {
    1cca:	9b01      	ldr	r3, [sp, #4]
    1ccc:	4418      	add	r0, r3
		if ((ticks == K_TICKS_FOREVER) ||
    1cce:	42b0      	cmp	r0, r6
    1cd0:	d9da      	bls.n	1c88 <pm_policy_next_state+0x34>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    1cd2:	3c01      	subs	r4, #1
    1cd4:	b2a4      	uxth	r4, r4
    1cd6:	3d0c      	subs	r5, #12
    1cd8:	e7d4      	b.n	1c84 <pm_policy_next_state+0x30>
    1cda:	bf00      	nop
    1cdc:	2000000c 	.word	0x2000000c
    1ce0:	000f4240 	.word	0x000f4240
    1ce4:	000f423f 	.word	0x000f423f

00001ce8 <pm_state_cpu_get_all>:
	DT_FOREACH_CHILD_SEP(DT_PATH(cpus), DT_NUM_CPU_POWER_STATES, (,))
};

uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
{
	if (cpu >= ARRAY_SIZE(cpus_states)) {
    1ce8:	b908      	cbnz	r0, 1cee <pm_state_cpu_get_all+0x6>
		return 0;
	}

	*states = cpus_states[cpu];
    1cea:	4b02      	ldr	r3, [pc, #8]	; (1cf4 <pm_state_cpu_get_all+0xc>)
    1cec:	600b      	str	r3, [r1, #0]

	return states_per_cpu[cpu];
}
    1cee:	2000      	movs	r0, #0
    1cf0:	4770      	bx	lr
    1cf2:	bf00      	nop
    1cf4:	0000a138 	.word	0x0000a138

00001cf8 <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    1cf8:	4801      	ldr	r0, [pc, #4]	; (1d00 <nrf_cc3xx_platform_abort_init+0x8>)
    1cfa:	f004 bfd1 	b.w	6ca0 <nrf_cc3xx_platform_set_abort>
    1cfe:	bf00      	nop
    1d00:	0000a1cc 	.word	0x0000a1cc

00001d04 <mutex_free_platform>:
}


/** @brief Static function to free a mutex
 */
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1d04:	b538      	push	{r3, r4, r5, lr}
    /* Ensure that the mutex is valid (not NULL) */
    if (mutex == NULL) {
    1d06:	4604      	mov	r4, r0
    1d08:	b918      	cbnz	r0, 1d12 <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    1d0a:	4b0f      	ldr	r3, [pc, #60]	; (1d48 <mutex_free_platform+0x44>)
    1d0c:	480f      	ldr	r0, [pc, #60]	; (1d4c <mutex_free_platform+0x48>)
    1d0e:	685b      	ldr	r3, [r3, #4]
    1d10:	4798      	blx	r3
            "mutex_init called with NULL parameter");
    }

    /* Check if we are freeing a mutex that is atomic */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    1d12:	6861      	ldr	r1, [r4, #4]
    1d14:	f5b1 3f68 	cmp.w	r1, #237568	; 0x3a000
    1d18:	d00f      	beq.n	1d3a <mutex_free_platform+0x36>
    1d1a:	f5b1 0f68 	cmp.w	r1, #15204352	; 0xe80000
    1d1e:	d00c      	beq.n	1d3a <mutex_free_platform+0x36>
        /*Nothing to free*/
        return;
    }

    /* Check if we are freeing a mutex that isn't initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1d20:	4d0b      	ldr	r5, [pc, #44]	; (1d50 <mutex_free_platform+0x4c>)
    1d22:	42a9      	cmp	r1, r5
    1d24:	d009      	beq.n	1d3a <mutex_free_platform+0x36>
        /*Nothing to free*/
        return;
    }

    /* Check if the mutex was allocated or being statically defined */
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    1d26:	f411 6168 	ands.w	r1, r1, #3712	; 0xe80
    1d2a:	d007      	beq.n	1d3c <mutex_free_platform+0x38>
        k_mem_slab_free(&mutex_slab, &mutex->mutex);
    1d2c:	4809      	ldr	r0, [pc, #36]	; (1d54 <mutex_free_platform+0x50>)
    1d2e:	4621      	mov	r1, r4
    1d30:	f007 febc 	bl	9aac <k_mem_slab_free>
        mutex->mutex = NULL;
    1d34:	2300      	movs	r3, #0
    1d36:	6023      	str	r3, [r4, #0]
    else {
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    }

    /* Reset the mutex to invalid state */
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    1d38:	6065      	str	r5, [r4, #4]
}
    1d3a:	bd38      	pop	{r3, r4, r5, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1d3c:	6820      	ldr	r0, [r4, #0]
    1d3e:	2214      	movs	r2, #20
    1d40:	f007 f884 	bl	8e4c <memset>
    1d44:	e7f8      	b.n	1d38 <mutex_free_platform+0x34>
    1d46:	bf00      	nop
    1d48:	200001cc 	.word	0x200001cc
    1d4c:	0000aa99 	.word	0x0000aa99
    1d50:	a95c5f2c 	.word	0xa95c5f2c
    1d54:	20001dc4 	.word	0x20001dc4

00001d58 <mutex_lock_platform>:


/** @brief Static function to lock a mutex
 */
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1d58:	b508      	push	{r3, lr}
    int ret;
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1d5a:	b320      	cbz	r0, 1da6 <mutex_lock_platform+0x4e>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags) {
    1d5c:	6843      	ldr	r3, [r0, #4]
    1d5e:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    1d62:	d110      	bne.n	1d86 <mutex_lock_platform+0x2e>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    1d64:	2201      	movs	r2, #1
    1d66:	6803      	ldr	r3, [r0, #0]
    1d68:	f3bf 8f5b 	dmb	ish
    1d6c:	e853 1f00 	ldrex	r1, [r3]
    1d70:	2900      	cmp	r1, #0
    1d72:	d103      	bne.n	1d7c <mutex_lock_platform+0x24>
    1d74:	e843 2000 	strex	r0, r2, [r3]
    1d78:	2800      	cmp	r0, #0
    1d7a:	d1f7      	bne.n	1d6c <mutex_lock_platform+0x14>
    1d7c:	f3bf 8f5b 	dmb	ish
    case NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC:
        return atomic_cas((atomic_t *)mutex->mutex, 0, 1) ?
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1d80:	d10d      	bne.n	1d9e <mutex_lock_platform+0x46>

        p_mutex = (struct k_mutex *)mutex->mutex;

        ret = k_mutex_lock(p_mutex, K_FOREVER);
        if (ret == 0) {
            return NRF_CC3XX_PLATFORM_SUCCESS;
    1d82:	2000      	movs	r0, #0
        } else {
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
        }
    }
}
    1d84:	bd08      	pop	{r3, pc}
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1d86:	4a09      	ldr	r2, [pc, #36]	; (1dac <mutex_lock_platform+0x54>)
    1d88:	4293      	cmp	r3, r2
    1d8a:	d00a      	beq.n	1da2 <mutex_lock_platform+0x4a>
        p_mutex = (struct k_mutex *)mutex->mutex;
    1d8c:	6800      	ldr	r0, [r0, #0]
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_MUTEX_LOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_lock(mutex, timeout);
    1d8e:	f04f 32ff 	mov.w	r2, #4294967295
    1d92:	f04f 33ff 	mov.w	r3, #4294967295
    1d96:	f004 f993 	bl	60c0 <z_impl_k_mutex_lock>
        if (ret == 0) {
    1d9a:	2800      	cmp	r0, #0
    1d9c:	d0f1      	beq.n	1d82 <mutex_lock_platform+0x2a>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1d9e:	4804      	ldr	r0, [pc, #16]	; (1db0 <mutex_lock_platform+0x58>)
    1da0:	e7f0      	b.n	1d84 <mutex_lock_platform+0x2c>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1da2:	4804      	ldr	r0, [pc, #16]	; (1db4 <mutex_lock_platform+0x5c>)
    1da4:	e7ee      	b.n	1d84 <mutex_lock_platform+0x2c>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1da6:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1daa:	e7eb      	b.n	1d84 <mutex_lock_platform+0x2c>
    1dac:	a95c5f2c 	.word	0xa95c5f2c
    1db0:	ffff8fe9 	.word	0xffff8fe9
    1db4:	ffff8fea 	.word	0xffff8fea

00001db8 <mutex_unlock_platform>:

/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1db8:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1dba:	b1d8      	cbz	r0, 1df4 <mutex_unlock_platform+0x3c>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags)
    1dbc:	6843      	ldr	r3, [r0, #4]
    1dbe:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    1dc2:	d110      	bne.n	1de6 <mutex_unlock_platform+0x2e>
    1dc4:	2200      	movs	r2, #0
    1dc6:	6803      	ldr	r3, [r0, #0]
    1dc8:	f3bf 8f5b 	dmb	ish
    1dcc:	e853 1f00 	ldrex	r1, [r3]
    1dd0:	2901      	cmp	r1, #1
    1dd2:	d103      	bne.n	1ddc <mutex_unlock_platform+0x24>
    1dd4:	e843 2000 	strex	r0, r2, [r3]
    1dd8:	2800      	cmp	r0, #0
    1dda:	d1f7      	bne.n	1dcc <mutex_unlock_platform+0x14>
    1ddc:	f3bf 8f5b 	dmb	ish
    {
    case NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC:
        return atomic_cas((atomic_t *)mutex->mutex, 1, 0) ?
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1de0:	d10b      	bne.n	1dfa <mutex_unlock_platform+0x42>
        }

        p_mutex = (struct k_mutex *)mutex->mutex;

        k_mutex_unlock(p_mutex);
        return NRF_CC3XX_PLATFORM_SUCCESS;
    1de2:	2000      	movs	r0, #0
    }
}
    1de4:	bd08      	pop	{r3, pc}
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1de6:	4a07      	ldr	r2, [pc, #28]	; (1e04 <mutex_unlock_platform+0x4c>)
    1de8:	4293      	cmp	r3, r2
    1dea:	d008      	beq.n	1dfe <mutex_unlock_platform+0x46>
        p_mutex = (struct k_mutex *)mutex->mutex;
    1dec:	6800      	ldr	r0, [r0, #0]
		union { uintptr_t x; struct k_mutex * val; } parm0 = { .val = mutex };
		return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_MUTEX_UNLOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_unlock(mutex);
    1dee:	f004 f9e1 	bl	61b4 <z_impl_k_mutex_unlock>
    1df2:	e7f6      	b.n	1de2 <mutex_unlock_platform+0x2a>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1df4:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1df8:	e7f4      	b.n	1de4 <mutex_unlock_platform+0x2c>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1dfa:	4803      	ldr	r0, [pc, #12]	; (1e08 <mutex_unlock_platform+0x50>)
    1dfc:	e7f2      	b.n	1de4 <mutex_unlock_platform+0x2c>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1dfe:	4803      	ldr	r0, [pc, #12]	; (1e0c <mutex_unlock_platform+0x54>)
    1e00:	e7f0      	b.n	1de4 <mutex_unlock_platform+0x2c>
    1e02:	bf00      	nop
    1e04:	a95c5f2c 	.word	0xa95c5f2c
    1e08:	ffff8fe9 	.word	0xffff8fe9
    1e0c:	ffff8fea 	.word	0xffff8fea

00001e10 <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1e10:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    1e12:	4604      	mov	r4, r0
    1e14:	b918      	cbnz	r0, 1e1e <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    1e16:	4b1d      	ldr	r3, [pc, #116]	; (1e8c <mutex_init_platform+0x7c>)
    1e18:	481d      	ldr	r0, [pc, #116]	; (1e90 <mutex_init_platform+0x80>)
    1e1a:	685b      	ldr	r3, [r3, #4]
    1e1c:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    1e1e:	6863      	ldr	r3, [r4, #4]
    1e20:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    1e24:	d02f      	beq.n	1e86 <mutex_init_platform+0x76>
    1e26:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    1e2a:	d02c      	beq.n	1e86 <mutex_init_platform+0x76>
    if ((mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID && mutex->mutex == NULL) ||
    1e2c:	4a19      	ldr	r2, [pc, #100]	; (1e94 <mutex_init_platform+0x84>)
    1e2e:	4293      	cmp	r3, r2
    1e30:	d119      	bne.n	1e66 <mutex_init_platform+0x56>
    1e32:	6823      	ldr	r3, [r4, #0]
    1e34:	bb03      	cbnz	r3, 1e78 <mutex_init_platform+0x68>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    1e36:	4818      	ldr	r0, [pc, #96]	; (1e98 <mutex_init_platform+0x88>)
    1e38:	f04f 32ff 	mov.w	r2, #4294967295
    1e3c:	f04f 33ff 	mov.w	r3, #4294967295
    1e40:	4621      	mov	r1, r4
    1e42:	f004 f865 	bl	5f10 <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    1e46:	b908      	cbnz	r0, 1e4c <mutex_init_platform+0x3c>
    1e48:	6823      	ldr	r3, [r4, #0]
    1e4a:	b91b      	cbnz	r3, 1e54 <mutex_init_platform+0x44>
            platform_abort_apis.abort_fn(
    1e4c:	4b0f      	ldr	r3, [pc, #60]	; (1e8c <mutex_init_platform+0x7c>)
    1e4e:	4813      	ldr	r0, [pc, #76]	; (1e9c <mutex_init_platform+0x8c>)
    1e50:	685b      	ldr	r3, [r3, #4]
    1e52:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1e54:	6820      	ldr	r0, [r4, #0]
    1e56:	2214      	movs	r2, #20
    1e58:	2100      	movs	r1, #0
    1e5a:	f006 fff7 	bl	8e4c <memset>
        mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    1e5e:	f44f 6368 	mov.w	r3, #3712	; 0xe80
    1e62:	6063      	str	r3, [r4, #4]
    1e64:	e008      	b.n	1e78 <mutex_init_platform+0x68>
    switch(flags){
    1e66:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    1e6a:	d80d      	bhi.n	1e88 <mutex_init_platform+0x78>
    1e6c:	2b3a      	cmp	r3, #58	; 0x3a
    1e6e:	d003      	beq.n	1e78 <mutex_init_platform+0x68>
    1e70:	f640 62ba 	movw	r2, #3770	; 0xeba
    1e74:	4293      	cmp	r3, r2
    1e76:	d1de      	bne.n	1e36 <mutex_init_platform+0x26>
    p_mutex = (struct k_mutex *)mutex->mutex;
    1e78:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    1e7a:	f007 fe57 	bl	9b2c <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    1e7e:	6863      	ldr	r3, [r4, #4]
    1e80:	f043 033a 	orr.w	r3, r3, #58	; 0x3a
    1e84:	6063      	str	r3, [r4, #4]
}
    1e86:	bd10      	pop	{r4, pc}
    switch(flags){
    1e88:	4a05      	ldr	r2, [pc, #20]	; (1ea0 <mutex_init_platform+0x90>)
    1e8a:	e7f3      	b.n	1e74 <mutex_init_platform+0x64>
    1e8c:	200001cc 	.word	0x200001cc
    1e90:	0000aa99 	.word	0x0000aa99
    1e94:	a95c5f2c 	.word	0xa95c5f2c
    1e98:	20001dc4 	.word	0x20001dc4
    1e9c:	0000aabf 	.word	0x0000aabf
    1ea0:	3a00003a 	.word	0x3a00003a

00001ea4 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    1ea4:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    1ea6:	4906      	ldr	r1, [pc, #24]	; (1ec0 <nrf_cc3xx_platform_mutex_init+0x1c>)
    1ea8:	4806      	ldr	r0, [pc, #24]	; (1ec4 <nrf_cc3xx_platform_mutex_init+0x20>)
    1eaa:	2340      	movs	r3, #64	; 0x40
    1eac:	2214      	movs	r2, #20
    1eae:	f007 fdef 	bl	9a90 <k_mem_slab_init>
                mutex_slab_buffer,
                sizeof(struct k_mutex),
                NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    1eb2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    1eb6:	4904      	ldr	r1, [pc, #16]	; (1ec8 <nrf_cc3xx_platform_mutex_init+0x24>)
    1eb8:	4804      	ldr	r0, [pc, #16]	; (1ecc <nrf_cc3xx_platform_mutex_init+0x28>)
    1eba:	f004 bf63 	b.w	6d84 <nrf_cc3xx_platform_set_mutexes>
    1ebe:	bf00      	nop
    1ec0:	200018c4 	.word	0x200018c4
    1ec4:	20001dc4 	.word	0x20001dc4
    1ec8:	0000a1d4 	.word	0x0000a1d4
    1ecc:	0000a1e8 	.word	0x0000a1e8

00001ed0 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1ed0:	4901      	ldr	r1, [pc, #4]	; (1ed8 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    1ed2:	2210      	movs	r2, #16
	str	r2, [r1]
    1ed4:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    1ed6:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    1ed8:	e000ed10 	.word	0xe000ed10

00001edc <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    1edc:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    1ede:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    1ee0:	f380 8811 	msr	BASEPRI, r0
	isb
    1ee4:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    1ee8:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    1eec:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    1eee:	b662      	cpsie	i
	isb
    1ef0:	f3bf 8f6f 	isb	sy

	bx	lr
    1ef4:	4770      	bx	lr
    1ef6:	bf00      	nop

00001ef8 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    1ef8:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    1efa:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1efc:	f381 8811 	msr	BASEPRI, r1

	wfe
    1f00:	bf20      	wfe

	msr	BASEPRI, r0
    1f02:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    1f06:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    1f08:	4770      	bx	lr
    1f0a:	bf00      	nop

00001f0c <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    1f0c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1f10:	4607      	mov	r7, r0
    1f12:	b086      	sub	sp, #24

	if (esf != NULL) {
    1f14:	460c      	mov	r4, r1
    1f16:	2900      	cmp	r1, #0
    1f18:	d04a      	beq.n	1fb0 <z_arm_fatal_error+0xa4>
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    1f1a:	688b      	ldr	r3, [r1, #8]
    1f1c:	9300      	str	r3, [sp, #0]
    1f1e:	e9d1 2300 	ldrd	r2, r3, [r1]
    1f22:	4827      	ldr	r0, [pc, #156]	; (1fc0 <z_arm_fatal_error+0xb4>)
		LOG_ERR("s[%2d]:  0x%08x  s[%2d]:  0x%08x"
    1f24:	f8df 80ac 	ldr.w	r8, [pc, #172]	; 1fd4 <z_arm_fatal_error+0xc8>
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    1f28:	2145      	movs	r1, #69	; 0x45
    1f2a:	f006 fed2 	bl	8cd2 <z_log_minimal_printk>
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    1f2e:	6963      	ldr	r3, [r4, #20]
    1f30:	9300      	str	r3, [sp, #0]
    1f32:	e9d4 2303 	ldrd	r2, r3, [r4, #12]
    1f36:	4823      	ldr	r0, [pc, #140]	; (1fc4 <z_arm_fatal_error+0xb8>)
    1f38:	2145      	movs	r1, #69	; 0x45
    1f3a:	f006 feca 	bl	8cd2 <z_log_minimal_printk>
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    1f3e:	69e2      	ldr	r2, [r4, #28]
    1f40:	4821      	ldr	r0, [pc, #132]	; (1fc8 <z_arm_fatal_error+0xbc>)
    1f42:	2145      	movs	r1, #69	; 0x45
    1f44:	f006 fec5 	bl	8cd2 <z_log_minimal_printk>
	for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) {
    1f48:	4626      	mov	r6, r4
    1f4a:	2500      	movs	r5, #0
		LOG_ERR("s[%2d]:  0x%08x  s[%2d]:  0x%08x"
    1f4c:	edd6 7a0b 	vldr	s15, [r6, #44]	; 0x2c
    1f50:	ed96 7a08 	vldr	s14, [r6, #32]
    1f54:	eefc 7ae7 	vcvt.u32.f32	s15, s15
    1f58:	1ceb      	adds	r3, r5, #3
    1f5a:	9304      	str	r3, [sp, #16]
    1f5c:	edcd 7a05 	vstr	s15, [sp, #20]
    1f60:	edd6 7a0a 	vldr	s15, [r6, #40]	; 0x28
    1f64:	eefc 7ae7 	vcvt.u32.f32	s15, s15
    1f68:	1cab      	adds	r3, r5, #2
    1f6a:	9302      	str	r3, [sp, #8]
    1f6c:	edcd 7a03 	vstr	s15, [sp, #12]
    1f70:	edd6 7a09 	vldr	s15, [r6, #36]	; 0x24
    1f74:	eefc 7ae7 	vcvt.u32.f32	s15, s15
    1f78:	1c6b      	adds	r3, r5, #1
    1f7a:	edcd 7a01 	vstr	s15, [sp, #4]
    1f7e:	eefc 7ac7 	vcvt.u32.f32	s15, s14
    1f82:	9300      	str	r3, [sp, #0]
    1f84:	462a      	mov	r2, r5
    1f86:	ee17 3a90 	vmov	r3, s15
    1f8a:	2145      	movs	r1, #69	; 0x45
    1f8c:	4640      	mov	r0, r8
	for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) {
    1f8e:	3504      	adds	r5, #4
		LOG_ERR("s[%2d]:  0x%08x  s[%2d]:  0x%08x"
    1f90:	f006 fe9f 	bl	8cd2 <z_log_minimal_printk>
	for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) {
    1f94:	2d10      	cmp	r5, #16
    1f96:	f106 0610 	add.w	r6, r6, #16
    1f9a:	d1d7      	bne.n	1f4c <z_arm_fatal_error+0x40>
	LOG_ERR("fpscr:  0x%08x", esf->fpu.fpscr);
    1f9c:	6e22      	ldr	r2, [r4, #96]	; 0x60
    1f9e:	480b      	ldr	r0, [pc, #44]	; (1fcc <z_arm_fatal_error+0xc0>)
    1fa0:	2145      	movs	r1, #69	; 0x45
    1fa2:	f006 fe96 	bl	8cd2 <z_log_minimal_printk>
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    1fa6:	69a2      	ldr	r2, [r4, #24]
    1fa8:	4809      	ldr	r0, [pc, #36]	; (1fd0 <z_arm_fatal_error+0xc4>)
    1faa:	2145      	movs	r1, #69	; 0x45
    1fac:	f006 fe91 	bl	8cd2 <z_log_minimal_printk>
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    1fb0:	4621      	mov	r1, r4
    1fb2:	4638      	mov	r0, r7
}
    1fb4:	b006      	add	sp, #24
    1fb6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	z_fatal_error(reason, esf);
    1fba:	f003 be5d 	b.w	5c78 <z_fatal_error>
    1fbe:	bf00      	nop
    1fc0:	0000aaec 	.word	0x0000aaec
    1fc4:	0000ab20 	.word	0x0000ab20
    1fc8:	0000ab54 	.word	0x0000ab54
    1fcc:	0000abb0 	.word	0x0000abb0
    1fd0:	0000abc4 	.word	0x0000abc4
    1fd4:	0000ab68 	.word	0x0000ab68

00001fd8 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1fd8:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    1fda:	2800      	cmp	r0, #0
    1fdc:	db07      	blt.n	1fee <arch_irq_enable+0x16>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1fde:	4a04      	ldr	r2, [pc, #16]	; (1ff0 <arch_irq_enable+0x18>)
    1fe0:	0941      	lsrs	r1, r0, #5
    1fe2:	2301      	movs	r3, #1
    1fe4:	f000 001f 	and.w	r0, r0, #31
    1fe8:	4083      	lsls	r3, r0
    1fea:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    1fee:	4770      	bx	lr
    1ff0:	e000e100 	.word	0xe000e100

00001ff4 <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
    1ff4:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    1ff6:	2800      	cmp	r0, #0
    1ff8:	db0c      	blt.n	2014 <arch_irq_disable+0x20>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1ffa:	0943      	lsrs	r3, r0, #5
    1ffc:	4906      	ldr	r1, [pc, #24]	; (2018 <arch_irq_disable+0x24>)
    1ffe:	f000 001f 	and.w	r0, r0, #31
    2002:	3320      	adds	r3, #32
    2004:	2201      	movs	r2, #1
    2006:	4082      	lsls	r2, r0
    2008:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  __ASM volatile ("dsb 0xF":::"memory");
    200c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2010:	f3bf 8f6f 	isb	sy
}
    2014:	4770      	bx	lr
    2016:	bf00      	nop
    2018:	e000e100 	.word	0xe000e100

0000201c <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    201c:	4b05      	ldr	r3, [pc, #20]	; (2034 <arch_irq_is_enabled+0x18>)
    201e:	0942      	lsrs	r2, r0, #5
    2020:	f000 001f 	and.w	r0, r0, #31
    2024:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    2028:	2301      	movs	r3, #1
    202a:	fa03 f000 	lsl.w	r0, r3, r0
}
    202e:	4010      	ands	r0, r2
    2030:	4770      	bx	lr
    2032:	bf00      	nop
    2034:	e000e100 	.word	0xe000e100

00002038 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    2038:	b240      	sxtb	r0, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    203a:	2800      	cmp	r0, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    203c:	bfa8      	it	ge
    203e:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    2042:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2046:	bfb8      	it	lt
    2048:	4b06      	ldrlt	r3, [pc, #24]	; (2064 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    204a:	ea4f 1141 	mov.w	r1, r1, lsl #5
    204e:	bfac      	ite	ge
    2050:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2054:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2058:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    205a:	bfb4      	ite	lt
    205c:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    205e:	f880 1300 	strbge.w	r1, [r0, #768]	; 0x300
}
    2062:	4770      	bx	lr
    2064:	e000ed14 	.word	0xe000ed14

00002068 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    2068:	bf30      	wfi
    b z_SysNmiOnReset
    206a:	f7ff bffd 	b.w	2068 <z_SysNmiOnReset>
    206e:	bf00      	nop

00002070 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    2070:	4a14      	ldr	r2, [pc, #80]	; (20c4 <z_arm_prep_c+0x54>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    2072:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    2074:	4b14      	ldr	r3, [pc, #80]	; (20c8 <z_arm_prep_c+0x58>)
    2076:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    207a:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    207c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2080:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    2084:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2088:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    208c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
    2090:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2094:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
    2098:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	FPU->FPCCR = FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
    209c:	f04f 4240 	mov.w	r2, #3221225472	; 0xc0000000
    20a0:	f8c3 2234 	str.w	r2, [r3, #564]	; 0x234
  __ASM volatile ("dsb 0xF":::"memory");
    20a4:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    20a8:	f3bf 8f6f 	isb	sy
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
  __builtin_arm_set_fpscr(fpscr);
    20ac:	2300      	movs	r3, #0
    20ae:	eee1 3a10 	vmsr	fpscr, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    20b2:	f003 fe69 	bl	5d88 <z_bss_zero>
	z_data_copy();
    20b6:	f004 fc49 	bl	694c <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    20ba:	f000 fb53 	bl	2764 <z_arm_interrupt_init>
	z_cstart();
    20be:	f003 fea7 	bl	5e10 <z_cstart>
    20c2:	bf00      	nop
    20c4:	00000000 	.word	0x00000000
    20c8:	e000ed00 	.word	0xe000ed00

000020cc <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    20cc:	4a09      	ldr	r2, [pc, #36]	; (20f4 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    20ce:	490a      	ldr	r1, [pc, #40]	; (20f8 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    20d0:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    20d2:	6809      	ldr	r1, [r1, #0]
    20d4:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    20d6:	4909      	ldr	r1, [pc, #36]	; (20fc <arch_swap+0x30>)
	_current->arch.basepri = key;
    20d8:	6758      	str	r0, [r3, #116]	; 0x74
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    20da:	684b      	ldr	r3, [r1, #4]
    20dc:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    20e0:	604b      	str	r3, [r1, #4]
    20e2:	2300      	movs	r3, #0
    20e4:	f383 8811 	msr	BASEPRI, r3
    20e8:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    20ec:	6893      	ldr	r3, [r2, #8]
}
    20ee:	6f98      	ldr	r0, [r3, #120]	; 0x78
    20f0:	4770      	bx	lr
    20f2:	bf00      	nop
    20f4:	20001fa0 	.word	0x20001fa0
    20f8:	0000a428 	.word	0x0000a428
    20fc:	e000ed00 	.word	0xe000ed00

00002100 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    2100:	4921      	ldr	r1, [pc, #132]	; (2188 <in_fp_endif+0x2a>)
    ldr r2, [r1, #_kernel_offset_to_current]
    2102:	688a      	ldr	r2, [r1, #8]

#if defined(CONFIG_ARM_STORE_EXC_RETURN)
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
    2104:	f882 e0bd 	strb.w	lr, [r2, #189]	; 0xbd
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    2108:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    210c:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    210e:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    2112:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#ifdef CONFIG_FPU_SHARING
    /* Assess whether switched-out thread had been using the FP registers. */
    tst lr, #_EXC_RETURN_FTYPE_Msk
    2116:	f01e 0f10 	tst.w	lr, #16
    bne out_fp_endif
    211a:	d103      	bne.n	2124 <out_fp_endif>
    /* FP context active: set FP state and store callee-saved registers.
     * Note: if Lazy FP stacking is enabled, storing the callee-saved
     * registers will automatically trigger FP state preservation in
     * the thread's stack. This will also clear the FPCCR.LSPACT flag.
     */
    add r0, r2, #_thread_offset_to_preempt_float
    211c:	f102 007c 	add.w	r0, r2, #124	; 0x7c
    vstmia r0, {s16-s31}
    2120:	ec80 8a10 	vstmia	r0, {s16-s31}

00002124 <out_fp_endif>:

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    2124:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    2126:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    212a:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    212e:	4f17      	ldr	r7, [pc, #92]	; (218c <in_fp_endif+0x2e>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    2130:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    2134:	6a0a      	ldr	r2, [r1, #32]

    str r2, [r1, #_kernel_offset_to_current]
    2136:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    2138:	603e      	str	r6, [r7, #0]

#endif

#if defined(CONFIG_ARM_STORE_EXC_RETURN)
    /* Restore EXC_RETURN value. */
    ldrsb lr, [r2, #_thread_offset_to_mode_exc_return]
    213a:	f992 e0bd 	ldrsb.w	lr, [r2, #189]	; 0xbd

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    213e:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    2140:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    2142:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    2144:	f380 8811 	msr	BASEPRI, r0

#ifdef CONFIG_FPU_SHARING
    /* Assess whether switched-in thread had been using the FP registers. */
    tst lr, #_EXC_RETURN_FTYPE_Msk
    2148:	f01e 0f10 	tst.w	lr, #16
    beq in_fp_active
    214c:	d003      	beq.n	2156 <in_fp_active>
    /* FP context inactive for swapped-in thread:
     * - reset FPSCR to 0
     * - set EXC_RETURN.F_Type (prevents FP frame un-stacking when returning
     *   from pendSV)
     */
    movs.n r3, #0
    214e:	2300      	movs	r3, #0
    vmsr fpscr, r3
    2150:	eee1 3a10 	vmsr	fpscr, r3
    b in_fp_endif
    2154:	e003      	b.n	215e <in_fp_endif>

00002156 <in_fp_active>:
    /* FP context active:
     * - clear EXC_RETURN.F_Type
     * - FPSCR and caller-saved registers will be restored automatically
     * - restore callee-saved FP registers
     */
    add r0, r2, #_thread_offset_to_preempt_float
    2156:	f102 007c 	add.w	r0, r2, #124	; 0x7c
    vldmia r0, {s16-s31}
    215a:	ec90 8a10 	vldmia	r0, {s16-s31}

0000215e <in_fp_endif>:
in_fp_endif:
    /* Clear CONTROL.FPCA that may have been set by FP instructions */
    mrs r3, CONTROL
    215e:	f3ef 8314 	mrs	r3, CONTROL
    bic r3, #_CONTROL_FPCA_Msk
    2162:	f023 0304 	bic.w	r3, r3, #4
    msr CONTROL, r3
    2166:	f383 8814 	msr	CONTROL, r3
    isb
    216a:	f3bf 8f6f 	isb	sy
#endif

#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
    /* Re-program dynamic memory map */
    push {r2,lr}
    216e:	b504      	push	{r2, lr}
    mov r0, r2 /* _current thread */
    2170:	4610      	mov	r0, r2
    bl z_arm_configure_dynamic_mpu_regions
    2172:	f000 fb93 	bl	289c <z_arm_configure_dynamic_mpu_regions>
    pop {r2,lr}
    2176:	e8bd 4004 	ldmia.w	sp!, {r2, lr}
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    217a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    217e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    2182:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    2186:	4770      	bx	lr
    ldr r1, =_kernel
    2188:	20001fa0 	.word	0x20001fa0
    ldr v4, =_SCS_ICSR
    218c:	e000ed04 	.word	0xe000ed04

00002190 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    2190:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    2194:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    2196:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    219a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    219e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    21a0:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    21a4:	2902      	cmp	r1, #2
    beq _oops
    21a6:	d0ff      	beq.n	21a8 <_oops>

000021a8 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    21a8:	b501      	push	{r0, lr}
    push {r1, r2}
    push {r4-r11}
    mov  r1, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    bl z_do_kernel_oops
    21aa:	f006 fe14 	bl	8dd6 <z_do_kernel_oops>
     * the MSP to its value prior to entering the function
     */
    add sp, #40
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    pop {r0, pc}
    21ae:	bd01      	pop	{r0, pc}

000021b0 <arch_new_thread>:
		thread->stack_info.start += MPU_GUARD_ALIGN_AND_SIZE;
		thread->stack_info.size -= MPU_GUARD_ALIGN_AND_SIZE;
	}
#endif /* CONFIG_USERSPACE */
#if FP_GUARD_EXTRA_SIZE > 0
	if ((thread->base.user_options & K_FP_REGS) != 0) {
    21b0:	7b01      	ldrb	r1, [r0, #12]
    21b2:	0789      	lsls	r1, r1, #30
    21b4:	d505      	bpl.n	21c2 <arch_new_thread+0x12>
		/* Larger guard needed due to lazy stacking of FP regs may
		 * overshoot the guard area without writing anything. We
		 * carve it out of the stack buffer as-needed instead of
		 * unconditionally reserving it.
		 */
		thread->stack_info.start += FP_GUARD_EXTRA_SIZE;
    21b6:	6e41      	ldr	r1, [r0, #100]	; 0x64
    21b8:	3140      	adds	r1, #64	; 0x40
    21ba:	6641      	str	r1, [r0, #100]	; 0x64
		thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
    21bc:	6e81      	ldr	r1, [r0, #104]	; 0x68
    21be:	3940      	subs	r1, #64	; 0x40
    21c0:	6681      	str	r1, [r0, #104]	; 0x68

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    21c2:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    21c6:	9b00      	ldr	r3, [sp, #0]
    21c8:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->pc &= 0xfffffffe;
    21cc:	490f      	ldr	r1, [pc, #60]	; (220c <arch_new_thread+0x5c>)
	iframe->a3 = (uint32_t)p2;
    21ce:	9b01      	ldr	r3, [sp, #4]
    21d0:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    21d4:	9b02      	ldr	r3, [sp, #8]
    21d6:	f842 3c14 	str.w	r3, [r2, #-20]
	iframe->pc &= 0xfffffffe;
    21da:	f021 0101 	bic.w	r1, r1, #1

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    21de:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    21e2:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->pc &= 0xfffffffe;
    21e6:	f842 1c08 	str.w	r1, [r2, #-8]
		((uintptr_t)iframe - sizeof(struct __fpu_sf));
	memset(iframe, 0, sizeof(struct __fpu_sf));
#endif

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    21ea:	2300      	movs	r3, #0
    21ec:	6743      	str	r3, [r0, #116]	; 0x74
	thread->arch.mode = 0;
#if defined(CONFIG_ARM_STORE_EXC_RETURN)
	thread->arch.mode_exc_return = DEFAULT_EXC_RETURN;
#endif
#if FP_GUARD_EXTRA_SIZE > 0
	if ((thread->base.user_options & K_FP_REGS) != 0) {
    21ee:	7b03      	ldrb	r3, [r0, #12]
		thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
    21f0:	f013 0f02 	tst.w	r3, #2
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    21f4:	f1a2 0220 	sub.w	r2, r2, #32
		thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
    21f8:	f64f 5308 	movw	r3, #64776	; 0xfd08
    21fc:	bf08      	it	eq
    21fe:	f44f 437d 	moveq.w	r3, #64768	; 0xfd00
	thread->callee_saved.psp = (uint32_t)iframe;
    2202:	6502      	str	r2, [r0, #80]	; 0x50
	if ((thread->base.user_options & K_FP_REGS) != 0) {
    2204:	f8c0 30bc 	str.w	r3, [r0, #188]	; 0xbc
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    2208:	4770      	bx	lr
    220a:	bf00      	nop
    220c:	00008b09 	.word	0x00008b09

00002210 <z_arm_mpu_stack_guard_and_fpu_adjust>:
 * policy and the stack_info values for the thread that is
 * being switched in.
 */
uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread)
{
	if (((thread->base.user_options & K_FP_REGS) != 0) ||
    2210:	7b03      	ldrb	r3, [r0, #12]
    2212:	f013 0f02 	tst.w	r3, #2
    2216:	4b19      	ldr	r3, [pc, #100]	; (227c <z_arm_mpu_stack_guard_and_fpu_adjust+0x6c>)
    2218:	d103      	bne.n	2222 <z_arm_mpu_stack_guard_and_fpu_adjust+0x12>
    221a:	f890 20bd 	ldrb.w	r2, [r0, #189]	; 0xbd
    221e:	06d2      	lsls	r2, r2, #27
    2220:	d417      	bmi.n	2252 <z_arm_mpu_stack_guard_and_fpu_adjust+0x42>
		 * The thread is not pre-tagged with K_FP_REGS, but it has
		 * generated an FP context. Activate lazy stacking and
		 * program a large MPU guard to detect privilege thread
		 * stack overflows.
		 */
		FPU->FPCCR |= FPU_FPCCR_LSPEN_Msk;
    2222:	6b5a      	ldr	r2, [r3, #52]	; 0x34
    2224:	f042 4280 	orr.w	r2, r2, #1073741824	; 0x40000000
    2228:	635a      	str	r2, [r3, #52]	; 0x34
		if ((thread->arch.mode &
    222a:	f8d0 30bc 	ldr.w	r3, [r0, #188]	; 0xbc
    222e:	0719      	lsls	r1, r3, #28
    2230:	d409      	bmi.n	2246 <z_arm_mpu_stack_guard_and_fpu_adjust+0x36>
			thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
    2232:	f043 0308 	orr.w	r3, r3, #8
    2236:	f8c0 30bc 	str.w	r3, [r0, #188]	; 0xbc
				thread->stack_info.start +=
    223a:	6e43      	ldr	r3, [r0, #100]	; 0x64
    223c:	3340      	adds	r3, #64	; 0x40
    223e:	6643      	str	r3, [r0, #100]	; 0x64
				thread->stack_info.size -=
    2240:	6e83      	ldr	r3, [r0, #104]	; 0x68
    2242:	3b40      	subs	r3, #64	; 0x40
    2244:	6683      	str	r3, [r0, #104]	; 0x68

		z_arm_thread_stack_info_adjust(thread, true);

		/* Tag the thread with K_FP_REGS */
		thread->base.user_options |= K_FP_REGS;
    2246:	7b03      	ldrb	r3, [r0, #12]
    2248:	f043 0302 	orr.w	r3, r3, #2
    224c:	7303      	strb	r3, [r0, #12]

		return MPU_GUARD_ALIGN_AND_SIZE_FLOAT;
    224e:	2080      	movs	r0, #128	; 0x80
    2250:	4770      	bx	lr
	/* Thread is not pre-tagged with K_FP_REGS, and it has
	 * not been using the FPU. Since there is no active FPU
	 * context, de-activate lazy stacking and program the
	 * default MPU guard size.
	 */
	FPU->FPCCR &= (~FPU_FPCCR_LSPEN_Msk);
    2252:	6b5a      	ldr	r2, [r3, #52]	; 0x34
    2254:	f022 4280 	bic.w	r2, r2, #1073741824	; 0x40000000
    2258:	635a      	str	r2, [r3, #52]	; 0x34
		if ((thread->arch.mode &
    225a:	f8d0 30bc 	ldr.w	r3, [r0, #188]	; 0xbc
    225e:	071a      	lsls	r2, r3, #28
    2260:	d401      	bmi.n	2266 <z_arm_mpu_stack_guard_and_fpu_adjust+0x56>

	z_arm_thread_stack_info_adjust(thread, false);

	return MPU_GUARD_ALIGN_AND_SIZE;
    2262:	2040      	movs	r0, #64	; 0x40
}
    2264:	4770      	bx	lr
			thread->arch.mode &= ~Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
    2266:	f023 0308 	bic.w	r3, r3, #8
    226a:	f8c0 30bc 	str.w	r3, [r0, #188]	; 0xbc
				thread->stack_info.start -=
    226e:	6e43      	ldr	r3, [r0, #100]	; 0x64
    2270:	3b40      	subs	r3, #64	; 0x40
    2272:	6643      	str	r3, [r0, #100]	; 0x64
				thread->stack_info.size +=
    2274:	6e83      	ldr	r3, [r0, #104]	; 0x68
    2276:	3340      	adds	r3, #64	; 0x40
    2278:	6683      	str	r3, [r0, #104]	; 0x68
    227a:	e7f2      	b.n	2262 <z_arm_mpu_stack_guard_and_fpu_adjust+0x52>
    227c:	e000ef00 	.word	0xe000ef00

00002280 <z_check_thread_stack_fail>:
 *         thread stack corruption, otherwise return 0.
 */
uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
{
#if defined(CONFIG_MULTITHREADING)
	const struct k_thread *thread = _current;
    2280:	4a0c      	ldr	r2, [pc, #48]	; (22b4 <z_check_thread_stack_fail+0x34>)
{
    2282:	4603      	mov	r3, r0
	const struct k_thread *thread = _current;
    2284:	6890      	ldr	r0, [r2, #8]

	if (thread == NULL) {
    2286:	b1a0      	cbz	r0, 22b2 <z_check_thread_stack_fail+0x32>
#endif

#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && \
	defined(CONFIG_MPU_STACK_GUARD)
	uint32_t guard_len =
		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
    2288:	f8d0 20bc 	ldr.w	r2, [r0, #188]	; 0xbc
			return thread->stack_info.start;
		}
	}
#else /* CONFIG_USERSPACE */
#if defined(CONFIG_MULTITHREADING)
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    228c:	6e40      	ldr	r0, [r0, #100]	; 0x64
		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
    228e:	f012 0f08 	tst.w	r2, #8
    2292:	bf0c      	ite	eq
    2294:	2240      	moveq	r2, #64	; 0x40
    2296:	2280      	movne	r2, #128	; 0x80
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    2298:	f113 0f16 	cmn.w	r3, #22
    229c:	d004      	beq.n	22a8 <z_check_thread_stack_fail+0x28>
    229e:	1a82      	subs	r2, r0, r2
    22a0:	429a      	cmp	r2, r3
    22a2:	d805      	bhi.n	22b0 <z_check_thread_stack_fail+0x30>
    22a4:	4283      	cmp	r3, r0
    22a6:	d203      	bcs.n	22b0 <z_check_thread_stack_fail+0x30>
		return 0;
    22a8:	4281      	cmp	r1, r0
    22aa:	bf28      	it	cs
    22ac:	2000      	movcs	r0, #0
    22ae:	4770      	bx	lr
    22b0:	2000      	movs	r0, #0
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
}
    22b2:	4770      	bx	lr
    22b4:	20001fa0 	.word	0x20001fa0

000022b8 <arch_switch_to_main_thread>:
#endif /* CONFIG_FPU */
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    22b8:	b508      	push	{r3, lr}
    22ba:	4614      	mov	r4, r2
    22bc:	460d      	mov	r5, r1
    22be:	2200      	movs	r2, #0
    22c0:	eee1 2a10 	vmsr	fpscr, r2
  __ASM volatile ("MRS %0, control" : "=r" (result) );
    22c4:	f3ef 8214 	mrs	r2, CONTROL
	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
    22c8:	f022 0204 	bic.w	r2, r2, #4
  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
    22cc:	f382 8814 	msr	CONTROL, r2
  __ASM volatile ("isb 0xF":::"memory");
    22d0:	f3bf 8f6f 	isb	sy
    22d4:	f3bf 8f6f 	isb	sy
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    22d8:	4a08      	ldr	r2, [pc, #32]	; (22fc <arch_switch_to_main_thread+0x44>)
    22da:	6090      	str	r0, [r2, #8]
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
	/*
	 * If stack protection is enabled, make sure to set it
	 * before jumping to thread entry function
	 */
	z_arm_configure_dynamic_mpu_regions(main_thread);
    22dc:	f000 fade 	bl	289c <z_arm_configure_dynamic_mpu_regions>

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    22e0:	4620      	mov	r0, r4
    22e2:	f385 8809 	msr	PSP, r5
    22e6:	2100      	movs	r1, #0
    22e8:	b663      	cpsie	if
    22ea:	f381 8811 	msr	BASEPRI, r1
    22ee:	f3bf 8f6f 	isb	sy
    22f2:	2200      	movs	r2, #0
    22f4:	2300      	movs	r3, #0
    22f6:	f006 fc07 	bl	8b08 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    22fa:	bf00      	nop
    22fc:	20001fa0 	.word	0x20001fa0

00002300 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    2300:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    2302:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    2304:	4a0b      	ldr	r2, [pc, #44]	; (2334 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    2306:	69d0      	ldr	r0, [r2, #28]
	cmp r0, #0
    2308:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    230a:	bf1e      	ittt	ne
	movne	r1, #0
    230c:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    230e:	61d1      	strne	r1, [r2, #28]
		blne	z_pm_save_idle_exit
    2310:	f007 fbfd 	blne	9b0e <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    2314:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    2316:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    231a:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    231e:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    2322:	4905      	ldr	r1, [pc, #20]	; (2338 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    2324:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    2326:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    2328:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    232a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    232e:	4903      	ldr	r1, [pc, #12]	; (233c <_isr_wrapper+0x3c>)
	bx r1
    2330:	4708      	bx	r1
    2332:	0000      	.short	0x0000
	ldr r2, =_kernel
    2334:	20001fa0 	.word	0x20001fa0
	ldr r1, =_sw_isr_table
    2338:	00009edc 	.word	0x00009edc
	ldr r1, =z_arm_int_exit
    233c:	00002341 	.word	0x00002341

00002340 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    2340:	4b04      	ldr	r3, [pc, #16]	; (2354 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    2342:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    2344:	6a18      	ldr	r0, [r3, #32]
	cmp r0, r1
    2346:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    2348:	d003      	beq.n	2352 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    234a:	4903      	ldr	r1, [pc, #12]	; (2358 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    234c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    2350:	600a      	str	r2, [r1, #0]

00002352 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    2352:	4770      	bx	lr
	ldr r3, =_kernel
    2354:	20001fa0 	.word	0x20001fa0
	ldr r1, =_SCS_ICSR
    2358:	e000ed04 	.word	0xe000ed04

0000235c <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    235c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    2360:	4c32      	ldr	r4, [pc, #200]	; (242c <mem_manage_fault+0xd0>)
{
    2362:	4607      	mov	r7, r0
    2364:	4688      	mov	r8, r1
	PR_FAULT_INFO("***** MPU FAULT *****");
    2366:	4832      	ldr	r0, [pc, #200]	; (2430 <mem_manage_fault+0xd4>)
    2368:	2145      	movs	r1, #69	; 0x45
{
    236a:	4615      	mov	r5, r2
	PR_FAULT_INFO("***** MPU FAULT *****");
    236c:	f006 fcb1 	bl	8cd2 <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    2370:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2372:	06de      	lsls	r6, r3, #27
    2374:	d503      	bpl.n	237e <mem_manage_fault+0x22>
		PR_FAULT_INFO("  Stacking error (context area might be"
    2376:	482f      	ldr	r0, [pc, #188]	; (2434 <mem_manage_fault+0xd8>)
    2378:	2145      	movs	r1, #69	; 0x45
    237a:	f006 fcaa 	bl	8cd2 <z_log_minimal_printk>
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    237e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2380:	0718      	lsls	r0, r3, #28
    2382:	d503      	bpl.n	238c <mem_manage_fault+0x30>
		PR_FAULT_INFO("  Unstacking error");
    2384:	482c      	ldr	r0, [pc, #176]	; (2438 <mem_manage_fault+0xdc>)
    2386:	2145      	movs	r1, #69	; 0x45
    2388:	f006 fca3 	bl	8cd2 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    238c:	4c27      	ldr	r4, [pc, #156]	; (242c <mem_manage_fault+0xd0>)
    238e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2390:	0799      	lsls	r1, r3, #30
    2392:	d428      	bmi.n	23e6 <mem_manage_fault+0x8a>
	uint32_t mmfar = -EINVAL;
    2394:	f06f 0615 	mvn.w	r6, #21
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    2398:	4c24      	ldr	r4, [pc, #144]	; (242c <mem_manage_fault+0xd0>)
    239a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    239c:	07db      	lsls	r3, r3, #31
    239e:	d503      	bpl.n	23a8 <mem_manage_fault+0x4c>
		PR_FAULT_INFO("  Instruction Access Violation");
    23a0:	4826      	ldr	r0, [pc, #152]	; (243c <mem_manage_fault+0xe0>)
    23a2:	2145      	movs	r1, #69	; 0x45
    23a4:	f006 fc95 	bl	8cd2 <z_log_minimal_printk>
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    23a8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    23aa:	069c      	lsls	r4, r3, #26
    23ac:	d503      	bpl.n	23b6 <mem_manage_fault+0x5a>
		PR_FAULT_INFO(
    23ae:	4824      	ldr	r0, [pc, #144]	; (2440 <mem_manage_fault+0xe4>)
    23b0:	2145      	movs	r1, #69	; 0x45
    23b2:	f006 fc8e 	bl	8cd2 <z_log_minimal_printk>
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    23b6:	4c1d      	ldr	r4, [pc, #116]	; (242c <mem_manage_fault+0xd0>)
    23b8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    23ba:	06d8      	lsls	r0, r3, #27
    23bc:	d428      	bmi.n	2410 <mem_manage_fault+0xb4>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    23be:	6aa3      	ldr	r3, [r4, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    23c0:	0799      	lsls	r1, r3, #30
    23c2:	d425      	bmi.n	2410 <mem_manage_fault+0xb4>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    23c4:	2000      	movs	r0, #0
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    23c6:	6aa3      	ldr	r3, [r4, #40]	; 0x28
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    23c8:	4a18      	ldr	r2, [pc, #96]	; (242c <mem_manage_fault+0xd0>)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    23ca:	069b      	lsls	r3, r3, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    23cc:	bf42      	ittt	mi
    23ce:	6a63      	ldrmi	r3, [r4, #36]	; 0x24
    23d0:	f423 5300 	bicmi.w	r3, r3, #8192	; 0x2000
    23d4:	6263      	strmi	r3, [r4, #36]	; 0x24
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    23d6:	6a93      	ldr	r3, [r2, #40]	; 0x28
    23d8:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    23dc:	6293      	str	r3, [r2, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    23de:	2300      	movs	r3, #0
    23e0:	702b      	strb	r3, [r5, #0]

	return reason;
}
    23e2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		PR_FAULT_INFO("  Data Access Violation");
    23e6:	4817      	ldr	r0, [pc, #92]	; (2444 <mem_manage_fault+0xe8>)
    23e8:	2145      	movs	r1, #69	; 0x45
    23ea:	f006 fc72 	bl	8cd2 <z_log_minimal_printk>
		uint32_t temp = SCB->MMFAR;
    23ee:	6b66      	ldr	r6, [r4, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    23f0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    23f2:	061a      	lsls	r2, r3, #24
    23f4:	d5ce      	bpl.n	2394 <mem_manage_fault+0x38>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    23f6:	4814      	ldr	r0, [pc, #80]	; (2448 <mem_manage_fault+0xec>)
    23f8:	4632      	mov	r2, r6
    23fa:	2145      	movs	r1, #69	; 0x45
    23fc:	f006 fc69 	bl	8cd2 <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    2400:	f1b8 0f00 	cmp.w	r8, #0
    2404:	d0c8      	beq.n	2398 <mem_manage_fault+0x3c>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    2406:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2408:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    240c:	62a3      	str	r3, [r4, #40]	; 0x28
    240e:	e7c3      	b.n	2398 <mem_manage_fault+0x3c>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    2410:	6863      	ldr	r3, [r4, #4]
    2412:	051a      	lsls	r2, r3, #20
    2414:	d5d6      	bpl.n	23c4 <mem_manage_fault+0x68>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    2416:	4639      	mov	r1, r7
    2418:	4630      	mov	r0, r6
    241a:	f7ff ff31 	bl	2280 <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    241e:	2800      	cmp	r0, #0
    2420:	d0d0      	beq.n	23c4 <mem_manage_fault+0x68>
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    2422:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    2426:	2002      	movs	r0, #2
    2428:	e7cd      	b.n	23c6 <mem_manage_fault+0x6a>
    242a:	bf00      	nop
    242c:	e000ed00 	.word	0xe000ed00
    2430:	0000abf7 	.word	0x0000abf7
    2434:	0000ac12 	.word	0x0000ac12
    2438:	0000ac4a 	.word	0x0000ac4a
    243c:	0000ac9a 	.word	0x0000ac9a
    2440:	0000acbe 	.word	0x0000acbe
    2444:	0000ac62 	.word	0x0000ac62
    2448:	0000ac7f 	.word	0x0000ac7f

0000244c <usage_fault.constprop.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
    244c:	b510      	push	{r4, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    244e:	4c1d      	ldr	r4, [pc, #116]	; (24c4 <usage_fault.constprop.0+0x78>)
	PR_FAULT_INFO("***** USAGE FAULT *****");
    2450:	481d      	ldr	r0, [pc, #116]	; (24c8 <usage_fault.constprop.0+0x7c>)
    2452:	2145      	movs	r1, #69	; 0x45
    2454:	f006 fc3d 	bl	8cd2 <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    2458:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    245a:	019b      	lsls	r3, r3, #6
    245c:	d503      	bpl.n	2466 <usage_fault.constprop.0+0x1a>
		PR_FAULT_INFO("  Division by zero");
    245e:	481b      	ldr	r0, [pc, #108]	; (24cc <usage_fault.constprop.0+0x80>)
    2460:	2145      	movs	r1, #69	; 0x45
    2462:	f006 fc36 	bl	8cd2 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    2466:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2468:	01dc      	lsls	r4, r3, #7
    246a:	d503      	bpl.n	2474 <usage_fault.constprop.0+0x28>
		PR_FAULT_INFO("  Unaligned memory access");
    246c:	4818      	ldr	r0, [pc, #96]	; (24d0 <usage_fault.constprop.0+0x84>)
    246e:	2145      	movs	r1, #69	; 0x45
    2470:	f006 fc2f 	bl	8cd2 <z_log_minimal_printk>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    2474:	4c13      	ldr	r4, [pc, #76]	; (24c4 <usage_fault.constprop.0+0x78>)
    2476:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2478:	0318      	lsls	r0, r3, #12
    247a:	d503      	bpl.n	2484 <usage_fault.constprop.0+0x38>
		PR_FAULT_INFO("  No coprocessor instructions");
    247c:	4815      	ldr	r0, [pc, #84]	; (24d4 <usage_fault.constprop.0+0x88>)
    247e:	2145      	movs	r1, #69	; 0x45
    2480:	f006 fc27 	bl	8cd2 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    2484:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2486:	0359      	lsls	r1, r3, #13
    2488:	d503      	bpl.n	2492 <usage_fault.constprop.0+0x46>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    248a:	4813      	ldr	r0, [pc, #76]	; (24d8 <usage_fault.constprop.0+0x8c>)
    248c:	2145      	movs	r1, #69	; 0x45
    248e:	f006 fc20 	bl	8cd2 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    2492:	4c0c      	ldr	r4, [pc, #48]	; (24c4 <usage_fault.constprop.0+0x78>)
    2494:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2496:	039a      	lsls	r2, r3, #14
    2498:	d503      	bpl.n	24a2 <usage_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Illegal use of the EPSR");
    249a:	4810      	ldr	r0, [pc, #64]	; (24dc <usage_fault.constprop.0+0x90>)
    249c:	2145      	movs	r1, #69	; 0x45
    249e:	f006 fc18 	bl	8cd2 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    24a2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    24a4:	03db      	lsls	r3, r3, #15
    24a6:	d503      	bpl.n	24b0 <usage_fault.constprop.0+0x64>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    24a8:	480d      	ldr	r0, [pc, #52]	; (24e0 <usage_fault.constprop.0+0x94>)
    24aa:	2145      	movs	r1, #69	; 0x45
    24ac:	f006 fc11 	bl	8cd2 <z_log_minimal_printk>
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    24b0:	4a04      	ldr	r2, [pc, #16]	; (24c4 <usage_fault.constprop.0+0x78>)
    24b2:	6a93      	ldr	r3, [r2, #40]	; 0x28
    24b4:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    24b8:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    24bc:	6293      	str	r3, [r2, #40]	; 0x28

	return reason;
}
    24be:	2000      	movs	r0, #0
    24c0:	bd10      	pop	{r4, pc}
    24c2:	bf00      	nop
    24c4:	e000ed00 	.word	0xe000ed00
    24c8:	0000acf2 	.word	0x0000acf2
    24cc:	0000ad0f 	.word	0x0000ad0f
    24d0:	0000ad27 	.word	0x0000ad27
    24d4:	0000ad46 	.word	0x0000ad46
    24d8:	0000ad69 	.word	0x0000ad69
    24dc:	0000ad93 	.word	0x0000ad93
    24e0:	0000adb2 	.word	0x0000adb2

000024e4 <bus_fault.constprop.0>:
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    24e4:	b570      	push	{r4, r5, r6, lr}
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    24e6:	4c23      	ldr	r4, [pc, #140]	; (2574 <bus_fault.constprop.0+0x90>)
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    24e8:	4606      	mov	r6, r0
    24ea:	460d      	mov	r5, r1
	PR_FAULT_INFO("***** BUS FAULT *****");
    24ec:	4822      	ldr	r0, [pc, #136]	; (2578 <bus_fault.constprop.0+0x94>)
    24ee:	2145      	movs	r1, #69	; 0x45
    24f0:	f006 fbef 	bl	8cd2 <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    24f4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    24f6:	04d9      	lsls	r1, r3, #19
    24f8:	d503      	bpl.n	2502 <bus_fault.constprop.0+0x1e>
		PR_FAULT_INFO("  Stacking error");
    24fa:	4820      	ldr	r0, [pc, #128]	; (257c <bus_fault.constprop.0+0x98>)
    24fc:	2145      	movs	r1, #69	; 0x45
    24fe:	f006 fbe8 	bl	8cd2 <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    2502:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2504:	051a      	lsls	r2, r3, #20
    2506:	d503      	bpl.n	2510 <bus_fault.constprop.0+0x2c>
		PR_FAULT_INFO("  Unstacking error");
    2508:	481d      	ldr	r0, [pc, #116]	; (2580 <bus_fault.constprop.0+0x9c>)
    250a:	2145      	movs	r1, #69	; 0x45
    250c:	f006 fbe1 	bl	8cd2 <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    2510:	4c18      	ldr	r4, [pc, #96]	; (2574 <bus_fault.constprop.0+0x90>)
    2512:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2514:	059b      	lsls	r3, r3, #22
    2516:	d510      	bpl.n	253a <bus_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Precise data bus error");
    2518:	481a      	ldr	r0, [pc, #104]	; (2584 <bus_fault.constprop.0+0xa0>)
    251a:	2145      	movs	r1, #69	; 0x45
    251c:	f006 fbd9 	bl	8cd2 <z_log_minimal_printk>
		STORE_xFAR(bfar, SCB->BFAR);
    2520:	6ba2      	ldr	r2, [r4, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    2522:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2524:	0418      	lsls	r0, r3, #16
    2526:	d508      	bpl.n	253a <bus_fault.constprop.0+0x56>
			PR_EXC("  BFAR Address: 0x%x", bfar);
    2528:	4817      	ldr	r0, [pc, #92]	; (2588 <bus_fault.constprop.0+0xa4>)
    252a:	2145      	movs	r1, #69	; 0x45
    252c:	f006 fbd1 	bl	8cd2 <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    2530:	b11e      	cbz	r6, 253a <bus_fault.constprop.0+0x56>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    2532:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2534:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    2538:	62a3      	str	r3, [r4, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    253a:	4c0e      	ldr	r4, [pc, #56]	; (2574 <bus_fault.constprop.0+0x90>)
    253c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    253e:	0559      	lsls	r1, r3, #21
    2540:	d503      	bpl.n	254a <bus_fault.constprop.0+0x66>
		PR_FAULT_INFO("  Imprecise data bus error");
    2542:	4812      	ldr	r0, [pc, #72]	; (258c <bus_fault.constprop.0+0xa8>)
    2544:	2145      	movs	r1, #69	; 0x45
    2546:	f006 fbc4 	bl	8cd2 <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    254a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    254c:	05da      	lsls	r2, r3, #23
    254e:	d50b      	bpl.n	2568 <bus_fault.constprop.0+0x84>
		PR_FAULT_INFO("  Instruction bus error");
    2550:	480f      	ldr	r0, [pc, #60]	; (2590 <bus_fault.constprop.0+0xac>)
    2552:	2145      	movs	r1, #69	; 0x45
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    2554:	f006 fbbd 	bl	8cd2 <z_log_minimal_printk>
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2558:	4a06      	ldr	r2, [pc, #24]	; (2574 <bus_fault.constprop.0+0x90>)
    255a:	6a93      	ldr	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    255c:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    255e:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    2562:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    2564:	7028      	strb	r0, [r5, #0]
}
    2566:	bd70      	pop	{r4, r5, r6, pc}
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    2568:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    256a:	049b      	lsls	r3, r3, #18
    256c:	d5f4      	bpl.n	2558 <bus_fault.constprop.0+0x74>
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    256e:	4809      	ldr	r0, [pc, #36]	; (2594 <bus_fault.constprop.0+0xb0>)
    2570:	2145      	movs	r1, #69	; 0x45
    2572:	e7ef      	b.n	2554 <bus_fault.constprop.0+0x70>
    2574:	e000ed00 	.word	0xe000ed00
    2578:	0000ade2 	.word	0x0000ade2
    257c:	0000adfd 	.word	0x0000adfd
    2580:	0000ac4a 	.word	0x0000ac4a
    2584:	0000ae13 	.word	0x0000ae13
    2588:	0000ae31 	.word	0x0000ae31
    258c:	0000ae4b 	.word	0x0000ae4b
    2590:	0000ae6b 	.word	0x0000ae6b
    2594:	0000acbe 	.word	0x0000acbe

00002598 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    2598:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    259c:	4b5d      	ldr	r3, [pc, #372]	; (2714 <z_arm_fault+0x17c>)
    259e:	685f      	ldr	r7, [r3, #4]
{
    25a0:	b09c      	sub	sp, #112	; 0x70
    25a2:	4605      	mov	r5, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    25a4:	f3c7 0408 	ubfx	r4, r7, #0, #9
    25a8:	2600      	movs	r6, #0
    25aa:	f386 8811 	msr	BASEPRI, r6
    25ae:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    25b2:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    25b6:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    25ba:	d107      	bne.n	25cc <z_arm_fault+0x34>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    25bc:	f002 030c 	and.w	r3, r2, #12
    25c0:	2b08      	cmp	r3, #8
    25c2:	d114      	bne.n	25ee <z_arm_fault+0x56>
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    25c4:	4854      	ldr	r0, [pc, #336]	; (2718 <z_arm_fault+0x180>)
    25c6:	2145      	movs	r1, #69	; 0x45
    25c8:	f006 fb83 	bl	8cd2 <z_log_minimal_printk>
	*nested_exc = false;
    25cc:	2600      	movs	r6, #0
		return NULL;
    25ce:	4635      	mov	r5, r6
	*recoverable = false;
    25d0:	f04f 0800 	mov.w	r8, #0
	switch (fault) {
    25d4:	1ee3      	subs	r3, r4, #3
	*recoverable = false;
    25d6:	f88d 8007 	strb.w	r8, [sp, #7]
	switch (fault) {
    25da:	2b09      	cmp	r3, #9
    25dc:	f200 8087 	bhi.w	26ee <z_arm_fault+0x156>
    25e0:	e8df f003 	tbb	[pc, r3]
    25e4:	767e7a0a 	.word	0x767e7a0a
    25e8:	85858585 	.word	0x85858585
    25ec:	8285      	.short	0x8285
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    25ee:	0710      	lsls	r0, r2, #28
			ptr_esf =  (z_arch_esf_t *)psp;
    25f0:	bf4c      	ite	mi
    25f2:	460d      	movmi	r5, r1
			*nested_exc = true;
    25f4:	2601      	movpl	r6, #1
    25f6:	e7eb      	b.n	25d0 <z_arm_fault+0x38>
	PR_FAULT_INFO("***** HARD FAULT *****");
    25f8:	4848      	ldr	r0, [pc, #288]	; (271c <z_arm_fault+0x184>)
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    25fa:	4c46      	ldr	r4, [pc, #280]	; (2714 <z_arm_fault+0x17c>)
	PR_FAULT_INFO("***** HARD FAULT *****");
    25fc:	2145      	movs	r1, #69	; 0x45
    25fe:	f006 fb68 	bl	8cd2 <z_log_minimal_printk>
	*recoverable = false;
    2602:	f88d 8007 	strb.w	r8, [sp, #7]
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2606:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    2608:	079a      	lsls	r2, r3, #30
    260a:	d505      	bpl.n	2618 <z_arm_fault+0x80>
		PR_EXC("  Bus fault on vector table read");
    260c:	4844      	ldr	r0, [pc, #272]	; (2720 <z_arm_fault+0x188>)
    260e:	2145      	movs	r1, #69	; 0x45
	PR_FAULT_INFO(
    2610:	f006 fb5f 	bl	8cd2 <z_log_minimal_printk>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    2614:	2400      	movs	r4, #0
    2616:	e033      	b.n	2680 <z_arm_fault+0xe8>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    2618:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    261a:	2b00      	cmp	r3, #0
    261c:	da02      	bge.n	2624 <z_arm_fault+0x8c>
		PR_EXC("  Debug event");
    261e:	4841      	ldr	r0, [pc, #260]	; (2724 <z_arm_fault+0x18c>)
    2620:	2145      	movs	r1, #69	; 0x45
    2622:	e7f5      	b.n	2610 <z_arm_fault+0x78>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    2624:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    2626:	005b      	lsls	r3, r3, #1
    2628:	d5f4      	bpl.n	2614 <z_arm_fault+0x7c>
		PR_EXC("  Fault escalation (see below)");
    262a:	483f      	ldr	r0, [pc, #252]	; (2728 <z_arm_fault+0x190>)
    262c:	2145      	movs	r1, #69	; 0x45
    262e:	f006 fb50 	bl	8cd2 <z_log_minimal_printk>
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    2632:	6963      	ldr	r3, [r4, #20]
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    2634:	69aa      	ldr	r2, [r5, #24]
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    2636:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    263a:	6163      	str	r3, [r4, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    263c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2640:	f3bf 8f6f 	isb	sy
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    2644:	6963      	ldr	r3, [r4, #20]
	uint16_t fault_insn = *(ret_addr - 1);
    2646:	f832 2c02 	ldrh.w	r2, [r2, #-2]
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    264a:	f423 7380 	bic.w	r3, r3, #256	; 0x100
    264e:	6163      	str	r3, [r4, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    2650:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2654:	f3bf 8f6f 	isb	sy
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    2658:	f64d 7302 	movw	r3, #57090	; 0xdf02
    265c:	429a      	cmp	r2, r3
    265e:	d009      	beq.n	2674 <z_arm_fault+0xdc>
		} else if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) != 0) {
    2660:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2662:	b2db      	uxtb	r3, r3
    2664:	b333      	cbz	r3, 26b4 <z_arm_fault+0x11c>
			reason = mem_manage_fault(esf, 1, recoverable);
    2666:	f10d 0207 	add.w	r2, sp, #7
    266a:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    266c:	4628      	mov	r0, r5
    266e:	f7ff fe75 	bl	235c <mem_manage_fault>
    2672:	e02f      	b.n	26d4 <z_arm_fault+0x13c>
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
    2674:	682a      	ldr	r2, [r5, #0]
    2676:	482d      	ldr	r0, [pc, #180]	; (272c <z_arm_fault+0x194>)
    2678:	2145      	movs	r1, #69	; 0x45
    267a:	f006 fb2a 	bl	8cd2 <z_log_minimal_printk>
			reason = esf->basic.r0;
    267e:	682c      	ldr	r4, [r5, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    2680:	f89d 3007 	ldrb.w	r3, [sp, #7]
    2684:	b99b      	cbnz	r3, 26ae <z_arm_fault+0x116>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    2686:	2268      	movs	r2, #104	; 0x68
    2688:	4629      	mov	r1, r5
    268a:	a802      	add	r0, sp, #8
    268c:	f006 fbd3 	bl	8e36 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    2690:	9b09      	ldr	r3, [sp, #36]	; 0x24
    2692:	2e00      	cmp	r6, #0
    2694:	d038      	beq.n	2708 <z_arm_fault+0x170>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    2696:	f3c3 0208 	ubfx	r2, r3, #0, #9
    269a:	b922      	cbnz	r2, 26a6 <z_arm_fault+0x10e>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    269c:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    26a0:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    26a4:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    26a6:	a902      	add	r1, sp, #8
    26a8:	4620      	mov	r0, r4
    26aa:	f7ff fc2f 	bl	1f0c <z_arm_fatal_error>
}
    26ae:	b01c      	add	sp, #112	; 0x70
    26b0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		} else if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) != 0) {
    26b4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    26b6:	f413 4f7f 	tst.w	r3, #65280	; 0xff00
    26ba:	d005      	beq.n	26c8 <z_arm_fault+0x130>
			reason = bus_fault(esf, 1, recoverable);
    26bc:	f10d 0107 	add.w	r1, sp, #7
    26c0:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    26c2:	f7ff ff0f 	bl	24e4 <bus_fault.constprop.0>
    26c6:	e005      	b.n	26d4 <z_arm_fault+0x13c>
		} else if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) != 0) {
    26c8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    26ca:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    26ce:	d3a1      	bcc.n	2614 <z_arm_fault+0x7c>
			reason = usage_fault(esf);
    26d0:	f7ff febc 	bl	244c <usage_fault.constprop.0>
    26d4:	4604      	mov	r4, r0
    26d6:	e7d3      	b.n	2680 <z_arm_fault+0xe8>
		reason = mem_manage_fault(esf, 0, recoverable);
    26d8:	f10d 0207 	add.w	r2, sp, #7
    26dc:	2100      	movs	r1, #0
    26de:	e7c5      	b.n	266c <z_arm_fault+0xd4>
		reason = bus_fault(esf, 0, recoverable);
    26e0:	f10d 0107 	add.w	r1, sp, #7
    26e4:	2000      	movs	r0, #0
    26e6:	e7ec      	b.n	26c2 <z_arm_fault+0x12a>
	PR_FAULT_INFO(
    26e8:	4811      	ldr	r0, [pc, #68]	; (2730 <z_arm_fault+0x198>)
    26ea:	2145      	movs	r1, #69	; 0x45
    26ec:	e790      	b.n	2610 <z_arm_fault+0x78>
	PR_FAULT_INFO("***** %s %d) *****",
    26ee:	4911      	ldr	r1, [pc, #68]	; (2734 <z_arm_fault+0x19c>)
    26f0:	4a11      	ldr	r2, [pc, #68]	; (2738 <z_arm_fault+0x1a0>)
    26f2:	4812      	ldr	r0, [pc, #72]	; (273c <z_arm_fault+0x1a4>)
    26f4:	f417 7ff8 	tst.w	r7, #496	; 0x1f0
    26f8:	bf08      	it	eq
    26fa:	460a      	moveq	r2, r1
    26fc:	f1a4 0310 	sub.w	r3, r4, #16
    2700:	2145      	movs	r1, #69	; 0x45
    2702:	f006 fae6 	bl	8cd2 <z_log_minimal_printk>
}
    2706:	e785      	b.n	2614 <z_arm_fault+0x7c>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2708:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    270c:	f023 0301 	bic.w	r3, r3, #1
    2710:	e7c8      	b.n	26a4 <z_arm_fault+0x10c>
    2712:	bf00      	nop
    2714:	e000ed00 	.word	0xe000ed00
    2718:	0000aeb6 	.word	0x0000aeb6
    271c:	0000aee6 	.word	0x0000aee6
    2720:	0000af02 	.word	0x0000af02
    2724:	0000af28 	.word	0x0000af28
    2728:	0000af3b 	.word	0x0000af3b
    272c:	0000af5f 	.word	0x0000af5f
    2730:	0000af80 	.word	0x0000af80
    2734:	0000ae88 	.word	0x0000ae88
    2738:	0000ae9d 	.word	0x0000ae9d
    273c:	0000afa9 	.word	0x0000afa9

00002740 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    2740:	4a02      	ldr	r2, [pc, #8]	; (274c <z_arm_fault_init+0xc>)
    2742:	6953      	ldr	r3, [r2, #20]
    2744:	f043 0310 	orr.w	r3, r3, #16
    2748:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    274a:	4770      	bx	lr
    274c:	e000ed00 	.word	0xe000ed00

00002750 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    2750:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    2754:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    2758:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    275a:	4672      	mov	r2, lr
	bl z_arm_fault
    275c:	f7ff ff1c 	bl	2598 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    2760:	bd01      	pop	{r0, pc}
    2762:	bf00      	nop

00002764 <z_arm_interrupt_init>:
    2764:	4804      	ldr	r0, [pc, #16]	; (2778 <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    2766:	2300      	movs	r3, #0
    2768:	2120      	movs	r1, #32
    276a:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    276c:	3301      	adds	r3, #1
    276e:	2b30      	cmp	r3, #48	; 0x30
    2770:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    2774:	d1f9      	bne.n	276a <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    2776:	4770      	bx	lr
    2778:	e000e100 	.word	0xe000e100

0000277c <__start>:
    strb r0, [r1]
#endif /* CONFIG_DEBUG_THREAD_INFO */

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    277c:	2000      	movs	r0, #0
    msr CONTROL, r0
    277e:	f380 8814 	msr	CONTROL, r0
    isb
    2782:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_PM_S2RAM)
    bl arch_pm_s2ram_resume
#endif /* CONFIG_PM_S2RAM */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    2786:	f7ff f925 	bl	19d4 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    278a:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    278c:	490d      	ldr	r1, [pc, #52]	; (27c4 <__start+0x48>)
    str r0, [r1]
    278e:	6008      	str	r0, [r1, #0]
    dsb
    2790:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2794:	480c      	ldr	r0, [pc, #48]	; (27c8 <__start+0x4c>)
    msr msp, r0
    2796:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    279a:	f000 f82b 	bl	27f4 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    279e:	2020      	movs	r0, #32
    msr BASEPRI, r0
    27a0:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    27a4:	4809      	ldr	r0, [pc, #36]	; (27cc <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    27a6:	f44f 6104 	mov.w	r1, #2112	; 0x840
    adds r0, r0, r1
    27aa:	1840      	adds	r0, r0, r1
    msr PSP, r0
    27ac:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    27b0:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    27b4:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    27b6:	4308      	orrs	r0, r1
    msr CONTROL, r0
    27b8:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    27bc:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    27c0:	f7ff fc56 	bl	2070 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    27c4:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    27c8:	20005900 	.word	0x20005900
    ldr r0, =z_interrupt_stacks
    27cc:	20002700 	.word	0x20002700

000027d0 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    27d0:	4907      	ldr	r1, [pc, #28]	; (27f0 <z_arm_clear_arm_mpu_config+0x20>)
    27d2:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    27d6:	2300      	movs	r3, #0
	int num_regions =
    27d8:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    27dc:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    27de:	4293      	cmp	r3, r2
    27e0:	db00      	blt.n	27e4 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    27e2:	4770      	bx	lr
  MPU->RNR = rnr;
    27e4:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    27e8:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    27ec:	3301      	adds	r3, #1
    27ee:	e7f6      	b.n	27de <z_arm_clear_arm_mpu_config+0xe>
    27f0:	e000ed00 	.word	0xe000ed00

000027f4 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    27f4:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    27f6:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    27f8:	2300      	movs	r3, #0
    27fa:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    27fe:	f7ff ffe7 	bl	27d0 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    2802:	4b14      	ldr	r3, [pc, #80]	; (2854 <CONFIG_MAIN_STACK_SIZE+0x54>)
    2804:	f04f 32ff 	mov.w	r2, #4294967295
    2808:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    280c:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    2810:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    2814:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    2818:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    281c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    2820:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    2824:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    2828:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    282c:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    2830:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    2834:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    2838:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    283c:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    2840:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    2844:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    2848:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    284a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    284e:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    2852:	bd08      	pop	{r3, pc}
    2854:	e000e100 	.word	0xe000e100

00002858 <z_impl_k_thread_abort>:
#include <zephyr/wait_q.h>
#include <zephyr/sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    2858:	4b08      	ldr	r3, [pc, #32]	; (287c <z_impl_k_thread_abort+0x24>)
    285a:	689b      	ldr	r3, [r3, #8]
    285c:	4283      	cmp	r3, r0
    285e:	d10b      	bne.n	2878 <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    2860:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    2864:	b143      	cbz	r3, 2878 <z_impl_k_thread_abort+0x20>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    2866:	4b06      	ldr	r3, [pc, #24]	; (2880 <z_impl_k_thread_abort+0x28>)
    2868:	685a      	ldr	r2, [r3, #4]
    286a:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
    286e:	605a      	str	r2, [r3, #4]
			/* Clear any system calls that may be pending
			 * as they have a higher priority than the PendSV
			 * handler and will check the stack of the thread
			 * being aborted.
			 */
			SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk;
    2870:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    2872:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    2876:	625a      	str	r2, [r3, #36]	; 0x24
		}
	}

	z_thread_abort(thread);
    2878:	f004 b808 	b.w	688c <z_thread_abort>
    287c:	20001fa0 	.word	0x20001fa0
    2880:	e000ed00 	.word	0xe000ed00

00002884 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    2884:	4b02      	ldr	r3, [pc, #8]	; (2890 <z_arm_configure_static_mpu_regions+0xc>)
    2886:	4a03      	ldr	r2, [pc, #12]	; (2894 <z_arm_configure_static_mpu_regions+0x10>)
    2888:	4803      	ldr	r0, [pc, #12]	; (2898 <z_arm_configure_static_mpu_regions+0x14>)
    288a:	2101      	movs	r1, #1
    288c:	f000 b882 	b.w	2994 <arm_core_mpu_configure_static_mpu_regions>
    2890:	20040000 	.word	0x20040000
    2894:	20000000 	.word	0x20000000
    2898:	0000a1f8 	.word	0x0000a1f8

0000289c <z_arm_configure_dynamic_mpu_regions>:
 *
 * This function is not inherently thread-safe, but the memory domain
 * spinlock needs to be held anyway.
 */
void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread)
{
    289c:	b510      	push	{r4, lr}
    289e:	4604      	mov	r4, r0
	/* Privileged stack guard */
	uintptr_t guard_start;
	size_t guard_size = MPU_GUARD_ALIGN_AND_SIZE;

#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
	guard_size = z_arm_mpu_stack_guard_and_fpu_adjust(thread);
    28a0:	f7ff fcb6 	bl	2210 <z_arm_mpu_stack_guard_and_fpu_adjust>
#endif /* CONFIG_USERSPACE */
	{
		/* A supervisor thread only has the normal thread stack to
		 * protect with a stack guard.
		 */
		guard_start = thread->stack_info.start - guard_size;
    28a4:	6e62      	ldr	r2, [r4, #100]	; 0x64
	guard_size = z_arm_mpu_stack_guard_and_fpu_adjust(thread);
    28a6:	4603      	mov	r3, r0
	}

	__ASSERT(region_num < _MAX_DYNAMIC_MPU_REGIONS_NUM,
		"Out-of-bounds error for dynamic region map.");

	dynamic_regions[region_num].start = guard_start;
    28a8:	4805      	ldr	r0, [pc, #20]	; (28c0 <z_arm_configure_dynamic_mpu_regions+0x24>)
		guard_start = thread->stack_info.start - guard_size;
    28aa:	1ad2      	subs	r2, r2, r3
	dynamic_regions[region_num].size = guard_size;
    28ac:	e9c0 2300 	strd	r2, r3, [r0]
	dynamic_regions[region_num].attr = K_MEM_PARTITION_P_RO_U_NA;
    28b0:	4b04      	ldr	r3, [pc, #16]	; (28c4 <z_arm_configure_dynamic_mpu_regions+0x28>)
    28b2:	6083      	str	r3, [r0, #8]
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
						   region_num);
#ifdef CONFIG_AARCH32_ARMV8_R
	arm_core_mpu_enable();
#endif
}
    28b4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
    28b8:	2101      	movs	r1, #1
    28ba:	f000 b875 	b.w	29a8 <arm_core_mpu_configure_dynamic_mpu_regions>
    28be:	bf00      	nop
    28c0:	20001de0 	.word	0x20001de0
    28c4:	150b0000 	.word	0x150b0000

000028c8 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    28c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    28ca:	4e24      	ldr	r6, [pc, #144]	; (295c <mpu_configure_regions+0x94>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    28cc:	2500      	movs	r5, #0
    28ce:	428d      	cmp	r5, r1
    28d0:	da0f      	bge.n	28f2 <mpu_configure_regions+0x2a>
		if (regions[i].size == 0U) {
    28d2:	6844      	ldr	r4, [r0, #4]
    28d4:	2c00      	cmp	r4, #0
    28d6:	d03e      	beq.n	2956 <mpu_configure_regions+0x8e>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    28d8:	b19b      	cbz	r3, 2902 <mpu_configure_regions+0x3a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    28da:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    28de:	ea14 0f0c 	tst.w	r4, ip
    28e2:	d008      	beq.n	28f6 <mpu_configure_regions+0x2e>
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
    28e4:	481e      	ldr	r0, [pc, #120]	; (2960 <mpu_configure_regions+0x98>)
    28e6:	462a      	mov	r2, r5
    28e8:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    28ea:	f006 f9f2 	bl	8cd2 <z_log_minimal_printk>
			return -EINVAL;
    28ee:	f06f 0215 	mvn.w	r2, #21
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    28f2:	4610      	mov	r0, r2
    28f4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		&&
    28f6:	2c1f      	cmp	r4, #31
    28f8:	d9f4      	bls.n	28e4 <mpu_configure_regions+0x1c>
		((part->start & (part->size - 1U)) == 0U);
    28fa:	6807      	ldr	r7, [r0, #0]
		&&
    28fc:	ea1c 0f07 	tst.w	ip, r7
    2900:	d1f0      	bne.n	28e4 <mpu_configure_regions+0x1c>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    2902:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    2904:	6807      	ldr	r7, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2906:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    290a:	fa5f fe82 	uxtb.w	lr, r2
	if (size <= 32U) {
    290e:	d910      	bls.n	2932 <mpu_configure_regions+0x6a>
	if (size > (1UL << 31)) {
    2910:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    2914:	d80f      	bhi.n	2936 <mpu_configure_regions+0x6e>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    2916:	3c01      	subs	r4, #1
    2918:	fab4 f484 	clz	r4, r4
    291c:	f1c4 041f 	rsb	r4, r4, #31
    2920:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    2922:	f1be 0f07 	cmp.w	lr, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2926:	ea4c 0c04 	orr.w	ip, ip, r4
    292a:	d906      	bls.n	293a <mpu_configure_regions+0x72>
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    292c:	480d      	ldr	r0, [pc, #52]	; (2964 <mpu_configure_regions+0x9c>)
    292e:	2145      	movs	r1, #69	; 0x45
    2930:	e7db      	b.n	28ea <mpu_configure_regions+0x22>
		return REGION_32B;
    2932:	2408      	movs	r4, #8
    2934:	e7f5      	b.n	2922 <mpu_configure_regions+0x5a>
		return REGION_4G;
    2936:	243e      	movs	r4, #62	; 0x3e
    2938:	e7f3      	b.n	2922 <mpu_configure_regions+0x5a>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    293a:	f027 041f 	bic.w	r4, r7, #31
				| MPU_RBAR_VALID_Msk | index;
    293e:	4314      	orrs	r4, r2
    2940:	f044 0410 	orr.w	r4, r4, #16
    2944:	f8c6 2098 	str.w	r2, [r6, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2948:	f8c6 409c 	str.w	r4, [r6, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    294c:	f04c 0401 	orr.w	r4, ip, #1
    2950:	f8c6 40a0 	str.w	r4, [r6, #160]	; 0xa0
		reg_index++;
    2954:	3201      	adds	r2, #1
	for (i = 0; i < regions_num; i++) {
    2956:	3501      	adds	r5, #1
    2958:	300c      	adds	r0, #12
    295a:	e7b8      	b.n	28ce <mpu_configure_regions+0x6>
    295c:	e000ed00 	.word	0xe000ed00
    2960:	0000afc5 	.word	0x0000afc5
    2964:	0000afed 	.word	0x0000afed

00002968 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    2968:	4b04      	ldr	r3, [pc, #16]	; (297c <arm_core_mpu_enable+0x14>)
    296a:	2205      	movs	r2, #5
    296c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    2970:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2974:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    2978:	4770      	bx	lr
    297a:	bf00      	nop
    297c:	e000ed00 	.word	0xe000ed00

00002980 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    2980:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    2984:	4b02      	ldr	r3, [pc, #8]	; (2990 <arm_core_mpu_disable+0x10>)
    2986:	2200      	movs	r2, #0
    2988:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    298c:	4770      	bx	lr
    298e:	bf00      	nop
    2990:	e000ed00 	.word	0xe000ed00

00002994 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	*static_regions, const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    2994:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    2996:	4c03      	ldr	r4, [pc, #12]	; (29a4 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    2998:	2301      	movs	r3, #1
    299a:	7822      	ldrb	r2, [r4, #0]
    299c:	f7ff ff94 	bl	28c8 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    29a0:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    29a2:	bd10      	pop	{r4, pc}
    29a4:	200022b9 	.word	0x200022b9

000029a8 <arm_core_mpu_configure_dynamic_mpu_regions>:
/**
 * @brief configure dynamic MPU regions.
 */
void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
	*dynamic_regions, uint8_t regions_num)
{
    29a8:	b508      	push	{r3, lr}

	/* In ARMv7-M architecture the dynamic regions are
	 * programmed on top of existing SRAM region configuration.
	 */

	mpu_reg_index = mpu_configure_regions(dynamic_regions,
    29aa:	4a09      	ldr	r2, [pc, #36]	; (29d0 <arm_core_mpu_configure_dynamic_mpu_regions+0x28>)
    29ac:	2300      	movs	r3, #0
    29ae:	7812      	ldrb	r2, [r2, #0]
    29b0:	f7ff ff8a 	bl	28c8 <mpu_configure_regions>
		regions_num, mpu_reg_index, false);

	if (mpu_reg_index != -EINVAL) {
    29b4:	f110 0f16 	cmn.w	r0, #22
    29b8:	d003      	beq.n	29c2 <arm_core_mpu_configure_dynamic_mpu_regions+0x1a>
  MPU->RNR = rnr;
    29ba:	4b06      	ldr	r3, [pc, #24]	; (29d4 <arm_core_mpu_configure_dynamic_mpu_regions+0x2c>)
  MPU->RASR = 0U;
    29bc:	2200      	movs	r2, #0

		/* Disable the non-programmed MPU regions. */
		for (int i = mpu_reg_index; i < get_num_regions(); i++) {
    29be:	2807      	cmp	r0, #7
    29c0:	dd00      	ble.n	29c4 <arm_core_mpu_configure_dynamic_mpu_regions+0x1c>
		== -EINVAL) {

		__ASSERT(0, "Configuring %u dynamic MPU regions failed\n",
			regions_num);
	}
}
    29c2:	bd08      	pop	{r3, pc}
  MPU->RNR = rnr;
    29c4:	f8c3 0098 	str.w	r0, [r3, #152]	; 0x98
  MPU->RASR = 0U;
    29c8:	f8c3 20a0 	str.w	r2, [r3, #160]	; 0xa0
    29cc:	3001      	adds	r0, #1
    29ce:	e7f6      	b.n	29be <arm_core_mpu_configure_dynamic_mpu_regions+0x16>
    29d0:	200022b9 	.word	0x200022b9
    29d4:	e000ed00 	.word	0xe000ed00

000029d8 <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    29d8:	4914      	ldr	r1, [pc, #80]	; (2a2c <z_arm_mpu_init+0x54>)
    29da:	6808      	ldr	r0, [r1, #0]
    29dc:	2808      	cmp	r0, #8
{
    29de:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    29e0:	d821      	bhi.n	2a26 <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    29e2:	f7ff ffcd 	bl	2980 <arm_core_mpu_disable>
    29e6:	4c12      	ldr	r4, [pc, #72]	; (2a30 <z_arm_mpu_init+0x58>)
    29e8:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    29ea:	2200      	movs	r2, #0
    29ec:	4290      	cmp	r0, r2
    29ee:	f101 010c 	add.w	r1, r1, #12
    29f2:	d105      	bne.n	2a00 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    29f4:	4b0f      	ldr	r3, [pc, #60]	; (2a34 <z_arm_mpu_init+0x5c>)
    29f6:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    29f8:	f7ff ffb6 	bl	2968 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    29fc:	2000      	movs	r0, #0
}
    29fe:	bd10      	pop	{r4, pc}
    2a00:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2a04:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    2a08:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    2a0c:	4313      	orrs	r3, r2
    2a0e:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2a12:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2a16:	f851 3c04 	ldr.w	r3, [r1, #-4]
    2a1a:	f043 0301 	orr.w	r3, r3, #1
    2a1e:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2a22:	3201      	adds	r2, #1
    2a24:	e7e2      	b.n	29ec <z_arm_mpu_init+0x14>
		return -1;
    2a26:	f04f 30ff 	mov.w	r0, #4294967295
    2a2a:	e7e8      	b.n	29fe <z_arm_mpu_init+0x26>
    2a2c:	0000a204 	.word	0x0000a204
    2a30:	e000ed00 	.word	0xe000ed00
    2a34:	200022b9 	.word	0x200022b9

00002a38 <__stdout_hook_install>:

static int (*_stdout_hook)(int c) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int c))
{
	_stdout_hook = hook;
    2a38:	4b01      	ldr	r3, [pc, #4]	; (2a40 <__stdout_hook_install+0x8>)
    2a3a:	6018      	str	r0, [r3, #0]
}
    2a3c:	4770      	bx	lr
    2a3e:	bf00      	nop
    2a40:	20000034 	.word	0x20000034

00002a44 <nordicsemi_nrf52_init>:
	nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
	NVIC_SystemReset();
}

static int nordicsemi_nrf52_init(const struct device *arg)
{
    2a44:	b510      	push	{r4, lr}
	__asm__ volatile(
    2a46:	f04f 0320 	mov.w	r3, #32
    2a4a:	f3ef 8011 	mrs	r0, BASEPRI
    2a4e:	f383 8812 	msr	BASEPRI_MAX, r3
    2a52:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    2a56:	4a11      	ldr	r2, [pc, #68]	; (2a9c <nordicsemi_nrf52_init+0x58>)
    2a58:	2301      	movs	r3, #1
    2a5a:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    2a5e:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
{
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2a62:	f04f 5180 	mov.w	r1, #268435456	; 0x10000000
    2a66:	f8c2 3578 	str.w	r3, [r2, #1400]	; 0x578
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    2a6a:	f8d1 4130 	ldr.w	r4, [r1, #304]	; 0x130
    2a6e:	2c08      	cmp	r4, #8
    2a70:	d108      	bne.n	2a84 <nordicsemi_nrf52_init+0x40>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    2a72:	f8d1 1134 	ldr.w	r1, [r1, #308]	; 0x134
            {
                switch(var2)
    2a76:	2905      	cmp	r1, #5
    2a78:	d804      	bhi.n	2a84 <nordicsemi_nrf52_init+0x40>
#endif // defined(POWER_RAM_POWER_S0POWER_Msk)

#if NRF_POWER_HAS_DCDCEN_VDDH
NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
{
    if (enable && nrf52_errata_197())
    2a7a:	4c09      	ldr	r4, [pc, #36]	; (2aa0 <nordicsemi_nrf52_init+0x5c>)
    2a7c:	5c61      	ldrb	r1, [r4, r1]
    2a7e:	b109      	cbz	r1, 2a84 <nordicsemi_nrf52_init+0x40>
    {
        // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
        *(volatile uint32_t *)0x40000638ul = 1ul;
    2a80:	f8c2 3638 	str.w	r3, [r2, #1592]	; 0x638
    }
    p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
    2a84:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a88:	2201      	movs	r2, #1
    2a8a:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
	__asm__ volatile(
    2a8e:	f380 8811 	msr	BASEPRI, r0
    2a92:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    2a96:	2000      	movs	r0, #0
    2a98:	bd10      	pop	{r4, pc}
    2a9a:	bf00      	nop
    2a9c:	4001e000 	.word	0x4001e000
    2aa0:	0000b027 	.word	0x0000b027

00002aa4 <sys_arch_reboot>:
    *p_gpregret = val;
    2aa4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2aa8:	b2c0      	uxtb	r0, r0
    2aaa:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    2aae:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2ab2:	4905      	ldr	r1, [pc, #20]	; (2ac8 <sys_arch_reboot+0x24>)
    2ab4:	4b05      	ldr	r3, [pc, #20]	; (2acc <sys_arch_reboot+0x28>)
    2ab6:	68ca      	ldr	r2, [r1, #12]
    2ab8:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2abc:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2abe:	60cb      	str	r3, [r1, #12]
    2ac0:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2ac4:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2ac6:	e7fd      	b.n	2ac4 <sys_arch_reboot+0x20>
    2ac8:	e000ed00 	.word	0xe000ed00
    2acc:	05fa0004 	.word	0x05fa0004

00002ad0 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    2ad0:	b120      	cbz	r0, 2adc <arch_busy_wait+0xc>
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    2ad2:	4b03      	ldr	r3, [pc, #12]	; (2ae0 <arch_busy_wait+0x10>)
    2ad4:	0180      	lsls	r0, r0, #6
    2ad6:	f043 0301 	orr.w	r3, r3, #1
    2ada:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    2adc:	4770      	bx	lr
    2ade:	bf00      	nop
    2ae0:	0000a120 	.word	0x0000a120

00002ae4 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    2ae4:	4b08      	ldr	r3, [pc, #32]	; (2b08 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    2ae6:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    2ae8:	1ac3      	subs	r3, r0, r3
{
    2aea:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    2aec:	4907      	ldr	r1, [pc, #28]	; (2b0c <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    2aee:	109b      	asrs	r3, r3, #2
{
    2af0:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    2af2:	4359      	muls	r1, r3
    2af4:	4806      	ldr	r0, [pc, #24]	; (2b10 <onoff_stop+0x2c>)
    2af6:	2240      	movs	r2, #64	; 0x40
    2af8:	f006 f9e2 	bl	8ec0 <stop>
	notify(mgr, res);
    2afc:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    2afe:	4601      	mov	r1, r0
	notify(mgr, res);
    2b00:	4620      	mov	r0, r4
}
    2b02:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    2b06:	4718      	bx	r3
    2b08:	20001e00 	.word	0x20001e00
    2b0c:	b6db6db7 	.word	0xb6db6db7
    2b10:	00009e04 	.word	0x00009e04

00002b14 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    2b14:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    2b16:	4c0c      	ldr	r4, [pc, #48]	; (2b48 <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2b18:	4a0c      	ldr	r2, [pc, #48]	; (2b4c <onoff_start+0x38>)
    2b1a:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    2b1c:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2b1e:	9300      	str	r3, [sp, #0]
{
    2b20:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2b22:	460b      	mov	r3, r1
    2b24:	490a      	ldr	r1, [pc, #40]	; (2b50 <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    2b26:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2b28:	4361      	muls	r1, r4
{
    2b2a:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2b2c:	4809      	ldr	r0, [pc, #36]	; (2b54 <onoff_start+0x40>)
    2b2e:	f006 f9f3 	bl	8f18 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    2b32:	1e01      	subs	r1, r0, #0
    2b34:	da05      	bge.n	2b42 <onoff_start+0x2e>
		notify(mgr, err);
    2b36:	4630      	mov	r0, r6
    2b38:	462b      	mov	r3, r5
	}
}
    2b3a:	b002      	add	sp, #8
    2b3c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    2b40:	4718      	bx	r3
}
    2b42:	b002      	add	sp, #8
    2b44:	bd70      	pop	{r4, r5, r6, pc}
    2b46:	bf00      	nop
    2b48:	20001e00 	.word	0x20001e00
    2b4c:	00008f83 	.word	0x00008f83
    2b50:	b6db6db7 	.word	0xb6db6db7
    2b54:	00009e04 	.word	0x00009e04

00002b58 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2b58:	2200      	movs	r2, #0
{
    2b5a:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2b5c:	2101      	movs	r1, #1
{
    2b5e:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2b60:	4610      	mov	r0, r2
    2b62:	f7ff fa69 	bl	2038 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    2b66:	480f      	ldr	r0, [pc, #60]	; (2ba4 <clk_init+0x4c>)
    2b68:	f002 f8ca 	bl	4d00 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    2b6c:	4b0e      	ldr	r3, [pc, #56]	; (2ba8 <clk_init+0x50>)
    2b6e:	4298      	cmp	r0, r3
    2b70:	d115      	bne.n	2b9e <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    2b72:	f006 fe1a 	bl	97aa <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    2b76:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    2b78:	490c      	ldr	r1, [pc, #48]	; (2bac <clk_init+0x54>)
    2b7a:	4630      	mov	r0, r6
    2b7c:	f006 f81f 	bl	8bbe <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    2b80:	2800      	cmp	r0, #0
    2b82:	db0b      	blt.n	2b9c <clk_init+0x44>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    2b84:	2501      	movs	r5, #1
    2b86:	6435      	str	r5, [r6, #64]	; 0x40
	struct nrf_clock_control_data *data = dev->data;
    2b88:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    2b8a:	4908      	ldr	r1, [pc, #32]	; (2bac <clk_init+0x54>)
    2b8c:	f104 001c 	add.w	r0, r4, #28
    2b90:	f006 f815 	bl	8bbe <onoff_manager_init>
		if (err < 0) {
    2b94:	2800      	cmp	r0, #0
    2b96:	db01      	blt.n	2b9c <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    2b98:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    2b9a:	2000      	movs	r0, #0
}
    2b9c:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    2b9e:	f06f 0004 	mvn.w	r0, #4
    2ba2:	e7fb      	b.n	2b9c <clk_init+0x44>
    2ba4:	00002be5 	.word	0x00002be5
    2ba8:	0bad0000 	.word	0x0bad0000
    2bac:	0000a224 	.word	0x0000a224

00002bb0 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    2bb0:	b570      	push	{r4, r5, r6, lr}
    2bb2:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    2bb4:	230c      	movs	r3, #12
    2bb6:	4809      	ldr	r0, [pc, #36]	; (2bdc <clkstarted_handle.constprop.0+0x2c>)
    2bb8:	434b      	muls	r3, r1
    2bba:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    2bbc:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    2bc0:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    2bc2:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    2bc4:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    2bc6:	4418      	add	r0, r3
    2bc8:	f006 f967 	bl	8e9a <set_on_state>
	if (callback) {
    2bcc:	b12d      	cbz	r5, 2bda <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    2bce:	4632      	mov	r2, r6
    2bd0:	462b      	mov	r3, r5
    2bd2:	4803      	ldr	r0, [pc, #12]	; (2be0 <clkstarted_handle.constprop.0+0x30>)
}
    2bd4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    2bd8:	4718      	bx	r3
}
    2bda:	bd70      	pop	{r4, r5, r6, pc}
    2bdc:	20001e00 	.word	0x20001e00
    2be0:	00009e04 	.word	0x00009e04

00002be4 <clock_event_handler>:
	switch (event) {
    2be4:	b110      	cbz	r0, 2bec <clock_event_handler+0x8>
    2be6:	2801      	cmp	r0, #1
    2be8:	d004      	beq.n	2bf4 <clock_event_handler+0x10>
    2bea:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    2bec:	4b03      	ldr	r3, [pc, #12]	; (2bfc <clock_event_handler+0x18>)
    2bee:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    2bf0:	075b      	lsls	r3, r3, #29
    2bf2:	d101      	bne.n	2bf8 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    2bf4:	f7ff bfdc 	b.w	2bb0 <clkstarted_handle.constprop.0>
}
    2bf8:	4770      	bx	lr
    2bfa:	bf00      	nop
    2bfc:	20001e00 	.word	0x20001e00

00002c00 <generic_hfclk_start>:
{
    2c00:	b508      	push	{r3, lr}
	__asm__ volatile(
    2c02:	f04f 0320 	mov.w	r3, #32
    2c06:	f3ef 8111 	mrs	r1, BASEPRI
    2c0a:	f383 8812 	msr	BASEPRI_MAX, r3
    2c0e:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    2c12:	4a12      	ldr	r2, [pc, #72]	; (2c5c <generic_hfclk_start+0x5c>)
    2c14:	6813      	ldr	r3, [r2, #0]
    2c16:	f043 0002 	orr.w	r0, r3, #2
    2c1a:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    2c1c:	07da      	lsls	r2, r3, #31
    2c1e:	d408      	bmi.n	2c32 <generic_hfclk_start+0x32>
	__asm__ volatile(
    2c20:	f381 8811 	msr	BASEPRI, r1
    2c24:	f3bf 8f6f 	isb	sy
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    2c28:	2001      	movs	r0, #1
}
    2c2a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    2c2e:	f006 bdc9 	b.w	97c4 <nrfx_clock_start>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2c32:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2c36:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2c3a:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    2c3e:	07d3      	lsls	r3, r2, #31
    2c40:	d5ee      	bpl.n	2c20 <generic_hfclk_start+0x20>
			set_on_state(get_hf_flags());
    2c42:	4807      	ldr	r0, [pc, #28]	; (2c60 <generic_hfclk_start+0x60>)
    2c44:	f006 f929 	bl	8e9a <set_on_state>
    2c48:	f381 8811 	msr	BASEPRI, r1
    2c4c:	f3bf 8f6f 	isb	sy
		clkstarted_handle(CLOCK_DEVICE,
    2c50:	2000      	movs	r0, #0
}
    2c52:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    2c56:	f7ff bfab 	b.w	2bb0 <clkstarted_handle.constprop.0>
    2c5a:	bf00      	nop
    2c5c:	20001e50 	.word	0x20001e50
    2c60:	20001e40 	.word	0x20001e40

00002c64 <api_blocking_start>:
{
    2c64:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    2c66:	2200      	movs	r2, #0
    2c68:	2301      	movs	r3, #1
    2c6a:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    2c6e:	4a09      	ldr	r2, [pc, #36]	; (2c94 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    2c70:	f8cd d000 	str.w	sp, [sp]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    2c74:	466b      	mov	r3, sp
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    2c76:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    2c7a:	f006 f97b 	bl	8f74 <api_start>
	if (err < 0) {
    2c7e:	2800      	cmp	r0, #0
    2c80:	db05      	blt.n	2c8e <api_blocking_start+0x2a>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    2c82:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    2c86:	2300      	movs	r3, #0
    2c88:	4668      	mov	r0, sp
    2c8a:	f003 faef 	bl	626c <z_impl_k_sem_take>
}
    2c8e:	b005      	add	sp, #20
    2c90:	f85d fb04 	ldr.w	pc, [sp], #4
    2c94:	00008fa3 	.word	0x00008fa3

00002c98 <generic_hfclk_stop>:
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2c98:	4b09      	ldr	r3, [pc, #36]	; (2cc0 <generic_hfclk_stop+0x28>)
    2c9a:	f3bf 8f5b 	dmb	ish
    2c9e:	e853 2f00 	ldrex	r2, [r3]
    2ca2:	f022 0102 	bic.w	r1, r2, #2
    2ca6:	e843 1000 	strex	r0, r1, [r3]
    2caa:	2800      	cmp	r0, #0
    2cac:	d1f7      	bne.n	2c9e <generic_hfclk_stop+0x6>
    2cae:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    2cb2:	07d3      	lsls	r3, r2, #31
    2cb4:	d402      	bmi.n	2cbc <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    2cb6:	2001      	movs	r0, #1
    2cb8:	f006 bdc0 	b.w	983c <nrfx_clock_stop>
}
    2cbc:	4770      	bx	lr
    2cbe:	bf00      	nop
    2cc0:	20001e50 	.word	0x20001e50

00002cc4 <z_nrf_clock_control_lf_on>:
{
    2cc4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    2cc8:	4938      	ldr	r1, [pc, #224]	; (2dac <z_nrf_clock_control_lf_on+0xe8>)
    2cca:	f3bf 8f5b 	dmb	ish
    2cce:	4607      	mov	r7, r0
    2cd0:	2201      	movs	r2, #1
    2cd2:	e851 3f00 	ldrex	r3, [r1]
    2cd6:	e841 2000 	strex	r0, r2, [r1]
    2cda:	2800      	cmp	r0, #0
    2cdc:	d1f9      	bne.n	2cd2 <z_nrf_clock_control_lf_on+0xe>
    2cde:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    2ce2:	b933      	cbnz	r3, 2cf2 <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    2ce4:	4932      	ldr	r1, [pc, #200]	; (2db0 <z_nrf_clock_control_lf_on+0xec>)
		err = onoff_request(mgr, &cli);
    2ce6:	4833      	ldr	r0, [pc, #204]	; (2db4 <z_nrf_clock_control_lf_on+0xf0>)
    2ce8:	604b      	str	r3, [r1, #4]
    2cea:	60cb      	str	r3, [r1, #12]
    2cec:	608a      	str	r2, [r1, #8]
    2cee:	f005 ff79 	bl	8be4 <onoff_request>
	switch (start_mode) {
    2cf2:	1e7b      	subs	r3, r7, #1
    2cf4:	2b01      	cmp	r3, #1
    2cf6:	d82b      	bhi.n	2d50 <z_nrf_clock_control_lf_on+0x8c>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    2cf8:	2f01      	cmp	r7, #1
    2cfa:	d107      	bne.n	2d0c <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    2cfc:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2d00:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    2d04:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    2d08:	2b01      	cmp	r3, #1
    2d0a:	d021      	beq.n	2d50 <z_nrf_clock_control_lf_on+0x8c>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2d0c:	f006 fef7 	bl	9afe <k_is_in_isr>
    2d10:	4605      	mov	r5, r0
    2d12:	b9f8      	cbnz	r0, 2d54 <z_nrf_clock_control_lf_on+0x90>
	return !z_sys_post_kernel;
    2d14:	4b28      	ldr	r3, [pc, #160]	; (2db8 <z_nrf_clock_control_lf_on+0xf4>)
    2d16:	781b      	ldrb	r3, [r3, #0]
    2d18:	b1e3      	cbz	r3, 2d54 <z_nrf_clock_control_lf_on+0x90>
    p_reg->INTENCLR = mask;
    2d1a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2d1e:	2202      	movs	r2, #2
    2d20:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    2d24:	4606      	mov	r6, r0
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2d26:	f8df 8094 	ldr.w	r8, [pc, #148]	; 2dbc <z_nrf_clock_control_lf_on+0xf8>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2d2a:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    2d2e:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2d32:	f8d4 2418 	ldr.w	r2, [r4, #1048]	; 0x418
    2d36:	03d2      	lsls	r2, r2, #15
    2d38:	d516      	bpl.n	2d68 <z_nrf_clock_control_lf_on+0xa4>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    2d3a:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    2d3e:	2b01      	cmp	r3, #1
    2d40:	d001      	beq.n	2d46 <z_nrf_clock_control_lf_on+0x82>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    2d42:	2f01      	cmp	r7, #1
    2d44:	d110      	bne.n	2d68 <z_nrf_clock_control_lf_on+0xa4>
	if (isr_mode) {
    2d46:	b35d      	cbz	r5, 2da0 <z_nrf_clock_control_lf_on+0xdc>
    2d48:	f386 8811 	msr	BASEPRI, r6
    2d4c:	f3bf 8f6f 	isb	sy
}
    2d50:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	__asm__ volatile(
    2d54:	f04f 0320 	mov.w	r3, #32
    2d58:	f3ef 8611 	mrs	r6, BASEPRI
    2d5c:	f383 8812 	msr	BASEPRI_MAX, r3
    2d60:	f3bf 8f6f 	isb	sy
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2d64:	2501      	movs	r5, #1
    2d66:	e7de      	b.n	2d26 <z_nrf_clock_control_lf_on+0x62>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    2d68:	b1ad      	cbz	r5, 2d96 <z_nrf_clock_control_lf_on+0xd2>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    2d6a:	4630      	mov	r0, r6
    2d6c:	f7ff f8c4 	bl	1ef8 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    2d70:	f8d4 3518 	ldr.w	r3, [r4, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    2d74:	2b00      	cmp	r3, #0
    2d76:	d1da      	bne.n	2d2e <z_nrf_clock_control_lf_on+0x6a>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2d78:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    2d7c:	2a00      	cmp	r2, #0
    2d7e:	d0d6      	beq.n	2d2e <z_nrf_clock_control_lf_on+0x6a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2d80:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    2d84:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    2d88:	2301      	movs	r3, #1
    2d8a:	f8c4 3518 	str.w	r3, [r4, #1304]	; 0x518
    2d8e:	f8c8 3180 	str.w	r3, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d92:	60a3      	str	r3, [r4, #8]
}
    2d94:	e7cb      	b.n	2d2e <z_nrf_clock_control_lf_on+0x6a>
	return z_impl_k_sleep(timeout);
    2d96:	2100      	movs	r1, #0
    2d98:	2021      	movs	r0, #33	; 0x21
    2d9a:	f003 fd57 	bl	684c <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    2d9e:	e7e7      	b.n	2d70 <z_nrf_clock_control_lf_on+0xac>
    p_reg->INTENSET = mask;
    2da0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2da4:	2202      	movs	r2, #2
    2da6:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    2daa:	e7d1      	b.n	2d50 <z_nrf_clock_control_lf_on+0x8c>
    2dac:	20001dfc 	.word	0x20001dfc
    2db0:	20001dec 	.word	0x20001dec
    2db4:	20001e1c 	.word	0x20001e1c
    2db8:	200026d7 	.word	0x200026d7
    2dbc:	e000e100 	.word	0xe000e100

00002dc0 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    2dc0:	b508      	push	{r3, lr}
    2dc2:	4807      	ldr	r0, [pc, #28]	; (2de0 <uart_console_init+0x20>)
    2dc4:	f006 fe3f 	bl	9a46 <z_device_is_ready>

	ARG_UNUSED(arg);

	if (!device_is_ready(uart_console_dev)) {
    2dc8:	b138      	cbz	r0, 2dda <uart_console_init+0x1a>
	__stdout_hook_install(console_out);
    2dca:	4806      	ldr	r0, [pc, #24]	; (2de4 <uart_console_init+0x24>)
    2dcc:	f7ff fe34 	bl	2a38 <__stdout_hook_install>
	__printk_hook_install(console_out);
    2dd0:	4804      	ldr	r0, [pc, #16]	; (2de4 <uart_console_init+0x24>)
    2dd2:	f7fe faa9 	bl	1328 <__printk_hook_install>
		return -ENODEV;
	}

	uart_console_hook_install();

	return 0;
    2dd6:	2000      	movs	r0, #0
}
    2dd8:	bd08      	pop	{r3, pc}
		return -ENODEV;
    2dda:	f06f 0012 	mvn.w	r0, #18
    2dde:	e7fb      	b.n	2dd8 <uart_console_init+0x18>
    2de0:	00009e64 	.word	0x00009e64
    2de4:	00002de9 	.word	0x00002de9

00002de8 <console_out>:
	if ('\n' == c) {
    2de8:	280a      	cmp	r0, #10
{
    2dea:	b538      	push	{r3, r4, r5, lr}
    2dec:	4d07      	ldr	r5, [pc, #28]	; (2e0c <console_out+0x24>)
    2dee:	4604      	mov	r4, r0
	if ('\n' == c) {
    2df0:	d104      	bne.n	2dfc <console_out+0x14>
					unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    2df2:	68ab      	ldr	r3, [r5, #8]
    2df4:	210d      	movs	r1, #13
    2df6:	685b      	ldr	r3, [r3, #4]
    2df8:	4628      	mov	r0, r5
    2dfa:	4798      	blx	r3
    2dfc:	68ab      	ldr	r3, [r5, #8]
    2dfe:	4803      	ldr	r0, [pc, #12]	; (2e0c <console_out+0x24>)
    2e00:	685b      	ldr	r3, [r3, #4]
    2e02:	b2e1      	uxtb	r1, r4
    2e04:	4798      	blx	r3
}
    2e06:	4620      	mov	r0, r4
    2e08:	bd38      	pop	{r3, r4, r5, pc}
    2e0a:	bf00      	nop
    2e0c:	00009e64 	.word	0x00009e64

00002e10 <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    2e10:	b530      	push	{r4, r5, lr}
	return port->config;
    2e12:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2e14:	7b05      	ldrb	r5, [r0, #12]
    2e16:	f001 041f 	and.w	r4, r1, #31
	nrfx_err_t err;
	uint8_t ch;

	if (mode == GPIO_INT_MODE_DISABLED) {
    2e1a:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
{
    2e1e:	b085      	sub	sp, #20
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2e20:	ea44 1445 	orr.w	r4, r4, r5, lsl #5
	if (mode == GPIO_INT_MODE_DISABLED) {
    2e24:	d105      	bne.n	2e32 <gpio_nrfx_pin_interrupt_configure+0x22>
		nrfx_gpiote_trigger_disable(abs_pin);
    2e26:	4620      	mov	r0, r4
    2e28:	f002 f9ee 	bl	5208 <nrfx_gpiote_trigger_disable>

		return 0;
    2e2c:	2000      	movs	r0, #0
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
}
    2e2e:	b005      	add	sp, #20
    2e30:	bd30      	pop	{r4, r5, pc}
	nrfx_gpiote_trigger_config_t trigger_config = {
    2e32:	2500      	movs	r5, #0
	if (mode == GPIO_INT_MODE_LEVEL) {
    2e34:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    2e38:	e9cd 5502 	strd	r5, r5, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    2e3c:	d114      	bne.n	2e68 <gpio_nrfx_pin_interrupt_configure+0x58>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    2e3e:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
	nrfx_gpiote_trigger_config_t trigger_config = {
    2e42:	bf0c      	ite	eq
    2e44:	2304      	moveq	r3, #4
    2e46:	2305      	movne	r3, #5
    2e48:	f88d 3008 	strb.w	r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2e4c:	2300      	movs	r3, #0
    2e4e:	4619      	mov	r1, r3
    2e50:	aa02      	add	r2, sp, #8
    2e52:	4620      	mov	r0, r4
    2e54:	f002 f816 	bl	4e84 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    2e58:	4b1f      	ldr	r3, [pc, #124]	; (2ed8 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    2e5a:	4298      	cmp	r0, r3
    2e5c:	d139      	bne.n	2ed2 <gpio_nrfx_pin_interrupt_configure+0xc2>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    2e5e:	2101      	movs	r1, #1
    2e60:	4620      	mov	r0, r4
    2e62:	f002 f989 	bl	5178 <nrfx_gpiote_trigger_enable>
	return 0;
    2e66:	e7e1      	b.n	2e2c <gpio_nrfx_pin_interrupt_configure+0x1c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    2e68:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    2e6c:	d026      	beq.n	2ebc <gpio_nrfx_pin_interrupt_configure+0xac>
    2e6e:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    2e72:	bf14      	ite	ne
    2e74:	2301      	movne	r3, #1
    2e76:	2302      	moveq	r3, #2
	nrfx_gpiote_trigger_config_t trigger_config = {
    2e78:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    2e7c:	6883      	ldr	r3, [r0, #8]
    2e7e:	40cb      	lsrs	r3, r1
    2e80:	07d9      	lsls	r1, r3, #31
    2e82:	d4e3      	bmi.n	2e4c <gpio_nrfx_pin_interrupt_configure+0x3c>
    2e84:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    2e88:	d1e0      	bne.n	2e4c <gpio_nrfx_pin_interrupt_configure+0x3c>
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    2e8a:	0962      	lsrs	r2, r4, #5
        case 1: return NRF_P1;
    2e8c:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    2e8e:	f004 031f 	and.w	r3, r4, #31
        case 1: return NRF_P1;
    2e92:	4a12      	ldr	r2, [pc, #72]	; (2edc <gpio_nrfx_pin_interrupt_configure+0xcc>)
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2e94:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
        case 1: return NRF_P1;
    2e98:	bf18      	it	ne
    2e9a:	f04f 42a0 	movne.w	r2, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2e9e:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    2ea2:	07db      	lsls	r3, r3, #31
    2ea4:	d4d2      	bmi.n	2e4c <gpio_nrfx_pin_interrupt_configure+0x3c>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2ea6:	f10d 0507 	add.w	r5, sp, #7
    2eaa:	4629      	mov	r1, r5
    2eac:	4620      	mov	r0, r4
    2eae:	f002 f90f 	bl	50d0 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    2eb2:	4b0b      	ldr	r3, [pc, #44]	; (2ee0 <gpio_nrfx_pin_interrupt_configure+0xd0>)
    2eb4:	4298      	cmp	r0, r3
    2eb6:	d003      	beq.n	2ec0 <gpio_nrfx_pin_interrupt_configure+0xb0>
		trigger_config.p_in_channel = &ch;
    2eb8:	9503      	str	r5, [sp, #12]
    2eba:	e7c7      	b.n	2e4c <gpio_nrfx_pin_interrupt_configure+0x3c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    2ebc:	2303      	movs	r3, #3
    2ebe:	e7db      	b.n	2e78 <gpio_nrfx_pin_interrupt_configure+0x68>
			err = nrfx_gpiote_channel_alloc(&ch);
    2ec0:	4628      	mov	r0, r5
    2ec2:	f002 f953 	bl	516c <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    2ec6:	4b04      	ldr	r3, [pc, #16]	; (2ed8 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    2ec8:	4298      	cmp	r0, r3
    2eca:	d0f5      	beq.n	2eb8 <gpio_nrfx_pin_interrupt_configure+0xa8>
				return -ENOMEM;
    2ecc:	f06f 000b 	mvn.w	r0, #11
    2ed0:	e7ad      	b.n	2e2e <gpio_nrfx_pin_interrupt_configure+0x1e>
		return -EINVAL;
    2ed2:	f06f 0015 	mvn.w	r0, #21
    2ed6:	e7aa      	b.n	2e2e <gpio_nrfx_pin_interrupt_configure+0x1e>
    2ed8:	0bad0000 	.word	0x0bad0000
    2edc:	50000300 	.word	0x50000300
    2ee0:	0bad0004 	.word	0x0bad0004

00002ee4 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    2ee4:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    2ee6:	f002 f931 	bl	514c <nrfx_gpiote_is_init>
    2eea:	4604      	mov	r4, r0
    2eec:	b968      	cbnz	r0, 2f0a <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    2eee:	f002 f905 	bl	50fc <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    2ef2:	4b08      	ldr	r3, [pc, #32]	; (2f14 <gpio_nrfx_init+0x30>)
    2ef4:	4298      	cmp	r0, r3
    2ef6:	d10a      	bne.n	2f0e <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    2ef8:	4807      	ldr	r0, [pc, #28]	; (2f18 <gpio_nrfx_init+0x34>)
    2efa:	4621      	mov	r1, r4
    2efc:	f002 f8e2 	bl	50c4 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2f00:	4622      	mov	r2, r4
    2f02:	2105      	movs	r1, #5
    2f04:	2006      	movs	r0, #6
    2f06:	f7ff f897 	bl	2038 <z_arm_irq_priority_set>
		return 0;
    2f0a:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    2f0c:	bd10      	pop	{r4, pc}
		return -EIO;
    2f0e:	f06f 0004 	mvn.w	r0, #4
    2f12:	e7fb      	b.n	2f0c <gpio_nrfx_init+0x28>
    2f14:	0bad0000 	.word	0x0bad0000
    2f18:	00002f1d 	.word	0x00002f1d

00002f1c <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2f1c:	0942      	lsrs	r2, r0, #5
{
    2f1e:	b570      	push	{r4, r5, r6, lr}
    2f20:	4603      	mov	r3, r0
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2f22:	d002      	beq.n	2f2a <nrfx_gpio_handler+0xe>
    2f24:	2a01      	cmp	r2, #1
    2f26:	d017      	beq.n	2f58 <nrfx_gpio_handler+0x3c>
}
    2f28:	bd70      	pop	{r4, r5, r6, pc}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2f2a:	4e0d      	ldr	r6, [pc, #52]	; (2f60 <nrfx_gpio_handler+0x44>)
	gpio_fire_callbacks(list, port, BIT(pin));
    2f2c:	6932      	ldr	r2, [r6, #16]
    2f2e:	6851      	ldr	r1, [r2, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2f30:	2900      	cmp	r1, #0
    2f32:	d0f9      	beq.n	2f28 <nrfx_gpio_handler+0xc>
    *p_pin = pin_number & 0x1F;
    2f34:	f003 031f 	and.w	r3, r3, #31
    2f38:	2501      	movs	r5, #1
    2f3a:	680c      	ldr	r4, [r1, #0]
    2f3c:	409d      	lsls	r5, r3
    2f3e:	2900      	cmp	r1, #0
    2f40:	d0f2      	beq.n	2f28 <nrfx_gpio_handler+0xc>
		if (cb->pin_mask & pins) {
    2f42:	688a      	ldr	r2, [r1, #8]
    2f44:	402a      	ands	r2, r5
    2f46:	d002      	beq.n	2f4e <nrfx_gpio_handler+0x32>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    2f48:	684b      	ldr	r3, [r1, #4]
    2f4a:	4630      	mov	r0, r6
    2f4c:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2f4e:	b12c      	cbz	r4, 2f5c <nrfx_gpio_handler+0x40>
    2f50:	6823      	ldr	r3, [r4, #0]
    2f52:	4621      	mov	r1, r4
    2f54:	461c      	mov	r4, r3
    2f56:	e7f2      	b.n	2f3e <nrfx_gpio_handler+0x22>
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2f58:	4e02      	ldr	r6, [pc, #8]	; (2f64 <nrfx_gpio_handler+0x48>)
    2f5a:	e7e7      	b.n	2f2c <nrfx_gpio_handler+0x10>
    2f5c:	4623      	mov	r3, r4
    2f5e:	e7f8      	b.n	2f52 <nrfx_gpio_handler+0x36>
    2f60:	00009e34 	.word	0x00009e34
    2f64:	00009e1c 	.word	0x00009e1c

00002f68 <gpio_nrfx_pin_configure>:
{
    2f68:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	return port->config;
    2f6c:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2f6e:	7b3b      	ldrb	r3, [r7, #12]
    2f70:	f001 051f 	and.w	r5, r1, #31
    2f74:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
{
    2f78:	460e      	mov	r6, r1
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2f7a:	4628      	mov	r0, r5
    2f7c:	f10d 0103 	add.w	r1, sp, #3
{
    2f80:	4614      	mov	r4, r2
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2f82:	f002 f8a5 	bl	50d0 <nrfx_gpiote_channel_get>
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    2f86:	f414 3f40 	tst.w	r4, #196608	; 0x30000
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2f8a:	4680      	mov	r8, r0
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    2f8c:	d10b      	bne.n	2fa6 <gpio_nrfx_pin_configure+0x3e>
		(void)nrfx_gpiote_pin_uninit(abs_pin);
    2f8e:	4628      	mov	r0, r5
    2f90:	f002 f962 	bl	5258 <nrfx_gpiote_pin_uninit>
		if (free_ch) {
    2f94:	4b3d      	ldr	r3, [pc, #244]	; (308c <gpio_nrfx_pin_configure+0x124>)
    2f96:	4598      	cmp	r8, r3
    2f98:	d103      	bne.n	2fa2 <gpio_nrfx_pin_configure+0x3a>
			err = nrfx_gpiote_channel_free(ch);
    2f9a:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2f9e:	f002 f8df 	bl	5160 <nrfx_gpiote_channel_free>
		return 0;
    2fa2:	2000      	movs	r0, #0
    2fa4:	e00c      	b.n	2fc0 <gpio_nrfx_pin_configure+0x58>
	nrfx_gpiote_trigger_config_t trigger_config = {
    2fa6:	2300      	movs	r3, #0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2fa8:	4619      	mov	r1, r3
    2faa:	aa02      	add	r2, sp, #8
    2fac:	4628      	mov	r0, r5
	nrfx_gpiote_trigger_config_t trigger_config = {
    2fae:	e9cd 3302 	strd	r3, r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2fb2:	f001 ff67 	bl	4e84 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    2fb6:	4b35      	ldr	r3, [pc, #212]	; (308c <gpio_nrfx_pin_configure+0x124>)
    2fb8:	4298      	cmp	r0, r3
    2fba:	d004      	beq.n	2fc6 <gpio_nrfx_pin_configure+0x5e>
		return NRF_GPIO_PIN_PULLUP;
    2fbc:	f06f 0015 	mvn.w	r0, #21
}
    2fc0:	b004      	add	sp, #16
    2fc2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (free_ch) {
    2fc6:	4580      	cmp	r8, r0
    2fc8:	d103      	bne.n	2fd2 <gpio_nrfx_pin_configure+0x6a>
		err = nrfx_gpiote_channel_free(ch);
    2fca:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2fce:	f002 f8c7 	bl	5160 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    2fd2:	03a3      	lsls	r3, r4, #14
    2fd4:	d54b      	bpl.n	306e <gpio_nrfx_pin_configure+0x106>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    2fd6:	f240 3306 	movw	r3, #774	; 0x306
    2fda:	4023      	ands	r3, r4
    2fdc:	f5b3 7f83 	cmp.w	r3, #262	; 0x106
    2fe0:	d019      	beq.n	3016 <gpio_nrfx_pin_configure+0xae>
    2fe2:	d80c      	bhi.n	2ffe <gpio_nrfx_pin_configure+0x96>
    2fe4:	2b06      	cmp	r3, #6
    2fe6:	d017      	beq.n	3018 <gpio_nrfx_pin_configure+0xb0>
    2fe8:	d804      	bhi.n	2ff4 <gpio_nrfx_pin_configure+0x8c>
    2fea:	b1ab      	cbz	r3, 3018 <gpio_nrfx_pin_configure+0xb0>
    2fec:	2b02      	cmp	r3, #2
    2fee:	d1e5      	bne.n	2fbc <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0S1;
    2ff0:	2304      	movs	r3, #4
    2ff2:	e011      	b.n	3018 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    2ff4:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    2ff8:	d1e0      	bne.n	2fbc <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_H0S1;
    2ffa:	2301      	movs	r3, #1
    2ffc:	e00c      	b.n	3018 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    2ffe:	f240 2202 	movw	r2, #514	; 0x202
    3002:	4293      	cmp	r3, r2
    3004:	d027      	beq.n	3056 <gpio_nrfx_pin_configure+0xee>
    3006:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
    300a:	d026      	beq.n	305a <gpio_nrfx_pin_configure+0xf2>
    300c:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    3010:	d1d4      	bne.n	2fbc <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_S0H1;
    3012:	2302      	movs	r3, #2
    3014:	e000      	b.n	3018 <gpio_nrfx_pin_configure+0xb0>
		*drive = NRF_GPIO_PIN_H0D1;
    3016:	2307      	movs	r3, #7
		nrfx_gpiote_output_config_t output_config = {
    3018:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    301c:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    3020:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    3024:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    3026:	f88d 3005 	strb.w	r3, [sp, #5]
	} else if (flags & GPIO_PULL_DOWN) {
    302a:	bf54      	ite	pl
    302c:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    3030:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    3032:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    3034:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    3038:	d511      	bpl.n	305e <gpio_nrfx_pin_configure+0xf6>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    303a:	687a      	ldr	r2, [r7, #4]
    303c:	2301      	movs	r3, #1
    303e:	40b3      	lsls	r3, r6
    p_reg->OUTSET = set_mask;
    3040:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    3044:	2200      	movs	r2, #0
    3046:	a901      	add	r1, sp, #4
    3048:	4628      	mov	r0, r5
    304a:	f001 ffc9 	bl	4fe0 <nrfx_gpiote_output_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    304e:	4b0f      	ldr	r3, [pc, #60]	; (308c <gpio_nrfx_pin_configure+0x124>)
    3050:	4298      	cmp	r0, r3
    3052:	d0a6      	beq.n	2fa2 <gpio_nrfx_pin_configure+0x3a>
    3054:	e7b2      	b.n	2fbc <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0H1;
    3056:	2305      	movs	r3, #5
    3058:	e7de      	b.n	3018 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    305a:	2303      	movs	r3, #3
    305c:	e7dc      	b.n	3018 <gpio_nrfx_pin_configure+0xb0>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    305e:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    3060:	bf41      	itttt	mi
    3062:	2301      	movmi	r3, #1
    3064:	687a      	ldrmi	r2, [r7, #4]
    3066:	40b3      	lslmi	r3, r6
    p_reg->OUTCLR = clr_mask;
    3068:	f8c2 350c 	strmi.w	r3, [r2, #1292]	; 0x50c
}
    306c:	e7ea      	b.n	3044 <gpio_nrfx_pin_configure+0xdc>
	if (flags & GPIO_PULL_UP) {
    306e:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    3070:	f04f 0300 	mov.w	r3, #0
	} else if (flags & GPIO_PULL_DOWN) {
    3074:	bf54      	ite	pl
    3076:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    307a:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    307c:	461a      	mov	r2, r3
    307e:	a901      	add	r1, sp, #4
    3080:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    3082:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    3086:	f001 fefd 	bl	4e84 <nrfx_gpiote_input_configure>
    308a:	e7e0      	b.n	304e <gpio_nrfx_pin_configure+0xe6>
    308c:	0bad0000 	.word	0x0bad0000

00003090 <spi_nrfx_init>:
	return ret;
}
#endif /* CONFIG_PM_DEVICE */

static int spi_nrfx_init(const struct device *dev)
{
    3090:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	const struct spi_nrfx_config *dev_config = dev->config;
    3094:	6844      	ldr	r4, [r0, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    3096:	6905      	ldr	r5, [r0, #16]
	int err;

#ifdef CONFIG_PINCTRL
	err = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    3098:	6a26      	ldr	r6, [r4, #32]
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    309a:	aa01      	add	r2, sp, #4
    309c:	2100      	movs	r1, #0
    309e:	4630      	mov	r0, r6
    30a0:	f006 fab4 	bl	960c <pinctrl_lookup_state>
	if (ret < 0) {
    30a4:	2800      	cmp	r0, #0
    30a6:	db23      	blt.n	30f0 <spi_nrfx_init+0x60>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    30a8:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    30aa:	6832      	ldr	r2, [r6, #0]
    30ac:	7919      	ldrb	r1, [r3, #4]
    30ae:	6818      	ldr	r0, [r3, #0]
    30b0:	f001 fade 	bl	4670 <pinctrl_configure_pins>
	if (err < 0) {
    30b4:	2800      	cmp	r0, #0
    30b6:	db1b      	blt.n	30f0 <spi_nrfx_init+0x60>
		return err;
	}
#endif

	dev_config->irq_connect();
    30b8:	69e3      	ldr	r3, [r4, #28]
    30ba:	4798      	blx	r3
static inline int spi_context_cs_configure_all(struct spi_context *ctx)
{
	int ret;
	const struct gpio_dt_spec *cs_gpio;

	for (cs_gpio = ctx->cs_gpios; cs_gpio < &ctx->cs_gpios[ctx->num_cs_gpios]; cs_gpio++) {
    30bc:	68ac      	ldr	r4, [r5, #8]

	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
		data->invert |= (gpio_port_pins_t)BIT(pin);
    30be:	2601      	movs	r6, #1
    30c0:	e9d5 3202 	ldrd	r3, r2, [r5, #8]
    30c4:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
    30c8:	429c      	cmp	r4, r3
    30ca:	d304      	bcc.n	30d6 <spi_nrfx_init+0x46>
	err = spi_context_cs_configure_all(&dev_data->ctx);
	if (err < 0) {
		return err;
	}

	spi_context_unlock_unconditionally(&dev_data->ctx);
    30cc:	4628      	mov	r0, r5
    30ce:	f006 f80e 	bl	90ee <spi_context_unlock_unconditionally>
		if (ret < 0) {
			return ret;
		}
	}

	return 0;
    30d2:	2000      	movs	r0, #0

	return 0;
    30d4:	e00c      	b.n	30f0 <spi_nrfx_init+0x60>
		if (!device_is_ready(cs_gpio->port)) {
    30d6:	6820      	ldr	r0, [r4, #0]
    30d8:	f006 fcb5 	bl	9a46 <z_device_is_ready>
    30dc:	b958      	cbnz	r0, 30f6 <spi_nrfx_init+0x66>
			LOG_ERR("CS GPIO port %s pin %d is not ready",
    30de:	6822      	ldr	r2, [r4, #0]
    30e0:	4816      	ldr	r0, [pc, #88]	; (313c <spi_nrfx_init+0xac>)
    30e2:	7923      	ldrb	r3, [r4, #4]
    30e4:	6812      	ldr	r2, [r2, #0]
    30e6:	2145      	movs	r1, #69	; 0x45
    30e8:	f005 fdf3 	bl	8cd2 <z_log_minimal_printk>
			return -ENODEV;
    30ec:	f06f 0012 	mvn.w	r0, #18
}
    30f0:	b002      	add	sp, #8
    30f2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 * @return a value from gpio_pin_configure()
 */
static inline int gpio_pin_configure_dt(const struct gpio_dt_spec *spec,
					gpio_flags_t extra_flags)
{
	return gpio_pin_configure(spec->port,
    30f6:	6820      	ldr	r0, [r4, #0]
				  spec->pin,
    30f8:	7921      	ldrb	r1, [r4, #4]
				  spec->dt_flags | extra_flags);
    30fa:	88e3      	ldrh	r3, [r4, #6]
	struct gpio_driver_data *data =
    30fc:	f8d0 c010 	ldr.w	ip, [r0, #16]
	const struct gpio_driver_api *api =
    3100:	f8d0 8008 	ldr.w	r8, [r0, #8]
		data->invert |= (gpio_port_pins_t)BIT(pin);
    3104:	f8dc 7000 	ldr.w	r7, [ip]
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    3108:	07da      	lsls	r2, r3, #31
	return gpio_pin_configure(spec->port,
    310a:	bf54      	ite	pl
    310c:	f443 13b0 	orrpl.w	r3, r3, #1441792	; 0x160000
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
    3110:	f483 13d0 	eormi.w	r3, r3, #1703936	; 0x1a0000
	flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
    3114:	f423 1280 	bic.w	r2, r3, #1048576	; 0x100000
		data->invert |= (gpio_port_pins_t)BIT(pin);
    3118:	fa06 fe01 	lsl.w	lr, r6, r1
	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    311c:	07db      	lsls	r3, r3, #31
		data->invert |= (gpio_port_pins_t)BIT(pin);
    311e:	bf4c      	ite	mi
    3120:	ea4e 0707 	orrmi.w	r7, lr, r7
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    3124:	ea27 070e 	bicpl.w	r7, r7, lr
    3128:	f8cc 7000 	str.w	r7, [ip]
	return api->pin_configure(port, pin, flags);
    312c:	f8d8 3000 	ldr.w	r3, [r8]
    3130:	4798      	blx	r3
		if (ret < 0) {
    3132:	2800      	cmp	r0, #0
    3134:	dbdc      	blt.n	30f0 <spi_nrfx_init+0x60>
	for (cs_gpio = ctx->cs_gpios; cs_gpio < &ctx->cs_gpios[ctx->num_cs_gpios]; cs_gpio++) {
    3136:	3408      	adds	r4, #8
    3138:	e7c2      	b.n	30c0 <spi_nrfx_init+0x30>
    313a:	bf00      	nop
    313c:	0000b076 	.word	0x0000b076

00003140 <transfer_next_chunk>:
{
    3140:	b530      	push	{r4, r5, lr}
    3142:	4603      	mov	r3, r0
    3144:	b085      	sub	sp, #20
	struct spi_nrfx_data *dev_data = dev->data;
    3146:	691d      	ldr	r5, [r3, #16]
	const struct spi_nrfx_config *dev_config = dev->config;
    3148:	6840      	ldr	r0, [r0, #4]
 * directions have a continuous buffer, i.e. the maximum SPI transfer that
 * can be done with DMA that handles only non-scattered buffers.
 */
static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
{
	if (!ctx->tx_len) {
    314a:	6caa      	ldr	r2, [r5, #72]	; 0x48
		return ctx->rx_len;
    314c:	6d2b      	ldr	r3, [r5, #80]	; 0x50
	if (!ctx->tx_len) {
    314e:	bb2a      	cbnz	r2, 319c <transfer_next_chunk+0x5c>
	if (chunk_len > 0) {
    3150:	b38b      	cbz	r3, 31b6 <transfer_next_chunk+0x76>
		xfer.p_tx_buffer = ctx->tx_buf;
    3152:	6c69      	ldr	r1, [r5, #68]	; 0x44
		dev_data->chunk_len = chunk_len;
    3154:	65ab      	str	r3, [r5, #88]	; 0x58
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    3156:	4614      	mov	r4, r2
		xfer.p_tx_buffer = ctx->tx_buf;
    3158:	461a      	mov	r2, r3
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    315a:	e9cd 1400 	strd	r1, r4, [sp]
		xfer.p_rx_buffer = ctx->rx_buf;
    315e:	6ce9      	ldr	r1, [r5, #76]	; 0x4c
    3160:	9102      	str	r1, [sp, #8]
	return !!(ctx->rx_buf && ctx->rx_len);
    3162:	b331      	cbz	r1, 31b2 <transfer_next_chunk+0x72>
    3164:	2b00      	cmp	r3, #0
    3166:	bf18      	it	ne
    3168:	4613      	movne	r3, r2
		result = nrfx_spi_xfer(&dev_config->spi, &xfer, 0);
    316a:	2200      	movs	r2, #0
    316c:	4669      	mov	r1, sp
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    316e:	9303      	str	r3, [sp, #12]
		result = nrfx_spi_xfer(&dev_config->spi, &xfer, 0);
    3170:	f002 faa8 	bl	56c4 <nrfx_spi_xfer>
		if (result == NRFX_SUCCESS) {
    3174:	4b11      	ldr	r3, [pc, #68]	; (31bc <transfer_next_chunk+0x7c>)
    3176:	4298      	cmp	r0, r3
    3178:	d00e      	beq.n	3198 <transfer_next_chunk+0x58>
		error = -EIO;
    317a:	f06f 0404 	mvn.w	r4, #4
	_spi_context_cs_control(ctx, on, false);
    317e:	2200      	movs	r2, #0
    3180:	4611      	mov	r1, r2
    3182:	4628      	mov	r0, r5
    3184:	f005 ff91 	bl	90aa <_spi_context_cs_control>
	ctx->sync_status = status;
    3188:	632c      	str	r4, [r5, #48]	; 0x30
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    318a:	f105 0020 	add.w	r0, r5, #32
    318e:	f003 f84d 	bl	622c <z_impl_k_sem_give>
	dev_data->busy = false;
    3192:	2300      	movs	r3, #0
    3194:	f885 305c 	strb.w	r3, [r5, #92]	; 0x5c
}
    3198:	b005      	add	sp, #20
    319a:	bd30      	pop	{r4, r5, pc}
	} else if (!ctx->rx_len) {
    319c:	6c69      	ldr	r1, [r5, #68]	; 0x44
    319e:	b113      	cbz	r3, 31a6 <transfer_next_chunk+0x66>
		return ctx->tx_len;
	}

	return MIN(ctx->tx_len, ctx->rx_len);
    31a0:	429a      	cmp	r2, r3
    31a2:	bf28      	it	cs
    31a4:	461a      	movcs	r2, r3
		return ctx->tx_len;
    31a6:	2900      	cmp	r1, #0
		dev_data->chunk_len = chunk_len;
    31a8:	65aa      	str	r2, [r5, #88]	; 0x58
    31aa:	bf14      	ite	ne
    31ac:	4614      	movne	r4, r2
    31ae:	2400      	moveq	r4, #0
    31b0:	e7d3      	b.n	315a <transfer_next_chunk+0x1a>
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    31b2:	460b      	mov	r3, r1
    31b4:	e7d9      	b.n	316a <transfer_next_chunk+0x2a>
	int error = 0;
    31b6:	461c      	mov	r4, r3
    31b8:	e7e1      	b.n	317e <transfer_next_chunk+0x3e>
    31ba:	bf00      	nop
    31bc:	0bad0000 	.word	0x0bad0000

000031c0 <event_handler>:
{
    31c0:	b510      	push	{r4, lr}
	if (p_event->type == NRFX_SPI_EVENT_DONE) {
    31c2:	7803      	ldrb	r3, [r0, #0]
{
    31c4:	460c      	mov	r4, r1
	if (p_event->type == NRFX_SPI_EVENT_DONE) {
    31c6:	2b00      	cmp	r3, #0
    31c8:	d147      	bne.n	325a <event_handler+0x9a>
	if (!ctx->tx_len) {
    31ca:	6c8b      	ldr	r3, [r1, #72]	; 0x48
		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
    31cc:	6d8a      	ldr	r2, [r1, #88]	; 0x58
    31ce:	b12b      	cbz	r3, 31dc <event_handler+0x1c>
	if (len > ctx->tx_len) {
    31d0:	429a      	cmp	r2, r3
    31d2:	d911      	bls.n	31f8 <event_handler+0x38>
		LOG_ERR("Update exceeds current buffer");
    31d4:	4821      	ldr	r0, [pc, #132]	; (325c <event_handler+0x9c>)
    31d6:	2145      	movs	r1, #69	; 0x45
    31d8:	f005 fd7b 	bl	8cd2 <z_log_minimal_printk>
	if (!ctx->rx_len) {
    31dc:	6d23      	ldr	r3, [r4, #80]	; 0x50
		spi_context_update_rx(&dev_data->ctx, 1, dev_data->chunk_len);
    31de:	6da2      	ldr	r2, [r4, #88]	; 0x58
    31e0:	b12b      	cbz	r3, 31ee <event_handler+0x2e>
	if (len > ctx->rx_len) {
    31e2:	429a      	cmp	r2, r3
    31e4:	d920      	bls.n	3228 <event_handler+0x68>
		LOG_ERR("Update exceeds current buffer");
    31e6:	481d      	ldr	r0, [pc, #116]	; (325c <event_handler+0x9c>)
    31e8:	2145      	movs	r1, #69	; 0x45
    31ea:	f005 fd72 	bl	8cd2 <z_log_minimal_printk>
		transfer_next_chunk(dev_data->dev);
    31ee:	6d60      	ldr	r0, [r4, #84]	; 0x54
}
    31f0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		transfer_next_chunk(dev_data->dev);
    31f4:	f7ff bfa4 	b.w	3140 <transfer_next_chunk>
	ctx->tx_len -= len;
    31f8:	1a9b      	subs	r3, r3, r2
    31fa:	648b      	str	r3, [r1, #72]	; 0x48
	if (!ctx->tx_len) {
    31fc:	b973      	cbnz	r3, 321c <event_handler+0x5c>
		++ctx->current_tx;
    31fe:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    3200:	3308      	adds	r3, #8
    3202:	634b      	str	r3, [r1, #52]	; 0x34
		--ctx->tx_count;
    3204:	6b8b      	ldr	r3, [r1, #56]	; 0x38
    3206:	3b01      	subs	r3, #1
    3208:	638b      	str	r3, [r1, #56]	; 0x38
			spi_context_get_next_buf(&ctx->current_tx,
    320a:	f101 0248 	add.w	r2, r1, #72	; 0x48
    320e:	f104 0034 	add.w	r0, r4, #52	; 0x34
    3212:	3138      	adds	r1, #56	; 0x38
    3214:	f005 ff22 	bl	905c <spi_context_get_next_buf.constprop.0>
		ctx->tx_buf = (const uint8_t *)
    3218:	6460      	str	r0, [r4, #68]	; 0x44
    321a:	e7df      	b.n	31dc <event_handler+0x1c>
	} else if (ctx->tx_buf) {
    321c:	6c4b      	ldr	r3, [r1, #68]	; 0x44
    321e:	2b00      	cmp	r3, #0
    3220:	d0dc      	beq.n	31dc <event_handler+0x1c>
		ctx->tx_buf += dfs * len;
    3222:	4413      	add	r3, r2
    3224:	644b      	str	r3, [r1, #68]	; 0x44
    3226:	e7d9      	b.n	31dc <event_handler+0x1c>
	ctx->rx_len -= len;
    3228:	1a9b      	subs	r3, r3, r2
    322a:	6523      	str	r3, [r4, #80]	; 0x50
	if (!ctx->rx_len) {
    322c:	b97b      	cbnz	r3, 324e <event_handler+0x8e>
		++ctx->current_rx;
    322e:	6be3      	ldr	r3, [r4, #60]	; 0x3c
    3230:	3308      	adds	r3, #8
    3232:	63e3      	str	r3, [r4, #60]	; 0x3c
		--ctx->rx_count;
    3234:	6c23      	ldr	r3, [r4, #64]	; 0x40
    3236:	3b01      	subs	r3, #1
    3238:	6423      	str	r3, [r4, #64]	; 0x40
			spi_context_get_next_buf(&ctx->current_rx,
    323a:	f104 0250 	add.w	r2, r4, #80	; 0x50
    323e:	f104 0140 	add.w	r1, r4, #64	; 0x40
    3242:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    3246:	f005 ff09 	bl	905c <spi_context_get_next_buf.constprop.0>
		ctx->rx_buf = (uint8_t *)
    324a:	64e0      	str	r0, [r4, #76]	; 0x4c
    324c:	e7cf      	b.n	31ee <event_handler+0x2e>
	} else if (ctx->rx_buf) {
    324e:	6ce3      	ldr	r3, [r4, #76]	; 0x4c
    3250:	2b00      	cmp	r3, #0
    3252:	d0cc      	beq.n	31ee <event_handler+0x2e>
		ctx->rx_buf += dfs * len;
    3254:	4413      	add	r3, r2
    3256:	64e3      	str	r3, [r4, #76]	; 0x4c
    3258:	e7c9      	b.n	31ee <event_handler+0x2e>
}
    325a:	bd10      	pop	{r4, pc}
    325c:	0000b09f 	.word	0x0000b09f

00003260 <spi_nrfx_transceive>:
{
    3260:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3264:	4699      	mov	r9, r3
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    3266:	888b      	ldrh	r3, [r1, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    3268:	6904      	ldr	r4, [r0, #16]
    326a:	049f      	lsls	r7, r3, #18
{
    326c:	b089      	sub	sp, #36	; 0x24
    326e:	4680      	mov	r8, r0
    3270:	460e      	mov	r6, r1
    3272:	4692      	mov	sl, r2
    3274:	d42d      	bmi.n	32d2 <spi_nrfx_transceive+0x72>
	return z_impl_k_sem_take(sem, timeout);
    3276:	f04f 32ff 	mov.w	r2, #4294967295
    327a:	f04f 33ff 	mov.w	r3, #4294967295
    327e:	f104 0010 	add.w	r0, r4, #16
    3282:	f002 fff3 	bl	626c <z_impl_k_sem_take>
	ctx->owner = spi_cfg;
    3286:	6066      	str	r6, [r4, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    3288:	f8d8 b010 	ldr.w	fp, [r8, #16]
	const struct spi_nrfx_config *dev_config = dev->config;
    328c:	f8d8 3004 	ldr.w	r3, [r8, #4]
    3290:	9300      	str	r3, [sp, #0]
	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
    3292:	f89b 305d 	ldrb.w	r3, [fp, #93]	; 0x5d
    3296:	9301      	str	r3, [sp, #4]
    3298:	b123      	cbz	r3, 32a4 <spi_nrfx_transceive+0x44>
    329a:	f8db 3000 	ldr.w	r3, [fp]
    329e:	429e      	cmp	r6, r3
    32a0:	f000 80a1 	beq.w	33e6 <spi_nrfx_transceive+0x186>
	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
    32a4:	88b7      	ldrh	r7, [r6, #4]
    32a6:	053d      	lsls	r5, r7, #20
    32a8:	d51a      	bpl.n	32e0 <spi_nrfx_transceive+0x80>
		LOG_ERR("Half-duplex not supported");
    32aa:	4882      	ldr	r0, [pc, #520]	; (34b4 <spi_nrfx_transceive+0x254>)
    32ac:	2145      	movs	r1, #69	; 0x45
    32ae:	f005 fd10 	bl	8cd2 <z_log_minimal_printk>
		return -ENOTSUP;
    32b2:	f06f 0585 	mvn.w	r5, #133	; 0x85
	if (!(ctx->config->operation & SPI_LOCK_ON)) {
    32b6:	6823      	ldr	r3, [r4, #0]
    32b8:	889b      	ldrh	r3, [r3, #4]
    32ba:	f413 5300 	ands.w	r3, r3, #8192	; 0x2000
    32be:	d104      	bne.n	32ca <spi_nrfx_transceive+0x6a>
		ctx->owner = NULL;
    32c0:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    32c2:	f104 0010 	add.w	r0, r4, #16
    32c6:	f002 ffb1 	bl	622c <z_impl_k_sem_give>
}
    32ca:	4628      	mov	r0, r5
    32cc:	b009      	add	sp, #36	; 0x24
    32ce:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    32d2:	69a3      	ldr	r3, [r4, #24]
    32d4:	2b00      	cmp	r3, #0
    32d6:	d1ce      	bne.n	3276 <spi_nrfx_transceive+0x16>
		(k_sem_count_get(&ctx->lock) == 0) &&
    32d8:	6863      	ldr	r3, [r4, #4]
    32da:	4299      	cmp	r1, r3
    32dc:	d1cb      	bne.n	3276 <spi_nrfx_transceive+0x16>
    32de:	e7d3      	b.n	3288 <spi_nrfx_transceive+0x28>
	if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
    32e0:	07f8      	lsls	r0, r7, #31
    32e2:	d508      	bpl.n	32f6 <spi_nrfx_transceive+0x96>
		LOG_ERR("Slave mode is not supported on %s", dev->name);
    32e4:	f8d8 2000 	ldr.w	r2, [r8]
    32e8:	4873      	ldr	r0, [pc, #460]	; (34b8 <spi_nrfx_transceive+0x258>)
    32ea:	2145      	movs	r1, #69	; 0x45
    32ec:	f005 fcf1 	bl	8cd2 <z_log_minimal_printk>
		return -EINVAL;
    32f0:	f06f 0515 	mvn.w	r5, #21
    32f4:	e7df      	b.n	32b6 <spi_nrfx_transceive+0x56>
	if (spi_cfg->operation & SPI_MODE_LOOP) {
    32f6:	0739      	lsls	r1, r7, #28
    32f8:	d504      	bpl.n	3304 <spi_nrfx_transceive+0xa4>
		LOG_ERR("Loopback mode is not supported");
    32fa:	4870      	ldr	r0, [pc, #448]	; (34bc <spi_nrfx_transceive+0x25c>)
    32fc:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("Word sizes other than 8 bits are not supported");
    32fe:	f005 fce8 	bl	8cd2 <z_log_minimal_printk>
	if (error == 0) {
    3302:	e7f5      	b.n	32f0 <spi_nrfx_transceive+0x90>
	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    3304:	f3c7 1345 	ubfx	r3, r7, #5, #6
    3308:	2b08      	cmp	r3, #8
    330a:	d002      	beq.n	3312 <spi_nrfx_transceive+0xb2>
		LOG_ERR("Word sizes other than 8 bits are not supported");
    330c:	486c      	ldr	r0, [pc, #432]	; (34c0 <spi_nrfx_transceive+0x260>)
    330e:	2145      	movs	r1, #69	; 0x45
    3310:	e7f5      	b.n	32fe <spi_nrfx_transceive+0x9e>
	if (spi_cfg->frequency < 125000) {
    3312:	6835      	ldr	r5, [r6, #0]
    3314:	4b6b      	ldr	r3, [pc, #428]	; (34c4 <spi_nrfx_transceive+0x264>)
    3316:	429d      	cmp	r5, r3
    3318:	d802      	bhi.n	3320 <spi_nrfx_transceive+0xc0>
		LOG_ERR("Frequencies lower than 125 kHz are not supported");
    331a:	486b      	ldr	r0, [pc, #428]	; (34c8 <spi_nrfx_transceive+0x268>)
    331c:	2145      	movs	r1, #69	; 0x45
    331e:	e7ee      	b.n	32fe <spi_nrfx_transceive+0x9e>
	config = dev_config->def_config;
    3320:	9b00      	ldr	r3, [sp, #0]
    3322:	f103 0e08 	add.w	lr, r3, #8
    3326:	e8be 000f 	ldmia.w	lr!, {r0, r1, r2, r3}
    332a:	f10d 0c0c 	add.w	ip, sp, #12
    332e:	e8ac 000f 	stmia.w	ip!, {r0, r1, r2, r3}
    3332:	f8de 3000 	ldr.w	r3, [lr]
    3336:	f8cc 3000 	str.w	r3, [ip]
	if (frequency < 250000) {
    333a:	4b64      	ldr	r3, [pc, #400]	; (34cc <spi_nrfx_transceive+0x26c>)
    333c:	429d      	cmp	r5, r3
    333e:	d93a      	bls.n	33b6 <spi_nrfx_transceive+0x156>
	} else if (frequency < 500000) {
    3340:	4b63      	ldr	r3, [pc, #396]	; (34d0 <spi_nrfx_transceive+0x270>)
    3342:	429d      	cmp	r5, r3
    3344:	d93a      	bls.n	33bc <spi_nrfx_transceive+0x15c>
	} else if (frequency < 1000000) {
    3346:	4b63      	ldr	r3, [pc, #396]	; (34d4 <spi_nrfx_transceive+0x274>)
    3348:	429d      	cmp	r5, r3
    334a:	d93a      	bls.n	33c2 <spi_nrfx_transceive+0x162>
	} else if (frequency < 2000000) {
    334c:	4b62      	ldr	r3, [pc, #392]	; (34d8 <spi_nrfx_transceive+0x278>)
    334e:	429d      	cmp	r5, r3
    3350:	d93a      	bls.n	33c8 <spi_nrfx_transceive+0x168>
	} else if (frequency < 4000000) {
    3352:	4b62      	ldr	r3, [pc, #392]	; (34dc <spi_nrfx_transceive+0x27c>)
    3354:	429d      	cmp	r5, r3
    3356:	d93a      	bls.n	33ce <spi_nrfx_transceive+0x16e>
		return NRF_SPI_FREQ_4M;
    3358:	4b61      	ldr	r3, [pc, #388]	; (34e0 <spi_nrfx_transceive+0x280>)
    335a:	429d      	cmp	r5, r3
    335c:	bf2c      	ite	cs
    335e:	f04f 4500 	movcs.w	r5, #2147483648	; 0x80000000
    3362:	f04f 4580 	movcc.w	r5, #1073741824	; 0x40000000
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    3366:	07ba      	lsls	r2, r7, #30
	config.frequency = get_nrf_spi_frequency(spi_cfg->frequency);
    3368:	9505      	str	r5, [sp, #20]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    336a:	f007 0304 	and.w	r3, r7, #4
    336e:	d531      	bpl.n	33d4 <spi_nrfx_transceive+0x174>
			return NRF_SPI_MODE_2;
    3370:	2b00      	cmp	r3, #0
    3372:	bf14      	ite	ne
    3374:	2303      	movne	r3, #3
    3376:	2302      	moveq	r3, #2
	config.mode      = get_nrf_spi_mode(spi_cfg->operation);
    3378:	f88d 3018 	strb.w	r3, [sp, #24]
	if (dev_data->initialized) {
    337c:	9b01      	ldr	r3, [sp, #4]
	if (operation & SPI_TRANSFER_LSB) {
    337e:	f3c7 1700 	ubfx	r7, r7, #4, #1
	config.bit_order = get_nrf_spi_bit_order(spi_cfg->operation);
    3382:	f88d 7019 	strb.w	r7, [sp, #25]
	if (dev_data->initialized) {
    3386:	b12b      	cbz	r3, 3394 <spi_nrfx_transceive+0x134>
		nrfx_spi_uninit(&dev_config->spi);
    3388:	9800      	ldr	r0, [sp, #0]
    338a:	f002 f963 	bl	5654 <nrfx_spi_uninit>
		dev_data->initialized = false;
    338e:	2300      	movs	r3, #0
    3390:	f88b 305d 	strb.w	r3, [fp, #93]	; 0x5d
	result = nrfx_spi_init(&dev_config->spi, &config,
    3394:	4a53      	ldr	r2, [pc, #332]	; (34e4 <spi_nrfx_transceive+0x284>)
    3396:	9800      	ldr	r0, [sp, #0]
    3398:	465b      	mov	r3, fp
    339a:	a903      	add	r1, sp, #12
    339c:	f002 f8ac 	bl	54f8 <nrfx_spi_init>
	if (result != NRFX_SUCCESS) {
    33a0:	4b51      	ldr	r3, [pc, #324]	; (34e8 <spi_nrfx_transceive+0x288>)
    33a2:	4298      	cmp	r0, r3
	result = nrfx_spi_init(&dev_config->spi, &config,
    33a4:	4602      	mov	r2, r0
	if (result != NRFX_SUCCESS) {
    33a6:	d019      	beq.n	33dc <spi_nrfx_transceive+0x17c>
		LOG_ERR("Failed to initialize nrfx driver: %08x", result);
    33a8:	4850      	ldr	r0, [pc, #320]	; (34ec <spi_nrfx_transceive+0x28c>)
    33aa:	2145      	movs	r1, #69	; 0x45
    33ac:	f005 fc91 	bl	8cd2 <z_log_minimal_printk>
		return -EIO;
    33b0:	f06f 0504 	mvn.w	r5, #4
    33b4:	e77f      	b.n	32b6 <spi_nrfx_transceive+0x56>
		return NRF_SPI_FREQ_125K;
    33b6:	f04f 7500 	mov.w	r5, #33554432	; 0x2000000
    33ba:	e7d4      	b.n	3366 <spi_nrfx_transceive+0x106>
		return NRF_SPI_FREQ_250K;
    33bc:	f04f 6580 	mov.w	r5, #67108864	; 0x4000000
    33c0:	e7d1      	b.n	3366 <spi_nrfx_transceive+0x106>
		return NRF_SPI_FREQ_500K;
    33c2:	f04f 6500 	mov.w	r5, #134217728	; 0x8000000
    33c6:	e7ce      	b.n	3366 <spi_nrfx_transceive+0x106>
		return NRF_SPI_FREQ_1M;
    33c8:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
    33cc:	e7cb      	b.n	3366 <spi_nrfx_transceive+0x106>
		return NRF_SPI_FREQ_2M;
    33ce:	f04f 5500 	mov.w	r5, #536870912	; 0x20000000
    33d2:	e7c8      	b.n	3366 <spi_nrfx_transceive+0x106>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    33d4:	3b00      	subs	r3, #0
    33d6:	bf18      	it	ne
    33d8:	2301      	movne	r3, #1
    33da:	e7cd      	b.n	3378 <spi_nrfx_transceive+0x118>
	dev_data->initialized = true;
    33dc:	2301      	movs	r3, #1
    33de:	f88b 305d 	strb.w	r3, [fp, #93]	; 0x5d
	ctx->config = spi_cfg;
    33e2:	f8cb 6000 	str.w	r6, [fp]
		dev_data->busy = true;
    33e6:	2301      	movs	r3, #1
    33e8:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    33ec:	f1ba 0f00 	cmp.w	sl, #0
    33f0:	d14e      	bne.n	3490 <spi_nrfx_transceive+0x230>
    33f2:	f8c4 a034 	str.w	sl, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    33f6:	2300      	movs	r3, #0
    33f8:	63a3      	str	r3, [r4, #56]	; 0x38
		spi_context_get_next_buf(&ctx->current_tx, &ctx->tx_count,
    33fa:	f104 0248 	add.w	r2, r4, #72	; 0x48
    33fe:	f104 0138 	add.w	r1, r4, #56	; 0x38
    3402:	f104 0034 	add.w	r0, r4, #52	; 0x34
    3406:	f005 fe29 	bl	905c <spi_context_get_next_buf.constprop.0>
	ctx->tx_buf = (const uint8_t *)
    340a:	6460      	str	r0, [r4, #68]	; 0x44
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    340c:	f1b9 0f00 	cmp.w	r9, #0
    3410:	d146      	bne.n	34a0 <spi_nrfx_transceive+0x240>
    3412:	f8c4 903c 	str.w	r9, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    3416:	2300      	movs	r3, #0
    3418:	6423      	str	r3, [r4, #64]	; 0x40
		spi_context_get_next_buf(&ctx->current_rx, &ctx->rx_count,
    341a:	f104 0250 	add.w	r2, r4, #80	; 0x50
    341e:	f104 0140 	add.w	r1, r4, #64	; 0x40
    3422:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    3426:	f005 fe19 	bl	905c <spi_context_get_next_buf.constprop.0>
	ctx->sync_status = 0;
    342a:	2600      	movs	r6, #0
	_spi_context_cs_control(ctx, on, false);
    342c:	4632      	mov	r2, r6
	ctx->rx_buf = (uint8_t *)
    342e:	64e0      	str	r0, [r4, #76]	; 0x4c
	_spi_context_cs_control(ctx, on, false);
    3430:	2101      	movs	r1, #1
    3432:	4620      	mov	r0, r4
	ctx->sync_status = 0;
    3434:	6326      	str	r6, [r4, #48]	; 0x30
	_spi_context_cs_control(ctx, on, false);
    3436:	f005 fe38 	bl	90aa <_spi_context_cs_control>
		transfer_next_chunk(dev);
    343a:	4640      	mov	r0, r8
    343c:	f7ff fe80 	bl	3140 <transfer_next_chunk>
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    3440:	6d25      	ldr	r5, [r4, #80]	; 0x50
    3442:	6ca3      	ldr	r3, [r4, #72]	; 0x48
			     ctx->config->frequency;
    3444:	4627      	mov	r7, r4
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    3446:	429d      	cmp	r5, r3
    3448:	bf38      	it	cc
    344a:	461d      	movcc	r5, r3
    344c:	f44f 53fa 	mov.w	r3, #8000	; 0x1f40
    3450:	435d      	muls	r5, r3
			     ctx->config->frequency;
    3452:	f857 3b20 	ldr.w	r3, [r7], #32
			/* Faster algorithm but source is first multiplied by target frequency
			 * and it can overflow even though final result would not overflow.
			 * Kconfig option shall prevent use of this algorithm when there is a
			 * risk of overflow.
			 */
			return ((t * to_hz + off) / from_hz);
    3456:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    345a:	681b      	ldr	r3, [r3, #0]
    345c:	fbb5 f5f3 	udiv	r5, r5, r3
    3460:	4631      	mov	r1, r6
		timeout_ms += CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE;
    3462:	35c8      	adds	r5, #200	; 0xc8
    3464:	f240 30e7 	movw	r0, #999	; 0x3e7
    3468:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    346c:	2300      	movs	r3, #0
    346e:	fbe5 010c 	umlal	r0, r1, r5, ip
    3472:	f7fc fe45 	bl	100 <__aeabi_uldivmod>
    3476:	4602      	mov	r2, r0
    3478:	460b      	mov	r3, r1
	return z_impl_k_sem_take(sem, timeout);
    347a:	4638      	mov	r0, r7
    347c:	f002 fef6 	bl	626c <z_impl_k_sem_take>
	if (k_sem_take(&ctx->sync, timeout)) {
    3480:	b1b0      	cbz	r0, 34b0 <spi_nrfx_transceive+0x250>
		LOG_ERR("Timeout waiting for transfer complete");
    3482:	481b      	ldr	r0, [pc, #108]	; (34f0 <spi_nrfx_transceive+0x290>)
    3484:	2145      	movs	r1, #69	; 0x45
    3486:	f005 fc24 	bl	8cd2 <z_log_minimal_printk>
		return -ETIMEDOUT;
    348a:	f06f 0573 	mvn.w	r5, #115	; 0x73
    348e:	e712      	b.n	32b6 <spi_nrfx_transceive+0x56>
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    3490:	f8da 3000 	ldr.w	r3, [sl]
    3494:	6363      	str	r3, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    3496:	2b00      	cmp	r3, #0
    3498:	d0ad      	beq.n	33f6 <spi_nrfx_transceive+0x196>
    349a:	f8da 3004 	ldr.w	r3, [sl, #4]
    349e:	e7ab      	b.n	33f8 <spi_nrfx_transceive+0x198>
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    34a0:	f8d9 3000 	ldr.w	r3, [r9]
    34a4:	63e3      	str	r3, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    34a6:	2b00      	cmp	r3, #0
    34a8:	d0b5      	beq.n	3416 <spi_nrfx_transceive+0x1b6>
    34aa:	f8d9 3004 	ldr.w	r3, [r9, #4]
    34ae:	e7b3      	b.n	3418 <spi_nrfx_transceive+0x1b8>
	status = ctx->sync_status;
    34b0:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return status;
    34b2:	e700      	b.n	32b6 <spi_nrfx_transceive+0x56>
    34b4:	0000b0c2 	.word	0x0000b0c2
    34b8:	0000b0e1 	.word	0x0000b0e1
    34bc:	0000b108 	.word	0x0000b108
    34c0:	0000b12c 	.word	0x0000b12c
    34c4:	0001e847 	.word	0x0001e847
    34c8:	0000b160 	.word	0x0000b160
    34cc:	0003d08f 	.word	0x0003d08f
    34d0:	0007a11f 	.word	0x0007a11f
    34d4:	000f423f 	.word	0x000f423f
    34d8:	001e847f 	.word	0x001e847f
    34dc:	003d08ff 	.word	0x003d08ff
    34e0:	007a1200 	.word	0x007a1200
    34e4:	000031c1 	.word	0x000031c1
    34e8:	0bad0000 	.word	0x0bad0000
    34ec:	0000b196 	.word	0x0000b196
    34f0:	0000b1c2 	.word	0x0000b1c2

000034f4 <spi_nrfx_init>:
}
#endif /* CONFIG_PM_DEVICE */


static int spi_nrfx_init(const struct device *dev)
{
    34f4:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	const struct spi_nrfx_config *dev_config = dev->config;
    34f8:	6844      	ldr	r4, [r0, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    34fa:	6905      	ldr	r5, [r0, #16]
	int err;

#ifdef CONFIG_PINCTRL
	err = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    34fc:	6aa6      	ldr	r6, [r4, #40]	; 0x28
	ret = pinctrl_lookup_state(config, id, &state);
    34fe:	aa01      	add	r2, sp, #4
    3500:	2100      	movs	r1, #0
    3502:	4630      	mov	r0, r6
    3504:	f006 f882 	bl	960c <pinctrl_lookup_state>
	if (ret < 0) {
    3508:	2800      	cmp	r0, #0
    350a:	db23      	blt.n	3554 <spi_nrfx_init+0x60>
	return pinctrl_apply_state_direct(config, state);
    350c:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    350e:	6832      	ldr	r2, [r6, #0]
    3510:	7919      	ldrb	r1, [r3, #4]
    3512:	6818      	ldr	r0, [r3, #0]
    3514:	f001 f8ac 	bl	4670 <pinctrl_configure_pins>
	if (err < 0) {
    3518:	2800      	cmp	r0, #0
    351a:	db1b      	blt.n	3554 <spi_nrfx_init+0x60>
		return err;
	}
#endif

	dev_config->irq_connect();
    351c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    351e:	4798      	blx	r3
	for (cs_gpio = ctx->cs_gpios; cs_gpio < &ctx->cs_gpios[ctx->num_cs_gpios]; cs_gpio++) {
    3520:	68ac      	ldr	r4, [r5, #8]
		data->invert |= (gpio_port_pins_t)BIT(pin);
    3522:	2601      	movs	r6, #1
    3524:	e9d5 3202 	ldrd	r3, r2, [r5, #8]
    3528:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
    352c:	429c      	cmp	r4, r3
    352e:	d304      	bcc.n	353a <spi_nrfx_init+0x46>
	err = spi_context_cs_configure_all(&dev_data->ctx);
	if (err < 0) {
		return err;
	}

	spi_context_unlock_unconditionally(&dev_data->ctx);
    3530:	4628      	mov	r0, r5
    3532:	f005 fe4c 	bl	91ce <spi_context_unlock_unconditionally>
	return 0;
    3536:	2000      	movs	r0, #0

#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
	return anomaly_58_workaround_init(dev);
#else
	return 0;
    3538:	e00c      	b.n	3554 <spi_nrfx_init+0x60>
		if (!device_is_ready(cs_gpio->port)) {
    353a:	6820      	ldr	r0, [r4, #0]
    353c:	f006 fa83 	bl	9a46 <z_device_is_ready>
    3540:	b958      	cbnz	r0, 355a <spi_nrfx_init+0x66>
			LOG_ERR("CS GPIO port %s pin %d is not ready",
    3542:	6822      	ldr	r2, [r4, #0]
    3544:	4816      	ldr	r0, [pc, #88]	; (35a0 <spi_nrfx_init+0xac>)
    3546:	7923      	ldrb	r3, [r4, #4]
    3548:	6812      	ldr	r2, [r2, #0]
    354a:	2145      	movs	r1, #69	; 0x45
    354c:	f005 fbc1 	bl	8cd2 <z_log_minimal_printk>
			return -ENODEV;
    3550:	f06f 0012 	mvn.w	r0, #18
#endif
}
    3554:	b002      	add	sp, #8
    3556:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	return gpio_pin_configure(spec->port,
    355a:	6820      	ldr	r0, [r4, #0]
				  spec->pin,
    355c:	7921      	ldrb	r1, [r4, #4]
				  spec->dt_flags | extra_flags);
    355e:	88e3      	ldrh	r3, [r4, #6]
	struct gpio_driver_data *data =
    3560:	f8d0 c010 	ldr.w	ip, [r0, #16]
	const struct gpio_driver_api *api =
    3564:	f8d0 8008 	ldr.w	r8, [r0, #8]
		data->invert |= (gpio_port_pins_t)BIT(pin);
    3568:	f8dc 7000 	ldr.w	r7, [ip]
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    356c:	07da      	lsls	r2, r3, #31
	return gpio_pin_configure(spec->port,
    356e:	bf54      	ite	pl
    3570:	f443 13b0 	orrpl.w	r3, r3, #1441792	; 0x160000
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
    3574:	f483 13d0 	eormi.w	r3, r3, #1703936	; 0x1a0000
	flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
    3578:	f423 1280 	bic.w	r2, r3, #1048576	; 0x100000
		data->invert |= (gpio_port_pins_t)BIT(pin);
    357c:	fa06 fe01 	lsl.w	lr, r6, r1
	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    3580:	07db      	lsls	r3, r3, #31
		data->invert |= (gpio_port_pins_t)BIT(pin);
    3582:	bf4c      	ite	mi
    3584:	ea4e 0707 	orrmi.w	r7, lr, r7
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    3588:	ea27 070e 	bicpl.w	r7, r7, lr
    358c:	f8cc 7000 	str.w	r7, [ip]
	return api->pin_configure(port, pin, flags);
    3590:	f8d8 3000 	ldr.w	r3, [r8]
    3594:	4798      	blx	r3
		if (ret < 0) {
    3596:	2800      	cmp	r0, #0
    3598:	dbdc      	blt.n	3554 <spi_nrfx_init+0x60>
	for (cs_gpio = ctx->cs_gpios; cs_gpio < &ctx->cs_gpios[ctx->num_cs_gpios]; cs_gpio++) {
    359a:	3408      	adds	r4, #8
    359c:	e7c2      	b.n	3524 <spi_nrfx_init+0x30>
    359e:	bf00      	nop
    35a0:	0000b076 	.word	0x0000b076

000035a4 <transfer_next_chunk>:
{
    35a4:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	struct spi_nrfx_data *dev_data = dev->data;
    35a6:	6904      	ldr	r4, [r0, #16]
	const struct spi_nrfx_config *dev_config = dev->config;
    35a8:	6846      	ldr	r6, [r0, #4]
	if (!ctx->tx_len) {
    35aa:	6ca5      	ldr	r5, [r4, #72]	; 0x48
		return ctx->rx_len;
    35ac:	6d23      	ldr	r3, [r4, #80]	; 0x50
	if (!ctx->tx_len) {
    35ae:	b98d      	cbnz	r5, 35d4 <transfer_next_chunk+0x30>
	if (chunk_len > 0) {
    35b0:	2b00      	cmp	r3, #0
    35b2:	d137      	bne.n	3624 <transfer_next_chunk+0x80>
	int error = 0;
    35b4:	461d      	mov	r5, r3
	_spi_context_cs_control(ctx, on, false);
    35b6:	2200      	movs	r2, #0
    35b8:	4611      	mov	r1, r2
    35ba:	4620      	mov	r0, r4
    35bc:	f005 fde5 	bl	918a <_spi_context_cs_control>
	ctx->sync_status = status;
    35c0:	6325      	str	r5, [r4, #48]	; 0x30
	z_impl_k_sem_give(sem);
    35c2:	f104 0020 	add.w	r0, r4, #32
    35c6:	f002 fe31 	bl	622c <z_impl_k_sem_give>
	dev_data->busy = false;
    35ca:	2300      	movs	r3, #0
    35cc:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
}
    35d0:	b004      	add	sp, #16
    35d2:	bd70      	pop	{r4, r5, r6, pc}
		const uint8_t *tx_buf = ctx->tx_buf;
    35d4:	6c61      	ldr	r1, [r4, #68]	; 0x44
	} else if (!ctx->rx_len) {
    35d6:	bb0b      	cbnz	r3, 361c <transfer_next_chunk+0x78>
	return !!(ctx->tx_buf && ctx->tx_len);
    35d8:	bb39      	cbnz	r1, 362a <transfer_next_chunk+0x86>
		if (chunk_len > MAX_CHUNK_LEN) {
    35da:	f64f 72ff 	movw	r2, #65535	; 0xffff
    35de:	42aa      	cmp	r2, r5
    35e0:	6c63      	ldr	r3, [r4, #68]	; 0x44
		xfer.p_tx_buffer = tx_buf;
    35e2:	9100      	str	r1, [sp, #0]
		if (chunk_len > MAX_CHUNK_LEN) {
    35e4:	bf28      	it	cs
    35e6:	462a      	movcs	r2, r5
		dev_data->chunk_len = chunk_len;
    35e8:	65a2      	str	r2, [r4, #88]	; 0x58
    35ea:	b11b      	cbz	r3, 35f4 <transfer_next_chunk+0x50>
    35ec:	6ca3      	ldr	r3, [r4, #72]	; 0x48
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    35ee:	2b00      	cmp	r3, #0
    35f0:	bf18      	it	ne
    35f2:	4613      	movne	r3, r2
    35f4:	9301      	str	r3, [sp, #4]
		xfer.p_rx_buffer = ctx->rx_buf;
    35f6:	6ce3      	ldr	r3, [r4, #76]	; 0x4c
    35f8:	9302      	str	r3, [sp, #8]
	return !!(ctx->rx_buf && ctx->rx_len);
    35fa:	b11b      	cbz	r3, 3604 <transfer_next_chunk+0x60>
    35fc:	6d23      	ldr	r3, [r4, #80]	; 0x50
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    35fe:	2b00      	cmp	r3, #0
    3600:	bf18      	it	ne
    3602:	4613      	movne	r3, r2
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    3604:	2200      	movs	r2, #0
    3606:	4669      	mov	r1, sp
    3608:	4630      	mov	r0, r6
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    360a:	9303      	str	r3, [sp, #12]
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    360c:	f002 fa64 	bl	5ad8 <nrfx_spim_xfer>
			if (result == NRFX_SUCCESS) {
    3610:	4b0d      	ldr	r3, [pc, #52]	; (3648 <transfer_next_chunk+0xa4>)
    3612:	4298      	cmp	r0, r3
    3614:	d0dc      	beq.n	35d0 <transfer_next_chunk+0x2c>
			error = -EIO;
    3616:	f06f 0504 	mvn.w	r5, #4
    361a:	e7cc      	b.n	35b6 <transfer_next_chunk+0x12>
	return MIN(ctx->tx_len, ctx->rx_len);
    361c:	429d      	cmp	r5, r3
    361e:	bf28      	it	cs
    3620:	461d      	movcs	r5, r3
    3622:	e7d9      	b.n	35d8 <transfer_next_chunk+0x34>
		const uint8_t *tx_buf = ctx->tx_buf;
    3624:	6c61      	ldr	r1, [r4, #68]	; 0x44
    3626:	461d      	mov	r5, r3
    3628:	e7d7      	b.n	35da <transfer_next_chunk+0x36>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
{
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    362a:	f001 4360 	and.w	r3, r1, #3758096384	; 0xe0000000
		if (spi_context_tx_buf_on(ctx) && !nrfx_is_in_ram(tx_buf)) {
    362e:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    3632:	d0d2      	beq.n	35da <transfer_next_chunk+0x36>
			if (chunk_len > CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) {
    3634:	2d08      	cmp	r5, #8
    3636:	bf28      	it	cs
    3638:	2508      	movcs	r5, #8
			memcpy(dev_data->buffer, tx_buf, chunk_len);
    363a:	6e20      	ldr	r0, [r4, #96]	; 0x60
    363c:	462a      	mov	r2, r5
    363e:	f005 fbfa 	bl	8e36 <memcpy>
			tx_buf = dev_data->buffer;
    3642:	6e21      	ldr	r1, [r4, #96]	; 0x60
    3644:	e7c9      	b.n	35da <transfer_next_chunk+0x36>
    3646:	bf00      	nop
    3648:	0bad0000 	.word	0x0bad0000

0000364c <event_handler>:
{
    364c:	b510      	push	{r4, lr}
	if (p_event->type == NRFX_SPIM_EVENT_DONE) {
    364e:	7803      	ldrb	r3, [r0, #0]
{
    3650:	460c      	mov	r4, r1
	if (p_event->type == NRFX_SPIM_EVENT_DONE) {
    3652:	2b00      	cmp	r3, #0
    3654:	d147      	bne.n	36e6 <event_handler+0x9a>
	if (!ctx->tx_len) {
    3656:	6c8b      	ldr	r3, [r1, #72]	; 0x48
		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
    3658:	6d8a      	ldr	r2, [r1, #88]	; 0x58
    365a:	b12b      	cbz	r3, 3668 <event_handler+0x1c>
	if (len > ctx->tx_len) {
    365c:	429a      	cmp	r2, r3
    365e:	d911      	bls.n	3684 <event_handler+0x38>
		LOG_ERR("Update exceeds current buffer");
    3660:	4821      	ldr	r0, [pc, #132]	; (36e8 <event_handler+0x9c>)
    3662:	2145      	movs	r1, #69	; 0x45
    3664:	f005 fb35 	bl	8cd2 <z_log_minimal_printk>
	if (!ctx->rx_len) {
    3668:	6d23      	ldr	r3, [r4, #80]	; 0x50
		spi_context_update_rx(&dev_data->ctx, 1, dev_data->chunk_len);
    366a:	6da2      	ldr	r2, [r4, #88]	; 0x58
    366c:	b12b      	cbz	r3, 367a <event_handler+0x2e>
	if (len > ctx->rx_len) {
    366e:	429a      	cmp	r2, r3
    3670:	d920      	bls.n	36b4 <event_handler+0x68>
		LOG_ERR("Update exceeds current buffer");
    3672:	481d      	ldr	r0, [pc, #116]	; (36e8 <event_handler+0x9c>)
    3674:	2145      	movs	r1, #69	; 0x45
    3676:	f005 fb2c 	bl	8cd2 <z_log_minimal_printk>
		transfer_next_chunk(dev_data->dev);
    367a:	6d60      	ldr	r0, [r4, #84]	; 0x54
}
    367c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		transfer_next_chunk(dev_data->dev);
    3680:	f7ff bf90 	b.w	35a4 <transfer_next_chunk>
	ctx->tx_len -= len;
    3684:	1a9b      	subs	r3, r3, r2
    3686:	648b      	str	r3, [r1, #72]	; 0x48
	if (!ctx->tx_len) {
    3688:	b973      	cbnz	r3, 36a8 <event_handler+0x5c>
		++ctx->current_tx;
    368a:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    368c:	3308      	adds	r3, #8
    368e:	634b      	str	r3, [r1, #52]	; 0x34
		--ctx->tx_count;
    3690:	6b8b      	ldr	r3, [r1, #56]	; 0x38
    3692:	3b01      	subs	r3, #1
    3694:	638b      	str	r3, [r1, #56]	; 0x38
			spi_context_get_next_buf(&ctx->current_tx,
    3696:	f101 0248 	add.w	r2, r1, #72	; 0x48
    369a:	f104 0034 	add.w	r0, r4, #52	; 0x34
    369e:	3138      	adds	r1, #56	; 0x38
    36a0:	f005 fd4c 	bl	913c <spi_context_get_next_buf.constprop.0>
		ctx->tx_buf = (const uint8_t *)
    36a4:	6460      	str	r0, [r4, #68]	; 0x44
    36a6:	e7df      	b.n	3668 <event_handler+0x1c>
	} else if (ctx->tx_buf) {
    36a8:	6c4b      	ldr	r3, [r1, #68]	; 0x44
    36aa:	2b00      	cmp	r3, #0
    36ac:	d0dc      	beq.n	3668 <event_handler+0x1c>
		ctx->tx_buf += dfs * len;
    36ae:	4413      	add	r3, r2
    36b0:	644b      	str	r3, [r1, #68]	; 0x44
    36b2:	e7d9      	b.n	3668 <event_handler+0x1c>
	ctx->rx_len -= len;
    36b4:	1a9b      	subs	r3, r3, r2
    36b6:	6523      	str	r3, [r4, #80]	; 0x50
	if (!ctx->rx_len) {
    36b8:	b97b      	cbnz	r3, 36da <event_handler+0x8e>
		++ctx->current_rx;
    36ba:	6be3      	ldr	r3, [r4, #60]	; 0x3c
    36bc:	3308      	adds	r3, #8
    36be:	63e3      	str	r3, [r4, #60]	; 0x3c
		--ctx->rx_count;
    36c0:	6c23      	ldr	r3, [r4, #64]	; 0x40
    36c2:	3b01      	subs	r3, #1
    36c4:	6423      	str	r3, [r4, #64]	; 0x40
			spi_context_get_next_buf(&ctx->current_rx,
    36c6:	f104 0250 	add.w	r2, r4, #80	; 0x50
    36ca:	f104 0140 	add.w	r1, r4, #64	; 0x40
    36ce:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    36d2:	f005 fd33 	bl	913c <spi_context_get_next_buf.constprop.0>
		ctx->rx_buf = (uint8_t *)
    36d6:	64e0      	str	r0, [r4, #76]	; 0x4c
    36d8:	e7cf      	b.n	367a <event_handler+0x2e>
	} else if (ctx->rx_buf) {
    36da:	6ce3      	ldr	r3, [r4, #76]	; 0x4c
    36dc:	2b00      	cmp	r3, #0
    36de:	d0cc      	beq.n	367a <event_handler+0x2e>
		ctx->rx_buf += dfs * len;
    36e0:	4413      	add	r3, r2
    36e2:	64e3      	str	r3, [r4, #76]	; 0x4c
    36e4:	e7c9      	b.n	367a <event_handler+0x2e>
}
    36e6:	bd10      	pop	{r4, pc}
    36e8:	0000b09f 	.word	0x0000b09f

000036ec <spi_nrfx_transceive>:
{
    36ec:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    36f0:	469b      	mov	fp, r3
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    36f2:	888b      	ldrh	r3, [r1, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    36f4:	6904      	ldr	r4, [r0, #16]
    36f6:	049f      	lsls	r7, r3, #18
{
    36f8:	b08b      	sub	sp, #44	; 0x2c
    36fa:	4680      	mov	r8, r0
    36fc:	460e      	mov	r6, r1
    36fe:	4691      	mov	r9, r2
    3700:	d42f      	bmi.n	3762 <spi_nrfx_transceive+0x76>
	return z_impl_k_sem_take(sem, timeout);
    3702:	f04f 32ff 	mov.w	r2, #4294967295
    3706:	f04f 33ff 	mov.w	r3, #4294967295
    370a:	f104 0010 	add.w	r0, r4, #16
    370e:	f002 fdad 	bl	626c <z_impl_k_sem_take>
	ctx->owner = spi_cfg;
    3712:	6066      	str	r6, [r4, #4]
	const struct spi_nrfx_config *dev_config = dev->config;
    3714:	f8d8 3004 	ldr.w	r3, [r8, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    3718:	f8d8 a010 	ldr.w	sl, [r8, #16]
	const struct spi_nrfx_config *dev_config = dev->config;
    371c:	9301      	str	r3, [sp, #4]
	uint32_t max_freq = dev_config->max_freq;
    371e:	689b      	ldr	r3, [r3, #8]
    3720:	9303      	str	r3, [sp, #12]
	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
    3722:	f89a 305d 	ldrb.w	r3, [sl, #93]	; 0x5d
    3726:	9302      	str	r3, [sp, #8]
    3728:	b123      	cbz	r3, 3734 <spi_nrfx_transceive+0x48>
    372a:	f8da 3000 	ldr.w	r3, [sl]
    372e:	429e      	cmp	r6, r3
    3730:	f000 80b2 	beq.w	3898 <spi_nrfx_transceive+0x1ac>
	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
    3734:	88b7      	ldrh	r7, [r6, #4]
    3736:	053d      	lsls	r5, r7, #20
    3738:	d51a      	bpl.n	3770 <spi_nrfx_transceive+0x84>
		LOG_ERR("Half-duplex not supported");
    373a:	488b      	ldr	r0, [pc, #556]	; (3968 <spi_nrfx_transceive+0x27c>)
    373c:	2145      	movs	r1, #69	; 0x45
    373e:	f005 fac8 	bl	8cd2 <z_log_minimal_printk>
		return -ENOTSUP;
    3742:	f06f 0585 	mvn.w	r5, #133	; 0x85
	if (!(ctx->config->operation & SPI_LOCK_ON)) {
    3746:	6823      	ldr	r3, [r4, #0]
    3748:	889b      	ldrh	r3, [r3, #4]
    374a:	f413 5300 	ands.w	r3, r3, #8192	; 0x2000
    374e:	d104      	bne.n	375a <spi_nrfx_transceive+0x6e>
		ctx->owner = NULL;
    3750:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    3752:	f104 0010 	add.w	r0, r4, #16
    3756:	f002 fd69 	bl	622c <z_impl_k_sem_give>
}
    375a:	4628      	mov	r0, r5
    375c:	b00b      	add	sp, #44	; 0x2c
    375e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    3762:	69a3      	ldr	r3, [r4, #24]
    3764:	2b00      	cmp	r3, #0
    3766:	d1cc      	bne.n	3702 <spi_nrfx_transceive+0x16>
		(k_sem_count_get(&ctx->lock) == 0) &&
    3768:	6863      	ldr	r3, [r4, #4]
    376a:	4299      	cmp	r1, r3
    376c:	d1c9      	bne.n	3702 <spi_nrfx_transceive+0x16>
    376e:	e7d1      	b.n	3714 <spi_nrfx_transceive+0x28>
	if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
    3770:	07f8      	lsls	r0, r7, #31
    3772:	d508      	bpl.n	3786 <spi_nrfx_transceive+0x9a>
		LOG_ERR("Slave mode is not supported on %s", dev->name);
    3774:	f8d8 2000 	ldr.w	r2, [r8]
    3778:	487c      	ldr	r0, [pc, #496]	; (396c <spi_nrfx_transceive+0x280>)
    377a:	2145      	movs	r1, #69	; 0x45
    377c:	f005 faa9 	bl	8cd2 <z_log_minimal_printk>
		return -EINVAL;
    3780:	f06f 0515 	mvn.w	r5, #21
    3784:	e7df      	b.n	3746 <spi_nrfx_transceive+0x5a>
	if (spi_cfg->operation & SPI_MODE_LOOP) {
    3786:	0739      	lsls	r1, r7, #28
    3788:	d504      	bpl.n	3794 <spi_nrfx_transceive+0xa8>
		LOG_ERR("Loopback mode is not supported");
    378a:	4879      	ldr	r0, [pc, #484]	; (3970 <spi_nrfx_transceive+0x284>)
    378c:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("Word sizes other than 8 bits are not supported");
    378e:	f005 faa0 	bl	8cd2 <z_log_minimal_printk>
	if (error == 0) {
    3792:	e7f5      	b.n	3780 <spi_nrfx_transceive+0x94>
	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    3794:	f3c7 1345 	ubfx	r3, r7, #5, #6
    3798:	2b08      	cmp	r3, #8
    379a:	d002      	beq.n	37a2 <spi_nrfx_transceive+0xb6>
		LOG_ERR("Word sizes other than 8 bits are not supported");
    379c:	4875      	ldr	r0, [pc, #468]	; (3974 <spi_nrfx_transceive+0x288>)
    379e:	2145      	movs	r1, #69	; 0x45
    37a0:	e7f5      	b.n	378e <spi_nrfx_transceive+0xa2>
	if (spi_cfg->frequency < 125000) {
    37a2:	6835      	ldr	r5, [r6, #0]
    37a4:	4b74      	ldr	r3, [pc, #464]	; (3978 <spi_nrfx_transceive+0x28c>)
    37a6:	429d      	cmp	r5, r3
    37a8:	d802      	bhi.n	37b0 <spi_nrfx_transceive+0xc4>
		LOG_ERR("Frequencies lower than 125 kHz are not supported");
    37aa:	4874      	ldr	r0, [pc, #464]	; (397c <spi_nrfx_transceive+0x290>)
    37ac:	2145      	movs	r1, #69	; 0x45
    37ae:	e7ee      	b.n	378e <spi_nrfx_transceive+0xa2>
	config = dev_config->def_config;
    37b0:	9b01      	ldr	r3, [sp, #4]
    37b2:	f103 0e0c 	add.w	lr, r3, #12
    37b6:	e8be 000f 	ldmia.w	lr!, {r0, r1, r2, r3}
    37ba:	f10d 0c10 	add.w	ip, sp, #16
    37be:	e8ac 000f 	stmia.w	ip!, {r0, r1, r2, r3}
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    37c2:	9b03      	ldr	r3, [sp, #12]
    37c4:	42ab      	cmp	r3, r5
    37c6:	bf28      	it	cs
    37c8:	462b      	movcs	r3, r5
    37ca:	461d      	mov	r5, r3
	config = dev_config->def_config;
    37cc:	e89e 0003 	ldmia.w	lr, {r0, r1}
	if (frequency < 250000) {
    37d0:	4b6b      	ldr	r3, [pc, #428]	; (3980 <spi_nrfx_transceive+0x294>)
    37d2:	429d      	cmp	r5, r3
	config = dev_config->def_config;
    37d4:	e88c 0003 	stmia.w	ip, {r0, r1}
	if (frequency < 250000) {
    37d8:	d940      	bls.n	385c <spi_nrfx_transceive+0x170>
	} else if (frequency < 500000) {
    37da:	4b6a      	ldr	r3, [pc, #424]	; (3984 <spi_nrfx_transceive+0x298>)
    37dc:	429d      	cmp	r5, r3
    37de:	d940      	bls.n	3862 <spi_nrfx_transceive+0x176>
	} else if (frequency < 1000000) {
    37e0:	4b69      	ldr	r3, [pc, #420]	; (3988 <spi_nrfx_transceive+0x29c>)
    37e2:	429d      	cmp	r5, r3
    37e4:	d940      	bls.n	3868 <spi_nrfx_transceive+0x17c>
	} else if (frequency < 2000000) {
    37e6:	4b69      	ldr	r3, [pc, #420]	; (398c <spi_nrfx_transceive+0x2a0>)
    37e8:	429d      	cmp	r5, r3
    37ea:	d940      	bls.n	386e <spi_nrfx_transceive+0x182>
	} else if (frequency < 4000000) {
    37ec:	4b68      	ldr	r3, [pc, #416]	; (3990 <spi_nrfx_transceive+0x2a4>)
    37ee:	429d      	cmp	r5, r3
    37f0:	d940      	bls.n	3874 <spi_nrfx_transceive+0x188>
	} else if (frequency < 8000000) {
    37f2:	4b68      	ldr	r3, [pc, #416]	; (3994 <spi_nrfx_transceive+0x2a8>)
    37f4:	429d      	cmp	r5, r3
    37f6:	d340      	bcc.n	387a <spi_nrfx_transceive+0x18e>
	} else if (frequency < 16000000) {
    37f8:	4b67      	ldr	r3, [pc, #412]	; (3998 <spi_nrfx_transceive+0x2ac>)
    37fa:	429d      	cmp	r5, r3
    37fc:	d340      	bcc.n	3880 <spi_nrfx_transceive+0x194>
		return NRF_SPIM_FREQ_16M;
    37fe:	4b67      	ldr	r3, [pc, #412]	; (399c <spi_nrfx_transceive+0x2b0>)
    3800:	429d      	cmp	r5, r3
    3802:	bf2c      	ite	cs
    3804:	f04f 55a0 	movcs.w	r5, #335544320	; 0x14000000
    3808:	f04f 6520 	movcc.w	r5, #167772160	; 0xa000000
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    380c:	07ba      	lsls	r2, r7, #30
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    380e:	9506      	str	r5, [sp, #24]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    3810:	f007 0304 	and.w	r3, r7, #4
    3814:	d537      	bpl.n	3886 <spi_nrfx_transceive+0x19a>
			return NRF_SPIM_MODE_2;
    3816:	2b00      	cmp	r3, #0
    3818:	bf14      	ite	ne
    381a:	2303      	movne	r3, #3
    381c:	2302      	moveq	r3, #2
	config.mode      = get_nrf_spim_mode(spi_cfg->operation);
    381e:	f88d 301c 	strb.w	r3, [sp, #28]
	if (dev_data->initialized) {
    3822:	9b02      	ldr	r3, [sp, #8]
	if (operation & SPI_TRANSFER_LSB) {
    3824:	f3c7 1700 	ubfx	r7, r7, #4, #1
	config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
    3828:	f88d 701d 	strb.w	r7, [sp, #29]
	if (dev_data->initialized) {
    382c:	b12b      	cbz	r3, 383a <spi_nrfx_transceive+0x14e>
		nrfx_spim_uninit(&dev_config->spim);
    382e:	9801      	ldr	r0, [sp, #4]
    3830:	f002 f8f4 	bl	5a1c <nrfx_spim_uninit>
		dev_data->initialized = false;
    3834:	2300      	movs	r3, #0
    3836:	f88a 305d 	strb.w	r3, [sl, #93]	; 0x5d
	result = nrfx_spim_init(&dev_config->spim, &config,
    383a:	4a59      	ldr	r2, [pc, #356]	; (39a0 <spi_nrfx_transceive+0x2b4>)
    383c:	9801      	ldr	r0, [sp, #4]
    383e:	4653      	mov	r3, sl
    3840:	a904      	add	r1, sp, #16
    3842:	f001 ffeb 	bl	581c <nrfx_spim_init>
	if (result != NRFX_SUCCESS) {
    3846:	4b57      	ldr	r3, [pc, #348]	; (39a4 <spi_nrfx_transceive+0x2b8>)
    3848:	4298      	cmp	r0, r3
	result = nrfx_spim_init(&dev_config->spim, &config,
    384a:	4602      	mov	r2, r0
	if (result != NRFX_SUCCESS) {
    384c:	d01f      	beq.n	388e <spi_nrfx_transceive+0x1a2>
		LOG_ERR("Failed to initialize nrfx driver: %08x", result);
    384e:	4856      	ldr	r0, [pc, #344]	; (39a8 <spi_nrfx_transceive+0x2bc>)
    3850:	2145      	movs	r1, #69	; 0x45
    3852:	f005 fa3e 	bl	8cd2 <z_log_minimal_printk>
		return -EIO;
    3856:	f06f 0504 	mvn.w	r5, #4
    385a:	e774      	b.n	3746 <spi_nrfx_transceive+0x5a>
		return NRF_SPIM_FREQ_125K;
    385c:	f04f 7500 	mov.w	r5, #33554432	; 0x2000000
    3860:	e7d4      	b.n	380c <spi_nrfx_transceive+0x120>
		return NRF_SPIM_FREQ_250K;
    3862:	f04f 6580 	mov.w	r5, #67108864	; 0x4000000
    3866:	e7d1      	b.n	380c <spi_nrfx_transceive+0x120>
		return NRF_SPIM_FREQ_500K;
    3868:	f04f 6500 	mov.w	r5, #134217728	; 0x8000000
    386c:	e7ce      	b.n	380c <spi_nrfx_transceive+0x120>
		return NRF_SPIM_FREQ_1M;
    386e:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
    3872:	e7cb      	b.n	380c <spi_nrfx_transceive+0x120>
		return NRF_SPIM_FREQ_2M;
    3874:	f04f 5500 	mov.w	r5, #536870912	; 0x20000000
    3878:	e7c8      	b.n	380c <spi_nrfx_transceive+0x120>
		return NRF_SPIM_FREQ_4M;
    387a:	f04f 4580 	mov.w	r5, #1073741824	; 0x40000000
    387e:	e7c5      	b.n	380c <spi_nrfx_transceive+0x120>
		return NRF_SPIM_FREQ_8M;
    3880:	f04f 4500 	mov.w	r5, #2147483648	; 0x80000000
    3884:	e7c2      	b.n	380c <spi_nrfx_transceive+0x120>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    3886:	3b00      	subs	r3, #0
    3888:	bf18      	it	ne
    388a:	2301      	movne	r3, #1
    388c:	e7c7      	b.n	381e <spi_nrfx_transceive+0x132>
	dev_data->initialized = true;
    388e:	2301      	movs	r3, #1
    3890:	f88a 305d 	strb.w	r3, [sl, #93]	; 0x5d
	ctx->config = spi_cfg;
    3894:	f8ca 6000 	str.w	r6, [sl]
		dev_data->busy = true;
    3898:	2301      	movs	r3, #1
    389a:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    389e:	f1b9 0f00 	cmp.w	r9, #0
    38a2:	d14e      	bne.n	3942 <spi_nrfx_transceive+0x256>
    38a4:	f8c4 9034 	str.w	r9, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    38a8:	2300      	movs	r3, #0
    38aa:	63a3      	str	r3, [r4, #56]	; 0x38
		spi_context_get_next_buf(&ctx->current_tx, &ctx->tx_count,
    38ac:	f104 0248 	add.w	r2, r4, #72	; 0x48
    38b0:	f104 0138 	add.w	r1, r4, #56	; 0x38
    38b4:	f104 0034 	add.w	r0, r4, #52	; 0x34
    38b8:	f005 fc40 	bl	913c <spi_context_get_next_buf.constprop.0>
	ctx->tx_buf = (const uint8_t *)
    38bc:	6460      	str	r0, [r4, #68]	; 0x44
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    38be:	f1bb 0f00 	cmp.w	fp, #0
    38c2:	d146      	bne.n	3952 <spi_nrfx_transceive+0x266>
    38c4:	f8c4 b03c 	str.w	fp, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    38c8:	2300      	movs	r3, #0
    38ca:	6423      	str	r3, [r4, #64]	; 0x40
		spi_context_get_next_buf(&ctx->current_rx, &ctx->rx_count,
    38cc:	f104 0250 	add.w	r2, r4, #80	; 0x50
    38d0:	f104 0140 	add.w	r1, r4, #64	; 0x40
    38d4:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    38d8:	f005 fc30 	bl	913c <spi_context_get_next_buf.constprop.0>
	ctx->sync_status = 0;
    38dc:	2600      	movs	r6, #0
	_spi_context_cs_control(ctx, on, false);
    38de:	4632      	mov	r2, r6
	ctx->rx_buf = (uint8_t *)
    38e0:	64e0      	str	r0, [r4, #76]	; 0x4c
	_spi_context_cs_control(ctx, on, false);
    38e2:	2101      	movs	r1, #1
    38e4:	4620      	mov	r0, r4
	ctx->sync_status = 0;
    38e6:	6326      	str	r6, [r4, #48]	; 0x30
	_spi_context_cs_control(ctx, on, false);
    38e8:	f005 fc4f 	bl	918a <_spi_context_cs_control>
		transfer_next_chunk(dev);
    38ec:	4640      	mov	r0, r8
    38ee:	f7ff fe59 	bl	35a4 <transfer_next_chunk>
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    38f2:	6d25      	ldr	r5, [r4, #80]	; 0x50
    38f4:	6ca3      	ldr	r3, [r4, #72]	; 0x48
			     ctx->config->frequency;
    38f6:	4627      	mov	r7, r4
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    38f8:	429d      	cmp	r5, r3
    38fa:	bf38      	it	cc
    38fc:	461d      	movcc	r5, r3
    38fe:	f44f 53fa 	mov.w	r3, #8000	; 0x1f40
    3902:	435d      	muls	r5, r3
			     ctx->config->frequency;
    3904:	f857 3b20 	ldr.w	r3, [r7], #32
    3908:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    390c:	681b      	ldr	r3, [r3, #0]
    390e:	fbb5 f5f3 	udiv	r5, r5, r3
    3912:	4631      	mov	r1, r6
		timeout_ms += CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE;
    3914:	35c8      	adds	r5, #200	; 0xc8
    3916:	f240 30e7 	movw	r0, #999	; 0x3e7
    391a:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    391e:	2300      	movs	r3, #0
    3920:	fbe5 010c 	umlal	r0, r1, r5, ip
    3924:	f7fc fbec 	bl	100 <__aeabi_uldivmod>
    3928:	4602      	mov	r2, r0
    392a:	460b      	mov	r3, r1
	return z_impl_k_sem_take(sem, timeout);
    392c:	4638      	mov	r0, r7
    392e:	f002 fc9d 	bl	626c <z_impl_k_sem_take>
	if (k_sem_take(&ctx->sync, timeout)) {
    3932:	b1b0      	cbz	r0, 3962 <spi_nrfx_transceive+0x276>
		LOG_ERR("Timeout waiting for transfer complete");
    3934:	481d      	ldr	r0, [pc, #116]	; (39ac <spi_nrfx_transceive+0x2c0>)
    3936:	2145      	movs	r1, #69	; 0x45
    3938:	f005 f9cb 	bl	8cd2 <z_log_minimal_printk>
		return -ETIMEDOUT;
    393c:	f06f 0573 	mvn.w	r5, #115	; 0x73
    3940:	e701      	b.n	3746 <spi_nrfx_transceive+0x5a>
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    3942:	f8d9 3000 	ldr.w	r3, [r9]
    3946:	6363      	str	r3, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    3948:	2b00      	cmp	r3, #0
    394a:	d0ad      	beq.n	38a8 <spi_nrfx_transceive+0x1bc>
    394c:	f8d9 3004 	ldr.w	r3, [r9, #4]
    3950:	e7ab      	b.n	38aa <spi_nrfx_transceive+0x1be>
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    3952:	f8db 3000 	ldr.w	r3, [fp]
    3956:	63e3      	str	r3, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    3958:	2b00      	cmp	r3, #0
    395a:	d0b5      	beq.n	38c8 <spi_nrfx_transceive+0x1dc>
    395c:	f8db 3004 	ldr.w	r3, [fp, #4]
    3960:	e7b3      	b.n	38ca <spi_nrfx_transceive+0x1de>
	status = ctx->sync_status;
    3962:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return status;
    3964:	e6ef      	b.n	3746 <spi_nrfx_transceive+0x5a>
    3966:	bf00      	nop
    3968:	0000b0c2 	.word	0x0000b0c2
    396c:	0000b0e1 	.word	0x0000b0e1
    3970:	0000b108 	.word	0x0000b108
    3974:	0000b12c 	.word	0x0000b12c
    3978:	0001e847 	.word	0x0001e847
    397c:	0000b160 	.word	0x0000b160
    3980:	0003d08f 	.word	0x0003d08f
    3984:	0007a11f 	.word	0x0007a11f
    3988:	000f423f 	.word	0x000f423f
    398c:	001e847f 	.word	0x001e847f
    3990:	003d08ff 	.word	0x003d08ff
    3994:	007a1200 	.word	0x007a1200
    3998:	00f42400 	.word	0x00f42400
    399c:	01e84800 	.word	0x01e84800
    39a0:	0000364d 	.word	0x0000364d
    39a4:	0bad0000 	.word	0x0bad0000
    39a8:	0000b196 	.word	0x0000b196
    39ac:	0000b1c2 	.word	0x0000b1c2

000039b0 <flash_nor_get_parameters>:
flash_nor_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nor_parameters;
}
    39b0:	4800      	ldr	r0, [pc, #0]	; (39b4 <flash_nor_get_parameters+0x4>)
    39b2:	4770      	bx	lr
    39b4:	0000a390 	.word	0x0000a390

000039b8 <spi_nor_erase>:
{
    39b8:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	return cfg->flash_size;
    39bc:	6843      	ldr	r3, [r0, #4]
	if ((addr < 0) || ((size + addr) > flash_size)) {
    39be:	1e0f      	subs	r7, r1, #0
	return cfg->flash_size;
    39c0:	f8d3 a010 	ldr.w	sl, [r3, #16]
{
    39c4:	4604      	mov	r4, r0
    39c6:	4616      	mov	r6, r2
	if ((addr < 0) || ((size + addr) > flash_size)) {
    39c8:	f2c0 8082 	blt.w	3ad0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x38>
    39cc:	18bb      	adds	r3, r7, r2
    39ce:	4553      	cmp	r3, sl
    39d0:	d87e      	bhi.n	3ad0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x38>
	if ((size % SPI_NOR_SECTOR_SIZE) != 0) {
    39d2:	ea47 0502 	orr.w	r5, r7, r2
    39d6:	f3c5 050b 	ubfx	r5, r5, #0, #12
    39da:	2d00      	cmp	r5, #0
    39dc:	d17b      	bne.n	3ad6 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x3e>
	acquire_device(dev);
    39de:	6900      	ldr	r0, [r0, #16]
    39e0:	f005 fc1f 	bl	9222 <acquire_device.isra.0>
	ret = spi_nor_write_protection_set(dev, false);
    39e4:	4629      	mov	r1, r5
    39e6:	4620      	mov	r0, r4
    39e8:	f005 fc68 	bl	92bc <spi_nor_write_protection_set>
    39ec:	4605      	mov	r5, r0
	while ((size > 0) && (ret == 0)) {
    39ee:	2e00      	cmp	r6, #0
    39f0:	d164      	bne.n	3abc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x24>
	int ret2 = spi_nor_write_protection_set(dev, true);
    39f2:	2101      	movs	r1, #1
    39f4:	4620      	mov	r0, r4
    39f6:	f005 fc61 	bl	92bc <spi_nor_write_protection_set>
	if (!ret) {
    39fa:	2d00      	cmp	r5, #0
    39fc:	d04a      	beq.n	3a94 <spi_nor_erase+0xdc>
    39fe:	e056      	b.n	3aae <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x16>
		if (size == flash_size) {
    3a00:	2200      	movs	r2, #0
    3a02:	4b36      	ldr	r3, [pc, #216]	; (3adc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x44>)
			const struct jesd216_erase_type *bet = NULL;
    3a04:	4690      	mov	r8, r2
				    && SPI_NOR_IS_ALIGNED(size, etp->exp)
    3a06:	ea47 0c06 	orr.w	ip, r7, r6
				if ((etp->exp != 0)
    3a0a:	7859      	ldrb	r1, [r3, #1]
    3a0c:	b161      	cbz	r1, 3a28 <spi_nor_erase+0x70>
				    && SPI_NOR_IS_ALIGNED(addr, etp->exp)
    3a0e:	fa0b f001 	lsl.w	r0, fp, r1
				    && SPI_NOR_IS_ALIGNED(size, etp->exp)
    3a12:	ea3c 0000 	bics.w	r0, ip, r0
    3a16:	d107      	bne.n	3a28 <spi_nor_erase+0x70>
				    && ((bet == NULL)
    3a18:	f1b8 0f00 	cmp.w	r8, #0
    3a1c:	d03c      	beq.n	3a98 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT>
					|| (etp->exp > bet->exp))) {
    3a1e:	f898 0001 	ldrb.w	r0, [r8, #1]
    3a22:	4288      	cmp	r0, r1
    3a24:	bf38      	it	cc
    3a26:	4698      	movcc	r8, r3
			for (uint8_t ei = 0; ei < JESD216_NUM_ERASE_TYPES; ++ei) {
    3a28:	3201      	adds	r2, #1
    3a2a:	2a04      	cmp	r2, #4
    3a2c:	f103 0302 	add.w	r3, r3, #2
    3a30:	d1eb      	bne.n	3a0a <spi_nor_erase+0x52>
			if (bet != NULL) {
    3a32:	f1b8 0f00 	cmp.w	r8, #0
    3a36:	d031      	beq.n	3a9c <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x4>
				spi_nor_cmd_addr_write(dev, bet->cmd, addr, NULL, 0);
    3a38:	2300      	movs	r3, #0
    3a3a:	f898 1000 	ldrb.w	r1, [r8]
    3a3e:	2281      	movs	r2, #129	; 0x81
    3a40:	e9cd 3300 	strd	r3, r3, [sp]
    3a44:	4620      	mov	r0, r4
    3a46:	463b      	mov	r3, r7
    3a48:	f005 fbf1 	bl	922e <spi_nor_access>
				addr += BIT(bet->exp);
    3a4c:	f898 2001 	ldrb.w	r2, [r8, #1]
    3a50:	2301      	movs	r3, #1
    3a52:	4093      	lsls	r3, r2
				size -= BIT(bet->exp);
    3a54:	1af6      	subs	r6, r6, r3
		spi_nor_wait_until_ready(dev);
    3a56:	4620      	mov	r0, r4
				addr += BIT(bet->exp);
    3a58:	441f      	add	r7, r3
		spi_nor_wait_until_ready(dev);
    3a5a:	f005 fc5f 	bl	931c <spi_nor_wait_until_ready.isra.0>
	while ((size > 0) && (ret == 0)) {
    3a5e:	2e00      	cmp	r6, #0
    3a60:	d0c7      	beq.n	39f2 <spi_nor_erase+0x3a>
		spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
    3a62:	e9cd 9900 	strd	r9, r9, [sp]
    3a66:	2300      	movs	r3, #0
    3a68:	2280      	movs	r2, #128	; 0x80
    3a6a:	2106      	movs	r1, #6
    3a6c:	4620      	mov	r0, r4
    3a6e:	f005 fbde 	bl	922e <spi_nor_access>
		if (size == flash_size) {
    3a72:	45b2      	cmp	sl, r6
    3a74:	d1c4      	bne.n	3a00 <spi_nor_erase+0x48>
			spi_nor_cmd_write(dev, SPI_NOR_CMD_CE);
    3a76:	21c7      	movs	r1, #199	; 0xc7
    3a78:	2300      	movs	r3, #0
    3a7a:	2280      	movs	r2, #128	; 0x80
    3a7c:	e9cd 9900 	strd	r9, r9, [sp]
    3a80:	4620      	mov	r0, r4
    3a82:	f005 fbd4 	bl	922e <spi_nor_access>
		spi_nor_wait_until_ready(dev);
    3a86:	4620      	mov	r0, r4
    3a88:	f005 fc48 	bl	931c <spi_nor_wait_until_ready.isra.0>
	int ret2 = spi_nor_write_protection_set(dev, true);
    3a8c:	2101      	movs	r1, #1
    3a8e:	4620      	mov	r0, r4
    3a90:	f005 fc14 	bl	92bc <spi_nor_write_protection_set>
					|| (etp->exp > bet->exp))) {
    3a94:	4605      	mov	r5, r0
    3a96:	e00a      	b.n	3aae <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x16>
    3a98:	4698      	mov	r8, r3
    3a9a:	e7c5      	b.n	3a28 <spi_nor_erase+0x70>
		spi_nor_wait_until_ready(dev);
    3a9c:	4620      	mov	r0, r4
    3a9e:	f005 fc3d 	bl	931c <spi_nor_wait_until_ready.isra.0>
	int ret2 = spi_nor_write_protection_set(dev, true);
    3aa2:	2101      	movs	r1, #1
    3aa4:	4620      	mov	r0, r4
    3aa6:	f005 fc09 	bl	92bc <spi_nor_write_protection_set>
				ret = -EINVAL;
    3aaa:	f06f 0515 	mvn.w	r5, #21
	release_device(dev);
    3aae:	6920      	ldr	r0, [r4, #16]
    3ab0:	f005 fbb5 	bl	921e <release_device.isra.0>
}
    3ab4:	4628      	mov	r0, r5
    3ab6:	b003      	add	sp, #12
    3ab8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	while ((size > 0) && (ret == 0)) {
    3abc:	b918      	cbnz	r0, 3ac6 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x2e>
		spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
    3abe:	4681      	mov	r9, r0
				    && SPI_NOR_IS_ALIGNED(addr, etp->exp)
    3ac0:	f04f 3bff 	mov.w	fp, #4294967295
    3ac4:	e7cd      	b.n	3a62 <spi_nor_erase+0xaa>
	int ret2 = spi_nor_write_protection_set(dev, true);
    3ac6:	2101      	movs	r1, #1
    3ac8:	4620      	mov	r0, r4
    3aca:	f005 fbf7 	bl	92bc <spi_nor_write_protection_set>
	if (!ret) {
    3ace:	e7ee      	b.n	3aae <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x16>
		return -ENODEV;
    3ad0:	f06f 0512 	mvn.w	r5, #18
    3ad4:	e7ee      	b.n	3ab4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1c>
		return -EINVAL;
    3ad6:	f06f 0515 	mvn.w	r5, #21
    3ada:	e7eb      	b.n	3ab4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1c>
    3adc:	0000b2d8 	.word	0x0000b2d8

00003ae0 <spi_nor_init>:
{
    3ae0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3ae4:	4604      	mov	r4, r0
    3ae6:	b086      	sub	sp, #24
		k_sem_init(&driver_data->sem, 1, K_SEM_MAX_LIMIT);
    3ae8:	6900      	ldr	r0, [r0, #16]
	return z_impl_k_sem_init(sem, initial_count, limit);
    3aea:	f04f 32ff 	mov.w	r2, #4294967295
    3aee:	2101      	movs	r1, #1
    3af0:	f006 f823 	bl	9b3a <z_impl_k_sem_init>
	const struct spi_nor_config *cfg = dev->config;
    3af4:	6867      	ldr	r7, [r4, #4]
 * @retval false if the SPI bus is not ready for use.
 */
static inline bool spi_is_ready(const struct spi_dt_spec *spec)
{
	/* Validate bus is ready */
	if (!device_is_ready(spec->bus)) {
    3af6:	6838      	ldr	r0, [r7, #0]
    3af8:	f005 ffa5 	bl	9a46 <z_device_is_ready>
    3afc:	b300      	cbz	r0, 3b40 <spi_nor_init+0x60>
		return false;
	}
	/* Validate CS gpio port is ready, if it is used */
	if (spec->config.cs &&
    3afe:	68fb      	ldr	r3, [r7, #12]
    3b00:	b9cb      	cbnz	r3, 3b36 <spi_nor_init+0x56>
	acquire_device(dev);
    3b02:	6920      	ldr	r0, [r4, #16]
    3b04:	f005 fb8d 	bl	9222 <acquire_device.isra.0>
	int ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDID, id, SPI_NOR_MAX_ID_LEN);
    3b08:	f04f 0803 	mov.w	r8, #3
    3b0c:	2300      	movs	r3, #0
    3b0e:	ae05      	add	r6, sp, #20
    3b10:	f8cd 8004 	str.w	r8, [sp, #4]
    3b14:	9600      	str	r6, [sp, #0]
    3b16:	461a      	mov	r2, r3
    3b18:	219f      	movs	r1, #159	; 0x9f
    3b1a:	4620      	mov	r0, r4
    3b1c:	f005 fb87 	bl	922e <spi_nor_access>
    3b20:	4605      	mov	r5, r0
	release_device(dev);
    3b22:	6920      	ldr	r0, [r4, #16]
    3b24:	f005 fb7b 	bl	921e <release_device.isra.0>
	if (rc != 0) {
    3b28:	b185      	cbz	r5, 3b4c <spi_nor_init+0x6c>
		LOG_ERR("JEDEC ID read failed: %d", rc);
    3b2a:	484e      	ldr	r0, [pc, #312]	; (3c64 <spi_nor_init+0x184>)
    3b2c:	462a      	mov	r2, r5
    3b2e:	2145      	movs	r1, #69	; 0x45
    3b30:	f005 f8cf 	bl	8cd2 <z_log_minimal_printk>
		return -ENODEV;
    3b34:	e004      	b.n	3b40 <spi_nor_init+0x60>
	    !device_is_ready(spec->config.cs->gpio.port)) {
    3b36:	6818      	ldr	r0, [r3, #0]
    3b38:	f005 ff85 	bl	9a46 <z_device_is_ready>
	if (spec->config.cs &&
    3b3c:	2800      	cmp	r0, #0
    3b3e:	d1e0      	bne.n	3b02 <spi_nor_init+0x22>
		return -ENODEV;
    3b40:	f06f 0812 	mvn.w	r8, #18
}
    3b44:	4640      	mov	r0, r8
    3b46:	b006      	add	sp, #24
    3b48:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (memcmp(jedec_id, cfg->jedec_id, sizeof(jedec_id)) != 0) {
    3b4c:	4642      	mov	r2, r8
    3b4e:	f107 011c 	add.w	r1, r7, #28
    3b52:	4630      	mov	r0, r6
    3b54:	f005 f95f 	bl	8e16 <memcmp>
    3b58:	4680      	mov	r8, r0
    3b5a:	b198      	cbz	r0, 3b84 <spi_nor_init+0xa4>
		LOG_ERR("Device id %02x %02x %02x does not match config %02x %02x %02x",
    3b5c:	7fbb      	ldrb	r3, [r7, #30]
    3b5e:	9303      	str	r3, [sp, #12]
    3b60:	7f7b      	ldrb	r3, [r7, #29]
    3b62:	9302      	str	r3, [sp, #8]
    3b64:	7f3b      	ldrb	r3, [r7, #28]
    3b66:	9301      	str	r3, [sp, #4]
    3b68:	f89d 3016 	ldrb.w	r3, [sp, #22]
    3b6c:	9300      	str	r3, [sp, #0]
    3b6e:	f89d 2014 	ldrb.w	r2, [sp, #20]
    3b72:	f89d 3015 	ldrb.w	r3, [sp, #21]
    3b76:	483c      	ldr	r0, [pc, #240]	; (3c68 <spi_nor_init+0x188>)
    3b78:	2145      	movs	r1, #69	; 0x45
    3b7a:	f005 f8aa 	bl	8cd2 <z_log_minimal_printk>
		return -EINVAL;
    3b7e:	f06f 0815 	mvn.w	r8, #21
    3b82:	e7df      	b.n	3b44 <spi_nor_init+0x64>
	if (cfg->has_lock != 0) {
    3b84:	f897 3020 	ldrb.w	r3, [r7, #32]
    3b88:	b393      	cbz	r3, 3bf0 <spi_nor_init+0x110>
		acquire_device(dev);
    3b8a:	6920      	ldr	r0, [r4, #16]
    3b8c:	f005 fb49 	bl	9222 <acquire_device.isra.0>
	int ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDSR, &reg, sizeof(reg));
    3b90:	f10d 0613 	add.w	r6, sp, #19
    3b94:	2301      	movs	r3, #1
    3b96:	9301      	str	r3, [sp, #4]
    3b98:	9600      	str	r6, [sp, #0]
    3b9a:	4643      	mov	r3, r8
    3b9c:	4642      	mov	r2, r8
    3b9e:	2105      	movs	r1, #5
    3ba0:	4620      	mov	r0, r4
    3ba2:	f005 fb44 	bl	922e <spi_nor_access>
	if (ret == 0) {
    3ba6:	1e05      	subs	r5, r0, #0
    3ba8:	d13f      	bne.n	3c2a <spi_nor_init+0x14a>
		ret = reg;
    3baa:	f89d 5013 	ldrb.w	r5, [sp, #19]
		if (rc > 0) {
    3bae:	b1e5      	cbz	r5, 3bea <spi_nor_init+0x10a>
			rc = spi_nor_wrsr(dev, rc & ~cfg->has_lock);
    3bb0:	f897 3020 	ldrb.w	r3, [r7, #32]
    3bb4:	ea25 0503 	bic.w	r5, r5, r3
	int ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
    3bb8:	2300      	movs	r3, #0
    3bba:	e9cd 3300 	strd	r3, r3, [sp]
    3bbe:	2280      	movs	r2, #128	; 0x80
    3bc0:	2106      	movs	r1, #6
    3bc2:	4620      	mov	r0, r4
    3bc4:	f88d 5013 	strb.w	r5, [sp, #19]
    3bc8:	f005 fb31 	bl	922e <spi_nor_access>
	if (ret == 0) {
    3bcc:	4605      	mov	r5, r0
    3bce:	bb68      	cbnz	r0, 3c2c <spi_nor_init+0x14c>
		ret = spi_nor_access(dev, SPI_NOR_CMD_WRSR, NOR_ACCESS_WRITE, 0, &sr,
    3bd0:	2101      	movs	r1, #1
    3bd2:	4603      	mov	r3, r0
    3bd4:	e9cd 6100 	strd	r6, r1, [sp]
    3bd8:	2280      	movs	r2, #128	; 0x80
    3bda:	4620      	mov	r0, r4
    3bdc:	f005 fb27 	bl	922e <spi_nor_access>
    3be0:	4605      	mov	r5, r0
		spi_nor_wait_until_ready(dev);
    3be2:	4620      	mov	r0, r4
    3be4:	f005 fb9a 	bl	931c <spi_nor_wait_until_ready.isra.0>
		if (rc != 0) {
    3be8:	bb05      	cbnz	r5, 3c2c <spi_nor_init+0x14c>
		release_device(dev);
    3bea:	6920      	ldr	r0, [r4, #16]
    3bec:	f005 fb17 	bl	921e <release_device.isra.0>
	if (cfg->enter_4byte_addr != 0) {
    3bf0:	7ffd      	ldrb	r5, [r7, #31]
    3bf2:	1e6b      	subs	r3, r5, #1
    3bf4:	b2db      	uxtb	r3, r3
    3bf6:	2bfd      	cmp	r3, #253	; 0xfd
    3bf8:	d8a4      	bhi.n	3b44 <spi_nor_init+0x64>
	if ((enter_4byte_addr & 0x03) == 0) {
    3bfa:	07aa      	lsls	r2, r5, #30
    3bfc:	d02f      	beq.n	3c5e <spi_nor_init+0x17e>
	acquire_device(dev);
    3bfe:	6920      	ldr	r0, [r4, #16]
    3c00:	f005 fb0f 	bl	9222 <acquire_device.isra.0>
	if ((enter_4byte_addr & 0x02) != 0) {
    3c04:	07ab      	lsls	r3, r5, #30
    3c06:	d415      	bmi.n	3c34 <spi_nor_init+0x154>
		ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_4BA);
    3c08:	2300      	movs	r3, #0
    3c0a:	e9cd 3300 	strd	r3, r3, [sp]
    3c0e:	2280      	movs	r2, #128	; 0x80
    3c10:	21b7      	movs	r1, #183	; 0xb7
    3c12:	4620      	mov	r0, r4
    3c14:	f005 fb0b 	bl	922e <spi_nor_access>
	if (ret == 0) {
    3c18:	4605      	mov	r5, r0
    3c1a:	b1b8      	cbz	r0, 3c4c <spi_nor_init+0x16c>
	release_device(dev);
    3c1c:	6920      	ldr	r0, [r4, #16]
    3c1e:	f005 fafe 	bl	921e <release_device.isra.0>
			LOG_ERR("Unable to enter 4-byte mode: %d\n", rc);
    3c22:	4812      	ldr	r0, [pc, #72]	; (3c6c <spi_nor_init+0x18c>)
    3c24:	462a      	mov	r2, r5
    3c26:	2145      	movs	r1, #69	; 0x45
    3c28:	e782      	b.n	3b30 <spi_nor_init+0x50>
		if (rc > 0) {
    3c2a:	dcc1      	bgt.n	3bb0 <spi_nor_init+0xd0>
			LOG_ERR("BP clear failed: %d\n", rc);
    3c2c:	4810      	ldr	r0, [pc, #64]	; (3c70 <spi_nor_init+0x190>)
    3c2e:	462a      	mov	r2, r5
    3c30:	2145      	movs	r1, #69	; 0x45
    3c32:	e77d      	b.n	3b30 <spi_nor_init+0x50>
		ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
    3c34:	2300      	movs	r3, #0
    3c36:	e9cd 3300 	strd	r3, r3, [sp]
    3c3a:	2280      	movs	r2, #128	; 0x80
    3c3c:	2106      	movs	r1, #6
    3c3e:	4620      	mov	r0, r4
    3c40:	f005 faf5 	bl	922e <spi_nor_access>
	if (ret == 0) {
    3c44:	4605      	mov	r5, r0
    3c46:	2800      	cmp	r0, #0
    3c48:	d0de      	beq.n	3c08 <spi_nor_init+0x128>
    3c4a:	e7e7      	b.n	3c1c <spi_nor_init+0x13c>
		struct spi_nor_data *data = dev->data;
    3c4c:	6922      	ldr	r2, [r4, #16]
		data->flag_access_32bit = true;
    3c4e:	7d13      	ldrb	r3, [r2, #20]
    3c50:	f043 0301 	orr.w	r3, r3, #1
    3c54:	7513      	strb	r3, [r2, #20]
	release_device(dev);
    3c56:	6920      	ldr	r0, [r4, #16]
    3c58:	f005 fae1 	bl	921e <release_device.isra.0>
		if (rc != 0) {
    3c5c:	e772      	b.n	3b44 <spi_nor_init+0x64>
		return -ENOTSUP;
    3c5e:	f06f 0585 	mvn.w	r5, #133	; 0x85
    3c62:	e7de      	b.n	3c22 <spi_nor_init+0x142>
    3c64:	0000b222 	.word	0x0000b222
    3c68:	0000b240 	.word	0x0000b240
    3c6c:	0000b29d 	.word	0x0000b29d
    3c70:	0000b283 	.word	0x0000b283

00003c74 <flash_nrf_pages_layout>:

static void flash_nrf_pages_layout(const struct device *dev,
				     const struct flash_pages_layout **layout,
				     size_t *layout_size)
{
	*layout = &dev_layout;
    3c74:	4b02      	ldr	r3, [pc, #8]	; (3c80 <flash_nrf_pages_layout+0xc>)
    3c76:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    3c78:	2301      	movs	r3, #1
    3c7a:	6013      	str	r3, [r2, #0]
}
    3c7c:	4770      	bx	lr
    3c7e:	bf00      	nop
    3c80:	20001e84 	.word	0x20001e84

00003c84 <flash_nrf_get_parameters>:
flash_nrf_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nrf_parameters;
}
    3c84:	4800      	ldr	r0, [pc, #0]	; (3c88 <flash_nrf_get_parameters+0x4>)
    3c86:	4770      	bx	lr
    3c88:	0000a3ac 	.word	0x0000a3ac

00003c8c <flash_nrf_read>:
{
    3c8c:	b570      	push	{r4, r5, r6, lr}
    3c8e:	460d      	mov	r5, r1
	if (is_regular_addr_valid(addr, len)) {
    3c90:	4628      	mov	r0, r5
    3c92:	4619      	mov	r1, r3
{
    3c94:	4616      	mov	r6, r2
    3c96:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    3c98:	f005 fbb9 	bl	940e <is_regular_addr_valid>
    3c9c:	b940      	cbnz	r0, 3cb0 <flash_nrf_read+0x24>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    3c9e:	4808      	ldr	r0, [pc, #32]	; (3cc0 <flash_nrf_read+0x34>)
    3ca0:	4623      	mov	r3, r4
    3ca2:	462a      	mov	r2, r5
    3ca4:	2145      	movs	r1, #69	; 0x45
    3ca6:	f005 f814 	bl	8cd2 <z_log_minimal_printk>
    3caa:	f06f 0015 	mvn.w	r0, #21
}
    3cae:	bd70      	pop	{r4, r5, r6, pc}
	if (!len) {
    3cb0:	b124      	cbz	r4, 3cbc <flash_nrf_read+0x30>
	memcpy(data, (void *)addr, len);
    3cb2:	4622      	mov	r2, r4
    3cb4:	4629      	mov	r1, r5
    3cb6:	4630      	mov	r0, r6
    3cb8:	f005 f8bd 	bl	8e36 <memcpy>
		return 0;
    3cbc:	2000      	movs	r0, #0
    3cbe:	e7f6      	b.n	3cae <flash_nrf_read+0x22>
    3cc0:	0000b2e0 	.word	0x0000b2e0

00003cc4 <nrf_flash_init>:
	.page_layout = flash_nrf_pages_layout,
#endif
};

static int nrf_flash_init(const struct device *dev)
{
    3cc4:	b510      	push	{r4, lr}
    3cc6:	2201      	movs	r2, #1
    3cc8:	4611      	mov	r1, r2
    3cca:	4806      	ldr	r0, [pc, #24]	; (3ce4 <nrf_flash_init+0x20>)
#ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
	nrf_flash_sync_init();
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

#if defined(CONFIG_FLASH_PAGE_LAYOUT)
	dev_layout.pages_count = nrfx_nvmc_flash_page_count_get();
    3ccc:	4c06      	ldr	r4, [pc, #24]	; (3ce8 <nrf_flash_init+0x24>)
    3cce:	f005 ff34 	bl	9b3a <z_impl_k_sem_init>
    3cd2:	f005 fe17 	bl	9904 <nrfx_nvmc_flash_page_count_get>
    3cd6:	6020      	str	r0, [r4, #0]
	dev_layout.pages_size = nrfx_nvmc_flash_page_size_get();
    3cd8:	f005 fe10 	bl	98fc <nrfx_nvmc_flash_page_size_get>
    3cdc:	6060      	str	r0, [r4, #4]
#endif

	return 0;
}
    3cde:	2000      	movs	r0, #0
    3ce0:	bd10      	pop	{r4, pc}
    3ce2:	bf00      	nop
    3ce4:	20001e8c 	.word	0x20001e8c
    3ce8:	20001e84 	.word	0x20001e84

00003cec <restore_pofwarn.part.0>:
    uint32_t pofcon = p_reg->POFCON;
    3cec:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3cf0:	f8d2 1510 	ldr.w	r1, [r2, #1296]	; 0x510
    uint32_t pofcon = p_reg->POFCON;
    3cf4:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
        (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
    3cf8:	f001 011e 	and.w	r1, r1, #30
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    3cfc:	f023 031f 	bic.w	r3, r3, #31
    3d00:	430b      	orrs	r3, r1
    pofcon |=
    3d02:	f043 0301 	orr.w	r3, r3, #1
    p_reg->POFCON = pofcon;
    3d06:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510

	if (pofcon_enabled) {
		pof_thr = nrf_power_pofcon_get(NRF_POWER, NULL);

		nrf_power_pofcon_set(NRF_POWER, true, pof_thr);
		pofcon_enabled = false;
    3d0a:	4b02      	ldr	r3, [pc, #8]	; (3d14 <restore_pofwarn.part.0+0x28>)
    3d0c:	2200      	movs	r2, #0
    3d0e:	701a      	strb	r2, [r3, #0]
	}
}
    3d10:	4770      	bx	lr
    3d12:	bf00      	nop
    3d14:	200022c2 	.word	0x200022c2

00003d18 <suspend_pofwarn>:
    #else
        #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    3d18:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    3d1c:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    3d20:	2b08      	cmp	r3, #8
    3d22:	d120      	bne.n	3d66 <suspend_pofwarn+0x4e>
    uint32_t pofcon = p_reg->POFCON;
    3d24:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3d28:	f8d2 1510 	ldr.w	r1, [r2, #1296]	; 0x510
	if (enabled) {
    3d2c:	07cb      	lsls	r3, r1, #31
    3d2e:	d51a      	bpl.n	3d66 <suspend_pofwarn+0x4e>
    uint32_t pofcon = p_reg->POFCON;
    3d30:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
        (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
    3d34:	f001 011e 	and.w	r1, r1, #30
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    3d38:	f023 031f 	bic.w	r3, r3, #31
    pofcon |=
    3d3c:	430b      	orrs	r3, r1
    p_reg->POFCON = pofcon;
    3d3e:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3d42:	f8d2 3108 	ldr.w	r3, [r2, #264]	; 0x108
		if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_POFWARN)) {
    3d46:	b15b      	cbz	r3, 3d60 <suspend_pofwarn+0x48>
    uint32_t pofcon = p_reg->POFCON;
    3d48:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    3d4c:	f023 031f 	bic.w	r3, r3, #31
    3d50:	430b      	orrs	r3, r1
    pofcon |=
    3d52:	f043 0301 	orr.w	r3, r3, #1
    p_reg->POFCON = pofcon;
    3d56:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			return -ECANCELED;
    3d5a:	f06f 008b 	mvn.w	r0, #139	; 0x8b
}
    3d5e:	4770      	bx	lr
		pofcon_enabled = enabled;
    3d60:	4b02      	ldr	r3, [pc, #8]	; (3d6c <suspend_pofwarn+0x54>)
    3d62:	2201      	movs	r2, #1
    3d64:	701a      	strb	r2, [r3, #0]
		return 0;
    3d66:	2000      	movs	r0, #0
}
    3d68:	4770      	bx	lr
    3d6a:	bf00      	nop
    3d6c:	200022c2 	.word	0x200022c2

00003d70 <flash_nrf_erase>:
{
    3d70:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3d74:	460f      	mov	r7, r1
    3d76:	4615      	mov	r5, r2
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    3d78:	f005 fdc0 	bl	98fc <nrfx_nvmc_flash_page_size_get>
	if (is_regular_addr_valid(addr, size)) {
    3d7c:	4629      	mov	r1, r5
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    3d7e:	4606      	mov	r6, r0
	if (is_regular_addr_valid(addr, size)) {
    3d80:	4638      	mov	r0, r7
    3d82:	f005 fb44 	bl	940e <is_regular_addr_valid>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    3d86:	46b8      	mov	r8, r7
	if (is_regular_addr_valid(addr, size)) {
    3d88:	b3b0      	cbz	r0, 3df8 <flash_nrf_erase+0x88>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    3d8a:	fbb7 f3f6 	udiv	r3, r7, r6
    3d8e:	fb06 7313 	mls	r3, r6, r3, r7
    3d92:	b923      	cbnz	r3, 3d9e <flash_nrf_erase+0x2e>
    3d94:	fbb5 f4f6 	udiv	r4, r5, r6
    3d98:	fb06 5414 	mls	r4, r6, r4, r5
    3d9c:	b144      	cbz	r4, 3db0 <flash_nrf_erase+0x40>
			LOG_ERR("unaligned address: 0x%08lx:%zu",
    3d9e:	4819      	ldr	r0, [pc, #100]	; (3e04 <flash_nrf_erase+0x94>)
    3da0:	462b      	mov	r3, r5
    3da2:	463a      	mov	r2, r7
    3da4:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("invalid address: 0x%08lx:%zu",
    3da6:	f004 ff94 	bl	8cd2 <z_log_minimal_printk>
			return -EINVAL;
    3daa:	f06f 0415 	mvn.w	r4, #21
    3dae:	e01d      	b.n	3dec <flash_nrf_erase+0x7c>
		if (!n_pages) {
    3db0:	42ae      	cmp	r6, r5
    3db2:	d81b      	bhi.n	3dec <flash_nrf_erase+0x7c>
	return z_impl_k_sem_take(sem, timeout);
    3db4:	f04f 32ff 	mov.w	r2, #4294967295
    3db8:	f04f 33ff 	mov.w	r3, #4294967295
    3dbc:	4812      	ldr	r0, [pc, #72]	; (3e08 <flash_nrf_erase+0x98>)
	if (pofcon_enabled) {
    3dbe:	4f13      	ldr	r7, [pc, #76]	; (3e0c <flash_nrf_erase+0x9c>)
    3dc0:	f002 fa54 	bl	626c <z_impl_k_sem_take>
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    3dc4:	f005 fd9a 	bl	98fc <nrfx_nvmc_flash_page_size_get>
    3dc8:	4606      	mov	r6, r0
		if (SUSPEND_POFWARN()) {
    3dca:	f7ff ffa5 	bl	3d18 <suspend_pofwarn>
    3dce:	4604      	mov	r4, r0
    3dd0:	b978      	cbnz	r0, 3df2 <flash_nrf_erase+0x82>
		(void)nrfx_nvmc_page_erase(e_ctx->flash_addr);
    3dd2:	4640      	mov	r0, r8
    3dd4:	f001 fb4e 	bl	5474 <nrfx_nvmc_page_erase>
	if (pofcon_enabled) {
    3dd8:	783b      	ldrb	r3, [r7, #0]
    3dda:	b10b      	cbz	r3, 3de0 <flash_nrf_erase+0x70>
    3ddc:	f7ff ff86 	bl	3cec <restore_pofwarn.part.0>
	} while (e_ctx->len > 0);
    3de0:	1bad      	subs	r5, r5, r6
    3de2:	44b0      	add	r8, r6
    3de4:	d1f1      	bne.n	3dca <flash_nrf_erase+0x5a>
	z_impl_k_sem_give(sem);
    3de6:	4808      	ldr	r0, [pc, #32]	; (3e08 <flash_nrf_erase+0x98>)
    3de8:	f002 fa20 	bl	622c <z_impl_k_sem_give>
}
    3dec:	4620      	mov	r0, r4
    3dee:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			return -ECANCELED;
    3df2:	f06f 048b 	mvn.w	r4, #139	; 0x8b
    3df6:	e7f6      	b.n	3de6 <flash_nrf_erase+0x76>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    3df8:	4805      	ldr	r0, [pc, #20]	; (3e10 <flash_nrf_erase+0xa0>)
    3dfa:	462b      	mov	r3, r5
    3dfc:	463a      	mov	r2, r7
    3dfe:	2145      	movs	r1, #69	; 0x45
    3e00:	e7d1      	b.n	3da6 <flash_nrf_erase+0x36>
    3e02:	bf00      	nop
    3e04:	0000b302 	.word	0x0000b302
    3e08:	20001e8c 	.word	0x20001e8c
    3e0c:	200022c2 	.word	0x200022c2
    3e10:	0000b2e0 	.word	0x0000b2e0

00003e14 <flash_nrf_write>:
{
    3e14:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    3e18:	460e      	mov	r6, r1
	if (is_regular_addr_valid(addr, len)) {
    3e1a:	4630      	mov	r0, r6
    3e1c:	4619      	mov	r1, r3
{
    3e1e:	4617      	mov	r7, r2
    3e20:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    3e22:	f005 faf4 	bl	940e <is_regular_addr_valid>
    3e26:	b950      	cbnz	r0, 3e3e <flash_nrf_write+0x2a>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    3e28:	4820      	ldr	r0, [pc, #128]	; (3eac <flash_nrf_write+0x98>)
    3e2a:	4623      	mov	r3, r4
    3e2c:	4632      	mov	r2, r6
    3e2e:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    3e30:	f004 ff4f 	bl	8cd2 <z_log_minimal_printk>
		return -EINVAL;
    3e34:	f06f 0415 	mvn.w	r4, #21
}
    3e38:	4620      	mov	r0, r4
    3e3a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	if (!is_aligned_32(addr) || (len % sizeof(uint32_t))) {
    3e3e:	ea46 0504 	orr.w	r5, r6, r4
    3e42:	f015 0503 	ands.w	r5, r5, #3
    3e46:	d004      	beq.n	3e52 <flash_nrf_write+0x3e>
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    3e48:	4819      	ldr	r0, [pc, #100]	; (3eb0 <flash_nrf_write+0x9c>)
    3e4a:	4623      	mov	r3, r4
    3e4c:	4632      	mov	r2, r6
    3e4e:	2145      	movs	r1, #69	; 0x45
    3e50:	e7ee      	b.n	3e30 <flash_nrf_write+0x1c>
	if (!len) {
    3e52:	2c00      	cmp	r4, #0
    3e54:	d0f0      	beq.n	3e38 <flash_nrf_write+0x24>
	return z_impl_k_sem_take(sem, timeout);
    3e56:	4817      	ldr	r0, [pc, #92]	; (3eb4 <flash_nrf_write+0xa0>)
	if (pofcon_enabled) {
    3e58:	f8df 9060 	ldr.w	r9, [pc, #96]	; 3ebc <flash_nrf_write+0xa8>
    3e5c:	f04f 32ff 	mov.w	r2, #4294967295
    3e60:	f04f 33ff 	mov.w	r3, #4294967295
    3e64:	f002 fa02 	bl	626c <z_impl_k_sem_take>
static int write_op(void *context)
    3e68:	f024 0403 	bic.w	r4, r4, #3
	while (w_ctx->len >= sizeof(uint32_t)) {
    3e6c:	42a5      	cmp	r5, r4
    3e6e:	eb05 0806 	add.w	r8, r5, r6
    3e72:	d109      	bne.n	3e88 <flash_nrf_write+0x74>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
{
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    3e74:	4a10      	ldr	r2, [pc, #64]	; (3eb8 <flash_nrf_write+0xa4>)
    3e76:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
	while (!nrfx_nvmc_write_done_check()) {
    3e7a:	07db      	lsls	r3, r3, #31
    3e7c:	d5fb      	bpl.n	3e76 <flash_nrf_write+0x62>
	return FLASH_OP_DONE;
    3e7e:	2400      	movs	r4, #0
	z_impl_k_sem_give(sem);
    3e80:	480c      	ldr	r0, [pc, #48]	; (3eb4 <flash_nrf_write+0xa0>)
    3e82:	f002 f9d3 	bl	622c <z_impl_k_sem_give>
}
    3e86:	e7d7      	b.n	3e38 <flash_nrf_write+0x24>
		if (SUSPEND_POFWARN()) {
    3e88:	f7ff ff46 	bl	3d18 <suspend_pofwarn>
    3e8c:	b950      	cbnz	r0, 3ea4 <flash_nrf_write+0x90>
		nrfx_nvmc_word_write(w_ctx->flash_addr,
    3e8e:	5979      	ldr	r1, [r7, r5]
    3e90:	4640      	mov	r0, r8
    3e92:	f001 fb0f 	bl	54b4 <nrfx_nvmc_word_write>
	if (pofcon_enabled) {
    3e96:	f899 3000 	ldrb.w	r3, [r9]
    3e9a:	b10b      	cbz	r3, 3ea0 <flash_nrf_write+0x8c>
    3e9c:	f7ff ff26 	bl	3cec <restore_pofwarn.part.0>
	w_ctx->len -= shift;
    3ea0:	3504      	adds	r5, #4
}
    3ea2:	e7e3      	b.n	3e6c <flash_nrf_write+0x58>
			return -ECANCELED;
    3ea4:	f06f 048b 	mvn.w	r4, #139	; 0x8b
    3ea8:	e7ea      	b.n	3e80 <flash_nrf_write+0x6c>
    3eaa:	bf00      	nop
    3eac:	0000b2e0 	.word	0x0000b2e0
    3eb0:	0000b326 	.word	0x0000b326
    3eb4:	20001e8c 	.word	0x20001e8c
    3eb8:	4001e000 	.word	0x4001e000
    3ebc:	200022c2 	.word	0x200022c2

00003ec0 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    3ec0:	b5f0      	push	{r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    3ec2:	794b      	ldrb	r3, [r1, #5]
    3ec4:	2b01      	cmp	r3, #1
    3ec6:	d026      	beq.n	3f16 <uarte_nrfx_configure+0x56>
    3ec8:	2b03      	cmp	r3, #3
    3eca:	d121      	bne.n	3f10 <uarte_nrfx_configure+0x50>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    3ecc:	2510      	movs	r5, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    3ece:	798b      	ldrb	r3, [r1, #6]
    3ed0:	2b03      	cmp	r3, #3
    3ed2:	d11d      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    3ed4:	79ce      	ldrb	r6, [r1, #7]
    3ed6:	b10e      	cbz	r6, 3edc <uarte_nrfx_configure+0x1c>
    3ed8:	2e01      	cmp	r6, #1
    3eda:	d119      	bne.n	3f10 <uarte_nrfx_configure+0x50>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    3edc:	790a      	ldrb	r2, [r1, #4]
    3ede:	b112      	cbz	r2, 3ee6 <uarte_nrfx_configure+0x26>
    3ee0:	2a02      	cmp	r2, #2
    3ee2:	d115      	bne.n	3f10 <uarte_nrfx_configure+0x50>
	case UART_CFG_PARITY_NONE:
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
		break;
	case UART_CFG_PARITY_EVEN:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    3ee4:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    3ee6:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    3ee8:	6844      	ldr	r4, [r0, #4]
	switch (baudrate) {
    3eea:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    3eee:	6827      	ldr	r7, [r4, #0]
	switch (baudrate) {
    3ef0:	d067      	beq.n	3fc2 <uarte_nrfx_configure+0x102>
    3ef2:	d82d      	bhi.n	3f50 <uarte_nrfx_configure+0x90>
    3ef4:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    3ef8:	d066      	beq.n	3fc8 <uarte_nrfx_configure+0x108>
    3efa:	d816      	bhi.n	3f2a <uarte_nrfx_configure+0x6a>
    3efc:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    3f00:	d064      	beq.n	3fcc <uarte_nrfx_configure+0x10c>
    3f02:	d80a      	bhi.n	3f1a <uarte_nrfx_configure+0x5a>
    3f04:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    3f08:	d063      	beq.n	3fd2 <uarte_nrfx_configure+0x112>
    3f0a:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    3f0e:	d063      	beq.n	3fd8 <uarte_nrfx_configure+0x118>
		return -ENOTSUP;
    3f10:	f06f 0085 	mvn.w	r0, #133	; 0x85
    3f14:	e054      	b.n	3fc0 <uarte_nrfx_configure+0x100>
	switch (cfg->stop_bits) {
    3f16:	2500      	movs	r5, #0
    3f18:	e7d9      	b.n	3ece <uarte_nrfx_configure+0xe>
	switch (baudrate) {
    3f1a:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    3f1e:	d05e      	beq.n	3fde <uarte_nrfx_configure+0x11e>
    3f20:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    3f24:	d1f4      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    3f26:	4b38      	ldr	r3, [pc, #224]	; (4008 <uarte_nrfx_configure+0x148>)
    3f28:	e03c      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3f2a:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    3f2e:	d059      	beq.n	3fe4 <uarte_nrfx_configure+0x124>
    3f30:	d807      	bhi.n	3f42 <uarte_nrfx_configure+0x82>
    3f32:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    3f36:	d057      	beq.n	3fe8 <uarte_nrfx_configure+0x128>
    3f38:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    3f3c:	d1e8      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    3f3e:	4b33      	ldr	r3, [pc, #204]	; (400c <uarte_nrfx_configure+0x14c>)
    3f40:	e030      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3f42:	f647 2412 	movw	r4, #31250	; 0x7a12
    3f46:	42a3      	cmp	r3, r4
    3f48:	d1e2      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    3f4a:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    3f4e:	e029      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3f50:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    3f54:	d04a      	beq.n	3fec <uarte_nrfx_configure+0x12c>
    3f56:	d813      	bhi.n	3f80 <uarte_nrfx_configure+0xc0>
    3f58:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    3f5c:	d049      	beq.n	3ff2 <uarte_nrfx_configure+0x132>
    3f5e:	d809      	bhi.n	3f74 <uarte_nrfx_configure+0xb4>
    3f60:	f64d 24c0 	movw	r4, #56000	; 0xdac0
    3f64:	42a3      	cmp	r3, r4
    3f66:	d046      	beq.n	3ff6 <uarte_nrfx_configure+0x136>
    3f68:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    3f6c:	d1d0      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    3f6e:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    3f72:	e017      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3f74:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    3f78:	d1ca      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    3f7a:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    3f7e:	e011      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3f80:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    3f84:	d03a      	beq.n	3ffc <uarte_nrfx_configure+0x13c>
    3f86:	d808      	bhi.n	3f9a <uarte_nrfx_configure+0xda>
    3f88:	4c21      	ldr	r4, [pc, #132]	; (4010 <uarte_nrfx_configure+0x150>)
    3f8a:	42a3      	cmp	r3, r4
    3f8c:	d039      	beq.n	4002 <uarte_nrfx_configure+0x142>
    3f8e:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    3f92:	d1bd      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    3f94:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    3f98:	e004      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3f9a:	4c1e      	ldr	r4, [pc, #120]	; (4014 <uarte_nrfx_configure+0x154>)
    3f9c:	42a3      	cmp	r3, r4
    3f9e:	d1b7      	bne.n	3f10 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    3fa0:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    3fa4:	6904      	ldr	r4, [r0, #16]
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    3fa6:	f8c7 3524 	str.w	r3, [r7, #1316]	; 0x524
	return config->uarte_regs;
    3faa:	6843      	ldr	r3, [r0, #4]
                    | (uint32_t)p_cfg->hwfc;
    3fac:	4335      	orrs	r5, r6
    3fae:	681b      	ldr	r3, [r3, #0]
    3fb0:	432a      	orrs	r2, r5
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    3fb2:	f8c3 256c 	str.w	r2, [r3, #1388]	; 0x56c
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	data->uart_config = *cfg;
    3fb6:	c903      	ldmia	r1, {r0, r1}
    3fb8:	1d23      	adds	r3, r4, #4
    3fba:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    3fbe:	2000      	movs	r0, #0
}
    3fc0:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    3fc2:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    3fc6:	e7ed      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    3fc8:	4b13      	ldr	r3, [pc, #76]	; (4018 <uarte_nrfx_configure+0x158>)
    3fca:	e7eb      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    3fcc:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    3fd0:	e7e8      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = 0x00014000;
    3fd2:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    3fd6:	e7e5      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    3fd8:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    3fdc:	e7e2      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    3fde:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    3fe2:	e7df      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    3fe4:	4b0d      	ldr	r3, [pc, #52]	; (401c <uarte_nrfx_configure+0x15c>)
    3fe6:	e7dd      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    3fe8:	4b0d      	ldr	r3, [pc, #52]	; (4020 <uarte_nrfx_configure+0x160>)
    3fea:	e7db      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    3fec:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    3ff0:	e7d8      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    3ff2:	4b0c      	ldr	r3, [pc, #48]	; (4024 <uarte_nrfx_configure+0x164>)
    3ff4:	e7d6      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    3ff6:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    3ffa:	e7d3      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    3ffc:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    4000:	e7d0      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    4002:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    4006:	e7cd      	b.n	3fa4 <uarte_nrfx_configure+0xe4>
    4008:	0013b000 	.word	0x0013b000
    400c:	004ea000 	.word	0x004ea000
    4010:	0003d090 	.word	0x0003d090
    4014:	000f4240 	.word	0x000f4240
    4018:	00275000 	.word	0x00275000
    401c:	0075c000 	.word	0x0075c000
    4020:	003af000 	.word	0x003af000
    4024:	013a9000 	.word	0x013a9000

00004028 <uarte_instance_init.constprop.0>:
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));

	return 0;
}

static int uarte_instance_init(const struct device *dev,
    4028:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
	const struct uarte_nrfx_config *config = dev->config;
    402c:	6847      	ldr	r7, [r0, #4]
			       uint8_t interrupts_active)
{
	int err;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = dev->data;
    402e:	6906      	ldr	r6, [r0, #16]
	return config->uarte_regs;
    4030:	683c      	ldr	r4, [r7, #0]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    4032:	2100      	movs	r1, #0
    4034:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
	const struct uarte_nrfx_config *cfg = dev->config;

	nrf_uarte_disable(uarte);

	data->dev = dev;
    4038:	6030      	str	r0, [r6, #0]

#ifdef CONFIG_PINCTRL
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    403a:	f8d7 900c 	ldr.w	r9, [r7, #12]
static int uarte_instance_init(const struct device *dev,
    403e:	4680      	mov	r8, r0
	ret = pinctrl_lookup_state(config, id, &state);
    4040:	aa01      	add	r2, sp, #4
    4042:	4648      	mov	r0, r9
    4044:	f005 fae2 	bl	960c <pinctrl_lookup_state>
	if (ret < 0) {
    4048:	1e05      	subs	r5, r0, #0
    404a:	db1e      	blt.n	408a <uarte_instance_init.constprop.0+0x62>
	return pinctrl_apply_state_direct(config, state);
    404c:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    404e:	f8d9 2000 	ldr.w	r2, [r9]
    4052:	7919      	ldrb	r1, [r3, #4]
    4054:	6818      	ldr	r0, [r3, #0]
    4056:	f000 fb0b 	bl	4670 <pinctrl_configure_pins>
	if (err < 0) {
    405a:	1e05      	subs	r5, r0, #0
    405c:	db15      	blt.n	408a <uarte_instance_init.constprop.0+0x62>
	}
#else
	uarte_nrfx_pins_configure(dev, false);
#endif /* CONFIG_PINCTRL */

	err = uarte_nrfx_configure(dev, &data->uart_config);
    405e:	1d31      	adds	r1, r6, #4
    4060:	4640      	mov	r0, r8
    4062:	f7ff ff2d 	bl	3ec0 <uarte_nrfx_configure>
	if (err) {
    4066:	4605      	mov	r5, r0
    4068:	b978      	cbnz	r0, 408a <uarte_instance_init.constprop.0+0x62>
		return err;
	}

	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    406a:	687b      	ldr	r3, [r7, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    406c:	0799      	lsls	r1, r3, #30
    406e:	d524      	bpl.n	40ba <uarte_instance_init.constprop.0+0x92>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    4070:	f106 0018 	add.w	r0, r6, #24
    4074:	f001 fa2c 	bl	54d0 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    4078:	4b24      	ldr	r3, [pc, #144]	; (410c <uarte_instance_init.constprop.0+0xe4>)
    407a:	4298      	cmp	r0, r3
    407c:	d009      	beq.n	4092 <uarte_instance_init.constprop.0+0x6a>
		LOG_ERR("Failed to allocate PPI Channel");
    407e:	4824      	ldr	r0, [pc, #144]	; (4110 <uarte_instance_init.constprop.0+0xe8>)
    4080:	2145      	movs	r1, #69	; 0x45
    4082:	f004 fe26 	bl	8cd2 <z_log_minimal_printk>
		return -EIO;
    4086:	f06f 0504 	mvn.w	r5, #4

	/* switch off transmitter to save an energy */
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);

	return 0;
}
    408a:	4628      	mov	r0, r5
    408c:	b003      	add	sp, #12
    408e:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    4092:	7e33      	ldrb	r3, [r6, #24]
    4094:	00db      	lsls	r3, r3, #3
    4096:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    409a:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    409e:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    40a2:	f504 7190 	add.w	r1, r4, #288	; 0x120
    40a6:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    40aa:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    40ae:	7e32      	ldrb	r2, [r6, #24]
    40b0:	2301      	movs	r3, #1
    40b2:	4093      	lsls	r3, r2
    p_reg->CHENSET = mask;
    40b4:	4a17      	ldr	r2, [pc, #92]	; (4114 <uarte_instance_init.constprop.0+0xec>)
    40b6:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    40ba:	2308      	movs	r3, #8
    40bc:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    40c0:	7a3b      	ldrb	r3, [r7, #8]
    40c2:	b953      	cbnz	r3, 40da <uarte_instance_init.constprop.0+0xb2>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    40c4:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    40c8:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    40cc:	6973      	ldr	r3, [r6, #20]
    40ce:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    40d2:	2301      	movs	r3, #1
    40d4:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    40d8:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    40da:	687b      	ldr	r3, [r7, #4]
    40dc:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    40de:	bf5c      	itt	pl
    40e0:	f44f 7380 	movpl.w	r3, #256	; 0x100
    40e4:	f8c4 3304 	strpl.w	r3, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    40e8:	687b      	ldr	r3, [r7, #4]
    40ea:	06db      	lsls	r3, r3, #27
    40ec:	bf44      	itt	mi
    40ee:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    40f2:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    40f6:	6933      	ldr	r3, [r6, #16]
    40f8:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    40fc:	2300      	movs	r3, #0
    40fe:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4102:	2301      	movs	r3, #1
    4104:	60a3      	str	r3, [r4, #8]
    4106:	60e3      	str	r3, [r4, #12]
	return 0;
    4108:	e7bf      	b.n	408a <uarte_instance_init.constprop.0+0x62>
    410a:	bf00      	nop
    410c:	0bad0000 	.word	0x0bad0000
    4110:	0000b36d 	.word	0x0000b36d
    4114:	4001f000 	.word	0x4001f000

00004118 <uarte_nrfx_poll_out>:
{
    4118:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    411a:	4604      	mov	r4, r0
	struct uarte_nrfx_data *data = dev->data;
    411c:	6907      	ldr	r7, [r0, #16]
{
    411e:	460d      	mov	r5, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    4120:	f005 fced 	bl	9afe <k_is_in_isr>
    4124:	b9b0      	cbnz	r0, 4154 <uarte_nrfx_poll_out+0x3c>
	return !z_sys_post_kernel;
    4126:	4b2e      	ldr	r3, [pc, #184]	; (41e0 <uarte_nrfx_poll_out+0xc8>)
    4128:	781b      	ldrb	r3, [r3, #0]
    412a:	b19b      	cbz	r3, 4154 <uarte_nrfx_poll_out+0x3c>
{
    412c:	2664      	movs	r6, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    412e:	6860      	ldr	r0, [r4, #4]
    4130:	f005 fa04 	bl	953c <is_tx_ready.isra.0>
    4134:	bb00      	cbnz	r0, 4178 <uarte_nrfx_poll_out+0x60>
    4136:	2001      	movs	r0, #1
    4138:	f005 fb35 	bl	97a6 <nrfx_busy_wait>
    413c:	3e01      	subs	r6, #1
    413e:	d1f6      	bne.n	412e <uarte_nrfx_poll_out+0x16>
	return z_impl_k_sleep(timeout);
    4140:	2100      	movs	r1, #0
    4142:	2021      	movs	r0, #33	; 0x21
    4144:	f002 fb82 	bl	684c <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    4148:	e7f0      	b.n	412c <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    414a:	f386 8811 	msr	BASEPRI, r6
    414e:	f3bf 8f6f 	isb	sy
}
    4152:	e7f5      	b.n	4140 <uarte_nrfx_poll_out+0x28>
	__asm__ volatile(
    4154:	f04f 0320 	mov.w	r3, #32
    4158:	f3ef 8611 	mrs	r6, BASEPRI
    415c:	f383 8812 	msr	BASEPRI_MAX, r3
    4160:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    4164:	6860      	ldr	r0, [r4, #4]
    4166:	4631      	mov	r1, r6
    4168:	f005 f9e8 	bl	953c <is_tx_ready.isra.0>
    416c:	b990      	cbnz	r0, 4194 <uarte_nrfx_poll_out+0x7c>
	__asm__ volatile(
    416e:	f386 8811 	msr	BASEPRI, r6
    4172:	f3bf 8f6f 	isb	sy
}
    4176:	e7ed      	b.n	4154 <uarte_nrfx_poll_out+0x3c>
	__asm__ volatile(
    4178:	f04f 0320 	mov.w	r3, #32
    417c:	f3ef 8611 	mrs	r6, BASEPRI
    4180:	f383 8812 	msr	BASEPRI_MAX, r3
    4184:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    4188:	6860      	ldr	r0, [r4, #4]
    418a:	4631      	mov	r1, r6
    418c:	f005 f9d6 	bl	953c <is_tx_ready.isra.0>
    4190:	2800      	cmp	r0, #0
    4192:	d0da      	beq.n	414a <uarte_nrfx_poll_out+0x32>
	*data->char_out = c;
    4194:	693b      	ldr	r3, [r7, #16]
    4196:	701d      	strb	r5, [r3, #0]
	const struct uarte_nrfx_config *config = dev->config;
    4198:	6862      	ldr	r2, [r4, #4]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    419a:	6938      	ldr	r0, [r7, #16]
	return config->uarte_regs;
    419c:	6813      	ldr	r3, [r2, #0]
    419e:	f8c3 0544 	str.w	r0, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    41a2:	2001      	movs	r0, #1
    41a4:	f8c3 0548 	str.w	r0, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    41a8:	2000      	movs	r0, #0
    41aa:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    41ae:	f8d3 5120 	ldr.w	r5, [r3, #288]	; 0x120
    41b2:	f8c3 0158 	str.w	r0, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    41b6:	6852      	ldr	r2, [r2, #4]
    41b8:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
    41bc:	06d2      	lsls	r2, r2, #27
    41be:	d508      	bpl.n	41d2 <uarte_nrfx_poll_out+0xba>
	return config->uarte_regs;
    41c0:	6862      	ldr	r2, [r4, #4]
    41c2:	6812      	ldr	r2, [r2, #0]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    41c4:	2008      	movs	r0, #8
    41c6:	f8c2 0500 	str.w	r0, [r2, #1280]	; 0x500
    p_reg->INTENSET = mask;
    41ca:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    41ce:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    41d2:	2201      	movs	r2, #1
    41d4:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    41d6:	f381 8811 	msr	BASEPRI, r1
    41da:	f3bf 8f6f 	isb	sy
}
    41de:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    41e0:	200026d7 	.word	0x200026d7

000041e4 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    41e4:	b570      	push	{r4, r5, r6, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    41e6:	2301      	movs	r3, #1
    41e8:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    41ea:	4a0e      	ldr	r2, [pc, #56]	; (4224 <compare_int_lock+0x40>)
    41ec:	f3bf 8f5b 	dmb	ish
    41f0:	43dc      	mvns	r4, r3
    41f2:	e852 1f00 	ldrex	r1, [r2]
    41f6:	ea01 0504 	and.w	r5, r1, r4
    41fa:	e842 5600 	strex	r6, r5, [r2]
    41fe:	2e00      	cmp	r6, #0
    4200:	d1f7      	bne.n	41f2 <compare_int_lock+0xe>
    4202:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    4206:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    420a:	4082      	lsls	r2, r0
    420c:	4806      	ldr	r0, [pc, #24]	; (4228 <compare_int_lock+0x44>)
    420e:	f8c0 2308 	str.w	r2, [r0, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    4212:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    4216:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    421a:	420b      	tst	r3, r1
}
    421c:	bf14      	ite	ne
    421e:	2001      	movne	r0, #1
    4220:	2000      	moveq	r0, #0
    4222:	bd70      	pop	{r4, r5, r6, pc}
    4224:	20001ea0 	.word	0x20001ea0
    4228:	40011000 	.word	0x40011000

0000422c <sys_clock_timeout_handler>:
}

static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
    422c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    422e:	491b      	ldr	r1, [pc, #108]	; (429c <sys_clock_timeout_handler+0x70>)
{
    4230:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    4232:	f022 457f 	bic.w	r5, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    4236:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    4238:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    423c:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    4240:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    4242:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    4246:	d30f      	bcc.n	4268 <sys_clock_timeout_handler+0x3c>
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    4248:	f002 fc66 	bl	6b18 <sys_clock_announce>
    return p_reg->CC[ch];
    424c:	00a3      	lsls	r3, r4, #2
    424e:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    4252:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    4256:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    425a:	4295      	cmp	r5, r2
    425c:	d11d      	bne.n	429a <sys_clock_timeout_handler+0x6e>
    p_reg->CC[ch] = cc_val;
    425e:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    4262:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
}
    4266:	e012      	b.n	428e <sys_clock_timeout_handler+0x62>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    4268:	4b0d      	ldr	r3, [pc, #52]	; (42a0 <sys_clock_timeout_handler+0x74>)
    426a:	681b      	ldr	r3, [r3, #0]
    426c:	0a1a      	lsrs	r2, r3, #8
    426e:	061b      	lsls	r3, r3, #24
    4270:	195e      	adds	r6, r3, r5
    4272:	4b0c      	ldr	r3, [pc, #48]	; (42a4 <sys_clock_timeout_handler+0x78>)
    4274:	f142 0700 	adc.w	r7, r2, #0
    4278:	e9c3 6700 	strd	r6, r7, [r3]
	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    427c:	f002 fc4c 	bl	6b18 <sys_clock_announce>
    return p_reg->CC[ch];
    4280:	4a09      	ldr	r2, [pc, #36]	; (42a8 <sys_clock_timeout_handler+0x7c>)
    4282:	f504 73a8 	add.w	r3, r4, #336	; 0x150
    4286:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	if (cc_value == get_comparator(chan)) {
    428a:	429d      	cmp	r5, r3
    428c:	d105      	bne.n	429a <sys_clock_timeout_handler+0x6e>
    p_reg->EVTENSET = mask;
    428e:	4a06      	ldr	r2, [pc, #24]	; (42a8 <sys_clock_timeout_handler+0x7c>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    4290:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    4294:	40a3      	lsls	r3, r4
    4296:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
		if (!anchor_updated) {
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    429a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    429c:	200002a0 	.word	0x200002a0
    42a0:	20001ea4 	.word	0x20001ea4
    42a4:	200002a8 	.word	0x200002a8
    42a8:	40011000 	.word	0x40011000

000042ac <compare_int_unlock>:
	if (key) {
    42ac:	b311      	cbz	r1, 42f4 <compare_int_unlock+0x48>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    42ae:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    42b2:	2301      	movs	r3, #1
    42b4:	4a10      	ldr	r2, [pc, #64]	; (42f8 <compare_int_unlock+0x4c>)
    42b6:	4083      	lsls	r3, r0
    42b8:	e852 cf00 	ldrex	ip, [r2]
    42bc:	ea4c 0c03 	orr.w	ip, ip, r3
    42c0:	e842 c100 	strex	r1, ip, [r2]
    42c4:	2900      	cmp	r1, #0
    42c6:	d1f7      	bne.n	42b8 <compare_int_unlock+0xc>
    42c8:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    42cc:	4a0b      	ldr	r2, [pc, #44]	; (42fc <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    42ce:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    42d2:	4083      	lsls	r3, r0
    42d4:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    42d8:	4b09      	ldr	r3, [pc, #36]	; (4300 <compare_int_unlock+0x54>)
    42da:	f3bf 8f5b 	dmb	ish
    42de:	681b      	ldr	r3, [r3, #0]
    42e0:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    42e4:	40c3      	lsrs	r3, r0
    42e6:	07db      	lsls	r3, r3, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    42e8:	bf42      	ittt	mi
    42ea:	4b06      	ldrmi	r3, [pc, #24]	; (4304 <compare_int_unlock+0x58>)
    42ec:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    42f0:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    42f4:	4770      	bx	lr
    42f6:	bf00      	nop
    42f8:	20001ea0 	.word	0x20001ea0
    42fc:	40011000 	.word	0x40011000
    4300:	20001e9c 	.word	0x20001e9c
    4304:	e000e100 	.word	0xe000e100

00004308 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    4308:	4b0d      	ldr	r3, [pc, #52]	; (4340 <z_nrf_rtc_timer_read+0x38>)
    430a:	6818      	ldr	r0, [r3, #0]
    430c:	0a01      	lsrs	r1, r0, #8
    430e:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    4310:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    4314:	4b0b      	ldr	r3, [pc, #44]	; (4344 <z_nrf_rtc_timer_read+0x3c>)
    4316:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    431a:	1818      	adds	r0, r3, r0
    431c:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    4320:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    4324:	d20a      	bcs.n	433c <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    4326:	4b08      	ldr	r3, [pc, #32]	; (4348 <z_nrf_rtc_timer_read+0x40>)
    4328:	e9d3 2300 	ldrd	r2, r3, [r3]
    432c:	4290      	cmp	r0, r2
    432e:	eb71 0303 	sbcs.w	r3, r1, r3
    4332:	d203      	bcs.n	433c <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    4334:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    4338:	f141 0100 	adc.w	r1, r1, #0
}
    433c:	4770      	bx	lr
    433e:	bf00      	nop
    4340:	20001ea4 	.word	0x20001ea4
    4344:	40011000 	.word	0x40011000
    4348:	200002a8 	.word	0x200002a8

0000434c <compare_set>:
{
    434c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4350:	4614      	mov	r4, r2
    4352:	461d      	mov	r5, r3
    4354:	4607      	mov	r7, r0
	key = compare_int_lock(chan);
    4356:	f7ff ff45 	bl	41e4 <compare_int_lock>
    435a:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    435c:	f7ff ffd4 	bl	4308 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    4360:	42a0      	cmp	r0, r4
    4362:	eb71 0305 	sbcs.w	r3, r1, r5
    4366:	d27a      	bcs.n	445e <compare_set+0x112>
		if (target_time - curr_time > COUNTER_SPAN) {
    4368:	4b46      	ldr	r3, [pc, #280]	; (4484 <compare_set+0x138>)
    436a:	1a20      	subs	r0, r4, r0
    436c:	eb65 0101 	sbc.w	r1, r5, r1
    4370:	4298      	cmp	r0, r3
    4372:	f171 0100 	sbcs.w	r1, r1, #0
    4376:	f080 8081 	bcs.w	447c <compare_set+0x130>
		if (target_time != cc_data[chan].target_time) {
    437a:	4b43      	ldr	r3, [pc, #268]	; (4488 <compare_set+0x13c>)
    437c:	eb03 1307 	add.w	r3, r3, r7, lsl #4
    4380:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    4384:	429d      	cmp	r5, r3
    4386:	bf08      	it	eq
    4388:	4294      	cmpeq	r4, r2
    438a:	d053      	beq.n	4434 <compare_set+0xe8>
    438c:	ea4f 0a87 	mov.w	sl, r7, lsl #2
    4390:	f10a 4a80 	add.w	sl, sl, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    4394:	f107 0950 	add.w	r9, r7, #80	; 0x50
    4398:	f50a 3a88 	add.w	sl, sl, #69632	; 0x11000
    439c:	ea4f 0989 	mov.w	r9, r9, lsl #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    43a0:	fa1f f989 	uxth.w	r9, r9
	return absolute_time & COUNTER_MAX;
    43a4:	f024 487f 	bic.w	r8, r4, #4278190080	; 0xff000000
    43a8:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    43ac:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    return p_reg->CC[ch];
    43b0:	f8da 0540 	ldr.w	r0, [sl, #1344]	; 0x540
     return p_reg->COUNTER;
    43b4:	4a35      	ldr	r2, [pc, #212]	; (448c <compare_set+0x140>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    43b6:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
    43ba:	40bb      	lsls	r3, r7
	uint32_t cc_val = abs_val & COUNTER_MAX;
    43bc:	4646      	mov	r6, r8
     return p_reg->COUNTER;
    43be:	f8d2 b504 	ldr.w	fp, [r2, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    43c2:	eba0 000b 	sub.w	r0, r0, fp
    43c6:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    43ca:	f02b 417f 	bic.w	r1, fp, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    43ce:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    43d0:	f8ca 1540 	str.w	r1, [sl, #1344]	; 0x540
    43d4:	d105      	bne.n	43e2 <compare_set+0x96>
    43d6:	9301      	str	r3, [sp, #4]
	z_impl_k_busy_wait(usec_to_wait);
    43d8:	2013      	movs	r0, #19
    43da:	f005 fc9e 	bl	9d1a <z_impl_k_busy_wait>
    43de:	4a2b      	ldr	r2, [pc, #172]	; (448c <compare_set+0x140>)
    43e0:	9b01      	ldr	r3, [sp, #4]
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    43e2:	f10b 0c02 	add.w	ip, fp, #2
	return (a - b) & COUNTER_MAX;
    43e6:	eba6 000c 	sub.w	r0, r6, ip
    43ea:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    43ee:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    43f2:	bf88      	it	hi
    43f4:	4666      	movhi	r6, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    43f6:	2000      	movs	r0, #0
    43f8:	f8c9 0000 	str.w	r0, [r9]
    43fc:	f8d9 0000 	ldr.w	r0, [r9]
    p_reg->EVTENSET = mask;
    4400:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    4404:	f026 407f 	bic.w	r0, r6, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    4408:	f8ca 0540 	str.w	r0, [sl, #1344]	; 0x540
     return p_reg->COUNTER;
    440c:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	} while ((now2 != now) &&
    4410:	4583      	cmp	fp, r0
    4412:	d006      	beq.n	4422 <compare_set+0xd6>
	return (a - b) & COUNTER_MAX;
    4414:	1a30      	subs	r0, r6, r0
    4416:	3802      	subs	r0, #2
    4418:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    441c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    4420:	d81b      	bhi.n	445a <compare_set+0x10e>
	return (a - b) & COUNTER_MAX;
    4422:	eba6 0608 	sub.w	r6, r6, r8
    4426:	f026 467f 	bic.w	r6, r6, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    442a:	1936      	adds	r6, r6, r4
    442c:	f145 0300 	adc.w	r3, r5, #0
    4430:	4634      	mov	r4, r6
    4432:	461d      	mov	r5, r3
	cc_data[chan].target_time = target_time;
    4434:	4914      	ldr	r1, [pc, #80]	; (4488 <compare_set+0x13c>)
	cc_data[chan].callback = handler;
    4436:	980c      	ldr	r0, [sp, #48]	; 0x30
	cc_data[chan].target_time = target_time;
    4438:	013b      	lsls	r3, r7, #4
    443a:	eb01 1207 	add.w	r2, r1, r7, lsl #4
	cc_data[chan].callback = handler;
    443e:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    4440:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    4442:	6053      	str	r3, [r2, #4]
	cc_data[chan].target_time = target_time;
    4444:	e9c2 4502 	strd	r4, r5, [r2, #8]
	return ret;
    4448:	2400      	movs	r4, #0
	compare_int_unlock(chan, key);
    444a:	4638      	mov	r0, r7
    444c:	9900      	ldr	r1, [sp, #0]
    444e:	f7ff ff2d 	bl	42ac <compare_int_unlock>
}
    4452:	4620      	mov	r0, r4
    4454:	b003      	add	sp, #12
    4456:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    445a:	4630      	mov	r0, r6
    445c:	e7af      	b.n	43be <compare_set+0x72>
		atomic_or(&force_isr_mask, BIT(chan));
    445e:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    4460:	4a0b      	ldr	r2, [pc, #44]	; (4490 <compare_set+0x144>)
    4462:	f3bf 8f5b 	dmb	ish
    4466:	40bb      	lsls	r3, r7
    4468:	e852 0f00 	ldrex	r0, [r2]
    446c:	4318      	orrs	r0, r3
    446e:	e842 0100 	strex	r1, r0, [r2]
    4472:	2900      	cmp	r1, #0
    4474:	d1f8      	bne.n	4468 <compare_set+0x11c>
    4476:	f3bf 8f5b 	dmb	ish
    447a:	e7db      	b.n	4434 <compare_set+0xe8>
			return -EINVAL;
    447c:	f06f 0415 	mvn.w	r4, #21
    4480:	e7e3      	b.n	444a <compare_set+0xfe>
    4482:	bf00      	nop
    4484:	01000001 	.word	0x01000001
    4488:	20000290 	.word	0x20000290
    448c:	40011000 	.word	0x40011000
    4490:	20001e9c 	.word	0x20001e9c

00004494 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    4494:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    4496:	4b19      	ldr	r3, [pc, #100]	; (44fc <sys_clock_driver_init+0x68>)
    p_reg->PRESCALER = val;
    4498:	4d19      	ldr	r5, [pc, #100]	; (4500 <sys_clock_driver_init+0x6c>)
    449a:	2400      	movs	r4, #0
    449c:	f04f 30ff 	mov.w	r0, #4294967295
    44a0:	f04f 31ff 	mov.w	r1, #4294967295
    44a4:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    44a8:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    44ac:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    44b0:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    44b4:	4b13      	ldr	r3, [pc, #76]	; (4504 <sys_clock_driver_init+0x70>)
    44b6:	2602      	movs	r6, #2
    44b8:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    44bc:	2101      	movs	r1, #1
    44be:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    44c2:	2011      	movs	r0, #17
    44c4:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    44c8:	4622      	mov	r2, r4
    44ca:	f7fd fdb5 	bl	2038 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    44ce:	2011      	movs	r0, #17
    44d0:	f7fd fd82 	bl	1fd8 <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    44d4:	4a0c      	ldr	r2, [pc, #48]	; (4508 <sys_clock_driver_init+0x74>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    44d6:	2301      	movs	r3, #1
    44d8:	60ab      	str	r3, [r5, #8]
    44da:	602b      	str	r3, [r5, #0]
    44dc:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    44de:	4b0b      	ldr	r3, [pc, #44]	; (450c <sys_clock_driver_init+0x78>)
    44e0:	4a0b      	ldr	r2, [pc, #44]	; (4510 <sys_clock_driver_init+0x7c>)
    44e2:	9300      	str	r3, [sp, #0]
    44e4:	9401      	str	r4, [sp, #4]
    44e6:	2300      	movs	r3, #0
    44e8:	4620      	mov	r0, r4
    44ea:	f7ff ff2f 	bl	434c <compare_set>

	z_nrf_clock_control_lf_on(mode);
    44ee:	4630      	mov	r0, r6
    44f0:	f7fe fbe8 	bl	2cc4 <z_nrf_clock_control_lf_on>

	return 0;
}
    44f4:	4620      	mov	r0, r4
    44f6:	b002      	add	sp, #8
    44f8:	bd70      	pop	{r4, r5, r6, pc}
    44fa:	bf00      	nop
    44fc:	20000290 	.word	0x20000290
    4500:	40011000 	.word	0x40011000
    4504:	e000e100 	.word	0xe000e100
    4508:	20001ea0 	.word	0x20001ea0
    450c:	0000422d 	.word	0x0000422d
    4510:	007fffff 	.word	0x007fffff

00004514 <rtc_nrf_isr>:
{
    4514:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    4518:	4c33      	ldr	r4, [pc, #204]	; (45e8 <rtc_nrf_isr+0xd4>)
    451a:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    451e:	079a      	lsls	r2, r3, #30
    4520:	d50b      	bpl.n	453a <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4522:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    4526:	b143      	cbz	r3, 453a <rtc_nrf_isr+0x26>
		overflow_cnt++;
    4528:	4a30      	ldr	r2, [pc, #192]	; (45ec <rtc_nrf_isr+0xd8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    452a:	2300      	movs	r3, #0
    452c:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    4530:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    4534:	6813      	ldr	r3, [r2, #0]
    4536:	3301      	adds	r3, #1
    4538:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    453a:	f04f 0320 	mov.w	r3, #32
    453e:	f3ef 8211 	mrs	r2, BASEPRI
    4542:	f383 8812 	msr	BASEPRI_MAX, r3
    4546:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    454a:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    454e:	03db      	lsls	r3, r3, #15
    4550:	d529      	bpl.n	45a6 <rtc_nrf_isr+0x92>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    4552:	f3bf 8f5b 	dmb	ish
    4556:	4b26      	ldr	r3, [pc, #152]	; (45f0 <rtc_nrf_isr+0xdc>)
    4558:	e853 1f00 	ldrex	r1, [r3]
    455c:	f021 0001 	bic.w	r0, r1, #1
    4560:	e843 0500 	strex	r5, r0, [r3]
    4564:	2d00      	cmp	r5, #0
    4566:	d1f7      	bne.n	4558 <rtc_nrf_isr+0x44>
    4568:	f3bf 8f5b 	dmb	ish
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    456c:	b911      	cbnz	r1, 4574 <rtc_nrf_isr+0x60>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    456e:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
    4572:	b1c3      	cbz	r3, 45a6 <rtc_nrf_isr+0x92>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    4574:	2500      	movs	r5, #0
    4576:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    457a:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
	__asm__ volatile(
    457e:	f382 8811 	msr	BASEPRI, r2
    4582:	f3bf 8f6f 	isb	sy
		curr_time = z_nrf_rtc_timer_read();
    4586:	f7ff febf 	bl	4308 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    458a:	f04f 0320 	mov.w	r3, #32
    458e:	f3ef 8211 	mrs	r2, BASEPRI
    4592:	f383 8812 	msr	BASEPRI_MAX, r3
    4596:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    459a:	4b16      	ldr	r3, [pc, #88]	; (45f4 <rtc_nrf_isr+0xe0>)
    459c:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    45a0:	42b0      	cmp	r0, r6
    45a2:	41b9      	sbcs	r1, r7
    45a4:	d206      	bcs.n	45b4 <rtc_nrf_isr+0xa0>
	__asm__ volatile(
    45a6:	f382 8811 	msr	BASEPRI, r2
    45aa:	f3bf 8f6f 	isb	sy
}
    45ae:	b003      	add	sp, #12
    45b0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    45b4:	f04f 38ff 	mov.w	r8, #4294967295
    45b8:	f04f 39ff 	mov.w	r9, #4294967295
			user_context = cc_data[chan].user_context;
    45bc:	e9d3 1000 	ldrd	r1, r0, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    45c0:	e9c3 8902 	strd	r8, r9, [r3, #8]
			cc_data[chan].callback = NULL;
    45c4:	601d      	str	r5, [r3, #0]
    p_reg->EVTENCLR = mask;
    45c6:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    45ca:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
    45ce:	f382 8811 	msr	BASEPRI, r2
    45d2:	f3bf 8f6f 	isb	sy
		if (handler) {
    45d6:	2900      	cmp	r1, #0
    45d8:	d0e9      	beq.n	45ae <rtc_nrf_isr+0x9a>
			handler(chan, expire_time, user_context);
    45da:	9000      	str	r0, [sp, #0]
    45dc:	4632      	mov	r2, r6
    45de:	463b      	mov	r3, r7
    45e0:	4628      	mov	r0, r5
    45e2:	4788      	blx	r1
}
    45e4:	e7e3      	b.n	45ae <rtc_nrf_isr+0x9a>
    45e6:	bf00      	nop
    45e8:	40011000 	.word	0x40011000
    45ec:	20001ea4 	.word	0x20001ea4
    45f0:	20001e9c 	.word	0x20001e9c
    45f4:	20000290 	.word	0x20000290

000045f8 <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    45f8:	1c43      	adds	r3, r0, #1
{
    45fa:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    45fc:	d021      	beq.n	4642 <sys_clock_set_timeout+0x4a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    45fe:	2801      	cmp	r0, #1
    4600:	dd21      	ble.n	4646 <sys_clock_set_timeout+0x4e>
    4602:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    4606:	da20      	bge.n	464a <sys_clock_set_timeout+0x52>
    4608:	1e44      	subs	r4, r0, #1
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    460a:	f7ff fe7d 	bl	4308 <z_nrf_rtc_timer_read>
    460e:	4b10      	ldr	r3, [pc, #64]	; (4650 <sys_clock_set_timeout+0x58>)
    4610:	e9d3 1300 	ldrd	r1, r3, [r3]
    4614:	1a42      	subs	r2, r0, r1
		ticks = 0;
    4616:	f5b2 0f00 	cmp.w	r2, #8388608	; 0x800000
	if (cyc > MAX_CYCLES) {
    461a:	480e      	ldr	r0, [pc, #56]	; (4654 <sys_clock_set_timeout+0x5c>)
		ticks = 0;
    461c:	bf28      	it	cs
    461e:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    4620:	3201      	adds	r2, #1
    4622:	4422      	add	r2, r4
	if (cyc > MAX_CYCLES) {
    4624:	4282      	cmp	r2, r0
    4626:	bf28      	it	cs
    4628:	4602      	movcs	r2, r0
	uint64_t target_time = cyc + last_count;
    462a:	1852      	adds	r2, r2, r1
    462c:	f04f 0000 	mov.w	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    4630:	4909      	ldr	r1, [pc, #36]	; (4658 <sys_clock_set_timeout+0x60>)
    4632:	9001      	str	r0, [sp, #4]
    4634:	9100      	str	r1, [sp, #0]
    4636:	f143 0300 	adc.w	r3, r3, #0
    463a:	f7ff fe87 	bl	434c <compare_set>
}
    463e:	b002      	add	sp, #8
    4640:	bd10      	pop	{r4, pc}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    4642:	4804      	ldr	r0, [pc, #16]	; (4654 <sys_clock_set_timeout+0x5c>)
    4644:	e7e0      	b.n	4608 <sys_clock_set_timeout+0x10>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    4646:	2400      	movs	r4, #0
    4648:	e7df      	b.n	460a <sys_clock_set_timeout+0x12>
    464a:	4c02      	ldr	r4, [pc, #8]	; (4654 <sys_clock_set_timeout+0x5c>)
    464c:	e7dd      	b.n	460a <sys_clock_set_timeout+0x12>
    464e:	bf00      	nop
    4650:	200002a0 	.word	0x200002a0
    4654:	007fffff 	.word	0x007fffff
    4658:	0000422d 	.word	0x0000422d

0000465c <sys_clock_elapsed>:
{
    465c:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    465e:	f7ff fe53 	bl	4308 <z_nrf_rtc_timer_read>
    4662:	4b02      	ldr	r3, [pc, #8]	; (466c <sys_clock_elapsed+0x10>)
    4664:	681b      	ldr	r3, [r3, #0]
}
    4666:	1ac0      	subs	r0, r0, r3
    4668:	bd08      	pop	{r3, pc}
    466a:	bf00      	nop
    466c:	200002a0 	.word	0x200002a0

00004670 <pinctrl_configure_pins>:
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    4670:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
        case 1: return NRF_P1;
    4674:	4e4d      	ldr	r6, [pc, #308]	; (47ac <pinctrl_configure_pins+0x13c>)
    4676:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    467a:	2701      	movs	r7, #1
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    467c:	4281      	cmp	r1, r0
    467e:	d102      	bne.n	4686 <pinctrl_configure_pins+0x16>
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
				     drive, NRF_GPIO_PIN_NOSENSE);
		}
	}

	return 0;
    4680:	2000      	movs	r0, #0
}
    4682:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    4686:	6805      	ldr	r5, [r0, #0]
		uint32_t pin = NRF_GET_PIN(pins[i]);
    4688:	f005 037f 	and.w	r3, r5, #127	; 0x7f
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    468c:	f3c5 2443 	ubfx	r4, r5, #9, #4
			pin = 0xFFFFFFFFU;
    4690:	2b7f      	cmp	r3, #127	; 0x7f
		switch (NRF_GET_FUN(pins[i])) {
    4692:	ea4f 4515 	mov.w	r5, r5, lsr #16
			pin = 0xFFFFFFFFU;
    4696:	bf08      	it	eq
    4698:	f04f 33ff 	moveq.w	r3, #4294967295
		switch (NRF_GET_FUN(pins[i])) {
    469c:	2d19      	cmp	r5, #25
    469e:	f200 8081 	bhi.w	47a4 <pinctrl_configure_pins+0x134>
    46a2:	e8df f005 	tbb	[pc, r5]
    46a6:	1f0d      	.short	0x1f0d
    46a8:	3e2a2724 	.word	0x3e2a2724
    46ac:	7f7f7f27 	.word	0x7f7f7f27
    46b0:	7f6b427f 	.word	0x7f6b427f
    46b4:	7f7f7f7f 	.word	0x7f7f7f7f
    46b8:	7f7f7f7f 	.word	0x7f7f7f7f
    46bc:	7c79766e 	.word	0x7c79766e
			NRF_PSEL_UART(reg, TXD) = pin;
    46c0:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    return pin_number >> 5;
    46c4:	ea4f 1c53 	mov.w	ip, r3, lsr #5
        case 1: return NRF_P1;
    46c8:	f1bc 0f01 	cmp.w	ip, #1
    *p_pin = pin_number & 0x1F;
    46cc:	f003 051f 	and.w	r5, r3, #31
        case 1: return NRF_P1;
    46d0:	bf14      	ite	ne
    46d2:	f04f 4ca0 	movne.w	ip, #1342177280	; 0x50000000
    46d6:	46b4      	moveq	ip, r6
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    46d8:	fa07 f505 	lsl.w	r5, r7, r5
    p_reg->OUTSET = set_mask;
    46dc:	f8cc 5508 	str.w	r5, [ip, #1288]	; 0x508
    46e0:	2501      	movs	r5, #1
    46e2:	e002      	b.n	46ea <pinctrl_configure_pins+0x7a>
			NRF_PSEL_UART(reg, RXD) = pin;
    46e4:	f8c2 3514 	str.w	r3, [r2, #1300]	; 0x514
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    46e8:	2500      	movs	r5, #0
    46ea:	46ae      	mov	lr, r5
    46ec:	e024      	b.n	4738 <pinctrl_configure_pins+0xc8>
			NRF_PSEL_UART(reg, RTS) = pin;
    46ee:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (write != NO_WRITE) {
    46f2:	e7e7      	b.n	46c4 <pinctrl_configure_pins+0x54>
			NRF_PSEL_UART(reg, CTS) = pin;
    46f4:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			if (write != NO_WRITE) {
    46f8:	e7f6      	b.n	46e8 <pinctrl_configure_pins+0x78>
			NRF_PSEL_SPIM(reg, SCK) = pin;
    46fa:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    46fe:	2500      	movs	r5, #0
    return pin_number >> 5;
    4700:	ea4f 1e53 	mov.w	lr, r3, lsr #5
        case 1: return NRF_P1;
    4704:	f1be 0f01 	cmp.w	lr, #1
    4708:	bf14      	ite	ne
    470a:	f04f 4ea0 	movne.w	lr, #1342177280	; 0x50000000
    470e:	46b6      	moveq	lr, r6
    *p_pin = pin_number & 0x1F;
    4710:	f003 0c1f 	and.w	ip, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    4714:	fa07 fc0c 	lsl.w	ip, r7, ip
    p_reg->OUTCLR = clr_mask;
    4718:	f8ce c50c 	str.w	ip, [lr, #1292]	; 0x50c
    471c:	f04f 0e01 	mov.w	lr, #1
    4720:	e00a      	b.n	4738 <pinctrl_configure_pins+0xc8>
			NRF_PSEL_SPIM(reg, MOSI) = pin;
    4722:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			pin = 0xFFFFFFFFU;
    4726:	2501      	movs	r5, #1
    4728:	e7ea      	b.n	4700 <pinctrl_configure_pins+0x90>
			NRF_PSEL_TWIM(reg, SCL) = pin;
    472a:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (drive == NRF_DRIVE_S0S1) {
    472e:	2c00      	cmp	r4, #0
    4730:	d1da      	bne.n	46e8 <pinctrl_configure_pins+0x78>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    4732:	2500      	movs	r5, #0
			dir = NRF_GPIO_PIN_DIR_INPUT;
    4734:	46ae      	mov	lr, r5
				drive = NRF_DRIVE_S0D1;
    4736:	2406      	movs	r4, #6
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    4738:	f850 cb04 	ldr.w	ip, [r0], #4
    473c:	f40c 5800 	and.w	r8, ip, #8192	; 0x2000
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    4740:	f1b8 0f00 	cmp.w	r8, #0
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    4744:	ea4f 2404 	mov.w	r4, r4, lsl #8
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
    4748:	f3cc 18c1 	ubfx	r8, ip, #7, #2
    *p_pin = pin_number & 0x1F;
    474c:	f003 0c1f 	and.w	ip, r3, #31
    return pin_number >> 5;
    4750:	ea4f 1353 	mov.w	r3, r3, lsr #5
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    4754:	bf1c      	itt	ne
    4756:	2501      	movne	r5, #1
    4758:	f04f 0e00 	movne.w	lr, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    475c:	ea44 0488 	orr.w	r4, r4, r8, lsl #2
        case 0: return NRF_P0;
    4760:	2b01      	cmp	r3, #1
    4762:	bf0c      	ite	eq
    4764:	4633      	moveq	r3, r6
    4766:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    476a:	ea44 040e 	orr.w	r4, r4, lr
    reg->PIN_CNF[pin_number] = cnf;
    476e:	f50c 7ce0 	add.w	ip, ip, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    4772:	ea44 0445 	orr.w	r4, r4, r5, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    4776:	f843 402c 	str.w	r4, [r3, ip, lsl #2]
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    477a:	e77f      	b.n	467c <pinctrl_configure_pins+0xc>
			NRF_PSEL_TWIM(reg, SDA) = pin;
    477c:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			if (drive == NRF_DRIVE_S0S1) {
    4780:	e7d5      	b.n	472e <pinctrl_configure_pins+0xbe>
			NRF_PSEL_PWM(reg, OUT[0]) = pin;
    4782:	f8c2 3560 	str.w	r3, [r2, #1376]	; 0x560
			write = NRF_GET_INVERT(pins[i]);
    4786:	6805      	ldr	r5, [r0, #0]
    4788:	f3c5 3580 	ubfx	r5, r5, #14, #1
    if (value == 0)
    478c:	2d00      	cmp	r5, #0
    478e:	d0ca      	beq.n	4726 <pinctrl_configure_pins+0xb6>
    4790:	e798      	b.n	46c4 <pinctrl_configure_pins+0x54>
			NRF_PSEL_PWM(reg, OUT[1]) = pin;
    4792:	f8c2 3564 	str.w	r3, [r2, #1380]	; 0x564
			write = NRF_GET_INVERT(pins[i]);
    4796:	e7f6      	b.n	4786 <pinctrl_configure_pins+0x116>
			NRF_PSEL_PWM(reg, OUT[2]) = pin;
    4798:	f8c2 3568 	str.w	r3, [r2, #1384]	; 0x568
			write = NRF_GET_INVERT(pins[i]);
    479c:	e7f3      	b.n	4786 <pinctrl_configure_pins+0x116>
			NRF_PSEL_PWM(reg, OUT[3]) = pin;
    479e:	f8c2 356c 	str.w	r3, [r2, #1388]	; 0x56c
    47a2:	e7f0      	b.n	4786 <pinctrl_configure_pins+0x116>
		switch (NRF_GET_FUN(pins[i])) {
    47a4:	f06f 0085 	mvn.w	r0, #133	; 0x85
    47a8:	e76b      	b.n	4682 <pinctrl_configure_pins+0x12>
    47aa:	bf00      	nop
    47ac:	50000300 	.word	0x50000300

000047b0 <k_sys_fatal_error_handler>:
	defined(CONFIG_SPM_SERVICE_NS_HANDLER_FROM_SPM_FAULT)
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    47b0:	4803      	ldr	r0, [pc, #12]	; (47c0 <k_sys_fatal_error_handler+0x10>)
{
    47b2:	b508      	push	{r3, lr}
		LOG_ERR("Resetting system");
    47b4:	2145      	movs	r1, #69	; 0x45
    47b6:	f004 fa8c 	bl	8cd2 <z_log_minimal_printk>
		sys_arch_reboot(0);
    47ba:	2000      	movs	r0, #0
    47bc:	f7fe f972 	bl	2aa4 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    47c0:	0000b3bd 	.word	0x0000b3bd

000047c4 <boot_write_magic>:
    return rc;
}

int
boot_write_magic(const struct flash_area *fap)
{
    47c4:	b530      	push	{r4, r5, lr}
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    47c6:	6881      	ldr	r1, [r0, #8]
{
    47c8:	b085      	sub	sp, #20
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    47ca:	3910      	subs	r1, #16
     * returned by boot_magic_off() is the start of magic which is not the
     * start of the flash write boundary and thus writes to the magic will fail.
     * To account for this change, write to magic is first padded with 0xFF
     * before writing to the trailer.
     */
    pad_off = ALIGN_DOWN(off, BOOT_MAX_ALIGN);
    47cc:	f021 0407 	bic.w	r4, r1, #7
{
    47d0:	4605      	mov	r5, r0

    erased_val = flash_area_erased_val(fap);
    47d2:	f004 fad3 	bl	8d7c <flash_area_erased_val>

    memset(&magic[0], erased_val, sizeof(magic));
    47d6:	2210      	movs	r2, #16
    erased_val = flash_area_erased_val(fap);
    47d8:	4601      	mov	r1, r0
    memset(&magic[0], erased_val, sizeof(magic));
    47da:	4668      	mov	r0, sp
    47dc:	f004 fb36 	bl	8e4c <memset>
    memcpy(&magic[BOOT_MAGIC_ALIGN_SIZE - BOOT_MAGIC_SZ], BOOT_IMG_MAGIC, BOOT_MAGIC_SZ);
    47e0:	4907      	ldr	r1, [pc, #28]	; (4800 <boot_write_magic+0x3c>)
    47e2:	2210      	movs	r2, #16
    47e4:	4668      	mov	r0, sp
    47e6:	f004 fb26 	bl	8e36 <memcpy>

    BOOT_LOG_DBG("writing magic; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    rc = flash_area_write(fap, pad_off, &magic[0], BOOT_MAGIC_ALIGN_SIZE);
    47ea:	2310      	movs	r3, #16
    47ec:	466a      	mov	r2, sp
    47ee:	4621      	mov	r1, r4
    47f0:	4628      	mov	r0, r5
    47f2:	f004 fa91 	bl	8d18 <flash_area_write>
    if (rc != 0) {
        return BOOT_EFLASH;
    }

    return 0;
}
    47f6:	3800      	subs	r0, #0
    47f8:	bf18      	it	ne
    47fa:	2001      	movne	r0, #1
    47fc:	b005      	add	sp, #20
    47fe:	bd30      	pop	{r4, r5, pc}
    4800:	0000a5cc 	.word	0x0000a5cc

00004804 <boot_read_swap_state>:
{
    4804:	b530      	push	{r4, r5, lr}
    4806:	460d      	mov	r5, r1
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    4808:	6881      	ldr	r1, [r0, #8]
{
    480a:	b087      	sub	sp, #28
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    480c:	2310      	movs	r3, #16
    480e:	aa02      	add	r2, sp, #8
    4810:	3910      	subs	r1, #16
{
    4812:	4604      	mov	r4, r0
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    4814:	f004 fa6b 	bl	8cee <flash_area_read>
    if (rc < 0) {
    4818:	2800      	cmp	r0, #0
    481a:	da02      	bge.n	4822 <boot_read_swap_state+0x1e>
        return BOOT_EFLASH;
    481c:	2001      	movs	r0, #1
}
    481e:	b007      	add	sp, #28
    4820:	bd30      	pop	{r4, r5, pc}
    if (bootutil_buffer_is_erased(fap, magic, BOOT_MAGIC_SZ)) {
    4822:	2210      	movs	r2, #16
    4824:	a902      	add	r1, sp, #8
    4826:	4620      	mov	r0, r4
    4828:	f004 ff25 	bl	9676 <bootutil_buffer_is_erased>
    482c:	2800      	cmp	r0, #0
    482e:	d13a      	bne.n	48a6 <boot_read_swap_state+0xa2>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
    4830:	491e      	ldr	r1, [pc, #120]	; (48ac <boot_read_swap_state+0xa8>)
    4832:	2210      	movs	r2, #16
    4834:	a802      	add	r0, sp, #8
    4836:	f004 faee 	bl	8e16 <memcmp>
    return BOOT_MAGIC_BAD;
    483a:	2800      	cmp	r0, #0
        state->magic = boot_magic_decode(magic);
    483c:	bf0c      	ite	eq
    483e:	2301      	moveq	r3, #1
    4840:	2302      	movne	r3, #2
        state->magic = BOOT_MAGIC_UNSET;
    4842:	702b      	strb	r3, [r5, #0]
    off = boot_swap_info_off(fap);
    4844:	4620      	mov	r0, r4
    4846:	f004 ff02 	bl	964e <boot_swap_info_off>
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    484a:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    484c:	4601      	mov	r1, r0
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    484e:	f10d 0207 	add.w	r2, sp, #7
    4852:	4620      	mov	r0, r4
    4854:	f004 fa4b 	bl	8cee <flash_area_read>
    if (rc < 0) {
    4858:	2800      	cmp	r0, #0
    485a:	dbdf      	blt.n	481c <boot_read_swap_state+0x18>
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    485c:	f89d 3007 	ldrb.w	r3, [sp, #7]
    4860:	f003 020f 	and.w	r2, r3, #15
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    4864:	091b      	lsrs	r3, r3, #4
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    4866:	706a      	strb	r2, [r5, #1]
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    4868:	712b      	strb	r3, [r5, #4]
    if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info) ||
    486a:	2201      	movs	r2, #1
    486c:	f10d 0107 	add.w	r1, sp, #7
    4870:	4620      	mov	r0, r4
    4872:	f004 ff00 	bl	9676 <bootutil_buffer_is_erased>
    4876:	b910      	cbnz	r0, 487e <boot_read_swap_state+0x7a>
    4878:	786b      	ldrb	r3, [r5, #1]
    487a:	2b04      	cmp	r3, #4
    487c:	d903      	bls.n	4886 <boot_read_swap_state+0x82>
        state->swap_type = BOOT_SWAP_TYPE_NONE;
    487e:	2301      	movs	r3, #1
    4880:	706b      	strb	r3, [r5, #1]
        state->image_num = 0;
    4882:	2300      	movs	r3, #0
    4884:	712b      	strb	r3, [r5, #4]
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    4886:	68a2      	ldr	r2, [r4, #8]
    4888:	3a18      	subs	r2, #24
    488a:	f022 0207 	bic.w	r2, r2, #7
    return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
    488e:	3a08      	subs	r2, #8
    4890:	1ca9      	adds	r1, r5, #2
    4892:	4620      	mov	r0, r4
    4894:	f004 ff02 	bl	969c <boot_read_flag>
    if (rc) {
    4898:	2800      	cmp	r0, #0
    489a:	d1bf      	bne.n	481c <boot_read_swap_state+0x18>
    return boot_read_image_ok(fap, &state->image_ok);
    489c:	1ce9      	adds	r1, r5, #3
    489e:	4620      	mov	r0, r4
    48a0:	f004 ff55 	bl	974e <boot_read_image_ok>
    48a4:	e7bb      	b.n	481e <boot_read_swap_state+0x1a>
    48a6:	2303      	movs	r3, #3
    48a8:	e7cb      	b.n	4842 <boot_read_swap_state+0x3e>
    48aa:	bf00      	nop
    48ac:	0000a5cc 	.word	0x0000a5cc

000048b0 <boot_swap_type_multi>:
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
}

int
boot_swap_type_multi(int image_index)
{
    48b0:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    48b2:	4605      	mov	r5, r0

    rc = BOOT_HOOK_CALL(boot_read_swap_state_primary_slot_hook,
                        BOOT_HOOK_REGULAR, image_index, &primary_slot);
    if (rc == BOOT_HOOK_REGULAR)
    {
        rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    48b4:	4669      	mov	r1, sp
    48b6:	2003      	movs	r0, #3
    48b8:	f004 ff4f 	bl	975a <boot_read_swap_state_by_id>
                                        &primary_slot);
    }
    if (rc) {
    48bc:	4604      	mov	r4, r0
    48be:	b110      	cbz	r0, 48c6 <boot_swap_type_multi+0x16>
        return BOOT_SWAP_TYPE_PANIC;
    48c0:	20ff      	movs	r0, #255	; 0xff
        }
    }

    BOOT_LOG_INF("Swap type: none");
    return BOOT_SWAP_TYPE_NONE;
}
    48c2:	b004      	add	sp, #16
    48c4:	bd70      	pop	{r4, r5, r6, pc}
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    48c6:	a902      	add	r1, sp, #8
    48c8:	2001      	movs	r0, #1
    48ca:	f004 ff46 	bl	975a <boot_read_swap_state_by_id>
    if (rc == BOOT_EFLASH) {
    48ce:	2801      	cmp	r0, #1
    48d0:	d136      	bne.n	4940 <boot_swap_type_multi+0x90>
        BOOT_LOG_INF("Secondary image of image pair (%d.) "
    48d2:	4829      	ldr	r0, [pc, #164]	; (4978 <boot_swap_type_multi+0xc8>)
    48d4:	462a      	mov	r2, r5
    48d6:	2149      	movs	r1, #73	; 0x49
    48d8:	f004 f9fb 	bl	8cd2 <z_log_minimal_printk>
        secondary_slot.magic = BOOT_MAGIC_UNSET;
    48dc:	4b27      	ldr	r3, [pc, #156]	; (497c <boot_swap_type_multi+0xcc>)
    48de:	9302      	str	r3, [sp, #8]
        secondary_slot.image_num = 0;
    48e0:	f88d 400c 	strb.w	r4, [sp, #12]
        if (boot_magic_compatible_check(table->magic_primary_slot,
    48e4:	f89d 5000 	ldrb.w	r5, [sp]
            boot_magic_compatible_check(table->magic_secondary_slot,
    48e8:	f89d 6008 	ldrb.w	r6, [sp, #8]
    48ec:	4c24      	ldr	r4, [pc, #144]	; (4980 <boot_swap_type_multi+0xd0>)
    48ee:	2200      	movs	r2, #0
        if (boot_magic_compatible_check(table->magic_primary_slot,
    48f0:	7820      	ldrb	r0, [r4, #0]
    48f2:	4629      	mov	r1, r5
    48f4:	f004 feb1 	bl	965a <boot_magic_compatible_check>
    48f8:	b348      	cbz	r0, 494e <boot_swap_type_multi+0x9e>
            boot_magic_compatible_check(table->magic_secondary_slot,
    48fa:	7860      	ldrb	r0, [r4, #1]
    48fc:	4631      	mov	r1, r6
    48fe:	f004 feac 	bl	965a <boot_magic_compatible_check>
                                        primary_slot.magic) &&
    4902:	b320      	cbz	r0, 494e <boot_swap_type_multi+0x9e>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    4904:	78a3      	ldrb	r3, [r4, #2]
                                        secondary_slot.magic) &&
    4906:	2b04      	cmp	r3, #4
    4908:	d003      	beq.n	4912 <boot_swap_type_multi+0x62>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    490a:	f89d 1003 	ldrb.w	r1, [sp, #3]
    490e:	4299      	cmp	r1, r3
    4910:	d11d      	bne.n	494e <boot_swap_type_multi+0x9e>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    4912:	78e3      	ldrb	r3, [r4, #3]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    4914:	2b04      	cmp	r3, #4
    4916:	d003      	beq.n	4920 <boot_swap_type_multi+0x70>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    4918:	f89d 100b 	ldrb.w	r1, [sp, #11]
    491c:	4299      	cmp	r1, r3
    491e:	d116      	bne.n	494e <boot_swap_type_multi+0x9e>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    4920:	7923      	ldrb	r3, [r4, #4]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    4922:	2b04      	cmp	r3, #4
    4924:	d10f      	bne.n	4946 <boot_swap_type_multi+0x96>
            BOOT_LOG_INF("Swap type: %s",
    4926:	7963      	ldrb	r3, [r4, #5]
    4928:	2b02      	cmp	r3, #2
    492a:	d11b      	bne.n	4964 <boot_swap_type_multi+0xb4>
    492c:	4a15      	ldr	r2, [pc, #84]	; (4984 <boot_swap_type_multi+0xd4>)
    492e:	4816      	ldr	r0, [pc, #88]	; (4988 <boot_swap_type_multi+0xd8>)
    4930:	2149      	movs	r1, #73	; 0x49
    4932:	f004 f9ce 	bl	8cd2 <z_log_minimal_printk>
            if (table->swap_type != BOOT_SWAP_TYPE_TEST &&
    4936:	7960      	ldrb	r0, [r4, #5]
    4938:	1e83      	subs	r3, r0, #2
    493a:	2b02      	cmp	r3, #2
    493c:	d9c1      	bls.n	48c2 <boot_swap_type_multi+0x12>
    493e:	e7bf      	b.n	48c0 <boot_swap_type_multi+0x10>
    } else if (rc) {
    4940:	2800      	cmp	r0, #0
    4942:	d0cf      	beq.n	48e4 <boot_swap_type_multi+0x34>
    4944:	e7bc      	b.n	48c0 <boot_swap_type_multi+0x10>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    4946:	f89d 1002 	ldrb.w	r1, [sp, #2]
    494a:	4299      	cmp	r1, r3
    494c:	d0eb      	beq.n	4926 <boot_swap_type_multi+0x76>
    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
    494e:	3201      	adds	r2, #1
    4950:	2a03      	cmp	r2, #3
    4952:	f104 0406 	add.w	r4, r4, #6
    4956:	d1cb      	bne.n	48f0 <boot_swap_type_multi+0x40>
    BOOT_LOG_INF("Swap type: none");
    4958:	480c      	ldr	r0, [pc, #48]	; (498c <boot_swap_type_multi+0xdc>)
    495a:	2149      	movs	r1, #73	; 0x49
    495c:	f004 f9b9 	bl	8cd2 <z_log_minimal_printk>
    return BOOT_SWAP_TYPE_NONE;
    4960:	2001      	movs	r0, #1
    4962:	e7ae      	b.n	48c2 <boot_swap_type_multi+0x12>
            BOOT_LOG_INF("Swap type: %s",
    4964:	2b03      	cmp	r3, #3
    4966:	d005      	beq.n	4974 <boot_swap_type_multi+0xc4>
    4968:	4a09      	ldr	r2, [pc, #36]	; (4990 <boot_swap_type_multi+0xe0>)
    496a:	490a      	ldr	r1, [pc, #40]	; (4994 <boot_swap_type_multi+0xe4>)
    496c:	2b04      	cmp	r3, #4
    496e:	bf08      	it	eq
    4970:	460a      	moveq	r2, r1
    4972:	e7dc      	b.n	492e <boot_swap_type_multi+0x7e>
    4974:	4a08      	ldr	r2, [pc, #32]	; (4998 <boot_swap_type_multi+0xe8>)
    4976:	e7da      	b.n	492e <boot_swap_type_multi+0x7e>
    4978:	0000b402 	.word	0x0000b402
    497c:	03030103 	.word	0x03030103
    4980:	0000b475 	.word	0x0000b475
    4984:	0000b3e4 	.word	0x0000b3e4
    4988:	0000b44d 	.word	0x0000b44d
    498c:	0000b460 	.word	0x0000b460
    4990:	0000b3e9 	.word	0x0000b3e9
    4994:	0000b3fb 	.word	0x0000b3fb
    4998:	0000b3df 	.word	0x0000b3df

0000499c <nrf52_errata_103>:
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    499c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    49a0:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    49a4:	2a08      	cmp	r2, #8
    49a6:	d106      	bne.n	49b6 <nrf52_errata_103+0x1a>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    49a8:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                switch(var2)
    49ac:	2b05      	cmp	r3, #5
    49ae:	d802      	bhi.n	49b6 <nrf52_errata_103+0x1a>
    49b0:	4a02      	ldr	r2, [pc, #8]	; (49bc <nrf52_errata_103+0x20>)
    49b2:	5cd0      	ldrb	r0, [r2, r3]
    49b4:	4770      	bx	lr
                        return false;
    49b6:	2000      	movs	r0, #0
}
    49b8:	4770      	bx	lr
    49ba:	bf00      	nop
    49bc:	0000b48d 	.word	0x0000b48d

000049c0 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    49c0:	4a02      	ldr	r2, [pc, #8]	; (49cc <nvmc_wait+0xc>)
    49c2:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    49c6:	2b00      	cmp	r3, #0
    49c8:	d0fb      	beq.n	49c2 <nvmc_wait+0x2>
}
    49ca:	4770      	bx	lr
    49cc:	4001e000 	.word	0x4001e000

000049d0 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    49d0:	b510      	push	{r4, lr}
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    49d2:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    49d6:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    49da:	2a08      	cmp	r2, #8
    49dc:	d14e      	bne.n	4a7c <SystemInit+0xac>

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
            NRF_CLOCK->EVENTS_DONE = 0;
    49de:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    49e2:	2100      	movs	r1, #0
    49e4:	f8c2 110c 	str.w	r1, [r2, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    49e8:	f8c2 1110 	str.w	r1, [r2, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    49ec:	f8c2 1538 	str.w	r1, [r2, #1336]	; 0x538

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    49f0:	f502 4240 	add.w	r2, r2, #49152	; 0xc000
    49f4:	f8d3 1404 	ldr.w	r1, [r3, #1028]	; 0x404
    49f8:	f8c2 1520 	str.w	r1, [r2, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    49fc:	f8d3 1408 	ldr.w	r1, [r3, #1032]	; 0x408
    4a00:	f8c2 1524 	str.w	r1, [r2, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    4a04:	f8d3 140c 	ldr.w	r1, [r3, #1036]	; 0x40c
    4a08:	f8c2 1528 	str.w	r1, [r2, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    4a0c:	f8d3 1410 	ldr.w	r1, [r3, #1040]	; 0x410
    4a10:	f8c2 152c 	str.w	r1, [r2, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    4a14:	f8d3 1414 	ldr.w	r1, [r3, #1044]	; 0x414
    4a18:	f8c2 1530 	str.w	r1, [r2, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    4a1c:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    4a20:	f8c2 1534 	str.w	r1, [r2, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    4a24:	f8d3 141c 	ldr.w	r1, [r3, #1052]	; 0x41c
    4a28:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    4a2c:	f8d3 1420 	ldr.w	r1, [r3, #1056]	; 0x420
    4a30:	f8c2 1544 	str.w	r1, [r2, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    4a34:	f8d3 1424 	ldr.w	r1, [r3, #1060]	; 0x424
    4a38:	f8c2 1548 	str.w	r1, [r2, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    4a3c:	f8d3 1428 	ldr.w	r1, [r3, #1064]	; 0x428
    4a40:	f8c2 154c 	str.w	r1, [r2, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    4a44:	f8d3 142c 	ldr.w	r1, [r3, #1068]	; 0x42c
    4a48:	f8c2 1550 	str.w	r1, [r2, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    4a4c:	f8d3 1430 	ldr.w	r1, [r3, #1072]	; 0x430
    4a50:	f8c2 1554 	str.w	r1, [r2, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    4a54:	f8d3 1434 	ldr.w	r1, [r3, #1076]	; 0x434
    4a58:	f8c2 1560 	str.w	r1, [r2, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    4a5c:	f8d3 1438 	ldr.w	r1, [r3, #1080]	; 0x438
    4a60:	f8c2 1564 	str.w	r1, [r2, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    4a64:	f8d3 143c 	ldr.w	r1, [r3, #1084]	; 0x43c
    4a68:	f8c2 1568 	str.w	r1, [r2, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    4a6c:	f8d3 1440 	ldr.w	r1, [r3, #1088]	; 0x440
    4a70:	f8c2 156c 	str.w	r1, [r2, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    4a74:	f8d3 3444 	ldr.w	r3, [r3, #1092]	; 0x444
    4a78:	f8c2 3570 	str.w	r3, [r2, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_98_ENABLE_WORKAROUND
        /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_98()){
    4a7c:	f7ff ff8e 	bl	499c <nrf52_errata_103>
    4a80:	b118      	cbz	r0, 4a8a <SystemInit+0xba>
            *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
    4a82:	4b43      	ldr	r3, [pc, #268]	; (4b90 <SystemInit+0x1c0>)
    4a84:	4a43      	ldr	r2, [pc, #268]	; (4b94 <SystemInit+0x1c4>)
    4a86:	f8c3 268c 	str.w	r2, [r3, #1676]	; 0x68c
    #endif

    #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
        /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_103()){
    4a8a:	f7ff ff87 	bl	499c <nrf52_errata_103>
    4a8e:	b118      	cbz	r0, 4a98 <SystemInit+0xc8>
            NRF_CCM->MAXPACKETSIZE = 0xFBul;
    4a90:	4b41      	ldr	r3, [pc, #260]	; (4b98 <SystemInit+0x1c8>)
    4a92:	22fb      	movs	r2, #251	; 0xfb
    4a94:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    #endif

    #if NRF52_ERRATA_115_ENABLE_WORKAROUND
        /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_115()){
    4a98:	f7ff ff80 	bl	499c <nrf52_errata_103>
    4a9c:	b170      	cbz	r0, 4abc <SystemInit+0xec>
            *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
    4a9e:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    4aa2:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    4aa6:	f8d1 2ee4 	ldr.w	r2, [r1, #3812]	; 0xee4
    4aaa:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    4aae:	f022 020f 	bic.w	r2, r2, #15
    4ab2:	f003 030f 	and.w	r3, r3, #15
    4ab6:	4313      	orrs	r3, r2
    4ab8:	f8c1 3ee4 	str.w	r3, [r1, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_120_ENABLE_WORKAROUND
        /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_120()){
    4abc:	f7ff ff6e 	bl	499c <nrf52_errata_103>
    4ac0:	b120      	cbz	r0, 4acc <SystemInit+0xfc>
            *(volatile uint32_t *)0x40029640ul = 0x200ul;
    4ac2:	4b36      	ldr	r3, [pc, #216]	; (4b9c <SystemInit+0x1cc>)
    4ac4:	f44f 7200 	mov.w	r2, #512	; 0x200
    4ac8:	f8c3 2640 	str.w	r2, [r3, #1600]	; 0x640
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    4acc:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    4ad0:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    4ad4:	2b08      	cmp	r3, #8
    4ad6:	d109      	bne.n	4aec <SystemInit+0x11c>

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    4ad8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4adc:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    4ae0:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    4ae2:	bf44      	itt	mi
    4ae4:	f06f 0201 	mvnmi.w	r2, #1
    4ae8:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400

    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
     * operations are not used in your code. */
    #if (__FPU_USED == 1)
        SCB->CPACR |= (3UL << 20) | (3UL << 22);
    4aec:	4a2c      	ldr	r2, [pc, #176]	; (4ba0 <SystemInit+0x1d0>)
    4aee:	f8d2 3088 	ldr.w	r3, [r2, #136]	; 0x88
    4af2:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
    4af6:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
  __ASM volatile ("dsb 0xF":::"memory");
    4afa:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    4afe:	f3bf 8f6f 	isb	sy
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    4b02:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                        return true;
                }
            }
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    4b06:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    4b0a:	2a08      	cmp	r2, #8
    4b0c:	d10e      	bne.n	4b2c <SystemInit+0x15c>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    4b0e:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
            {
                switch(var2)
    4b12:	2b05      	cmp	r3, #5
    4b14:	d802      	bhi.n	4b1c <SystemInit+0x14c>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    4b16:	4a23      	ldr	r2, [pc, #140]	; (4ba4 <SystemInit+0x1d4>)
    4b18:	5cd3      	ldrb	r3, [r2, r3]
    4b1a:	b13b      	cbz	r3, 4b2c <SystemInit+0x15c>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    4b1c:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    4b20:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    4b24:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4b28:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    4b2c:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    4b30:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    4b34:	2a00      	cmp	r2, #0
    4b36:	db03      	blt.n	4b40 <SystemInit+0x170>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    4b38:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    4b3c:	2b00      	cmp	r3, #0
    4b3e:	da22      	bge.n	4b86 <SystemInit+0x1b6>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    4b40:	4919      	ldr	r1, [pc, #100]	; (4ba8 <SystemInit+0x1d8>)
    4b42:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    4b44:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    4b48:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    4b4c:	2412      	movs	r4, #18
    nvmc_wait();
    4b4e:	f7ff ff37 	bl	49c0 <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    4b52:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    4b56:	f7ff ff33 	bl	49c0 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    4b5a:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    4b5e:	f7ff ff2f 	bl	49c0 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    4b62:	2300      	movs	r3, #0
    4b64:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    4b68:	f7ff ff2a 	bl	49c0 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    4b6c:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    4b70:	490b      	ldr	r1, [pc, #44]	; (4ba0 <SystemInit+0x1d0>)
    4b72:	4b0e      	ldr	r3, [pc, #56]	; (4bac <SystemInit+0x1dc>)
    4b74:	68ca      	ldr	r2, [r1, #12]
    4b76:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    4b7a:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    4b7c:	60cb      	str	r3, [r1, #12]
    4b7e:	f3bf 8f4f 	dsb	sy
    __NOP();
    4b82:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    4b84:	e7fd      	b.n	4b82 <SystemInit+0x1b2>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    4b86:	4b0a      	ldr	r3, [pc, #40]	; (4bb0 <SystemInit+0x1e0>)
    4b88:	4a0a      	ldr	r2, [pc, #40]	; (4bb4 <SystemInit+0x1e4>)
    4b8a:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    4b8c:	bd10      	pop	{r4, pc}
    4b8e:	bf00      	nop
    4b90:	40005000 	.word	0x40005000
    4b94:	00038148 	.word	0x00038148
    4b98:	4000f000 	.word	0x4000f000
    4b9c:	40029000 	.word	0x40029000
    4ba0:	e000ed00 	.word	0xe000ed00
    4ba4:	0000b487 	.word	0x0000b487
    4ba8:	4001e000 	.word	0x4001e000
    4bac:	05fa0004 	.word	0x05fa0004
    4bb0:	20000140 	.word	0x20000140
    4bb4:	03d09000 	.word	0x03d09000

00004bb8 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    4bb8:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    4bba:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    4bbc:	6802      	ldr	r2, [r0, #0]
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    4bbe:	f3bf 8f5b 	dmb	ish
        idx = 31 - NRF_CLZ(prev_mask);
    4bc2:	fab2 f382 	clz	r3, r2
    4bc6:	f1c3 031f 	rsb	r3, r3, #31
    4bca:	b2db      	uxtb	r3, r3
        new_mask = prev_mask & ~NRFX_BIT(idx);
    4bcc:	fa05 f403 	lsl.w	r4, r5, r3
    4bd0:	ea22 0404 	bic.w	r4, r2, r4
    4bd4:	e850 6f00 	ldrex	r6, [r0]
    4bd8:	4296      	cmp	r6, r2
    4bda:	d104      	bne.n	4be6 <nrfx_flag32_alloc+0x2e>
    4bdc:	e840 4c00 	strex	ip, r4, [r0]
    4be0:	f1bc 0f00 	cmp.w	ip, #0
    4be4:	d1f6      	bne.n	4bd4 <nrfx_flag32_alloc+0x1c>
    4be6:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    4bea:	d1e7      	bne.n	4bbc <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
}
    4bec:	4801      	ldr	r0, [pc, #4]	; (4bf4 <nrfx_flag32_alloc+0x3c>)
    *p_flag = idx;
    4bee:	700b      	strb	r3, [r1, #0]
}
    4bf0:	bd70      	pop	{r4, r5, r6, pc}
    4bf2:	bf00      	nop
    4bf4:	0bad0000 	.word	0x0bad0000

00004bf8 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    4bf8:	b510      	push	{r4, lr}
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    4bfa:	6803      	ldr	r3, [r0, #0]
    4bfc:	40cb      	lsrs	r3, r1
    4bfe:	07db      	lsls	r3, r3, #31
    4c00:	d414      	bmi.n	4c2c <nrfx_flag32_free+0x34>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    4c02:	2301      	movs	r3, #1
    4c04:	408b      	lsls	r3, r1
        prev_mask = *p_mask;
    4c06:	6802      	ldr	r2, [r0, #0]
    4c08:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    4c0c:	ea43 0102 	orr.w	r1, r3, r2
    4c10:	e850 4f00 	ldrex	r4, [r0]
    4c14:	4294      	cmp	r4, r2
    4c16:	d104      	bne.n	4c22 <nrfx_flag32_free+0x2a>
    4c18:	e840 1c00 	strex	ip, r1, [r0]
    4c1c:	f1bc 0f00 	cmp.w	ip, #0
    4c20:	d1f6      	bne.n	4c10 <nrfx_flag32_free+0x18>
    4c22:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    4c26:	d1ee      	bne.n	4c06 <nrfx_flag32_free+0xe>

    return NRFX_SUCCESS;
    4c28:	4801      	ldr	r0, [pc, #4]	; (4c30 <nrfx_flag32_free+0x38>)
}
    4c2a:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    4c2c:	4801      	ldr	r0, [pc, #4]	; (4c34 <nrfx_flag32_free+0x3c>)
    4c2e:	e7fc      	b.n	4c2a <nrfx_flag32_free+0x32>
    4c30:	0bad0000 	.word	0x0bad0000
    4c34:	0bad0004 	.word	0x0bad0004

00004c38 <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    4c38:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    4c3a:	4604      	mov	r4, r0
    4c3c:	b118      	cbz	r0, 4c46 <clock_stop+0xe>
    4c3e:	2801      	cmp	r0, #1
    4c40:	d022      	beq.n	4c88 <clock_stop+0x50>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    4c42:	b003      	add	sp, #12
    4c44:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    4c46:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4c4a:	2202      	movs	r2, #2
    4c4c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4c50:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    4c54:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4c58:	2201      	movs	r2, #1
    4c5a:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    4c5c:	4607      	mov	r7, r0
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    4c5e:	2301      	movs	r3, #1
    4c60:	f88d 3007 	strb.w	r3, [sp, #7]
    4c64:	f242 7510 	movw	r5, #10000	; 0x2710
    4c68:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    4c6c:	b1cc      	cbz	r4, 4ca2 <clock_stop+0x6a>
    4c6e:	2c01      	cmp	r4, #1
    4c70:	d1e7      	bne.n	4c42 <clock_stop+0xa>
            if (p_clk_src != NULL)
    4c72:	b3c7      	cbz	r7, 4ce6 <clock_stop+0xae>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    4c74:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    4c78:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    4c7c:	703b      	strb	r3, [r7, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    4c7e:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    4c82:	03da      	lsls	r2, r3, #15
    4c84:	d521      	bpl.n	4cca <clock_stop+0x92>
    4c86:	e016      	b.n	4cb6 <clock_stop+0x7e>
    p_reg->INTENCLR = mask;
    4c88:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4c8c:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    4c8e:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4c92:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    4c96:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4c9a:	6058      	str	r0, [r3, #4]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    4c9c:	f10d 0707 	add.w	r7, sp, #7
    4ca0:	e7dd      	b.n	4c5e <clock_stop+0x26>
            if (p_clk_src != NULL)
    4ca2:	b1b7      	cbz	r7, 4cd2 <clock_stop+0x9a>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    4ca4:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    4ca8:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    4cac:	603b      	str	r3, [r7, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4cae:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    4cb2:	03d8      	lsls	r0, r3, #15
    4cb4:	d5c5      	bpl.n	4c42 <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    4cb6:	f89d 0007 	ldrb.w	r0, [sp, #7]
    4cba:	2801      	cmp	r0, #1
    4cbc:	d103      	bne.n	4cc6 <clock_stop+0x8e>
    4cbe:	f004 fd72 	bl	97a6 <nrfx_busy_wait>
    4cc2:	3d01      	subs	r5, #1
    4cc4:	d1d2      	bne.n	4c6c <clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    4cc6:	2c01      	cmp	r4, #1
    4cc8:	d1bb      	bne.n	4c42 <clock_stop+0xa>
            m_clock_cb.hfclk_started = false;
    4cca:	4b0c      	ldr	r3, [pc, #48]	; (4cfc <clock_stop+0xc4>)
    4ccc:	2200      	movs	r2, #0
    4cce:	715a      	strb	r2, [r3, #5]
    4cd0:	e7b7      	b.n	4c42 <clock_stop+0xa>
    4cd2:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    4cd6:	03d9      	lsls	r1, r3, #15
    4cd8:	d5b3      	bpl.n	4c42 <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    4cda:	2001      	movs	r0, #1
    4cdc:	f004 fd63 	bl	97a6 <nrfx_busy_wait>
    4ce0:	3d01      	subs	r5, #1
    4ce2:	d1f6      	bne.n	4cd2 <clock_stop+0x9a>
    4ce4:	e7ad      	b.n	4c42 <clock_stop+0xa>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    4ce6:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    4cea:	03db      	lsls	r3, r3, #15
    4cec:	d5ed      	bpl.n	4cca <clock_stop+0x92>
    4cee:	2001      	movs	r0, #1
    4cf0:	f004 fd59 	bl	97a6 <nrfx_busy_wait>
    4cf4:	3d01      	subs	r5, #1
    4cf6:	d1f6      	bne.n	4ce6 <clock_stop+0xae>
    4cf8:	e7e7      	b.n	4cca <clock_stop+0x92>
    4cfa:	bf00      	nop
    4cfc:	20001ea8 	.word	0x20001ea8

00004d00 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    4d00:	4b04      	ldr	r3, [pc, #16]	; (4d14 <nrfx_clock_init+0x14>)
    4d02:	791a      	ldrb	r2, [r3, #4]
    4d04:	b922      	cbnz	r2, 4d10 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    4d06:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    4d08:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    4d0a:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    4d0c:	4802      	ldr	r0, [pc, #8]	; (4d18 <nrfx_clock_init+0x18>)
    4d0e:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    4d10:	4802      	ldr	r0, [pc, #8]	; (4d1c <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    4d12:	4770      	bx	lr
    4d14:	20001ea8 	.word	0x20001ea8
    4d18:	0bad0000 	.word	0x0bad0000
    4d1c:	0bad000c 	.word	0x0bad000c

00004d20 <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    4d20:	b510      	push	{r4, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4d22:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4d26:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    4d2a:	b16a      	cbz	r2, 4d48 <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4d2c:	2200      	movs	r2, #0
    4d2e:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    4d32:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    4d36:	2201      	movs	r2, #1
    4d38:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    4d3c:	4b11      	ldr	r3, [pc, #68]	; (4d84 <nrfx_power_clock_irq_handler+0x64>)
    4d3e:	7958      	ldrb	r0, [r3, #5]
    4d40:	b910      	cbnz	r0, 4d48 <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    4d42:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    4d44:	681b      	ldr	r3, [r3, #0]
    4d46:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4d48:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4d4c:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    4d50:	b172      	cbz	r2, 4d70 <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4d52:	2200      	movs	r2, #0
    4d54:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    4d58:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    4d5c:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4d60:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    4d64:	0792      	lsls	r2, r2, #30
    4d66:	d104      	bne.n	4d72 <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    4d68:	2201      	movs	r2, #1
    4d6a:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4d6e:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    4d70:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    4d72:	2202      	movs	r2, #2
    4d74:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    4d78:	4b02      	ldr	r3, [pc, #8]	; (4d84 <nrfx_power_clock_irq_handler+0x64>)
}
    4d7a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    4d7e:	681b      	ldr	r3, [r3, #0]
    4d80:	2001      	movs	r0, #1
    4d82:	4718      	bx	r3
    4d84:	20001ea8 	.word	0x20001ea8

00004d88 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    4d88:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    4d8a:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    4d8e:	095b      	lsrs	r3, r3, #5
        case 0: return NRF_P0;
    4d90:	2b01      	cmp	r3, #1
    *p_pin = pin_number & 0x1F;
    4d92:	6002      	str	r2, [r0, #0]
}
    4d94:	4802      	ldr	r0, [pc, #8]	; (4da0 <nrf_gpio_pin_port_decode+0x18>)
    4d96:	bf18      	it	ne
    4d98:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    4d9c:	4770      	bx	lr
    4d9e:	bf00      	nop
    4da0:	50000300 	.word	0x50000300

00004da4 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    4da4:	4b03      	ldr	r3, [pc, #12]	; (4db4 <pin_in_use_by_te+0x10>)
    4da6:	3008      	adds	r0, #8
    4da8:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    4dac:	f3c0 1040 	ubfx	r0, r0, #5, #1
    4db0:	4770      	bx	lr
    4db2:	bf00      	nop
    4db4:	20000144 	.word	0x20000144

00004db8 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    4db8:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4dba:	f100 0308 	add.w	r3, r0, #8
    4dbe:	4c0c      	ldr	r4, [pc, #48]	; (4df0 <call_handler+0x38>)
    4dc0:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    4dc4:	05da      	lsls	r2, r3, #23
{
    4dc6:	4605      	mov	r5, r0
    4dc8:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4dca:	d507      	bpl.n	4ddc <call_handler+0x24>
    4dcc:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    4dd0:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    4dd4:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    4dd8:	6852      	ldr	r2, [r2, #4]
    4dda:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    4ddc:	68a3      	ldr	r3, [r4, #8]
    4dde:	b12b      	cbz	r3, 4dec <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    4de0:	68e2      	ldr	r2, [r4, #12]
    4de2:	4631      	mov	r1, r6
    4de4:	4628      	mov	r0, r5
    }
}
    4de6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    4dea:	4718      	bx	r3
}
    4dec:	bd70      	pop	{r4, r5, r6, pc}
    4dee:	bf00      	nop
    4df0:	20000144 	.word	0x20000144

00004df4 <release_handler>:
{
    4df4:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4df6:	4a13      	ldr	r2, [pc, #76]	; (4e44 <release_handler+0x50>)
    4df8:	3008      	adds	r0, #8
    4dfa:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    4dfe:	05d9      	lsls	r1, r3, #23
    4e00:	d51c      	bpl.n	4e3c <release_handler+0x48>
    4e02:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    4e06:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    4e0a:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    4e0e:	f102 040e 	add.w	r4, r2, #14
    4e12:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    4e14:	f834 3f02 	ldrh.w	r3, [r4, #2]!
    4e18:	f413 7f80 	tst.w	r3, #256	; 0x100
    4e1c:	d003      	beq.n	4e26 <release_handler+0x32>
    4e1e:	f3c3 2343 	ubfx	r3, r3, #9, #4
    4e22:	4299      	cmp	r1, r3
    4e24:	d00a      	beq.n	4e3c <release_handler+0x48>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    4e26:	3001      	adds	r0, #1
    4e28:	2830      	cmp	r0, #48	; 0x30
    4e2a:	d1f3      	bne.n	4e14 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    4e2c:	2300      	movs	r3, #0
    4e2e:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    4e32:	4805      	ldr	r0, [pc, #20]	; (4e48 <release_handler+0x54>)
}
    4e34:	f85d 4b04 	ldr.w	r4, [sp], #4
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    4e38:	f7ff bede 	b.w	4bf8 <nrfx_flag32_free>
}
    4e3c:	f85d 4b04 	ldr.w	r4, [sp], #4
    4e40:	4770      	bx	lr
    4e42:	bf00      	nop
    4e44:	20000144 	.word	0x20000144
    4e48:	200001b8 	.word	0x200001b8

00004e4c <pin_handler_trigger_uninit>:
{
    4e4c:	b538      	push	{r3, r4, r5, lr}
    4e4e:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    4e50:	f7ff ffa8 	bl	4da4 <pin_in_use_by_te>
    4e54:	4c09      	ldr	r4, [pc, #36]	; (4e7c <pin_handler_trigger_uninit+0x30>)
    4e56:	f102 0508 	add.w	r5, r2, #8
    4e5a:	b140      	cbz	r0, 4e6e <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    4e5c:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    4e60:	4907      	ldr	r1, [pc, #28]	; (4e80 <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    4e62:	0b5b      	lsrs	r3, r3, #13
    4e64:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    4e68:	2000      	movs	r0, #0
    4e6a:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    4e6e:	4610      	mov	r0, r2
    4e70:	f7ff ffc0 	bl	4df4 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    4e74:	2300      	movs	r3, #0
    4e76:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    4e7a:	bd38      	pop	{r3, r4, r5, pc}
    4e7c:	20000144 	.word	0x20000144
    4e80:	40006000 	.word	0x40006000

00004e84 <nrfx_gpiote_input_configure>:
{
    4e84:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    4e88:	4604      	mov	r4, r0
    4e8a:	4616      	mov	r6, r2
    4e8c:	461d      	mov	r5, r3
    if (p_input_config)
    4e8e:	b301      	cbz	r1, 4ed2 <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4e90:	4f4e      	ldr	r7, [pc, #312]	; (4fcc <nrfx_gpiote_input_configure+0x148>)
    4e92:	f100 0808 	add.w	r8, r0, #8
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    4e96:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    4e9a:	079b      	lsls	r3, r3, #30
    4e9c:	d502      	bpl.n	4ea4 <nrfx_gpiote_input_configure+0x20>
    4e9e:	f7ff ff81 	bl	4da4 <pin_in_use_by_te>
    4ea2:	bb10      	cbnz	r0, 4eea <nrfx_gpiote_input_configure+0x66>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    4ea4:	2300      	movs	r3, #0
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    4ea6:	e9cd 3300 	strd	r3, r3, [sp]
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    4eaa:	f88d 300e 	strb.w	r3, [sp, #14]
        nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT;
    4eae:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    4eb2:	f10d 020f 	add.w	r2, sp, #15
    4eb6:	460b      	mov	r3, r1
    4eb8:	4620      	mov	r0, r4
    4eba:	f10d 010e 	add.w	r1, sp, #14
    4ebe:	f004 fcbf 	bl	9840 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    4ec2:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    4ec6:	f023 0302 	bic.w	r3, r3, #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    4eca:	f043 0301 	orr.w	r3, r3, #1
    4ece:	f827 3018 	strh.w	r3, [r7, r8, lsl #1]
    if (p_trigger_config)
    4ed2:	b346      	cbz	r6, 4f26 <nrfx_gpiote_input_configure+0xa2>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4ed4:	4b3d      	ldr	r3, [pc, #244]	; (4fcc <nrfx_gpiote_input_configure+0x148>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    4ed6:	f896 c000 	ldrb.w	ip, [r6]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    4eda:	6872      	ldr	r2, [r6, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4edc:	f104 0708 	add.w	r7, r4, #8
    4ee0:	f833 1017 	ldrh.w	r1, [r3, r7, lsl #1]
        if (pin_is_output(pin))
    4ee4:	0788      	lsls	r0, r1, #30
    4ee6:	d502      	bpl.n	4eee <nrfx_gpiote_input_configure+0x6a>
            if (use_evt)
    4ee8:	b1aa      	cbz	r2, 4f16 <nrfx_gpiote_input_configure+0x92>
            return NRFX_ERROR_INVALID_PARAM;
    4eea:	4839      	ldr	r0, [pc, #228]	; (4fd0 <nrfx_gpiote_input_configure+0x14c>)
    4eec:	e01d      	b.n	4f2a <nrfx_gpiote_input_configure+0xa6>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    4eee:	f021 0120 	bic.w	r1, r1, #32
    4ef2:	04c9      	lsls	r1, r1, #19
    4ef4:	0cc9      	lsrs	r1, r1, #19
    4ef6:	f823 1017 	strh.w	r1, [r3, r7, lsl #1]
            if (use_evt)
    4efa:	b162      	cbz	r2, 4f16 <nrfx_gpiote_input_configure+0x92>
                if (!edge)
    4efc:	f1bc 0f03 	cmp.w	ip, #3
    4f00:	d8f3      	bhi.n	4eea <nrfx_gpiote_input_configure+0x66>
                uint8_t ch = *p_trigger_config->p_in_channel;
    4f02:	6872      	ldr	r2, [r6, #4]
    4f04:	7816      	ldrb	r6, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    4f06:	f1bc 0f00 	cmp.w	ip, #0
    4f0a:	d111      	bne.n	4f30 <nrfx_gpiote_input_configure+0xac>
    4f0c:	4a31      	ldr	r2, [pc, #196]	; (4fd4 <nrfx_gpiote_input_configure+0x150>)
    4f0e:	f506 76a2 	add.w	r6, r6, #324	; 0x144
    4f12:	f842 c026 	str.w	ip, [r2, r6, lsl #2]
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    4f16:	f833 2017 	ldrh.w	r2, [r3, r7, lsl #1]
    4f1a:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    4f1e:	ea42 028c 	orr.w	r2, r2, ip, lsl #2
    4f22:	f823 2017 	strh.w	r2, [r3, r7, lsl #1]
    if (p_handler_config)
    4f26:	bb45      	cbnz	r5, 4f7a <nrfx_gpiote_input_configure+0xf6>
        err = NRFX_SUCCESS;
    4f28:	482b      	ldr	r0, [pc, #172]	; (4fd8 <nrfx_gpiote_input_configure+0x154>)
}
    4f2a:	b004      	add	sp, #16
    4f2c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    4f30:	00b2      	lsls	r2, r6, #2
    4f32:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    4f36:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    4f3a:	ea41 3146 	orr.w	r1, r1, r6, lsl #13
    4f3e:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    4f42:	f020 0003 	bic.w	r0, r0, #3
    4f46:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    4f4a:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    4f4e:	f420 304f 	bic.w	r0, r0, #211968	; 0x33c00
    4f52:	f420 7040 	bic.w	r0, r0, #768	; 0x300
    4f56:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    4f5a:	0220      	lsls	r0, r4, #8
    4f5c:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    4f60:	f400 507c 	and.w	r0, r0, #16128	; 0x3f00
    4f64:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
    4f68:	ea40 000e 	orr.w	r0, r0, lr
    4f6c:	f041 0120 	orr.w	r1, r1, #32
    4f70:	f823 1017 	strh.w	r1, [r3, r7, lsl #1]
    4f74:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
    4f78:	e7cd      	b.n	4f16 <nrfx_gpiote_input_configure+0x92>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    4f7a:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    4f7e:	4620      	mov	r0, r4
    4f80:	f7ff ff38 	bl	4df4 <release_handler>
    if (!handler)
    4f84:	2e00      	cmp	r6, #0
    4f86:	d0cf      	beq.n	4f28 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    4f88:	4d10      	ldr	r5, [pc, #64]	; (4fcc <nrfx_gpiote_input_configure+0x148>)
    4f8a:	e9d5 2300 	ldrd	r2, r3, [r5]
    4f8e:	4296      	cmp	r6, r2
    4f90:	d101      	bne.n	4f96 <nrfx_gpiote_input_configure+0x112>
    4f92:	429f      	cmp	r7, r3
    4f94:	d018      	beq.n	4fc8 <nrfx_gpiote_input_configure+0x144>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    4f96:	4811      	ldr	r0, [pc, #68]	; (4fdc <nrfx_gpiote_input_configure+0x158>)
    4f98:	f10d 010f 	add.w	r1, sp, #15
    4f9c:	f7ff fe0c 	bl	4bb8 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    4fa0:	4b0d      	ldr	r3, [pc, #52]	; (4fd8 <nrfx_gpiote_input_configure+0x154>)
    4fa2:	4298      	cmp	r0, r3
    4fa4:	d1c1      	bne.n	4f2a <nrfx_gpiote_input_configure+0xa6>
        handler_id = (int32_t)id;
    4fa6:	f89d 200f 	ldrb.w	r2, [sp, #15]
    m_cb.handlers[handler_id].handler = handler;
    4faa:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    4fae:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    4fb2:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    4fb4:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    4fb6:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    4fba:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    4fbe:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    4fc2:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    return NRFX_SUCCESS;
    4fc6:	e7af      	b.n	4f28 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    4fc8:	2200      	movs	r2, #0
    4fca:	e7ee      	b.n	4faa <nrfx_gpiote_input_configure+0x126>
    4fcc:	20000144 	.word	0x20000144
    4fd0:	0bad0004 	.word	0x0bad0004
    4fd4:	40006000 	.word	0x40006000
    4fd8:	0bad0000 	.word	0x0bad0000
    4fdc:	200001b8 	.word	0x200001b8

00004fe0 <nrfx_gpiote_output_configure>:
{
    4fe0:	b5f0      	push	{r4, r5, r6, r7, lr}
    4fe2:	4604      	mov	r4, r0
    4fe4:	b085      	sub	sp, #20
    4fe6:	4615      	mov	r5, r2
    if (p_config)
    4fe8:	b319      	cbz	r1, 5032 <nrfx_gpiote_output_configure+0x52>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4fea:	4e33      	ldr	r6, [pc, #204]	; (50b8 <nrfx_gpiote_output_configure+0xd8>)
    4fec:	f100 0708 	add.w	r7, r0, #8
    4ff0:	f836 2017 	ldrh.w	r2, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    4ff4:	0793      	lsls	r3, r2, #30
    4ff6:	d403      	bmi.n	5000 <nrfx_gpiote_output_configure+0x20>
    4ff8:	f7ff fed4 	bl	4da4 <pin_in_use_by_te>
    4ffc:	2800      	cmp	r0, #0
    4ffe:	d158      	bne.n	50b2 <nrfx_gpiote_output_configure+0xd2>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    5000:	f012 0f1c 	tst.w	r2, #28
    5004:	d002      	beq.n	500c <nrfx_gpiote_output_configure+0x2c>
    5006:	784b      	ldrb	r3, [r1, #1]
    5008:	2b01      	cmp	r3, #1
    500a:	d052      	beq.n	50b2 <nrfx_gpiote_output_configure+0xd2>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT;
    500c:	2301      	movs	r3, #1
    500e:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull,
    5012:	2300      	movs	r3, #0
    5014:	e9cd 1300 	strd	r1, r3, [sp]
    5018:	1c4a      	adds	r2, r1, #1
    501a:	1c8b      	adds	r3, r1, #2
    501c:	4620      	mov	r0, r4
    501e:	f10d 010f 	add.w	r1, sp, #15
    5022:	f004 fc0d 	bl	9840 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    5026:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    502a:	f043 0303 	orr.w	r3, r3, #3
    502e:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_task_config)
    5032:	b915      	cbnz	r5, 503a <nrfx_gpiote_output_configure+0x5a>
    return NRFX_SUCCESS;
    5034:	4821      	ldr	r0, [pc, #132]	; (50bc <nrfx_gpiote_output_configure+0xdc>)
}
    5036:	b005      	add	sp, #20
    5038:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    503a:	4e1f      	ldr	r6, [pc, #124]	; (50b8 <nrfx_gpiote_output_configure+0xd8>)
    503c:	f104 0708 	add.w	r7, r4, #8
    5040:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    5044:	0783      	lsls	r3, r0, #30
    5046:	d534      	bpl.n	50b2 <nrfx_gpiote_output_configure+0xd2>
        uint32_t ch = p_task_config->task_ch;
    5048:	f895 c000 	ldrb.w	ip, [r5]
    p_reg->CONFIG[idx] = 0;
    504c:	4661      	mov	r1, ip
    504e:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    5050:	f020 0020 	bic.w	r0, r0, #32
    5054:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    5058:	04c0      	lsls	r0, r0, #19
    505a:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    505e:	0cc0      	lsrs	r0, r0, #19
    5060:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    5064:	2300      	movs	r3, #0
    5066:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    506a:	786a      	ldrb	r2, [r5, #1]
    506c:	2a00      	cmp	r2, #0
    506e:	d0e1      	beq.n	5034 <nrfx_gpiote_output_configure+0x54>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    5070:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
                                      p_task_config->init_val);
    5074:	78ad      	ldrb	r5, [r5, #2]
    5076:	f423 1399 	bic.w	r3, r3, #1253376	; 0x132000
    507a:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    507e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    5082:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    5086:	0223      	lsls	r3, r4, #8
    5088:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    508c:	0412      	lsls	r2, r2, #16
    508e:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    5092:	ea43 030e 	orr.w	r3, r3, lr
    5096:	4313      	orrs	r3, r2
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    5098:	052a      	lsls	r2, r5, #20
    509a:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    509e:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    50a2:	4313      	orrs	r3, r2
    50a4:	f040 0020 	orr.w	r0, r0, #32
    50a8:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    50ac:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    50b0:	e7c0      	b.n	5034 <nrfx_gpiote_output_configure+0x54>
{
    50b2:	4803      	ldr	r0, [pc, #12]	; (50c0 <nrfx_gpiote_output_configure+0xe0>)
    50b4:	e7bf      	b.n	5036 <nrfx_gpiote_output_configure+0x56>
    50b6:	bf00      	nop
    50b8:	20000144 	.word	0x20000144
    50bc:	0bad0000 	.word	0x0bad0000
    50c0:	0bad0004 	.word	0x0bad0004

000050c4 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    50c4:	4b01      	ldr	r3, [pc, #4]	; (50cc <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    50c6:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    50ca:	4770      	bx	lr
    50cc:	20000144 	.word	0x20000144

000050d0 <nrfx_gpiote_channel_get>:
{
    50d0:	b508      	push	{r3, lr}
    50d2:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    50d4:	f7ff fe66 	bl	4da4 <pin_in_use_by_te>
    50d8:	b138      	cbz	r0, 50ea <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    50da:	4b05      	ldr	r3, [pc, #20]	; (50f0 <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    50dc:	4805      	ldr	r0, [pc, #20]	; (50f4 <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    50de:	3208      	adds	r2, #8
    50e0:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    50e4:	0b5b      	lsrs	r3, r3, #13
    50e6:	700b      	strb	r3, [r1, #0]
}
    50e8:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    50ea:	4803      	ldr	r0, [pc, #12]	; (50f8 <nrfx_gpiote_channel_get+0x28>)
    50ec:	e7fc      	b.n	50e8 <nrfx_gpiote_channel_get+0x18>
    50ee:	bf00      	nop
    50f0:	20000144 	.word	0x20000144
    50f4:	0bad0000 	.word	0x0bad0000
    50f8:	0bad0004 	.word	0x0bad0004

000050fc <nrfx_gpiote_init>:
{
    50fc:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    50fe:	4c0f      	ldr	r4, [pc, #60]	; (513c <nrfx_gpiote_init+0x40>)
    5100:	f894 5078 	ldrb.w	r5, [r4, #120]	; 0x78
    5104:	b9bd      	cbnz	r5, 5136 <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    5106:	2260      	movs	r2, #96	; 0x60
    5108:	4629      	mov	r1, r5
    510a:	f104 0010 	add.w	r0, r4, #16
    510e:	f003 fe9d 	bl	8e4c <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    5112:	2006      	movs	r0, #6
    5114:	f7fc ff60 	bl	1fd8 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    5118:	4b09      	ldr	r3, [pc, #36]	; (5140 <nrfx_gpiote_init+0x44>)
    return err_code;
    511a:	480a      	ldr	r0, [pc, #40]	; (5144 <nrfx_gpiote_init+0x48>)
    511c:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    5120:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    5124:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    5128:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    512c:	2301      	movs	r3, #1
    512e:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    5132:	6763      	str	r3, [r4, #116]	; 0x74
}
    5134:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    5136:	4804      	ldr	r0, [pc, #16]	; (5148 <nrfx_gpiote_init+0x4c>)
    5138:	e7fc      	b.n	5134 <nrfx_gpiote_init+0x38>
    513a:	bf00      	nop
    513c:	20000144 	.word	0x20000144
    5140:	40006000 	.word	0x40006000
    5144:	0bad0000 	.word	0x0bad0000
    5148:	0bad0005 	.word	0x0bad0005

0000514c <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    514c:	4b03      	ldr	r3, [pc, #12]	; (515c <nrfx_gpiote_is_init+0x10>)
    514e:	f893 0078 	ldrb.w	r0, [r3, #120]	; 0x78
}
    5152:	3800      	subs	r0, #0
    5154:	bf18      	it	ne
    5156:	2001      	movne	r0, #1
    5158:	4770      	bx	lr
    515a:	bf00      	nop
    515c:	20000144 	.word	0x20000144

00005160 <nrfx_gpiote_channel_free>:
{
    5160:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    5162:	4801      	ldr	r0, [pc, #4]	; (5168 <nrfx_gpiote_channel_free+0x8>)
    5164:	f7ff bd48 	b.w	4bf8 <nrfx_flag32_free>
    5168:	200001b4 	.word	0x200001b4

0000516c <nrfx_gpiote_channel_alloc>:
{
    516c:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    516e:	4801      	ldr	r0, [pc, #4]	; (5174 <nrfx_gpiote_channel_alloc+0x8>)
    5170:	f7ff bd22 	b.w	4bb8 <nrfx_flag32_alloc>
    5174:	200001b4 	.word	0x200001b4

00005178 <nrfx_gpiote_trigger_enable>:
{
    5178:	b537      	push	{r0, r1, r2, r4, r5, lr}
    517a:	4604      	mov	r4, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    517c:	f7ff fe12 	bl	4da4 <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    5180:	f104 0208 	add.w	r2, r4, #8
    5184:	4b1e      	ldr	r3, [pc, #120]	; (5200 <nrfx_gpiote_trigger_enable+0x88>)
    5186:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    518a:	b1e8      	cbz	r0, 51c8 <nrfx_gpiote_trigger_enable+0x50>
    518c:	f013 0502 	ands.w	r5, r3, #2
    5190:	d11a      	bne.n	51c8 <nrfx_gpiote_trigger_enable+0x50>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    5192:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    5194:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    5196:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    519a:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    519e:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    51a2:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    51a6:	6005      	str	r5, [r0, #0]
    51a8:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    51aa:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    51ae:	f040 0001 	orr.w	r0, r0, #1
    51b2:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    51b6:	b129      	cbz	r1, 51c4 <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    51b8:	2201      	movs	r2, #1
    51ba:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    51be:	4a11      	ldr	r2, [pc, #68]	; (5204 <nrfx_gpiote_trigger_enable+0x8c>)
    51c0:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    51c4:	b003      	add	sp, #12
    51c6:	bd30      	pop	{r4, r5, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    51c8:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    51cc:	2b04      	cmp	r3, #4
    51ce:	d012      	beq.n	51f6 <nrfx_gpiote_trigger_enable+0x7e>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    51d0:	2b05      	cmp	r3, #5
    51d2:	d012      	beq.n	51fa <nrfx_gpiote_trigger_enable+0x82>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    51d4:	a801      	add	r0, sp, #4
    51d6:	9401      	str	r4, [sp, #4]
    51d8:	f7ff fdd6 	bl	4d88 <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    51dc:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    51de:	f8d0 1510 	ldr.w	r1, [r0, #1296]	; 0x510
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    51e2:	40d9      	lsrs	r1, r3
    51e4:	f001 0101 	and.w	r1, r1, #1
    51e8:	3102      	adds	r1, #2
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    51ea:	4620      	mov	r0, r4
}
    51ec:	b003      	add	sp, #12
    51ee:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    51f2:	f004 bb6e 	b.w	98d2 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    51f6:	2103      	movs	r1, #3
    51f8:	e7f7      	b.n	51ea <nrfx_gpiote_trigger_enable+0x72>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    51fa:	2102      	movs	r1, #2
    51fc:	e7f5      	b.n	51ea <nrfx_gpiote_trigger_enable+0x72>
    51fe:	bf00      	nop
    5200:	20000144 	.word	0x20000144
    5204:	40006000 	.word	0x40006000

00005208 <nrfx_gpiote_trigger_disable>:
{
    5208:	b508      	push	{r3, lr}
    520a:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    520c:	f7ff fdca 	bl	4da4 <pin_in_use_by_te>
    5210:	b1c0      	cbz	r0, 5244 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    5212:	f102 0108 	add.w	r1, r2, #8
    5216:	4b0e      	ldr	r3, [pc, #56]	; (5250 <nrfx_gpiote_trigger_disable+0x48>)
    5218:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    521c:	0799      	lsls	r1, r3, #30
    521e:	d411      	bmi.n	5244 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    5220:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    5222:	2201      	movs	r2, #1
    5224:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    5226:	009b      	lsls	r3, r3, #2
    5228:	490a      	ldr	r1, [pc, #40]	; (5254 <nrfx_gpiote_trigger_disable+0x4c>)
    522a:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    522e:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    5232:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    5236:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    523a:	f022 0203 	bic.w	r2, r2, #3
    523e:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    5242:	bd08      	pop	{r3, pc}
    5244:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    5248:	2100      	movs	r1, #0
    524a:	4610      	mov	r0, r2
    524c:	f004 bb41 	b.w	98d2 <nrf_gpio_cfg_sense_set>
    5250:	20000144 	.word	0x20000144
    5254:	40006000 	.word	0x40006000

00005258 <nrfx_gpiote_pin_uninit>:
{
    5258:	b513      	push	{r0, r1, r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    525a:	4b0e      	ldr	r3, [pc, #56]	; (5294 <nrfx_gpiote_pin_uninit+0x3c>)
    525c:	f100 0208 	add.w	r2, r0, #8
{
    5260:	4604      	mov	r4, r0
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    5262:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    5266:	07db      	lsls	r3, r3, #31
    5268:	d511      	bpl.n	528e <nrfx_gpiote_pin_uninit+0x36>
    nrfx_gpiote_trigger_disable(pin);
    526a:	f7ff ffcd 	bl	5208 <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    526e:	4620      	mov	r0, r4
    5270:	f7ff fdec 	bl	4e4c <pin_handler_trigger_uninit>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5274:	a801      	add	r0, sp, #4
    5276:	9401      	str	r4, [sp, #4]
    5278:	f7ff fd86 	bl	4d88 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    527c:	9b01      	ldr	r3, [sp, #4]
    527e:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    5282:	2202      	movs	r2, #2
    5284:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
    nrf_gpio_cfg(
    5288:	4803      	ldr	r0, [pc, #12]	; (5298 <nrfx_gpiote_pin_uninit+0x40>)
}
    528a:	b002      	add	sp, #8
    528c:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    528e:	4803      	ldr	r0, [pc, #12]	; (529c <nrfx_gpiote_pin_uninit+0x44>)
    5290:	e7fb      	b.n	528a <nrfx_gpiote_pin_uninit+0x32>
    5292:	bf00      	nop
    5294:	20000144 	.word	0x20000144
    5298:	0bad0000 	.word	0x0bad0000
    529c:	0bad0004 	.word	0x0bad0004

000052a0 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    52a0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    52a4:	4b68      	ldr	r3, [pc, #416]	; (5448 <nrfx_gpiote_irq_handler+0x1a8>)
    return p_reg->INTENSET & mask;
    52a6:	4869      	ldr	r0, [pc, #420]	; (544c <nrfx_gpiote_irq_handler+0x1ac>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    52a8:	4969      	ldr	r1, [pc, #420]	; (5450 <nrfx_gpiote_irq_handler+0x1b0>)
    uint32_t status = 0;
    52aa:	2600      	movs	r6, #0
{
    52ac:	b087      	sub	sp, #28
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    52ae:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    52b0:	4634      	mov	r4, r6
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    52b2:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    52b4:	b135      	cbz	r5, 52c4 <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    52b6:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    52ba:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    52bc:	bf1e      	ittt	ne
    52be:	601c      	strne	r4, [r3, #0]
    52c0:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    52c2:	4316      	orrne	r6, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    52c4:	3304      	adds	r3, #4
    52c6:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    52c8:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    52cc:	d1f1      	bne.n	52b2 <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    52ce:	f8df 917c 	ldr.w	r9, [pc, #380]	; 544c <nrfx_gpiote_irq_handler+0x1ac>
    52d2:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    52d6:	2b00      	cmp	r3, #0
    52d8:	f000 8099 	beq.w	540e <nrfx_gpiote_irq_handler+0x16e>
        *p_masks = gpio_regs[i]->LATCH;
    52dc:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    52e0:	f8d3 2520 	ldr.w	r2, [r3, #1312]	; 0x520
    52e4:	9204      	str	r2, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    52e6:	f8c3 2520 	str.w	r2, [r3, #1312]	; 0x520
        *p_masks = gpio_regs[i]->LATCH;
    52ea:	f8d3 2820 	ldr.w	r2, [r3, #2080]	; 0x820
    52ee:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    52f0:	f8c3 2820 	str.w	r2, [r3, #2080]	; 0x820
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    52f4:	f04f 0800 	mov.w	r8, #0
            while (latch[i])
    52f8:	f10d 0a10 	add.w	sl, sp, #16
    52fc:	ea4f 1348 	mov.w	r3, r8, lsl #5
    5300:	9300      	str	r3, [sp, #0]
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    5302:	f04f 0b01 	mov.w	fp, #1
    5306:	e049      	b.n	539c <nrfx_gpiote_irq_handler+0xfc>
                pin += 32 * i;
    5308:	9b00      	ldr	r3, [sp, #0]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    530a:	4a52      	ldr	r2, [pc, #328]	; (5454 <nrfx_gpiote_irq_handler+0x1b4>)
                uint32_t pin = NRF_CTZ(latch[i]);
    530c:	fa94 f4a4 	rbit	r4, r4
    5310:	fab4 f484 	clz	r4, r4
                pin += 32 * i;
    5314:	441c      	add	r4, r3
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    5316:	08e0      	lsrs	r0, r4, #3
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    5318:	f104 0308 	add.w	r3, r4, #8
    531c:	9403      	str	r4, [sp, #12]
    531e:	f832 7013 	ldrh.w	r7, [r2, r3, lsl #1]
    p_mask8[byte_idx] &= ~(1 << bit);
    5322:	f81a 3000 	ldrb.w	r3, [sl, r0]
    bit = BITMASK_RELBIT_GET(bit);
    5326:	f004 0207 	and.w	r2, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    532a:	fa0b f202 	lsl.w	r2, fp, r2
    532e:	ea23 0302 	bic.w	r3, r3, r2
    5332:	f80a 3000 	strb.w	r3, [sl, r0]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5336:	a803      	add	r0, sp, #12
    5338:	f7ff fd26 	bl	4d88 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    533c:	9b03      	ldr	r3, [sp, #12]
    533e:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    5342:	08b9      	lsrs	r1, r7, #2
    5344:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    5348:	f3c7 0582 	ubfx	r5, r7, #2, #3
    if (is_level(trigger))
    534c:	074a      	lsls	r2, r1, #29
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    534e:	462f      	mov	r7, r5
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    5350:	f3c3 4301 	ubfx	r3, r3, #16, #2
    if (is_level(trigger))
    5354:	d52c      	bpl.n	53b0 <nrfx_gpiote_irq_handler+0x110>
        call_handler(pin, trigger);
    5356:	4620      	mov	r0, r4
    5358:	4639      	mov	r1, r7
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    535a:	b2dd      	uxtb	r5, r3
    535c:	f7ff fd2c 	bl	4db8 <call_handler>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5360:	a803      	add	r0, sp, #12
    5362:	9403      	str	r4, [sp, #12]
    5364:	f7ff fd10 	bl	4d88 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    5368:	9b03      	ldr	r3, [sp, #12]
    536a:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    536e:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
        if (nrf_gpio_pin_sense_get(pin) == sense)
    5372:	f3c3 4301 	ubfx	r3, r3, #16, #2
    5376:	429d      	cmp	r5, r3
    5378:	d107      	bne.n	538a <nrfx_gpiote_irq_handler+0xea>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    537a:	2100      	movs	r1, #0
    537c:	4620      	mov	r0, r4
    537e:	f004 faa8 	bl	98d2 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    5382:	4629      	mov	r1, r5
    5384:	4620      	mov	r0, r4
    5386:	f004 faa4 	bl	98d2 <nrf_gpio_cfg_sense_set>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    538a:	a803      	add	r0, sp, #12
    538c:	9403      	str	r4, [sp, #12]
    538e:	f7ff fcfb 	bl	4d88 <nrf_gpio_pin_port_decode>
    reg->LATCH = (1 << pin_number);
    5392:	9b03      	ldr	r3, [sp, #12]
    5394:	fa0b f303 	lsl.w	r3, fp, r3
    5398:	f8c0 3520 	str.w	r3, [r0, #1312]	; 0x520
            while (latch[i])
    539c:	f85a 4028 	ldr.w	r4, [sl, r8, lsl #2]
    53a0:	2c00      	cmp	r4, #0
    53a2:	d1b1      	bne.n	5308 <nrfx_gpiote_irq_handler+0x68>
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    53a4:	f1b8 0f00 	cmp.w	r8, #0
    53a8:	d11d      	bne.n	53e6 <nrfx_gpiote_irq_handler+0x146>
    53aa:	f04f 0801 	mov.w	r8, #1
    53ae:	e7a5      	b.n	52fc <nrfx_gpiote_irq_handler+0x5c>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    53b0:	2b02      	cmp	r3, #2
    53b2:	d10c      	bne.n	53ce <nrfx_gpiote_irq_handler+0x12e>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    53b4:	2103      	movs	r1, #3
    53b6:	4620      	mov	r0, r4
    53b8:	f004 fa8b 	bl	98d2 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    53bc:	f005 0305 	and.w	r3, r5, #5
    53c0:	2b01      	cmp	r3, #1
    53c2:	d1e2      	bne.n	538a <nrfx_gpiote_irq_handler+0xea>
            call_handler(pin, trigger);
    53c4:	4639      	mov	r1, r7
    53c6:	4620      	mov	r0, r4
    53c8:	f7ff fcf6 	bl	4db8 <call_handler>
    53cc:	e7dd      	b.n	538a <nrfx_gpiote_irq_handler+0xea>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    53ce:	2102      	movs	r1, #2
    53d0:	4620      	mov	r0, r4
    53d2:	9301      	str	r3, [sp, #4]
    53d4:	f004 fa7d 	bl	98d2 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    53d8:	2d03      	cmp	r5, #3
    53da:	d0f3      	beq.n	53c4 <nrfx_gpiote_irq_handler+0x124>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    53dc:	9b01      	ldr	r3, [sp, #4]
    53de:	2b03      	cmp	r3, #3
    53e0:	d1d3      	bne.n	538a <nrfx_gpiote_irq_handler+0xea>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    53e2:	2d02      	cmp	r5, #2
    53e4:	e7ed      	b.n	53c2 <nrfx_gpiote_irq_handler+0x122>
        *p_masks = gpio_regs[i]->LATCH;
    53e6:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    53ea:	f8c9 417c 	str.w	r4, [r9, #380]	; 0x17c
    53ee:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
    53f2:	4919      	ldr	r1, [pc, #100]	; (5458 <nrfx_gpiote_irq_handler+0x1b8>)
    53f4:	f8d2 3520 	ldr.w	r3, [r2, #1312]	; 0x520
    53f8:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    53fa:	f8c2 3520 	str.w	r3, [r2, #1312]	; 0x520
        *p_masks = gpio_regs[i]->LATCH;
    53fe:	f8d1 2520 	ldr.w	r2, [r1, #1312]	; 0x520
    5402:	9205      	str	r2, [sp, #20]
        if (latch[port_idx])
    5404:	4313      	orrs	r3, r2
        gpio_regs[i]->LATCH = *p_masks;
    5406:	f8c1 2520 	str.w	r2, [r1, #1312]	; 0x520
    540a:	f47f af73 	bne.w	52f4 <nrfx_gpiote_irq_handler+0x54>
        mask &= ~NRFX_BIT(ch);
    540e:	2401      	movs	r4, #1
    while (mask)
    5410:	b916      	cbnz	r6, 5418 <nrfx_gpiote_irq_handler+0x178>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    5412:	b007      	add	sp, #28
    5414:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t ch = NRF_CTZ(mask);
    5418:	fa96 f3a6 	rbit	r3, r6
    541c:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    5420:	fa04 f203 	lsl.w	r2, r4, r3
    5424:	009b      	lsls	r3, r3, #2
    5426:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    542a:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    542e:	ea26 0602 	bic.w	r6, r6, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    5432:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    5436:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    543a:	f3c0 2005 	ubfx	r0, r0, #8, #6
    543e:	f3c1 4101 	ubfx	r1, r1, #16, #2
    5442:	f7ff fcb9 	bl	4db8 <call_handler>
    5446:	e7e3      	b.n	5410 <nrfx_gpiote_irq_handler+0x170>
    5448:	40006100 	.word	0x40006100
    544c:	40006000 	.word	0x40006000
    5450:	40006120 	.word	0x40006120
    5454:	20000144 	.word	0x20000144
    5458:	50000300 	.word	0x50000300

0000545c <nvmc_word_write>:
    545c:	4a04      	ldr	r2, [pc, #16]	; (5470 <nvmc_word_write+0x14>)
    545e:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
{
#if defined(NRF9160_XXAA)
    while (!nrf_nvmc_write_ready_check(NRF_NVMC))
    {}
#else
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    5462:	07db      	lsls	r3, r3, #31
    5464:	d5fb      	bpl.n	545e <nvmc_word_write+0x2>
    {}
#endif

    *(volatile uint32_t *)addr = value;
    5466:	6001      	str	r1, [r0, #0]
  __ASM volatile ("dmb 0xF":::"memory");
    5468:	f3bf 8f5f 	dmb	sy
    __DMB();
}
    546c:	4770      	bx	lr
    546e:	bf00      	nop
    5470:	4001e000 	.word	0x4001e000

00005474 <nrfx_nvmc_page_erase>:
NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk)
    return p_reg->INFO.CODEPAGESIZE;
#else
    return p_reg->CODEPAGESIZE;
    5474:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    5478:	691a      	ldr	r2, [r3, #16]
    return !(addr % flash_page_size_get());
    547a:	fbb0 f3f2 	udiv	r3, r0, r2
    547e:	fb02 0313 	mls	r3, r2, r3, r0

nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
    NRFX_ASSERT(is_valid_address(addr, false));

    if (!is_page_aligned_check(addr))
    5482:	b973      	cbnz	r3, 54a2 <nrfx_nvmc_page_erase+0x2e>
#endif

NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
                                         nrf_nvmc_mode_t mode)
{
    p_reg->CONFIG = (uint32_t)mode;
    5484:	4b08      	ldr	r3, [pc, #32]	; (54a8 <nrfx_nvmc_page_erase+0x34>)
    5486:	2202      	movs	r2, #2
    5488:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    else
    {
        p_reg->ERASEPCR1 = page_addr;
    }
#elif defined(NRF52_SERIES)
    p_reg->ERASEPAGE = page_addr;
    548c:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    5490:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
        return NRFX_ERROR_INVALID_ADDR;
    }

    nvmc_erase_mode_set();
    nrf_nvmc_page_erase_start(NRF_NVMC, addr);
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    5494:	07d2      	lsls	r2, r2, #31
    5496:	d5fb      	bpl.n	5490 <nrfx_nvmc_page_erase+0x1c>
    p_reg->CONFIG = (uint32_t)mode;
    5498:	2200      	movs	r2, #0
    {}
    nvmc_readonly_mode_set();

    return NRFX_SUCCESS;
    549a:	4804      	ldr	r0, [pc, #16]	; (54ac <nrfx_nvmc_page_erase+0x38>)
    549c:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    54a0:	4770      	bx	lr
        return NRFX_ERROR_INVALID_ADDR;
    54a2:	4803      	ldr	r0, [pc, #12]	; (54b0 <nrfx_nvmc_page_erase+0x3c>)
}
    54a4:	4770      	bx	lr
    54a6:	bf00      	nop
    54a8:	4001e000 	.word	0x4001e000
    54ac:	0bad0000 	.word	0x0bad0000
    54b0:	0bad000a 	.word	0x0bad000a

000054b4 <nrfx_nvmc_word_write>:

    nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
}

void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
    54b4:	b510      	push	{r4, lr}
    54b6:	4c05      	ldr	r4, [pc, #20]	; (54cc <nrfx_nvmc_word_write+0x18>)
    54b8:	2301      	movs	r3, #1
    54ba:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504
    NRFX_ASSERT(is_valid_address(addr, true));
    NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));

    nvmc_write_mode_set();

    nvmc_word_write(addr, value);
    54be:	f7ff ffcd 	bl	545c <nvmc_word_write>
    54c2:	2300      	movs	r3, #0
    54c4:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504

    nvmc_readonly_mode_set();
}
    54c8:	bd10      	pop	{r4, pc}
    54ca:	bf00      	nop
    54cc:	4001e000 	.word	0x4001e000

000054d0 <nrfx_ppi_channel_alloc>:
    nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK);
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    54d0:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel);
    54d2:	4801      	ldr	r0, [pc, #4]	; (54d8 <nrfx_ppi_channel_alloc+0x8>)
    54d4:	f7ff bb70 	b.w	4bb8 <nrfx_flag32_alloc>
    54d8:	200001c0 	.word	0x200001c0

000054dc <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    54dc:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    54de:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    54e2:	095b      	lsrs	r3, r3, #5
        case 0: return NRF_P0;
    54e4:	2b01      	cmp	r3, #1
    *p_pin = pin_number & 0x1F;
    54e6:	6002      	str	r2, [r0, #0]
}
    54e8:	4802      	ldr	r0, [pc, #8]	; (54f4 <nrf_gpio_pin_port_decode+0x18>)
    54ea:	bf18      	it	ne
    54ec:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    54f0:	4770      	bx	lr
    54f2:	bf00      	nop
    54f4:	50000300 	.word	0x50000300

000054f8 <nrfx_spi_init>:

nrfx_err_t nrfx_spi_init(nrfx_spi_t const *        p_instance,
                         nrfx_spi_config_t const * p_config,
                         nrfx_spi_evt_handler_t    handler,
                         void *                    p_context)
{
    54f8:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    NRFX_ASSERT(p_config);
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    54fc:	7907      	ldrb	r7, [r0, #4]
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    nrfx_err_t err_code;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    54fe:	4c52      	ldr	r4, [pc, #328]	; (5648 <nrfx_spi_init+0x150>)
    5500:	f04f 0c28 	mov.w	ip, #40	; 0x28
    5504:	fb0c fc07 	mul.w	ip, ip, r7
{
    5508:	4606      	mov	r6, r0
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    550a:	eb04 000c 	add.w	r0, r4, ip
    550e:	7f05      	ldrb	r5, [r0, #28]
    5510:	2d00      	cmp	r5, #0
    5512:	f040 8096 	bne.w	5642 <nrfx_spi_init+0x14a>
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    5516:	6835      	ldr	r5, [r6, #0]
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)

    p_cb->handler = handler;
    5518:	f844 200c 	str.w	r2, [r4, ip]
    p_cb->p_context = p_context;
    551c:	6043      	str	r3, [r0, #4]

    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
    551e:	7bcb      	ldrb	r3, [r1, #15]
    5520:	f880 3025 	strb.w	r3, [r0, #37]	; 0x25
    p_cb->ss_pin = p_config->ss_pin;
    5524:	78cb      	ldrb	r3, [r1, #3]
    5526:	7783      	strb	r3, [r0, #30]
    p_cb->orc = p_config->orc;
    5528:	794b      	ldrb	r3, [r1, #5]
    552a:	77c3      	strb	r3, [r0, #31]
    if (!p_config->skip_gpio_cfg)
    552c:	7bcb      	ldrb	r3, [r1, #15]
    552e:	2b00      	cmp	r3, #0
    5530:	d140      	bne.n	55b4 <nrfx_spi_init+0xbc>
    if (value == 0)
    5532:	7b0b      	ldrb	r3, [r1, #12]
        nrf_gpio_pin_write(p_config->sck_pin,
    5534:	7808      	ldrb	r0, [r1, #0]
    5536:	2b01      	cmp	r3, #1
    5538:	d87a      	bhi.n	5630 <nrfx_spi_init+0x138>
        nrf_gpio_pin_clear(pin_number);
    553a:	f004 fa02 	bl	9942 <nrf_gpio_pin_clear>
        nrf_gpio_cfg(p_config->sck_pin,
    553e:	780b      	ldrb	r3, [r1, #0]
    5540:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5542:	a801      	add	r0, sp, #4
    5544:	f7ff ffca 	bl	54dc <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    5548:	9b01      	ldr	r3, [sp, #4]
    554a:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    554e:	2201      	movs	r2, #1
    5550:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED)
    5554:	7848      	ldrb	r0, [r1, #1]
    5556:	28ff      	cmp	r0, #255	; 0xff
    5558:	d00c      	beq.n	5574 <nrfx_spi_init+0x7c>
        nrf_gpio_pin_clear(pin_number);
    555a:	f004 f9f2 	bl	9942 <nrf_gpio_pin_clear>
            nrf_gpio_cfg_output(p_config->mosi_pin);
    555e:	784b      	ldrb	r3, [r1, #1]
    5560:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5562:	a801      	add	r0, sp, #4
    5564:	f7ff ffba 	bl	54dc <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    5568:	9b01      	ldr	r3, [sp, #4]
    556a:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    556e:	2203      	movs	r2, #3
    5570:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
    5574:	788b      	ldrb	r3, [r1, #2]
    5576:	2bff      	cmp	r3, #255	; 0xff
    5578:	d00c      	beq.n	5594 <nrfx_spi_init+0x9c>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    557a:	a801      	add	r0, sp, #4
            nrf_gpio_cfg_input(p_config->miso_pin, p_config->miso_pull);
    557c:	f891 800e 	ldrb.w	r8, [r1, #14]
    5580:	9301      	str	r3, [sp, #4]
    5582:	f7ff ffab 	bl	54dc <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    5586:	9b01      	ldr	r3, [sp, #4]
    5588:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    558c:	ea4f 0288 	mov.w	r2, r8, lsl #2
    reg->PIN_CNF[pin_number] = cnf;
    5590:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED)
    5594:	78c8      	ldrb	r0, [r1, #3]
    5596:	28ff      	cmp	r0, #255	; 0xff
    5598:	d00c      	beq.n	55b4 <nrfx_spi_init+0xbc>
        nrf_gpio_pin_set(pin_number);
    559a:	f004 f9c5 	bl	9928 <nrf_gpio_pin_set>
            nrf_gpio_cfg_output(p_config->ss_pin);
    559e:	78cb      	ldrb	r3, [r1, #3]
    55a0:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    55a2:	a801      	add	r0, sp, #4
    55a4:	f7ff ff9a 	bl	54dc <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    55a8:	9b01      	ldr	r3, [sp, #4]
    55aa:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    55ae:	2203      	movs	r2, #3
    55b0:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
    if (!p_config->skip_psel_cfg)
    55b4:	7c0b      	ldrb	r3, [r1, #16]
    55b6:	b993      	cbnz	r3, 55de <nrfx_spi_init+0xe6>
        uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED)
    55b8:	784b      	ldrb	r3, [r1, #1]
        nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
    55ba:	7808      	ldrb	r0, [r1, #0]
                            : NRF_SPI_PIN_NOT_CONNECTED;
    55bc:	2bff      	cmp	r3, #255	; 0xff
    55be:	bf18      	it	ne
    55c0:	461a      	movne	r2, r3
        uint32_t miso_pin = (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
    55c2:	788b      	ldrb	r3, [r1, #2]
                                        uint32_t       sck_pin,
                                        uint32_t       mosi_pin,
                                        uint32_t       miso_pin)
{
#if defined(SPI_PSEL_SCK_CONNECT_Pos)
    p_reg->PSEL.SCK = sck_pin;
    55c4:	f8c5 0508 	str.w	r0, [r5, #1288]	; 0x508
                            : NRF_SPI_PIN_NOT_CONNECTED;
    55c8:	bf08      	it	eq
    55ca:	f04f 32ff 	moveq.w	r2, #4294967295
                            : NRF_SPI_PIN_NOT_CONNECTED;
    55ce:	2bff      	cmp	r3, #255	; 0xff
    55d0:	bf08      	it	eq
    55d2:	f04f 33ff 	moveq.w	r3, #4294967295
#else
    p_reg->PSELSCK  = sck_pin;
#endif

#if defined(SPI_PSEL_MOSI_CONNECT_Pos)
    p_reg->PSEL.MOSI = mosi_pin;
    55d6:	f8c5 250c 	str.w	r2, [r5, #1292]	; 0x50c
#else
    p_reg->PSELMOSI = mosi_pin;
#endif

#if defined(SPI_PSEL_MISO_CONNECT_Pos)
    p_reg->PSEL.MISO = miso_pin;
    55da:	f8c5 3510 	str.w	r3, [r5, #1296]	; 0x510
}

NRF_STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type *      p_reg,
                                             nrf_spi_frequency_t frequency)
{
    p_reg->FREQUENCY = (uint32_t)frequency;
    55de:	688b      	ldr	r3, [r1, #8]
    55e0:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
NRF_STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type *      p_reg,
                                         nrf_spi_mode_t      spi_mode,
                                         nrf_spi_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
        SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
    55e4:	7b4b      	ldrb	r3, [r1, #13]

    configure_pins(p_spi, p_config);

    nrf_spi_frequency_set(p_spi, p_config->frequency);
    nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order);
    55e6:	7b0a      	ldrb	r2, [r1, #12]
    55e8:	3b00      	subs	r3, #0
    55ea:	bf18      	it	ne
    55ec:	2301      	movne	r3, #1
    switch (spi_mode)
    55ee:	2a02      	cmp	r2, #2
    55f0:	d021      	beq.n	5636 <nrfx_spi_init+0x13e>
    55f2:	2a03      	cmp	r2, #3
    55f4:	d022      	beq.n	563c <nrfx_spi_init+0x144>
    55f6:	2a01      	cmp	r2, #1
    55f8:	d101      	bne.n	55fe <nrfx_spi_init+0x106>
        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
                  (SPI_CONFIG_CPHA_Leading    << SPI_CONFIG_CPHA_Pos);
        break;

    case NRF_SPI_MODE_1:
        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
    55fa:	f043 0302 	orr.w	r3, r3, #2
    case NRF_SPI_MODE_3:
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    55fe:	f8c5 3554 	str.w	r3, [r5, #1364]	; 0x554
    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
    5602:	2301      	movs	r3, #1
    5604:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500

    nrf_spi_enable(p_spi);

    if (p_cb->handler)
    5608:	2328      	movs	r3, #40	; 0x28
    560a:	437b      	muls	r3, r7
    560c:	58e3      	ldr	r3, [r4, r3]
    560e:	b123      	cbz	r3, 561a <nrfx_spi_init+0x122>
    return ((((uint32_t)p_object) & 0x3u) == 0u);
}

NRF_STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg)
{
    return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg);
    5610:	6830      	ldr	r0, [r6, #0]
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
            p_config->irq_priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    5612:	f340 3007 	sbfx	r0, r0, #12, #8
    5616:	f7fc fcdf 	bl	1fd8 <arch_irq_enable>
    }

    p_cb->transfer_in_progress = false;
    561a:	2328      	movs	r3, #40	; 0x28
    561c:	fb03 4407 	mla	r4, r3, r7, r4
    5620:	2300      	movs	r3, #0
    5622:	7763      	strb	r3, [r4, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    5624:	4809      	ldr	r0, [pc, #36]	; (564c <nrfx_spi_init+0x154>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    5626:	2301      	movs	r3, #1
    5628:	7723      	strb	r3, [r4, #28]
}
    562a:	b002      	add	sp, #8
    562c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        nrf_gpio_pin_set(pin_number);
    5630:	f004 f97a 	bl	9928 <nrf_gpio_pin_set>
    5634:	e783      	b.n	553e <nrfx_spi_init+0x46>
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
    5636:	f043 0304 	orr.w	r3, r3, #4
        break;
    563a:	e7e0      	b.n	55fe <nrfx_spi_init+0x106>
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
    563c:	f043 0306 	orr.w	r3, r3, #6
        break;
    5640:	e7dd      	b.n	55fe <nrfx_spi_init+0x106>
        return err_code;
    5642:	4803      	ldr	r0, [pc, #12]	; (5650 <nrfx_spi_init+0x158>)
    5644:	e7f1      	b.n	562a <nrfx_spi_init+0x132>
    5646:	bf00      	nop
    5648:	20001eb0 	.word	0x20001eb0
    564c:	0bad0000 	.word	0x0bad0000
    5650:	0bad0005 	.word	0x0bad0005

00005654 <nrfx_spi_uninit>:

void nrfx_spi_uninit(nrfx_spi_t const * p_instance)
{
    5654:	b570      	push	{r4, r5, r6, lr}
    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    5656:	7906      	ldrb	r6, [r0, #4]
    NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
    NRF_SPI_Type * p_spi = p_instance->p_reg;

    if (p_cb->handler)
    5658:	4c19      	ldr	r4, [pc, #100]	; (56c0 <nrfx_spi_uninit+0x6c>)
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    565a:	6805      	ldr	r5, [r0, #0]
    if (p_cb->handler)
    565c:	2328      	movs	r3, #40	; 0x28
    565e:	4373      	muls	r3, r6
    5660:	58e3      	ldr	r3, [r4, r3]
    5662:	b133      	cbz	r3, 5672 <nrfx_spi_uninit+0x1e>
    {
        NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    5664:	f345 3007 	sbfx	r0, r5, #12, #8
    5668:	f7fc fcc4 	bl	1ff4 <arch_irq_disable>
    p_reg->INTENCLR = mask;
    566c:	2304      	movs	r3, #4
    566e:	f8c5 3308 	str.w	r3, [r5, #776]	; 0x308
    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
    5672:	2300      	movs	r3, #0
    5674:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
        nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK);
    }

    nrf_spi_disable(p_spi);

    if (!p_cb->skip_gpio_cfg)
    5678:	2328      	movs	r3, #40	; 0x28
    567a:	fb03 4306 	mla	r3, r3, r6, r4
    567e:	f893 3025 	ldrb.w	r3, [r3, #37]	; 0x25
    5682:	b9bb      	cbnz	r3, 56b4 <nrfx_spi_uninit+0x60>
    return p_reg->PSEL.SCK;
    5684:	f8d5 0508 	ldr.w	r0, [r5, #1288]	; 0x508
    {
        nrf_gpio_cfg_default(nrf_spi_sck_pin_get(p_spi));
    5688:	f004 f940 	bl	990c <nrf_gpio_cfg_default>
    return p_reg->PSEL.MISO;
    568c:	f8d5 0510 	ldr.w	r0, [r5, #1296]	; 0x510

        uint32_t miso_pin = nrf_spi_miso_pin_get(p_spi);
        if (miso_pin != NRF_SPI_PIN_NOT_CONNECTED)
    5690:	1c42      	adds	r2, r0, #1
    5692:	d001      	beq.n	5698 <nrfx_spi_uninit+0x44>
        {
            nrf_gpio_cfg_default(miso_pin);
    5694:	f004 f93a 	bl	990c <nrf_gpio_cfg_default>
    return p_reg->PSEL.MOSI;
    5698:	f8d5 050c 	ldr.w	r0, [r5, #1292]	; 0x50c
        }

        uint32_t mosi_pin = nrf_spi_mosi_pin_get(p_spi);
        if (mosi_pin != NRF_SPI_PIN_NOT_CONNECTED)
    569c:	1c43      	adds	r3, r0, #1
    569e:	d001      	beq.n	56a4 <nrfx_spi_uninit+0x50>
        {
            nrf_gpio_cfg_default(mosi_pin);
    56a0:	f004 f934 	bl	990c <nrf_gpio_cfg_default>
        }

        if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    56a4:	2328      	movs	r3, #40	; 0x28
    56a6:	fb03 4306 	mla	r3, r3, r6, r4
    56aa:	7f98      	ldrb	r0, [r3, #30]
    56ac:	28ff      	cmp	r0, #255	; 0xff
    56ae:	d001      	beq.n	56b4 <nrfx_spi_uninit+0x60>
        {
            nrf_gpio_cfg_default(p_cb->ss_pin);
    56b0:	f004 f92c 	bl	990c <nrf_gpio_cfg_default>

#if NRFX_CHECK(NRFX_PRS_ENABLED)
    nrfx_prs_release(p_instance->p_reg);
#endif

    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    56b4:	2328      	movs	r3, #40	; 0x28
    56b6:	fb03 4406 	mla	r4, r3, r6, r4
    56ba:	2300      	movs	r3, #0
    56bc:	7723      	strb	r3, [r4, #28]
}
    56be:	bd70      	pop	{r4, r5, r6, pc}
    56c0:	20001eb0 	.word	0x20001eb0

000056c4 <nrfx_spi_xfer>:
}

nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const *           p_instance,
                         nrfx_spi_xfer_desc_t const * p_xfer_desc,
                         uint32_t                     flags)
{
    56c4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    56c8:	7907      	ldrb	r7, [r0, #4]
    NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
    NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    56ca:	4c39      	ldr	r4, [pc, #228]	; (57b0 <nrfx_spi_xfer+0xec>)
    56cc:	2328      	movs	r3, #40	; 0x28
    56ce:	437b      	muls	r3, r7
{
    56d0:	4690      	mov	r8, r2
    if (p_cb->transfer_in_progress)
    56d2:	18e2      	adds	r2, r4, r3
{
    56d4:	460e      	mov	r6, r1
    if (p_cb->transfer_in_progress)
    56d6:	7f51      	ldrb	r1, [r2, #29]
{
    56d8:	4681      	mov	r9, r0
    if (p_cb->transfer_in_progress)
    56da:	2900      	cmp	r1, #0
    56dc:	d166      	bne.n	57ac <nrfx_spi_xfer+0xe8>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler)
    56de:	58e3      	ldr	r3, [r4, r3]
    56e0:	b10b      	cbz	r3, 56e6 <nrfx_spi_xfer+0x22>
        {
            p_cb->transfer_in_progress = true;
    56e2:	2301      	movs	r3, #1
    56e4:	7753      	strb	r3, [r2, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    56e6:	e896 000f 	ldmia.w	r6, {r0, r1, r2, r3}
    56ea:	2528      	movs	r5, #40	; 0x28
    56ec:	fb05 4507 	mla	r5, r5, r7, r4
    56f0:	f105 0c0c 	add.w	ip, r5, #12
    56f4:	e88c 000f 	stmia.w	ip, {r0, r1, r2, r3}
    p_cb->abort = false;

    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    56f8:	7fa8      	ldrb	r0, [r5, #30]
    p_cb->abort = false;
    56fa:	2300      	movs	r3, #0
    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    56fc:	28ff      	cmp	r0, #255	; 0xff
    p_cb->abort = false;
    56fe:	f885 3024 	strb.w	r3, [r5, #36]	; 0x24
    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    5702:	d001      	beq.n	5708 <nrfx_spi_xfer+0x44>
        nrf_gpio_pin_clear(pin_number);
    5704:	f004 f91d 	bl	9942 <nrf_gpio_pin_clear>
    {
        nrf_gpio_pin_write(p_cb->ss_pin, 0);
    }
    if (flags)
    5708:	2328      	movs	r3, #40	; 0x28
    570a:	f1b8 0f00 	cmp.w	r8, #0
    570e:	d006      	beq.n	571e <nrfx_spi_xfer+0x5a>
    {
        p_cb->transfer_in_progress = false;
    5710:	fb03 4307 	mla	r3, r3, r7, r4
    5714:	2200      	movs	r2, #0
        err_code = NRFX_ERROR_NOT_SUPPORTED;
    5716:	4827      	ldr	r0, [pc, #156]	; (57b4 <nrfx_spi_xfer+0xf0>)
        p_cb->transfer_in_progress = false;
    5718:	775a      	strb	r2, [r3, #29]
    }
    NRFX_LOG_INFO("Function: %s, error code: %s.",
                  __func__,
                  NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    571a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        spi_xfer(p_instance->p_reg, p_cb, p_xfer_desc);
    571e:	f8d9 5000 	ldr.w	r5, [r9]
    p_cb->bytes_transferred = 0;
    5722:	fb03 4307 	mla	r3, r3, r7, r4
    p_reg->INTENCLR = mask;
    5726:	2204      	movs	r2, #4
    5728:	f8c5 2308 	str.w	r2, [r5, #776]	; 0x308
    572c:	f8c3 8020 	str.w	r8, [r3, #32]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5730:	f8c5 8108 	str.w	r8, [r5, #264]	; 0x108
    5734:	f8d5 2108 	ldr.w	r2, [r5, #264]	; 0x108
    nrf_spi_txd_set(p_spi,
    5738:	6872      	ldr	r2, [r6, #4]
    573a:	b19a      	cbz	r2, 5764 <nrfx_spi_xfer+0xa0>
    573c:	6833      	ldr	r3, [r6, #0]
    573e:	781b      	ldrb	r3, [r3, #0]
    p_reg->TXD = data;
    5740:	f8c5 351c 	str.w	r3, [r5, #1308]	; 0x51c
    if (p_xfer_desc->tx_length > 1)
    5744:	6873      	ldr	r3, [r6, #4]
    5746:	2b01      	cmp	r3, #1
    5748:	d90e      	bls.n	5768 <nrfx_spi_xfer+0xa4>
        nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
    574a:	6833      	ldr	r3, [r6, #0]
    574c:	785b      	ldrb	r3, [r3, #1]
    574e:	f8c5 351c 	str.w	r3, [r5, #1308]	; 0x51c
    if (p_cb->handler)
    5752:	2328      	movs	r3, #40	; 0x28
    5754:	437b      	muls	r3, r7
    5756:	58e6      	ldr	r6, [r4, r3]
    5758:	b176      	cbz	r6, 5778 <nrfx_spi_xfer+0xb4>
    p_reg->INTENSET = mask;
    575a:	2304      	movs	r3, #4
    575c:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    nrfx_err_t err_code = NRFX_SUCCESS;
    5760:	4815      	ldr	r0, [pc, #84]	; (57b8 <nrfx_spi_xfer+0xf4>)
    5762:	e7da      	b.n	571a <nrfx_spi_xfer+0x56>
    nrf_spi_txd_set(p_spi,
    5764:	7fdb      	ldrb	r3, [r3, #31]
    5766:	e7eb      	b.n	5740 <nrfx_spi_xfer+0x7c>
    else if (p_xfer_desc->rx_length > 1)
    5768:	68f3      	ldr	r3, [r6, #12]
    576a:	2b01      	cmp	r3, #1
    576c:	d9f1      	bls.n	5752 <nrfx_spi_xfer+0x8e>
        nrf_spi_txd_set(p_spi, p_cb->orc);
    576e:	2328      	movs	r3, #40	; 0x28
    5770:	fb03 4307 	mla	r3, r3, r7, r4
    p_reg->TXD = data;
    5774:	7fdb      	ldrb	r3, [r3, #31]
    5776:	e7ea      	b.n	574e <nrfx_spi_xfer+0x8a>
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    5778:	eb07 0187 	add.w	r1, r7, r7, lsl #2
    577c:	eb04 01c1 	add.w	r1, r4, r1, lsl #3
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5780:	f8d5 3108 	ldr.w	r3, [r5, #264]	; 0x108
            while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
    5784:	2b00      	cmp	r3, #0
    5786:	d0fb      	beq.n	5780 <nrfx_spi_xfer+0xbc>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5788:	f8c5 6108 	str.w	r6, [r5, #264]	; 0x108
        } while (transfer_byte(p_spi, p_cb));
    578c:	4628      	mov	r0, r5
    578e:	f8d5 3108 	ldr.w	r3, [r5, #264]	; 0x108
    5792:	f004 f8e3 	bl	995c <transfer_byte>
    5796:	2800      	cmp	r0, #0
    5798:	d1f2      	bne.n	5780 <nrfx_spi_xfer+0xbc>
        if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    579a:	2328      	movs	r3, #40	; 0x28
    579c:	fb03 4407 	mla	r4, r3, r7, r4
    57a0:	7fa0      	ldrb	r0, [r4, #30]
    57a2:	28ff      	cmp	r0, #255	; 0xff
    57a4:	d0dc      	beq.n	5760 <nrfx_spi_xfer+0x9c>
        nrf_gpio_pin_set(pin_number);
    57a6:	f004 f8bf 	bl	9928 <nrf_gpio_pin_set>
    57aa:	e7d9      	b.n	5760 <nrfx_spi_xfer+0x9c>
        return err_code;
    57ac:	4803      	ldr	r0, [pc, #12]	; (57bc <nrfx_spi_xfer+0xf8>)
    57ae:	e7b4      	b.n	571a <nrfx_spi_xfer+0x56>
    57b0:	20001eb0 	.word	0x20001eb0
    57b4:	0bad0003 	.word	0x0bad0003
    57b8:	0bad0000 	.word	0x0bad0000
    57bc:	0bad000b 	.word	0x0bad000b

000057c0 <nrfx_spi_1_irq_handler>:
}
#endif

#if NRFX_CHECK(NRFX_SPI1_ENABLED)
void nrfx_spi_1_irq_handler(void)
{
    57c0:	b510      	push	{r4, lr}
    57c2:	f04f 2040 	mov.w	r0, #1073758208	; 0x40004000
    57c6:	2300      	movs	r3, #0
    57c8:	f8c0 3108 	str.w	r3, [r0, #264]	; 0x108
    if (!transfer_byte(p_spi, p_cb))
    57cc:	490a      	ldr	r1, [pc, #40]	; (57f8 <nrfx_spi_1_irq_handler+0x38>)
    57ce:	f8d0 3108 	ldr.w	r3, [r0, #264]	; 0x108
    57d2:	f004 f8c3 	bl	995c <transfer_byte>
    57d6:	b968      	cbnz	r0, 57f4 <nrfx_spi_1_irq_handler+0x34>
    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    57d8:	7f88      	ldrb	r0, [r1, #30]
    57da:	28ff      	cmp	r0, #255	; 0xff
    57dc:	d001      	beq.n	57e2 <nrfx_spi_1_irq_handler+0x22>
    57de:	f004 f8a3 	bl	9928 <nrf_gpio_pin_set>
    p_cb->transfer_in_progress = false;
    57e2:	2300      	movs	r3, #0
    57e4:	774b      	strb	r3, [r1, #29]
    p_cb->evt.type = NRFX_SPI_EVENT_DONE;
    57e6:	720b      	strb	r3, [r1, #8]
    irq_handler(NRF_SPI1, &m_cb[NRFX_SPI1_INST_IDX]);
}
    57e8:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    57ec:	e9d1 3100 	ldrd	r3, r1, [r1]
    57f0:	4802      	ldr	r0, [pc, #8]	; (57fc <nrfx_spi_1_irq_handler+0x3c>)
    57f2:	4718      	bx	r3
}
    57f4:	bd10      	pop	{r4, pc}
    57f6:	bf00      	nop
    57f8:	20001eb0 	.word	0x20001eb0
    57fc:	20001eb8 	.word	0x20001eb8

00005800 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    5800:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    5802:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    5806:	095b      	lsrs	r3, r3, #5
        case 0: return NRF_P0;
    5808:	2b01      	cmp	r3, #1
    *p_pin = pin_number & 0x1F;
    580a:	6002      	str	r2, [r0, #0]
}
    580c:	4802      	ldr	r0, [pc, #8]	; (5818 <nrf_gpio_pin_port_decode+0x18>)
    580e:	bf18      	it	ne
    5810:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    5814:	4770      	bx	lr
    5816:	bf00      	nop
    5818:	50000300 	.word	0x50000300

0000581c <nrfx_spim_init>:

nrfx_err_t nrfx_spim_init(nrfx_spim_t const *        p_instance,
                          nrfx_spim_config_t const * p_config,
                          nrfx_spim_evt_handler_t    handler,
                          void *                     p_context)
{
    581c:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    NRFX_ASSERT(p_config);
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    nrfx_err_t err_code;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    5820:	4c7a      	ldr	r4, [pc, #488]	; (5a0c <nrfx_spim_init+0x1f0>)
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    5822:	7905      	ldrb	r5, [r0, #4]
{
    5824:	4606      	mov	r6, r0
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    5826:	eb04 1045 	add.w	r0, r4, r5, lsl #5
    582a:	7f00      	ldrb	r0, [r0, #28]
    582c:	2800      	cmp	r0, #0
    582e:	f040 80e9 	bne.w	5a04 <nrfx_spim_init+0x1e8>
        return err_code;
    }

#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
    // Check if SPIM instance supports the extended features.
    if (
    5832:	2d00      	cmp	r5, #0
    5834:	f040 80e8 	bne.w	5a08 <nrfx_spim_init+0x1ec>
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    5838:	6837      	ldr	r7, [r6, #0]
        return err_code;
    }
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)

    p_cb->handler = handler;
    p_cb->p_context = p_context;
    583a:	e9c4 2300 	strd	r2, r3, [r4]

    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
    583e:	7cca      	ldrb	r2, [r1, #19]
    5840:	7fa3      	ldrb	r3, [r4, #30]
    5842:	f362 0300 	bfi	r3, r2, #0, #1
    5846:	77a3      	strb	r3, [r4, #30]
    p_cb->ss_active_high = p_config->ss_active_high;
    5848:	790a      	ldrb	r2, [r1, #4]
    584a:	b2db      	uxtb	r3, r3
    584c:	f362 0341 	bfi	r3, r2, #1, #1
    5850:	77a3      	strb	r3, [r4, #30]
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
    p_cb->use_hw_ss = p_config->use_hw_ss;
    5852:	7c4a      	ldrb	r2, [r1, #17]
    5854:	b2db      	uxtb	r3, r3
    5856:	f362 0382 	bfi	r3, r2, #2, #1
    585a:	77a3      	strb	r3, [r4, #30]
#endif
    p_cb->ss_pin = p_config->ss_pin;
    585c:	78cb      	ldrb	r3, [r1, #3]
    585e:	77e3      	strb	r3, [r4, #31]
    if (!p_config->skip_gpio_cfg)
    5860:	7ccb      	ldrb	r3, [r1, #19]
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    5862:	f8d6 8000 	ldr.w	r8, [r6]
    if (!p_config->skip_gpio_cfg)
    5866:	2b00      	cmp	r3, #0
    5868:	d15e      	bne.n	5928 <nrfx_spim_init+0x10c>
                    : NRF_GPIO_PIN_S0S1;
    586a:	688b      	ldr	r3, [r1, #8]
        nrf_gpio_pin_write(p_config->sck_pin,
    586c:	7808      	ldrb	r0, [r1, #0]
                    : NRF_GPIO_PIN_S0S1;
    586e:	f1b3 5fa0 	cmp.w	r3, #335544320	; 0x14000000
    if (value == 0)
    5872:	7b0b      	ldrb	r3, [r1, #12]
    5874:	bf08      	it	eq
    5876:	2503      	moveq	r5, #3
    5878:	2b01      	cmp	r3, #1
    587a:	f200 80ad 	bhi.w	59d8 <nrfx_spim_init+0x1bc>
        nrf_gpio_pin_clear(pin_number);
    587e:	f004 f8ad 	bl	99dc <nrf_gpio_pin_clear>
        nrf_gpio_cfg(p_config->sck_pin,
    5882:	780b      	ldrb	r3, [r1, #0]
    5884:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5886:	a801      	add	r0, sp, #4
    5888:	f7ff ffba 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    588c:	9b01      	ldr	r3, [sp, #4]
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    588e:	022d      	lsls	r5, r5, #8
    reg->PIN_CNF[pin_number] = cnf;
    5890:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    5894:	f045 0201 	orr.w	r2, r5, #1
    reg->PIN_CNF[pin_number] = cnf;
    5898:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED)
    589c:	7848      	ldrb	r0, [r1, #1]
    589e:	28ff      	cmp	r0, #255	; 0xff
    58a0:	d00d      	beq.n	58be <nrfx_spim_init+0xa2>
        nrf_gpio_pin_clear(pin_number);
    58a2:	f004 f89b 	bl	99dc <nrf_gpio_pin_clear>
            nrf_gpio_cfg(p_config->mosi_pin,
    58a6:	784b      	ldrb	r3, [r1, #1]
    58a8:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    58aa:	a801      	add	r0, sp, #4
    58ac:	f7ff ffa8 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    58b0:	9b01      	ldr	r3, [sp, #4]
    58b2:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    58b6:	f045 0203 	orr.w	r2, r5, #3
    reg->PIN_CNF[pin_number] = cnf;
    58ba:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    58be:	788b      	ldrb	r3, [r1, #2]
    58c0:	2bff      	cmp	r3, #255	; 0xff
    58c2:	d00c      	beq.n	58de <nrfx_spim_init+0xc2>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    58c4:	a801      	add	r0, sp, #4
                         p_config->miso_pull,
    58c6:	f891 900e 	ldrb.w	r9, [r1, #14]
            nrf_gpio_cfg(p_config->miso_pin,
    58ca:	9301      	str	r3, [sp, #4]
    58cc:	f7ff ff98 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    58d0:	9b01      	ldr	r3, [sp, #4]
    58d2:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    58d6:	ea45 0289 	orr.w	r2, r5, r9, lsl #2
    reg->PIN_CNF[pin_number] = cnf;
    58da:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    58de:	78c8      	ldrb	r0, [r1, #3]
    58e0:	28ff      	cmp	r0, #255	; 0xff
    58e2:	d010      	beq.n	5906 <nrfx_spim_init+0xea>
    if (value == 0)
    58e4:	790b      	ldrb	r3, [r1, #4]
    58e6:	2b00      	cmp	r3, #0
    58e8:	d079      	beq.n	59de <nrfx_spim_init+0x1c2>
        nrf_gpio_pin_clear(pin_number);
    58ea:	f004 f877 	bl	99dc <nrf_gpio_pin_clear>
            nrf_gpio_cfg(p_config->ss_pin,
    58ee:	78cb      	ldrb	r3, [r1, #3]
    58f0:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    58f2:	a801      	add	r0, sp, #4
    58f4:	f7ff ff84 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    58f8:	9b01      	ldr	r3, [sp, #4]
    58fa:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    58fe:	f045 0203 	orr.w	r2, r5, #3
    reg->PIN_CNF[pin_number] = cnf;
    5902:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED)
    5906:	7bc8      	ldrb	r0, [r1, #15]
    5908:	28ff      	cmp	r0, #255	; 0xff
    590a:	d00d      	beq.n	5928 <nrfx_spim_init+0x10c>
        nrf_gpio_pin_set(pin_number);
    590c:	f004 f859 	bl	99c2 <nrf_gpio_pin_set>
            nrf_gpio_cfg(p_config->dcx_pin,
    5910:	7bcb      	ldrb	r3, [r1, #15]
    5912:	9301      	str	r3, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5914:	a801      	add	r0, sp, #4
    5916:	f7ff ff73 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    591a:	9b01      	ldr	r3, [sp, #4]
    591c:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    5920:	f045 0503 	orr.w	r5, r5, #3
    reg->PIN_CNF[pin_number] = cnf;
    5924:	f840 5023 	str.w	r5, [r0, r3, lsl #2]
    if (!p_config->skip_psel_cfg)
    5928:	7d0b      	ldrb	r3, [r1, #20]
    592a:	bb5b      	cbnz	r3, 5984 <nrfx_spim_init+0x168>
        uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED)
    592c:	784b      	ldrb	r3, [r1, #1]
        nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin);
    592e:	7808      	ldrb	r0, [r1, #0]
                            : NRF_SPIM_PIN_NOT_CONNECTED;
    5930:	2bff      	cmp	r3, #255	; 0xff
    5932:	bf18      	it	ne
    5934:	461a      	movne	r2, r3
        uint32_t miso_pin = (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    5936:	788b      	ldrb	r3, [r1, #2]
NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
                                         uint32_t        sck_pin,
                                         uint32_t        mosi_pin,
                                         uint32_t        miso_pin)
{
    p_reg->PSEL.SCK  = sck_pin;
    5938:	f8c8 0508 	str.w	r0, [r8, #1288]	; 0x508
                            : NRF_SPIM_PIN_NOT_CONNECTED;
    593c:	bf08      	it	eq
    593e:	f04f 32ff 	moveq.w	r2, #4294967295
                            : NRF_SPIM_PIN_NOT_CONNECTED;
    5942:	2bff      	cmp	r3, #255	; 0xff
    5944:	bf08      	it	eq
    5946:	f04f 33ff 	moveq.w	r3, #4294967295
    p_reg->PSEL.MOSI = mosi_pin;
    594a:	f8c8 250c 	str.w	r2, [r8, #1292]	; 0x50c
    p_reg->PSEL.MISO = miso_pin;
    594e:	f8c8 3510 	str.w	r3, [r8, #1296]	; 0x510
        if (SPIM_HW_CSN_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    5952:	7933      	ldrb	r3, [r6, #4]
    5954:	b9b3      	cbnz	r3, 5984 <nrfx_spim_init+0x168>
            if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED &&
    5956:	78cb      	ldrb	r3, [r1, #3]
    5958:	2bff      	cmp	r3, #255	; 0xff
    595a:	d043      	beq.n	59e4 <nrfx_spim_init+0x1c8>
    595c:	7c4a      	ldrb	r2, [r1, #17]
    595e:	2a00      	cmp	r2, #0
    5960:	d040      	beq.n	59e4 <nrfx_spim_init+0x1c8>
                                    (p_config->ss_active_high == true
    5962:	7908      	ldrb	r0, [r1, #4]
                nrf_spim_csn_configure(p_spim,
    5964:	7c8a      	ldrb	r2, [r1, #18]
NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type *    p_reg,
                                              uint32_t           pin,
                                              nrf_spim_csn_pol_t polarity,
                                              uint32_t           duration)
{
    p_reg->PSEL.CSN = pin;
    5966:	f8c8 3514 	str.w	r3, [r8, #1300]	; 0x514
    p_reg->CSNPOL = polarity;
    596a:	f8c8 0568 	str.w	r0, [r8, #1384]	; 0x568
    p_reg->IFTIMING.CSNDUR = duration;
    596e:	f8c8 2564 	str.w	r2, [r8, #1380]	; 0x564
        if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    5972:	7933      	ldrb	r3, [r6, #4]
    5974:	b933      	cbnz	r3, 5984 <nrfx_spim_init+0x168>
            uint32_t dcx_pin = (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED)
    5976:	7bcb      	ldrb	r3, [r1, #15]
                               : NRF_SPIM_PIN_NOT_CONNECTED;
    5978:	2bff      	cmp	r3, #255	; 0xff
    597a:	bf08      	it	eq
    597c:	f04f 33ff 	moveq.w	r3, #4294967295

#if NRF_SPIM_DCX_PRESENT
NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
                                            uint32_t        dcx_pin)
{
    p_reg->PSELDCX = dcx_pin;
    5980:	f8c8 356c 	str.w	r3, [r8, #1388]	; 0x56c

    configure_pins(p_instance, p_config);

#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
    // Change rx delay
    nrf_spim_iftiming_set(p_spim, p_config->rx_delay);
    5984:	7c0b      	ldrb	r3, [r1, #16]

#if NRF_SPIM_RXDELAY_PRESENT
NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
                                             uint32_t        rxdelay)
{
    p_reg->IFTIMING.RXDELAY = rxdelay;
    5986:	f8c7 3560 	str.w	r3, [r7, #1376]	; 0x560
#endif // defined(SPIM_STALLSTAT_TX_Msk)

NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type *      p_reg,
                                              nrf_spim_frequency_t frequency)
{
    p_reg->FREQUENCY = (uint32_t)frequency;
    598a:	688b      	ldr	r3, [r1, #8]
    598c:	f8c7 3524 	str.w	r3, [r7, #1316]	; 0x524
NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type *      p_reg,
                                          nrf_spim_mode_t      spi_mode,
                                          nrf_spim_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
    5990:	7b4b      	ldrb	r3, [r1, #13]
#endif

    nrf_spim_frequency_set(p_spim, p_config->frequency);
    nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order);
    5992:	7b0a      	ldrb	r2, [r1, #12]
    5994:	3b00      	subs	r3, #0
    5996:	bf18      	it	ne
    5998:	2301      	movne	r3, #1
    switch (spi_mode)
    599a:	2a02      	cmp	r2, #2
    599c:	d02c      	beq.n	59f8 <nrfx_spim_init+0x1dc>
    599e:	2a03      	cmp	r2, #3
    59a0:	d02d      	beq.n	59fe <nrfx_spim_init+0x1e2>
    59a2:	2a01      	cmp	r2, #1
    59a4:	d101      	bne.n	59aa <nrfx_spim_init+0x18e>
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
        break;

    case NRF_SPIM_MODE_1:
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
    59a6:	f043 0302 	orr.w	r3, r3, #2
    case NRF_SPIM_MODE_3:
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    59aa:	f8c7 3554 	str.w	r3, [r7, #1364]	; 0x554
}

NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
                                        uint8_t         orc)
{
    p_reg->ORC = orc;
    59ae:	798b      	ldrb	r3, [r1, #6]
    59b0:	f8c7 35c0 	str.w	r3, [r7, #1472]	; 0x5c0
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    59b4:	2307      	movs	r3, #7
    59b6:	f8c7 3500 	str.w	r3, [r7, #1280]	; 0x500

    nrf_spim_orc_set(p_spim, p_config->orc);

    nrf_spim_enable(p_spim);

    if (p_cb->handler)
    59ba:	6823      	ldr	r3, [r4, #0]
    59bc:	b123      	cbz	r3, 59c8 <nrfx_spim_init+0x1ac>
    59be:	6830      	ldr	r0, [r6, #0]
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
            p_config->irq_priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    59c0:	f340 3007 	sbfx	r0, r0, #12, #8
    59c4:	f7fc fb08 	bl	1fd8 <arch_irq_enable>
    }

    p_cb->transfer_in_progress = false;
    59c8:	2300      	movs	r3, #0
    59ca:	7763      	strb	r3, [r4, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    59cc:	4810      	ldr	r0, [pc, #64]	; (5a10 <nrfx_spim_init+0x1f4>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    59ce:	2301      	movs	r3, #1
    59d0:	7723      	strb	r3, [r4, #28]
}
    59d2:	b003      	add	sp, #12
    59d4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        nrf_gpio_pin_set(pin_number);
    59d8:	f003 fff3 	bl	99c2 <nrf_gpio_pin_set>
    59dc:	e751      	b.n	5882 <nrfx_spim_init+0x66>
    59de:	f003 fff0 	bl	99c2 <nrf_gpio_pin_set>
    59e2:	e784      	b.n	58ee <nrfx_spim_init+0xd2>
    p_reg->PSEL.CSN = pin;
    59e4:	f04f 33ff 	mov.w	r3, #4294967295
    59e8:	f8c8 3514 	str.w	r3, [r8, #1300]	; 0x514
    p_reg->CSNPOL = polarity;
    59ec:	2300      	movs	r3, #0
    59ee:	f8c8 3568 	str.w	r3, [r8, #1384]	; 0x568
    p_reg->IFTIMING.CSNDUR = duration;
    59f2:	f8c8 3564 	str.w	r3, [r8, #1380]	; 0x564
}
    59f6:	e7bc      	b.n	5972 <nrfx_spim_init+0x156>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    59f8:	f043 0304 	orr.w	r3, r3, #4
        break;
    59fc:	e7d5      	b.n	59aa <nrfx_spim_init+0x18e>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    59fe:	f043 0306 	orr.w	r3, r3, #6
        break;
    5a02:	e7d2      	b.n	59aa <nrfx_spim_init+0x18e>
        return err_code;
    5a04:	4803      	ldr	r0, [pc, #12]	; (5a14 <nrfx_spim_init+0x1f8>)
    5a06:	e7e4      	b.n	59d2 <nrfx_spim_init+0x1b6>
        return err_code;
    5a08:	4803      	ldr	r0, [pc, #12]	; (5a18 <nrfx_spim_init+0x1fc>)
    5a0a:	e7e2      	b.n	59d2 <nrfx_spim_init+0x1b6>
    5a0c:	20001ed8 	.word	0x20001ed8
    5a10:	0bad0000 	.word	0x0bad0000
    5a14:	0bad0005 	.word	0x0bad0005
    5a18:	0bad0003 	.word	0x0bad0003

00005a1c <nrfx_spim_uninit>:

    nrf_gpio_cfg_default(pin);
}

void nrfx_spim_uninit(nrfx_spim_t const * p_instance)
{
    5a1c:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    5a20:	7903      	ldrb	r3, [r0, #4]
    NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
    NRF_SPIM_Type * p_spim = p_instance->p_reg;

    if (p_cb->handler)
    5a22:	4d2a      	ldr	r5, [pc, #168]	; (5acc <nrfx_spim_uninit+0xb0>)
    NRF_SPIM_Type * p_spim = p_instance->p_reg;
    5a24:	6804      	ldr	r4, [r0, #0]
    if (p_cb->handler)
    5a26:	015e      	lsls	r6, r3, #5
    5a28:	eb05 1843 	add.w	r8, r5, r3, lsl #5
    5a2c:	59ab      	ldr	r3, [r5, r6]
{
    5a2e:	4607      	mov	r7, r0
    if (p_cb->handler)
    5a30:	b1cb      	cbz	r3, 5a66 <nrfx_spim_uninit+0x4a>
    {
        NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    5a32:	f344 3007 	sbfx	r0, r4, #12, #8
    5a36:	f7fc fadd 	bl	1ff4 <arch_irq_disable>
    p_reg->INTENCLR = mask;
    5a3a:	4b25      	ldr	r3, [pc, #148]	; (5ad0 <nrfx_spim_uninit+0xb4>)
    5a3c:	f8c4 3308 	str.w	r3, [r4, #776]	; 0x308
        nrf_spim_int_disable(p_spim, NRF_SPIM_ALL_INTS_MASK);
        if (p_cb->transfer_in_progress)
    5a40:	f898 301d 	ldrb.w	r3, [r8, #29]
    5a44:	b17b      	cbz	r3, 5a66 <nrfx_spim_uninit+0x4a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5a46:	2301      	movs	r3, #1
    5a48:	6163      	str	r3, [r4, #20]
    5a4a:	f04f 0864 	mov.w	r8, #100	; 0x64
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5a4e:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    NRFX_WAIT_FOR(nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED), 100, 1, stopped);
    5a52:	b92b      	cbnz	r3, 5a60 <nrfx_spim_uninit+0x44>
    5a54:	2001      	movs	r0, #1
    5a56:	f003 fea6 	bl	97a6 <nrfx_busy_wait>
    5a5a:	f1b8 0801 	subs.w	r8, r8, #1
    5a5e:	d1f6      	bne.n	5a4e <nrfx_spim_uninit+0x32>
    p_cb->transfer_in_progress = false;
    5a60:	19ab      	adds	r3, r5, r6
    5a62:	2200      	movs	r2, #0
    5a64:	775a      	strb	r2, [r3, #29]
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
    5a66:	2300      	movs	r3, #0
    5a68:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
        }
    }

    nrf_spim_disable(p_spim);

    if (!p_cb->skip_gpio_cfg)
    5a6c:	19ab      	adds	r3, r5, r6
    5a6e:	7f9b      	ldrb	r3, [r3, #30]
    5a70:	07db      	lsls	r3, r3, #31
    5a72:	d41f      	bmi.n	5ab4 <nrfx_spim_uninit+0x98>
    return p_reg->PSEL.SCK;
    5a74:	f8d4 0508 	ldr.w	r0, [r4, #1288]	; 0x508
    {
        spim_pin_uninit(nrf_spim_sck_pin_get(p_spim));
    5a78:	f003 ffbd 	bl	99f6 <spim_pin_uninit>
    return p_reg->PSEL.MISO;
    5a7c:	f8d4 0510 	ldr.w	r0, [r4, #1296]	; 0x510
        spim_pin_uninit(nrf_spim_miso_pin_get(p_spim));
    5a80:	f003 ffb9 	bl	99f6 <spim_pin_uninit>
    return p_reg->PSEL.MOSI;
    5a84:	f8d4 050c 	ldr.w	r0, [r4, #1292]	; 0x50c
        spim_pin_uninit(nrf_spim_mosi_pin_get(p_spim));
    5a88:	f003 ffb5 	bl	99f6 <spim_pin_uninit>
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
        if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    5a8c:	793b      	ldrb	r3, [r7, #4]
    5a8e:	b91b      	cbnz	r3, 5a98 <nrfx_spim_uninit+0x7c>
    return p_reg->PSELDCX;
    5a90:	f8d4 056c 	ldr.w	r0, [r4, #1388]	; 0x56c
        {
            spim_pin_uninit(nrf_spim_dcx_pin_get(p_spim));
    5a94:	f003 ffaf 	bl	99f6 <spim_pin_uninit>
        }
#endif
        if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    5a98:	19ab      	adds	r3, r5, r6
    5a9a:	7fdb      	ldrb	r3, [r3, #31]
    5a9c:	2bff      	cmp	r3, #255	; 0xff
    5a9e:	d009      	beq.n	5ab4 <nrfx_spim_uninit+0x98>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    5aa0:	a801      	add	r0, sp, #4
        {
            nrf_gpio_cfg_default(p_cb->ss_pin);
    5aa2:	9301      	str	r3, [sp, #4]
    5aa4:	f7ff feac 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    5aa8:	9b01      	ldr	r3, [sp, #4]
    5aaa:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    5aae:	2202      	movs	r2, #2
    5ab0:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
        }
    }

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_195)
    if (p_spim == NRF_SPIM3)
    5ab4:	4b07      	ldr	r3, [pc, #28]	; (5ad4 <nrfx_spim_uninit+0xb8>)
    5ab6:	429c      	cmp	r4, r3
    {
        *(volatile uint32_t *)0x4002F004 = 1;
    5ab8:	bf08      	it	eq
    5aba:	2301      	moveq	r3, #1

#if NRFX_CHECK(NRFX_PRS_ENABLED)
    nrfx_prs_release(p_instance->p_reg);
#endif

    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    5abc:	4435      	add	r5, r6
        *(volatile uint32_t *)0x4002F004 = 1;
    5abe:	bf08      	it	eq
    5ac0:	6063      	streq	r3, [r4, #4]
    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    5ac2:	2300      	movs	r3, #0
    5ac4:	772b      	strb	r3, [r5, #28]
}
    5ac6:	b002      	add	sp, #8
    5ac8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5acc:	20001ed8 	.word	0x20001ed8
    5ad0:	00080152 	.word	0x00080152
    5ad4:	4002f000 	.word	0x4002f000

00005ad8 <nrfx_spim_xfer>:
}

nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const *           p_instance,
                          nrfx_spim_xfer_desc_t const * p_xfer_desc,
                          uint32_t                      flags)
{
    5ad8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    5adc:	4f38      	ldr	r7, [pc, #224]	; (5bc0 <nrfx_spim_xfer+0xe8>)
    5ade:	7903      	ldrb	r3, [r0, #4]
    5ae0:	eb07 1843 	add.w	r8, r7, r3, lsl #5
{
    5ae4:	4615      	mov	r5, r2
#endif
                (p_cb->ss_pin == NRFX_SPIM_PIN_NOT_USED));

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    5ae6:	f898 201d 	ldrb.w	r2, [r8, #29]
{
    5aea:	4681      	mov	r9, r0
    5aec:	460c      	mov	r4, r1
    if (p_cb->transfer_in_progress)
    5aee:	015e      	lsls	r6, r3, #5
    5af0:	2a00      	cmp	r2, #0
    5af2:	d163      	bne.n	5bbc <nrfx_spim_xfer+0xe4>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler && !(flags & (NRFX_SPIM_FLAG_REPEATED_XFER |
    5af4:	59ba      	ldr	r2, [r7, r6]
    5af6:	b12a      	cbz	r2, 5b04 <nrfx_spim_xfer+0x2c>
    5af8:	f015 0f14 	tst.w	r5, #20
                                        NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER)))
        {
            p_cb->transfer_in_progress = true;
    5afc:	bf04      	itt	eq
    5afe:	2201      	moveq	r2, #1
    5b00:	f888 201d 	strbeq.w	r2, [r8, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    5b04:	e894 000f 	ldmia.w	r4, {r0, r1, r2, r3}
    5b08:	eb07 0c06 	add.w	ip, r7, r6
    5b0c:	f10c 0c0c 	add.w	ip, ip, #12
    5b10:	e88c 000f 	stmia.w	ip, {r0, r1, r2, r3}

    set_ss_pin_state(p_cb, true);
    5b14:	2101      	movs	r1, #1
    5b16:	4640      	mov	r0, r8
    5b18:	f003 ff7d 	bl	9a16 <set_ss_pin_state>
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    5b1c:	6821      	ldr	r1, [r4, #0]

    return spim_xfer(p_instance->p_reg, p_cb,  p_xfer_desc, flags);
    5b1e:	f8d9 3000 	ldr.w	r3, [r9]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    5b22:	b121      	cbz	r1, 5b2e <nrfx_spim_xfer+0x56>
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    5b24:	f001 4260 	and.w	r2, r1, #3758096384	; 0xe0000000
    5b28:	f1b2 5f00 	cmp.w	r2, #536870912	; 0x20000000
    5b2c:	d106      	bne.n	5b3c <nrfx_spim_xfer+0x64>
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    5b2e:	68a2      	ldr	r2, [r4, #8]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    5b30:	b152      	cbz	r2, 5b48 <nrfx_spim_xfer+0x70>
    5b32:	f002 4260 	and.w	r2, r2, #3758096384	; 0xe0000000
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    5b36:	f1b2 5f00 	cmp.w	r2, #536870912	; 0x20000000
    5b3a:	d005      	beq.n	5b48 <nrfx_spim_xfer+0x70>
        p_cb->transfer_in_progress = false;
    5b3c:	443e      	add	r6, r7
    5b3e:	2300      	movs	r3, #0
        return err_code;
    5b40:	4820      	ldr	r0, [pc, #128]	; (5bc4 <nrfx_spim_xfer+0xec>)
        p_cb->transfer_in_progress = false;
    5b42:	7773      	strb	r3, [r6, #29]
}
    5b44:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length);
    5b48:	6862      	ldr	r2, [r4, #4]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    5b4a:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    5b4e:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    5b52:	e9d4 1202 	ldrd	r1, r2, [r4, #8]
    5b56:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    5b5a:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5b5e:	2200      	movs	r2, #0
    5b60:	f8c3 2118 	str.w	r2, [r3, #280]	; 0x118
    5b64:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
    if (NRFX_SPIM_FLAG_TX_POSTINC & flags)
    5b68:	f015 0201 	ands.w	r2, r5, #1
}


NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
    5b6c:	bf18      	it	ne
    5b6e:	2201      	movne	r2, #1
}

NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
    5b70:	f8c3 2550 	str.w	r2, [r3, #1360]	; 0x550
    if (NRFX_SPIM_FLAG_RX_POSTINC & flags)
    5b74:	f015 0202 	ands.w	r2, r5, #2
}

NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
    5b78:	bf18      	it	ne
    5b7a:	2201      	movne	r2, #1
}

NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
    5b7c:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
    5b80:	072a      	lsls	r2, r5, #28
    5b82:	d507      	bpl.n	5b94 <nrfx_spim_xfer+0xbc>
    if (!p_cb->handler)
    5b84:	59ba      	ldr	r2, [r7, r6]
    5b86:	b972      	cbnz	r2, 5ba6 <nrfx_spim_xfer+0xce>
        set_ss_pin_state(p_cb, false);
    5b88:	2100      	movs	r1, #0
    5b8a:	4640      	mov	r0, r8
    5b8c:	f003 ff43 	bl	9a16 <set_ss_pin_state>
    return err_code;
    5b90:	480d      	ldr	r0, [pc, #52]	; (5bc8 <nrfx_spim_xfer+0xf0>)
    5b92:	e7d7      	b.n	5b44 <nrfx_spim_xfer+0x6c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5b94:	2201      	movs	r2, #1
    5b96:	611a      	str	r2, [r3, #16]
    if (!p_cb->handler)
    5b98:	59ba      	ldr	r2, [r7, r6]
    5b9a:	b922      	cbnz	r2, 5ba6 <nrfx_spim_xfer+0xce>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5b9c:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
            while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    5ba0:	2a00      	cmp	r2, #0
    5ba2:	d0fb      	beq.n	5b9c <nrfx_spim_xfer+0xc4>
    5ba4:	e7f0      	b.n	5b88 <nrfx_spim_xfer+0xb0>
    if (!enable)
    5ba6:	f015 0f04 	tst.w	r5, #4
    5baa:	f04f 0240 	mov.w	r2, #64	; 0x40
    5bae:	d002      	beq.n	5bb6 <nrfx_spim_xfer+0xde>
    p_reg->INTENCLR = mask;
    5bb0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    5bb4:	e7ec      	b.n	5b90 <nrfx_spim_xfer+0xb8>
    p_reg->INTENSET = mask;
    5bb6:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    5bba:	e7e9      	b.n	5b90 <nrfx_spim_xfer+0xb8>
        return err_code;
    5bbc:	4803      	ldr	r0, [pc, #12]	; (5bcc <nrfx_spim_xfer+0xf4>)
    5bbe:	e7c1      	b.n	5b44 <nrfx_spim_xfer+0x6c>
    5bc0:	20001ed8 	.word	0x20001ed8
    5bc4:	0bad000a 	.word	0x0bad000a
    5bc8:	0bad0000 	.word	0x0bad0000
    5bcc:	0bad000b 	.word	0x0bad000b

00005bd0 <nrfx_spim_3_irq_handler>:
}
#endif

#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
void nrfx_spim_3_irq_handler(void)
{
    5bd0:	b570      	push	{r4, r5, r6, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5bd2:	4b0c      	ldr	r3, [pc, #48]	; (5c04 <nrfx_spim_3_irq_handler+0x34>)
    5bd4:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    5bd8:	b192      	cbz	r2, 5c00 <nrfx_spim_3_irq_handler+0x30>
    set_ss_pin_state(p_cb, false);
    5bda:	4c0b      	ldr	r4, [pc, #44]	; (5c08 <nrfx_spim_3_irq_handler+0x38>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5bdc:	2500      	movs	r5, #0
    5bde:	f8c3 5118 	str.w	r5, [r3, #280]	; 0x118
    5be2:	4629      	mov	r1, r5
    5be4:	4620      	mov	r0, r4
    5be6:	f8d3 3118 	ldr.w	r3, [r3, #280]	; 0x118
    5bea:	f003 ff14 	bl	9a16 <set_ss_pin_state>
    p_cb->transfer_in_progress = false;
    5bee:	7765      	strb	r5, [r4, #29]
    p_cb->evt.type = NRFX_SPIM_EVENT_DONE;
    5bf0:	7225      	strb	r5, [r4, #8]
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    5bf2:	e9d4 3100 	ldrd	r3, r1, [r4]
    5bf6:	f104 0008 	add.w	r0, r4, #8
    irq_handler(NRF_SPIM3, &m_cb[NRFX_SPIM3_INST_IDX]);
}
    5bfa:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    5bfe:	4718      	bx	r3
}
    5c00:	bd70      	pop	{r4, r5, r6, pc}
    5c02:	bf00      	nop
    5c04:	4002f000 	.word	0x4002f000
    5c08:	20001ed8 	.word	0x20001ed8

00005c0c <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    5c0c:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    5c0e:	4c14      	ldr	r4, [pc, #80]	; (5c60 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    5c10:	4a14      	ldr	r2, [pc, #80]	; (5c64 <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    5c12:	4915      	ldr	r1, [pc, #84]	; (5c68 <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    5c14:	2303      	movs	r3, #3
    5c16:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    5c18:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    5c1a:	4b14      	ldr	r3, [pc, #80]	; (5c6c <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    5c1c:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    5c1e:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    5c20:	f44f 6380 	mov.w	r3, #1024	; 0x400
    5c24:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    5c26:	2300      	movs	r3, #0
    5c28:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    5c2a:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    5c2c:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    5c2e:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    5c30:	4a0f      	ldr	r2, [pc, #60]	; (5c70 <_DoInit+0x64>)
    5c32:	6662      	str	r2, [r4, #100]	; 0x64
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    5c34:	2210      	movs	r2, #16
    5c36:	66a2      	str	r2, [r4, #104]	; 0x68
  STRCPY((char*)&p->acID[7], "RTT");
    5c38:	1de0      	adds	r0, r4, #7
  p->aDown[0].RdOff         = 0u;
    5c3a:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    5c3c:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    5c3e:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    5c40:	f003 f8d8 	bl	8df4 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    5c44:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    5c48:	490a      	ldr	r1, [pc, #40]	; (5c74 <_DoInit+0x68>)
    5c4a:	4620      	mov	r0, r4
    5c4c:	f003 f8d2 	bl	8df4 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    5c50:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    5c54:	2320      	movs	r3, #32
    5c56:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    5c58:	f3bf 8f5f 	dmb	sy
}
    5c5c:	bd10      	pop	{r4, pc}
    5c5e:	bf00      	nop
    5c60:	20001ef8 	.word	0x20001ef8
    5c64:	0000b493 	.word	0x0000b493
    5c68:	0000b49c 	.word	0x0000b49c
    5c6c:	200022d7 	.word	0x200022d7
    5c70:	200022c7 	.word	0x200022c7
    5c74:	0000b4a0 	.word	0x0000b4a0

00005c78 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    5c78:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    5c7a:	4605      	mov	r5, r0
    5c7c:	460e      	mov	r6, r1
	__asm__ volatile(
    5c7e:	f04f 0320 	mov.w	r3, #32
    5c82:	f3ef 8711 	mrs	r7, BASEPRI
    5c86:	f383 8812 	msr	BASEPRI_MAX, r3
    5c8a:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    5c8e:	f000 fdf7 	bl	6880 <z_impl_z_current_get>
    5c92:	2d04      	cmp	r5, #4
    5c94:	bf96      	itet	ls
    5c96:	4b18      	ldrls	r3, [pc, #96]	; (5cf8 <z_fatal_error+0x80>)
    5c98:	4b18      	ldrhi	r3, [pc, #96]	; (5cfc <z_fatal_error+0x84>)
    5c9a:	f853 3025 	ldrls.w	r3, [r3, r5, lsl #2]
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    5c9e:	2200      	movs	r2, #0
    5ca0:	4604      	mov	r4, r0
    5ca2:	9200      	str	r2, [sp, #0]
    5ca4:	4816      	ldr	r0, [pc, #88]	; (5d00 <z_fatal_error+0x88>)
    5ca6:	462a      	mov	r2, r5
    5ca8:	2145      	movs	r1, #69	; 0x45
    5caa:	f003 f812 	bl	8cd2 <z_log_minimal_printk>
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    5cae:	b13e      	cbz	r6, 5cc0 <z_fatal_error+0x48>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    5cb0:	69f3      	ldr	r3, [r6, #28]
    5cb2:	f3c3 0308 	ubfx	r3, r3, #0, #9
    5cb6:	b11b      	cbz	r3, 5cc0 <z_fatal_error+0x48>
		LOG_ERR("Fault during interrupt handling\n");
    5cb8:	4812      	ldr	r0, [pc, #72]	; (5d04 <z_fatal_error+0x8c>)
    5cba:	2145      	movs	r1, #69	; 0x45
    5cbc:	f003 f809 	bl	8cd2 <z_log_minimal_printk>
	const char *thread_name = (thread != NULL) ? k_thread_name_get(thread) : NULL;
    5cc0:	b134      	cbz	r4, 5cd0 <z_fatal_error+0x58>
    5cc2:	4620      	mov	r0, r4
    5cc4:	f003 ff21 	bl	9b0a <k_thread_name_get>
	if ((thread_name == NULL) || (thread_name[0] == '\0')) {
    5cc8:	4603      	mov	r3, r0
    5cca:	b108      	cbz	r0, 5cd0 <z_fatal_error+0x58>
    5ccc:	7802      	ldrb	r2, [r0, #0]
    5cce:	b902      	cbnz	r2, 5cd2 <z_fatal_error+0x5a>
		thread_name = "unknown";
    5cd0:	4b0d      	ldr	r3, [pc, #52]	; (5d08 <z_fatal_error+0x90>)
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    5cd2:	480e      	ldr	r0, [pc, #56]	; (5d0c <z_fatal_error+0x94>)
    5cd4:	4622      	mov	r2, r4
    5cd6:	2145      	movs	r1, #69	; 0x45
    5cd8:	f002 fffb 	bl	8cd2 <z_log_minimal_printk>

#ifndef CONFIG_XTENSA
	coredump(reason, esf, thread);
#endif

	k_sys_fatal_error_handler(reason, esf);
    5cdc:	4631      	mov	r1, r6
    5cde:	4628      	mov	r0, r5
    5ce0:	f7fe fd66 	bl	47b0 <k_sys_fatal_error_handler>
	__asm__ volatile(
    5ce4:	f387 8811 	msr	BASEPRI, r7
    5ce8:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    5cec:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    5cee:	b003      	add	sp, #12
    5cf0:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
    5cf4:	f7fc bdb0 	b.w	2858 <z_impl_k_thread_abort>
    5cf8:	0000a42c 	.word	0x0000a42c
    5cfc:	0000b4a7 	.word	0x0000b4a7
    5d00:	0000b4bd 	.word	0x0000b4bd
    5d04:	0000b4ea 	.word	0x0000b4ea
    5d08:	0000b4b5 	.word	0x0000b4b5
    5d0c:	0000b510 	.word	0x0000b510

00005d10 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5d10:	4b0f      	ldr	r3, [pc, #60]	; (5d50 <z_sys_init_run_level+0x40>)
{
    5d12:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5d14:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    5d18:	3001      	adds	r0, #1
    5d1a:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    5d1e:	42a6      	cmp	r6, r4
    5d20:	d800      	bhi.n	5d24 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    5d22:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    5d24:	e9d4 3500 	ldrd	r3, r5, [r4]
    5d28:	4628      	mov	r0, r5
    5d2a:	4798      	blx	r3
		if (dev != NULL) {
    5d2c:	b16d      	cbz	r5, 5d4a <z_sys_init_run_level+0x3a>
			if (rc != 0) {
    5d2e:	b138      	cbz	r0, 5d40 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    5d30:	2800      	cmp	r0, #0
    5d32:	bfb8      	it	lt
    5d34:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    5d36:	68eb      	ldr	r3, [r5, #12]
				if (rc > UINT8_MAX) {
    5d38:	28ff      	cmp	r0, #255	; 0xff
    5d3a:	bfa8      	it	ge
    5d3c:	20ff      	movge	r0, #255	; 0xff
				dev->state->init_res = rc;
    5d3e:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    5d40:	68ea      	ldr	r2, [r5, #12]
    5d42:	7853      	ldrb	r3, [r2, #1]
    5d44:	f043 0301 	orr.w	r3, r3, #1
    5d48:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5d4a:	3408      	adds	r4, #8
    5d4c:	e7e7      	b.n	5d1e <z_sys_init_run_level+0xe>
    5d4e:	bf00      	nop
    5d50:	0000a440 	.word	0x0000a440

00005d54 <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    5d54:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    5d56:	4b0a      	ldr	r3, [pc, #40]	; (5d80 <bg_thread_main+0x2c>)
    5d58:	2201      	movs	r2, #1

	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    5d5a:	2003      	movs	r0, #3
	z_sys_post_kernel = true;
    5d5c:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    5d5e:	f7ff ffd7 	bl	5d10 <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    5d62:	f000 ff4d 	bl	6c00 <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
    5d66:	2004      	movs	r0, #4
    5d68:	f7ff ffd2 	bl	5d10 <z_sys_init_run_level>

	z_init_static_threads();
    5d6c:	f000 f930 	bl	5fd0 <z_init_static_threads>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    5d70:	f7fa fb30 	bl	3d4 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    5d74:	4a03      	ldr	r2, [pc, #12]	; (5d84 <bg_thread_main+0x30>)
    5d76:	7b13      	ldrb	r3, [r2, #12]
    5d78:	f023 0301 	bic.w	r3, r3, #1
    5d7c:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    5d7e:	bd08      	pop	{r3, pc}
    5d80:	200026d7 	.word	0x200026d7
    5d84:	20000370 	.word	0x20000370

00005d88 <z_bss_zero>:
{
    5d88:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    5d8a:	4803      	ldr	r0, [pc, #12]	; (5d98 <z_bss_zero+0x10>)
    5d8c:	4a03      	ldr	r2, [pc, #12]	; (5d9c <z_bss_zero+0x14>)
    5d8e:	2100      	movs	r1, #0
    5d90:	1a12      	subs	r2, r2, r0
    5d92:	f003 fe63 	bl	9a5c <z_early_memset>
}
    5d96:	bd08      	pop	{r3, pc}
    5d98:	20000290 	.word	0x20000290
    5d9c:	200026d8 	.word	0x200026d8

00005da0 <z_init_cpu>:
	thread->base.is_idle = 1U;
#endif
}

void z_init_cpu(int id)
{
    5da0:	b570      	push	{r4, r5, r6, lr}
	struct k_thread *thread = &z_idle_threads[i];
    5da2:	4e16      	ldr	r6, [pc, #88]	; (5dfc <z_init_cpu+0x5c>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    5da4:	4d16      	ldr	r5, [pc, #88]	; (5e00 <z_init_cpu+0x60>)
	z_setup_new_thread(thread, stack,
    5da6:	4917      	ldr	r1, [pc, #92]	; (5e04 <z_init_cpu+0x64>)
	struct k_thread *thread = &z_idle_threads[i];
    5da8:	23c0      	movs	r3, #192	; 0xc0
{
    5daa:	b086      	sub	sp, #24
	struct k_thread *thread = &z_idle_threads[i];
    5dac:	fb03 6600 	mla	r6, r3, r0, r6
	z_setup_new_thread(thread, stack,
    5db0:	2201      	movs	r2, #1
    5db2:	2300      	movs	r3, #0
    5db4:	e9cd 2304 	strd	r2, r3, [sp, #16]
    5db8:	220f      	movs	r2, #15
    5dba:	e9cd 3202 	strd	r3, r2, [sp, #8]
    5dbe:	9301      	str	r3, [sp, #4]
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    5dc0:	231c      	movs	r3, #28
    5dc2:	fb03 5500 	mla	r5, r3, r0, r5
{
    5dc6:	4604      	mov	r4, r0
	z_setup_new_thread(thread, stack,
    5dc8:	f44f 70c0 	mov.w	r0, #384	; 0x180
    5dcc:	fb00 1104 	mla	r1, r0, r4, r1
    5dd0:	4b0d      	ldr	r3, [pc, #52]	; (5e08 <z_init_cpu+0x68>)
    5dd2:	9500      	str	r5, [sp, #0]
    5dd4:	f44f 72a0 	mov.w	r2, #320	; 0x140
    5dd8:	4630      	mov	r0, r6
    5dda:	f000 f8c7 	bl	5f6c <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    5dde:	7b73      	ldrb	r3, [r6, #13]
	init_idle_thread(id);
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
	_kernel.cpus[id].id = id;
	_kernel.cpus[id].irq_stack =
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    5de0:	4a0a      	ldr	r2, [pc, #40]	; (5e0c <z_init_cpu+0x6c>)
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
    5de2:	60ee      	str	r6, [r5, #12]
    5de4:	f023 0304 	bic.w	r3, r3, #4
    5de8:	7373      	strb	r3, [r6, #13]
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    5dea:	f44f 6308 	mov.w	r3, #2176	; 0x880
    5dee:	fb04 3303 	mla	r3, r4, r3, r3
    5df2:	4413      	add	r3, r2
	_kernel.cpus[id].id = id;
    5df4:	752c      	strb	r4, [r5, #20]
	_kernel.cpus[id].irq_stack =
    5df6:	606b      	str	r3, [r5, #4]
		 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id]));
#ifdef CONFIG_SCHED_THREAD_USAGE_ALL
	_kernel.cpus[id].usage.track_usage =
		CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE;
#endif
}
    5df8:	b006      	add	sp, #24
    5dfa:	bd70      	pop	{r4, r5, r6, pc}
    5dfc:	200002b0 	.word	0x200002b0
    5e00:	20001fa0 	.word	0x20001fa0
    5e04:	20002f80 	.word	0x20002f80
    5e08:	00006089 	.word	0x00006089
    5e0c:	20002700 	.word	0x20002700

00005e10 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    5e10:	b580      	push	{r7, lr}
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	/* initialize early init calls */
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    5e12:	2000      	movs	r0, #0
{
    5e14:	b0b6      	sub	sp, #216	; 0xd8
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    5e16:	f7ff ff7b 	bl	5d10 <z_sys_init_run_level>
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    5e1a:	4b2d      	ldr	r3, [pc, #180]	; (5ed0 <z_cstart+0xc0>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    5e1c:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    5e20:	4d2c      	ldr	r5, [pc, #176]	; (5ed4 <z_cstart+0xc4>)

#ifdef CONFIG_TIMESLICE_PER_THREAD
	dummy_thread->base.slice_ticks = 0;
#endif

	_current_cpu->current = dummy_thread;
    5e22:	4e2d      	ldr	r6, [pc, #180]	; (5ed8 <z_cstart+0xc8>)
    5e24:	696b      	ldr	r3, [r5, #20]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    5e26:	4f2d      	ldr	r7, [pc, #180]	; (5edc <z_cstart+0xcc>)
    5e28:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    5e2c:	616b      	str	r3, [r5, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    5e2e:	2400      	movs	r4, #0
    5e30:	23e0      	movs	r3, #224	; 0xe0
    5e32:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    5e36:	77ec      	strb	r4, [r5, #31]
    5e38:	762c      	strb	r4, [r5, #24]
    5e3a:	766c      	strb	r4, [r5, #25]
    5e3c:	76ac      	strb	r4, [r5, #26]
    5e3e:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    5e42:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    5e44:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    5e48:	626b      	str	r3, [r5, #36]	; 0x24
    5e4a:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    5e4e:	f7fc fc77 	bl	2740 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    5e52:	f7fc f83d 	bl	1ed0 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    5e56:	f04f 33ff 	mov.w	r3, #4294967295
    5e5a:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    5e5c:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    5e5e:	f7fc fdbb 	bl	29d8 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    5e62:	f7fc fd0f 	bl	2884 <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    5e66:	f240 1301 	movw	r3, #257	; 0x101
    5e6a:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    5e6e:	ab06      	add	r3, sp, #24
    5e70:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    5e72:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	dummy_thread->resource_pool = NULL;
    5e76:	9422      	str	r4, [sp, #136]	; 0x88
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    5e78:	f003 fde4 	bl	9a44 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_1);
    5e7c:	2001      	movs	r0, #1
    5e7e:	f7ff ff47 	bl	5d10 <z_sys_init_run_level>
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    5e82:	2002      	movs	r0, #2
	_kernel.ready_q.cache = &z_main_thread;
    5e84:	4d16      	ldr	r5, [pc, #88]	; (5ee0 <z_cstart+0xd0>)
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    5e86:	f7ff ff43 	bl	5d10 <z_sys_init_run_level>
	z_sched_init();
    5e8a:	f000 fc51 	bl	6730 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    5e8e:	4b15      	ldr	r3, [pc, #84]	; (5ee4 <z_cstart+0xd4>)
	_kernel.ready_q.cache = &z_main_thread;
    5e90:	6235      	str	r5, [r6, #32]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    5e92:	9305      	str	r3, [sp, #20]
    5e94:	2301      	movs	r3, #1
    5e96:	4914      	ldr	r1, [pc, #80]	; (5ee8 <z_cstart+0xd8>)
    5e98:	9400      	str	r4, [sp, #0]
    5e9a:	e9cd 4303 	strd	r4, r3, [sp, #12]
    5e9e:	f44f 5220 	mov.w	r2, #10240	; 0x2800
    5ea2:	463b      	mov	r3, r7
    5ea4:	e9cd 4401 	strd	r4, r4, [sp, #4]
    5ea8:	4628      	mov	r0, r5
    5eaa:	f000 f85f 	bl	5f6c <z_setup_new_thread>
    5eae:	7b6a      	ldrb	r2, [r5, #13]
    5eb0:	4606      	mov	r6, r0
    5eb2:	f022 0204 	bic.w	r2, r2, #4
	z_ready_thread(&z_main_thread);
    5eb6:	4628      	mov	r0, r5
    5eb8:	736a      	strb	r2, [r5, #13]
    5eba:	f003 fea6 	bl	9c0a <z_ready_thread>
	z_init_cpu(0);
    5ebe:	4620      	mov	r0, r4
    5ec0:	f7ff ff6e 	bl	5da0 <z_init_cpu>
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    5ec4:	463a      	mov	r2, r7
    5ec6:	4631      	mov	r1, r6
    5ec8:	4628      	mov	r0, r5
    5eca:	f7fc f9f5 	bl	22b8 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    5ece:	bf00      	nop
    5ed0:	20002f80 	.word	0x20002f80
    5ed4:	e000ed00 	.word	0xe000ed00
    5ed8:	20001fa0 	.word	0x20001fa0
    5edc:	00005d55 	.word	0x00005d55
    5ee0:	20000370 	.word	0x20000370
    5ee4:	0000b577 	.word	0x0000b577
    5ee8:	20003100 	.word	0x20003100

00005eec <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return 0 on success, fails otherwise.
 */
static int init_mem_slab_module(const struct device *dev)
{
    5eec:	b538      	push	{r3, r4, r5, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    5eee:	4c06      	ldr	r4, [pc, #24]	; (5f08 <init_mem_slab_module+0x1c>)
    5ef0:	4d06      	ldr	r5, [pc, #24]	; (5f0c <init_mem_slab_module+0x20>)
	int rc = 0;
    5ef2:	2000      	movs	r0, #0
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    5ef4:	42ac      	cmp	r4, r5
    5ef6:	d300      	bcc.n	5efa <init_mem_slab_module+0xe>
		z_object_init(slab);
	}

out:
	return rc;
}
    5ef8:	bd38      	pop	{r3, r4, r5, pc}
		rc = create_free_list(slab);
    5efa:	4620      	mov	r0, r4
    5efc:	f003 fdb2 	bl	9a64 <create_free_list>
		if (rc < 0) {
    5f00:	2800      	cmp	r0, #0
    5f02:	dbf9      	blt.n	5ef8 <init_mem_slab_module+0xc>
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    5f04:	341c      	adds	r4, #28
    5f06:	e7f5      	b.n	5ef4 <init_mem_slab_module+0x8>
    5f08:	2000023e 	.word	0x2000023e
    5f0c:	2000023e 	.word	0x2000023e

00005f10 <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    5f10:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5f12:	460c      	mov	r4, r1
	__asm__ volatile(
    5f14:	f04f 0520 	mov.w	r5, #32
    5f18:	f3ef 8111 	mrs	r1, BASEPRI
    5f1c:	f385 8812 	msr	BASEPRI_MAX, r5
    5f20:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    5f24:	6945      	ldr	r5, [r0, #20]
    5f26:	b15d      	cbz	r5, 5f40 <k_mem_slab_alloc+0x30>
		/* take a free block */
		*mem = slab->free_list;
    5f28:	6025      	str	r5, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    5f2a:	682b      	ldr	r3, [r5, #0]
    5f2c:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    5f2e:	6983      	ldr	r3, [r0, #24]
    5f30:	3301      	adds	r3, #1
    5f32:	6183      	str	r3, [r0, #24]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    5f34:	2000      	movs	r0, #0
	__asm__ volatile(
    5f36:	f381 8811 	msr	BASEPRI, r1
    5f3a:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
    5f3e:	e011      	b.n	5f64 <k_mem_slab_alloc+0x54>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    5f40:	ea52 0603 	orrs.w	r6, r2, r3
    5f44:	d103      	bne.n	5f4e <k_mem_slab_alloc+0x3e>
		*mem = NULL;
    5f46:	6025      	str	r5, [r4, #0]
		result = -ENOMEM;
    5f48:	f06f 000b 	mvn.w	r0, #11
    5f4c:	e7f3      	b.n	5f36 <k_mem_slab_alloc+0x26>
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    5f4e:	e9cd 2300 	strd	r2, r3, [sp]
    5f52:	4602      	mov	r2, r0
    5f54:	3008      	adds	r0, #8
    5f56:	f000 faf5 	bl	6544 <z_pend_curr>
		if (result == 0) {
    5f5a:	b918      	cbnz	r0, 5f64 <k_mem_slab_alloc+0x54>
			*mem = _current->base.swap_data;
    5f5c:	4b02      	ldr	r3, [pc, #8]	; (5f68 <k_mem_slab_alloc+0x58>)
    5f5e:	689b      	ldr	r3, [r3, #8]
    5f60:	695b      	ldr	r3, [r3, #20]
    5f62:	6023      	str	r3, [r4, #0]
}
    5f64:	b002      	add	sp, #8
    5f66:	bd70      	pop	{r4, r5, r6, pc}
    5f68:	20001fa0 	.word	0x20001fa0

00005f6c <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    5f6c:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    5f70:	9e0e      	ldr	r6, [sp, #56]	; 0x38
    5f72:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    5f74:	2604      	movs	r6, #4
    5f76:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    5f78:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    5f7a:	7386      	strb	r6, [r0, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    5f7c:	f100 0558 	add.w	r5, r0, #88	; 0x58
{
    5f80:	460f      	mov	r7, r1
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    5f82:	1dd6      	adds	r6, r2, #7
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    5f84:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    5f88:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    5f8a:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    5f8c:	f026 0607 	bic.w	r6, r6, #7

/** @} */

static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym)
{
	return (char *)sym + K_KERNEL_STACK_RESERVED;
    5f90:	3740      	adds	r7, #64	; 0x40
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    5f92:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    5f96:	e9c0 7619 	strd	r7, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    5f9a:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    5f9c:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    5f9e:	66c5      	str	r5, [r0, #108]	; 0x6c
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    5fa0:	f106 0840 	add.w	r8, r6, #64	; 0x40
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    5fa4:	9202      	str	r2, [sp, #8]
    5fa6:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    5fa8:	9201      	str	r2, [sp, #4]
	stack_ptr = (char *)stack + stack_obj_size;
    5faa:	4488      	add	r8, r1
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    5fac:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    5fae:	9200      	str	r2, [sp, #0]
    5fb0:	4642      	mov	r2, r8
{
    5fb2:	4604      	mov	r4, r0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    5fb4:	f7fc f8fc 	bl	21b0 <arch_new_thread>
	if (!_current) {
    5fb8:	4b04      	ldr	r3, [pc, #16]	; (5fcc <z_setup_new_thread+0x60>)
	new_thread->init_data = NULL;
    5fba:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    5fbc:	689b      	ldr	r3, [r3, #8]
    5fbe:	b103      	cbz	r3, 5fc2 <z_setup_new_thread+0x56>
	new_thread->resource_pool = _current->resource_pool;
    5fc0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
	return stack_ptr;
    5fc2:	6723      	str	r3, [r4, #112]	; 0x70
}
    5fc4:	4640      	mov	r0, r8
    5fc6:	b004      	add	sp, #16
    5fc8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5fcc:	20001fa0 	.word	0x20001fa0

00005fd0 <z_init_static_threads>:
{
    5fd0:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    5fd4:	4c29      	ldr	r4, [pc, #164]	; (607c <z_init_static_threads+0xac>)
	_FOREACH_STATIC_THREAD(thread_data) {
    5fd6:	4d2a      	ldr	r5, [pc, #168]	; (6080 <z_init_static_threads+0xb0>)
{
    5fd8:	b087      	sub	sp, #28
    5fda:	4626      	mov	r6, r4
	_FOREACH_STATIC_THREAD(thread_data) {
    5fdc:	42ae      	cmp	r6, r5
    5fde:	f104 0430 	add.w	r4, r4, #48	; 0x30
    5fe2:	d30f      	bcc.n	6004 <z_init_static_threads+0x34>
	k_sched_lock();
    5fe4:	f000 fb74 	bl	66d0 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    5fe8:	4c24      	ldr	r4, [pc, #144]	; (607c <z_init_static_threads+0xac>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    5fea:	f8df 9098 	ldr.w	r9, [pc, #152]	; 6084 <z_init_static_threads+0xb4>
    5fee:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    5ff2:	f240 37e7 	movw	r7, #999	; 0x3e7
    5ff6:	42ac      	cmp	r4, r5
    5ff8:	d320      	bcc.n	603c <z_init_static_threads+0x6c>
}
    5ffa:	b007      	add	sp, #28
    5ffc:	e8bd 43f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, lr}
	k_sched_unlock();
    6000:	f000 bb7a 	b.w	66f8 <k_sched_unlock>
		z_setup_new_thread(
    6004:	f854 3c04 	ldr.w	r3, [r4, #-4]
    6008:	9305      	str	r3, [sp, #20]
    600a:	f854 3c10 	ldr.w	r3, [r4, #-16]
    600e:	9304      	str	r3, [sp, #16]
    6010:	f854 3c14 	ldr.w	r3, [r4, #-20]
    6014:	9303      	str	r3, [sp, #12]
    6016:	f854 3c18 	ldr.w	r3, [r4, #-24]
    601a:	9302      	str	r3, [sp, #8]
    601c:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    6020:	9301      	str	r3, [sp, #4]
    6022:	f854 3c20 	ldr.w	r3, [r4, #-32]
    6026:	9300      	str	r3, [sp, #0]
    6028:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    602c:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    6030:	f7ff ff9c 	bl	5f6c <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    6034:	f854 3c30 	ldr.w	r3, [r4, #-48]
    6038:	655e      	str	r6, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    603a:	e7ce      	b.n	5fda <z_init_static_threads+0xa>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    603c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    603e:	1c5a      	adds	r2, r3, #1
    6040:	d00d      	beq.n	605e <z_init_static_threads+0x8e>
					    K_MSEC(thread_data->init_delay));
    6042:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    6046:	2100      	movs	r1, #0
    6048:	4638      	mov	r0, r7
    604a:	fbc3 0106 	smlal	r0, r1, r3, r6
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    604e:	ea51 33c3 	orrs.w	r3, r1, r3, lsl #15
			schedule_new_thread(thread_data->init_thread,
    6052:	f8d4 8000 	ldr.w	r8, [r4]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    6056:	d104      	bne.n	6062 <z_init_static_threads+0x92>
	z_sched_start(thread);
    6058:	4640      	mov	r0, r8
    605a:	f000 fae9 	bl	6630 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    605e:	3430      	adds	r4, #48	; 0x30
    6060:	e7c9      	b.n	5ff6 <z_init_static_threads+0x26>
    6062:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    6066:	2300      	movs	r3, #0
    6068:	f7fa f84a 	bl	100 <__aeabi_uldivmod>
    606c:	4602      	mov	r2, r0
    606e:	460b      	mov	r3, r1
    6070:	f108 0018 	add.w	r0, r8, #24
    6074:	4649      	mov	r1, r9
    6076:	f000 fcd1 	bl	6a1c <z_add_timeout>
    607a:	e7f0      	b.n	605e <z_init_static_threads+0x8e>
    607c:	0000a05c 	.word	0x0000a05c
    6080:	0000a05c 	.word	0x0000a05c
    6084:	00009b77 	.word	0x00009b77

00006088 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    6088:	b508      	push	{r3, lr}
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    608a:	4c0b      	ldr	r4, [pc, #44]	; (60b8 <idle+0x30>)
	return !z_sys_post_kernel;
    608c:	4d0b      	ldr	r5, [pc, #44]	; (60bc <idle+0x34>)
	__asm__ volatile(
    608e:	f04f 0220 	mov.w	r2, #32
    6092:	f3ef 8311 	mrs	r3, BASEPRI
    6096:	f382 8812 	msr	BASEPRI_MAX, r2
    609a:	f3bf 8f6f 	isb	sy
    609e:	f003 fe0c 	bl	9cba <z_get_next_timeout_expiry>
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    60a2:	782b      	ldrb	r3, [r5, #0]
		_kernel.idle = z_get_next_timeout_expiry();
    60a4:	61e0      	str	r0, [r4, #28]
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    60a6:	b913      	cbnz	r3, 60ae <idle+0x26>
	arch_cpu_idle();
    60a8:	f7fb ff18 	bl	1edc <arch_cpu_idle>
}
    60ac:	e7ef      	b.n	608e <idle+0x6>
    60ae:	f7fb fd55 	bl	1b5c <pm_system_suspend>
    60b2:	2800      	cmp	r0, #0
    60b4:	d1eb      	bne.n	608e <idle+0x6>
    60b6:	e7f7      	b.n	60a8 <idle+0x20>
    60b8:	20001fa0 	.word	0x20001fa0
    60bc:	200026d7 	.word	0x200026d7

000060c0 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    60c0:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    60c4:	4604      	mov	r4, r0
    60c6:	4617      	mov	r7, r2
    60c8:	461e      	mov	r6, r3
    60ca:	f04f 0320 	mov.w	r3, #32
    60ce:	f3ef 8811 	mrs	r8, BASEPRI
    60d2:	f383 8812 	msr	BASEPRI_MAX, r3
    60d6:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    60da:	68c3      	ldr	r3, [r0, #12]
    60dc:	4a33      	ldr	r2, [pc, #204]	; (61ac <z_impl_k_mutex_lock+0xec>)
    60de:	b17b      	cbz	r3, 6100 <z_impl_k_mutex_lock+0x40>
    60e0:	6880      	ldr	r0, [r0, #8]
    60e2:	6891      	ldr	r1, [r2, #8]
    60e4:	4288      	cmp	r0, r1
    60e6:	d019      	beq.n	611c <z_impl_k_mutex_lock+0x5c>
		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    60e8:	ea57 0306 	orrs.w	r3, r7, r6
    60ec:	d118      	bne.n	6120 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    60ee:	f388 8811 	msr	BASEPRI, r8
    60f2:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EBUSY);

		return -EBUSY;
    60f6:	f06f 000f 	mvn.w	r0, #15
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    60fa:	b002      	add	sp, #8
    60fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    6100:	6891      	ldr	r1, [r2, #8]
    6102:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    6106:	6121      	str	r1, [r4, #16]
		mutex->lock_count++;
    6108:	3301      	adds	r3, #1
    610a:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    610c:	6893      	ldr	r3, [r2, #8]
    610e:	60a3      	str	r3, [r4, #8]
    6110:	f388 8811 	msr	BASEPRI, r8
    6114:	f3bf 8f6f 	isb	sy
		return 0;
    6118:	2000      	movs	r0, #0
    611a:	e7ee      	b.n	60fa <z_impl_k_mutex_lock+0x3a>
					_current->base.prio :
    611c:	6921      	ldr	r1, [r4, #16]
    611e:	e7f2      	b.n	6106 <z_impl_k_mutex_lock+0x46>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    6120:	f991 100e 	ldrsb.w	r1, [r1, #14]
    6124:	f990 300e 	ldrsb.w	r3, [r0, #14]
	return prio >= CONFIG_PRIORITY_CEILING;
}

static inline int z_get_new_prio_with_ceiling(int prio)
{
	return z_is_under_prio_ceiling(prio) ? prio : CONFIG_PRIORITY_CEILING;
    6128:	4299      	cmp	r1, r3
    612a:	bfa8      	it	ge
    612c:	4619      	movge	r1, r3
    612e:	f06f 027e 	mvn.w	r2, #126	; 0x7e
    6132:	4291      	cmp	r1, r2
    6134:	bfb8      	it	lt
    6136:	4611      	movlt	r1, r2
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    6138:	428b      	cmp	r3, r1
    613a:	dd2e      	ble.n	619a <z_impl_k_mutex_lock+0xda>
		resched = adjust_owner_prio(mutex, new_prio);
    613c:	f003 fcee 	bl	9b1c <adjust_owner_prio.isra.0>
    6140:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    6142:	e9cd 7600 	strd	r7, r6, [sp]
    6146:	481a      	ldr	r0, [pc, #104]	; (61b0 <z_impl_k_mutex_lock+0xf0>)
    6148:	4622      	mov	r2, r4
    614a:	4641      	mov	r1, r8
    614c:	f000 f9fa 	bl	6544 <z_pend_curr>
	if (got_mutex == 0) {
    6150:	2800      	cmp	r0, #0
    6152:	d0e1      	beq.n	6118 <z_impl_k_mutex_lock+0x58>
	__asm__ volatile(
    6154:	f04f 0320 	mov.w	r3, #32
    6158:	f3ef 8611 	mrs	r6, BASEPRI
    615c:	f383 8812 	msr	BASEPRI_MAX, r3
    6160:	f3bf 8f6f 	isb	sy
	if (likely(mutex->owner != NULL)) {
    6164:	68a0      	ldr	r0, [r4, #8]
    6166:	b1d0      	cbz	r0, 619e <z_impl_k_mutex_lock+0xde>
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    6168:	6823      	ldr	r3, [r4, #0]
			new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    616a:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    616c:	429c      	cmp	r4, r3
    616e:	d00a      	beq.n	6186 <z_impl_k_mutex_lock+0xc6>
    6170:	b14b      	cbz	r3, 6186 <z_impl_k_mutex_lock+0xc6>
    6172:	f993 300e 	ldrsb.w	r3, [r3, #14]
    6176:	4299      	cmp	r1, r3
    6178:	bfa8      	it	ge
    617a:	4619      	movge	r1, r3
    617c:	f06f 037e 	mvn.w	r3, #126	; 0x7e
    6180:	4299      	cmp	r1, r3
    6182:	bfb8      	it	lt
    6184:	4619      	movlt	r1, r3
		resched = adjust_owner_prio(mutex, new_prio) || resched;
    6186:	f003 fcc9 	bl	9b1c <adjust_owner_prio.isra.0>
    618a:	b140      	cbz	r0, 619e <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
    618c:	4808      	ldr	r0, [pc, #32]	; (61b0 <z_impl_k_mutex_lock+0xf0>)
    618e:	4631      	mov	r1, r6
    6190:	f000 fa3c 	bl	660c <z_reschedule>
	return -EAGAIN;
    6194:	f06f 000a 	mvn.w	r0, #10
    6198:	e7af      	b.n	60fa <z_impl_k_mutex_lock+0x3a>
	bool resched = false;
    619a:	2500      	movs	r5, #0
    619c:	e7d1      	b.n	6142 <z_impl_k_mutex_lock+0x82>
	if (resched) {
    619e:	2d00      	cmp	r5, #0
    61a0:	d1f4      	bne.n	618c <z_impl_k_mutex_lock+0xcc>
	__asm__ volatile(
    61a2:	f386 8811 	msr	BASEPRI, r6
    61a6:	f3bf 8f6f 	isb	sy
    61aa:	e7f3      	b.n	6194 <z_impl_k_mutex_lock+0xd4>
    61ac:	20001fa0 	.word	0x20001fa0
    61b0:	200026d8 	.word	0x200026d8

000061b4 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    61b4:	b538      	push	{r3, r4, r5, lr}

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    61b6:	6883      	ldr	r3, [r0, #8]
{
    61b8:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    61ba:	b36b      	cbz	r3, 6218 <z_impl_k_mutex_unlock+0x64>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    61bc:	4a19      	ldr	r2, [pc, #100]	; (6224 <z_impl_k_mutex_unlock+0x70>)
    61be:	6892      	ldr	r2, [r2, #8]
    61c0:	4293      	cmp	r3, r2
    61c2:	d12c      	bne.n	621e <z_impl_k_mutex_unlock+0x6a>

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    61c4:	68c3      	ldr	r3, [r0, #12]
    61c6:	2b01      	cmp	r3, #1
    61c8:	d903      	bls.n	61d2 <z_impl_k_mutex_unlock+0x1e>
		mutex->lock_count--;
    61ca:	3b01      	subs	r3, #1
    61cc:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	return 0;
    61ce:	2000      	movs	r0, #0
}
    61d0:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    61d2:	f04f 0320 	mov.w	r3, #32
    61d6:	f3ef 8511 	mrs	r5, BASEPRI
    61da:	f383 8812 	msr	BASEPRI_MAX, r3
    61de:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    61e2:	6901      	ldr	r1, [r0, #16]
    61e4:	6880      	ldr	r0, [r0, #8]
    61e6:	f003 fc99 	bl	9b1c <adjust_owner_prio.isra.0>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    61ea:	4620      	mov	r0, r4
    61ec:	f003 fd1d 	bl	9c2a <z_unpend_first_thread>
	mutex->owner = new_owner;
    61f0:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    61f2:	b158      	cbz	r0, 620c <z_impl_k_mutex_unlock+0x58>
		mutex->owner_orig_prio = new_owner->base.prio;
    61f4:	f990 200e 	ldrsb.w	r2, [r0, #14]
    61f8:	6122      	str	r2, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    61fa:	2200      	movs	r2, #0
    61fc:	6782      	str	r2, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    61fe:	f003 fd04 	bl	9c0a <z_ready_thread>
		z_reschedule(&lock, key);
    6202:	4809      	ldr	r0, [pc, #36]	; (6228 <z_impl_k_mutex_unlock+0x74>)
    6204:	4629      	mov	r1, r5
    6206:	f000 fa01 	bl	660c <z_reschedule>
    620a:	e7e0      	b.n	61ce <z_impl_k_mutex_unlock+0x1a>
		mutex->lock_count = 0U;
    620c:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    620e:	f385 8811 	msr	BASEPRI, r5
    6212:	f3bf 8f6f 	isb	sy
    6216:	e7da      	b.n	61ce <z_impl_k_mutex_unlock+0x1a>
		return -EINVAL;
    6218:	f06f 0015 	mvn.w	r0, #21
    621c:	e7d8      	b.n	61d0 <z_impl_k_mutex_unlock+0x1c>
		return -EPERM;
    621e:	f04f 30ff 	mov.w	r0, #4294967295
    6222:	e7d5      	b.n	61d0 <z_impl_k_mutex_unlock+0x1c>
    6224:	20001fa0 	.word	0x20001fa0
    6228:	200026d8 	.word	0x200026d8

0000622c <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    622c:	b538      	push	{r3, r4, r5, lr}
    622e:	4604      	mov	r4, r0
	__asm__ volatile(
    6230:	f04f 0320 	mov.w	r3, #32
    6234:	f3ef 8511 	mrs	r5, BASEPRI
    6238:	f383 8812 	msr	BASEPRI_MAX, r3
    623c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    6240:	f003 fcf3 	bl	9c2a <z_unpend_first_thread>

	if (thread != NULL) {
    6244:	b148      	cbz	r0, 625a <z_impl_k_sem_give+0x2e>
    6246:	2200      	movs	r2, #0
    6248:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    624a:	f003 fcde 	bl	9c0a <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    624e:	4629      	mov	r1, r5
    6250:	4805      	ldr	r0, [pc, #20]	; (6268 <z_impl_k_sem_give+0x3c>)

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    6252:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    6256:	f000 b9d9 	b.w	660c <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    625a:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    625e:	429a      	cmp	r2, r3
    6260:	bf18      	it	ne
    6262:	3301      	addne	r3, #1
    6264:	60a3      	str	r3, [r4, #8]
}
    6266:	e7f2      	b.n	624e <z_impl_k_sem_give+0x22>
    6268:	200026d8 	.word	0x200026d8

0000626c <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    626c:	b513      	push	{r0, r1, r4, lr}
    626e:	f04f 0420 	mov.w	r4, #32
    6272:	f3ef 8111 	mrs	r1, BASEPRI
    6276:	f384 8812 	msr	BASEPRI_MAX, r4
    627a:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    627e:	6884      	ldr	r4, [r0, #8]
    6280:	b144      	cbz	r4, 6294 <z_impl_k_sem_take+0x28>
		sem->count--;
    6282:	3c01      	subs	r4, #1
    6284:	6084      	str	r4, [r0, #8]
	__asm__ volatile(
    6286:	f381 8811 	msr	BASEPRI, r1
    628a:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    628e:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    6290:	b002      	add	sp, #8
    6292:	bd10      	pop	{r4, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    6294:	ea52 0403 	orrs.w	r4, r2, r3
    6298:	d106      	bne.n	62a8 <z_impl_k_sem_take+0x3c>
    629a:	f381 8811 	msr	BASEPRI, r1
    629e:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    62a2:	f06f 000f 	mvn.w	r0, #15
    62a6:	e7f3      	b.n	6290 <z_impl_k_sem_take+0x24>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    62a8:	e9cd 2300 	strd	r2, r3, [sp]
    62ac:	4602      	mov	r2, r0
    62ae:	4802      	ldr	r0, [pc, #8]	; (62b8 <z_impl_k_sem_take+0x4c>)
    62b0:	f000 f948 	bl	6544 <z_pend_curr>
	return ret;
    62b4:	e7ec      	b.n	6290 <z_impl_k_sem_take+0x24>
    62b6:	bf00      	nop
    62b8:	200026d8 	.word	0x200026d8

000062bc <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(struct k_thread *curr)
{
    62bc:	b538      	push	{r3, r4, r5, lr}
	int ret = slice_ticks;
    62be:	4d07      	ldr	r5, [pc, #28]	; (62dc <z_reset_time_slice+0x20>)
    62c0:	682c      	ldr	r4, [r5, #0]
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time(curr) != 0) {
    62c2:	b154      	cbz	r4, 62da <z_reset_time_slice+0x1e>
		_current_cpu->slice_ticks = slice_time(curr) + sys_clock_elapsed();
    62c4:	f7fe f9ca 	bl	465c <sys_clock_elapsed>
    62c8:	4b05      	ldr	r3, [pc, #20]	; (62e0 <z_reset_time_slice+0x24>)
    62ca:	4404      	add	r4, r0
    62cc:	611c      	str	r4, [r3, #16]
		z_set_timeout_expiry(slice_time(curr), false);
    62ce:	6828      	ldr	r0, [r5, #0]
    62d0:	2100      	movs	r1, #0
	}
}
    62d2:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		z_set_timeout_expiry(slice_time(curr), false);
    62d6:	f003 bd00 	b.w	9cda <z_set_timeout_expiry>
}
    62da:	bd38      	pop	{r3, r4, r5, pc}
    62dc:	20001fd8 	.word	0x20001fd8
    62e0:	20001fa0 	.word	0x20001fa0

000062e4 <update_cache>:
	}
#endif
}

static void update_cache(int preempt_ok)
{
    62e4:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    62e6:	4d0d      	ldr	r5, [pc, #52]	; (631c <update_cache+0x38>)
    62e8:	462b      	mov	r3, r5
    62ea:	f853 4f24 	ldr.w	r4, [r3, #36]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    62ee:	429c      	cmp	r4, r3
    62f0:	d000      	beq.n	62f4 <update_cache+0x10>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    62f2:	b904      	cbnz	r4, 62f6 <update_cache+0x12>
    62f4:	68ec      	ldr	r4, [r5, #12]
	if (z_is_thread_prevented_from_running(_current)) {
    62f6:	68ab      	ldr	r3, [r5, #8]
	if (preempt_ok != 0) {
    62f8:	b938      	cbnz	r0, 630a <update_cache+0x26>
	if (z_is_thread_prevented_from_running(_current)) {
    62fa:	7b5a      	ldrb	r2, [r3, #13]
    62fc:	06d2      	lsls	r2, r2, #27
    62fe:	d104      	bne.n	630a <update_cache+0x26>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    6300:	69a2      	ldr	r2, [r4, #24]
    6302:	b912      	cbnz	r2, 630a <update_cache+0x26>
	if (is_preempt(_current) || is_metairq(thread)) {
    6304:	89da      	ldrh	r2, [r3, #14]
    6306:	2a7f      	cmp	r2, #127	; 0x7f
    6308:	d805      	bhi.n	6316 <update_cache+0x32>
#ifndef CONFIG_SMP
	struct k_thread *thread = next_up();

	if (should_preempt(thread, preempt_ok)) {
#ifdef CONFIG_TIMESLICING
		if (thread != _current) {
    630a:	429c      	cmp	r4, r3
    630c:	d002      	beq.n	6314 <update_cache+0x30>
			z_reset_time_slice(thread);
    630e:	4620      	mov	r0, r4
    6310:	f7ff ffd4 	bl	62bc <z_reset_time_slice>
		}
#endif
		update_metairq_preempt(thread);
		_kernel.ready_q.cache = thread;
    6314:	4623      	mov	r3, r4
    6316:	622b      	str	r3, [r5, #32]
	 * thread because if the thread gets preempted for whatever
	 * reason the scheduler will make the same decision anyway.
	 */
	_current_cpu->swap_ok = preempt_ok;
#endif
}
    6318:	bd38      	pop	{r3, r4, r5, pc}
    631a:	bf00      	nop
    631c:	20001fa0 	.word	0x20001fa0

00006320 <move_thread_to_end_of_prio_q>:
{
    6320:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    6322:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    6326:	7b43      	ldrb	r3, [r0, #13]
    6328:	2a00      	cmp	r2, #0
{
    632a:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    632c:	da04      	bge.n	6338 <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    632e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    6332:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    6334:	f003 fc0d 	bl	9b52 <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    6338:	7b4b      	ldrb	r3, [r1, #13]
	return list->head == list;
    633a:	4a15      	ldr	r2, [pc, #84]	; (6390 <move_thread_to_end_of_prio_q+0x70>)
    633c:	f063 037f 	orn	r3, r3, #127	; 0x7f
    6340:	4610      	mov	r0, r2
    6342:	734b      	strb	r3, [r1, #13]
    6344:	f850 3f24 	ldr.w	r3, [r0, #36]!
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    6348:	6a94      	ldr	r4, [r2, #40]	; 0x28
	return sys_dlist_is_empty(list) ? NULL : list->head;
    634a:	4283      	cmp	r3, r0
    634c:	bf08      	it	eq
    634e:	2300      	moveq	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6350:	b923      	cbnz	r3, 635c <move_thread_to_end_of_prio_q+0x3c>
static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;

	node->next = list;
	node->prev = tail;
    6352:	e9c1 0400 	strd	r0, r4, [r1]

	tail->next = node;
    6356:	6021      	str	r1, [r4, #0]
	list->tail = node;
    6358:	6291      	str	r1, [r2, #40]	; 0x28
}
    635a:	e00c      	b.n	6376 <move_thread_to_end_of_prio_q+0x56>
	int32_t b1 = thread_1->base.prio;
    635c:	f991 500e 	ldrsb.w	r5, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    6360:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    6364:	42b5      	cmp	r5, r6
    6366:	d00e      	beq.n	6386 <move_thread_to_end_of_prio_q+0x66>
		if (z_sched_prio_cmp(thread, t) > 0) {
    6368:	42ae      	cmp	r6, r5
    636a:	dd0c      	ble.n	6386 <move_thread_to_end_of_prio_q+0x66>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    636c:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    636e:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    6372:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    6374:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    6376:	6890      	ldr	r0, [r2, #8]
    6378:	1a43      	subs	r3, r0, r1
    637a:	4258      	negs	r0, r3
}
    637c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    6380:	4158      	adcs	r0, r3
    6382:	f7ff bfaf 	b.w	62e4 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    6386:	429c      	cmp	r4, r3
    6388:	d0e3      	beq.n	6352 <move_thread_to_end_of_prio_q+0x32>
    638a:	681b      	ldr	r3, [r3, #0]
    638c:	e7e0      	b.n	6350 <move_thread_to_end_of_prio_q+0x30>
    638e:	bf00      	nop
    6390:	20001fa0 	.word	0x20001fa0

00006394 <ready_thread>:
{
    6394:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    6396:	f990 300d 	ldrsb.w	r3, [r0, #13]
    639a:	7b42      	ldrb	r2, [r0, #13]
    639c:	2b00      	cmp	r3, #0
    639e:	db29      	blt.n	63f4 <ready_thread+0x60>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    63a0:	06d3      	lsls	r3, r2, #27
    63a2:	d127      	bne.n	63f4 <ready_thread+0x60>
	return node->next != NULL;
    63a4:	6983      	ldr	r3, [r0, #24]
    63a6:	bb2b      	cbnz	r3, 63f4 <ready_thread+0x60>
	return list->head == list;
    63a8:	4913      	ldr	r1, [pc, #76]	; (63f8 <ready_thread+0x64>)
	thread->base.thread_state |= _THREAD_QUEUED;
    63aa:	f062 027f 	orn	r2, r2, #127	; 0x7f
    63ae:	7342      	strb	r2, [r0, #13]
    63b0:	460a      	mov	r2, r1
    63b2:	f852 4f24 	ldr.w	r4, [r2, #36]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    63b6:	4294      	cmp	r4, r2
    63b8:	bf18      	it	ne
    63ba:	4623      	movne	r3, r4
	return (node == list->tail) ? NULL : node->next;
    63bc:	6a8c      	ldr	r4, [r1, #40]	; 0x28
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    63be:	b923      	cbnz	r3, 63ca <ready_thread+0x36>
	node->prev = tail;
    63c0:	e9c0 2400 	strd	r2, r4, [r0]
	tail->next = node;
    63c4:	6020      	str	r0, [r4, #0]
	list->tail = node;
    63c6:	6288      	str	r0, [r1, #40]	; 0x28
}
    63c8:	e00c      	b.n	63e4 <ready_thread+0x50>
	int32_t b1 = thread_1->base.prio;
    63ca:	f990 500e 	ldrsb.w	r5, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    63ce:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    63d2:	42b5      	cmp	r5, r6
    63d4:	d00a      	beq.n	63ec <ready_thread+0x58>
		if (z_sched_prio_cmp(thread, t) > 0) {
    63d6:	42ae      	cmp	r6, r5
    63d8:	dd08      	ble.n	63ec <ready_thread+0x58>
	sys_dnode_t *const prev = successor->prev;
    63da:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    63dc:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    63e0:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    63e2:	6058      	str	r0, [r3, #4]
}
    63e4:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    63e6:	2000      	movs	r0, #0
    63e8:	f7ff bf7c 	b.w	62e4 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    63ec:	42a3      	cmp	r3, r4
    63ee:	d0e7      	beq.n	63c0 <ready_thread+0x2c>
    63f0:	681b      	ldr	r3, [r3, #0]
    63f2:	e7e4      	b.n	63be <ready_thread+0x2a>
}
    63f4:	bc70      	pop	{r4, r5, r6}
    63f6:	4770      	bx	lr
    63f8:	20001fa0 	.word	0x20001fa0

000063fc <unready_thread>:
{
    63fc:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    63fe:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    6402:	7b43      	ldrb	r3, [r0, #13]
    6404:	2a00      	cmp	r2, #0
{
    6406:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    6408:	da04      	bge.n	6414 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    640a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    640e:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    6410:	f003 fb9f 	bl	9b52 <sys_dlist_remove>
	update_cache(thread == _current);
    6414:	4b04      	ldr	r3, [pc, #16]	; (6428 <unready_thread+0x2c>)
    6416:	6898      	ldr	r0, [r3, #8]
    6418:	1a43      	subs	r3, r0, r1
    641a:	4258      	negs	r0, r3
    641c:	4158      	adcs	r0, r3
}
    641e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    6422:	f7ff bf5f 	b.w	62e4 <update_cache>
    6426:	bf00      	nop
    6428:	20001fa0 	.word	0x20001fa0

0000642c <pend_locked>:
{
    642c:	b570      	push	{r4, r5, r6, lr}
    642e:	4615      	mov	r5, r2
    6430:	461c      	mov	r4, r3
    6432:	4606      	mov	r6, r0
	add_to_waitq_locked(thread, wait_q);
    6434:	f003 fbc1 	bl	9bba <add_to_waitq_locked>
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    6438:	f1b4 3fff 	cmp.w	r4, #4294967295
    643c:	bf08      	it	eq
    643e:	f1b5 3fff 	cmpeq.w	r5, #4294967295
    6442:	d008      	beq.n	6456 <pend_locked+0x2a>
    6444:	462a      	mov	r2, r5
    6446:	4623      	mov	r3, r4
    6448:	f106 0018 	add.w	r0, r6, #24
    644c:	4902      	ldr	r1, [pc, #8]	; (6458 <pend_locked+0x2c>)
}
    644e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    6452:	f000 bae3 	b.w	6a1c <z_add_timeout>
    6456:	bd70      	pop	{r4, r5, r6, pc}
    6458:	00009b77 	.word	0x00009b77

0000645c <k_sched_time_slice_set>:
{
    645c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    645e:	4604      	mov	r4, r0
    6460:	460d      	mov	r5, r1
	__asm__ volatile(
    6462:	f04f 0320 	mov.w	r3, #32
    6466:	f3ef 8711 	mrs	r7, BASEPRI
    646a:	f383 8812 	msr	BASEPRI_MAX, r3
    646e:	f3bf 8f6f 	isb	sy
			return (uint32_t)((t * to_hz + off) / from_hz);
    6472:	2600      	movs	r6, #0
    6474:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
    6478:	f240 30e7 	movw	r0, #999	; 0x3e7
    647c:	4631      	mov	r1, r6
    647e:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    6482:	2300      	movs	r3, #0
    6484:	fbe4 010c 	umlal	r0, r1, r4, ip
    6488:	f7f9 fe3a 	bl	100 <__aeabi_uldivmod>
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    648c:	42b4      	cmp	r4, r6
    648e:	dd02      	ble.n	6496 <k_sched_time_slice_set+0x3a>
			slice_ticks = MAX(2, slice_ticks);
    6490:	2802      	cmp	r0, #2
    6492:	bfb8      	it	lt
    6494:	2002      	movlt	r0, #2
		slice_ticks = k_ms_to_ticks_ceil32(slice);
    6496:	4a07      	ldr	r2, [pc, #28]	; (64b4 <k_sched_time_slice_set+0x58>)
		_current_cpu->slice_ticks = 0;
    6498:	4b07      	ldr	r3, [pc, #28]	; (64b8 <k_sched_time_slice_set+0x5c>)
		slice_ticks = k_ms_to_ticks_ceil32(slice);
    649a:	6010      	str	r0, [r2, #0]
		slice_max_prio = prio;
    649c:	4a07      	ldr	r2, [pc, #28]	; (64bc <k_sched_time_slice_set+0x60>)
		z_reset_time_slice(_current);
    649e:	6898      	ldr	r0, [r3, #8]
		_current_cpu->slice_ticks = 0;
    64a0:	611e      	str	r6, [r3, #16]
		slice_max_prio = prio;
    64a2:	6015      	str	r5, [r2, #0]
		z_reset_time_slice(_current);
    64a4:	f7ff ff0a 	bl	62bc <z_reset_time_slice>
	__asm__ volatile(
    64a8:	f387 8811 	msr	BASEPRI, r7
    64ac:	f3bf 8f6f 	isb	sy
}
    64b0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    64b2:	bf00      	nop
    64b4:	20001fd8 	.word	0x20001fd8
    64b8:	20001fa0 	.word	0x20001fa0
    64bc:	20001fd4 	.word	0x20001fd4

000064c0 <z_time_slice>:
{
    64c0:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    64c2:	f04f 0320 	mov.w	r3, #32
    64c6:	f3ef 8511 	mrs	r5, BASEPRI
    64ca:	f383 8812 	msr	BASEPRI_MAX, r3
    64ce:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    64d2:	4b17      	ldr	r3, [pc, #92]	; (6530 <z_time_slice+0x70>)
    64d4:	4a17      	ldr	r2, [pc, #92]	; (6534 <z_time_slice+0x74>)
    64d6:	689c      	ldr	r4, [r3, #8]
    64d8:	6811      	ldr	r1, [r2, #0]
    64da:	428c      	cmp	r4, r1
    64dc:	d107      	bne.n	64ee <z_time_slice+0x2e>
	z_reset_time_slice(curr);
    64de:	4620      	mov	r0, r4
    64e0:	f7ff feec 	bl	62bc <z_reset_time_slice>
	__asm__ volatile(
    64e4:	f385 8811 	msr	BASEPRI, r5
    64e8:	f3bf 8f6f 	isb	sy
}
    64ec:	bd38      	pop	{r3, r4, r5, pc}
	pending_current = NULL;
    64ee:	2100      	movs	r1, #0
    64f0:	6011      	str	r1, [r2, #0]
	int ret = slice_ticks;
    64f2:	4a11      	ldr	r2, [pc, #68]	; (6538 <z_time_slice+0x78>)
	if (slice_time(_current) && sliceable(_current)) {
    64f4:	6812      	ldr	r2, [r2, #0]
    64f6:	b1c2      	cbz	r2, 652a <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    64f8:	89e2      	ldrh	r2, [r4, #14]
    64fa:	2a7f      	cmp	r2, #127	; 0x7f
    64fc:	d815      	bhi.n	652a <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    64fe:	7b62      	ldrb	r2, [r4, #13]
    6500:	06d2      	lsls	r2, r2, #27
    6502:	d112      	bne.n	652a <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    6504:	4a0d      	ldr	r2, [pc, #52]	; (653c <z_time_slice+0x7c>)
    6506:	f994 100e 	ldrsb.w	r1, [r4, #14]
    650a:	6812      	ldr	r2, [r2, #0]
    650c:	4291      	cmp	r1, r2
    650e:	db0c      	blt.n	652a <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    6510:	4a0b      	ldr	r2, [pc, #44]	; (6540 <z_time_slice+0x80>)
    6512:	4294      	cmp	r4, r2
    6514:	d009      	beq.n	652a <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    6516:	691a      	ldr	r2, [r3, #16]
    6518:	4282      	cmp	r2, r0
    651a:	dc03      	bgt.n	6524 <z_time_slice+0x64>
		move_thread_to_end_of_prio_q(curr);
    651c:	4620      	mov	r0, r4
    651e:	f7ff feff 	bl	6320 <move_thread_to_end_of_prio_q>
    6522:	e7dc      	b.n	64de <z_time_slice+0x1e>
			_current_cpu->slice_ticks -= ticks;
    6524:	1a12      	subs	r2, r2, r0
		_current_cpu->slice_ticks = 0;
    6526:	611a      	str	r2, [r3, #16]
    6528:	e7dc      	b.n	64e4 <z_time_slice+0x24>
    652a:	2200      	movs	r2, #0
    652c:	e7fb      	b.n	6526 <z_time_slice+0x66>
    652e:	bf00      	nop
    6530:	20001fa0 	.word	0x20001fa0
    6534:	20001fd0 	.word	0x20001fd0
    6538:	20001fd8 	.word	0x20001fd8
    653c:	20001fd4 	.word	0x20001fd4
    6540:	200002b0 	.word	0x200002b0

00006544 <z_pend_curr>:
{
    6544:	b570      	push	{r4, r5, r6, lr}
	pending_current = _current;
    6546:	480c      	ldr	r0, [pc, #48]	; (6578 <z_pend_curr+0x34>)
    6548:	4d0c      	ldr	r5, [pc, #48]	; (657c <z_pend_curr+0x38>)
    654a:	6886      	ldr	r6, [r0, #8]
    654c:	602e      	str	r6, [r5, #0]
{
    654e:	460c      	mov	r4, r1
    6550:	4611      	mov	r1, r2
    6552:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
	__asm__ volatile(
    6556:	f04f 0620 	mov.w	r6, #32
    655a:	f3ef 8511 	mrs	r5, BASEPRI
    655e:	f386 8812 	msr	BASEPRI_MAX, r6
    6562:	f3bf 8f6f 	isb	sy
	pend_locked(_current, wait_q, timeout);
    6566:	6880      	ldr	r0, [r0, #8]
    6568:	f7ff ff60 	bl	642c <pend_locked>
	ret = arch_swap(key);
    656c:	4620      	mov	r0, r4
}
    656e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    6572:	f7fb bdab 	b.w	20cc <arch_swap>
    6576:	bf00      	nop
    6578:	20001fa0 	.word	0x20001fa0
    657c:	20001fd0 	.word	0x20001fd0

00006580 <z_set_prio>:
{
    6580:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6582:	4604      	mov	r4, r0
    6584:	f04f 0320 	mov.w	r3, #32
    6588:	f3ef 8611 	mrs	r6, BASEPRI
    658c:	f383 8812 	msr	BASEPRI_MAX, r3
    6590:	f3bf 8f6f 	isb	sy
	uint8_t state = thread->base.thread_state;
    6594:	7b43      	ldrb	r3, [r0, #13]
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    6596:	06da      	lsls	r2, r3, #27
				thread->base.prio = prio;
    6598:	b249      	sxtb	r1, r1
    659a:	d119      	bne.n	65d0 <z_set_prio+0x50>
	return node->next != NULL;
    659c:	6985      	ldr	r5, [r0, #24]
    659e:	b9bd      	cbnz	r5, 65d0 <z_set_prio+0x50>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    65a0:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    65a4:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    65a6:	f003 fad4 	bl	9b52 <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    65aa:	7b43      	ldrb	r3, [r0, #13]
	return list->head == list;
    65ac:	4a16      	ldr	r2, [pc, #88]	; (6608 <z_set_prio+0x88>)
				thread->base.prio = prio;
    65ae:	7381      	strb	r1, [r0, #14]
	thread->base.thread_state |= _THREAD_QUEUED;
    65b0:	f063 037f 	orn	r3, r3, #127	; 0x7f
    65b4:	7343      	strb	r3, [r0, #13]
    65b6:	4613      	mov	r3, r2
    65b8:	f853 0f24 	ldr.w	r0, [r3, #36]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    65bc:	4298      	cmp	r0, r3
    65be:	bf18      	it	ne
    65c0:	4605      	movne	r5, r0
	return (node == list->tail) ? NULL : node->next;
    65c2:	6a90      	ldr	r0, [r2, #40]	; 0x28
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    65c4:	b95d      	cbnz	r5, 65de <z_set_prio+0x5e>
	node->prev = tail;
    65c6:	e9c4 3000 	strd	r3, r0, [r4]
	tail->next = node;
    65ca:	6004      	str	r4, [r0, #0]
	list->tail = node;
    65cc:	6294      	str	r4, [r2, #40]	; 0x28
}
    65ce:	e011      	b.n	65f4 <z_set_prio+0x74>
			thread->base.prio = prio;
    65d0:	73a1      	strb	r1, [r4, #14]
    65d2:	2000      	movs	r0, #0
	__asm__ volatile(
    65d4:	f386 8811 	msr	BASEPRI, r6
    65d8:	f3bf 8f6f 	isb	sy
}
    65dc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	int32_t b2 = thread_2->base.prio;
    65de:	f995 700e 	ldrsb.w	r7, [r5, #14]
	if (b1 != b2) {
    65e2:	42b9      	cmp	r1, r7
    65e4:	d00b      	beq.n	65fe <z_set_prio+0x7e>
		if (z_sched_prio_cmp(thread, t) > 0) {
    65e6:	428f      	cmp	r7, r1
    65e8:	dd09      	ble.n	65fe <z_set_prio+0x7e>
	sys_dnode_t *const prev = successor->prev;
    65ea:	686b      	ldr	r3, [r5, #4]
	node->next = successor;
    65ec:	e9c4 5300 	strd	r5, r3, [r4]
	prev->next = node;
    65f0:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    65f2:	606c      	str	r4, [r5, #4]
			update_cache(1);
    65f4:	2001      	movs	r0, #1
    65f6:	f7ff fe75 	bl	62e4 <update_cache>
    65fa:	2001      	movs	r0, #1
    65fc:	e7ea      	b.n	65d4 <z_set_prio+0x54>
	return (node == list->tail) ? NULL : node->next;
    65fe:	42a8      	cmp	r0, r5
    6600:	d0e1      	beq.n	65c6 <z_set_prio+0x46>
    6602:	682d      	ldr	r5, [r5, #0]
    6604:	e7de      	b.n	65c4 <z_set_prio+0x44>
    6606:	bf00      	nop
    6608:	20001fa0 	.word	0x20001fa0

0000660c <z_reschedule>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    660c:	b949      	cbnz	r1, 6622 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    660e:	f3ef 8005 	mrs	r0, IPSR
    6612:	b930      	cbnz	r0, 6622 <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    6614:	4b05      	ldr	r3, [pc, #20]	; (662c <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    6616:	6a1a      	ldr	r2, [r3, #32]
    6618:	689b      	ldr	r3, [r3, #8]
    661a:	429a      	cmp	r2, r3
    661c:	d001      	beq.n	6622 <z_reschedule+0x16>
    661e:	f7fb bd55 	b.w	20cc <arch_swap>
    6622:	f381 8811 	msr	BASEPRI, r1
    6626:	f3bf 8f6f 	isb	sy
}
    662a:	4770      	bx	lr
    662c:	20001fa0 	.word	0x20001fa0

00006630 <z_sched_start>:
{
    6630:	b510      	push	{r4, lr}
	__asm__ volatile(
    6632:	f04f 0220 	mov.w	r2, #32
    6636:	f3ef 8411 	mrs	r4, BASEPRI
    663a:	f382 8812 	msr	BASEPRI_MAX, r2
    663e:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    6642:	7b42      	ldrb	r2, [r0, #13]
	if (z_has_thread_started(thread)) {
    6644:	0751      	lsls	r1, r2, #29
    6646:	d404      	bmi.n	6652 <z_sched_start+0x22>
	__asm__ volatile(
    6648:	f384 8811 	msr	BASEPRI, r4
    664c:	f3bf 8f6f 	isb	sy
}
    6650:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    6652:	f022 0204 	bic.w	r2, r2, #4
    6656:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    6658:	f7ff fe9c 	bl	6394 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    665c:	4621      	mov	r1, r4
    665e:	4802      	ldr	r0, [pc, #8]	; (6668 <z_sched_start+0x38>)
}
    6660:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    6664:	f7ff bfd2 	b.w	660c <z_reschedule>
    6668:	200026d8 	.word	0x200026d8

0000666c <z_impl_k_thread_suspend>:
{
    666c:	b570      	push	{r4, r5, r6, lr}
    666e:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    6670:	3018      	adds	r0, #24
    6672:	f003 fb0c 	bl	9c8e <z_abort_timeout>
	__asm__ volatile(
    6676:	f04f 0320 	mov.w	r3, #32
    667a:	f3ef 8611 	mrs	r6, BASEPRI
    667e:	f383 8812 	msr	BASEPRI_MAX, r3
    6682:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    6686:	f994 200d 	ldrsb.w	r2, [r4, #13]
	return (thread->base.thread_state & state) != 0U;
    668a:	7b63      	ldrb	r3, [r4, #13]
    668c:	2a00      	cmp	r2, #0
    668e:	da05      	bge.n	669c <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    6690:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    6694:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    6696:	4620      	mov	r0, r4
    6698:	f003 fa5b 	bl	9b52 <sys_dlist_remove>
		update_cache(thread == _current);
    669c:	4d0b      	ldr	r5, [pc, #44]	; (66cc <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    669e:	7b63      	ldrb	r3, [r4, #13]
    66a0:	68a8      	ldr	r0, [r5, #8]
    66a2:	f043 0310 	orr.w	r3, r3, #16
    66a6:	7363      	strb	r3, [r4, #13]
    66a8:	1b03      	subs	r3, r0, r4
    66aa:	4258      	negs	r0, r3
    66ac:	4158      	adcs	r0, r3
    66ae:	f7ff fe19 	bl	62e4 <update_cache>
	__asm__ volatile(
    66b2:	f386 8811 	msr	BASEPRI, r6
    66b6:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    66ba:	68ab      	ldr	r3, [r5, #8]
    66bc:	42a3      	cmp	r3, r4
    66be:	d103      	bne.n	66c8 <z_impl_k_thread_suspend+0x5c>
}
    66c0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    66c4:	f003 bad9 	b.w	9c7a <z_reschedule_unlocked>
}
    66c8:	bd70      	pop	{r4, r5, r6, pc}
    66ca:	bf00      	nop
    66cc:	20001fa0 	.word	0x20001fa0

000066d0 <k_sched_lock>:
	__asm__ volatile(
    66d0:	f04f 0320 	mov.w	r3, #32
    66d4:	f3ef 8111 	mrs	r1, BASEPRI
    66d8:	f383 8812 	msr	BASEPRI_MAX, r3
    66dc:	f3bf 8f6f 	isb	sy
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    66e0:	4b04      	ldr	r3, [pc, #16]	; (66f4 <k_sched_lock+0x24>)
    66e2:	689a      	ldr	r2, [r3, #8]
    66e4:	7bd3      	ldrb	r3, [r2, #15]
    66e6:	3b01      	subs	r3, #1
    66e8:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    66ea:	f381 8811 	msr	BASEPRI, r1
    66ee:	f3bf 8f6f 	isb	sy
}
    66f2:	4770      	bx	lr
    66f4:	20001fa0 	.word	0x20001fa0

000066f8 <k_sched_unlock>:
{
    66f8:	b510      	push	{r4, lr}
	__asm__ volatile(
    66fa:	f04f 0320 	mov.w	r3, #32
    66fe:	f3ef 8411 	mrs	r4, BASEPRI
    6702:	f383 8812 	msr	BASEPRI_MAX, r3
    6706:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    670a:	4b08      	ldr	r3, [pc, #32]	; (672c <k_sched_unlock+0x34>)
    670c:	689a      	ldr	r2, [r3, #8]
    670e:	7bd3      	ldrb	r3, [r2, #15]
    6710:	3301      	adds	r3, #1
    6712:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    6714:	2000      	movs	r0, #0
    6716:	f7ff fde5 	bl	62e4 <update_cache>
	__asm__ volatile(
    671a:	f384 8811 	msr	BASEPRI, r4
    671e:	f3bf 8f6f 	isb	sy
}
    6722:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    6726:	f003 baa8 	b.w	9c7a <z_reschedule_unlocked>
    672a:	bf00      	nop
    672c:	20001fa0 	.word	0x20001fa0

00006730 <z_sched_init>:
	list->head = (sys_dnode_t *)list;
    6730:	4b04      	ldr	r3, [pc, #16]	; (6744 <z_sched_init+0x14>)
#else
	init_ready_q(&_kernel.ready_q);
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    6732:	2100      	movs	r1, #0
    6734:	f103 0224 	add.w	r2, r3, #36	; 0x24
	list->tail = (sys_dnode_t *)list;
    6738:	e9c3 2209 	strd	r2, r2, [r3, #36]	; 0x24
    673c:	4608      	mov	r0, r1
    673e:	f7ff be8d 	b.w	645c <k_sched_time_slice_set>
    6742:	bf00      	nop
    6744:	20001fa0 	.word	0x20001fa0

00006748 <z_impl_k_yield>:
	return !(k_is_pre_kernel() || k_is_in_isr() ||
		 z_is_idle_thread_object(_current));
}

void z_impl_k_yield(void)
{
    6748:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    674a:	f04f 0320 	mov.w	r3, #32
    674e:	f3ef 8511 	mrs	r5, BASEPRI
    6752:	f383 8812 	msr	BASEPRI_MAX, r3
    6756:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    675a:	4919      	ldr	r1, [pc, #100]	; (67c0 <z_impl_k_yield+0x78>)
    675c:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    675e:	7b43      	ldrb	r3, [r0, #13]
    6760:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    6764:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    6766:	f003 f9f4 	bl	9b52 <sys_dlist_remove>
	}
	queue_thread(_current);
    676a:	688b      	ldr	r3, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    676c:	7b5a      	ldrb	r2, [r3, #13]
	return list->head == list;
    676e:	4608      	mov	r0, r1
    6770:	f062 027f 	orn	r2, r2, #127	; 0x7f
    6774:	735a      	strb	r2, [r3, #13]
    6776:	f850 2f24 	ldr.w	r2, [r0, #36]!
	return (node == list->tail) ? NULL : node->next;
    677a:	6a8c      	ldr	r4, [r1, #40]	; 0x28
	return sys_dlist_is_empty(list) ? NULL : list->head;
    677c:	4282      	cmp	r2, r0
    677e:	bf08      	it	eq
    6780:	2200      	moveq	r2, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6782:	b922      	cbnz	r2, 678e <z_impl_k_yield+0x46>
	node->prev = tail;
    6784:	e9c3 0400 	strd	r0, r4, [r3]
	tail->next = node;
    6788:	6023      	str	r3, [r4, #0]
	list->tail = node;
    678a:	628b      	str	r3, [r1, #40]	; 0x28
}
    678c:	e00c      	b.n	67a8 <z_impl_k_yield+0x60>
	int32_t b1 = thread_1->base.prio;
    678e:	f993 600e 	ldrsb.w	r6, [r3, #14]
	int32_t b2 = thread_2->base.prio;
    6792:	f992 700e 	ldrsb.w	r7, [r2, #14]
	if (b1 != b2) {
    6796:	42be      	cmp	r6, r7
    6798:	d00e      	beq.n	67b8 <z_impl_k_yield+0x70>
		if (z_sched_prio_cmp(thread, t) > 0) {
    679a:	42b7      	cmp	r7, r6
    679c:	dd0c      	ble.n	67b8 <z_impl_k_yield+0x70>
	sys_dnode_t *const prev = successor->prev;
    679e:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    67a0:	e9c3 2100 	strd	r2, r1, [r3]
	prev->next = node;
    67a4:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    67a6:	6053      	str	r3, [r2, #4]
	update_cache(1);
    67a8:	2001      	movs	r0, #1
    67aa:	f7ff fd9b 	bl	62e4 <update_cache>
    67ae:	4628      	mov	r0, r5
	z_swap(&sched_spinlock, key);
}
    67b0:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    67b4:	f7fb bc8a 	b.w	20cc <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    67b8:	42a2      	cmp	r2, r4
    67ba:	d0e3      	beq.n	6784 <z_impl_k_yield+0x3c>
    67bc:	6812      	ldr	r2, [r2, #0]
    67be:	e7e0      	b.n	6782 <z_impl_k_yield+0x3a>
    67c0:	20001fa0 	.word	0x20001fa0

000067c4 <z_tick_sleep>:
	 */
	LOG_DBG("thread %p for %u ticks", _current, ticks);
#endif

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    67c4:	ea50 0301 	orrs.w	r3, r0, r1
{
    67c8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    67cc:	4605      	mov	r5, r0
    67ce:	460e      	mov	r6, r1
	if (ticks == 0) {
    67d0:	d103      	bne.n	67da <z_tick_sleep+0x16>
	z_impl_k_yield();
    67d2:	f7ff ffb9 	bl	6748 <z_impl_k_yield>
		k_yield();
		return 0;
    67d6:	2000      	movs	r0, #0
    67d8:	e02c      	b.n	6834 <z_tick_sleep+0x70>
	}

	k_timeout_t timeout = Z_TIMEOUT_TICKS(ticks);
	if (Z_TICK_ABS(ticks) <= 0) {
    67da:	1c83      	adds	r3, r0, #2
    67dc:	f171 33ff 	sbcs.w	r3, r1, #4294967295
    67e0:	db2a      	blt.n	6838 <z_tick_sleep+0x74>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    67e2:	f003 fa96 	bl	9d12 <sys_clock_tick_get_32>
    67e6:	1944      	adds	r4, r0, r5
    67e8:	f04f 0320 	mov.w	r3, #32
    67ec:	f3ef 8811 	mrs	r8, BASEPRI
    67f0:	f383 8812 	msr	BASEPRI_MAX, r3
    67f4:	f3bf 8f6f 	isb	sy
	}

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    67f8:	4f11      	ldr	r7, [pc, #68]	; (6840 <z_tick_sleep+0x7c>)
    67fa:	4b12      	ldr	r3, [pc, #72]	; (6844 <z_tick_sleep+0x80>)
    67fc:	68b8      	ldr	r0, [r7, #8]
    67fe:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
    6800:	f7ff fdfc 	bl	63fc <unready_thread>
	z_add_thread_timeout(_current, timeout);
    6804:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    6806:	4910      	ldr	r1, [pc, #64]	; (6848 <z_tick_sleep+0x84>)
    6808:	462a      	mov	r2, r5
    680a:	4633      	mov	r3, r6
    680c:	3018      	adds	r0, #24
    680e:	f000 f905 	bl	6a1c <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    6812:	68ba      	ldr	r2, [r7, #8]
	thread->base.thread_state |= _THREAD_SUSPENDED;
    6814:	7b53      	ldrb	r3, [r2, #13]
    6816:	f043 0310 	orr.w	r3, r3, #16
    681a:	7353      	strb	r3, [r2, #13]
    681c:	4640      	mov	r0, r8
    681e:	f7fb fc55 	bl	20cc <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    6822:	f003 fa76 	bl	9d12 <sys_clock_tick_get_32>
    6826:	1a20      	subs	r0, r4, r0
    6828:	eb63 0303 	sbc.w	r3, r3, r3
	if (ticks > 0) {
    682c:	2801      	cmp	r0, #1
    682e:	f173 0300 	sbcs.w	r3, r3, #0
    6832:	dbd0      	blt.n	67d6 <z_tick_sleep+0x12>
		return ticks;
	}
#endif

	return 0;
}
    6834:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    6838:	f06f 0401 	mvn.w	r4, #1
    683c:	1a24      	subs	r4, r4, r0
    683e:	e7d3      	b.n	67e8 <z_tick_sleep+0x24>
    6840:	20001fa0 	.word	0x20001fa0
    6844:	20001fd0 	.word	0x20001fd0
    6848:	00009b77 	.word	0x00009b77

0000684c <z_impl_k_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    684c:	f1b1 3fff 	cmp.w	r1, #4294967295
    6850:	bf08      	it	eq
    6852:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    6856:	b508      	push	{r3, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    6858:	d106      	bne.n	6868 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    685a:	4b08      	ldr	r3, [pc, #32]	; (687c <z_impl_k_sleep+0x30>)
    685c:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    685e:	f7ff ff05 	bl	666c <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    6862:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    6866:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    6868:	f7ff ffac 	bl	67c4 <z_tick_sleep>
			return ((t * to_hz + off) / from_hz);
    686c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    6870:	fb80 0303 	smull	r0, r3, r0, r3
    6874:	0bc0      	lsrs	r0, r0, #15
    6876:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    687a:	e7f4      	b.n	6866 <z_impl_k_sleep+0x1a>
    687c:	20001fa0 	.word	0x20001fa0

00006880 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    6880:	4b01      	ldr	r3, [pc, #4]	; (6888 <z_impl_z_current_get+0x8>)
    6882:	6898      	ldr	r0, [r3, #8]
    6884:	4770      	bx	lr
    6886:	bf00      	nop
    6888:	20001fa0 	.word	0x20001fa0

0000688c <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    688c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6890:	4604      	mov	r4, r0
    6892:	f04f 0320 	mov.w	r3, #32
    6896:	f3ef 8611 	mrs	r6, BASEPRI
    689a:	f383 8812 	msr	BASEPRI_MAX, r3
    689e:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.user_options & K_ESSENTIAL) != 0) {
    68a2:	7b03      	ldrb	r3, [r0, #12]
    68a4:	07d9      	lsls	r1, r3, #31
    68a6:	d50b      	bpl.n	68c0 <z_thread_abort+0x34>
	__asm__ volatile(
    68a8:	f386 8811 	msr	BASEPRI, r6
    68ac:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&sched_spinlock, key);
		__ASSERT(false, "aborting essential thread %p", thread);
		k_panic();
    68b0:	4040      	eors	r0, r0
    68b2:	f380 8811 	msr	BASEPRI, r0
    68b6:	f04f 0004 	mov.w	r0, #4
    68ba:	df02      	svc	2
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    68bc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    68c0:	7b43      	ldrb	r3, [r0, #13]
    68c2:	071a      	lsls	r2, r3, #28
    68c4:	d504      	bpl.n	68d0 <z_thread_abort+0x44>
    68c6:	f386 8811 	msr	BASEPRI, r6
    68ca:	f3bf 8f6f 	isb	sy
    68ce:	e7f5      	b.n	68bc <z_thread_abort+0x30>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    68d0:	f023 0220 	bic.w	r2, r3, #32
    68d4:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    68d8:	09d2      	lsrs	r2, r2, #7
    68da:	d120      	bne.n	691e <z_thread_abort+0x92>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    68dc:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    68de:	68a3      	ldr	r3, [r4, #8]
    68e0:	b113      	cbz	r3, 68e8 <z_thread_abort+0x5c>
			unpend_thread_no_timeout(thread);
    68e2:	4620      	mov	r0, r4
    68e4:	f003 f93d 	bl	9b62 <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    68e8:	f104 0018 	add.w	r0, r4, #24
    68ec:	f003 f9cf 	bl	9c8e <z_abort_timeout>
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    68f0:	f104 0758 	add.w	r7, r4, #88	; 0x58
    68f4:	f04f 0800 	mov.w	r8, #0
	return list->head == list;
    68f8:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    68fa:	42bd      	cmp	r5, r7
    68fc:	d000      	beq.n	6900 <z_thread_abort+0x74>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    68fe:	b9b5      	cbnz	r5, 692e <z_thread_abort+0xa2>
		update_cache(1);
    6900:	2001      	movs	r0, #1
    6902:	f7ff fcef 	bl	62e4 <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    6906:	4b10      	ldr	r3, [pc, #64]	; (6948 <z_thread_abort+0xbc>)
    6908:	689b      	ldr	r3, [r3, #8]
    690a:	42a3      	cmp	r3, r4
    690c:	d1db      	bne.n	68c6 <z_thread_abort+0x3a>
    690e:	f3ef 8305 	mrs	r3, IPSR
    6912:	2b00      	cmp	r3, #0
    6914:	d1d7      	bne.n	68c6 <z_thread_abort+0x3a>
    6916:	4630      	mov	r0, r6
    6918:	f7fb fbd8 	bl	20cc <arch_swap>
	return ret;
    691c:	e7d3      	b.n	68c6 <z_thread_abort+0x3a>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    691e:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    6922:	f043 0308 	orr.w	r3, r3, #8
    6926:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    6928:	f003 f913 	bl	9b52 <sys_dlist_remove>
}
    692c:	e7d7      	b.n	68de <z_thread_abort+0x52>
		unpend_thread_no_timeout(thread);
    692e:	4628      	mov	r0, r5
    6930:	f003 f917 	bl	9b62 <unpend_thread_no_timeout>
    6934:	f105 0018 	add.w	r0, r5, #24
    6938:	f003 f9a9 	bl	9c8e <z_abort_timeout>
    693c:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
		ready_thread(thread);
    6940:	4628      	mov	r0, r5
    6942:	f7ff fd27 	bl	6394 <ready_thread>
    6946:	e7d7      	b.n	68f8 <z_thread_abort+0x6c>
    6948:	20001fa0 	.word	0x20001fa0

0000694c <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    694c:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    694e:	4806      	ldr	r0, [pc, #24]	; (6968 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    6950:	4a06      	ldr	r2, [pc, #24]	; (696c <z_data_copy+0x20>)
    6952:	4907      	ldr	r1, [pc, #28]	; (6970 <z_data_copy+0x24>)
    6954:	1a12      	subs	r2, r2, r0
    6956:	f003 f883 	bl	9a60 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    695a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    695e:	4a05      	ldr	r2, [pc, #20]	; (6974 <z_data_copy+0x28>)
    6960:	4905      	ldr	r1, [pc, #20]	; (6978 <z_data_copy+0x2c>)
    6962:	4806      	ldr	r0, [pc, #24]	; (697c <z_data_copy+0x30>)
    6964:	f003 b87c 	b.w	9a60 <z_early_memcpy>
    6968:	20000000 	.word	0x20000000
    696c:	20000290 	.word	0x20000290
    6970:	0000b5b0 	.word	0x0000b5b0
    6974:	00000000 	.word	0x00000000
    6978:	0000b5b0 	.word	0x0000b5b0
    697c:	20000000 	.word	0x20000000

00006980 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    6980:	4b03      	ldr	r3, [pc, #12]	; (6990 <elapsed+0x10>)
    6982:	681b      	ldr	r3, [r3, #0]
    6984:	b90b      	cbnz	r3, 698a <elapsed+0xa>
    6986:	f7fd be69 	b.w	465c <sys_clock_elapsed>
}
    698a:	2000      	movs	r0, #0
    698c:	4770      	bx	lr
    698e:	bf00      	nop
    6990:	20001fdc 	.word	0x20001fdc

00006994 <next_timeout>:

static int32_t next_timeout(void)
{
    6994:	b510      	push	{r4, lr}
	return list->head == list;
    6996:	4b11      	ldr	r3, [pc, #68]	; (69dc <next_timeout+0x48>)
    6998:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    699a:	429c      	cmp	r4, r3
    699c:	d10a      	bne.n	69b4 <next_timeout+0x20>
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    699e:	f7ff ffef 	bl	6980 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
		ret = MAX_WAIT;
    69a2:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
	}

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    69a6:	4b0e      	ldr	r3, [pc, #56]	; (69e0 <next_timeout+0x4c>)
    69a8:	691b      	ldr	r3, [r3, #16]
    69aa:	b113      	cbz	r3, 69b2 <next_timeout+0x1e>
    69ac:	4298      	cmp	r0, r3
    69ae:	bfa8      	it	ge
    69b0:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    69b2:	bd10      	pop	{r4, pc}
	int32_t ticks_elapsed = elapsed();
    69b4:	f7ff ffe4 	bl	6980 <elapsed>
	if ((to == NULL) ||
    69b8:	2c00      	cmp	r4, #0
    69ba:	d0f2      	beq.n	69a2 <next_timeout+0xe>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    69bc:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    69c0:	1a1b      	subs	r3, r3, r0
    69c2:	eb62 72e0 	sbc.w	r2, r2, r0, asr #31
	if ((to == NULL) ||
    69c6:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    69ca:	f172 0100 	sbcs.w	r1, r2, #0
    69ce:	dae8      	bge.n	69a2 <next_timeout+0xe>
		ret = MAX(0, to->dticks - ticks_elapsed);
    69d0:	2a00      	cmp	r2, #0
    69d2:	bfac      	ite	ge
    69d4:	4618      	movge	r0, r3
    69d6:	2000      	movlt	r0, #0
    69d8:	e7e5      	b.n	69a6 <next_timeout+0x12>
    69da:	bf00      	nop
    69dc:	200001c4 	.word	0x200001c4
    69e0:	20001fa0 	.word	0x20001fa0

000069e4 <remove_timeout>:
{
    69e4:	b530      	push	{r4, r5, lr}
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    69e6:	b170      	cbz	r0, 6a06 <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    69e8:	4b0b      	ldr	r3, [pc, #44]	; (6a18 <remove_timeout+0x34>)
    69ea:	685b      	ldr	r3, [r3, #4]
    69ec:	4298      	cmp	r0, r3
    69ee:	d00a      	beq.n	6a06 <remove_timeout+0x22>
    69f0:	6803      	ldr	r3, [r0, #0]
	if (next(t) != NULL) {
    69f2:	b143      	cbz	r3, 6a06 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    69f4:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    69f8:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    69fc:	1912      	adds	r2, r2, r4
    69fe:	eb41 0105 	adc.w	r1, r1, r5
    6a02:	e9c3 2104 	strd	r2, r1, [r3, #16]
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
	sys_dnode_t *const next = node->next;
    6a06:	e9d0 3200 	ldrd	r3, r2, [r0]

	prev->next = next;
    6a0a:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    6a0c:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    6a0e:	2300      	movs	r3, #0
	node->prev = NULL;
    6a10:	e9c0 3300 	strd	r3, r3, [r0]
}
    6a14:	bd30      	pop	{r4, r5, pc}
    6a16:	bf00      	nop
    6a18:	200001c4 	.word	0x200001c4

00006a1c <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    6a1c:	f1b3 3fff 	cmp.w	r3, #4294967295
    6a20:	bf08      	it	eq
    6a22:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    6a26:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6a28:	4604      	mov	r4, r0
    6a2a:	461d      	mov	r5, r3
    6a2c:	4616      	mov	r6, r2
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    6a2e:	d061      	beq.n	6af4 <z_add_timeout+0xd8>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    6a30:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    6a32:	f04f 0320 	mov.w	r3, #32
    6a36:	f3ef 8711 	mrs	r7, BASEPRI
    6a3a:	f383 8812 	msr	BASEPRI_MAX, r3
    6a3e:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    6a42:	3201      	adds	r2, #1
    6a44:	f175 33ff 	sbcs.w	r3, r5, #4294967295
    6a48:	da24      	bge.n	6a94 <z_add_timeout+0x78>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    6a4a:	4930      	ldr	r1, [pc, #192]	; (6b0c <z_add_timeout+0xf0>)
    6a4c:	e9d1 2000 	ldrd	r2, r0, [r1]
    6a50:	f06f 0301 	mvn.w	r3, #1
    6a54:	1a9b      	subs	r3, r3, r2
    6a56:	f04f 32ff 	mov.w	r2, #4294967295
    6a5a:	eb62 0000 	sbc.w	r0, r2, r0
    6a5e:	1b9e      	subs	r6, r3, r6
    6a60:	eb60 0005 	sbc.w	r0, r0, r5

			to->dticks = MAX(1, ticks);
    6a64:	2e01      	cmp	r6, #1
    6a66:	f170 0300 	sbcs.w	r3, r0, #0
    6a6a:	da01      	bge.n	6a70 <z_add_timeout+0x54>
    6a6c:	2601      	movs	r6, #1
    6a6e:	2000      	movs	r0, #0
    6a70:	e9c4 6004 	strd	r6, r0, [r4, #16]
	return list->head == list;
    6a74:	4e26      	ldr	r6, [pc, #152]	; (6b10 <z_add_timeout+0xf4>)
    6a76:	f8d6 c000 	ldr.w	ip, [r6]
	return (node == list->tail) ? NULL : node->next;
    6a7a:	6875      	ldr	r5, [r6, #4]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6a7c:	45b4      	cmp	ip, r6
    6a7e:	bf08      	it	eq
    6a80:	f04f 0c00 	moveq.w	ip, #0
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
		}

		for (t = first(); t != NULL; t = next(t)) {
    6a84:	f1bc 0f00 	cmp.w	ip, #0
    6a88:	d10d      	bne.n	6aa6 <z_add_timeout+0x8a>
	node->prev = tail;
    6a8a:	e9c4 6500 	strd	r6, r5, [r4]
	tail->next = node;
    6a8e:	602c      	str	r4, [r5, #0]
	list->tail = node;
    6a90:	6074      	str	r4, [r6, #4]
}
    6a92:	e01c      	b.n	6ace <z_add_timeout+0xb2>
			to->dticks = timeout.ticks + 1 + elapsed();
    6a94:	f7ff ff74 	bl	6980 <elapsed>
    6a98:	3601      	adds	r6, #1
    6a9a:	f145 0500 	adc.w	r5, r5, #0
    6a9e:	1836      	adds	r6, r6, r0
    6aa0:	eb45 70e0 	adc.w	r0, r5, r0, asr #31
    6aa4:	e7e4      	b.n	6a70 <z_add_timeout+0x54>
			if (t->dticks > to->dticks) {
    6aa6:	e9dc 2004 	ldrd	r2, r0, [ip, #16]
    6aaa:	e9d4 3104 	ldrd	r3, r1, [r4, #16]
    6aae:	4293      	cmp	r3, r2
    6ab0:	eb71 0e00 	sbcs.w	lr, r1, r0
    6ab4:	da1f      	bge.n	6af6 <z_add_timeout+0xda>
				t->dticks -= to->dticks;
    6ab6:	1ad2      	subs	r2, r2, r3
	sys_dnode_t *const prev = successor->prev;
    6ab8:	f8dc 3004 	ldr.w	r3, [ip, #4]
    6abc:	eb60 0001 	sbc.w	r0, r0, r1
    6ac0:	e9cc 2004 	strd	r2, r0, [ip, #16]
	node->next = successor;
    6ac4:	e9c4 c300 	strd	ip, r3, [r4]
	prev->next = node;
    6ac8:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    6aca:	f8cc 4004 	str.w	r4, [ip, #4]
	return list->head == list;
    6ace:	6833      	ldr	r3, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6ad0:	42b3      	cmp	r3, r6
    6ad2:	d00b      	beq.n	6aec <z_add_timeout+0xd0>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    6ad4:	429c      	cmp	r4, r3
    6ad6:	d109      	bne.n	6aec <z_add_timeout+0xd0>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    6ad8:	f7ff ff5c 	bl	6994 <next_timeout>

			if (next_time == 0 ||
    6adc:	b118      	cbz	r0, 6ae6 <z_add_timeout+0xca>
			    _current_cpu->slice_ticks != next_time) {
    6ade:	4b0d      	ldr	r3, [pc, #52]	; (6b14 <z_add_timeout+0xf8>)
			if (next_time == 0 ||
    6ae0:	691b      	ldr	r3, [r3, #16]
    6ae2:	4283      	cmp	r3, r0
    6ae4:	d002      	beq.n	6aec <z_add_timeout+0xd0>
				sys_clock_set_timeout(next_time, false);
    6ae6:	2100      	movs	r1, #0
    6ae8:	f7fd fd86 	bl	45f8 <sys_clock_set_timeout>
	__asm__ volatile(
    6aec:	f387 8811 	msr	BASEPRI, r7
    6af0:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    6af4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			to->dticks -= t->dticks;
    6af6:	1a9b      	subs	r3, r3, r2
    6af8:	eb61 0100 	sbc.w	r1, r1, r0
	return (node == list->tail) ? NULL : node->next;
    6afc:	45ac      	cmp	ip, r5
    6afe:	e9c4 3104 	strd	r3, r1, [r4, #16]
    6b02:	d0c2      	beq.n	6a8a <z_add_timeout+0x6e>
    6b04:	f8dc c000 	ldr.w	ip, [ip]
    6b08:	e7bc      	b.n	6a84 <z_add_timeout+0x68>
    6b0a:	bf00      	nop
    6b0c:	20000430 	.word	0x20000430
    6b10:	200001c4 	.word	0x200001c4
    6b14:	20001fa0 	.word	0x20001fa0

00006b18 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    6b18:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    6b1c:	4604      	mov	r4, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    6b1e:	f7ff fccf 	bl	64c0 <z_time_slice>
	__asm__ volatile(
    6b22:	f04f 0320 	mov.w	r3, #32
    6b26:	f3ef 8611 	mrs	r6, BASEPRI
    6b2a:	f383 8812 	msr	BASEPRI_MAX, r3
    6b2e:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    6b32:	4f23      	ldr	r7, [pc, #140]	; (6bc0 <sys_clock_announce+0xa8>)
	return list->head == list;
    6b34:	f8df 8090 	ldr.w	r8, [pc, #144]	; 6bc8 <sys_clock_announce+0xb0>
    6b38:	f8d8 0000 	ldr.w	r0, [r8]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    6b3c:	4a21      	ldr	r2, [pc, #132]	; (6bc4 <sys_clock_announce+0xac>)
	announce_remaining = ticks;
    6b3e:	603c      	str	r4, [r7, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6b40:	4540      	cmp	r0, r8
		curr_tick += dt;
    6b42:	e9d2 3e00 	ldrd	r3, lr, [r2]
    6b46:	ea4f 71e4 	mov.w	r1, r4, asr #31
    6b4a:	d00b      	beq.n	6b64 <sys_clock_announce+0x4c>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    6b4c:	b150      	cbz	r0, 6b64 <sys_clock_announce+0x4c>
    6b4e:	e9d0 5c04 	ldrd	r5, ip, [r0, #16]
    6b52:	42ac      	cmp	r4, r5
    6b54:	eb71 090c 	sbcs.w	r9, r1, ip
    6b58:	da16      	bge.n	6b88 <sys_clock_announce+0x70>
		key = k_spin_lock(&timeout_lock);
		announce_remaining -= dt;
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    6b5a:	1b2d      	subs	r5, r5, r4
    6b5c:	eb6c 0c01 	sbc.w	ip, ip, r1
    6b60:	e9c0 5c04 	strd	r5, ip, [r0, #16]
	}

	curr_tick += announce_remaining;
    6b64:	18e3      	adds	r3, r4, r3
    6b66:	eb4e 0101 	adc.w	r1, lr, r1
	announce_remaining = 0;
    6b6a:	2400      	movs	r4, #0
	curr_tick += announce_remaining;
    6b6c:	e9c2 3100 	strd	r3, r1, [r2]
	announce_remaining = 0;
    6b70:	603c      	str	r4, [r7, #0]

	sys_clock_set_timeout(next_timeout(), false);
    6b72:	f7ff ff0f 	bl	6994 <next_timeout>
    6b76:	4621      	mov	r1, r4
    6b78:	f7fd fd3e 	bl	45f8 <sys_clock_set_timeout>
	__asm__ volatile(
    6b7c:	f386 8811 	msr	BASEPRI, r6
    6b80:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    6b84:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    6b88:	18eb      	adds	r3, r5, r3
    6b8a:	eb4e 71e5 	adc.w	r1, lr, r5, asr #31
    6b8e:	e9c2 3100 	strd	r3, r1, [r2]
		t->dticks = 0;
    6b92:	2200      	movs	r2, #0
    6b94:	2300      	movs	r3, #0
    6b96:	e9c0 2304 	strd	r2, r3, [r0, #16]
		remove_timeout(t);
    6b9a:	f7ff ff23 	bl	69e4 <remove_timeout>
    6b9e:	f386 8811 	msr	BASEPRI, r6
    6ba2:	f3bf 8f6f 	isb	sy
		t->fn(t);
    6ba6:	6883      	ldr	r3, [r0, #8]
    6ba8:	4798      	blx	r3
	__asm__ volatile(
    6baa:	f04f 0320 	mov.w	r3, #32
    6bae:	f3ef 8611 	mrs	r6, BASEPRI
    6bb2:	f383 8812 	msr	BASEPRI_MAX, r3
    6bb6:	f3bf 8f6f 	isb	sy
		announce_remaining -= dt;
    6bba:	683c      	ldr	r4, [r7, #0]
    6bbc:	1b64      	subs	r4, r4, r5
    6bbe:	e7bb      	b.n	6b38 <sys_clock_announce+0x20>
    6bc0:	20001fdc 	.word	0x20001fdc
    6bc4:	20000430 	.word	0x20000430
    6bc8:	200001c4 	.word	0x200001c4

00006bcc <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    6bcc:	b510      	push	{r4, lr}
    6bce:	f04f 0320 	mov.w	r3, #32
    6bd2:	f3ef 8411 	mrs	r4, BASEPRI
    6bd6:	f383 8812 	msr	BASEPRI_MAX, r3
    6bda:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + elapsed();
    6bde:	f7ff fecf 	bl	6980 <elapsed>
    6be2:	4a06      	ldr	r2, [pc, #24]	; (6bfc <sys_clock_tick_get+0x30>)
    6be4:	4603      	mov	r3, r0
    6be6:	e9d2 0100 	ldrd	r0, r1, [r2]
    6bea:	1818      	adds	r0, r3, r0
    6bec:	eb41 71e3 	adc.w	r1, r1, r3, asr #31
	__asm__ volatile(
    6bf0:	f384 8811 	msr	BASEPRI, r4
    6bf4:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    6bf8:	bd10      	pop	{r4, pc}
    6bfa:	bf00      	nop
    6bfc:	20000430 	.word	0x20000430

00006c00 <boot_banner>:
	printk("***** delaying boot " DELAY_STR "ms (per build configuration) *****\n");
	k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */

#if CONFIG_BOOT_BANNER
	printk("*** Booting Zephyr OS build " BANNER_VERSION BANNER_POSTFIX " ***\n");
    6c00:	4801      	ldr	r0, [pc, #4]	; (6c08 <boot_banner+0x8>)
    6c02:	f001 bf74 	b.w	8aee <printk>
    6c06:	bf00      	nop
    6c08:	0000b57f 	.word	0x0000b57f

00006c0c <nrf_cc3xx_platform_init_no_rng>:
    6c0c:	b510      	push	{r4, lr}
    6c0e:	4c0a      	ldr	r4, [pc, #40]	; (6c38 <nrf_cc3xx_platform_init_no_rng+0x2c>)
    6c10:	6823      	ldr	r3, [r4, #0]
    6c12:	b11b      	cbz	r3, 6c1c <nrf_cc3xx_platform_init_no_rng+0x10>
    6c14:	2301      	movs	r3, #1
    6c16:	6023      	str	r3, [r4, #0]
    6c18:	2000      	movs	r0, #0
    6c1a:	bd10      	pop	{r4, pc}
    6c1c:	f000 f8f2 	bl	6e04 <CC_LibInitNoRng>
    6c20:	2800      	cmp	r0, #0
    6c22:	d0f7      	beq.n	6c14 <nrf_cc3xx_platform_init_no_rng+0x8>
    6c24:	3801      	subs	r0, #1
    6c26:	2806      	cmp	r0, #6
    6c28:	d803      	bhi.n	6c32 <nrf_cc3xx_platform_init_no_rng+0x26>
    6c2a:	4b04      	ldr	r3, [pc, #16]	; (6c3c <nrf_cc3xx_platform_init_no_rng+0x30>)
    6c2c:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    6c30:	bd10      	pop	{r4, pc}
    6c32:	4803      	ldr	r0, [pc, #12]	; (6c40 <nrf_cc3xx_platform_init_no_rng+0x34>)
    6c34:	bd10      	pop	{r4, pc}
    6c36:	bf00      	nop
    6c38:	20001fe0 	.word	0x20001fe0
    6c3c:	0000a458 	.word	0x0000a458
    6c40:	ffff8ffe 	.word	0xffff8ffe

00006c44 <nrf_cc3xx_platform_abort>:
    6c44:	f3bf 8f4f 	dsb	sy
    6c48:	4905      	ldr	r1, [pc, #20]	; (6c60 <nrf_cc3xx_platform_abort+0x1c>)
    6c4a:	4b06      	ldr	r3, [pc, #24]	; (6c64 <nrf_cc3xx_platform_abort+0x20>)
    6c4c:	68ca      	ldr	r2, [r1, #12]
    6c4e:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    6c52:	4313      	orrs	r3, r2
    6c54:	60cb      	str	r3, [r1, #12]
    6c56:	f3bf 8f4f 	dsb	sy
    6c5a:	bf00      	nop
    6c5c:	e7fd      	b.n	6c5a <nrf_cc3xx_platform_abort+0x16>
    6c5e:	bf00      	nop
    6c60:	e000ed00 	.word	0xe000ed00
    6c64:	05fa0004 	.word	0x05fa0004

00006c68 <CC_PalAbort>:
    6c68:	b410      	push	{r4}
    6c6a:	4b0a      	ldr	r3, [pc, #40]	; (6c94 <CC_PalAbort+0x2c>)
    6c6c:	490a      	ldr	r1, [pc, #40]	; (6c98 <CC_PalAbort+0x30>)
    6c6e:	4c0b      	ldr	r4, [pc, #44]	; (6c9c <CC_PalAbort+0x34>)
    6c70:	f04f 32fe 	mov.w	r2, #4278124286	; 0xfefefefe
    6c74:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    6c78:	6849      	ldr	r1, [r1, #4]
    6c7a:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    6c7e:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    6c82:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    6c86:	2300      	movs	r3, #0
    6c88:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    6c8c:	f85d 4b04 	ldr.w	r4, [sp], #4
    6c90:	4708      	bx	r1
    6c92:	bf00      	nop
    6c94:	5002b000 	.word	0x5002b000
    6c98:	200001cc 	.word	0x200001cc
    6c9c:	5002a000 	.word	0x5002a000

00006ca0 <nrf_cc3xx_platform_set_abort>:
    6ca0:	e9d0 1200 	ldrd	r1, r2, [r0]
    6ca4:	4b01      	ldr	r3, [pc, #4]	; (6cac <nrf_cc3xx_platform_set_abort+0xc>)
    6ca6:	e9c3 1200 	strd	r1, r2, [r3]
    6caa:	4770      	bx	lr
    6cac:	200001cc 	.word	0x200001cc

00006cb0 <mutex_free>:
    6cb0:	b510      	push	{r4, lr}
    6cb2:	4604      	mov	r4, r0
    6cb4:	b150      	cbz	r0, 6ccc <mutex_free+0x1c>
    6cb6:	6863      	ldr	r3, [r4, #4]
    6cb8:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    6cbc:	d005      	beq.n	6cca <mutex_free+0x1a>
    6cbe:	4a06      	ldr	r2, [pc, #24]	; (6cd8 <mutex_free+0x28>)
    6cc0:	4293      	cmp	r3, r2
    6cc2:	d002      	beq.n	6cca <mutex_free+0x1a>
    6cc4:	2300      	movs	r3, #0
    6cc6:	6023      	str	r3, [r4, #0]
    6cc8:	6062      	str	r2, [r4, #4]
    6cca:	bd10      	pop	{r4, pc}
    6ccc:	4b03      	ldr	r3, [pc, #12]	; (6cdc <mutex_free+0x2c>)
    6cce:	4804      	ldr	r0, [pc, #16]	; (6ce0 <mutex_free+0x30>)
    6cd0:	685b      	ldr	r3, [r3, #4]
    6cd2:	4798      	blx	r3
    6cd4:	e7ef      	b.n	6cb6 <mutex_free+0x6>
    6cd6:	bf00      	nop
    6cd8:	a95c5f2c 	.word	0xa95c5f2c
    6cdc:	200001cc 	.word	0x200001cc
    6ce0:	0000a474 	.word	0x0000a474

00006ce4 <mutex_lock>:
    6ce4:	b1c8      	cbz	r0, 6d1a <mutex_lock+0x36>
    6ce6:	6843      	ldr	r3, [r0, #4]
    6ce8:	4a0d      	ldr	r2, [pc, #52]	; (6d20 <mutex_lock+0x3c>)
    6cea:	4293      	cmp	r3, r2
    6cec:	d013      	beq.n	6d16 <mutex_lock+0x32>
    6cee:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    6cf2:	d00e      	beq.n	6d12 <mutex_lock+0x2e>
    6cf4:	2301      	movs	r3, #1
    6cf6:	e850 2f00 	ldrex	r2, [r0]
    6cfa:	4619      	mov	r1, r3
    6cfc:	e840 1c00 	strex	ip, r1, [r0]
    6d00:	f09c 0f00 	teq	ip, #0
    6d04:	d1f7      	bne.n	6cf6 <mutex_lock+0x12>
    6d06:	2a01      	cmp	r2, #1
    6d08:	d0f5      	beq.n	6cf6 <mutex_lock+0x12>
    6d0a:	f3bf 8f5f 	dmb	sy
    6d0e:	2000      	movs	r0, #0
    6d10:	4770      	bx	lr
    6d12:	4804      	ldr	r0, [pc, #16]	; (6d24 <mutex_lock+0x40>)
    6d14:	4770      	bx	lr
    6d16:	4804      	ldr	r0, [pc, #16]	; (6d28 <mutex_lock+0x44>)
    6d18:	4770      	bx	lr
    6d1a:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    6d1e:	4770      	bx	lr
    6d20:	a95c5f2c 	.word	0xa95c5f2c
    6d24:	ffff8fe9 	.word	0xffff8fe9
    6d28:	ffff8fea 	.word	0xffff8fea

00006d2c <mutex_unlock>:
    6d2c:	b180      	cbz	r0, 6d50 <mutex_unlock+0x24>
    6d2e:	6843      	ldr	r3, [r0, #4]
    6d30:	4a09      	ldr	r2, [pc, #36]	; (6d58 <mutex_unlock+0x2c>)
    6d32:	4293      	cmp	r3, r2
    6d34:	d00a      	beq.n	6d4c <mutex_unlock+0x20>
    6d36:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    6d3a:	d005      	beq.n	6d48 <mutex_unlock+0x1c>
    6d3c:	f3bf 8f5f 	dmb	sy
    6d40:	2300      	movs	r3, #0
    6d42:	6003      	str	r3, [r0, #0]
    6d44:	4618      	mov	r0, r3
    6d46:	4770      	bx	lr
    6d48:	4804      	ldr	r0, [pc, #16]	; (6d5c <mutex_unlock+0x30>)
    6d4a:	4770      	bx	lr
    6d4c:	4804      	ldr	r0, [pc, #16]	; (6d60 <mutex_unlock+0x34>)
    6d4e:	4770      	bx	lr
    6d50:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    6d54:	4770      	bx	lr
    6d56:	bf00      	nop
    6d58:	a95c5f2c 	.word	0xa95c5f2c
    6d5c:	ffff8fe9 	.word	0xffff8fe9
    6d60:	ffff8fea 	.word	0xffff8fea

00006d64 <mutex_init>:
    6d64:	b510      	push	{r4, lr}
    6d66:	4604      	mov	r4, r0
    6d68:	b120      	cbz	r0, 6d74 <mutex_init+0x10>
    6d6a:	4b04      	ldr	r3, [pc, #16]	; (6d7c <mutex_init+0x18>)
    6d6c:	6063      	str	r3, [r4, #4]
    6d6e:	2200      	movs	r2, #0
    6d70:	6022      	str	r2, [r4, #0]
    6d72:	bd10      	pop	{r4, pc}
    6d74:	4802      	ldr	r0, [pc, #8]	; (6d80 <mutex_init+0x1c>)
    6d76:	f7ff ff77 	bl	6c68 <CC_PalAbort>
    6d7a:	e7f6      	b.n	6d6a <mutex_init+0x6>
    6d7c:	3a00003a 	.word	0x3a00003a
    6d80:	0000a49c 	.word	0x0000a49c

00006d84 <nrf_cc3xx_platform_set_mutexes>:
    6d84:	b570      	push	{r4, r5, r6, lr}
    6d86:	e9d0 2300 	ldrd	r2, r3, [r0]
    6d8a:	4c15      	ldr	r4, [pc, #84]	; (6de0 <nrf_cc3xx_platform_set_mutexes+0x5c>)
    6d8c:	4d15      	ldr	r5, [pc, #84]	; (6de4 <nrf_cc3xx_platform_set_mutexes+0x60>)
    6d8e:	6063      	str	r3, [r4, #4]
    6d90:	e9d0 3002 	ldrd	r3, r0, [r0, #8]
    6d94:	e9c4 3002 	strd	r3, r0, [r4, #8]
    6d98:	6022      	str	r2, [r4, #0]
    6d9a:	4b13      	ldr	r3, [pc, #76]	; (6de8 <nrf_cc3xx_platform_set_mutexes+0x64>)
    6d9c:	6808      	ldr	r0, [r1, #0]
    6d9e:	6018      	str	r0, [r3, #0]
    6da0:	6848      	ldr	r0, [r1, #4]
    6da2:	6058      	str	r0, [r3, #4]
    6da4:	6888      	ldr	r0, [r1, #8]
    6da6:	6098      	str	r0, [r3, #8]
    6da8:	e9d1 0103 	ldrd	r0, r1, [r1, #12]
    6dac:	60d8      	str	r0, [r3, #12]
    6dae:	6119      	str	r1, [r3, #16]
    6db0:	f8d5 3118 	ldr.w	r3, [r5, #280]	; 0x118
    6db4:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    6db8:	d010      	beq.n	6ddc <nrf_cc3xx_platform_set_mutexes+0x58>
    6dba:	490c      	ldr	r1, [pc, #48]	; (6dec <nrf_cc3xx_platform_set_mutexes+0x68>)
    6dbc:	f8c5 11bc 	str.w	r1, [r5, #444]	; 0x1bc
    6dc0:	2300      	movs	r3, #0
    6dc2:	e9c5 3145 	strd	r3, r1, [r5, #276]	; 0x114
    6dc6:	f505 708a 	add.w	r0, r5, #276	; 0x114
    6dca:	f8c5 31b8 	str.w	r3, [r5, #440]	; 0x1b8
    6dce:	4790      	blx	r2
    6dd0:	6823      	ldr	r3, [r4, #0]
    6dd2:	f505 70dc 	add.w	r0, r5, #440	; 0x1b8
    6dd6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    6dda:	4718      	bx	r3
    6ddc:	bd70      	pop	{r4, r5, r6, pc}
    6dde:	bf00      	nop
    6de0:	200001dc 	.word	0x200001dc
    6de4:	20001ff8 	.word	0x20001ff8
    6de8:	200001ec 	.word	0x200001ec
    6dec:	a95c5f2c 	.word	0xa95c5f2c

00006df0 <mbedtls_platform_zeroize>:
    6df0:	b138      	cbz	r0, 6e02 <mbedtls_platform_zeroize+0x12>
    6df2:	b131      	cbz	r1, 6e02 <mbedtls_platform_zeroize+0x12>
    6df4:	4401      	add	r1, r0
    6df6:	2200      	movs	r2, #0
    6df8:	4603      	mov	r3, r0
    6dfa:	3001      	adds	r0, #1
    6dfc:	4288      	cmp	r0, r1
    6dfe:	701a      	strb	r2, [r3, #0]
    6e00:	d1fa      	bne.n	6df8 <mbedtls_platform_zeroize+0x8>
    6e02:	4770      	bx	lr

00006e04 <CC_LibInitNoRng>:
    6e04:	b538      	push	{r3, r4, r5, lr}
    6e06:	f000 f82f 	bl	6e68 <CC_HalInit>
    6e0a:	b120      	cbz	r0, 6e16 <CC_LibInitNoRng+0x12>
    6e0c:	2403      	movs	r4, #3
    6e0e:	f000 f863 	bl	6ed8 <CC_PalTerminate>
    6e12:	4620      	mov	r0, r4
    6e14:	bd38      	pop	{r3, r4, r5, pc}
    6e16:	f000 f831 	bl	6e7c <CC_PalInit>
    6e1a:	b998      	cbnz	r0, 6e44 <CC_LibInitNoRng+0x40>
    6e1c:	f000 f8ac 	bl	6f78 <CC_PalPowerSaveModeSelect>
    6e20:	b998      	cbnz	r0, 6e4a <CC_LibInitNoRng+0x46>
    6e22:	4d0f      	ldr	r5, [pc, #60]	; (6e60 <CC_LibInitNoRng+0x5c>)
    6e24:	f8d5 3928 	ldr.w	r3, [r5, #2344]	; 0x928
    6e28:	0e1b      	lsrs	r3, r3, #24
    6e2a:	2bf0      	cmp	r3, #240	; 0xf0
    6e2c:	d108      	bne.n	6e40 <CC_LibInitNoRng+0x3c>
    6e2e:	f8d5 2a24 	ldr.w	r2, [r5, #2596]	; 0xa24
    6e32:	4b0c      	ldr	r3, [pc, #48]	; (6e64 <CC_LibInitNoRng+0x60>)
    6e34:	429a      	cmp	r2, r3
    6e36:	d00a      	beq.n	6e4e <CC_LibInitNoRng+0x4a>
    6e38:	2407      	movs	r4, #7
    6e3a:	f000 f817 	bl	6e6c <CC_HalTerminate>
    6e3e:	e7e6      	b.n	6e0e <CC_LibInitNoRng+0xa>
    6e40:	2406      	movs	r4, #6
    6e42:	e7fa      	b.n	6e3a <CC_LibInitNoRng+0x36>
    6e44:	2404      	movs	r4, #4
    6e46:	4620      	mov	r0, r4
    6e48:	bd38      	pop	{r3, r4, r5, pc}
    6e4a:	2400      	movs	r4, #0
    6e4c:	e7f5      	b.n	6e3a <CC_LibInitNoRng+0x36>
    6e4e:	2001      	movs	r0, #1
    6e50:	f000 f892 	bl	6f78 <CC_PalPowerSaveModeSelect>
    6e54:	4604      	mov	r4, r0
    6e56:	2800      	cmp	r0, #0
    6e58:	d1f7      	bne.n	6e4a <CC_LibInitNoRng+0x46>
    6e5a:	f8c5 0a0c 	str.w	r0, [r5, #2572]	; 0xa0c
    6e5e:	e7d8      	b.n	6e12 <CC_LibInitNoRng+0xe>
    6e60:	5002b000 	.word	0x5002b000
    6e64:	20e00000 	.word	0x20e00000

00006e68 <CC_HalInit>:
    6e68:	2000      	movs	r0, #0
    6e6a:	4770      	bx	lr

00006e6c <CC_HalTerminate>:
    6e6c:	2000      	movs	r0, #0
    6e6e:	4770      	bx	lr

00006e70 <CC_HalMaskInterrupt>:
    6e70:	4b01      	ldr	r3, [pc, #4]	; (6e78 <CC_HalMaskInterrupt+0x8>)
    6e72:	f8c3 0a04 	str.w	r0, [r3, #2564]	; 0xa04
    6e76:	4770      	bx	lr
    6e78:	5002b000 	.word	0x5002b000

00006e7c <CC_PalInit>:
    6e7c:	b510      	push	{r4, lr}
    6e7e:	4811      	ldr	r0, [pc, #68]	; (6ec4 <CC_PalInit+0x48>)
    6e80:	f000 f848 	bl	6f14 <CC_PalMutexCreate>
    6e84:	b100      	cbz	r0, 6e88 <CC_PalInit+0xc>
    6e86:	bd10      	pop	{r4, pc}
    6e88:	480f      	ldr	r0, [pc, #60]	; (6ec8 <CC_PalInit+0x4c>)
    6e8a:	f000 f843 	bl	6f14 <CC_PalMutexCreate>
    6e8e:	2800      	cmp	r0, #0
    6e90:	d1f9      	bne.n	6e86 <CC_PalInit+0xa>
    6e92:	4c0e      	ldr	r4, [pc, #56]	; (6ecc <CC_PalInit+0x50>)
    6e94:	4620      	mov	r0, r4
    6e96:	f000 f83d 	bl	6f14 <CC_PalMutexCreate>
    6e9a:	2800      	cmp	r0, #0
    6e9c:	d1f3      	bne.n	6e86 <CC_PalInit+0xa>
    6e9e:	4b0c      	ldr	r3, [pc, #48]	; (6ed0 <CC_PalInit+0x54>)
    6ea0:	480c      	ldr	r0, [pc, #48]	; (6ed4 <CC_PalInit+0x58>)
    6ea2:	601c      	str	r4, [r3, #0]
    6ea4:	f000 f836 	bl	6f14 <CC_PalMutexCreate>
    6ea8:	4601      	mov	r1, r0
    6eaa:	2800      	cmp	r0, #0
    6eac:	d1eb      	bne.n	6e86 <CC_PalInit+0xa>
    6eae:	f000 f82d 	bl	6f0c <CC_PalDmaInit>
    6eb2:	4604      	mov	r4, r0
    6eb4:	b108      	cbz	r0, 6eba <CC_PalInit+0x3e>
    6eb6:	4620      	mov	r0, r4
    6eb8:	bd10      	pop	{r4, pc}
    6eba:	f000 f83f 	bl	6f3c <CC_PalPowerSaveModeInit>
    6ebe:	4620      	mov	r0, r4
    6ec0:	e7fa      	b.n	6eb8 <CC_PalInit+0x3c>
    6ec2:	bf00      	nop
    6ec4:	20000224 	.word	0x20000224
    6ec8:	20000218 	.word	0x20000218
    6ecc:	20000220 	.word	0x20000220
    6ed0:	20000228 	.word	0x20000228
    6ed4:	2000021c 	.word	0x2000021c

00006ed8 <CC_PalTerminate>:
    6ed8:	b508      	push	{r3, lr}
    6eda:	4808      	ldr	r0, [pc, #32]	; (6efc <CC_PalTerminate+0x24>)
    6edc:	f000 f824 	bl	6f28 <CC_PalMutexDestroy>
    6ee0:	4807      	ldr	r0, [pc, #28]	; (6f00 <CC_PalTerminate+0x28>)
    6ee2:	f000 f821 	bl	6f28 <CC_PalMutexDestroy>
    6ee6:	4807      	ldr	r0, [pc, #28]	; (6f04 <CC_PalTerminate+0x2c>)
    6ee8:	f000 f81e 	bl	6f28 <CC_PalMutexDestroy>
    6eec:	4806      	ldr	r0, [pc, #24]	; (6f08 <CC_PalTerminate+0x30>)
    6eee:	f000 f81b 	bl	6f28 <CC_PalMutexDestroy>
    6ef2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    6ef6:	f000 b80b 	b.w	6f10 <CC_PalDmaTerminate>
    6efa:	bf00      	nop
    6efc:	20000224 	.word	0x20000224
    6f00:	20000218 	.word	0x20000218
    6f04:	20000220 	.word	0x20000220
    6f08:	2000021c 	.word	0x2000021c

00006f0c <CC_PalDmaInit>:
    6f0c:	2000      	movs	r0, #0
    6f0e:	4770      	bx	lr

00006f10 <CC_PalDmaTerminate>:
    6f10:	4770      	bx	lr
    6f12:	bf00      	nop

00006f14 <CC_PalMutexCreate>:
    6f14:	b508      	push	{r3, lr}
    6f16:	4b03      	ldr	r3, [pc, #12]	; (6f24 <CC_PalMutexCreate+0x10>)
    6f18:	6802      	ldr	r2, [r0, #0]
    6f1a:	681b      	ldr	r3, [r3, #0]
    6f1c:	6810      	ldr	r0, [r2, #0]
    6f1e:	4798      	blx	r3
    6f20:	2000      	movs	r0, #0
    6f22:	bd08      	pop	{r3, pc}
    6f24:	200001dc 	.word	0x200001dc

00006f28 <CC_PalMutexDestroy>:
    6f28:	b508      	push	{r3, lr}
    6f2a:	4b03      	ldr	r3, [pc, #12]	; (6f38 <CC_PalMutexDestroy+0x10>)
    6f2c:	6802      	ldr	r2, [r0, #0]
    6f2e:	685b      	ldr	r3, [r3, #4]
    6f30:	6810      	ldr	r0, [r2, #0]
    6f32:	4798      	blx	r3
    6f34:	2000      	movs	r0, #0
    6f36:	bd08      	pop	{r3, pc}
    6f38:	200001dc 	.word	0x200001dc

00006f3c <CC_PalPowerSaveModeInit>:
    6f3c:	b570      	push	{r4, r5, r6, lr}
    6f3e:	4c09      	ldr	r4, [pc, #36]	; (6f64 <CC_PalPowerSaveModeInit+0x28>)
    6f40:	4d09      	ldr	r5, [pc, #36]	; (6f68 <CC_PalPowerSaveModeInit+0x2c>)
    6f42:	6920      	ldr	r0, [r4, #16]
    6f44:	68ab      	ldr	r3, [r5, #8]
    6f46:	4798      	blx	r3
    6f48:	b118      	cbz	r0, 6f52 <CC_PalPowerSaveModeInit+0x16>
    6f4a:	4b08      	ldr	r3, [pc, #32]	; (6f6c <CC_PalPowerSaveModeInit+0x30>)
    6f4c:	4808      	ldr	r0, [pc, #32]	; (6f70 <CC_PalPowerSaveModeInit+0x34>)
    6f4e:	685b      	ldr	r3, [r3, #4]
    6f50:	4798      	blx	r3
    6f52:	4a08      	ldr	r2, [pc, #32]	; (6f74 <CC_PalPowerSaveModeInit+0x38>)
    6f54:	68eb      	ldr	r3, [r5, #12]
    6f56:	6920      	ldr	r0, [r4, #16]
    6f58:	2100      	movs	r1, #0
    6f5a:	6011      	str	r1, [r2, #0]
    6f5c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    6f60:	4718      	bx	r3
    6f62:	bf00      	nop
    6f64:	200001ec 	.word	0x200001ec
    6f68:	200001dc 	.word	0x200001dc
    6f6c:	200001cc 	.word	0x200001cc
    6f70:	0000a4c0 	.word	0x0000a4c0
    6f74:	20001ff4 	.word	0x20001ff4

00006f78 <CC_PalPowerSaveModeSelect>:
    6f78:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6f7a:	4d1a      	ldr	r5, [pc, #104]	; (6fe4 <CC_PalPowerSaveModeSelect+0x6c>)
    6f7c:	4e1a      	ldr	r6, [pc, #104]	; (6fe8 <CC_PalPowerSaveModeSelect+0x70>)
    6f7e:	4604      	mov	r4, r0
    6f80:	68b2      	ldr	r2, [r6, #8]
    6f82:	6928      	ldr	r0, [r5, #16]
    6f84:	4790      	blx	r2
    6f86:	b9e8      	cbnz	r0, 6fc4 <CC_PalPowerSaveModeSelect+0x4c>
    6f88:	4f18      	ldr	r7, [pc, #96]	; (6fec <CC_PalPowerSaveModeSelect+0x74>)
    6f8a:	683b      	ldr	r3, [r7, #0]
    6f8c:	b14c      	cbz	r4, 6fa2 <CC_PalPowerSaveModeSelect+0x2a>
    6f8e:	b1a3      	cbz	r3, 6fba <CC_PalPowerSaveModeSelect+0x42>
    6f90:	2b01      	cmp	r3, #1
    6f92:	d019      	beq.n	6fc8 <CC_PalPowerSaveModeSelect+0x50>
    6f94:	3b01      	subs	r3, #1
    6f96:	603b      	str	r3, [r7, #0]
    6f98:	6928      	ldr	r0, [r5, #16]
    6f9a:	68f3      	ldr	r3, [r6, #12]
    6f9c:	4798      	blx	r3
    6f9e:	2000      	movs	r0, #0
    6fa0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    6fa2:	b943      	cbnz	r3, 6fb6 <CC_PalPowerSaveModeSelect+0x3e>
    6fa4:	4a12      	ldr	r2, [pc, #72]	; (6ff0 <CC_PalPowerSaveModeSelect+0x78>)
    6fa6:	2101      	movs	r1, #1
    6fa8:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    6fac:	4911      	ldr	r1, [pc, #68]	; (6ff4 <CC_PalPowerSaveModeSelect+0x7c>)
    6fae:	f8d1 2910 	ldr.w	r2, [r1, #2320]	; 0x910
    6fb2:	2a00      	cmp	r2, #0
    6fb4:	d1fb      	bne.n	6fae <CC_PalPowerSaveModeSelect+0x36>
    6fb6:	3301      	adds	r3, #1
    6fb8:	603b      	str	r3, [r7, #0]
    6fba:	68f3      	ldr	r3, [r6, #12]
    6fbc:	6928      	ldr	r0, [r5, #16]
    6fbe:	4798      	blx	r3
    6fc0:	2000      	movs	r0, #0
    6fc2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    6fc4:	480c      	ldr	r0, [pc, #48]	; (6ff8 <CC_PalPowerSaveModeSelect+0x80>)
    6fc6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    6fc8:	4a0a      	ldr	r2, [pc, #40]	; (6ff4 <CC_PalPowerSaveModeSelect+0x7c>)
    6fca:	f8d2 3910 	ldr.w	r3, [r2, #2320]	; 0x910
    6fce:	2b00      	cmp	r3, #0
    6fd0:	d1fb      	bne.n	6fca <CC_PalPowerSaveModeSelect+0x52>
    6fd2:	4a07      	ldr	r2, [pc, #28]	; (6ff0 <CC_PalPowerSaveModeSelect+0x78>)
    6fd4:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    6fd8:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    6fdc:	f7ff ff48 	bl	6e70 <CC_HalMaskInterrupt>
    6fe0:	683b      	ldr	r3, [r7, #0]
    6fe2:	e7d7      	b.n	6f94 <CC_PalPowerSaveModeSelect+0x1c>
    6fe4:	200001ec 	.word	0x200001ec
    6fe8:	200001dc 	.word	0x200001dc
    6fec:	20001ff4 	.word	0x20001ff4
    6ff0:	5002a000 	.word	0x5002a000
    6ff4:	5002b000 	.word	0x5002b000
    6ff8:	ffff8fe9 	.word	0xffff8fe9

00006ffc <verify_context_ecdsa_verify_secp256r1>:
    6ffc:	b130      	cbz	r0, 700c <verify_context_ecdsa_verify_secp256r1+0x10>
    6ffe:	6802      	ldr	r2, [r0, #0]
    7000:	4b03      	ldr	r3, [pc, #12]	; (7010 <verify_context_ecdsa_verify_secp256r1+0x14>)
    7002:	4804      	ldr	r0, [pc, #16]	; (7014 <verify_context_ecdsa_verify_secp256r1+0x18>)
    7004:	429a      	cmp	r2, r3
    7006:	bf08      	it	eq
    7008:	2000      	moveq	r0, #0
    700a:	4770      	bx	lr
    700c:	4802      	ldr	r0, [pc, #8]	; (7018 <verify_context_ecdsa_verify_secp256r1+0x1c>)
    700e:	4770      	bx	lr
    7010:	bbaa55dd 	.word	0xbbaa55dd
    7014:	00f00882 	.word	0x00f00882
    7018:	00f00871 	.word	0x00f00871

0000701c <nrf_cc310_bl_ecdsa_verify_init_secp256r1>:
    701c:	b538      	push	{r3, r4, r5, lr}
    701e:	460d      	mov	r5, r1
    7020:	4604      	mov	r4, r0
    7022:	b1b0      	cbz	r0, 7052 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x36>
    7024:	22a0      	movs	r2, #160	; 0xa0
    7026:	2100      	movs	r1, #0
    7028:	3004      	adds	r0, #4
    702a:	f002 fe94 	bl	9d56 <SaSi_PalMemSet>
    702e:	b195      	cbz	r5, 7056 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x3a>
    7030:	2208      	movs	r2, #8
    7032:	4629      	mov	r1, r5
    7034:	f104 0064 	add.w	r0, r4, #100	; 0x64
    7038:	f002 fe93 	bl	9d62 <CRYS_COMMON_ReverseMemcpy32>
    703c:	2208      	movs	r2, #8
    703e:	f105 0120 	add.w	r1, r5, #32
    7042:	f104 0084 	add.w	r0, r4, #132	; 0x84
    7046:	f002 fe8c 	bl	9d62 <CRYS_COMMON_ReverseMemcpy32>
    704a:	4b04      	ldr	r3, [pc, #16]	; (705c <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x40>)
    704c:	6023      	str	r3, [r4, #0]
    704e:	2000      	movs	r0, #0
    7050:	bd38      	pop	{r3, r4, r5, pc}
    7052:	4803      	ldr	r0, [pc, #12]	; (7060 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x44>)
    7054:	e7fc      	b.n	7050 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x34>
    7056:	4803      	ldr	r0, [pc, #12]	; (7064 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x48>)
    7058:	e7fa      	b.n	7050 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x34>
    705a:	bf00      	nop
    705c:	bbaa55dd 	.word	0xbbaa55dd
    7060:	00f00871 	.word	0x00f00871
    7064:	00f00883 	.word	0x00f00883

00007068 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1>:
    7068:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    706c:	4605      	mov	r5, r0
    706e:	460e      	mov	r6, r1
    7070:	4699      	mov	r9, r3
    7072:	4611      	mov	r1, r2
    7074:	f7ff ffc2 	bl	6ffc <verify_context_ecdsa_verify_secp256r1>
    7078:	4604      	mov	r4, r0
    707a:	2800      	cmp	r0, #0
    707c:	f040 8084 	bne.w	7188 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    7080:	2e00      	cmp	r6, #0
    7082:	f000 8085 	beq.w	7190 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x128>
    7086:	2900      	cmp	r1, #0
    7088:	f000 8084 	beq.w	7194 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x12c>
    708c:	f1b9 0f20 	cmp.w	r9, #32
    7090:	f040 8082 	bne.w	7198 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x130>
    7094:	f105 0444 	add.w	r4, r5, #68	; 0x44
    7098:	2208      	movs	r2, #8
    709a:	f105 0804 	add.w	r8, r5, #4
    709e:	4620      	mov	r0, r4
    70a0:	f002 fe5f 	bl	9d62 <CRYS_COMMON_ReverseMemcpy32>
    70a4:	f105 0724 	add.w	r7, r5, #36	; 0x24
    70a8:	2208      	movs	r2, #8
    70aa:	4631      	mov	r1, r6
    70ac:	4640      	mov	r0, r8
    70ae:	f002 fe58 	bl	9d62 <CRYS_COMMON_ReverseMemcpy32>
    70b2:	f106 0120 	add.w	r1, r6, #32
    70b6:	2208      	movs	r2, #8
    70b8:	4638      	mov	r0, r7
    70ba:	f002 fe52 	bl	9d62 <CRYS_COMMON_ReverseMemcpy32>
    70be:	a902      	add	r1, sp, #8
    70c0:	f44f 7080 	mov.w	r0, #256	; 0x100
    70c4:	f841 9d04 	str.w	r9, [r1, #-4]!
    70c8:	f002 fe3f 	bl	9d4a <PkaInitAndMutexLock>
    70cc:	2800      	cmp	r0, #0
    70ce:	d165      	bne.n	719c <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x134>
    70d0:	4a33      	ldr	r2, [pc, #204]	; (71a0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x138>)
    70d2:	f44f 7380 	mov.w	r3, #256	; 0x100
    70d6:	6013      	str	r3, [r2, #0]
    70d8:	2101      	movs	r1, #1
    70da:	6093      	str	r3, [r2, #8]
    70dc:	2308      	movs	r3, #8
    70de:	4a31      	ldr	r2, [pc, #196]	; (71a4 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x13c>)
    70e0:	f000 fb2e 	bl	7740 <PkaCopyDataIntoPkaReg>
    70e4:	2101      	movs	r1, #1
    70e6:	4608      	mov	r0, r1
    70e8:	2305      	movs	r3, #5
    70ea:	4a2f      	ldr	r2, [pc, #188]	; (71a8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x140>)
    70ec:	f000 fb28 	bl	7740 <PkaCopyDataIntoPkaReg>
    70f0:	2308      	movs	r3, #8
    70f2:	4642      	mov	r2, r8
    70f4:	2101      	movs	r1, #1
    70f6:	201c      	movs	r0, #28
    70f8:	f000 fb22 	bl	7740 <PkaCopyDataIntoPkaReg>
    70fc:	2308      	movs	r3, #8
    70fe:	463a      	mov	r2, r7
    7100:	2101      	movs	r1, #1
    7102:	2003      	movs	r0, #3
    7104:	f000 fb1c 	bl	7740 <PkaCopyDataIntoPkaReg>
    7108:	4622      	mov	r2, r4
    710a:	2308      	movs	r3, #8
    710c:	2101      	movs	r1, #1
    710e:	2002      	movs	r0, #2
    7110:	f000 fb16 	bl	7740 <PkaCopyDataIntoPkaReg>
    7114:	2308      	movs	r3, #8
    7116:	4a25      	ldr	r2, [pc, #148]	; (71ac <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x144>)
    7118:	2101      	movs	r1, #1
    711a:	201a      	movs	r0, #26
    711c:	f000 fb10 	bl	7740 <PkaCopyDataIntoPkaReg>
    7120:	2305      	movs	r3, #5
    7122:	4a23      	ldr	r2, [pc, #140]	; (71b0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x148>)
    7124:	2101      	movs	r1, #1
    7126:	201b      	movs	r0, #27
    7128:	f000 fb0a 	bl	7740 <PkaCopyDataIntoPkaReg>
    712c:	2308      	movs	r3, #8
    712e:	4a21      	ldr	r2, [pc, #132]	; (71b4 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x14c>)
    7130:	2101      	movs	r1, #1
    7132:	2014      	movs	r0, #20
    7134:	f000 fb04 	bl	7740 <PkaCopyDataIntoPkaReg>
    7138:	2308      	movs	r3, #8
    713a:	4a1f      	ldr	r2, [pc, #124]	; (71b8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x150>)
    713c:	2101      	movs	r1, #1
    713e:	2015      	movs	r0, #21
    7140:	f000 fafe 	bl	7740 <PkaCopyDataIntoPkaReg>
    7144:	2308      	movs	r3, #8
    7146:	f105 0264 	add.w	r2, r5, #100	; 0x64
    714a:	2101      	movs	r1, #1
    714c:	2016      	movs	r0, #22
    714e:	f000 faf7 	bl	7740 <PkaCopyDataIntoPkaReg>
    7152:	2308      	movs	r3, #8
    7154:	f105 0284 	add.w	r2, r5, #132	; 0x84
    7158:	2101      	movs	r1, #1
    715a:	2017      	movs	r0, #23
    715c:	f000 faf0 	bl	7740 <PkaCopyDataIntoPkaReg>
    7160:	2308      	movs	r3, #8
    7162:	4a16      	ldr	r2, [pc, #88]	; (71bc <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x154>)
    7164:	2101      	movs	r1, #1
    7166:	200b      	movs	r0, #11
    7168:	f000 faea 	bl	7740 <PkaCopyDataIntoPkaReg>
    716c:	f000 fb44 	bl	77f8 <PkaEcdsaVerify>
    7170:	4604      	mov	r4, r0
    7172:	9801      	ldr	r0, [sp, #4]
    7174:	f000 fad2 	bl	771c <PkaFinishAndMutexUnlock>
    7178:	4b11      	ldr	r3, [pc, #68]	; (71c0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x158>)
    717a:	2c00      	cmp	r4, #0
    717c:	bf18      	it	ne
    717e:	461c      	movne	r4, r3
    7180:	21a4      	movs	r1, #164	; 0xa4
    7182:	4628      	mov	r0, r5
    7184:	f002 fde9 	bl	9d5a <SaSi_PalMemSetZero>
    7188:	4620      	mov	r0, r4
    718a:	b003      	add	sp, #12
    718c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    7190:	4c0c      	ldr	r4, [pc, #48]	; (71c4 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x15c>)
    7192:	e7f9      	b.n	7188 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    7194:	4c0c      	ldr	r4, [pc, #48]	; (71c8 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x160>)
    7196:	e7f7      	b.n	7188 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    7198:	4c0c      	ldr	r4, [pc, #48]	; (71cc <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x164>)
    719a:	e7f5      	b.n	7188 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    719c:	4c08      	ldr	r4, [pc, #32]	; (71c0 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x158>)
    719e:	e7ef      	b.n	7180 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x118>
    71a0:	5002b090 	.word	0x5002b090
    71a4:	0000a520 	.word	0x0000a520
    71a8:	0000a598 	.word	0x0000a598
    71ac:	0000a4e0 	.word	0x0000a4e0
    71b0:	0000a584 	.word	0x0000a584
    71b4:	0000a544 	.word	0x0000a544
    71b8:	0000a564 	.word	0x0000a564
    71bc:	0000a500 	.word	0x0000a500
    71c0:	00f00884 	.word	0x00f00884
    71c4:	00f00876 	.word	0x00f00876
    71c8:	00f00880 	.word	0x00f00880
    71cc:	00f00881 	.word	0x00f00881

000071d0 <set_digest_in_hw_sha256>:
    71d0:	4b0c      	ldr	r3, [pc, #48]	; (7204 <set_digest_in_hw_sha256+0x34>)
    71d2:	69c2      	ldr	r2, [r0, #28]
    71d4:	601a      	str	r2, [r3, #0]
    71d6:	6982      	ldr	r2, [r0, #24]
    71d8:	f843 2c04 	str.w	r2, [r3, #-4]
    71dc:	6942      	ldr	r2, [r0, #20]
    71de:	f843 2c08 	str.w	r2, [r3, #-8]
    71e2:	6902      	ldr	r2, [r0, #16]
    71e4:	f843 2c0c 	str.w	r2, [r3, #-12]
    71e8:	68c2      	ldr	r2, [r0, #12]
    71ea:	f843 2c10 	str.w	r2, [r3, #-16]
    71ee:	6882      	ldr	r2, [r0, #8]
    71f0:	f843 2c14 	str.w	r2, [r3, #-20]
    71f4:	6842      	ldr	r2, [r0, #4]
    71f6:	f843 2c18 	str.w	r2, [r3, #-24]
    71fa:	6802      	ldr	r2, [r0, #0]
    71fc:	f843 2c1c 	str.w	r2, [r3, #-28]
    7200:	4770      	bx	lr
    7202:	bf00      	nop
    7204:	5002b65c 	.word	0x5002b65c

00007208 <read_digest_in_hw_sha256>:
    7208:	4b0c      	ldr	r3, [pc, #48]	; (723c <read_digest_in_hw_sha256+0x34>)
    720a:	681b      	ldr	r3, [r3, #0]
    720c:	61c3      	str	r3, [r0, #28]
    720e:	4b0c      	ldr	r3, [pc, #48]	; (7240 <read_digest_in_hw_sha256+0x38>)
    7210:	681b      	ldr	r3, [r3, #0]
    7212:	6183      	str	r3, [r0, #24]
    7214:	4b0b      	ldr	r3, [pc, #44]	; (7244 <read_digest_in_hw_sha256+0x3c>)
    7216:	681b      	ldr	r3, [r3, #0]
    7218:	6143      	str	r3, [r0, #20]
    721a:	4b0b      	ldr	r3, [pc, #44]	; (7248 <read_digest_in_hw_sha256+0x40>)
    721c:	681b      	ldr	r3, [r3, #0]
    721e:	6103      	str	r3, [r0, #16]
    7220:	4b0a      	ldr	r3, [pc, #40]	; (724c <read_digest_in_hw_sha256+0x44>)
    7222:	681b      	ldr	r3, [r3, #0]
    7224:	60c3      	str	r3, [r0, #12]
    7226:	4b0a      	ldr	r3, [pc, #40]	; (7250 <read_digest_in_hw_sha256+0x48>)
    7228:	681b      	ldr	r3, [r3, #0]
    722a:	6083      	str	r3, [r0, #8]
    722c:	4b09      	ldr	r3, [pc, #36]	; (7254 <read_digest_in_hw_sha256+0x4c>)
    722e:	681b      	ldr	r3, [r3, #0]
    7230:	6043      	str	r3, [r0, #4]
    7232:	4b09      	ldr	r3, [pc, #36]	; (7258 <read_digest_in_hw_sha256+0x50>)
    7234:	681b      	ldr	r3, [r3, #0]
    7236:	6003      	str	r3, [r0, #0]
    7238:	4770      	bx	lr
    723a:	bf00      	nop
    723c:	5002b65c 	.word	0x5002b65c
    7240:	5002b658 	.word	0x5002b658
    7244:	5002b654 	.word	0x5002b654
    7248:	5002b650 	.word	0x5002b650
    724c:	5002b64c 	.word	0x5002b64c
    7250:	5002b648 	.word	0x5002b648
    7254:	5002b644 	.word	0x5002b644
    7258:	5002b640 	.word	0x5002b640

0000725c <verify_context_hash_sha256>:
    725c:	b130      	cbz	r0, 726c <verify_context_hash_sha256+0x10>
    725e:	6802      	ldr	r2, [r0, #0]
    7260:	4b03      	ldr	r3, [pc, #12]	; (7270 <verify_context_hash_sha256+0x14>)
    7262:	4804      	ldr	r0, [pc, #16]	; (7274 <verify_context_hash_sha256+0x18>)
    7264:	429a      	cmp	r2, r3
    7266:	bf08      	it	eq
    7268:	2000      	moveq	r0, #0
    726a:	4770      	bx	lr
    726c:	4802      	ldr	r0, [pc, #8]	; (7278 <verify_context_hash_sha256+0x1c>)
    726e:	4770      	bx	lr
    7270:	bbaa55dd 	.word	0xbbaa55dd
    7274:	00f00202 	.word	0x00f00202
    7278:	00f00200 	.word	0x00f00200

0000727c <nrf_cc310_bl_hash_sha256_init>:
    727c:	b538      	push	{r3, r4, r5, lr}
    727e:	4604      	mov	r4, r0
    7280:	b168      	cbz	r0, 729e <nrf_cc310_bl_hash_sha256_init+0x22>
    7282:	1d05      	adds	r5, r0, #4
    7284:	2170      	movs	r1, #112	; 0x70
    7286:	4628      	mov	r0, r5
    7288:	f002 fd67 	bl	9d5a <SaSi_PalMemSetZero>
    728c:	4628      	mov	r0, r5
    728e:	2220      	movs	r2, #32
    7290:	4904      	ldr	r1, [pc, #16]	; (72a4 <nrf_cc310_bl_hash_sha256_init+0x28>)
    7292:	f002 fd5e 	bl	9d52 <SaSi_PalMemCopy>
    7296:	4b04      	ldr	r3, [pc, #16]	; (72a8 <nrf_cc310_bl_hash_sha256_init+0x2c>)
    7298:	6023      	str	r3, [r4, #0]
    729a:	2000      	movs	r0, #0
    729c:	bd38      	pop	{r3, r4, r5, pc}
    729e:	4803      	ldr	r0, [pc, #12]	; (72ac <nrf_cc310_bl_hash_sha256_init+0x30>)
    72a0:	e7fc      	b.n	729c <nrf_cc310_bl_hash_sha256_init+0x20>
    72a2:	bf00      	nop
    72a4:	0000a5ac 	.word	0x0000a5ac
    72a8:	bbaa55dd 	.word	0xbbaa55dd
    72ac:	00f00200 	.word	0x00f00200

000072b0 <nrf_cc310_bl_hash_sha256_update>:
    72b0:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    72b4:	4b28      	ldr	r3, [pc, #160]	; (7358 <nrf_cc310_bl_hash_sha256_update+0xa8>)
    72b6:	4604      	mov	r4, r0
    72b8:	460e      	mov	r6, r1
    72ba:	4615      	mov	r5, r2
    72bc:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    72be:	b085      	sub	sp, #20
    72c0:	466f      	mov	r7, sp
    72c2:	e887 000f 	stmia.w	r7, {r0, r1, r2, r3}
    72c6:	b92d      	cbnz	r5, 72d4 <nrf_cc310_bl_hash_sha256_update+0x24>
    72c8:	f04f 0900 	mov.w	r9, #0
    72cc:	4648      	mov	r0, r9
    72ce:	b005      	add	sp, #20
    72d0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    72d4:	4620      	mov	r0, r4
    72d6:	f7ff ffc1 	bl	725c <verify_context_hash_sha256>
    72da:	4681      	mov	r9, r0
    72dc:	2800      	cmp	r0, #0
    72de:	d1f5      	bne.n	72cc <nrf_cc310_bl_hash_sha256_update+0x1c>
    72e0:	1d23      	adds	r3, r4, #4
    72e2:	9301      	str	r3, [sp, #4]
    72e4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    72e6:	bba3      	cbnz	r3, 7352 <nrf_cc310_bl_hash_sha256_update+0xa2>
    72e8:	6f23      	ldr	r3, [r4, #112]	; 0x70
    72ea:	b18b      	cbz	r3, 7310 <nrf_cc310_bl_hash_sha256_update+0x60>
    72ec:	f1c3 0840 	rsb	r8, r3, #64	; 0x40
    72f0:	45a8      	cmp	r8, r5
    72f2:	bf28      	it	cs
    72f4:	46a8      	movcs	r8, r5
    72f6:	f104 0030 	add.w	r0, r4, #48	; 0x30
    72fa:	4631      	mov	r1, r6
    72fc:	4418      	add	r0, r3
    72fe:	4642      	mov	r2, r8
    7300:	f002 fd27 	bl	9d52 <SaSi_PalMemCopy>
    7304:	6f23      	ldr	r3, [r4, #112]	; 0x70
    7306:	4443      	add	r3, r8
    7308:	4446      	add	r6, r8
    730a:	6723      	str	r3, [r4, #112]	; 0x70
    730c:	eba5 0508 	sub.w	r5, r5, r8
    7310:	6f22      	ldr	r2, [r4, #112]	; 0x70
    7312:	2a40      	cmp	r2, #64	; 0x40
    7314:	d106      	bne.n	7324 <nrf_cc310_bl_hash_sha256_update+0x74>
    7316:	f104 0130 	add.w	r1, r4, #48	; 0x30
    731a:	4638      	mov	r0, r7
    731c:	f000 fbae 	bl	7a7c <nrf_cc310_bl_hash_update_internal>
    7320:	2300      	movs	r3, #0
    7322:	6723      	str	r3, [r4, #112]	; 0x70
    7324:	f005 083f 	and.w	r8, r5, #63	; 0x3f
    7328:	f035 053f 	bics.w	r5, r5, #63	; 0x3f
    732c:	d005      	beq.n	733a <nrf_cc310_bl_hash_sha256_update+0x8a>
    732e:	4631      	mov	r1, r6
    7330:	462a      	mov	r2, r5
    7332:	4638      	mov	r0, r7
    7334:	f000 fba2 	bl	7a7c <nrf_cc310_bl_hash_update_internal>
    7338:	442e      	add	r6, r5
    733a:	f1b8 0f00 	cmp.w	r8, #0
    733e:	d0c3      	beq.n	72c8 <nrf_cc310_bl_hash_sha256_update+0x18>
    7340:	4642      	mov	r2, r8
    7342:	4631      	mov	r1, r6
    7344:	f104 0030 	add.w	r0, r4, #48	; 0x30
    7348:	f002 fd03 	bl	9d52 <SaSi_PalMemCopy>
    734c:	f8c4 8070 	str.w	r8, [r4, #112]	; 0x70
    7350:	e7bc      	b.n	72cc <nrf_cc310_bl_hash_sha256_update+0x1c>
    7352:	f8df 9008 	ldr.w	r9, [pc, #8]	; 735c <nrf_cc310_bl_hash_sha256_update+0xac>
    7356:	e7b9      	b.n	72cc <nrf_cc310_bl_hash_sha256_update+0x1c>
    7358:	0000a110 	.word	0x0000a110
    735c:	00f0020c 	.word	0x00f0020c

00007360 <nrf_cc310_bl_hash_sha256_finalize>:
    7360:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    7364:	4b14      	ldr	r3, [pc, #80]	; (73b8 <nrf_cc310_bl_hash_sha256_finalize+0x58>)
    7366:	4604      	mov	r4, r0
    7368:	460e      	mov	r6, r1
    736a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    736c:	466f      	mov	r7, sp
    736e:	e887 000f 	stmia.w	r7, {r0, r1, r2, r3}
    7372:	4620      	mov	r0, r4
    7374:	f7ff ff72 	bl	725c <verify_context_hash_sha256>
    7378:	4680      	mov	r8, r0
    737a:	b9b0      	cbnz	r0, 73aa <nrf_cc310_bl_hash_sha256_finalize+0x4a>
    737c:	b1ce      	cbz	r6, 73b2 <nrf_cc310_bl_hash_sha256_finalize+0x52>
    737e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    7380:	1d25      	adds	r5, r4, #4
    7382:	9501      	str	r5, [sp, #4]
    7384:	b93b      	cbnz	r3, 7396 <nrf_cc310_bl_hash_sha256_finalize+0x36>
    7386:	2301      	movs	r3, #1
    7388:	6263      	str	r3, [r4, #36]	; 0x24
    738a:	6f22      	ldr	r2, [r4, #112]	; 0x70
    738c:	f104 0130 	add.w	r1, r4, #48	; 0x30
    7390:	4638      	mov	r0, r7
    7392:	f000 fb73 	bl	7a7c <nrf_cc310_bl_hash_update_internal>
    7396:	462b      	mov	r3, r5
    7398:	3e04      	subs	r6, #4
    739a:	3424      	adds	r4, #36	; 0x24
    739c:	f853 2b04 	ldr.w	r2, [r3], #4
    73a0:	ba12      	rev	r2, r2
    73a2:	42a3      	cmp	r3, r4
    73a4:	f846 2f04 	str.w	r2, [r6, #4]!
    73a8:	d1f8      	bne.n	739c <nrf_cc310_bl_hash_sha256_finalize+0x3c>
    73aa:	4640      	mov	r0, r8
    73ac:	b004      	add	sp, #16
    73ae:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    73b2:	f8df 8008 	ldr.w	r8, [pc, #8]	; 73bc <nrf_cc310_bl_hash_sha256_finalize+0x5c>
    73b6:	e7f8      	b.n	73aa <nrf_cc310_bl_hash_sha256_finalize+0x4a>
    73b8:	0000a110 	.word	0x0000a110
    73bc:	00f00205 	.word	0x00f00205

000073c0 <nrf_cc310_bl_init>:
    73c0:	4b08      	ldr	r3, [pc, #32]	; (73e4 <nrf_cc310_bl_init+0x24>)
    73c2:	681b      	ldr	r3, [r3, #0]
    73c4:	0e1b      	lsrs	r3, r3, #24
    73c6:	2bf0      	cmp	r3, #240	; 0xf0
    73c8:	d108      	bne.n	73dc <nrf_cc310_bl_init+0x1c>
    73ca:	4b07      	ldr	r3, [pc, #28]	; (73e8 <nrf_cc310_bl_init+0x28>)
    73cc:	681a      	ldr	r2, [r3, #0]
    73ce:	4b07      	ldr	r3, [pc, #28]	; (73ec <nrf_cc310_bl_init+0x2c>)
    73d0:	429a      	cmp	r2, r3
    73d2:	d105      	bne.n	73e0 <nrf_cc310_bl_init+0x20>
    73d4:	4b06      	ldr	r3, [pc, #24]	; (73f0 <nrf_cc310_bl_init+0x30>)
    73d6:	2000      	movs	r0, #0
    73d8:	6018      	str	r0, [r3, #0]
    73da:	4770      	bx	lr
    73dc:	2005      	movs	r0, #5
    73de:	4770      	bx	lr
    73e0:	2006      	movs	r0, #6
    73e2:	4770      	bx	lr
    73e4:	5002b928 	.word	0x5002b928
    73e8:	5002ba24 	.word	0x5002ba24
    73ec:	20e00000 	.word	0x20e00000
    73f0:	5002ba0c 	.word	0x5002ba0c

000073f4 <PkaSetRegsMapTab>:
    73f4:	2200      	movs	r2, #0
    73f6:	b530      	push	{r4, r5, lr}
    73f8:	0049      	lsls	r1, r1, #1
    73fa:	4613      	mov	r3, r2
    73fc:	3802      	subs	r0, #2
    73fe:	f640 75fc 	movw	r5, #4092	; 0xffc
    7402:	f102 54a0 	add.w	r4, r2, #335544320	; 0x14000000
    7406:	f504 442c 	add.w	r4, r4, #44032	; 0xac00
    740a:	00a4      	lsls	r4, r4, #2
    740c:	4290      	cmp	r0, r2
    740e:	f102 0201 	add.w	r2, r2, #1
    7412:	bfca      	itet	gt
    7414:	6023      	strgt	r3, [r4, #0]
    7416:	6025      	strle	r5, [r4, #0]
    7418:	185b      	addgt	r3, r3, r1
    741a:	2a1e      	cmp	r2, #30
    741c:	d1f1      	bne.n	7402 <PkaSetRegsMapTab+0xe>
    741e:	4a04      	ldr	r2, [pc, #16]	; (7430 <PkaSetRegsMapTab+0x3c>)
    7420:	6013      	str	r3, [r2, #0]
    7422:	440b      	add	r3, r1
    7424:	6053      	str	r3, [r2, #4]
    7426:	4b03      	ldr	r3, [pc, #12]	; (7434 <PkaSetRegsMapTab+0x40>)
    7428:	4a03      	ldr	r2, [pc, #12]	; (7438 <PkaSetRegsMapTab+0x44>)
    742a:	601a      	str	r2, [r3, #0]
    742c:	bd30      	pop	{r4, r5, pc}
    742e:	bf00      	nop
    7430:	5002b078 	.word	0x5002b078
    7434:	5002b084 	.word	0x5002b084
    7438:	000ff820 	.word	0x000ff820

0000743c <PkaGetRegEffectiveSizeInBits>:
    743c:	b530      	push	{r4, r5, lr}
    743e:	4b1e      	ldr	r3, [pc, #120]	; (74b8 <PkaGetRegEffectiveSizeInBits+0x7c>)
    7440:	b085      	sub	sp, #20
    7442:	461a      	mov	r2, r3
    7444:	6819      	ldr	r1, [r3, #0]
    7446:	9100      	str	r1, [sp, #0]
    7448:	9900      	ldr	r1, [sp, #0]
    744a:	07cc      	lsls	r4, r1, #31
    744c:	d5fa      	bpl.n	7444 <PkaGetRegEffectiveSizeInBits+0x8>
    744e:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    7452:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    7456:	0080      	lsls	r0, r0, #2
    7458:	6801      	ldr	r1, [r0, #0]
    745a:	6813      	ldr	r3, [r2, #0]
    745c:	9301      	str	r3, [sp, #4]
    745e:	9b01      	ldr	r3, [sp, #4]
    7460:	07d8      	lsls	r0, r3, #31
    7462:	d5fa      	bpl.n	745a <PkaGetRegEffectiveSizeInBits+0x1e>
    7464:	4b15      	ldr	r3, [pc, #84]	; (74bc <PkaGetRegEffectiveSizeInBits+0x80>)
    7466:	4c16      	ldr	r4, [pc, #88]	; (74c0 <PkaGetRegEffectiveSizeInBits+0x84>)
    7468:	6818      	ldr	r0, [r3, #0]
    746a:	4d16      	ldr	r5, [pc, #88]	; (74c4 <PkaGetRegEffectiveSizeInBits+0x88>)
    746c:	301f      	adds	r0, #31
    746e:	2320      	movs	r3, #32
    7470:	fb90 f0f3 	sdiv	r0, r0, r3
    7474:	3801      	subs	r0, #1
    7476:	2800      	cmp	r0, #0
    7478:	da10      	bge.n	749c <PkaGetRegEffectiveSizeInBits+0x60>
    747a:	2300      	movs	r3, #0
    747c:	3001      	adds	r0, #1
    747e:	0140      	lsls	r0, r0, #5
    7480:	b153      	cbz	r3, 7498 <PkaGetRegEffectiveSizeInBits+0x5c>
    7482:	f1a0 0120 	sub.w	r1, r0, #32
    7486:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    748a:	4213      	tst	r3, r2
    748c:	d104      	bne.n	7498 <PkaGetRegEffectiveSizeInBits+0x5c>
    748e:	3801      	subs	r0, #1
    7490:	4288      	cmp	r0, r1
    7492:	ea4f 0252 	mov.w	r2, r2, lsr #1
    7496:	d1f8      	bne.n	748a <PkaGetRegEffectiveSizeInBits+0x4e>
    7498:	b005      	add	sp, #20
    749a:	bd30      	pop	{r4, r5, pc}
    749c:	6813      	ldr	r3, [r2, #0]
    749e:	9303      	str	r3, [sp, #12]
    74a0:	9b03      	ldr	r3, [sp, #12]
    74a2:	07db      	lsls	r3, r3, #31
    74a4:	d5fa      	bpl.n	749c <PkaGetRegEffectiveSizeInBits+0x60>
    74a6:	1843      	adds	r3, r0, r1
    74a8:	6023      	str	r3, [r4, #0]
    74aa:	682b      	ldr	r3, [r5, #0]
    74ac:	9302      	str	r3, [sp, #8]
    74ae:	9b02      	ldr	r3, [sp, #8]
    74b0:	2b00      	cmp	r3, #0
    74b2:	d1e3      	bne.n	747c <PkaGetRegEffectiveSizeInBits+0x40>
    74b4:	3801      	subs	r0, #1
    74b6:	e7de      	b.n	7476 <PkaGetRegEffectiveSizeInBits+0x3a>
    74b8:	5002b0b4 	.word	0x5002b0b4
    74bc:	5002b0ac 	.word	0x5002b0ac
    74c0:	5002b0e4 	.word	0x5002b0e4
    74c4:	5002b0dc 	.word	0x5002b0dc

000074c8 <PkaGetNextMsBit>:
    74c8:	b5f0      	push	{r4, r5, r6, r7, lr}
    74ca:	681d      	ldr	r5, [r3, #0]
    74cc:	b085      	sub	sp, #20
    74ce:	f001 041f 	and.w	r4, r1, #31
    74d2:	b90d      	cbnz	r5, 74d8 <PkaGetNextMsBit+0x10>
    74d4:	2c1f      	cmp	r4, #31
    74d6:	d125      	bne.n	7524 <PkaGetNextMsBit+0x5c>
    74d8:	4d15      	ldr	r5, [pc, #84]	; (7530 <PkaGetNextMsBit+0x68>)
    74da:	462e      	mov	r6, r5
    74dc:	682f      	ldr	r7, [r5, #0]
    74de:	9701      	str	r7, [sp, #4]
    74e0:	9f01      	ldr	r7, [sp, #4]
    74e2:	07ff      	lsls	r7, r7, #31
    74e4:	d5fa      	bpl.n	74dc <PkaGetNextMsBit+0x14>
    74e6:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    74ea:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    74ee:	0080      	lsls	r0, r0, #2
    74f0:	6800      	ldr	r0, [r0, #0]
    74f2:	6835      	ldr	r5, [r6, #0]
    74f4:	9503      	str	r5, [sp, #12]
    74f6:	9d03      	ldr	r5, [sp, #12]
    74f8:	07ed      	lsls	r5, r5, #31
    74fa:	d5fa      	bpl.n	74f2 <PkaGetNextMsBit+0x2a>
    74fc:	4d0d      	ldr	r5, [pc, #52]	; (7534 <PkaGetNextMsBit+0x6c>)
    74fe:	eb00 1061 	add.w	r0, r0, r1, asr #5
    7502:	6028      	str	r0, [r5, #0]
    7504:	480c      	ldr	r0, [pc, #48]	; (7538 <PkaGetNextMsBit+0x70>)
    7506:	6800      	ldr	r0, [r0, #0]
    7508:	9002      	str	r0, [sp, #8]
    750a:	2c1f      	cmp	r4, #31
    750c:	bf18      	it	ne
    750e:	43c9      	mvnne	r1, r1
    7510:	9802      	ldr	r0, [sp, #8]
    7512:	bf0f      	iteee	eq
    7514:	6010      	streq	r0, [r2, #0]
    7516:	f001 011f 	andne.w	r1, r1, #31
    751a:	fa00 f101 	lslne.w	r1, r0, r1
    751e:	6011      	strne	r1, [r2, #0]
    7520:	2100      	movs	r1, #0
    7522:	6019      	str	r1, [r3, #0]
    7524:	6810      	ldr	r0, [r2, #0]
    7526:	0043      	lsls	r3, r0, #1
    7528:	0fc0      	lsrs	r0, r0, #31
    752a:	6013      	str	r3, [r2, #0]
    752c:	b005      	add	sp, #20
    752e:	bdf0      	pop	{r4, r5, r6, r7, pc}
    7530:	5002b0b4 	.word	0x5002b0b4
    7534:	5002b0e4 	.word	0x5002b0e4
    7538:	5002b0dc 	.word	0x5002b0dc

0000753c <PkaSetRegsSizesTab>:
    753c:	4b0c      	ldr	r3, [pc, #48]	; (7570 <PkaSetRegsSizesTab+0x34>)
    753e:	6018      	str	r0, [r3, #0]
    7540:	303f      	adds	r0, #63	; 0x3f
    7542:	f020 003f 	bic.w	r0, r0, #63	; 0x3f
    7546:	0189      	lsls	r1, r1, #6
    7548:	3040      	adds	r0, #64	; 0x40
    754a:	6058      	str	r0, [r3, #4]
    754c:	6099      	str	r1, [r3, #8]
    754e:	60d9      	str	r1, [r3, #12]
    7550:	6119      	str	r1, [r3, #16]
    7552:	6159      	str	r1, [r3, #20]
    7554:	6199      	str	r1, [r3, #24]
    7556:	331c      	adds	r3, #28
    7558:	4806      	ldr	r0, [pc, #24]	; (7574 <PkaSetRegsSizesTab+0x38>)
    755a:	6019      	str	r1, [r3, #0]
    755c:	b082      	sub	sp, #8
    755e:	6802      	ldr	r2, [r0, #0]
    7560:	9201      	str	r2, [sp, #4]
    7562:	9a01      	ldr	r2, [sp, #4]
    7564:	07d2      	lsls	r2, r2, #31
    7566:	d5fa      	bpl.n	755e <PkaSetRegsSizesTab+0x22>
    7568:	6019      	str	r1, [r3, #0]
    756a:	b002      	add	sp, #8
    756c:	4770      	bx	lr
    756e:	bf00      	nop
    7570:	5002b090 	.word	0x5002b090
    7574:	5002b0b4 	.word	0x5002b0b4

00007578 <PkaInitPka>:
    7578:	b538      	push	{r3, r4, r5, lr}
    757a:	f1a0 0320 	sub.w	r3, r0, #32
    757e:	f5b3 6f42 	cmp.w	r3, #3104	; 0xc20
    7582:	4605      	mov	r5, r0
    7584:	d82c      	bhi.n	75e0 <PkaInitPka+0x68>
    7586:	288f      	cmp	r0, #143	; 0x8f
    7588:	d826      	bhi.n	75d8 <PkaInitPka+0x60>
    758a:	f100 0347 	add.w	r3, r0, #71	; 0x47
    758e:	f100 0466 	add.w	r4, r0, #102	; 0x66
    7592:	06db      	lsls	r3, r3, #27
    7594:	ea4f 1454 	mov.w	r4, r4, lsr #5
    7598:	d000      	beq.n	759c <PkaInitPka+0x24>
    759a:	3401      	adds	r4, #1
    759c:	0164      	lsls	r4, r4, #5
    759e:	343f      	adds	r4, #63	; 0x3f
    75a0:	09a4      	lsrs	r4, r4, #6
    75a2:	3401      	adds	r4, #1
    75a4:	b111      	cbz	r1, 75ac <PkaInitPka+0x34>
    75a6:	42a1      	cmp	r1, r4
    75a8:	d31a      	bcc.n	75e0 <PkaInitPka+0x68>
    75aa:	460c      	mov	r4, r1
    75ac:	00e3      	lsls	r3, r4, #3
    75ae:	f44f 5080 	mov.w	r0, #4096	; 0x1000
    75b2:	fbb0 f0f3 	udiv	r0, r0, r3
    75b6:	2820      	cmp	r0, #32
    75b8:	bf28      	it	cs
    75ba:	2020      	movcs	r0, #32
    75bc:	b102      	cbz	r2, 75c0 <PkaInitPka+0x48>
    75be:	6010      	str	r0, [r2, #0]
    75c0:	4b08      	ldr	r3, [pc, #32]	; (75e4 <PkaInitPka+0x6c>)
    75c2:	2201      	movs	r2, #1
    75c4:	601a      	str	r2, [r3, #0]
    75c6:	4621      	mov	r1, r4
    75c8:	f7ff ff14 	bl	73f4 <PkaSetRegsMapTab>
    75cc:	4628      	mov	r0, r5
    75ce:	4621      	mov	r1, r4
    75d0:	f7ff ffb4 	bl	753c <PkaSetRegsSizesTab>
    75d4:	2000      	movs	r0, #0
    75d6:	bd38      	pop	{r3, r4, r5, pc}
    75d8:	f100 041f 	add.w	r4, r0, #31
    75dc:	0964      	lsrs	r4, r4, #5
    75de:	e7dd      	b.n	759c <PkaInitPka+0x24>
    75e0:	4801      	ldr	r0, [pc, #4]	; (75e8 <PkaInitPka+0x70>)
    75e2:	e7f8      	b.n	75d6 <PkaInitPka+0x5e>
    75e4:	5002b81c 	.word	0x5002b81c
    75e8:	00f02122 	.word	0x00f02122

000075ec <PkaClearBlockOfRegs>:
    75ec:	b5f0      	push	{r4, r5, r6, r7, lr}
    75ee:	4b45      	ldr	r3, [pc, #276]	; (7704 <PkaClearBlockOfRegs+0x118>)
    75f0:	b089      	sub	sp, #36	; 0x24
    75f2:	461d      	mov	r5, r3
    75f4:	681c      	ldr	r4, [r3, #0]
    75f6:	9401      	str	r4, [sp, #4]
    75f8:	9c01      	ldr	r4, [sp, #4]
    75fa:	07e4      	lsls	r4, r4, #31
    75fc:	d5fa      	bpl.n	75f4 <PkaClearBlockOfRegs+0x8>
    75fe:	4b42      	ldr	r3, [pc, #264]	; (7708 <PkaClearBlockOfRegs+0x11c>)
    7600:	f8df e10c 	ldr.w	lr, [pc, #268]	; 7710 <PkaClearBlockOfRegs+0x124>
    7604:	f8df c10c 	ldr.w	ip, [pc, #268]	; 7714 <PkaClearBlockOfRegs+0x128>
    7608:	4413      	add	r3, r2
    760a:	009b      	lsls	r3, r3, #2
    760c:	2400      	movs	r4, #0
    760e:	681a      	ldr	r2, [r3, #0]
    7610:	180b      	adds	r3, r1, r0
    7612:	2b1e      	cmp	r3, #30
    7614:	bf88      	it	hi
    7616:	f1c0 011e 	rsbhi	r1, r0, #30
    761a:	321f      	adds	r2, #31
    761c:	180b      	adds	r3, r1, r0
    761e:	0952      	lsrs	r2, r2, #5
    7620:	4353      	muls	r3, r2
    7622:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    7626:	bf82      	ittt	hi
    7628:	f44f 6180 	movhi.w	r1, #1024	; 0x400
    762c:	fbb1 f1f2 	udivhi	r1, r1, r2
    7630:	1a09      	subhi	r1, r1, r0
    7632:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    7636:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    763a:	4627      	mov	r7, r4
    763c:	42a1      	cmp	r1, r4
    763e:	dc33      	bgt.n	76a8 <PkaClearBlockOfRegs+0xbc>
    7640:	682b      	ldr	r3, [r5, #0]
    7642:	9304      	str	r3, [sp, #16]
    7644:	9b04      	ldr	r3, [sp, #16]
    7646:	07db      	lsls	r3, r3, #31
    7648:	d5fa      	bpl.n	7640 <PkaClearBlockOfRegs+0x54>
    764a:	4b30      	ldr	r3, [pc, #192]	; (770c <PkaClearBlockOfRegs+0x120>)
    764c:	681b      	ldr	r3, [r3, #0]
    764e:	6829      	ldr	r1, [r5, #0]
    7650:	9105      	str	r1, [sp, #20]
    7652:	9905      	ldr	r1, [sp, #20]
    7654:	07cf      	lsls	r7, r1, #31
    7656:	d5fa      	bpl.n	764e <PkaClearBlockOfRegs+0x62>
    7658:	4c2d      	ldr	r4, [pc, #180]	; (7710 <PkaClearBlockOfRegs+0x124>)
    765a:	492e      	ldr	r1, [pc, #184]	; (7714 <PkaClearBlockOfRegs+0x128>)
    765c:	6023      	str	r3, [r4, #0]
    765e:	2300      	movs	r3, #0
    7660:	461e      	mov	r6, r3
    7662:	4293      	cmp	r3, r2
    7664:	f103 0001 	add.w	r0, r3, #1
    7668:	d140      	bne.n	76ec <PkaClearBlockOfRegs+0x100>
    766a:	f020 0201 	bic.w	r2, r0, #1
    766e:	4829      	ldr	r0, [pc, #164]	; (7714 <PkaClearBlockOfRegs+0x128>)
    7670:	4619      	mov	r1, r3
    7672:	2600      	movs	r6, #0
    7674:	428a      	cmp	r2, r1
    7676:	d83c      	bhi.n	76f2 <PkaClearBlockOfRegs+0x106>
    7678:	6829      	ldr	r1, [r5, #0]
    767a:	9106      	str	r1, [sp, #24]
    767c:	9906      	ldr	r1, [sp, #24]
    767e:	07ce      	lsls	r6, r1, #31
    7680:	d5fa      	bpl.n	7678 <PkaClearBlockOfRegs+0x8c>
    7682:	4925      	ldr	r1, [pc, #148]	; (7718 <PkaClearBlockOfRegs+0x12c>)
    7684:	6809      	ldr	r1, [r1, #0]
    7686:	6828      	ldr	r0, [r5, #0]
    7688:	9007      	str	r0, [sp, #28]
    768a:	9807      	ldr	r0, [sp, #28]
    768c:	07c0      	lsls	r0, r0, #31
    768e:	d5fa      	bpl.n	7686 <PkaClearBlockOfRegs+0x9a>
    7690:	6021      	str	r1, [r4, #0]
    7692:	4820      	ldr	r0, [pc, #128]	; (7714 <PkaClearBlockOfRegs+0x128>)
    7694:	2100      	movs	r1, #0
    7696:	460c      	mov	r4, r1
    7698:	428b      	cmp	r3, r1
    769a:	d12d      	bne.n	76f8 <PkaClearBlockOfRegs+0x10c>
    769c:	491d      	ldr	r1, [pc, #116]	; (7714 <PkaClearBlockOfRegs+0x128>)
    769e:	2000      	movs	r0, #0
    76a0:	429a      	cmp	r2, r3
    76a2:	d82c      	bhi.n	76fe <PkaClearBlockOfRegs+0x112>
    76a4:	b009      	add	sp, #36	; 0x24
    76a6:	bdf0      	pop	{r4, r5, r6, r7, pc}
    76a8:	682b      	ldr	r3, [r5, #0]
    76aa:	9302      	str	r3, [sp, #8]
    76ac:	9b02      	ldr	r3, [sp, #8]
    76ae:	07db      	lsls	r3, r3, #31
    76b0:	d5fa      	bpl.n	76a8 <PkaClearBlockOfRegs+0xbc>
    76b2:	1903      	adds	r3, r0, r4
    76b4:	009b      	lsls	r3, r3, #2
    76b6:	681b      	ldr	r3, [r3, #0]
    76b8:	682e      	ldr	r6, [r5, #0]
    76ba:	9603      	str	r6, [sp, #12]
    76bc:	9e03      	ldr	r6, [sp, #12]
    76be:	07f6      	lsls	r6, r6, #31
    76c0:	d5fa      	bpl.n	76b8 <PkaClearBlockOfRegs+0xcc>
    76c2:	f8ce 3000 	str.w	r3, [lr]
    76c6:	2300      	movs	r3, #0
    76c8:	4293      	cmp	r3, r2
    76ca:	f103 0301 	add.w	r3, r3, #1
    76ce:	d106      	bne.n	76de <PkaClearBlockOfRegs+0xf2>
    76d0:	4616      	mov	r6, r2
    76d2:	f023 0301 	bic.w	r3, r3, #1
    76d6:	42b3      	cmp	r3, r6
    76d8:	d804      	bhi.n	76e4 <PkaClearBlockOfRegs+0xf8>
    76da:	3401      	adds	r4, #1
    76dc:	e7ae      	b.n	763c <PkaClearBlockOfRegs+0x50>
    76de:	f8cc 7000 	str.w	r7, [ip]
    76e2:	e7f1      	b.n	76c8 <PkaClearBlockOfRegs+0xdc>
    76e4:	f8cc 7000 	str.w	r7, [ip]
    76e8:	3601      	adds	r6, #1
    76ea:	e7f4      	b.n	76d6 <PkaClearBlockOfRegs+0xea>
    76ec:	600e      	str	r6, [r1, #0]
    76ee:	4603      	mov	r3, r0
    76f0:	e7b7      	b.n	7662 <PkaClearBlockOfRegs+0x76>
    76f2:	6006      	str	r6, [r0, #0]
    76f4:	3101      	adds	r1, #1
    76f6:	e7bd      	b.n	7674 <PkaClearBlockOfRegs+0x88>
    76f8:	6004      	str	r4, [r0, #0]
    76fa:	3101      	adds	r1, #1
    76fc:	e7cc      	b.n	7698 <PkaClearBlockOfRegs+0xac>
    76fe:	6008      	str	r0, [r1, #0]
    7700:	3301      	adds	r3, #1
    7702:	e7cd      	b.n	76a0 <PkaClearBlockOfRegs+0xb4>
    7704:	5002b0b4 	.word	0x5002b0b4
    7708:	1400ac24 	.word	0x1400ac24
    770c:	5002b07c 	.word	0x5002b07c
    7710:	5002b0d4 	.word	0x5002b0d4
    7714:	5002b0d8 	.word	0x5002b0d8
    7718:	5002b078 	.word	0x5002b078

0000771c <PkaFinishAndMutexUnlock>:
    771c:	b508      	push	{r3, lr}
    771e:	b140      	cbz	r0, 7732 <PkaFinishAndMutexUnlock+0x16>
    7720:	2820      	cmp	r0, #32
    7722:	4601      	mov	r1, r0
    7724:	f04f 0207 	mov.w	r2, #7
    7728:	bf28      	it	cs
    772a:	2120      	movcs	r1, #32
    772c:	2000      	movs	r0, #0
    772e:	f7ff ff5d 	bl	75ec <PkaClearBlockOfRegs>
    7732:	4b02      	ldr	r3, [pc, #8]	; (773c <PkaFinishAndMutexUnlock+0x20>)
    7734:	2200      	movs	r2, #0
    7736:	601a      	str	r2, [r3, #0]
    7738:	bd08      	pop	{r3, pc}
    773a:	bf00      	nop
    773c:	5002b81c 	.word	0x5002b81c

00007740 <PkaCopyDataIntoPkaReg>:
    7740:	b5f0      	push	{r4, r5, r6, r7, lr}
    7742:	4d29      	ldr	r5, [pc, #164]	; (77e8 <PkaCopyDataIntoPkaReg+0xa8>)
    7744:	b085      	sub	sp, #20
    7746:	462c      	mov	r4, r5
    7748:	682e      	ldr	r6, [r5, #0]
    774a:	9600      	str	r6, [sp, #0]
    774c:	9e00      	ldr	r6, [sp, #0]
    774e:	07f6      	lsls	r6, r6, #31
    7750:	d5fa      	bpl.n	7748 <PkaCopyDataIntoPkaReg+0x8>
    7752:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    7756:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    775a:	0080      	lsls	r0, r0, #2
    775c:	6805      	ldr	r5, [r0, #0]
    775e:	6820      	ldr	r0, [r4, #0]
    7760:	9001      	str	r0, [sp, #4]
    7762:	9801      	ldr	r0, [sp, #4]
    7764:	07c7      	lsls	r7, r0, #31
    7766:	d5fa      	bpl.n	775e <PkaCopyDataIntoPkaReg+0x1e>
    7768:	4820      	ldr	r0, [pc, #128]	; (77ec <PkaCopyDataIntoPkaReg+0xac>)
    776a:	4f21      	ldr	r7, [pc, #132]	; (77f0 <PkaCopyDataIntoPkaReg+0xb0>)
    776c:	6005      	str	r5, [r0, #0]
    776e:	eb02 0683 	add.w	r6, r2, r3, lsl #2
    7772:	42b2      	cmp	r2, r6
    7774:	d129      	bne.n	77ca <PkaCopyDataIntoPkaReg+0x8a>
    7776:	1c5a      	adds	r2, r3, #1
    7778:	4e1d      	ldr	r6, [pc, #116]	; (77f0 <PkaCopyDataIntoPkaReg+0xb0>)
    777a:	f022 0201 	bic.w	r2, r2, #1
    777e:	2700      	movs	r7, #0
    7780:	429a      	cmp	r2, r3
    7782:	d827      	bhi.n	77d4 <PkaCopyDataIntoPkaReg+0x94>
    7784:	6823      	ldr	r3, [r4, #0]
    7786:	9302      	str	r3, [sp, #8]
    7788:	9b02      	ldr	r3, [sp, #8]
    778a:	07de      	lsls	r6, r3, #31
    778c:	d5fa      	bpl.n	7784 <PkaCopyDataIntoPkaReg+0x44>
    778e:	4b19      	ldr	r3, [pc, #100]	; (77f4 <PkaCopyDataIntoPkaReg+0xb4>)
    7790:	440b      	add	r3, r1
    7792:	009b      	lsls	r3, r3, #2
    7794:	681b      	ldr	r3, [r3, #0]
    7796:	331f      	adds	r3, #31
    7798:	095b      	lsrs	r3, r3, #5
    779a:	429a      	cmp	r2, r3
    779c:	d213      	bcs.n	77c6 <PkaCopyDataIntoPkaReg+0x86>
    779e:	6821      	ldr	r1, [r4, #0]
    77a0:	9103      	str	r1, [sp, #12]
    77a2:	9903      	ldr	r1, [sp, #12]
    77a4:	07c9      	lsls	r1, r1, #31
    77a6:	d5fa      	bpl.n	779e <PkaCopyDataIntoPkaReg+0x5e>
    77a8:	4415      	add	r5, r2
    77aa:	2100      	movs	r1, #0
    77ac:	1a9b      	subs	r3, r3, r2
    77ae:	4a10      	ldr	r2, [pc, #64]	; (77f0 <PkaCopyDataIntoPkaReg+0xb0>)
    77b0:	6005      	str	r5, [r0, #0]
    77b2:	4608      	mov	r0, r1
    77b4:	428b      	cmp	r3, r1
    77b6:	d810      	bhi.n	77da <PkaCopyDataIntoPkaReg+0x9a>
    77b8:	1c5a      	adds	r2, r3, #1
    77ba:	490d      	ldr	r1, [pc, #52]	; (77f0 <PkaCopyDataIntoPkaReg+0xb0>)
    77bc:	f022 0201 	bic.w	r2, r2, #1
    77c0:	2000      	movs	r0, #0
    77c2:	429a      	cmp	r2, r3
    77c4:	d80c      	bhi.n	77e0 <PkaCopyDataIntoPkaReg+0xa0>
    77c6:	b005      	add	sp, #20
    77c8:	bdf0      	pop	{r4, r5, r6, r7, pc}
    77ca:	f852 cb04 	ldr.w	ip, [r2], #4
    77ce:	f8c7 c000 	str.w	ip, [r7]
    77d2:	e7ce      	b.n	7772 <PkaCopyDataIntoPkaReg+0x32>
    77d4:	6037      	str	r7, [r6, #0]
    77d6:	3301      	adds	r3, #1
    77d8:	e7d2      	b.n	7780 <PkaCopyDataIntoPkaReg+0x40>
    77da:	6010      	str	r0, [r2, #0]
    77dc:	3101      	adds	r1, #1
    77de:	e7e9      	b.n	77b4 <PkaCopyDataIntoPkaReg+0x74>
    77e0:	6008      	str	r0, [r1, #0]
    77e2:	3301      	adds	r3, #1
    77e4:	e7ed      	b.n	77c2 <PkaCopyDataIntoPkaReg+0x82>
    77e6:	bf00      	nop
    77e8:	5002b0b4 	.word	0x5002b0b4
    77ec:	5002b0d4 	.word	0x5002b0d4
    77f0:	5002b0d8 	.word	0x5002b0d8
    77f4:	1400ac24 	.word	0x1400ac24

000077f8 <PkaEcdsaVerify>:
    77f8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    77fc:	4b81      	ldr	r3, [pc, #516]	; (7a04 <PkaEcdsaVerify+0x20c>)
    77fe:	681d      	ldr	r5, [r3, #0]
    7800:	6898      	ldr	r0, [r3, #8]
    7802:	3320      	adds	r3, #32
    7804:	b0a0      	sub	sp, #128	; 0x80
    7806:	461e      	mov	r6, r3
    7808:	681a      	ldr	r2, [r3, #0]
    780a:	9201      	str	r2, [sp, #4]
    780c:	9a01      	ldr	r2, [sp, #4]
    780e:	07d7      	lsls	r7, r2, #31
    7810:	d5fa      	bpl.n	7808 <PkaEcdsaVerify+0x10>
    7812:	4b7d      	ldr	r3, [pc, #500]	; (7a08 <PkaEcdsaVerify+0x210>)
    7814:	4a7d      	ldr	r2, [pc, #500]	; (7a0c <PkaEcdsaVerify+0x214>)
    7816:	601a      	str	r2, [r3, #0]
    7818:	6832      	ldr	r2, [r6, #0]
    781a:	9202      	str	r2, [sp, #8]
    781c:	9a02      	ldr	r2, [sp, #8]
    781e:	07d4      	lsls	r4, r2, #31
    7820:	d5fa      	bpl.n	7818 <PkaEcdsaVerify+0x20>
    7822:	4a7b      	ldr	r2, [pc, #492]	; (7a10 <PkaEcdsaVerify+0x218>)
    7824:	601a      	str	r2, [r3, #0]
    7826:	4a7b      	ldr	r2, [pc, #492]	; (7a14 <PkaEcdsaVerify+0x21c>)
    7828:	4614      	mov	r4, r2
    782a:	6811      	ldr	r1, [r2, #0]
    782c:	9103      	str	r1, [sp, #12]
    782e:	9903      	ldr	r1, [sp, #12]
    7830:	07c9      	lsls	r1, r1, #31
    7832:	d5fa      	bpl.n	782a <PkaEcdsaVerify+0x32>
    7834:	4a78      	ldr	r2, [pc, #480]	; (7a18 <PkaEcdsaVerify+0x220>)
    7836:	6811      	ldr	r1, [r2, #0]
    7838:	f3c1 2140 	ubfx	r1, r1, #9, #1
    783c:	6837      	ldr	r7, [r6, #0]
    783e:	9704      	str	r7, [sp, #16]
    7840:	9f04      	ldr	r7, [sp, #16]
    7842:	07ff      	lsls	r7, r7, #31
    7844:	d5fa      	bpl.n	783c <PkaEcdsaVerify+0x44>
    7846:	4f75      	ldr	r7, [pc, #468]	; (7a1c <PkaEcdsaVerify+0x224>)
    7848:	601f      	str	r7, [r3, #0]
    784a:	6827      	ldr	r7, [r4, #0]
    784c:	9705      	str	r7, [sp, #20]
    784e:	9f05      	ldr	r7, [sp, #20]
    7850:	07ff      	lsls	r7, r7, #31
    7852:	d5fa      	bpl.n	784a <PkaEcdsaVerify+0x52>
    7854:	6817      	ldr	r7, [r2, #0]
    7856:	2900      	cmp	r1, #0
    7858:	f000 80cf 	beq.w	79fa <PkaEcdsaVerify+0x202>
    785c:	05b9      	lsls	r1, r7, #22
    785e:	f140 80cc 	bpl.w	79fa <PkaEcdsaVerify+0x202>
    7862:	6831      	ldr	r1, [r6, #0]
    7864:	9106      	str	r1, [sp, #24]
    7866:	9906      	ldr	r1, [sp, #24]
    7868:	07cf      	lsls	r7, r1, #31
    786a:	d5fa      	bpl.n	7862 <PkaEcdsaVerify+0x6a>
    786c:	496c      	ldr	r1, [pc, #432]	; (7a20 <PkaEcdsaVerify+0x228>)
    786e:	6019      	str	r1, [r3, #0]
    7870:	6821      	ldr	r1, [r4, #0]
    7872:	9107      	str	r1, [sp, #28]
    7874:	9907      	ldr	r1, [sp, #28]
    7876:	07c9      	lsls	r1, r1, #31
    7878:	d5fa      	bpl.n	7870 <PkaEcdsaVerify+0x78>
    787a:	6811      	ldr	r1, [r2, #0]
    787c:	f3c1 2140 	ubfx	r1, r1, #9, #1
    7880:	6837      	ldr	r7, [r6, #0]
    7882:	9708      	str	r7, [sp, #32]
    7884:	9f08      	ldr	r7, [sp, #32]
    7886:	07ff      	lsls	r7, r7, #31
    7888:	d5fa      	bpl.n	7880 <PkaEcdsaVerify+0x88>
    788a:	4f66      	ldr	r7, [pc, #408]	; (7a24 <PkaEcdsaVerify+0x22c>)
    788c:	601f      	str	r7, [r3, #0]
    788e:	6827      	ldr	r7, [r4, #0]
    7890:	9709      	str	r7, [sp, #36]	; 0x24
    7892:	9f09      	ldr	r7, [sp, #36]	; 0x24
    7894:	07ff      	lsls	r7, r7, #31
    7896:	d5fa      	bpl.n	788e <PkaEcdsaVerify+0x96>
    7898:	6812      	ldr	r2, [r2, #0]
    789a:	2900      	cmp	r1, #0
    789c:	f000 80af 	beq.w	79fe <PkaEcdsaVerify+0x206>
    78a0:	0591      	lsls	r1, r2, #22
    78a2:	f140 80ac 	bpl.w	79fe <PkaEcdsaVerify+0x206>
    78a6:	6832      	ldr	r2, [r6, #0]
    78a8:	920a      	str	r2, [sp, #40]	; 0x28
    78aa:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    78ac:	07d2      	lsls	r2, r2, #31
    78ae:	d5fa      	bpl.n	78a6 <PkaEcdsaVerify+0xae>
    78b0:	4a56      	ldr	r2, [pc, #344]	; (7a0c <PkaEcdsaVerify+0x214>)
    78b2:	601a      	str	r2, [r3, #0]
    78b4:	6832      	ldr	r2, [r6, #0]
    78b6:	920b      	str	r2, [sp, #44]	; 0x2c
    78b8:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    78ba:	07d7      	lsls	r7, r2, #31
    78bc:	d5fa      	bpl.n	78b4 <PkaEcdsaVerify+0xbc>
    78be:	4a5a      	ldr	r2, [pc, #360]	; (7a28 <PkaEcdsaVerify+0x230>)
    78c0:	601a      	str	r2, [r3, #0]
    78c2:	6831      	ldr	r1, [r6, #0]
    78c4:	910c      	str	r1, [sp, #48]	; 0x30
    78c6:	990c      	ldr	r1, [sp, #48]	; 0x30
    78c8:	07cc      	lsls	r4, r1, #31
    78ca:	d5fa      	bpl.n	78c2 <PkaEcdsaVerify+0xca>
    78cc:	4957      	ldr	r1, [pc, #348]	; (7a2c <PkaEcdsaVerify+0x234>)
    78ce:	6019      	str	r1, [r3, #0]
    78d0:	6831      	ldr	r1, [r6, #0]
    78d2:	910d      	str	r1, [sp, #52]	; 0x34
    78d4:	990d      	ldr	r1, [sp, #52]	; 0x34
    78d6:	07c9      	lsls	r1, r1, #31
    78d8:	d5fa      	bpl.n	78d0 <PkaEcdsaVerify+0xd8>
    78da:	4955      	ldr	r1, [pc, #340]	; (7a30 <PkaEcdsaVerify+0x238>)
    78dc:	6019      	str	r1, [r3, #0]
    78de:	6831      	ldr	r1, [r6, #0]
    78e0:	910e      	str	r1, [sp, #56]	; 0x38
    78e2:	990e      	ldr	r1, [sp, #56]	; 0x38
    78e4:	07cf      	lsls	r7, r1, #31
    78e6:	d5fa      	bpl.n	78de <PkaEcdsaVerify+0xe6>
    78e8:	4952      	ldr	r1, [pc, #328]	; (7a34 <PkaEcdsaVerify+0x23c>)
    78ea:	6019      	str	r1, [r3, #0]
    78ec:	6831      	ldr	r1, [r6, #0]
    78ee:	910f      	str	r1, [sp, #60]	; 0x3c
    78f0:	990f      	ldr	r1, [sp, #60]	; 0x3c
    78f2:	07cc      	lsls	r4, r1, #31
    78f4:	d5fa      	bpl.n	78ec <PkaEcdsaVerify+0xf4>
    78f6:	4950      	ldr	r1, [pc, #320]	; (7a38 <PkaEcdsaVerify+0x240>)
    78f8:	6019      	str	r1, [r3, #0]
    78fa:	4b50      	ldr	r3, [pc, #320]	; (7a3c <PkaEcdsaVerify+0x244>)
    78fc:	461e      	mov	r6, r3
    78fe:	6819      	ldr	r1, [r3, #0]
    7900:	9110      	str	r1, [sp, #64]	; 0x40
    7902:	9910      	ldr	r1, [sp, #64]	; 0x40
    7904:	07c9      	lsls	r1, r1, #31
    7906:	d5fa      	bpl.n	78fe <PkaEcdsaVerify+0x106>
    7908:	4c3f      	ldr	r4, [pc, #252]	; (7a08 <PkaEcdsaVerify+0x210>)
    790a:	4b4d      	ldr	r3, [pc, #308]	; (7a40 <PkaEcdsaVerify+0x248>)
    790c:	6023      	str	r3, [r4, #0]
    790e:	6833      	ldr	r3, [r6, #0]
    7910:	9311      	str	r3, [sp, #68]	; 0x44
    7912:	9b11      	ldr	r3, [sp, #68]	; 0x44
    7914:	07db      	lsls	r3, r3, #31
    7916:	d5fa      	bpl.n	790e <PkaEcdsaVerify+0x116>
    7918:	4b4a      	ldr	r3, [pc, #296]	; (7a44 <PkaEcdsaVerify+0x24c>)
    791a:	6023      	str	r3, [r4, #0]
    791c:	6833      	ldr	r3, [r6, #0]
    791e:	9312      	str	r3, [sp, #72]	; 0x48
    7920:	9b12      	ldr	r3, [sp, #72]	; 0x48
    7922:	07df      	lsls	r7, r3, #31
    7924:	d5fa      	bpl.n	791c <PkaEcdsaVerify+0x124>
    7926:	4b48      	ldr	r3, [pc, #288]	; (7a48 <PkaEcdsaVerify+0x250>)
    7928:	6023      	str	r3, [r4, #0]
    792a:	4b3a      	ldr	r3, [pc, #232]	; (7a14 <PkaEcdsaVerify+0x21c>)
    792c:	4698      	mov	r8, r3
    792e:	6819      	ldr	r1, [r3, #0]
    7930:	9113      	str	r1, [sp, #76]	; 0x4c
    7932:	9913      	ldr	r1, [sp, #76]	; 0x4c
    7934:	07c9      	lsls	r1, r1, #31
    7936:	d5fa      	bpl.n	792e <PkaEcdsaVerify+0x136>
    7938:	4f32      	ldr	r7, [pc, #200]	; (7a04 <PkaEcdsaVerify+0x20c>)
    793a:	6038      	str	r0, [r7, #0]
    793c:	6833      	ldr	r3, [r6, #0]
    793e:	9314      	str	r3, [sp, #80]	; 0x50
    7940:	9b14      	ldr	r3, [sp, #80]	; 0x50
    7942:	07db      	lsls	r3, r3, #31
    7944:	d5fa      	bpl.n	793c <PkaEcdsaVerify+0x144>
    7946:	6022      	str	r2, [r4, #0]
    7948:	6833      	ldr	r3, [r6, #0]
    794a:	9315      	str	r3, [sp, #84]	; 0x54
    794c:	9b15      	ldr	r3, [sp, #84]	; 0x54
    794e:	07d8      	lsls	r0, r3, #31
    7950:	d5fa      	bpl.n	7948 <PkaEcdsaVerify+0x150>
    7952:	4b3e      	ldr	r3, [pc, #248]	; (7a4c <PkaEcdsaVerify+0x254>)
    7954:	6023      	str	r3, [r4, #0]
    7956:	6833      	ldr	r3, [r6, #0]
    7958:	9316      	str	r3, [sp, #88]	; 0x58
    795a:	9b16      	ldr	r3, [sp, #88]	; 0x58
    795c:	07d9      	lsls	r1, r3, #31
    795e:	d5fa      	bpl.n	7956 <PkaEcdsaVerify+0x15e>
    7960:	4b3b      	ldr	r3, [pc, #236]	; (7a50 <PkaEcdsaVerify+0x258>)
    7962:	6023      	str	r3, [r4, #0]
    7964:	6833      	ldr	r3, [r6, #0]
    7966:	9317      	str	r3, [sp, #92]	; 0x5c
    7968:	9b17      	ldr	r3, [sp, #92]	; 0x5c
    796a:	07da      	lsls	r2, r3, #31
    796c:	d5fa      	bpl.n	7964 <PkaEcdsaVerify+0x16c>
    796e:	4b39      	ldr	r3, [pc, #228]	; (7a54 <PkaEcdsaVerify+0x25c>)
    7970:	6023      	str	r3, [r4, #0]
    7972:	6833      	ldr	r3, [r6, #0]
    7974:	9318      	str	r3, [sp, #96]	; 0x60
    7976:	9b18      	ldr	r3, [sp, #96]	; 0x60
    7978:	07db      	lsls	r3, r3, #31
    797a:	d5fa      	bpl.n	7972 <PkaEcdsaVerify+0x17a>
    797c:	4b36      	ldr	r3, [pc, #216]	; (7a58 <PkaEcdsaVerify+0x260>)
    797e:	6023      	str	r3, [r4, #0]
    7980:	6833      	ldr	r3, [r6, #0]
    7982:	9319      	str	r3, [sp, #100]	; 0x64
    7984:	9b19      	ldr	r3, [sp, #100]	; 0x64
    7986:	07d8      	lsls	r0, r3, #31
    7988:	d5fa      	bpl.n	7980 <PkaEcdsaVerify+0x188>
    798a:	4b34      	ldr	r3, [pc, #208]	; (7a5c <PkaEcdsaVerify+0x264>)
    798c:	6023      	str	r3, [r4, #0]
    798e:	6833      	ldr	r3, [r6, #0]
    7990:	931a      	str	r3, [sp, #104]	; 0x68
    7992:	9b1a      	ldr	r3, [sp, #104]	; 0x68
    7994:	07d9      	lsls	r1, r3, #31
    7996:	d5fa      	bpl.n	798e <PkaEcdsaVerify+0x196>
    7998:	4b31      	ldr	r3, [pc, #196]	; (7a60 <PkaEcdsaVerify+0x268>)
    799a:	6023      	str	r3, [r4, #0]
    799c:	6833      	ldr	r3, [r6, #0]
    799e:	931b      	str	r3, [sp, #108]	; 0x6c
    79a0:	9b1b      	ldr	r3, [sp, #108]	; 0x6c
    79a2:	07da      	lsls	r2, r3, #31
    79a4:	d5fa      	bpl.n	799c <PkaEcdsaVerify+0x1a4>
    79a6:	4b2f      	ldr	r3, [pc, #188]	; (7a64 <PkaEcdsaVerify+0x26c>)
    79a8:	6023      	str	r3, [r4, #0]
    79aa:	f000 fc1d 	bl	81e8 <PkaSum2ScalarMullt>
    79ae:	bb08      	cbnz	r0, 79f4 <PkaEcdsaVerify+0x1fc>
    79b0:	f8d8 3000 	ldr.w	r3, [r8]
    79b4:	931c      	str	r3, [sp, #112]	; 0x70
    79b6:	9b1c      	ldr	r3, [sp, #112]	; 0x70
    79b8:	07db      	lsls	r3, r3, #31
    79ba:	d5f9      	bpl.n	79b0 <PkaEcdsaVerify+0x1b8>
    79bc:	603d      	str	r5, [r7, #0]
    79be:	6833      	ldr	r3, [r6, #0]
    79c0:	931d      	str	r3, [sp, #116]	; 0x74
    79c2:	9b1d      	ldr	r3, [sp, #116]	; 0x74
    79c4:	07d9      	lsls	r1, r3, #31
    79c6:	d5fa      	bpl.n	79be <PkaEcdsaVerify+0x1c6>
    79c8:	4b27      	ldr	r3, [pc, #156]	; (7a68 <PkaEcdsaVerify+0x270>)
    79ca:	6023      	str	r3, [r4, #0]
    79cc:	6833      	ldr	r3, [r6, #0]
    79ce:	931e      	str	r3, [sp, #120]	; 0x78
    79d0:	9b1e      	ldr	r3, [sp, #120]	; 0x78
    79d2:	07da      	lsls	r2, r3, #31
    79d4:	d5fa      	bpl.n	79cc <PkaEcdsaVerify+0x1d4>
    79d6:	4b25      	ldr	r3, [pc, #148]	; (7a6c <PkaEcdsaVerify+0x274>)
    79d8:	6023      	str	r3, [r4, #0]
    79da:	f8d8 3000 	ldr.w	r3, [r8]
    79de:	931f      	str	r3, [sp, #124]	; 0x7c
    79e0:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
    79e2:	07db      	lsls	r3, r3, #31
    79e4:	d5f9      	bpl.n	79da <PkaEcdsaVerify+0x1e2>
    79e6:	4b0c      	ldr	r3, [pc, #48]	; (7a18 <PkaEcdsaVerify+0x220>)
    79e8:	681b      	ldr	r3, [r3, #0]
    79ea:	f413 5f80 	tst.w	r3, #4096	; 0x1000
    79ee:	4b20      	ldr	r3, [pc, #128]	; (7a70 <PkaEcdsaVerify+0x278>)
    79f0:	bf08      	it	eq
    79f2:	4618      	moveq	r0, r3
    79f4:	b020      	add	sp, #128	; 0x80
    79f6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    79fa:	481e      	ldr	r0, [pc, #120]	; (7a74 <PkaEcdsaVerify+0x27c>)
    79fc:	e7fa      	b.n	79f4 <PkaEcdsaVerify+0x1fc>
    79fe:	481e      	ldr	r0, [pc, #120]	; (7a78 <PkaEcdsaVerify+0x280>)
    7a00:	e7f8      	b.n	79f4 <PkaEcdsaVerify+0x1fc>
    7a02:	bf00      	nop
    7a04:	5002b090 	.word	0x5002b090
    7a08:	5002b080 	.word	0x5002b080
    7a0c:	51021000 	.word	0x51021000
    7a10:	29721fc0 	.word	0x29721fc0
    7a14:	5002b0b4 	.word	0x5002b0b4
    7a18:	5002b088 	.word	0x5002b088
    7a1c:	2901cfc0 	.word	0x2901cfc0
    7a20:	290e1fc0 	.word	0x290e1fc0
    7a24:	29003fc0 	.word	0x29003fc0
    7a28:	49020140 	.word	0x49020140
    7a2c:	a8843100 	.word	0xa8843100
    7a30:	49160000 	.word	0x49160000
    7a34:	a1080140 	.word	0xa1080140
    7a38:	88084480 	.word	0x88084480
    7a3c:	5002b0b0 	.word	0x5002b0b0
    7a40:	887044c0 	.word	0x887044c0
    7a44:	417a0780 	.word	0x417a0780
    7a48:	417e07c0 	.word	0x417e07c0
    7a4c:	496a0000 	.word	0x496a0000
    7a50:	49160680 	.word	0x49160680
    7a54:	496e0040 	.word	0x496e0040
    7a58:	21000200 	.word	0x21000200
    7a5c:	21208200 	.word	0x21208200
    7a60:	21208240 	.word	0x21208240
    7a64:	21248280 	.word	0x21248280
    7a68:	a161a140 	.word	0xa161a140
    7a6c:	5161c800 	.word	0x5161c800
    7a70:	00f10803 	.word	0x00f10803
    7a74:	00f10801 	.word	0x00f10801
    7a78:	00f10802 	.word	0x00f10802

00007a7c <nrf_cc310_bl_hash_update_internal>:
    7a7c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    7a80:	4b31      	ldr	r3, [pc, #196]	; (7b48 <nrf_cc310_bl_hash_update_internal+0xcc>)
    7a82:	6844      	ldr	r4, [r0, #4]
    7a84:	4680      	mov	r8, r0
    7a86:	4692      	mov	sl, r2
    7a88:	4699      	mov	r9, r3
    7a8a:	681a      	ldr	r2, [r3, #0]
    7a8c:	2a00      	cmp	r2, #0
    7a8e:	d1fc      	bne.n	7a8a <nrf_cc310_bl_hash_update_internal+0xe>
    7a90:	4b2e      	ldr	r3, [pc, #184]	; (7b4c <nrf_cc310_bl_hash_update_internal+0xd0>)
    7a92:	469b      	mov	fp, r3
    7a94:	681a      	ldr	r2, [r3, #0]
    7a96:	2a00      	cmp	r2, #0
    7a98:	d1fc      	bne.n	7a94 <nrf_cc310_bl_hash_update_internal+0x18>
    7a9a:	f04f 30ff 	mov.w	r0, #4294967295
    7a9e:	9101      	str	r1, [sp, #4]
    7aa0:	f000 fc94 	bl	83cc <SaSi_HalClearInterruptBit>
    7aa4:	2080      	movs	r0, #128	; 0x80
    7aa6:	f000 fc97 	bl	83d8 <SaSi_HalMaskInterrupt>
    7aaa:	4d29      	ldr	r5, [pc, #164]	; (7b50 <nrf_cc310_bl_hash_update_internal+0xd4>)
    7aac:	4a29      	ldr	r2, [pc, #164]	; (7b54 <nrf_cc310_bl_hash_update_internal+0xd8>)
    7aae:	4f2a      	ldr	r7, [pc, #168]	; (7b58 <nrf_cc310_bl_hash_update_internal+0xdc>)
    7ab0:	4e2a      	ldr	r6, [pc, #168]	; (7b5c <nrf_cc310_bl_hash_update_internal+0xe0>)
    7ab2:	2301      	movs	r3, #1
    7ab4:	2007      	movs	r0, #7
    7ab6:	602b      	str	r3, [r5, #0]
    7ab8:	f5a2 729e 	sub.w	r2, r2, #316	; 0x13c
    7abc:	f8c2 013c 	str.w	r0, [r2, #316]	; 0x13c
    7ac0:	6013      	str	r3, [r2, #0]
    7ac2:	6a63      	ldr	r3, [r4, #36]	; 0x24
    7ac4:	603b      	str	r3, [r7, #0]
    7ac6:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    7ac8:	6033      	str	r3, [r6, #0]
    7aca:	f8d8 3000 	ldr.w	r3, [r8]
    7ace:	f842 3c04 	str.w	r3, [r2, #-4]
    7ad2:	f8d8 3008 	ldr.w	r3, [r8, #8]
    7ad6:	4620      	mov	r0, r4
    7ad8:	4798      	blx	r3
    7ada:	9901      	ldr	r1, [sp, #4]
    7adc:	f8d9 3000 	ldr.w	r3, [r9]
    7ae0:	2b00      	cmp	r3, #0
    7ae2:	d1fb      	bne.n	7adc <nrf_cc310_bl_hash_update_internal+0x60>
    7ae4:	f1ba 0f00 	cmp.w	sl, #0
    7ae8:	d120      	bne.n	7b2c <nrf_cc310_bl_hash_update_internal+0xb0>
    7aea:	4b1d      	ldr	r3, [pc, #116]	; (7b60 <nrf_cc310_bl_hash_update_internal+0xe4>)
    7aec:	2204      	movs	r2, #4
    7aee:	601a      	str	r2, [r3, #0]
    7af0:	f8d9 3000 	ldr.w	r3, [r9]
    7af4:	2b00      	cmp	r3, #0
    7af6:	d1fb      	bne.n	7af0 <nrf_cc310_bl_hash_update_internal+0x74>
    7af8:	f8db a000 	ldr.w	sl, [fp]
    7afc:	f1ba 0f00 	cmp.w	sl, #0
    7b00:	d1fa      	bne.n	7af8 <nrf_cc310_bl_hash_update_internal+0x7c>
    7b02:	f8d8 300c 	ldr.w	r3, [r8, #12]
    7b06:	4620      	mov	r0, r4
    7b08:	4798      	blx	r3
    7b0a:	683b      	ldr	r3, [r7, #0]
    7b0c:	6263      	str	r3, [r4, #36]	; 0x24
    7b0e:	6833      	ldr	r3, [r6, #0]
    7b10:	62a3      	str	r3, [r4, #40]	; 0x28
    7b12:	4b14      	ldr	r3, [pc, #80]	; (7b64 <nrf_cc310_bl_hash_update_internal+0xe8>)
    7b14:	f8c3 a000 	str.w	sl, [r3]
    7b18:	f8c3 a144 	str.w	sl, [r3, #324]	; 0x144
    7b1c:	f8d9 3000 	ldr.w	r3, [r9]
    7b20:	2b00      	cmp	r3, #0
    7b22:	d1fb      	bne.n	7b1c <nrf_cc310_bl_hash_update_internal+0xa0>
    7b24:	602b      	str	r3, [r5, #0]
    7b26:	b003      	add	sp, #12
    7b28:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    7b2c:	6a23      	ldr	r3, [r4, #32]
    7b2e:	2b01      	cmp	r3, #1
    7b30:	bf04      	itt	eq
    7b32:	4a0c      	ldreq	r2, [pc, #48]	; (7b64 <nrf_cc310_bl_hash_update_internal+0xe8>)
    7b34:	6013      	streq	r3, [r2, #0]
    7b36:	4b0c      	ldr	r3, [pc, #48]	; (7b68 <nrf_cc310_bl_hash_update_internal+0xec>)
    7b38:	2040      	movs	r0, #64	; 0x40
    7b3a:	6019      	str	r1, [r3, #0]
    7b3c:	f8c3 a004 	str.w	sl, [r3, #4]
    7b40:	f000 fc50 	bl	83e4 <SaSi_HalWaitInterrupt>
    7b44:	e7d4      	b.n	7af0 <nrf_cc310_bl_hash_update_internal+0x74>
    7b46:	bf00      	nop
    7b48:	5002b910 	.word	0x5002b910
    7b4c:	5002bc20 	.word	0x5002bc20
    7b50:	5002b818 	.word	0x5002b818
    7b54:	5002b900 	.word	0x5002b900
    7b58:	5002b7cc 	.word	0x5002b7cc
    7b5c:	5002b7d0 	.word	0x5002b7d0
    7b60:	5002b7c8 	.word	0x5002b7c8
    7b64:	5002b684 	.word	0x5002b684
    7b68:	5002bc28 	.word	0x5002bc28

00007b6c <PkaDoubleMdf2Mdf>:
    7b6c:	b510      	push	{r4, lr}
    7b6e:	4b54      	ldr	r3, [pc, #336]	; (7cc0 <PkaDoubleMdf2Mdf+0x154>)
    7b70:	b098      	sub	sp, #96	; 0x60
    7b72:	4619      	mov	r1, r3
    7b74:	681a      	ldr	r2, [r3, #0]
    7b76:	9201      	str	r2, [sp, #4]
    7b78:	9a01      	ldr	r2, [sp, #4]
    7b7a:	07d2      	lsls	r2, r2, #31
    7b7c:	d5fa      	bpl.n	7b74 <PkaDoubleMdf2Mdf+0x8>
    7b7e:	4b51      	ldr	r3, [pc, #324]	; (7cc4 <PkaDoubleMdf2Mdf+0x158>)
    7b80:	4a51      	ldr	r2, [pc, #324]	; (7cc8 <PkaDoubleMdf2Mdf+0x15c>)
    7b82:	601a      	str	r2, [r3, #0]
    7b84:	680a      	ldr	r2, [r1, #0]
    7b86:	9202      	str	r2, [sp, #8]
    7b88:	9a02      	ldr	r2, [sp, #8]
    7b8a:	07d4      	lsls	r4, r2, #31
    7b8c:	d5fa      	bpl.n	7b84 <PkaDoubleMdf2Mdf+0x18>
    7b8e:	4a4f      	ldr	r2, [pc, #316]	; (7ccc <PkaDoubleMdf2Mdf+0x160>)
    7b90:	601a      	str	r2, [r3, #0]
    7b92:	680a      	ldr	r2, [r1, #0]
    7b94:	9203      	str	r2, [sp, #12]
    7b96:	9a03      	ldr	r2, [sp, #12]
    7b98:	07d0      	lsls	r0, r2, #31
    7b9a:	d5fa      	bpl.n	7b92 <PkaDoubleMdf2Mdf+0x26>
    7b9c:	484c      	ldr	r0, [pc, #304]	; (7cd0 <PkaDoubleMdf2Mdf+0x164>)
    7b9e:	6018      	str	r0, [r3, #0]
    7ba0:	680a      	ldr	r2, [r1, #0]
    7ba2:	9204      	str	r2, [sp, #16]
    7ba4:	9a04      	ldr	r2, [sp, #16]
    7ba6:	07d2      	lsls	r2, r2, #31
    7ba8:	d5fa      	bpl.n	7ba0 <PkaDoubleMdf2Mdf+0x34>
    7baa:	4a4a      	ldr	r2, [pc, #296]	; (7cd4 <PkaDoubleMdf2Mdf+0x168>)
    7bac:	601a      	str	r2, [r3, #0]
    7bae:	680a      	ldr	r2, [r1, #0]
    7bb0:	9205      	str	r2, [sp, #20]
    7bb2:	9a05      	ldr	r2, [sp, #20]
    7bb4:	07d4      	lsls	r4, r2, #31
    7bb6:	d5fa      	bpl.n	7bae <PkaDoubleMdf2Mdf+0x42>
    7bb8:	4a47      	ldr	r2, [pc, #284]	; (7cd8 <PkaDoubleMdf2Mdf+0x16c>)
    7bba:	601a      	str	r2, [r3, #0]
    7bbc:	680a      	ldr	r2, [r1, #0]
    7bbe:	9206      	str	r2, [sp, #24]
    7bc0:	9a06      	ldr	r2, [sp, #24]
    7bc2:	07d2      	lsls	r2, r2, #31
    7bc4:	d5fa      	bpl.n	7bbc <PkaDoubleMdf2Mdf+0x50>
    7bc6:	4a45      	ldr	r2, [pc, #276]	; (7cdc <PkaDoubleMdf2Mdf+0x170>)
    7bc8:	601a      	str	r2, [r3, #0]
    7bca:	680a      	ldr	r2, [r1, #0]
    7bcc:	9207      	str	r2, [sp, #28]
    7bce:	9a07      	ldr	r2, [sp, #28]
    7bd0:	07d4      	lsls	r4, r2, #31
    7bd2:	d5fa      	bpl.n	7bca <PkaDoubleMdf2Mdf+0x5e>
    7bd4:	4a42      	ldr	r2, [pc, #264]	; (7ce0 <PkaDoubleMdf2Mdf+0x174>)
    7bd6:	601a      	str	r2, [r3, #0]
    7bd8:	680a      	ldr	r2, [r1, #0]
    7bda:	9208      	str	r2, [sp, #32]
    7bdc:	9a08      	ldr	r2, [sp, #32]
    7bde:	07d2      	lsls	r2, r2, #31
    7be0:	d5fa      	bpl.n	7bd8 <PkaDoubleMdf2Mdf+0x6c>
    7be2:	4a40      	ldr	r2, [pc, #256]	; (7ce4 <PkaDoubleMdf2Mdf+0x178>)
    7be4:	601a      	str	r2, [r3, #0]
    7be6:	680a      	ldr	r2, [r1, #0]
    7be8:	9209      	str	r2, [sp, #36]	; 0x24
    7bea:	9a09      	ldr	r2, [sp, #36]	; 0x24
    7bec:	07d4      	lsls	r4, r2, #31
    7bee:	d5fa      	bpl.n	7be6 <PkaDoubleMdf2Mdf+0x7a>
    7bf0:	4a3d      	ldr	r2, [pc, #244]	; (7ce8 <PkaDoubleMdf2Mdf+0x17c>)
    7bf2:	601a      	str	r2, [r3, #0]
    7bf4:	680a      	ldr	r2, [r1, #0]
    7bf6:	920a      	str	r2, [sp, #40]	; 0x28
    7bf8:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    7bfa:	07d2      	lsls	r2, r2, #31
    7bfc:	d5fa      	bpl.n	7bf4 <PkaDoubleMdf2Mdf+0x88>
    7bfe:	4a3b      	ldr	r2, [pc, #236]	; (7cec <PkaDoubleMdf2Mdf+0x180>)
    7c00:	601a      	str	r2, [r3, #0]
    7c02:	680a      	ldr	r2, [r1, #0]
    7c04:	920b      	str	r2, [sp, #44]	; 0x2c
    7c06:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    7c08:	07d4      	lsls	r4, r2, #31
    7c0a:	d5fa      	bpl.n	7c02 <PkaDoubleMdf2Mdf+0x96>
    7c0c:	4a38      	ldr	r2, [pc, #224]	; (7cf0 <PkaDoubleMdf2Mdf+0x184>)
    7c0e:	601a      	str	r2, [r3, #0]
    7c10:	680a      	ldr	r2, [r1, #0]
    7c12:	920c      	str	r2, [sp, #48]	; 0x30
    7c14:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    7c16:	07d2      	lsls	r2, r2, #31
    7c18:	d5fa      	bpl.n	7c10 <PkaDoubleMdf2Mdf+0xa4>
    7c1a:	4a36      	ldr	r2, [pc, #216]	; (7cf4 <PkaDoubleMdf2Mdf+0x188>)
    7c1c:	601a      	str	r2, [r3, #0]
    7c1e:	680a      	ldr	r2, [r1, #0]
    7c20:	920d      	str	r2, [sp, #52]	; 0x34
    7c22:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    7c24:	07d4      	lsls	r4, r2, #31
    7c26:	d5fa      	bpl.n	7c1e <PkaDoubleMdf2Mdf+0xb2>
    7c28:	4a33      	ldr	r2, [pc, #204]	; (7cf8 <PkaDoubleMdf2Mdf+0x18c>)
    7c2a:	601a      	str	r2, [r3, #0]
    7c2c:	680a      	ldr	r2, [r1, #0]
    7c2e:	920e      	str	r2, [sp, #56]	; 0x38
    7c30:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    7c32:	07d2      	lsls	r2, r2, #31
    7c34:	d5fa      	bpl.n	7c2c <PkaDoubleMdf2Mdf+0xc0>
    7c36:	4a31      	ldr	r2, [pc, #196]	; (7cfc <PkaDoubleMdf2Mdf+0x190>)
    7c38:	601a      	str	r2, [r3, #0]
    7c3a:	680a      	ldr	r2, [r1, #0]
    7c3c:	920f      	str	r2, [sp, #60]	; 0x3c
    7c3e:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    7c40:	07d4      	lsls	r4, r2, #31
    7c42:	d5fa      	bpl.n	7c3a <PkaDoubleMdf2Mdf+0xce>
    7c44:	4a2e      	ldr	r2, [pc, #184]	; (7d00 <PkaDoubleMdf2Mdf+0x194>)
    7c46:	601a      	str	r2, [r3, #0]
    7c48:	680a      	ldr	r2, [r1, #0]
    7c4a:	9210      	str	r2, [sp, #64]	; 0x40
    7c4c:	9a10      	ldr	r2, [sp, #64]	; 0x40
    7c4e:	07d2      	lsls	r2, r2, #31
    7c50:	d5fa      	bpl.n	7c48 <PkaDoubleMdf2Mdf+0xdc>
    7c52:	4a2c      	ldr	r2, [pc, #176]	; (7d04 <PkaDoubleMdf2Mdf+0x198>)
    7c54:	601a      	str	r2, [r3, #0]
    7c56:	4b1a      	ldr	r3, [pc, #104]	; (7cc0 <PkaDoubleMdf2Mdf+0x154>)
    7c58:	4619      	mov	r1, r3
    7c5a:	681c      	ldr	r4, [r3, #0]
    7c5c:	9411      	str	r4, [sp, #68]	; 0x44
    7c5e:	9c11      	ldr	r4, [sp, #68]	; 0x44
    7c60:	07e4      	lsls	r4, r4, #31
    7c62:	d5fa      	bpl.n	7c5a <PkaDoubleMdf2Mdf+0xee>
    7c64:	4b17      	ldr	r3, [pc, #92]	; (7cc4 <PkaDoubleMdf2Mdf+0x158>)
    7c66:	6018      	str	r0, [r3, #0]
    7c68:	6808      	ldr	r0, [r1, #0]
    7c6a:	9012      	str	r0, [sp, #72]	; 0x48
    7c6c:	9812      	ldr	r0, [sp, #72]	; 0x48
    7c6e:	07c4      	lsls	r4, r0, #31
    7c70:	d5fa      	bpl.n	7c68 <PkaDoubleMdf2Mdf+0xfc>
    7c72:	601a      	str	r2, [r3, #0]
    7c74:	680a      	ldr	r2, [r1, #0]
    7c76:	9213      	str	r2, [sp, #76]	; 0x4c
    7c78:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    7c7a:	07d0      	lsls	r0, r2, #31
    7c7c:	d5fa      	bpl.n	7c74 <PkaDoubleMdf2Mdf+0x108>
    7c7e:	4a12      	ldr	r2, [pc, #72]	; (7cc8 <PkaDoubleMdf2Mdf+0x15c>)
    7c80:	601a      	str	r2, [r3, #0]
    7c82:	680a      	ldr	r2, [r1, #0]
    7c84:	9214      	str	r2, [sp, #80]	; 0x50
    7c86:	9a14      	ldr	r2, [sp, #80]	; 0x50
    7c88:	07d2      	lsls	r2, r2, #31
    7c8a:	d5fa      	bpl.n	7c82 <PkaDoubleMdf2Mdf+0x116>
    7c8c:	4a1e      	ldr	r2, [pc, #120]	; (7d08 <PkaDoubleMdf2Mdf+0x19c>)
    7c8e:	601a      	str	r2, [r3, #0]
    7c90:	680a      	ldr	r2, [r1, #0]
    7c92:	9215      	str	r2, [sp, #84]	; 0x54
    7c94:	9a15      	ldr	r2, [sp, #84]	; 0x54
    7c96:	07d4      	lsls	r4, r2, #31
    7c98:	d5fa      	bpl.n	7c90 <PkaDoubleMdf2Mdf+0x124>
    7c9a:	4a1c      	ldr	r2, [pc, #112]	; (7d0c <PkaDoubleMdf2Mdf+0x1a0>)
    7c9c:	601a      	str	r2, [r3, #0]
    7c9e:	680a      	ldr	r2, [r1, #0]
    7ca0:	9216      	str	r2, [sp, #88]	; 0x58
    7ca2:	9a16      	ldr	r2, [sp, #88]	; 0x58
    7ca4:	07d0      	lsls	r0, r2, #31
    7ca6:	d5fa      	bpl.n	7c9e <PkaDoubleMdf2Mdf+0x132>
    7ca8:	4a19      	ldr	r2, [pc, #100]	; (7d10 <PkaDoubleMdf2Mdf+0x1a4>)
    7caa:	601a      	str	r2, [r3, #0]
    7cac:	680a      	ldr	r2, [r1, #0]
    7cae:	9217      	str	r2, [sp, #92]	; 0x5c
    7cb0:	9a17      	ldr	r2, [sp, #92]	; 0x5c
    7cb2:	07d2      	lsls	r2, r2, #31
    7cb4:	d5fa      	bpl.n	7cac <PkaDoubleMdf2Mdf+0x140>
    7cb6:	4a17      	ldr	r2, [pc, #92]	; (7d14 <PkaDoubleMdf2Mdf+0x1a8>)
    7cb8:	601a      	str	r2, [r3, #0]
    7cba:	b018      	add	sp, #96	; 0x60
    7cbc:	bd10      	pop	{r4, pc}
    7cbe:	bf00      	nop
    7cc0:	5002b0b0 	.word	0x5002b0b0
    7cc4:	5002b080 	.word	0x5002b080
    7cc8:	21659300 	.word	0x21659300
    7ccc:	90310400 	.word	0x90310400
    7cd0:	90659640 	.word	0x90659640
    7cd4:	21618300 	.word	0x21618300
    7cd8:	2130c300 	.word	0x2130c300
    7cdc:	9064c300 	.word	0x9064c300
    7ce0:	90618100 	.word	0x90618100
    7ce4:	21104600 	.word	0x21104600
    7ce8:	21118100 	.word	0x21118100
    7cec:	21444100 	.word	0x21444100
    7cf0:	2920c300 	.word	0x2920c300
    7cf4:	c810460c 	.word	0xc810460c
    7cf8:	21318600 	.word	0x21318600
    7cfc:	2160c300 	.word	0x2160c300
    7d00:	2928c140 	.word	0x2928c140
    7d04:	21659640 	.word	0x21659640
    7d08:	90311300 	.word	0x90311300
    7d0c:	29259640 	.word	0x29259640
    7d10:	c8144659 	.word	0xc8144659
    7d14:	49320440 	.word	0x49320440

00007d18 <PkaDoubleMdf2Jcb>:
    7d18:	b510      	push	{r4, lr}
    7d1a:	4b49      	ldr	r3, [pc, #292]	; (7e40 <PkaDoubleMdf2Jcb+0x128>)
    7d1c:	b094      	sub	sp, #80	; 0x50
    7d1e:	4619      	mov	r1, r3
    7d20:	681a      	ldr	r2, [r3, #0]
    7d22:	9200      	str	r2, [sp, #0]
    7d24:	9a00      	ldr	r2, [sp, #0]
    7d26:	07d2      	lsls	r2, r2, #31
    7d28:	d5fa      	bpl.n	7d20 <PkaDoubleMdf2Jcb+0x8>
    7d2a:	4b46      	ldr	r3, [pc, #280]	; (7e44 <PkaDoubleMdf2Jcb+0x12c>)
    7d2c:	4a46      	ldr	r2, [pc, #280]	; (7e48 <PkaDoubleMdf2Jcb+0x130>)
    7d2e:	601a      	str	r2, [r3, #0]
    7d30:	680a      	ldr	r2, [r1, #0]
    7d32:	9201      	str	r2, [sp, #4]
    7d34:	9a01      	ldr	r2, [sp, #4]
    7d36:	07d4      	lsls	r4, r2, #31
    7d38:	d5fa      	bpl.n	7d30 <PkaDoubleMdf2Jcb+0x18>
    7d3a:	4a44      	ldr	r2, [pc, #272]	; (7e4c <PkaDoubleMdf2Jcb+0x134>)
    7d3c:	601a      	str	r2, [r3, #0]
    7d3e:	680a      	ldr	r2, [r1, #0]
    7d40:	9202      	str	r2, [sp, #8]
    7d42:	9a02      	ldr	r2, [sp, #8]
    7d44:	07d0      	lsls	r0, r2, #31
    7d46:	d5fa      	bpl.n	7d3e <PkaDoubleMdf2Jcb+0x26>
    7d48:	4841      	ldr	r0, [pc, #260]	; (7e50 <PkaDoubleMdf2Jcb+0x138>)
    7d4a:	6018      	str	r0, [r3, #0]
    7d4c:	680a      	ldr	r2, [r1, #0]
    7d4e:	9203      	str	r2, [sp, #12]
    7d50:	9a03      	ldr	r2, [sp, #12]
    7d52:	07d2      	lsls	r2, r2, #31
    7d54:	d5fa      	bpl.n	7d4c <PkaDoubleMdf2Jcb+0x34>
    7d56:	4a3f      	ldr	r2, [pc, #252]	; (7e54 <PkaDoubleMdf2Jcb+0x13c>)
    7d58:	601a      	str	r2, [r3, #0]
    7d5a:	680a      	ldr	r2, [r1, #0]
    7d5c:	9204      	str	r2, [sp, #16]
    7d5e:	9a04      	ldr	r2, [sp, #16]
    7d60:	07d4      	lsls	r4, r2, #31
    7d62:	d5fa      	bpl.n	7d5a <PkaDoubleMdf2Jcb+0x42>
    7d64:	4a3c      	ldr	r2, [pc, #240]	; (7e58 <PkaDoubleMdf2Jcb+0x140>)
    7d66:	601a      	str	r2, [r3, #0]
    7d68:	680a      	ldr	r2, [r1, #0]
    7d6a:	9205      	str	r2, [sp, #20]
    7d6c:	9a05      	ldr	r2, [sp, #20]
    7d6e:	07d2      	lsls	r2, r2, #31
    7d70:	d5fa      	bpl.n	7d68 <PkaDoubleMdf2Jcb+0x50>
    7d72:	4a3a      	ldr	r2, [pc, #232]	; (7e5c <PkaDoubleMdf2Jcb+0x144>)
    7d74:	601a      	str	r2, [r3, #0]
    7d76:	680a      	ldr	r2, [r1, #0]
    7d78:	9206      	str	r2, [sp, #24]
    7d7a:	9a06      	ldr	r2, [sp, #24]
    7d7c:	07d4      	lsls	r4, r2, #31
    7d7e:	d5fa      	bpl.n	7d76 <PkaDoubleMdf2Jcb+0x5e>
    7d80:	4a37      	ldr	r2, [pc, #220]	; (7e60 <PkaDoubleMdf2Jcb+0x148>)
    7d82:	601a      	str	r2, [r3, #0]
    7d84:	680a      	ldr	r2, [r1, #0]
    7d86:	9207      	str	r2, [sp, #28]
    7d88:	9a07      	ldr	r2, [sp, #28]
    7d8a:	07d2      	lsls	r2, r2, #31
    7d8c:	d5fa      	bpl.n	7d84 <PkaDoubleMdf2Jcb+0x6c>
    7d8e:	4a35      	ldr	r2, [pc, #212]	; (7e64 <PkaDoubleMdf2Jcb+0x14c>)
    7d90:	601a      	str	r2, [r3, #0]
    7d92:	680a      	ldr	r2, [r1, #0]
    7d94:	9208      	str	r2, [sp, #32]
    7d96:	9a08      	ldr	r2, [sp, #32]
    7d98:	07d4      	lsls	r4, r2, #31
    7d9a:	d5fa      	bpl.n	7d92 <PkaDoubleMdf2Jcb+0x7a>
    7d9c:	4a32      	ldr	r2, [pc, #200]	; (7e68 <PkaDoubleMdf2Jcb+0x150>)
    7d9e:	601a      	str	r2, [r3, #0]
    7da0:	680a      	ldr	r2, [r1, #0]
    7da2:	9209      	str	r2, [sp, #36]	; 0x24
    7da4:	9a09      	ldr	r2, [sp, #36]	; 0x24
    7da6:	07d2      	lsls	r2, r2, #31
    7da8:	d5fa      	bpl.n	7da0 <PkaDoubleMdf2Jcb+0x88>
    7daa:	4a30      	ldr	r2, [pc, #192]	; (7e6c <PkaDoubleMdf2Jcb+0x154>)
    7dac:	601a      	str	r2, [r3, #0]
    7dae:	680a      	ldr	r2, [r1, #0]
    7db0:	920a      	str	r2, [sp, #40]	; 0x28
    7db2:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    7db4:	07d4      	lsls	r4, r2, #31
    7db6:	d5fa      	bpl.n	7dae <PkaDoubleMdf2Jcb+0x96>
    7db8:	4a2d      	ldr	r2, [pc, #180]	; (7e70 <PkaDoubleMdf2Jcb+0x158>)
    7dba:	601a      	str	r2, [r3, #0]
    7dbc:	680a      	ldr	r2, [r1, #0]
    7dbe:	920b      	str	r2, [sp, #44]	; 0x2c
    7dc0:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    7dc2:	07d2      	lsls	r2, r2, #31
    7dc4:	d5fa      	bpl.n	7dbc <PkaDoubleMdf2Jcb+0xa4>
    7dc6:	4a2b      	ldr	r2, [pc, #172]	; (7e74 <PkaDoubleMdf2Jcb+0x15c>)
    7dc8:	601a      	str	r2, [r3, #0]
    7dca:	680a      	ldr	r2, [r1, #0]
    7dcc:	920c      	str	r2, [sp, #48]	; 0x30
    7dce:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    7dd0:	07d4      	lsls	r4, r2, #31
    7dd2:	d5fa      	bpl.n	7dca <PkaDoubleMdf2Jcb+0xb2>
    7dd4:	4a28      	ldr	r2, [pc, #160]	; (7e78 <PkaDoubleMdf2Jcb+0x160>)
    7dd6:	601a      	str	r2, [r3, #0]
    7dd8:	680a      	ldr	r2, [r1, #0]
    7dda:	920d      	str	r2, [sp, #52]	; 0x34
    7ddc:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    7dde:	07d2      	lsls	r2, r2, #31
    7de0:	d5fa      	bpl.n	7dd8 <PkaDoubleMdf2Jcb+0xc0>
    7de2:	4a26      	ldr	r2, [pc, #152]	; (7e7c <PkaDoubleMdf2Jcb+0x164>)
    7de4:	601a      	str	r2, [r3, #0]
    7de6:	680a      	ldr	r2, [r1, #0]
    7de8:	920e      	str	r2, [sp, #56]	; 0x38
    7dea:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    7dec:	07d4      	lsls	r4, r2, #31
    7dee:	d5fa      	bpl.n	7de6 <PkaDoubleMdf2Jcb+0xce>
    7df0:	4a23      	ldr	r2, [pc, #140]	; (7e80 <PkaDoubleMdf2Jcb+0x168>)
    7df2:	601a      	str	r2, [r3, #0]
    7df4:	680a      	ldr	r2, [r1, #0]
    7df6:	920f      	str	r2, [sp, #60]	; 0x3c
    7df8:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    7dfa:	07d2      	lsls	r2, r2, #31
    7dfc:	d5fa      	bpl.n	7df4 <PkaDoubleMdf2Jcb+0xdc>
    7dfe:	4a21      	ldr	r2, [pc, #132]	; (7e84 <PkaDoubleMdf2Jcb+0x16c>)
    7e00:	601a      	str	r2, [r3, #0]
    7e02:	4b0f      	ldr	r3, [pc, #60]	; (7e40 <PkaDoubleMdf2Jcb+0x128>)
    7e04:	4619      	mov	r1, r3
    7e06:	681c      	ldr	r4, [r3, #0]
    7e08:	9410      	str	r4, [sp, #64]	; 0x40
    7e0a:	9c10      	ldr	r4, [sp, #64]	; 0x40
    7e0c:	07e4      	lsls	r4, r4, #31
    7e0e:	d5fa      	bpl.n	7e06 <PkaDoubleMdf2Jcb+0xee>
    7e10:	4b0c      	ldr	r3, [pc, #48]	; (7e44 <PkaDoubleMdf2Jcb+0x12c>)
    7e12:	6018      	str	r0, [r3, #0]
    7e14:	6808      	ldr	r0, [r1, #0]
    7e16:	9011      	str	r0, [sp, #68]	; 0x44
    7e18:	9811      	ldr	r0, [sp, #68]	; 0x44
    7e1a:	07c4      	lsls	r4, r0, #31
    7e1c:	d5fa      	bpl.n	7e14 <PkaDoubleMdf2Jcb+0xfc>
    7e1e:	601a      	str	r2, [r3, #0]
    7e20:	680a      	ldr	r2, [r1, #0]
    7e22:	9212      	str	r2, [sp, #72]	; 0x48
    7e24:	9a12      	ldr	r2, [sp, #72]	; 0x48
    7e26:	07d0      	lsls	r0, r2, #31
    7e28:	d5fa      	bpl.n	7e20 <PkaDoubleMdf2Jcb+0x108>
    7e2a:	4a17      	ldr	r2, [pc, #92]	; (7e88 <PkaDoubleMdf2Jcb+0x170>)
    7e2c:	601a      	str	r2, [r3, #0]
    7e2e:	680a      	ldr	r2, [r1, #0]
    7e30:	9213      	str	r2, [sp, #76]	; 0x4c
    7e32:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    7e34:	07d2      	lsls	r2, r2, #31
    7e36:	d5fa      	bpl.n	7e2e <PkaDoubleMdf2Jcb+0x116>
    7e38:	4a14      	ldr	r2, [pc, #80]	; (7e8c <PkaDoubleMdf2Jcb+0x174>)
    7e3a:	601a      	str	r2, [r3, #0]
    7e3c:	b014      	add	sp, #80	; 0x50
    7e3e:	bd10      	pop	{r4, pc}
    7e40:	5002b0b0 	.word	0x5002b0b0
    7e44:	5002b080 	.word	0x5002b080
    7e48:	21659080 	.word	0x21659080
    7e4c:	90090400 	.word	0x90090400
    7e50:	90659640 	.word	0x90659640
    7e54:	21618080 	.word	0x21618080
    7e58:	21082080 	.word	0x21082080
    7e5c:	90642080 	.word	0x90642080
    7e60:	90618100 	.word	0x90618100
    7e64:	21104600 	.word	0x21104600
    7e68:	21118100 	.word	0x21118100
    7e6c:	21444100 	.word	0x21444100
    7e70:	29202080 	.word	0x29202080
    7e74:	c8104602 	.word	0xc8104602
    7e78:	21098600 	.word	0x21098600
    7e7c:	21602080 	.word	0x21602080
    7e80:	29282140 	.word	0x29282140
    7e84:	21659640 	.word	0x21659640
    7e88:	29259640 	.word	0x29259640
    7e8c:	c8144659 	.word	0xc8144659

00007e90 <PkaAddJcbAfn2Mdf>:
    7e90:	b510      	push	{r4, lr}
    7e92:	4b50      	ldr	r3, [pc, #320]	; (7fd4 <PkaAddJcbAfn2Mdf+0x144>)
    7e94:	b096      	sub	sp, #88	; 0x58
    7e96:	461c      	mov	r4, r3
    7e98:	681a      	ldr	r2, [r3, #0]
    7e9a:	9201      	str	r2, [sp, #4]
    7e9c:	9a01      	ldr	r2, [sp, #4]
    7e9e:	07d2      	lsls	r2, r2, #31
    7ea0:	d5fa      	bpl.n	7e98 <PkaAddJcbAfn2Mdf+0x8>
    7ea2:	4b4d      	ldr	r3, [pc, #308]	; (7fd8 <PkaAddJcbAfn2Mdf+0x148>)
    7ea4:	4a4d      	ldr	r2, [pc, #308]	; (7fdc <PkaAddJcbAfn2Mdf+0x14c>)
    7ea6:	601a      	str	r2, [r3, #0]
    7ea8:	6822      	ldr	r2, [r4, #0]
    7eaa:	9202      	str	r2, [sp, #8]
    7eac:	9a02      	ldr	r2, [sp, #8]
    7eae:	07d2      	lsls	r2, r2, #31
    7eb0:	d5fa      	bpl.n	7ea8 <PkaAddJcbAfn2Mdf+0x18>
    7eb2:	4a4b      	ldr	r2, [pc, #300]	; (7fe0 <PkaAddJcbAfn2Mdf+0x150>)
    7eb4:	601a      	str	r2, [r3, #0]
    7eb6:	4a4b      	ldr	r2, [pc, #300]	; (7fe4 <PkaAddJcbAfn2Mdf+0x154>)
    7eb8:	ea42 4080 	orr.w	r0, r2, r0, lsl #18
    7ebc:	6822      	ldr	r2, [r4, #0]
    7ebe:	9203      	str	r2, [sp, #12]
    7ec0:	9a03      	ldr	r2, [sp, #12]
    7ec2:	07d2      	lsls	r2, r2, #31
    7ec4:	d5fa      	bpl.n	7ebc <PkaAddJcbAfn2Mdf+0x2c>
    7ec6:	6018      	str	r0, [r3, #0]
    7ec8:	6822      	ldr	r2, [r4, #0]
    7eca:	9204      	str	r2, [sp, #16]
    7ecc:	9a04      	ldr	r2, [sp, #16]
    7ece:	07d0      	lsls	r0, r2, #31
    7ed0:	d5fa      	bpl.n	7ec8 <PkaAddJcbAfn2Mdf+0x38>
    7ed2:	4a45      	ldr	r2, [pc, #276]	; (7fe8 <PkaAddJcbAfn2Mdf+0x158>)
    7ed4:	601a      	str	r2, [r3, #0]
    7ed6:	f5a2 0280 	sub.w	r2, r2, #4194304	; 0x400000
    7eda:	ea42 4181 	orr.w	r1, r2, r1, lsl #18
    7ede:	6822      	ldr	r2, [r4, #0]
    7ee0:	9205      	str	r2, [sp, #20]
    7ee2:	9a05      	ldr	r2, [sp, #20]
    7ee4:	07d2      	lsls	r2, r2, #31
    7ee6:	d5fa      	bpl.n	7ede <PkaAddJcbAfn2Mdf+0x4e>
    7ee8:	6019      	str	r1, [r3, #0]
    7eea:	6822      	ldr	r2, [r4, #0]
    7eec:	9206      	str	r2, [sp, #24]
    7eee:	9a06      	ldr	r2, [sp, #24]
    7ef0:	07d0      	lsls	r0, r2, #31
    7ef2:	d5fa      	bpl.n	7eea <PkaAddJcbAfn2Mdf+0x5a>
    7ef4:	4a3d      	ldr	r2, [pc, #244]	; (7fec <PkaAddJcbAfn2Mdf+0x15c>)
    7ef6:	601a      	str	r2, [r3, #0]
    7ef8:	6822      	ldr	r2, [r4, #0]
    7efa:	9207      	str	r2, [sp, #28]
    7efc:	9a07      	ldr	r2, [sp, #28]
    7efe:	07d1      	lsls	r1, r2, #31
    7f00:	d5fa      	bpl.n	7ef8 <PkaAddJcbAfn2Mdf+0x68>
    7f02:	4a3b      	ldr	r2, [pc, #236]	; (7ff0 <PkaAddJcbAfn2Mdf+0x160>)
    7f04:	601a      	str	r2, [r3, #0]
    7f06:	6822      	ldr	r2, [r4, #0]
    7f08:	9208      	str	r2, [sp, #32]
    7f0a:	9a08      	ldr	r2, [sp, #32]
    7f0c:	07d2      	lsls	r2, r2, #31
    7f0e:	d5fa      	bpl.n	7f06 <PkaAddJcbAfn2Mdf+0x76>
    7f10:	4a38      	ldr	r2, [pc, #224]	; (7ff4 <PkaAddJcbAfn2Mdf+0x164>)
    7f12:	601a      	str	r2, [r3, #0]
    7f14:	6822      	ldr	r2, [r4, #0]
    7f16:	9209      	str	r2, [sp, #36]	; 0x24
    7f18:	9a09      	ldr	r2, [sp, #36]	; 0x24
    7f1a:	07d0      	lsls	r0, r2, #31
    7f1c:	d5fa      	bpl.n	7f14 <PkaAddJcbAfn2Mdf+0x84>
    7f1e:	4a36      	ldr	r2, [pc, #216]	; (7ff8 <PkaAddJcbAfn2Mdf+0x168>)
    7f20:	601a      	str	r2, [r3, #0]
    7f22:	6822      	ldr	r2, [r4, #0]
    7f24:	920a      	str	r2, [sp, #40]	; 0x28
    7f26:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    7f28:	07d1      	lsls	r1, r2, #31
    7f2a:	d5fa      	bpl.n	7f22 <PkaAddJcbAfn2Mdf+0x92>
    7f2c:	4a33      	ldr	r2, [pc, #204]	; (7ffc <PkaAddJcbAfn2Mdf+0x16c>)
    7f2e:	601a      	str	r2, [r3, #0]
    7f30:	6822      	ldr	r2, [r4, #0]
    7f32:	920b      	str	r2, [sp, #44]	; 0x2c
    7f34:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    7f36:	07d2      	lsls	r2, r2, #31
    7f38:	d5fa      	bpl.n	7f30 <PkaAddJcbAfn2Mdf+0xa0>
    7f3a:	4a31      	ldr	r2, [pc, #196]	; (8000 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE>)
    7f3c:	601a      	str	r2, [r3, #0]
    7f3e:	6822      	ldr	r2, [r4, #0]
    7f40:	920c      	str	r2, [sp, #48]	; 0x30
    7f42:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    7f44:	07d0      	lsls	r0, r2, #31
    7f46:	d5fa      	bpl.n	7f3e <PkaAddJcbAfn2Mdf+0xae>
    7f48:	4a2e      	ldr	r2, [pc, #184]	; (8004 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x4>)
    7f4a:	601a      	str	r2, [r3, #0]
    7f4c:	6822      	ldr	r2, [r4, #0]
    7f4e:	920d      	str	r2, [sp, #52]	; 0x34
    7f50:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    7f52:	07d1      	lsls	r1, r2, #31
    7f54:	d5fa      	bpl.n	7f4c <PkaAddJcbAfn2Mdf+0xbc>
    7f56:	4a2c      	ldr	r2, [pc, #176]	; (8008 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x8>)
    7f58:	601a      	str	r2, [r3, #0]
    7f5a:	6822      	ldr	r2, [r4, #0]
    7f5c:	920e      	str	r2, [sp, #56]	; 0x38
    7f5e:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    7f60:	07d2      	lsls	r2, r2, #31
    7f62:	d5fa      	bpl.n	7f5a <PkaAddJcbAfn2Mdf+0xca>
    7f64:	4a29      	ldr	r2, [pc, #164]	; (800c <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0xc>)
    7f66:	601a      	str	r2, [r3, #0]
    7f68:	6822      	ldr	r2, [r4, #0]
    7f6a:	920f      	str	r2, [sp, #60]	; 0x3c
    7f6c:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    7f6e:	07d0      	lsls	r0, r2, #31
    7f70:	d5fa      	bpl.n	7f68 <PkaAddJcbAfn2Mdf+0xd8>
    7f72:	4a27      	ldr	r2, [pc, #156]	; (8010 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x10>)
    7f74:	601a      	str	r2, [r3, #0]
    7f76:	6821      	ldr	r1, [r4, #0]
    7f78:	9110      	str	r1, [sp, #64]	; 0x40
    7f7a:	9910      	ldr	r1, [sp, #64]	; 0x40
    7f7c:	07c9      	lsls	r1, r1, #31
    7f7e:	d5fa      	bpl.n	7f76 <PkaAddJcbAfn2Mdf+0xe6>
    7f80:	601a      	str	r2, [r3, #0]
    7f82:	4b14      	ldr	r3, [pc, #80]	; (7fd4 <PkaAddJcbAfn2Mdf+0x144>)
    7f84:	461a      	mov	r2, r3
    7f86:	6819      	ldr	r1, [r3, #0]
    7f88:	9111      	str	r1, [sp, #68]	; 0x44
    7f8a:	9911      	ldr	r1, [sp, #68]	; 0x44
    7f8c:	07c8      	lsls	r0, r1, #31
    7f8e:	d5fa      	bpl.n	7f86 <PkaAddJcbAfn2Mdf+0xf6>
    7f90:	4b11      	ldr	r3, [pc, #68]	; (7fd8 <PkaAddJcbAfn2Mdf+0x148>)
    7f92:	4920      	ldr	r1, [pc, #128]	; (8014 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x14>)
    7f94:	6019      	str	r1, [r3, #0]
    7f96:	6811      	ldr	r1, [r2, #0]
    7f98:	9112      	str	r1, [sp, #72]	; 0x48
    7f9a:	9912      	ldr	r1, [sp, #72]	; 0x48
    7f9c:	07c9      	lsls	r1, r1, #31
    7f9e:	d5fa      	bpl.n	7f96 <PkaAddJcbAfn2Mdf+0x106>
    7fa0:	491d      	ldr	r1, [pc, #116]	; (8018 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x18>)
    7fa2:	6019      	str	r1, [r3, #0]
    7fa4:	6811      	ldr	r1, [r2, #0]
    7fa6:	9113      	str	r1, [sp, #76]	; 0x4c
    7fa8:	9913      	ldr	r1, [sp, #76]	; 0x4c
    7faa:	07cc      	lsls	r4, r1, #31
    7fac:	d5fa      	bpl.n	7fa4 <PkaAddJcbAfn2Mdf+0x114>
    7fae:	490b      	ldr	r1, [pc, #44]	; (7fdc <PkaAddJcbAfn2Mdf+0x14c>)
    7fb0:	6019      	str	r1, [r3, #0]
    7fb2:	6811      	ldr	r1, [r2, #0]
    7fb4:	9114      	str	r1, [sp, #80]	; 0x50
    7fb6:	9914      	ldr	r1, [sp, #80]	; 0x50
    7fb8:	07c8      	lsls	r0, r1, #31
    7fba:	d5fa      	bpl.n	7fb2 <PkaAddJcbAfn2Mdf+0x122>
    7fbc:	4917      	ldr	r1, [pc, #92]	; (801c <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x1c>)
    7fbe:	6019      	str	r1, [r3, #0]
    7fc0:	6811      	ldr	r1, [r2, #0]
    7fc2:	9115      	str	r1, [sp, #84]	; 0x54
    7fc4:	9915      	ldr	r1, [sp, #84]	; 0x54
    7fc6:	07c9      	lsls	r1, r1, #31
    7fc8:	d5fa      	bpl.n	7fc0 <PkaAddJcbAfn2Mdf+0x130>
    7fca:	4a15      	ldr	r2, [pc, #84]	; (8020 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x20>)
    7fcc:	601a      	str	r2, [r3, #0]
    7fce:	b016      	add	sp, #88	; 0x58
    7fd0:	bd10      	pop	{r4, pc}
    7fd2:	bf00      	nop
    7fd4:	5002b0b0 	.word	0x5002b0b0
    7fd8:	5002b080 	.word	0x5002b080
    7fdc:	90410440 	.word	0x90410440
    7fe0:	29298600 	.word	0x29298600
    7fe4:	c80110d8 	.word	0xc80110d8
    7fe8:	90411440 	.word	0x90411440
    7fec:	29211440 	.word	0x29211440
    7ff0:	21651440 	.word	0x21651440
    7ff4:	90403400 	.word	0x90403400
    7ff8:	900c3100 	.word	0x900c3100
    7ffc:	900c40c0 	.word	0x900c40c0
    8000:	292030c0 	.word	0x292030c0
    8004:	900d9640 	.word	0x900d9640
    8008:	90604100 	.word	0x90604100
    800c:	c8451603 	.word	0xc8451603
    8010:	21118600 	.word	0x21118600
    8014:	21604100 	.word	0x21604100
    8018:	c8444659 	.word	0xc8444659
    801c:	90451440 	.word	0x90451440
    8020:	902d1440 	.word	0x902d1440

00008024 <PkaJcb2Afn>:
    8024:	b570      	push	{r4, r5, r6, lr}
    8026:	4826      	ldr	r0, [pc, #152]	; (80c0 <PkaJcb2Afn+0x9c>)
    8028:	b088      	sub	sp, #32
    802a:	4605      	mov	r5, r0
    802c:	6804      	ldr	r4, [r0, #0]
    802e:	9400      	str	r4, [sp, #0]
    8030:	9c00      	ldr	r4, [sp, #0]
    8032:	07e6      	lsls	r6, r4, #31
    8034:	d5fa      	bpl.n	802c <PkaJcb2Afn+0x8>
    8036:	4823      	ldr	r0, [pc, #140]	; (80c4 <PkaJcb2Afn+0xa0>)
    8038:	4c23      	ldr	r4, [pc, #140]	; (80c8 <PkaJcb2Afn+0xa4>)
    803a:	6004      	str	r4, [r0, #0]
    803c:	4c23      	ldr	r4, [pc, #140]	; (80cc <PkaJcb2Afn+0xa8>)
    803e:	ea44 4383 	orr.w	r3, r4, r3, lsl #18
    8042:	682c      	ldr	r4, [r5, #0]
    8044:	9401      	str	r4, [sp, #4]
    8046:	9c01      	ldr	r4, [sp, #4]
    8048:	07e4      	lsls	r4, r4, #31
    804a:	d5fa      	bpl.n	8042 <PkaJcb2Afn+0x1e>
    804c:	6003      	str	r3, [r0, #0]
    804e:	0193      	lsls	r3, r2, #6
    8050:	ea43 4282 	orr.w	r2, r3, r2, lsl #18
    8054:	f042 4410 	orr.w	r4, r2, #2415919104	; 0x90000000
    8058:	f444 44c0 	orr.w	r4, r4, #24576	; 0x6000
    805c:	682b      	ldr	r3, [r5, #0]
    805e:	9302      	str	r3, [sp, #8]
    8060:	9b02      	ldr	r3, [sp, #8]
    8062:	07de      	lsls	r6, r3, #31
    8064:	d5fa      	bpl.n	805c <PkaJcb2Afn+0x38>
    8066:	6004      	str	r4, [r0, #0]
    8068:	682b      	ldr	r3, [r5, #0]
    806a:	9303      	str	r3, [sp, #12]
    806c:	9b03      	ldr	r3, [sp, #12]
    806e:	07db      	lsls	r3, r3, #31
    8070:	d5fa      	bpl.n	8068 <PkaJcb2Afn+0x44>
    8072:	4b17      	ldr	r3, [pc, #92]	; (80d0 <PkaJcb2Afn+0xac>)
    8074:	6003      	str	r3, [r0, #0]
    8076:	018b      	lsls	r3, r1, #6
    8078:	ea43 4181 	orr.w	r1, r3, r1, lsl #18
    807c:	f041 4310 	orr.w	r3, r1, #2415919104	; 0x90000000
    8080:	f443 43c0 	orr.w	r3, r3, #24576	; 0x6000
    8084:	682e      	ldr	r6, [r5, #0]
    8086:	9604      	str	r6, [sp, #16]
    8088:	9e04      	ldr	r6, [sp, #16]
    808a:	07f6      	lsls	r6, r6, #31
    808c:	d5fa      	bpl.n	8084 <PkaJcb2Afn+0x60>
    808e:	6003      	str	r3, [r0, #0]
    8090:	682b      	ldr	r3, [r5, #0]
    8092:	9305      	str	r3, [sp, #20]
    8094:	9b05      	ldr	r3, [sp, #20]
    8096:	07de      	lsls	r6, r3, #31
    8098:	d5fa      	bpl.n	8090 <PkaJcb2Afn+0x6c>
    809a:	6004      	str	r4, [r0, #0]
    809c:	f041 4158 	orr.w	r1, r1, #3623878656	; 0xd8000000
    80a0:	682b      	ldr	r3, [r5, #0]
    80a2:	9306      	str	r3, [sp, #24]
    80a4:	9b06      	ldr	r3, [sp, #24]
    80a6:	07dc      	lsls	r4, r3, #31
    80a8:	d5fa      	bpl.n	80a0 <PkaJcb2Afn+0x7c>
    80aa:	6001      	str	r1, [r0, #0]
    80ac:	f042 4258 	orr.w	r2, r2, #3623878656	; 0xd8000000
    80b0:	682b      	ldr	r3, [r5, #0]
    80b2:	9307      	str	r3, [sp, #28]
    80b4:	9b07      	ldr	r3, [sp, #28]
    80b6:	07db      	lsls	r3, r3, #31
    80b8:	d5fa      	bpl.n	80b0 <PkaJcb2Afn+0x8c>
    80ba:	6002      	str	r2, [r0, #0]
    80bc:	b008      	add	sp, #32
    80be:	bd70      	pop	{r4, r5, r6, pc}
    80c0:	5002b0b0 	.word	0x5002b0b0
    80c4:	5002b080 	.word	0x5002b080
    80c8:	290221c0 	.word	0x290221c0
    80cc:	98007180 	.word	0x98007180
    80d0:	90186180 	.word	0x90186180

000080d4 <PkaAddAff>:
    80d4:	4b35      	ldr	r3, [pc, #212]	; (81ac <PkaAddAff+0xd8>)
    80d6:	b08e      	sub	sp, #56	; 0x38
    80d8:	4619      	mov	r1, r3
    80da:	681a      	ldr	r2, [r3, #0]
    80dc:	9200      	str	r2, [sp, #0]
    80de:	9a00      	ldr	r2, [sp, #0]
    80e0:	07d2      	lsls	r2, r2, #31
    80e2:	d5fa      	bpl.n	80da <PkaAddAff+0x6>
    80e4:	4b32      	ldr	r3, [pc, #200]	; (81b0 <PkaAddAff+0xdc>)
    80e6:	4a33      	ldr	r2, [pc, #204]	; (81b4 <PkaAddAff+0xe0>)
    80e8:	601a      	str	r2, [r3, #0]
    80ea:	680a      	ldr	r2, [r1, #0]
    80ec:	9201      	str	r2, [sp, #4]
    80ee:	9a01      	ldr	r2, [sp, #4]
    80f0:	07d0      	lsls	r0, r2, #31
    80f2:	d5fa      	bpl.n	80ea <PkaAddAff+0x16>
    80f4:	4a30      	ldr	r2, [pc, #192]	; (81b8 <PkaAddAff+0xe4>)
    80f6:	601a      	str	r2, [r3, #0]
    80f8:	680a      	ldr	r2, [r1, #0]
    80fa:	9202      	str	r2, [sp, #8]
    80fc:	9a02      	ldr	r2, [sp, #8]
    80fe:	07d2      	lsls	r2, r2, #31
    8100:	d5fa      	bpl.n	80f8 <PkaAddAff+0x24>
    8102:	4a2e      	ldr	r2, [pc, #184]	; (81bc <PkaAddAff+0xe8>)
    8104:	601a      	str	r2, [r3, #0]
    8106:	680a      	ldr	r2, [r1, #0]
    8108:	9203      	str	r2, [sp, #12]
    810a:	9a03      	ldr	r2, [sp, #12]
    810c:	07d0      	lsls	r0, r2, #31
    810e:	d5fa      	bpl.n	8106 <PkaAddAff+0x32>
    8110:	4a2b      	ldr	r2, [pc, #172]	; (81c0 <PkaAddAff+0xec>)
    8112:	601a      	str	r2, [r3, #0]
    8114:	680a      	ldr	r2, [r1, #0]
    8116:	9204      	str	r2, [sp, #16]
    8118:	9a04      	ldr	r2, [sp, #16]
    811a:	07d2      	lsls	r2, r2, #31
    811c:	d5fa      	bpl.n	8114 <PkaAddAff+0x40>
    811e:	4a29      	ldr	r2, [pc, #164]	; (81c4 <PkaAddAff+0xf0>)
    8120:	601a      	str	r2, [r3, #0]
    8122:	680a      	ldr	r2, [r1, #0]
    8124:	9205      	str	r2, [sp, #20]
    8126:	9a05      	ldr	r2, [sp, #20]
    8128:	07d0      	lsls	r0, r2, #31
    812a:	d5fa      	bpl.n	8122 <PkaAddAff+0x4e>
    812c:	4a26      	ldr	r2, [pc, #152]	; (81c8 <PkaAddAff+0xf4>)
    812e:	601a      	str	r2, [r3, #0]
    8130:	680a      	ldr	r2, [r1, #0]
    8132:	9206      	str	r2, [sp, #24]
    8134:	9a06      	ldr	r2, [sp, #24]
    8136:	07d2      	lsls	r2, r2, #31
    8138:	d5fa      	bpl.n	8130 <PkaAddAff+0x5c>
    813a:	4a24      	ldr	r2, [pc, #144]	; (81cc <PkaAddAff+0xf8>)
    813c:	601a      	str	r2, [r3, #0]
    813e:	680a      	ldr	r2, [r1, #0]
    8140:	9207      	str	r2, [sp, #28]
    8142:	9a07      	ldr	r2, [sp, #28]
    8144:	07d0      	lsls	r0, r2, #31
    8146:	d5fa      	bpl.n	813e <PkaAddAff+0x6a>
    8148:	4a21      	ldr	r2, [pc, #132]	; (81d0 <PkaAddAff+0xfc>)
    814a:	601a      	str	r2, [r3, #0]
    814c:	680a      	ldr	r2, [r1, #0]
    814e:	9208      	str	r2, [sp, #32]
    8150:	9a08      	ldr	r2, [sp, #32]
    8152:	07d2      	lsls	r2, r2, #31
    8154:	d5fa      	bpl.n	814c <PkaAddAff+0x78>
    8156:	4a1f      	ldr	r2, [pc, #124]	; (81d4 <PkaAddAff+0x100>)
    8158:	601a      	str	r2, [r3, #0]
    815a:	680a      	ldr	r2, [r1, #0]
    815c:	9209      	str	r2, [sp, #36]	; 0x24
    815e:	9a09      	ldr	r2, [sp, #36]	; 0x24
    8160:	07d0      	lsls	r0, r2, #31
    8162:	d5fa      	bpl.n	815a <PkaAddAff+0x86>
    8164:	4a1c      	ldr	r2, [pc, #112]	; (81d8 <PkaAddAff+0x104>)
    8166:	601a      	str	r2, [r3, #0]
    8168:	680a      	ldr	r2, [r1, #0]
    816a:	920a      	str	r2, [sp, #40]	; 0x28
    816c:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    816e:	07d2      	lsls	r2, r2, #31
    8170:	d5fa      	bpl.n	8168 <PkaAddAff+0x94>
    8172:	4a1a      	ldr	r2, [pc, #104]	; (81dc <PkaAddAff+0x108>)
    8174:	601a      	str	r2, [r3, #0]
    8176:	6808      	ldr	r0, [r1, #0]
    8178:	900b      	str	r0, [sp, #44]	; 0x2c
    817a:	980b      	ldr	r0, [sp, #44]	; 0x2c
    817c:	07c0      	lsls	r0, r0, #31
    817e:	d5fa      	bpl.n	8176 <PkaAddAff+0xa2>
    8180:	601a      	str	r2, [r3, #0]
    8182:	680a      	ldr	r2, [r1, #0]
    8184:	920c      	str	r2, [sp, #48]	; 0x30
    8186:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    8188:	07d0      	lsls	r0, r2, #31
    818a:	d5fa      	bpl.n	8182 <PkaAddAff+0xae>
    818c:	4a14      	ldr	r2, [pc, #80]	; (81e0 <PkaAddAff+0x10c>)
    818e:	601a      	str	r2, [r3, #0]
    8190:	680a      	ldr	r2, [r1, #0]
    8192:	920d      	str	r2, [sp, #52]	; 0x34
    8194:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    8196:	07d2      	lsls	r2, r2, #31
    8198:	d5fa      	bpl.n	8190 <PkaAddAff+0xbc>
    819a:	4a12      	ldr	r2, [pc, #72]	; (81e4 <PkaAddAff+0x110>)
    819c:	601a      	str	r2, [r3, #0]
    819e:	210e      	movs	r1, #14
    81a0:	230d      	movs	r3, #13
    81a2:	220f      	movs	r2, #15
    81a4:	2000      	movs	r0, #0
    81a6:	b00e      	add	sp, #56	; 0x38
    81a8:	f7ff bf3c 	b.w	8024 <PkaJcb2Afn>
    81ac:	5002b0b0 	.word	0x5002b0b0
    81b0:	5002b080 	.word	0x5002b080
    81b4:	29014380 	.word	0x29014380
    81b8:	21396340 	.word	0x21396340
    81bc:	29017080 	.word	0x29017080
    81c0:	21542080 	.word	0x21542080
    81c4:	9034d100 	.word	0x9034d100
    81c8:	903440c0 	.word	0x903440c0
    81cc:	292030c0 	.word	0x292030c0
    81d0:	900d53c0 	.word	0x900d53c0
    81d4:	90384100 	.word	0x90384100
    81d8:	c8082383 	.word	0xc8082383
    81dc:	2110e380 	.word	0x2110e380
    81e0:	21384100 	.word	0x21384100
    81e4:	c80843cf 	.word	0xc80843cf

000081e8 <PkaSum2ScalarMullt>:
    81e8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    81ec:	2301      	movs	r3, #1
    81ee:	b092      	sub	sp, #72	; 0x48
    81f0:	e9cd 3303 	strd	r3, r3, [sp, #12]
    81f4:	4b62      	ldr	r3, [pc, #392]	; (8380 <PkaSum2ScalarMullt+0x198>)
    81f6:	461d      	mov	r5, r3
    81f8:	681a      	ldr	r2, [r3, #0]
    81fa:	9205      	str	r2, [sp, #20]
    81fc:	9a05      	ldr	r2, [sp, #20]
    81fe:	07d2      	lsls	r2, r2, #31
    8200:	d5fa      	bpl.n	81f8 <PkaSum2ScalarMullt+0x10>
    8202:	4c60      	ldr	r4, [pc, #384]	; (8384 <PkaSum2ScalarMullt+0x19c>)
    8204:	4b60      	ldr	r3, [pc, #384]	; (8388 <PkaSum2ScalarMullt+0x1a0>)
    8206:	6023      	str	r3, [r4, #0]
    8208:	4b60      	ldr	r3, [pc, #384]	; (838c <PkaSum2ScalarMullt+0x1a4>)
    820a:	4619      	mov	r1, r3
    820c:	681a      	ldr	r2, [r3, #0]
    820e:	9206      	str	r2, [sp, #24]
    8210:	9a06      	ldr	r2, [sp, #24]
    8212:	07d7      	lsls	r7, r2, #31
    8214:	d5fa      	bpl.n	820c <PkaSum2ScalarMullt+0x24>
    8216:	4b5e      	ldr	r3, [pc, #376]	; (8390 <PkaSum2ScalarMullt+0x1a8>)
    8218:	681a      	ldr	r2, [r3, #0]
    821a:	04d6      	lsls	r6, r2, #19
    821c:	f100 80a8 	bmi.w	8370 <PkaSum2ScalarMullt+0x188>
    8220:	682a      	ldr	r2, [r5, #0]
    8222:	9207      	str	r2, [sp, #28]
    8224:	9a07      	ldr	r2, [sp, #28]
    8226:	07d0      	lsls	r0, r2, #31
    8228:	d5fa      	bpl.n	8220 <PkaSum2ScalarMullt+0x38>
    822a:	4a5a      	ldr	r2, [pc, #360]	; (8394 <PkaSum2ScalarMullt+0x1ac>)
    822c:	6022      	str	r2, [r4, #0]
    822e:	680a      	ldr	r2, [r1, #0]
    8230:	9208      	str	r2, [sp, #32]
    8232:	9a08      	ldr	r2, [sp, #32]
    8234:	07d2      	lsls	r2, r2, #31
    8236:	d5fa      	bpl.n	822e <PkaSum2ScalarMullt+0x46>
    8238:	681e      	ldr	r6, [r3, #0]
    823a:	f3c6 3600 	ubfx	r6, r6, #12, #1
    823e:	2e00      	cmp	r6, #0
    8240:	f040 8098 	bne.w	8374 <PkaSum2ScalarMullt+0x18c>
    8244:	2012      	movs	r0, #18
    8246:	f7ff f8f9 	bl	743c <PkaGetRegEffectiveSizeInBits>
    824a:	4607      	mov	r7, r0
    824c:	2013      	movs	r0, #19
    824e:	f7ff f8f5 	bl	743c <PkaGetRegEffectiveSizeInBits>
    8252:	4287      	cmp	r7, r0
    8254:	bf8c      	ite	hi
    8256:	2012      	movhi	r0, #18
    8258:	2013      	movls	r0, #19
    825a:	f7ff f8ef 	bl	743c <PkaGetRegEffectiveSizeInBits>
    825e:	1e47      	subs	r7, r0, #1
    8260:	f7ff ff38 	bl	80d4 <PkaAddAff>
    8264:	ab03      	add	r3, sp, #12
    8266:	aa01      	add	r2, sp, #4
    8268:	4639      	mov	r1, r7
    826a:	2012      	movs	r0, #18
    826c:	f7ff f92c 	bl	74c8 <PkaGetNextMsBit>
    8270:	ab04      	add	r3, sp, #16
    8272:	4680      	mov	r8, r0
    8274:	aa02      	add	r2, sp, #8
    8276:	4639      	mov	r1, r7
    8278:	2013      	movs	r0, #19
    827a:	f7ff f925 	bl	74c8 <PkaGetNextMsBit>
    827e:	eb00 0048 	add.w	r0, r0, r8, lsl #1
    8282:	2802      	cmp	r0, #2
    8284:	d032      	beq.n	82ec <PkaSum2ScalarMullt+0x104>
    8286:	2803      	cmp	r0, #3
    8288:	d03e      	beq.n	8308 <PkaSum2ScalarMullt+0x120>
    828a:	2801      	cmp	r0, #1
    828c:	d174      	bne.n	8378 <PkaSum2ScalarMullt+0x190>
    828e:	682b      	ldr	r3, [r5, #0]
    8290:	9309      	str	r3, [sp, #36]	; 0x24
    8292:	9b09      	ldr	r3, [sp, #36]	; 0x24
    8294:	07db      	lsls	r3, r3, #31
    8296:	d5fa      	bpl.n	828e <PkaSum2ScalarMullt+0xa6>
    8298:	4b3f      	ldr	r3, [pc, #252]	; (8398 <PkaSum2ScalarMullt+0x1b0>)
    829a:	6023      	str	r3, [r4, #0]
    829c:	682b      	ldr	r3, [r5, #0]
    829e:	930a      	str	r3, [sp, #40]	; 0x28
    82a0:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    82a2:	07d8      	lsls	r0, r3, #31
    82a4:	d5fa      	bpl.n	829c <PkaSum2ScalarMullt+0xb4>
    82a6:	4b3d      	ldr	r3, [pc, #244]	; (839c <PkaSum2ScalarMullt+0x1b4>)
    82a8:	6023      	str	r3, [r4, #0]
    82aa:	682b      	ldr	r3, [r5, #0]
    82ac:	930f      	str	r3, [sp, #60]	; 0x3c
    82ae:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    82b0:	07d9      	lsls	r1, r3, #31
    82b2:	d5fa      	bpl.n	82aa <PkaSum2ScalarMullt+0xc2>
    82b4:	4b3a      	ldr	r3, [pc, #232]	; (83a0 <PkaSum2ScalarMullt+0x1b8>)
    82b6:	6023      	str	r3, [r4, #0]
    82b8:	682b      	ldr	r3, [r5, #0]
    82ba:	9310      	str	r3, [sp, #64]	; 0x40
    82bc:	9b10      	ldr	r3, [sp, #64]	; 0x40
    82be:	07da      	lsls	r2, r3, #31
    82c0:	d5fa      	bpl.n	82b8 <PkaSum2ScalarMullt+0xd0>
    82c2:	4b38      	ldr	r3, [pc, #224]	; (83a4 <PkaSum2ScalarMullt+0x1bc>)
    82c4:	6023      	str	r3, [r4, #0]
    82c6:	682b      	ldr	r3, [r5, #0]
    82c8:	9311      	str	r3, [sp, #68]	; 0x44
    82ca:	9b11      	ldr	r3, [sp, #68]	; 0x44
    82cc:	07db      	lsls	r3, r3, #31
    82ce:	d5fa      	bpl.n	82c6 <PkaSum2ScalarMullt+0xde>
    82d0:	4b35      	ldr	r3, [pc, #212]	; (83a8 <PkaSum2ScalarMullt+0x1c0>)
    82d2:	6023      	str	r3, [r4, #0]
    82d4:	3f01      	subs	r7, #1
    82d6:	d525      	bpl.n	8324 <PkaSum2ScalarMullt+0x13c>
    82d8:	2310      	movs	r3, #16
    82da:	2219      	movs	r2, #25
    82dc:	2118      	movs	r1, #24
    82de:	2000      	movs	r0, #0
    82e0:	f7ff fea0 	bl	8024 <PkaJcb2Afn>
    82e4:	4630      	mov	r0, r6
    82e6:	b012      	add	sp, #72	; 0x48
    82e8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    82ec:	682b      	ldr	r3, [r5, #0]
    82ee:	930b      	str	r3, [sp, #44]	; 0x2c
    82f0:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
    82f2:	07d9      	lsls	r1, r3, #31
    82f4:	d5fa      	bpl.n	82ec <PkaSum2ScalarMullt+0x104>
    82f6:	4b2d      	ldr	r3, [pc, #180]	; (83ac <PkaSum2ScalarMullt+0x1c4>)
    82f8:	6023      	str	r3, [r4, #0]
    82fa:	682b      	ldr	r3, [r5, #0]
    82fc:	930c      	str	r3, [sp, #48]	; 0x30
    82fe:	9b0c      	ldr	r3, [sp, #48]	; 0x30
    8300:	07da      	lsls	r2, r3, #31
    8302:	d5fa      	bpl.n	82fa <PkaSum2ScalarMullt+0x112>
    8304:	4b2a      	ldr	r3, [pc, #168]	; (83b0 <PkaSum2ScalarMullt+0x1c8>)
    8306:	e7cf      	b.n	82a8 <PkaSum2ScalarMullt+0xc0>
    8308:	682b      	ldr	r3, [r5, #0]
    830a:	930d      	str	r3, [sp, #52]	; 0x34
    830c:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    830e:	07db      	lsls	r3, r3, #31
    8310:	d5fa      	bpl.n	8308 <PkaSum2ScalarMullt+0x120>
    8312:	4b28      	ldr	r3, [pc, #160]	; (83b4 <PkaSum2ScalarMullt+0x1cc>)
    8314:	6023      	str	r3, [r4, #0]
    8316:	682b      	ldr	r3, [r5, #0]
    8318:	930e      	str	r3, [sp, #56]	; 0x38
    831a:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    831c:	07d8      	lsls	r0, r3, #31
    831e:	d5fa      	bpl.n	8316 <PkaSum2ScalarMullt+0x12e>
    8320:	4b25      	ldr	r3, [pc, #148]	; (83b8 <PkaSum2ScalarMullt+0x1d0>)
    8322:	e7c1      	b.n	82a8 <PkaSum2ScalarMullt+0xc0>
    8324:	ab03      	add	r3, sp, #12
    8326:	aa01      	add	r2, sp, #4
    8328:	4639      	mov	r1, r7
    832a:	2012      	movs	r0, #18
    832c:	f7ff f8cc 	bl	74c8 <PkaGetNextMsBit>
    8330:	ab04      	add	r3, sp, #16
    8332:	4604      	mov	r4, r0
    8334:	aa02      	add	r2, sp, #8
    8336:	4639      	mov	r1, r7
    8338:	2013      	movs	r0, #19
    833a:	f7ff f8c5 	bl	74c8 <PkaGetNextMsBit>
    833e:	eb10 0444 	adds.w	r4, r0, r4, lsl #1
    8342:	d102      	bne.n	834a <PkaSum2ScalarMullt+0x162>
    8344:	f7ff fc12 	bl	7b6c <PkaDoubleMdf2Mdf>
    8348:	e7c4      	b.n	82d4 <PkaSum2ScalarMullt+0xec>
    834a:	f7ff fce5 	bl	7d18 <PkaDoubleMdf2Jcb>
    834e:	2c02      	cmp	r4, #2
    8350:	d008      	beq.n	8364 <PkaSum2ScalarMullt+0x17c>
    8352:	2c03      	cmp	r4, #3
    8354:	d009      	beq.n	836a <PkaSum2ScalarMullt+0x182>
    8356:	2c01      	cmp	r4, #1
    8358:	d110      	bne.n	837c <PkaSum2ScalarMullt+0x194>
    835a:	2117      	movs	r1, #23
    835c:	2016      	movs	r0, #22
    835e:	f7ff fd97 	bl	7e90 <PkaAddJcbAfn2Mdf>
    8362:	e7b7      	b.n	82d4 <PkaSum2ScalarMullt+0xec>
    8364:	2115      	movs	r1, #21
    8366:	2014      	movs	r0, #20
    8368:	e7f9      	b.n	835e <PkaSum2ScalarMullt+0x176>
    836a:	210f      	movs	r1, #15
    836c:	200e      	movs	r0, #14
    836e:	e7f6      	b.n	835e <PkaSum2ScalarMullt+0x176>
    8370:	4e12      	ldr	r6, [pc, #72]	; (83bc <PkaSum2ScalarMullt+0x1d4>)
    8372:	e7b7      	b.n	82e4 <PkaSum2ScalarMullt+0xfc>
    8374:	4e12      	ldr	r6, [pc, #72]	; (83c0 <PkaSum2ScalarMullt+0x1d8>)
    8376:	e7b5      	b.n	82e4 <PkaSum2ScalarMullt+0xfc>
    8378:	4e12      	ldr	r6, [pc, #72]	; (83c4 <PkaSum2ScalarMullt+0x1dc>)
    837a:	e7b3      	b.n	82e4 <PkaSum2ScalarMullt+0xfc>
    837c:	4e12      	ldr	r6, [pc, #72]	; (83c8 <PkaSum2ScalarMullt+0x1e0>)
    837e:	e7b1      	b.n	82e4 <PkaSum2ScalarMullt+0xfc>
    8380:	5002b0b0 	.word	0x5002b0b0
    8384:	5002b080 	.word	0x5002b080
    8388:	514a0800 	.word	0x514a0800
    838c:	5002b0b4 	.word	0x5002b0b4
    8390:	5002b088 	.word	0x5002b088
    8394:	514e0800 	.word	0x514e0800
    8398:	495a0600 	.word	0x495a0600
    839c:	495e0640 	.word	0x495e0640
    83a0:	41420400 	.word	0x41420400
    83a4:	49421400 	.word	0x49421400
    83a8:	492e0440 	.word	0x492e0440
    83ac:	49520600 	.word	0x49520600
    83b0:	49560640 	.word	0x49560640
    83b4:	493a0600 	.word	0x493a0600
    83b8:	493e0640 	.word	0x493e0640
    83bc:	00f10806 	.word	0x00f10806
    83c0:	00f10807 	.word	0x00f10807
    83c4:	00f10804 	.word	0x00f10804
    83c8:	00f10805 	.word	0x00f10805

000083cc <SaSi_HalClearInterruptBit>:
    83cc:	4b01      	ldr	r3, [pc, #4]	; (83d4 <SaSi_HalClearInterruptBit+0x8>)
    83ce:	6018      	str	r0, [r3, #0]
    83d0:	4770      	bx	lr
    83d2:	bf00      	nop
    83d4:	5002ba08 	.word	0x5002ba08

000083d8 <SaSi_HalMaskInterrupt>:
    83d8:	4b01      	ldr	r3, [pc, #4]	; (83e0 <SaSi_HalMaskInterrupt+0x8>)
    83da:	6018      	str	r0, [r3, #0]
    83dc:	4770      	bx	lr
    83de:	bf00      	nop
    83e0:	5002ba04 	.word	0x5002ba04

000083e4 <SaSi_HalWaitInterrupt>:
    83e4:	4a03      	ldr	r2, [pc, #12]	; (83f4 <SaSi_HalWaitInterrupt+0x10>)
    83e6:	6813      	ldr	r3, [r2, #0]
    83e8:	4218      	tst	r0, r3
    83ea:	d0fc      	beq.n	83e6 <SaSi_HalWaitInterrupt+0x2>
    83ec:	4a02      	ldr	r2, [pc, #8]	; (83f8 <SaSi_HalWaitInterrupt+0x14>)
    83ee:	6010      	str	r0, [r2, #0]
    83f0:	4618      	mov	r0, r3
    83f2:	4770      	bx	lr
    83f4:	5002ba00 	.word	0x5002ba00
    83f8:	5002ba08 	.word	0x5002ba08

000083fc <flash_area_id_from_multi_image_slot>:
    switch (slot) {
    83fc:	4608      	mov	r0, r1
    83fe:	b129      	cbz	r1, 840c <flash_area_id_from_multi_image_slot+0x10>
    return -EINVAL; /* flash_area_open will fail on that */
    8400:	2901      	cmp	r1, #1
    8402:	bf0c      	ite	eq
    8404:	4608      	moveq	r0, r1
    8406:	f06f 0015 	mvnne.w	r0, #21
    840a:	4770      	bx	lr
    case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
    840c:	2003      	movs	r0, #3
}
    840e:	4770      	bx	lr

00008410 <flash_area_get_device_id>:

uint8_t flash_area_get_device_id(const struct flash_area *fa)
{
	(void)fa;
	return FLASH_DEVICE_ID;
}
    8410:	2000      	movs	r0, #0
    8412:	4770      	bx	lr

00008414 <os_heap_init>:
    mbedtls_memory_buffer_alloc_init(mempool, sizeof(mempool));
}
#else
void os_heap_init(void)
{
}
    8414:	4770      	bx	lr

00008416 <bootutil_tlv_iter_begin>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_begin(struct image_tlv_iter *it, const struct image_header *hdr,
                        const struct flash_area *fap, uint16_t type, bool prot)
{
    8416:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    841a:	460e      	mov	r6, r1
    841c:	4617      	mov	r7, r2
    841e:	4699      	mov	r9, r3
    uint32_t off_;
    struct image_tlv_info info;

    if (it == NULL || hdr == NULL || fap == NULL) {
    8420:	4604      	mov	r4, r0
    8422:	b928      	cbnz	r0, 8430 <bootutil_tlv_iter_begin+0x1a>
        return -1;
    8424:	f04f 38ff 	mov.w	r8, #4294967295
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    // position on first TLV
    it->tlv_off = off_ + sizeof(info);
    return 0;
}
    8428:	4640      	mov	r0, r8
    842a:	b003      	add	sp, #12
    842c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || hdr == NULL || fap == NULL) {
    8430:	2900      	cmp	r1, #0
    8432:	d0f7      	beq.n	8424 <bootutil_tlv_iter_begin+0xe>
    8434:	2a00      	cmp	r2, #0
    8436:	d0f5      	beq.n	8424 <bootutil_tlv_iter_begin+0xe>
    off_ = BOOT_TLV_OFF(hdr);
    8438:	68cb      	ldr	r3, [r1, #12]
    843a:	890d      	ldrh	r5, [r1, #8]
    843c:	441d      	add	r5, r3
    if (LOAD_IMAGE_DATA(hdr, fap, off_, &info, sizeof(info))) {
    843e:	2304      	movs	r3, #4
    8440:	eb0d 0203 	add.w	r2, sp, r3
    8444:	4629      	mov	r1, r5
    8446:	4638      	mov	r0, r7
    8448:	f000 fc51 	bl	8cee <flash_area_read>
    844c:	4680      	mov	r8, r0
    844e:	2800      	cmp	r0, #0
    8450:	d1e8      	bne.n	8424 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    8452:	f8bd 1004 	ldrh.w	r1, [sp, #4]
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    8456:	8973      	ldrh	r3, [r6, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    8458:	f646 1208 	movw	r2, #26888	; 0x6908
    845c:	4291      	cmp	r1, r2
    845e:	d125      	bne.n	84ac <bootutil_tlv_iter_begin+0x96>
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    8460:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    8464:	4299      	cmp	r1, r3
    8466:	d1dd      	bne.n	8424 <bootutil_tlv_iter_begin+0xe>
        if (LOAD_IMAGE_DATA(hdr, fap, off_ + info.it_tlv_tot,
    8468:	2304      	movs	r3, #4
    846a:	eb0d 0203 	add.w	r2, sp, r3
    846e:	4429      	add	r1, r5
    8470:	4638      	mov	r0, r7
    8472:	f000 fc3c 	bl	8cee <flash_area_read>
    8476:	2800      	cmp	r0, #0
    8478:	d1d4      	bne.n	8424 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    847a:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    847e:	f646 1307 	movw	r3, #26887	; 0x6907
    8482:	429a      	cmp	r2, r3
    8484:	d1ce      	bne.n	8424 <bootutil_tlv_iter_begin+0xe>
    it->fap = fap;
    8486:	e9c4 6700 	strd	r6, r7, [r4]
    it->prot = prot;
    848a:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
    it->type = type;
    848e:	f8a4 9008 	strh.w	r9, [r4, #8]
    it->prot = prot;
    8492:	72a3      	strb	r3, [r4, #10]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    8494:	8973      	ldrh	r3, [r6, #10]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    8496:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    849a:	442b      	add	r3, r5
    849c:	60e3      	str	r3, [r4, #12]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    849e:	8973      	ldrh	r3, [r6, #10]
    84a0:	4413      	add	r3, r2
    84a2:	442b      	add	r3, r5
    it->tlv_off = off_ + sizeof(info);
    84a4:	3504      	adds	r5, #4
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    84a6:	6163      	str	r3, [r4, #20]
    it->tlv_off = off_ + sizeof(info);
    84a8:	6125      	str	r5, [r4, #16]
    return 0;
    84aa:	e7bd      	b.n	8428 <bootutil_tlv_iter_begin+0x12>
    } else if (hdr->ih_protect_tlv_size != 0) {
    84ac:	2b00      	cmp	r3, #0
    84ae:	d0e4      	beq.n	847a <bootutil_tlv_iter_begin+0x64>
    84b0:	e7b8      	b.n	8424 <bootutil_tlv_iter_begin+0xe>

000084b2 <bootutil_tlv_iter_next>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off, uint16_t *len,
                       uint16_t *type)
{
    84b2:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    84b6:	460e      	mov	r6, r1
    84b8:	4617      	mov	r7, r2
    84ba:	461d      	mov	r5, r3
    struct image_tlv tlv;
    int rc;

    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    84bc:	4604      	mov	r4, r0
    84be:	b920      	cbnz	r0, 84ca <bootutil_tlv_iter_next+0x18>
        return -1;
    84c0:	f04f 30ff 	mov.w	r0, #4294967295

        it->tlv_off += sizeof(tlv) + tlv.it_len;
    }

    return 1;
}
    84c4:	b002      	add	sp, #8
    84c6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    84ca:	6803      	ldr	r3, [r0, #0]
    84cc:	2b00      	cmp	r3, #0
    84ce:	d0f7      	beq.n	84c0 <bootutil_tlv_iter_next+0xe>
    84d0:	6843      	ldr	r3, [r0, #4]
    84d2:	2b00      	cmp	r3, #0
    84d4:	d0f4      	beq.n	84c0 <bootutil_tlv_iter_next+0xe>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    84d6:	f64f 78ff 	movw	r8, #65535	; 0xffff
    while (it->tlv_off < it->tlv_end) {
    84da:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    84de:	429a      	cmp	r2, r3
    84e0:	d216      	bcs.n	8510 <bootutil_tlv_iter_next+0x5e>
        if (it->hdr->ih_protect_tlv_size > 0 && it->tlv_off == it->prot_end) {
    84e2:	6823      	ldr	r3, [r4, #0]
    84e4:	895b      	ldrh	r3, [r3, #10]
    84e6:	b123      	cbz	r3, 84f2 <bootutil_tlv_iter_next+0x40>
    84e8:	68e3      	ldr	r3, [r4, #12]
    84ea:	4293      	cmp	r3, r2
            it->tlv_off += sizeof(struct image_tlv_info);
    84ec:	bf04      	itt	eq
    84ee:	3304      	addeq	r3, #4
    84f0:	6123      	streq	r3, [r4, #16]
        rc = LOAD_IMAGE_DATA(it->hdr, it->fap, it->tlv_off, &tlv, sizeof tlv);
    84f2:	2304      	movs	r3, #4
    84f4:	6921      	ldr	r1, [r4, #16]
    84f6:	6860      	ldr	r0, [r4, #4]
    84f8:	eb0d 0203 	add.w	r2, sp, r3
    84fc:	f000 fbf7 	bl	8cee <flash_area_read>
        if (rc) {
    8500:	2800      	cmp	r0, #0
    8502:	d1dd      	bne.n	84c0 <bootutil_tlv_iter_next+0xe>
        if (it->prot && it->tlv_off >= it->prot_end) {
    8504:	7aa3      	ldrb	r3, [r4, #10]
    8506:	b12b      	cbz	r3, 8514 <bootutil_tlv_iter_next+0x62>
    8508:	e9d4 3203 	ldrd	r3, r2, [r4, #12]
    850c:	429a      	cmp	r2, r3
    850e:	d301      	bcc.n	8514 <bootutil_tlv_iter_next+0x62>
            return 1;
    8510:	2001      	movs	r0, #1
    8512:	e7d7      	b.n	84c4 <bootutil_tlv_iter_next+0x12>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    8514:	8923      	ldrh	r3, [r4, #8]
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    8516:	f8bd 1006 	ldrh.w	r1, [sp, #6]
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    851a:	4543      	cmp	r3, r8
    851c:	f101 0204 	add.w	r2, r1, #4
    8520:	d003      	beq.n	852a <bootutil_tlv_iter_next+0x78>
    8522:	f8bd c004 	ldrh.w	ip, [sp, #4]
    8526:	459c      	cmp	ip, r3
    8528:	d10b      	bne.n	8542 <bootutil_tlv_iter_next+0x90>
            if (type != NULL) {
    852a:	b115      	cbz	r5, 8532 <bootutil_tlv_iter_next+0x80>
                *type = tlv.it_type;
    852c:	f8bd 3004 	ldrh.w	r3, [sp, #4]
    8530:	802b      	strh	r3, [r5, #0]
            *off = it->tlv_off + sizeof(tlv);
    8532:	6923      	ldr	r3, [r4, #16]
    8534:	3304      	adds	r3, #4
    8536:	6033      	str	r3, [r6, #0]
            *len = tlv.it_len;
    8538:	8039      	strh	r1, [r7, #0]
            it->tlv_off += sizeof(tlv) + tlv.it_len;
    853a:	6923      	ldr	r3, [r4, #16]
    853c:	4413      	add	r3, r2
    853e:	6123      	str	r3, [r4, #16]
            return 0;
    8540:	e7c0      	b.n	84c4 <bootutil_tlv_iter_next+0x12>
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    8542:	6923      	ldr	r3, [r4, #16]
    8544:	4413      	add	r3, r2
    8546:	6123      	str	r3, [r4, #16]
    8548:	e7c7      	b.n	84da <bootutil_tlv_iter_next+0x28>

0000854a <bootutil_read_bigint>:
{
    854a:	b573      	push	{r0, r1, r4, r5, r6, lr}
    854c:	460c      	mov	r4, r1
    854e:	4606      	mov	r6, r0
    8550:	4611      	mov	r1, r2
    if (mbedtls_asn1_get_tag(cp, end, &len, MBEDTLS_ASN1_INTEGER)) {
    8552:	2302      	movs	r3, #2
    8554:	aa01      	add	r2, sp, #4
    8556:	4620      	mov	r0, r4
    8558:	f000 fa3a 	bl	89d0 <mbedtls_asn1_get_tag>
    855c:	4605      	mov	r5, r0
    855e:	b9e8      	cbnz	r0, 859c <bootutil_read_bigint+0x52>
    if (len >= NUM_ECC_BYTES) {
    8560:	9a01      	ldr	r2, [sp, #4]
    8562:	2a1f      	cmp	r2, #31
    8564:	d90e      	bls.n	8584 <bootutil_read_bigint+0x3a>
        memcpy(i, *cp + len - NUM_ECC_BYTES, NUM_ECC_BYTES);
    8566:	6823      	ldr	r3, [r4, #0]
    8568:	f1a2 0120 	sub.w	r1, r2, #32
    856c:	4419      	add	r1, r3
    856e:	2220      	movs	r2, #32
    8570:	4630      	mov	r0, r6
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    8572:	f000 fc60 	bl	8e36 <memcpy>
    *cp += len;
    8576:	6823      	ldr	r3, [r4, #0]
    8578:	9a01      	ldr	r2, [sp, #4]
    857a:	4413      	add	r3, r2
    857c:	6023      	str	r3, [r4, #0]
}
    857e:	4628      	mov	r0, r5
    8580:	b002      	add	sp, #8
    8582:	bd70      	pop	{r4, r5, r6, pc}
        memset(i, 0, NUM_ECC_BYTES - len);
    8584:	4601      	mov	r1, r0
    8586:	f1c2 0220 	rsb	r2, r2, #32
    858a:	4630      	mov	r0, r6
    858c:	f000 fc5e 	bl	8e4c <memset>
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    8590:	9a01      	ldr	r2, [sp, #4]
    8592:	6821      	ldr	r1, [r4, #0]
    8594:	f1c2 0020 	rsb	r0, r2, #32
    8598:	4430      	add	r0, r6
    859a:	e7ea      	b.n	8572 <bootutil_read_bigint+0x28>
        return -3;
    859c:	f06f 0502 	mvn.w	r5, #2
    85a0:	e7ed      	b.n	857e <bootutil_read_bigint+0x34>

000085a2 <boot_fih_memequal>:
    return memcmp(s1, s2, n);
    85a2:	f000 bc38 	b.w	8e16 <memcmp>

000085a6 <boot_trailer_sz>:
    return BOOT_STATUS_MAX_ENTRIES * boot_status_entry_sz(min_write_sz);
    85a6:	f44f 7340 	mov.w	r3, #768	; 0x300
    85aa:	4358      	muls	r0, r3
}
    85ac:	3030      	adds	r0, #48	; 0x30
    85ae:	4770      	bx	lr

000085b0 <boot_status_entries>:
    if (flash_area_get_id(fap) == FLASH_AREA_IMAGE_PRIMARY(image_index) ||
    85b0:	780b      	ldrb	r3, [r1, #0]
    85b2:	f003 03fd 	and.w	r3, r3, #253	; 0xfd
    return -1;
    85b6:	2b01      	cmp	r3, #1
}
    85b8:	bf0c      	ite	eq
    85ba:	f44f 7040 	moveq.w	r0, #768	; 0x300
    85be:	f04f 30ff 	movne.w	r0, #4294967295
    85c2:	4770      	bx	lr

000085c4 <boot_status_off>:
{
    85c4:	b510      	push	{r4, lr}
    85c6:	4604      	mov	r4, r0
    elem_sz = flash_area_align(fap);
    85c8:	f000 fbd1 	bl	8d6e <flash_area_align>
    return flash_area_get_size(fap) - off_from_end;
    85cc:	68a3      	ldr	r3, [r4, #8]
}
    85ce:	f44f 7240 	mov.w	r2, #768	; 0x300
    return flash_area_get_size(fap) - off_from_end;
    85d2:	3b30      	subs	r3, #48	; 0x30
}
    85d4:	fb02 3010 	mls	r0, r2, r0, r3
    85d8:	bd10      	pop	{r4, pc}

000085da <boot_write_copy_done>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    85da:	6881      	ldr	r1, [r0, #8]
    85dc:	3918      	subs	r1, #24
    85de:	f021 0107 	bic.w	r1, r1, #7
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    85e2:	2201      	movs	r2, #1
    85e4:	3908      	subs	r1, #8
    85e6:	f001 b8a1 	b.w	972c <boot_write_trailer_flag>

000085ea <boot_write_swap_size>:
{
    85ea:	b513      	push	{r0, r1, r4, lr}
    85ec:	4604      	mov	r4, r0
    85ee:	9101      	str	r1, [sp, #4]
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
    85f0:	f001 f82d 	bl	964e <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_size, 4);
    85f4:	2304      	movs	r3, #4
    85f6:	f1a0 0108 	sub.w	r1, r0, #8
    85fa:	eb0d 0203 	add.w	r2, sp, r3
    85fe:	4620      	mov	r0, r4
    8600:	f001 f868 	bl	96d4 <boot_write_trailer>
}
    8604:	b002      	add	sp, #8
    8606:	bd10      	pop	{r4, pc}

00008608 <boot_read_image_headers>:
{
    8608:	b570      	push	{r4, r5, r6, lr}
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    860a:	4613      	mov	r3, r2
{
    860c:	460e      	mov	r6, r1
    860e:	4615      	mov	r5, r2
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    8610:	2100      	movs	r1, #0
    8612:	4602      	mov	r2, r0
{
    8614:	4604      	mov	r4, r0
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    8616:	f7f8 fb75 	bl	d04 <boot_read_image_header>
        if (rc != 0) {
    861a:	b950      	cbnz	r0, 8632 <boot_read_image_headers+0x2a>
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    861c:	462b      	mov	r3, r5
    861e:	f104 022c 	add.w	r2, r4, #44	; 0x2c
    8622:	2101      	movs	r1, #1
    8624:	4620      	mov	r0, r4
    8626:	f7f8 fb6d 	bl	d04 <boot_read_image_header>
        if (rc != 0) {
    862a:	b110      	cbz	r0, 8632 <boot_read_image_headers+0x2a>
                return 0;
    862c:	2e00      	cmp	r6, #0
    862e:	bf08      	it	eq
    8630:	2000      	moveq	r0, #0
}
    8632:	bd70      	pop	{r4, r5, r6, pc}

00008634 <boot_read_image_size.constprop.0.isra.0>:
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    8634:	b573      	push	{r0, r1, r4, r5, r6, lr}
    8636:	4604      	mov	r4, r0
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    8638:	2000      	movs	r0, #0
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    863a:	460d      	mov	r5, r1
    863c:	4616      	mov	r6, r2
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    863e:	f7ff fedd 	bl	83fc <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
    8642:	4669      	mov	r1, sp
    8644:	b2c0      	uxtb	r0, r0
    8646:	f7f9 f9c7 	bl	19d8 <flash_area_open>
    if (rc != 0) {
    864a:	bb30      	cbnz	r0, 869a <boot_read_image_size.constprop.0.isra.0+0x66>
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    864c:	232c      	movs	r3, #44	; 0x2c
    864e:	fb03 4405 	mla	r4, r3, r5, r4
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    8652:	9800      	ldr	r0, [sp, #0]
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    8654:	68e3      	ldr	r3, [r4, #12]
    8656:	8925      	ldrh	r5, [r4, #8]
    8658:	441d      	add	r5, r3
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    865a:	2304      	movs	r3, #4
    865c:	eb0d 0203 	add.w	r2, sp, r3
    8660:	4629      	mov	r1, r5
    8662:	f000 fb44 	bl	8cee <flash_area_read>
    8666:	b9c0      	cbnz	r0, 869a <boot_read_image_size.constprop.0.isra.0+0x66>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    8668:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    protect_tlv_size = boot_img_hdr(state, slot)->ih_protect_tlv_size;
    866c:	8964      	ldrh	r4, [r4, #10]
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    866e:	9800      	ldr	r0, [sp, #0]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    8670:	f646 1308 	movw	r3, #26888	; 0x6908
    8674:	429a      	cmp	r2, r3
    8676:	d115      	bne.n	86a4 <boot_read_image_size.constprop.0.isra.0+0x70>
        if (protect_tlv_size != info.it_tlv_tot) {
    8678:	f8bd 3006 	ldrh.w	r3, [sp, #6]
    867c:	429c      	cmp	r4, r3
    867e:	d10c      	bne.n	869a <boot_read_image_size.constprop.0.isra.0+0x66>
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    8680:	2304      	movs	r3, #4
    8682:	eb0d 0203 	add.w	r2, sp, r3
    8686:	1961      	adds	r1, r4, r5
    8688:	f000 fb31 	bl	8cee <flash_area_read>
    868c:	b928      	cbnz	r0, 869a <boot_read_image_size.constprop.0.isra.0+0x66>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    868e:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    8692:	f646 1307 	movw	r3, #26887	; 0x6907
    8696:	429a      	cmp	r2, r3
    8698:	d007      	beq.n	86aa <boot_read_image_size.constprop.0.isra.0+0x76>
    flash_area_close(fap);
    869a:	9800      	ldr	r0, [sp, #0]
    869c:	f000 fb26 	bl	8cec <flash_area_close>
}
    86a0:	b002      	add	sp, #8
    86a2:	bd70      	pop	{r4, r5, r6, pc}
    } else if (protect_tlv_size != 0) {
    86a4:	2c00      	cmp	r4, #0
    86a6:	d0f2      	beq.n	868e <boot_read_image_size.constprop.0.isra.0+0x5a>
    86a8:	e7f7      	b.n	869a <boot_read_image_size.constprop.0.isra.0+0x66>
    *size = off + protect_tlv_size + info.it_tlv_tot;
    86aa:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    86ae:	4421      	add	r1, r4
    86b0:	4429      	add	r1, r5
    86b2:	6031      	str	r1, [r6, #0]
    rc = 0;
    86b4:	e7f1      	b.n	869a <boot_read_image_size.constprop.0.isra.0+0x66>

000086b6 <boot_read_sectors>:
{
    86b6:	b537      	push	{r0, r1, r2, r4, r5, lr}
    86b8:	4604      	mov	r4, r0
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    86ba:	6a42      	ldr	r2, [r0, #36]	; 0x24
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    86bc:	f44f 7580 	mov.w	r5, #256	; 0x100
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    86c0:	a901      	add	r1, sp, #4
    86c2:	2003      	movs	r0, #3
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    86c4:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    86c6:	f7f9 f9af 	bl	1a28 <flash_area_get_sectors>
    if (rc != 0) {
    86ca:	b958      	cbnz	r0, 86e4 <boot_read_sectors+0x2e>
    *out_num_sectors = num_sectors;
    86cc:	9b01      	ldr	r3, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    86ce:	6d22      	ldr	r2, [r4, #80]	; 0x50
    *out_num_sectors = num_sectors;
    86d0:	62a3      	str	r3, [r4, #40]	; 0x28
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    86d2:	a901      	add	r1, sp, #4
    86d4:	2001      	movs	r0, #1
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    86d6:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    86d8:	f7f9 f9a6 	bl	1a28 <flash_area_get_sectors>
    if (rc != 0) {
    86dc:	4605      	mov	r5, r0
    86de:	b128      	cbz	r0, 86ec <boot_read_sectors+0x36>
        return BOOT_EFLASH_SEC;
    86e0:	2509      	movs	r5, #9
    86e2:	e000      	b.n	86e6 <boot_read_sectors+0x30>
        return BOOT_EFLASH;
    86e4:	2501      	movs	r5, #1
}
    86e6:	4628      	mov	r0, r5
    86e8:	b003      	add	sp, #12
    86ea:	bd30      	pop	{r4, r5, pc}
    *out_num_sectors = num_sectors;
    86ec:	9b01      	ldr	r3, [sp, #4]
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    86ee:	6a20      	ldr	r0, [r4, #32]
    *out_num_sectors = num_sectors;
    86f0:	6563      	str	r3, [r4, #84]	; 0x54
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    86f2:	f000 fb3c 	bl	8d6e <flash_area_align>
    BOOT_WRITE_SZ(state) = boot_write_sz(state);
    86f6:	65e0      	str	r0, [r4, #92]	; 0x5c
    return 0;
    86f8:	e7f5      	b.n	86e6 <boot_read_sectors+0x30>

000086fa <boot_status_reset>:
    bs->idx = BOOT_STATUS_IDX_0;
    86fa:	2301      	movs	r3, #1
    86fc:	6003      	str	r3, [r0, #0]
    bs->state = BOOT_STATUS_STATE_0;
    86fe:	f103 2301 	add.w	r3, r3, #16777472	; 0x1000100
    8702:	6043      	str	r3, [r0, #4]
    bs->swap_size = 0;
    8704:	2300      	movs	r3, #0
    bs->source = 0;
    8706:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    870a:	4770      	bx	lr

0000870c <boot_status_is_reset>:
            bs->idx == BOOT_STATUS_IDX_0 &&
    870c:	7943      	ldrb	r3, [r0, #5]
    870e:	2b01      	cmp	r3, #1
    8710:	d107      	bne.n	8722 <boot_status_is_reset+0x16>
    return (bs->op == BOOT_STATUS_OP_MOVE &&
    8712:	6803      	ldr	r3, [r0, #0]
    8714:	2b01      	cmp	r3, #1
    8716:	d104      	bne.n	8722 <boot_status_is_reset+0x16>
            bs->idx == BOOT_STATUS_IDX_0 &&
    8718:	7900      	ldrb	r0, [r0, #4]
    871a:	1e43      	subs	r3, r0, #1
    871c:	4258      	negs	r0, r3
    871e:	4158      	adcs	r0, r3
    8720:	4770      	bx	lr
    8722:	2000      	movs	r0, #0
}
    8724:	4770      	bx	lr

00008726 <boot_write_status>:
{
    8726:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    8728:	4606      	mov	r6, r0
    872a:	460d      	mov	r5, r1
    rc = flash_area_open(area_id, &fap);
    872c:	2003      	movs	r0, #3
    872e:	a901      	add	r1, sp, #4
    8730:	f7f9 f952 	bl	19d8 <flash_area_open>
    if (rc != 0) {
    8734:	bb38      	cbnz	r0, 8786 <boot_write_status+0x60>
    off = boot_status_off(fap) +
    8736:	9801      	ldr	r0, [sp, #4]
    8738:	f7ff ff44 	bl	85c4 <boot_status_off>
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    873c:	6df1      	ldr	r1, [r6, #92]	; 0x5c
    off = boot_status_off(fap) +
    873e:	4604      	mov	r4, r0
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    8740:	4628      	mov	r0, r5
    8742:	f000 f8e6 	bl	8912 <boot_status_internal_off>
    off = boot_status_off(fap) +
    8746:	4404      	add	r4, r0
    align = flash_area_align(fap);
    8748:	9801      	ldr	r0, [sp, #4]
    874a:	f000 fb10 	bl	8d6e <flash_area_align>
    874e:	4606      	mov	r6, r0
    erased_val = flash_area_erased_val(fap);
    8750:	9801      	ldr	r0, [sp, #4]
    8752:	f000 fb13 	bl	8d7c <flash_area_erased_val>
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    8756:	2208      	movs	r2, #8
    erased_val = flash_area_erased_val(fap);
    8758:	4601      	mov	r1, r0
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    875a:	eb0d 0002 	add.w	r0, sp, r2
    875e:	f000 fb75 	bl	8e4c <memset>
    buf[0] = bs->state;
    8762:	792b      	ldrb	r3, [r5, #4]
    8764:	f88d 3008 	strb.w	r3, [sp, #8]
    rc = flash_area_write(fap, off, buf, align);
    8768:	4621      	mov	r1, r4
    876a:	9801      	ldr	r0, [sp, #4]
    876c:	4633      	mov	r3, r6
    876e:	aa02      	add	r2, sp, #8
    8770:	f000 fad2 	bl	8d18 <flash_area_write>
    if (rc != 0) {
    8774:	1e04      	subs	r4, r0, #0
    flash_area_close(fap);
    8776:	9801      	ldr	r0, [sp, #4]
    if (rc != 0) {
    8778:	bf18      	it	ne
    877a:	2401      	movne	r4, #1
    flash_area_close(fap);
    877c:	f000 fab6 	bl	8cec <flash_area_close>
}
    8780:	4620      	mov	r0, r4
    8782:	b004      	add	sp, #16
    8784:	bd70      	pop	{r4, r5, r6, pc}
        return BOOT_EFLASH;
    8786:	2401      	movs	r4, #1
    8788:	e7fa      	b.n	8780 <boot_write_status+0x5a>

0000878a <boot_erase_region>:
    return flash_area_erase(fap, off, sz);
    878a:	f000 bada 	b.w	8d42 <flash_area_erase>

0000878e <swap_erase_trailer_sectors>:

#if defined(MCUBOOT_SWAP_USING_SCRATCH) || defined(MCUBOOT_SWAP_USING_MOVE)
int
swap_erase_trailer_sectors(const struct boot_loader_state *state,
                           const struct flash_area *fap)
{
    878e:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    8792:	460e      	mov	r6, r1
    int rc;

    BOOT_LOG_DBG("erasing trailer; fa_id=%d", flash_area_get_id(fap));

    image_index = BOOT_CURR_IMG(state);
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    8794:	2100      	movs	r1, #0
{
    8796:	4607      	mov	r7, r0
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    8798:	4608      	mov	r0, r1
    879a:	f7ff fe2f 	bl	83fc <flash_area_id_from_multi_image_slot>
            BOOT_PRIMARY_SLOT);
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    879e:	2101      	movs	r1, #1
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    87a0:	4604      	mov	r4, r0
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    87a2:	2000      	movs	r0, #0
    87a4:	f7ff fe2a 	bl	83fc <flash_area_id_from_multi_image_slot>
            BOOT_SECONDARY_SLOT);

    if (flash_area_get_id(fap) == fa_id_primary) {
    87a8:	7833      	ldrb	r3, [r6, #0]
    87aa:	429c      	cmp	r4, r3
    87ac:	d021      	beq.n	87f2 <swap_erase_trailer_sectors+0x64>
        slot = BOOT_PRIMARY_SLOT;
    } else if (flash_area_get_id(fap) == fa_id_secondary) {
    87ae:	4298      	cmp	r0, r3
    87b0:	d121      	bne.n	87f6 <swap_erase_trailer_sectors+0x68>
        slot = BOOT_SECONDARY_SLOT;
    87b2:	2501      	movs	r5, #1
    return BOOT_IMG(state, slot).num_sectors;
    87b4:	232c      	movs	r3, #44	; 0x2c
    87b6:	fb03 7505 	mla	r5, r3, r5, r7
        return BOOT_EFLASH;
    }

    /* delete starting from last sector and moving to beginning */
    sector = boot_img_num_sectors(state, slot) - 1;
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    87ba:	6df8      	ldr	r0, [r7, #92]	; 0x5c
    sector = boot_img_num_sectors(state, slot) - 1;
    87bc:	6aac      	ldr	r4, [r5, #40]	; 0x28
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    87be:	f7ff fef2 	bl	85a6 <boot_trailer_sz>
    sector = boot_img_num_sectors(state, slot) - 1;
    87c2:	3c01      	subs	r4, #1
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    87c4:	4607      	mov	r7, r0
    total_sz = 0;
    87c6:	f04f 0800 	mov.w	r8, #0
    return flash_sector_get_size(&BOOT_IMG(state, slot).sectors[sector]);
    87ca:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    87cc:	eb03 02c4 	add.w	r2, r3, r4, lsl #3
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    87d0:	f853 1034 	ldr.w	r1, [r3, r4, lsl #3]
	return fs->fs_size;
    87d4:	f8d2 9004 	ldr.w	r9, [r2, #4]
    87d8:	681b      	ldr	r3, [r3, #0]
    do {
        sz = boot_img_sector_size(state, slot, sector);
        off = boot_img_sector_off(state, slot, sector);
        rc = boot_erase_region(fap, off, sz);
    87da:	464a      	mov	r2, r9
    87dc:	1ac9      	subs	r1, r1, r3
    87de:	4630      	mov	r0, r6
        assert(rc == 0);

        sector--;
        total_sz += sz;
    87e0:	44c8      	add	r8, r9
        rc = boot_erase_region(fap, off, sz);
    87e2:	f7ff ffd2 	bl	878a <boot_erase_region>
    } while (total_sz < trailer_sz);
    87e6:	45b8      	cmp	r8, r7
        sector--;
    87e8:	f104 34ff 	add.w	r4, r4, #4294967295
    } while (total_sz < trailer_sz);
    87ec:	d3ed      	bcc.n	87ca <swap_erase_trailer_sectors+0x3c>

    return rc;
}
    87ee:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        slot = BOOT_PRIMARY_SLOT;
    87f2:	2500      	movs	r5, #0
    87f4:	e7de      	b.n	87b4 <swap_erase_trailer_sectors+0x26>
        return BOOT_EFLASH;
    87f6:	2001      	movs	r0, #1
    87f8:	e7f9      	b.n	87ee <swap_erase_trailer_sectors+0x60>

000087fa <swap_status_init>:

int
swap_status_init(const struct boot_loader_state *state,
                 const struct flash_area *fap,
                 const struct boot_status *bs)
{
    87fa:	b537      	push	{r0, r1, r2, r4, r5, lr}
    87fc:	4615      	mov	r5, r2
    87fe:	460c      	mov	r4, r1

    image_index = BOOT_CURR_IMG(state);

    BOOT_LOG_DBG("initializing status; fa_id=%d", flash_area_get_id(fap));

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    8800:	2001      	movs	r0, #1
    8802:	4669      	mov	r1, sp
    8804:	f000 ffa9 	bl	975a <boot_read_swap_state_by_id>
            &swap_state);
    assert(rc == 0);

    if (bs->swap_type != BOOT_SWAP_TYPE_NONE) {
    8808:	79e9      	ldrb	r1, [r5, #7]
    880a:	2901      	cmp	r1, #1
    880c:	d003      	beq.n	8816 <swap_status_init+0x1c>
        rc = boot_write_swap_info(fap, bs->swap_type, image_index);
    880e:	2200      	movs	r2, #0
    8810:	4620      	mov	r0, r4
    8812:	f000 ffb6 	bl	9782 <boot_write_swap_info>
        assert(rc == 0);
    }

    if (swap_state.image_ok == BOOT_FLAG_SET) {
    8816:	f89d 3003 	ldrb.w	r3, [sp, #3]
    881a:	2b01      	cmp	r3, #1
    881c:	d102      	bne.n	8824 <swap_status_init+0x2a>
        rc = boot_write_image_ok(fap);
    881e:	4620      	mov	r0, r4
    8820:	f000 ff8e 	bl	9740 <boot_write_image_ok>
        assert(rc == 0);
    }

    rc = boot_write_swap_size(fap, bs->swap_size);
    8824:	68a9      	ldr	r1, [r5, #8]
    8826:	4620      	mov	r0, r4
    8828:	f7ff fedf 	bl	85ea <boot_write_swap_size>

    rc = boot_write_enc_key(fap, 1, bs);
    assert(rc == 0);
#endif

    rc = boot_write_magic(fap);
    882c:	4620      	mov	r0, r4
    882e:	f7fb ffc9 	bl	47c4 <boot_write_magic>
    assert(rc == 0);

    return 0;
}
    8832:	2000      	movs	r0, #0
    8834:	b003      	add	sp, #12
    8836:	bd30      	pop	{r4, r5, pc}

00008838 <swap_read_status>:

int
swap_read_status(struct boot_loader_state *state, struct boot_status *bs)
{
    8838:	b573      	push	{r0, r1, r4, r5, r6, lr}
    883a:	460d      	mov	r5, r1
    883c:	4606      	mov	r6, r0
    uint32_t off;
    uint8_t swap_info;
    int area_id;
    int rc;

    bs->source = swap_status_source(state);
    883e:	f7f8 fb4b 	bl	ed8 <swap_status_source>
    8842:	4604      	mov	r4, r0
    8844:	60e8      	str	r0, [r5, #12]
    switch (bs->source) {
    8846:	b358      	cbz	r0, 88a0 <swap_read_status+0x68>
    8848:	2802      	cmp	r0, #2
    884a:	d12e      	bne.n	88aa <swap_read_status+0x72>
    default:
        assert(0);
        return BOOT_EBADARGS;
    }

    rc = flash_area_open(area_id, &fap);
    884c:	a901      	add	r1, sp, #4
    884e:	2003      	movs	r0, #3
    8850:	f7f9 f8c2 	bl	19d8 <flash_area_open>
    if (rc != 0) {
    8854:	bb58      	cbnz	r0, 88ae <swap_read_status+0x76>
        return BOOT_EFLASH;
    }

    rc = swap_read_status_bytes(fap, state, bs);
    8856:	9801      	ldr	r0, [sp, #4]
    8858:	462a      	mov	r2, r5
    885a:	4631      	mov	r1, r6
    885c:	f7f8 faa0 	bl	da0 <swap_read_status_bytes>
    if (rc == 0) {
    8860:	4604      	mov	r4, r0
    8862:	b9d0      	cbnz	r0, 889a <swap_read_status+0x62>
        off = boot_swap_info_off(fap);
    8864:	9801      	ldr	r0, [sp, #4]
    8866:	f000 fef2 	bl	964e <boot_swap_info_off>
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    886a:	2301      	movs	r3, #1
        off = boot_swap_info_off(fap);
    886c:	4601      	mov	r1, r0
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    886e:	f10d 0203 	add.w	r2, sp, #3
    8872:	9801      	ldr	r0, [sp, #4]
    8874:	f000 fa3b 	bl	8cee <flash_area_read>
        if (rc != 0) {
    8878:	4604      	mov	r4, r0
    887a:	b9a0      	cbnz	r0, 88a6 <swap_read_status+0x6e>
            rc = BOOT_EFLASH;
            goto done;
        }

        if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info)) {
    887c:	9801      	ldr	r0, [sp, #4]
    887e:	2201      	movs	r2, #1
    8880:	f10d 0103 	add.w	r1, sp, #3
    8884:	f000 fef7 	bl	9676 <bootutil_buffer_is_erased>
    8888:	b110      	cbz	r0, 8890 <swap_read_status+0x58>
            BOOT_SET_SWAP_INFO(swap_info, 0, BOOT_SWAP_TYPE_NONE);
    888a:	2301      	movs	r3, #1
    888c:	f88d 3003 	strb.w	r3, [sp, #3]
            rc = 0;
        }

        /* Extract the swap type info */
        bs->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    8890:	f89d 3003 	ldrb.w	r3, [sp, #3]
    8894:	f003 030f 	and.w	r3, r3, #15
    8898:	71eb      	strb	r3, [r5, #7]
    }

done:
    flash_area_close(fap);
    889a:	9801      	ldr	r0, [sp, #4]
    889c:	f000 fa26 	bl	8cec <flash_area_close>

    return rc;
}
    88a0:	4620      	mov	r0, r4
    88a2:	b002      	add	sp, #8
    88a4:	bd70      	pop	{r4, r5, r6, pc}
            rc = BOOT_EFLASH;
    88a6:	2401      	movs	r4, #1
    88a8:	e7f7      	b.n	889a <swap_read_status+0x62>
    switch (bs->source) {
    88aa:	2407      	movs	r4, #7
    88ac:	e7f8      	b.n	88a0 <swap_read_status+0x68>
        return BOOT_EFLASH;
    88ae:	2401      	movs	r4, #1
    88b0:	e7f6      	b.n	88a0 <swap_read_status+0x68>

000088b2 <swap_set_copy_done>:

int
swap_set_copy_done(uint8_t image_index)
{
    88b2:	b513      	push	{r0, r1, r4, lr}
    const struct flash_area *fap;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    88b4:	2003      	movs	r0, #3
    88b6:	a901      	add	r1, sp, #4
    88b8:	f7f9 f88e 	bl	19d8 <flash_area_open>
            &fap);
    if (rc != 0) {
    88bc:	b948      	cbnz	r0, 88d2 <swap_set_copy_done+0x20>
        return BOOT_EFLASH;
    }

    rc = boot_write_copy_done(fap);
    88be:	9801      	ldr	r0, [sp, #4]
    88c0:	f7ff fe8b 	bl	85da <boot_write_copy_done>
    88c4:	4604      	mov	r4, r0
    flash_area_close(fap);
    88c6:	9801      	ldr	r0, [sp, #4]
    88c8:	f000 fa10 	bl	8cec <flash_area_close>
    return rc;
}
    88cc:	4620      	mov	r0, r4
    88ce:	b002      	add	sp, #8
    88d0:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    88d2:	2401      	movs	r4, #1
    88d4:	e7fa      	b.n	88cc <swap_set_copy_done+0x1a>

000088d6 <swap_set_image_ok>:

int
swap_set_image_ok(uint8_t image_index)
{
    88d6:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    const struct flash_area *fap;
    struct boot_swap_state state;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    88d8:	2003      	movs	r0, #3
    88da:	a901      	add	r1, sp, #4
    88dc:	f7f9 f87c 	bl	19d8 <flash_area_open>
            &fap);
    if (rc != 0) {
    88e0:	b9a8      	cbnz	r0, 890e <swap_set_image_ok+0x38>
        return BOOT_EFLASH;
    }

    rc = boot_read_swap_state(fap, &state);
    88e2:	9801      	ldr	r0, [sp, #4]
    88e4:	a902      	add	r1, sp, #8
    88e6:	f7fb ff8d 	bl	4804 <boot_read_swap_state>
    if (rc != 0) {
    88ea:	4604      	mov	r4, r0
    88ec:	b968      	cbnz	r0, 890a <swap_set_image_ok+0x34>
        rc = BOOT_EFLASH;
        goto out;
    }

    if (state.image_ok == BOOT_FLAG_UNSET) {
    88ee:	f89d 300b 	ldrb.w	r3, [sp, #11]
    88f2:	2b03      	cmp	r3, #3
    88f4:	d103      	bne.n	88fe <swap_set_image_ok+0x28>
        rc = boot_write_image_ok(fap);
    88f6:	9801      	ldr	r0, [sp, #4]
    88f8:	f000 ff22 	bl	9740 <boot_write_image_ok>
    88fc:	4604      	mov	r4, r0
    }

out:
    flash_area_close(fap);
    88fe:	9801      	ldr	r0, [sp, #4]
    8900:	f000 f9f4 	bl	8cec <flash_area_close>
    return rc;
}
    8904:	4620      	mov	r0, r4
    8906:	b004      	add	sp, #16
    8908:	bd10      	pop	{r4, pc}
        rc = BOOT_EFLASH;
    890a:	2401      	movs	r4, #1
    890c:	e7f7      	b.n	88fe <swap_set_image_ok+0x28>
        return BOOT_EFLASH;
    890e:	2401      	movs	r4, #1
    8910:	e7f8      	b.n	8904 <swap_set_image_ok+0x2e>

00008912 <boot_status_internal_off>:
{
    8912:	b510      	push	{r4, lr}
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    8914:	7943      	ldrb	r3, [r0, #5]
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    8916:	7902      	ldrb	r2, [r0, #4]
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    8918:	2b01      	cmp	r3, #1
               0 : (BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT * elem_sz)) +
    891a:	bf14      	ite	ne
    891c:	020b      	lslne	r3, r1, #8
    891e:	2300      	moveq	r3, #0
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    8920:	f102 32ff 	add.w	r2, r2, #4294967295
    off = ((bs->op == BOOT_STATUS_OP_MOVE) ?
    8924:	fb01 3302 	mla	r3, r1, r2, r3
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    8928:	6802      	ldr	r2, [r0, #0]
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    892a:	bf14      	ite	ne
    892c:	004c      	lslne	r4, r1, #1
    892e:	460c      	moveq	r4, r1
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    8930:	3a01      	subs	r2, #1
}
    8932:	fb04 3002 	mla	r0, r4, r2, r3
    8936:	bd10      	pop	{r4, pc}

00008938 <mbedtls_asn1_get_len>:
 * ASN.1 DER decoding routines
 */
int mbedtls_asn1_get_len( unsigned char **p,
                  const unsigned char *end,
                  size_t *len )
{
    8938:	b570      	push	{r4, r5, r6, lr}
    if( ( end - *p ) < 1 )
    893a:	6803      	ldr	r3, [r0, #0]
    893c:	1acd      	subs	r5, r1, r3
    893e:	2d00      	cmp	r5, #0
    8940:	dc02      	bgt.n	8948 <mbedtls_asn1_get_len+0x10>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    8942:	f06f 005f 	mvn.w	r0, #95	; 0x5f

    if( *len > (size_t) ( end - *p ) )
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    return( 0 );
}
    8946:	bd70      	pop	{r4, r5, r6, pc}
    if( ( **p & 0x80 ) == 0 )
    8948:	f993 6000 	ldrsb.w	r6, [r3]
    894c:	781c      	ldrb	r4, [r3, #0]
    894e:	2e00      	cmp	r6, #0
    8950:	db0a      	blt.n	8968 <mbedtls_asn1_get_len+0x30>
        *len = *(*p)++;
    8952:	1c5c      	adds	r4, r3, #1
    8954:	6004      	str	r4, [r0, #0]
    8956:	781b      	ldrb	r3, [r3, #0]
    8958:	6013      	str	r3, [r2, #0]
    if( *len > (size_t) ( end - *p ) )
    895a:	6803      	ldr	r3, [r0, #0]
    895c:	1ac9      	subs	r1, r1, r3
    895e:	6813      	ldr	r3, [r2, #0]
    8960:	428b      	cmp	r3, r1
    8962:	d8ee      	bhi.n	8942 <mbedtls_asn1_get_len+0xa>
    return( 0 );
    8964:	2000      	movs	r0, #0
    8966:	e7ee      	b.n	8946 <mbedtls_asn1_get_len+0xe>
        switch( **p & 0x7F )
    8968:	f004 047f 	and.w	r4, r4, #127	; 0x7f
    896c:	3c01      	subs	r4, #1
    896e:	2c03      	cmp	r4, #3
    8970:	d82b      	bhi.n	89ca <mbedtls_asn1_get_len+0x92>
    8972:	e8df f004 	tbb	[pc, r4]
    8976:	0a02      	.short	0x0a02
    8978:	2114      	.short	0x2114
            if( ( end - *p ) < 2 )
    897a:	2d01      	cmp	r5, #1
    897c:	d0e1      	beq.n	8942 <mbedtls_asn1_get_len+0xa>
            *len = (*p)[1];
    897e:	785b      	ldrb	r3, [r3, #1]
    8980:	6013      	str	r3, [r2, #0]
            (*p) += 2;
    8982:	6803      	ldr	r3, [r0, #0]
    8984:	3302      	adds	r3, #2
            (*p) += 5;
    8986:	6003      	str	r3, [r0, #0]
            break;
    8988:	e7e7      	b.n	895a <mbedtls_asn1_get_len+0x22>
            if( ( end - *p ) < 3 )
    898a:	2d02      	cmp	r5, #2
    898c:	ddd9      	ble.n	8942 <mbedtls_asn1_get_len+0xa>
            *len = ( (size_t)(*p)[1] << 8 ) | (*p)[2];
    898e:	f8b3 3001 	ldrh.w	r3, [r3, #1]
    8992:	ba5b      	rev16	r3, r3
    8994:	b29b      	uxth	r3, r3
    8996:	6013      	str	r3, [r2, #0]
            (*p) += 3;
    8998:	6803      	ldr	r3, [r0, #0]
    899a:	3303      	adds	r3, #3
    899c:	e7f3      	b.n	8986 <mbedtls_asn1_get_len+0x4e>
            if( ( end - *p ) < 4 )
    899e:	2d03      	cmp	r5, #3
    89a0:	ddcf      	ble.n	8942 <mbedtls_asn1_get_len+0xa>
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    89a2:	789c      	ldrb	r4, [r3, #2]
            *len = ( (size_t)(*p)[1] << 16 ) |
    89a4:	785d      	ldrb	r5, [r3, #1]
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    89a6:	78db      	ldrb	r3, [r3, #3]
    89a8:	0224      	lsls	r4, r4, #8
            *len = ( (size_t)(*p)[1] << 16 ) |
    89aa:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    89ae:	4323      	orrs	r3, r4
            *len = ( (size_t)(*p)[1] << 16 ) |
    89b0:	6013      	str	r3, [r2, #0]
            (*p) += 4;
    89b2:	6803      	ldr	r3, [r0, #0]
    89b4:	3304      	adds	r3, #4
    89b6:	e7e6      	b.n	8986 <mbedtls_asn1_get_len+0x4e>
            if( ( end - *p ) < 5 )
    89b8:	2d04      	cmp	r5, #4
    89ba:	ddc2      	ble.n	8942 <mbedtls_asn1_get_len+0xa>
            *len = ( (size_t)(*p)[1] << 24 ) | ( (size_t)(*p)[2] << 16 ) |
    89bc:	f8d3 3001 	ldr.w	r3, [r3, #1]
    89c0:	ba1b      	rev	r3, r3
    89c2:	6013      	str	r3, [r2, #0]
            (*p) += 5;
    89c4:	6803      	ldr	r3, [r0, #0]
    89c6:	3305      	adds	r3, #5
    89c8:	e7dd      	b.n	8986 <mbedtls_asn1_get_len+0x4e>
        switch( **p & 0x7F )
    89ca:	f06f 0063 	mvn.w	r0, #99	; 0x63
    89ce:	e7ba      	b.n	8946 <mbedtls_asn1_get_len+0xe>

000089d0 <mbedtls_asn1_get_tag>:

int mbedtls_asn1_get_tag( unsigned char **p,
                  const unsigned char *end,
                  size_t *len, int tag )
{
    89d0:	b470      	push	{r4, r5, r6}
    if( ( end - *p ) < 1 )
    89d2:	6804      	ldr	r4, [r0, #0]
    89d4:	1b0e      	subs	r6, r1, r4
    89d6:	2e00      	cmp	r6, #0
    89d8:	dd07      	ble.n	89ea <mbedtls_asn1_get_tag+0x1a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( **p != tag )
    89da:	7826      	ldrb	r6, [r4, #0]
    89dc:	429e      	cmp	r6, r3
    89de:	d108      	bne.n	89f2 <mbedtls_asn1_get_tag+0x22>
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );

    (*p)++;
    89e0:	3401      	adds	r4, #1
    89e2:	6004      	str	r4, [r0, #0]

    return( mbedtls_asn1_get_len( p, end, len ) );
}
    89e4:	bc70      	pop	{r4, r5, r6}
    return( mbedtls_asn1_get_len( p, end, len ) );
    89e6:	f7ff bfa7 	b.w	8938 <mbedtls_asn1_get_len>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    89ea:	f06f 005f 	mvn.w	r0, #95	; 0x5f
}
    89ee:	bc70      	pop	{r4, r5, r6}
    89f0:	4770      	bx	lr
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );
    89f2:	f06f 0061 	mvn.w	r0, #97	; 0x61
    89f6:	e7fa      	b.n	89ee <mbedtls_asn1_get_tag+0x1e>

000089f8 <mbedtls_asn1_get_bitstring_null>:
/*
 * Get a bit string without unused bits
 */
int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end,
                             size_t *len )
{
    89f8:	b538      	push	{r3, r4, r5, lr}
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;

    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    89fa:	2303      	movs	r3, #3
{
    89fc:	4604      	mov	r4, r0
    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    89fe:	f7ff ffe7 	bl	89d0 <mbedtls_asn1_get_tag>
    8a02:	b918      	cbnz	r0, 8a0c <mbedtls_asn1_get_bitstring_null+0x14>
        return( ret );

    if( *len == 0 )
    8a04:	6813      	ldr	r3, [r2, #0]
    8a06:	b913      	cbnz	r3, 8a0e <mbedtls_asn1_get_bitstring_null+0x16>
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    8a08:	f06f 0067 	mvn.w	r0, #103	; 0x67
    if( **p != 0 )
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    ++( *p );

    return( 0 );
}
    8a0c:	bd38      	pop	{r3, r4, r5, pc}
    --( *len );
    8a0e:	3b01      	subs	r3, #1
    8a10:	6013      	str	r3, [r2, #0]
    if( **p != 0 )
    8a12:	6823      	ldr	r3, [r4, #0]
    8a14:	781a      	ldrb	r2, [r3, #0]
    8a16:	2a00      	cmp	r2, #0
    8a18:	d1f6      	bne.n	8a08 <mbedtls_asn1_get_bitstring_null+0x10>
    ++( *p );
    8a1a:	3301      	adds	r3, #1
    8a1c:	6023      	str	r3, [r4, #0]
    return( 0 );
    8a1e:	e7f5      	b.n	8a0c <mbedtls_asn1_get_bitstring_null+0x14>

00008a20 <mbedtls_asn1_get_alg>:
}

int mbedtls_asn1_get_alg( unsigned char **p,
                  const unsigned char *end,
                  mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params )
{
    8a20:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    8a24:	4690      	mov	r8, r2
    8a26:	461f      	mov	r7, r3
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
    size_t len;

    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    8a28:	aa01      	add	r2, sp, #4
    8a2a:	2330      	movs	r3, #48	; 0x30
{
    8a2c:	4605      	mov	r5, r0
    8a2e:	460e      	mov	r6, r1
    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    8a30:	f7ff ffce 	bl	89d0 <mbedtls_asn1_get_tag>
    8a34:	4604      	mov	r4, r0
    8a36:	b9f0      	cbnz	r0, 8a76 <mbedtls_asn1_get_alg+0x56>
            MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 )
        return( ret );

    if( ( end - *p ) < 1 )
    8a38:	682b      	ldr	r3, [r5, #0]
    8a3a:	1af6      	subs	r6, r6, r3
    8a3c:	2e00      	cmp	r6, #0
    8a3e:	dd34      	ble.n	8aaa <mbedtls_asn1_get_alg+0x8a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    alg->tag = **p;
    8a40:	4642      	mov	r2, r8
    8a42:	781b      	ldrb	r3, [r3, #0]
    8a44:	f842 3b04 	str.w	r3, [r2], #4
    end = *p + len;
    8a48:	9b01      	ldr	r3, [sp, #4]
    8a4a:	682e      	ldr	r6, [r5, #0]
    8a4c:	441e      	add	r6, r3

    if( ( ret = mbedtls_asn1_get_tag( p, end, &alg->len, MBEDTLS_ASN1_OID ) ) != 0 )
    8a4e:	4631      	mov	r1, r6
    8a50:	2306      	movs	r3, #6
    8a52:	4628      	mov	r0, r5
    8a54:	f7ff ffbc 	bl	89d0 <mbedtls_asn1_get_tag>
    8a58:	4604      	mov	r4, r0
    8a5a:	b960      	cbnz	r0, 8a76 <mbedtls_asn1_get_alg+0x56>
        return( ret );

    alg->p = *p;
    8a5c:	682b      	ldr	r3, [r5, #0]
    *p += alg->len;
    8a5e:	f8d8 2004 	ldr.w	r2, [r8, #4]
    alg->p = *p;
    8a62:	f8c8 3008 	str.w	r3, [r8, #8]
    *p += alg->len;
    8a66:	1899      	adds	r1, r3, r2

    if( *p == end )
    8a68:	42b1      	cmp	r1, r6
    *p += alg->len;
    8a6a:	6029      	str	r1, [r5, #0]
    if( *p == end )
    8a6c:	d107      	bne.n	8a7e <mbedtls_asn1_get_alg+0x5e>
    {
        mbedtls_platform_zeroize( params, sizeof(mbedtls_asn1_buf) );
    8a6e:	210c      	movs	r1, #12
    8a70:	4638      	mov	r0, r7
    8a72:	f7fe f9bd 	bl	6df0 <mbedtls_platform_zeroize>

    if( *p != end )
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );

    return( 0 );
}
    8a76:	4620      	mov	r0, r4
    8a78:	b002      	add	sp, #8
    8a7a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    params->tag = **p;
    8a7e:	5c9b      	ldrb	r3, [r3, r2]
    8a80:	463a      	mov	r2, r7
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    8a82:	4631      	mov	r1, r6
    params->tag = **p;
    8a84:	f842 3b04 	str.w	r3, [r2], #4
    (*p)++;
    8a88:	682b      	ldr	r3, [r5, #0]
    8a8a:	3301      	adds	r3, #1
    8a8c:	602b      	str	r3, [r5, #0]
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    8a8e:	4628      	mov	r0, r5
    8a90:	f7ff ff52 	bl	8938 <mbedtls_asn1_get_len>
    8a94:	b960      	cbnz	r0, 8ab0 <mbedtls_asn1_get_alg+0x90>
    params->p = *p;
    8a96:	682b      	ldr	r3, [r5, #0]
    *p += params->len;
    8a98:	687a      	ldr	r2, [r7, #4]
    params->p = *p;
    8a9a:	60bb      	str	r3, [r7, #8]
    *p += params->len;
    8a9c:	4413      	add	r3, r2
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    8a9e:	42b3      	cmp	r3, r6
    *p += params->len;
    8aa0:	602b      	str	r3, [r5, #0]
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    8aa2:	bf18      	it	ne
    8aa4:	f06f 0465 	mvnne.w	r4, #101	; 0x65
    8aa8:	e7e5      	b.n	8a76 <mbedtls_asn1_get_alg+0x56>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    8aaa:	f06f 045f 	mvn.w	r4, #95	; 0x5f
    8aae:	e7e2      	b.n	8a76 <mbedtls_asn1_get_alg+0x56>
    8ab0:	4604      	mov	r4, r0
    8ab2:	e7e0      	b.n	8a76 <mbedtls_asn1_get_alg+0x56>

00008ab4 <cc310_sha256_update>:
{
    8ab4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    8ab6:	f1b1 5f00 	cmp.w	r1, #536870912	; 0x20000000
{
    8aba:	af00      	add	r7, sp, #0
    8abc:	4605      	mov	r5, r0
    8abe:	4614      	mov	r4, r2
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    8ac0:	d210      	bcs.n	8ae4 <cc310_sha256_update+0x30>
        uint8_t stack_buffer[data_len];
    8ac2:	1dd3      	adds	r3, r2, #7
    8ac4:	f023 0307 	bic.w	r3, r3, #7
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    8ac8:	466e      	mov	r6, sp
        uint8_t stack_buffer[data_len];
    8aca:	ebad 0d03 	sub.w	sp, sp, r3
        memcpy(stack_buffer, data, block_len);
    8ace:	4668      	mov	r0, sp
    8ad0:	f000 f9b1 	bl	8e36 <memcpy>
        nrf_cc310_bl_hash_sha256_update(ctx, stack_buffer, block_len);
    8ad4:	4669      	mov	r1, sp
    8ad6:	4622      	mov	r2, r4
    8ad8:	4628      	mov	r0, r5
    8ada:	f7fe fbe9 	bl	72b0 <nrf_cc310_bl_hash_sha256_update>
    8ade:	46b5      	mov	sp, r6
};
    8ae0:	46bd      	mov	sp, r7
    8ae2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        nrf_cc310_bl_hash_sha256_update(ctx, data, data_len);
    8ae4:	f7fe fbe4 	bl	72b0 <nrf_cc310_bl_hash_sha256_update>
};
    8ae8:	e7fa      	b.n	8ae0 <cc310_sha256_update+0x2c>

00008aea <arch_printk_char_out>:
}
    8aea:	2000      	movs	r0, #0
    8aec:	4770      	bx	lr

00008aee <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    8aee:	b40f      	push	{r0, r1, r2, r3}
    8af0:	b507      	push	{r0, r1, r2, lr}
    8af2:	a904      	add	r1, sp, #16
    8af4:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    8af8:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    8afa:	f7f8 fc1b 	bl	1334 <vprintk>

	va_end(ap);
}
    8afe:	b003      	add	sp, #12
    8b00:	f85d eb04 	ldr.w	lr, [sp], #4
    8b04:	b004      	add	sp, #16
    8b06:	4770      	bx	lr

00008b08 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    8b08:	4604      	mov	r4, r0
    8b0a:	b508      	push	{r3, lr}
    8b0c:	4608      	mov	r0, r1
    8b0e:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    8b10:	461a      	mov	r2, r3
    8b12:	47a0      	blx	r4
	return z_impl_z_current_get();
    8b14:	f7fd feb4 	bl	6880 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    8b18:	f7f9 fe9e 	bl	2858 <z_impl_k_thread_abort>

00008b1c <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    8b1c:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    8b1e:	f013 0307 	ands.w	r3, r3, #7
    8b22:	d105      	bne.n	8b30 <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    8b24:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    8b26:	2b00      	cmp	r3, #0
    8b28:	bf0c      	ite	eq
    8b2a:	2000      	moveq	r0, #0
    8b2c:	2003      	movne	r0, #3
    8b2e:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    8b30:	2b02      	cmp	r3, #2
    8b32:	d105      	bne.n	8b40 <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    8b34:	8b40      	ldrh	r0, [r0, #26]
    8b36:	fab0 f080 	clz	r0, r0
    8b3a:	0940      	lsrs	r0, r0, #5
    8b3c:	0080      	lsls	r0, r0, #2
    8b3e:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    8b40:	2b01      	cmp	r3, #1
    8b42:	d105      	bne.n	8b50 <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    8b44:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    8b46:	2b00      	cmp	r3, #0
    8b48:	bf0c      	ite	eq
    8b4a:	2000      	moveq	r0, #0
    8b4c:	2005      	movne	r0, #5
    8b4e:	4770      	bx	lr
	int evt = EVT_NOP;
    8b50:	2000      	movs	r0, #0
}
    8b52:	4770      	bx	lr

00008b54 <validate_args>:
{
    8b54:	b510      	push	{r4, lr}
    8b56:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    8b58:	b100      	cbz	r0, 8b5c <validate_args+0x8>
    8b5a:	b911      	cbnz	r1, 8b62 <validate_args+0xe>
		return -EINVAL;
    8b5c:	f06f 0015 	mvn.w	r0, #21
}
    8b60:	bd10      	pop	{r4, pc}
	int rv = sys_notify_validate(&cli->notify);
    8b62:	1d08      	adds	r0, r1, #4
    8b64:	f000 f896 	bl	8c94 <sys_notify_validate>
	if ((rv == 0)
    8b68:	2800      	cmp	r0, #0
    8b6a:	d1f9      	bne.n	8b60 <validate_args+0xc>
	    && ((cli->notify.flags
    8b6c:	68a3      	ldr	r3, [r4, #8]
    8b6e:	2b03      	cmp	r3, #3
    8b70:	d9f6      	bls.n	8b60 <validate_args+0xc>
    8b72:	e7f3      	b.n	8b5c <validate_args+0x8>

00008b74 <notify_one>:
{
    8b74:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    8b78:	460d      	mov	r5, r1
    8b7a:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    8b7c:	4619      	mov	r1, r3
    8b7e:	1d28      	adds	r0, r5, #4
{
    8b80:	4690      	mov	r8, r2
    8b82:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    8b84:	f000 f897 	bl	8cb6 <sys_notify_finalize>
	if (cb) {
    8b88:	4604      	mov	r4, r0
    8b8a:	b138      	cbz	r0, 8b9c <notify_one+0x28>
		cb(mgr, cli, state, res);
    8b8c:	4633      	mov	r3, r6
    8b8e:	4642      	mov	r2, r8
    8b90:	4629      	mov	r1, r5
    8b92:	4638      	mov	r0, r7
    8b94:	46a4      	mov	ip, r4
}
    8b96:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    8b9a:	4760      	bx	ip
}
    8b9c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00008ba0 <transition_complete>:
{
    8ba0:	b410      	push	{r4}
	__asm__ volatile(
    8ba2:	f04f 0420 	mov.w	r4, #32
    8ba6:	f3ef 8211 	mrs	r2, BASEPRI
    8baa:	f384 8812 	msr	BASEPRI_MAX, r4
    8bae:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    8bb2:	6141      	str	r1, [r0, #20]
}
    8bb4:	f85d 4b04 	ldr.w	r4, [sp], #4
	process_event(mgr, EVT_COMPLETE, key);
    8bb8:	2101      	movs	r1, #1
    8bba:	f7f8 bbc9 	b.w	1350 <process_event>

00008bbe <onoff_manager_init>:
{
    8bbe:	b538      	push	{r3, r4, r5, lr}
    8bc0:	460c      	mov	r4, r1
	if ((mgr == NULL)
    8bc2:	4605      	mov	r5, r0
    8bc4:	b158      	cbz	r0, 8bde <onoff_manager_init+0x20>
	    || (transitions == NULL)
    8bc6:	b151      	cbz	r1, 8bde <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    8bc8:	680b      	ldr	r3, [r1, #0]
    8bca:	b143      	cbz	r3, 8bde <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    8bcc:	684b      	ldr	r3, [r1, #4]
    8bce:	b133      	cbz	r3, 8bde <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    8bd0:	221c      	movs	r2, #28
    8bd2:	2100      	movs	r1, #0
    8bd4:	f000 f93a 	bl	8e4c <memset>
    8bd8:	612c      	str	r4, [r5, #16]
	return 0;
    8bda:	2000      	movs	r0, #0
}
    8bdc:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    8bde:	f06f 0015 	mvn.w	r0, #21
    8be2:	e7fb      	b.n	8bdc <onoff_manager_init+0x1e>

00008be4 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    8be4:	b570      	push	{r4, r5, r6, lr}
    8be6:	4605      	mov	r5, r0
    8be8:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    8bea:	f7ff ffb3 	bl	8b54 <validate_args>

	if (rv < 0) {
    8bee:	1e04      	subs	r4, r0, #0
    8bf0:	db15      	blt.n	8c1e <onoff_request+0x3a>
    8bf2:	f04f 0320 	mov.w	r3, #32
    8bf6:	f3ef 8211 	mrs	r2, BASEPRI
    8bfa:	f383 8812 	msr	BASEPRI_MAX, r3
    8bfe:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    8c02:	8b6b      	ldrh	r3, [r5, #26]
    8c04:	8b2c      	ldrh	r4, [r5, #24]
    8c06:	f64f 71ff 	movw	r1, #65535	; 0xffff
    8c0a:	428b      	cmp	r3, r1
    8c0c:	f004 0407 	and.w	r4, r4, #7
    8c10:	d107      	bne.n	8c22 <onoff_request+0x3e>
	__asm__ volatile(
    8c12:	f382 8811 	msr	BASEPRI, r2
    8c16:	f3bf 8f6f 	isb	sy
		rv = -EAGAIN;
    8c1a:	f06f 040a 	mvn.w	r4, #10
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    8c1e:	4620      	mov	r0, r4
    8c20:	bd70      	pop	{r4, r5, r6, pc}
	if (state == ONOFF_STATE_ON) {
    8c22:	2c02      	cmp	r4, #2
    8c24:	d10c      	bne.n	8c40 <onoff_request+0x5c>
		mgr->refs += 1U;
    8c26:	3301      	adds	r3, #1
    8c28:	836b      	strh	r3, [r5, #26]
    8c2a:	f382 8811 	msr	BASEPRI, r2
    8c2e:	f3bf 8f6f 	isb	sy
			notify_one(mgr, cli, state, 0);
    8c32:	2300      	movs	r3, #0
    8c34:	4622      	mov	r2, r4
    8c36:	4631      	mov	r1, r6
    8c38:	4628      	mov	r0, r5
    8c3a:	f7ff ff9b 	bl	8b74 <notify_one>
    8c3e:	e7ee      	b.n	8c1e <onoff_request+0x3a>
	} else if ((state == ONOFF_STATE_OFF)
    8c40:	2c06      	cmp	r4, #6
    8c42:	d814      	bhi.n	8c6e <onoff_request+0x8a>
    8c44:	e8df f004 	tbb	[pc, r4]
    8c48:	13131304 	.word	0x13131304
    8c4c:	1a04      	.short	0x1a04
    8c4e:	04          	.byte	0x04
    8c4f:	00          	.byte	0x00
	parent->next = child;
    8c50:	2300      	movs	r3, #0
    8c52:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    8c54:	686b      	ldr	r3, [r5, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    8c56:	b93b      	cbnz	r3, 8c68 <onoff_request+0x84>
	list->head = node;
    8c58:	e9c5 6600 	strd	r6, r6, [r5]
	if (start) {
    8c5c:	b9ac      	cbnz	r4, 8c8a <onoff_request+0xa6>
		process_event(mgr, EVT_RECHECK, key);
    8c5e:	2102      	movs	r1, #2
    8c60:	4628      	mov	r0, r5
    8c62:	f7f8 fb75 	bl	1350 <process_event>
    8c66:	e7da      	b.n	8c1e <onoff_request+0x3a>
	parent->next = child;
    8c68:	601e      	str	r6, [r3, #0]
	list->tail = node;
    8c6a:	606e      	str	r6, [r5, #4]
}
    8c6c:	e7f6      	b.n	8c5c <onoff_request+0x78>
    8c6e:	f382 8811 	msr	BASEPRI, r2
    8c72:	f3bf 8f6f 	isb	sy
		rv = -EIO;
    8c76:	f06f 0404 	mvn.w	r4, #4
    8c7a:	e7d0      	b.n	8c1e <onoff_request+0x3a>
    8c7c:	f382 8811 	msr	BASEPRI, r2
    8c80:	f3bf 8f6f 	isb	sy
    8c84:	f06f 0485 	mvn.w	r4, #133	; 0x85
    8c88:	e7c9      	b.n	8c1e <onoff_request+0x3a>
    8c8a:	f382 8811 	msr	BASEPRI, r2
    8c8e:	f3bf 8f6f 	isb	sy
		if (notify) {
    8c92:	e7c4      	b.n	8c1e <onoff_request+0x3a>

00008c94 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    8c94:	4603      	mov	r3, r0
    8c96:	b158      	cbz	r0, 8cb0 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    8c98:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    8c9a:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    8c9e:	2a01      	cmp	r2, #1
    8ca0:	d003      	beq.n	8caa <sys_notify_validate+0x16>
    8ca2:	2a03      	cmp	r2, #3
    8ca4:	d104      	bne.n	8cb0 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    8ca6:	6802      	ldr	r2, [r0, #0]
    8ca8:	b112      	cbz	r2, 8cb0 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    8caa:	2000      	movs	r0, #0
    8cac:	6098      	str	r0, [r3, #8]
    8cae:	4770      	bx	lr
    8cb0:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    8cb4:	4770      	bx	lr

00008cb6 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    8cb6:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    8cb8:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    8cba:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    8cbe:	2a03      	cmp	r2, #3
    8cc0:	f04f 0200 	mov.w	r2, #0
{
    8cc4:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    8cc6:	bf0c      	ite	eq
    8cc8:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    8cca:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    8ccc:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    8cce:	4770      	bx	lr

00008cd0 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_META, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_WARN_DEPRECATED, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_ENFORCE_ZEPHYR_STDINT, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    8cd0:	4770      	bx	lr

00008cd2 <z_log_minimal_printk>:
#include <zephyr/sys/printk.h>

#define HEXDUMP_BYTES_IN_LINE 8U

void z_log_minimal_printk(const char *fmt, ...)
{
    8cd2:	b40f      	push	{r0, r1, r2, r3}
    8cd4:	b507      	push	{r0, r1, r2, lr}
    8cd6:	a904      	add	r1, sp, #16
    8cd8:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    8cdc:	9101      	str	r1, [sp, #4]
	vprintk(fmt, ap);
    8cde:	f7f8 fb29 	bl	1334 <vprintk>
	va_end(ap);
}
    8ce2:	b003      	add	sp, #12
    8ce4:	f85d eb04 	ldr.w	lr, [sp], #4
    8ce8:	b004      	add	sp, #16
    8cea:	4770      	bx	lr

00008cec <flash_area_close>:

void flash_area_close(const struct flash_area *fa)
{
	/* nothing to do for now */
}
    8cec:	4770      	bx	lr

00008cee <flash_area_read>:


static inline bool is_in_flash_area_bounds(const struct flash_area *fa,
					   off_t off, size_t len)
{
	return (off >= 0) && ((off + len) <= fa->fa_size);
    8cee:	2900      	cmp	r1, #0

int flash_area_read(const struct flash_area *fa, off_t off, void *dst,
		    size_t len)
{
    8cf0:	b430      	push	{r4, r5}
    8cf2:	4604      	mov	r4, r0
    8cf4:	4618      	mov	r0, r3
    8cf6:	db0b      	blt.n	8d10 <flash_area_read+0x22>
    8cf8:	68a5      	ldr	r5, [r4, #8]
    8cfa:	4408      	add	r0, r1
    8cfc:	42a8      	cmp	r0, r5
    8cfe:	d807      	bhi.n	8d10 <flash_area_read+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_read(fa->fa_dev, fa->fa_off + off, dst, len);
    8d00:	68e0      	ldr	r0, [r4, #12]
    8d02:	6864      	ldr	r4, [r4, #4]
    8d04:	4421      	add	r1, r4
				    size_t len)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->read(dev, offset, data, len);
    8d06:	6884      	ldr	r4, [r0, #8]
    8d08:	6824      	ldr	r4, [r4, #0]
    8d0a:	46a4      	mov	ip, r4
}
    8d0c:	bc30      	pop	{r4, r5}
    8d0e:	4760      	bx	ip
    8d10:	f06f 0015 	mvn.w	r0, #21
    8d14:	bc30      	pop	{r4, r5}
    8d16:	4770      	bx	lr

00008d18 <flash_area_write>:
    8d18:	2900      	cmp	r1, #0

int flash_area_write(const struct flash_area *fa, off_t off, const void *src,
		     size_t len)
{
    8d1a:	b430      	push	{r4, r5}
    8d1c:	4604      	mov	r4, r0
    8d1e:	4618      	mov	r0, r3
    8d20:	db0b      	blt.n	8d3a <flash_area_write+0x22>
    8d22:	68a5      	ldr	r5, [r4, #8]
    8d24:	4408      	add	r0, r1
    8d26:	42a8      	cmp	r0, r5
    8d28:	d807      	bhi.n	8d3a <flash_area_write+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_write(fa->fa_dev, fa->fa_off + off, (void *)src, len);
    8d2a:	68e0      	ldr	r0, [r4, #12]
    8d2c:	6864      	ldr	r4, [r4, #4]
    8d2e:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->write(dev, offset, data, len);
    8d30:	6884      	ldr	r4, [r0, #8]
    8d32:	6864      	ldr	r4, [r4, #4]
    8d34:	46a4      	mov	ip, r4
}
    8d36:	bc30      	pop	{r4, r5}
    8d38:	4760      	bx	ip
    8d3a:	f06f 0015 	mvn.w	r0, #21
    8d3e:	bc30      	pop	{r4, r5}
    8d40:	4770      	bx	lr

00008d42 <flash_area_erase>:
    8d42:	2900      	cmp	r1, #0

int flash_area_erase(const struct flash_area *fa, off_t off, size_t len)
{
    8d44:	4603      	mov	r3, r0
    8d46:	b410      	push	{r4}
    8d48:	4610      	mov	r0, r2
    8d4a:	db0b      	blt.n	8d64 <flash_area_erase+0x22>
    8d4c:	689c      	ldr	r4, [r3, #8]
    8d4e:	4408      	add	r0, r1
    8d50:	42a0      	cmp	r0, r4
    8d52:	d807      	bhi.n	8d64 <flash_area_erase+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_erase(fa->fa_dev, fa->fa_off + off, len);
    8d54:	68d8      	ldr	r0, [r3, #12]
    8d56:	685b      	ldr	r3, [r3, #4]
    8d58:	4419      	add	r1, r3
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->erase(dev, offset, size);
    8d5a:	6883      	ldr	r3, [r0, #8]
}
    8d5c:	f85d 4b04 	ldr.w	r4, [sp], #4
    8d60:	689b      	ldr	r3, [r3, #8]
    8d62:	4718      	bx	r3
    8d64:	f06f 0015 	mvn.w	r0, #21
    8d68:	f85d 4b04 	ldr.w	r4, [sp], #4
    8d6c:	4770      	bx	lr

00008d6e <flash_area_align>:

uint32_t flash_area_align(const struct flash_area *fa)
{
    8d6e:	b508      	push	{r3, lr}
	return flash_get_write_block_size(fa->fa_dev);
    8d70:	68c0      	ldr	r0, [r0, #12]
static inline size_t z_impl_flash_get_write_block_size(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev)->write_block_size;
    8d72:	6883      	ldr	r3, [r0, #8]
    8d74:	68db      	ldr	r3, [r3, #12]
    8d76:	4798      	blx	r3
}
    8d78:	6800      	ldr	r0, [r0, #0]
    8d7a:	bd08      	pop	{r3, pc}

00008d7c <flash_area_erased_val>:
{
	return fa->fa_dev;
}

uint8_t flash_area_erased_val(const struct flash_area *fa)
{
    8d7c:	b508      	push	{r3, lr}
	const struct flash_parameters *param;

	param = flash_get_parameters(fa->fa_dev);
    8d7e:	68c0      	ldr	r0, [r0, #12]
static inline const struct flash_parameters *z_impl_flash_get_parameters(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev);
    8d80:	6883      	ldr	r3, [r0, #8]
    8d82:	68db      	ldr	r3, [r3, #12]
    8d84:	4798      	blx	r3

	return param->erase_value;
}
    8d86:	7900      	ldrb	r0, [r0, #4]
    8d88:	bd08      	pop	{r3, pc}

00008d8a <get_sectors_cb>:
{
    8d8a:	b570      	push	{r4, r5, r6, lr}
	if (info->start_offset < data->area_off) {
    8d8c:	684c      	ldr	r4, [r1, #4]
    8d8e:	6803      	ldr	r3, [r0, #0]
    8d90:	42a3      	cmp	r3, r4
    8d92:	d201      	bcs.n	8d98 <get_sectors_cb+0xe>
		*bail_value = true;
    8d94:	2001      	movs	r0, #1
}
    8d96:	bd70      	pop	{r4, r5, r6, pc}
	} else if (info->start_offset >= data->area_off + data->area_len) {
    8d98:	688a      	ldr	r2, [r1, #8]
    8d9a:	4422      	add	r2, r4
    8d9c:	4293      	cmp	r3, r2
    8d9e:	d301      	bcc.n	8da4 <get_sectors_cb+0x1a>
		*bail_value = false;
    8da0:	2000      	movs	r0, #0
    8da2:	e7f8      	b.n	8d96 <get_sectors_cb+0xc>
	} else if (data->ret_idx >= data->ret_len) {
    8da4:	e9d1 2503 	ldrd	r2, r5, [r1, #12]
    8da8:	694e      	ldr	r6, [r1, #20]
    8daa:	42b5      	cmp	r5, r6
    8dac:	d303      	bcc.n	8db6 <get_sectors_cb+0x2c>
		data->status = -ENOMEM;
    8dae:	f06f 030b 	mvn.w	r3, #11
    8db2:	618b      	str	r3, [r1, #24]
		return true;
    8db4:	e7f4      	b.n	8da0 <get_sectors_cb+0x16>
	ret[data->ret_idx].fs_off = info->start_offset - data->area_off;
    8db6:	1b1b      	subs	r3, r3, r4
    8db8:	f842 3035 	str.w	r3, [r2, r5, lsl #3]
	ret[data->ret_idx].fs_size = info->size;
    8dbc:	6843      	ldr	r3, [r0, #4]
    8dbe:	6908      	ldr	r0, [r1, #16]
    8dc0:	eb02 02c0 	add.w	r2, r2, r0, lsl #3
    8dc4:	6053      	str	r3, [r2, #4]
	data->ret_idx++;
    8dc6:	690b      	ldr	r3, [r1, #16]
    8dc8:	3301      	adds	r3, #1
    8dca:	610b      	str	r3, [r1, #16]
	return true;
    8dcc:	e7e2      	b.n	8d94 <get_sectors_cb+0xa>

00008dce <abort_function>:
{
    8dce:	b508      	push	{r3, lr}
	sys_reboot(SYS_REBOOT_WARM);
    8dd0:	2000      	movs	r0, #0
    8dd2:	f7f8 fdeb 	bl	19ac <sys_reboot>

00008dd6 <z_do_kernel_oops>:
 *
 * @param esf exception frame
 * @param callee_regs Callee-saved registers (R4-R11)
 */
void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs)
{
    8dd6:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    8dd8:	6800      	ldr	r0, [r0, #0]
    8dda:	f7f9 b897 	b.w	1f0c <z_arm_fatal_error>

00008dde <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    8dde:	2100      	movs	r1, #0
    8de0:	2001      	movs	r0, #1
    8de2:	f7f9 b893 	b.w	1f0c <z_arm_fatal_error>

00008de6 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    8de6:	b508      	push	{r3, lr}
	handler();
    8de8:	f7f9 f93e 	bl	2068 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    8dec:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    8df0:	f7f9 baa6 	b.w	2340 <z_arm_exc_exit>

00008df4 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    8df4:	3901      	subs	r1, #1
    8df6:	4603      	mov	r3, r0
    8df8:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    8dfc:	b90a      	cbnz	r2, 8e02 <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    8dfe:	701a      	strb	r2, [r3, #0]

	return dest;
}
    8e00:	4770      	bx	lr
		*d = *s;
    8e02:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    8e06:	e7f7      	b.n	8df8 <strcpy+0x4>

00008e08 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    8e08:	4603      	mov	r3, r0
	size_t n = 0;
    8e0a:	2000      	movs	r0, #0

	while (*s != '\0') {
    8e0c:	5c1a      	ldrb	r2, [r3, r0]
    8e0e:	b902      	cbnz	r2, 8e12 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    8e10:	4770      	bx	lr
		n++;
    8e12:	3001      	adds	r0, #1
    8e14:	e7fa      	b.n	8e0c <strlen+0x4>

00008e16 <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    8e16:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    8e18:	b15a      	cbz	r2, 8e32 <memcmp+0x1c>
    8e1a:	3901      	subs	r1, #1
    8e1c:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    8e1e:	f810 2b01 	ldrb.w	r2, [r0], #1
    8e22:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    8e26:	42a0      	cmp	r0, r4
    8e28:	d001      	beq.n	8e2e <memcmp+0x18>
    8e2a:	429a      	cmp	r2, r3
    8e2c:	d0f7      	beq.n	8e1e <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    8e2e:	1ad0      	subs	r0, r2, r3
}
    8e30:	bd10      	pop	{r4, pc}
		return 0;
    8e32:	4610      	mov	r0, r2
    8e34:	e7fc      	b.n	8e30 <memcmp+0x1a>

00008e36 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    8e36:	b510      	push	{r4, lr}
    8e38:	1e43      	subs	r3, r0, #1
    8e3a:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    8e3c:	4291      	cmp	r1, r2
    8e3e:	d100      	bne.n	8e42 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    8e40:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    8e42:	f811 4b01 	ldrb.w	r4, [r1], #1
    8e46:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    8e4a:	e7f7      	b.n	8e3c <memcpy+0x6>

00008e4c <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    8e4c:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    8e4e:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    8e50:	4603      	mov	r3, r0
	while (n > 0) {
    8e52:	4293      	cmp	r3, r2
    8e54:	d100      	bne.n	8e58 <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    8e56:	4770      	bx	lr
		*(d_byte++) = c_byte;
    8e58:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    8e5c:	e7f9      	b.n	8e52 <memset+0x6>

00008e5e <_stdout_hook_default>:
}
    8e5e:	f04f 30ff 	mov.w	r0, #4294967295
    8e62:	4770      	bx	lr

00008e64 <pm_state_set>:
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
	ARG_UNUSED(substate_id);

	switch (state) {
    8e64:	2806      	cmp	r0, #6
    8e66:	d108      	bne.n	8e7a <pm_state_set+0x16>
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    8e68:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    8e6c:	2201      	movs	r2, #1
    8e6e:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    8e72:	f3bf 8f4f 	dsb	sy
        __WFE();
    8e76:	bf20      	wfe
    while (true)
    8e78:	e7fd      	b.n	8e76 <pm_state_set+0x12>
		break;
	default:
		LOG_DBG("Unsupported power state %u", state);
		break;
	}
}
    8e7a:	4770      	bx	lr

00008e7c <pm_state_exit_post_ops>:
    8e7c:	2300      	movs	r3, #0
    8e7e:	f383 8811 	msr	BASEPRI, r3
    8e82:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    8e86:	4770      	bx	lr

00008e88 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    8e88:	6903      	ldr	r3, [r0, #16]
    8e8a:	b2c9      	uxtb	r1, r1
    8e8c:	220c      	movs	r2, #12
    8e8e:	fb01 3302 	mla	r3, r1, r2, r3
    8e92:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
    8e94:	f000 0007 	and.w	r0, r0, #7
    8e98:	4770      	bx	lr

00008e9a <set_on_state>:
	__asm__ volatile(
    8e9a:	f04f 0320 	mov.w	r3, #32
    8e9e:	f3ef 8211 	mrs	r2, BASEPRI
    8ea2:	f383 8812 	msr	BASEPRI_MAX, r3
    8ea6:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    8eaa:	6803      	ldr	r3, [r0, #0]
    8eac:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    8eb0:	f043 0302 	orr.w	r3, r3, #2
    8eb4:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    8eb6:	f382 8811 	msr	BASEPRI, r2
    8eba:	f3bf 8f6f 	isb	sy
}
    8ebe:	4770      	bx	lr

00008ec0 <stop>:
{
    8ec0:	b570      	push	{r4, r5, r6, lr}
    8ec2:	b2c9      	uxtb	r1, r1
	struct nrf_clock_control_data *data = dev->data;
    8ec4:	6903      	ldr	r3, [r0, #16]
	__asm__ volatile(
    8ec6:	f04f 0420 	mov.w	r4, #32
    8eca:	f3ef 8511 	mrs	r5, BASEPRI
    8ece:	f384 8812 	msr	BASEPRI_MAX, r4
    8ed2:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    8ed6:	260c      	movs	r6, #12
    8ed8:	fb06 3401 	mla	r4, r6, r1, r3
    8edc:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    8ede:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    8ee2:	d008      	beq.n	8ef6 <stop+0x36>
    8ee4:	42a2      	cmp	r2, r4
    8ee6:	d006      	beq.n	8ef6 <stop+0x36>
	__asm__ volatile(
    8ee8:	f385 8811 	msr	BASEPRI, r5
    8eec:	f3bf 8f6f 	isb	sy
		err = -EPERM;
    8ef0:	f04f 30ff 	mov.w	r0, #4294967295
}
    8ef4:	bd70      	pop	{r4, r5, r6, pc}
		*flags = CLOCK_CONTROL_STATUS_OFF;
    8ef6:	4371      	muls	r1, r6
    8ef8:	440b      	add	r3, r1
    8efa:	2201      	movs	r2, #1
    8efc:	641a      	str	r2, [r3, #64]	; 0x40
    8efe:	f385 8811 	msr	BASEPRI, r5
    8f02:	f3bf 8f6f 	isb	sy
	get_sub_config(dev, type)->stop();
    8f06:	6843      	ldr	r3, [r0, #4]
    8f08:	440b      	add	r3, r1
    8f0a:	685b      	ldr	r3, [r3, #4]
    8f0c:	4798      	blx	r3
	return 0;
    8f0e:	2000      	movs	r0, #0
    8f10:	e7f0      	b.n	8ef4 <stop+0x34>

00008f12 <api_stop>:
	return stop(dev, subsys, CTX_API);
    8f12:	2280      	movs	r2, #128	; 0x80
    8f14:	f7ff bfd4 	b.w	8ec0 <stop>

00008f18 <async_start>:
{
    8f18:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    8f1a:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    8f1c:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    8f1e:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    8f20:	f04f 0520 	mov.w	r5, #32
    8f24:	f3ef 8611 	mrs	r6, BASEPRI
    8f28:	f385 8812 	msr	BASEPRI_MAX, r5
    8f2c:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    8f30:	250c      	movs	r5, #12
    8f32:	4369      	muls	r1, r5
    8f34:	440c      	add	r4, r1
    8f36:	6c25      	ldr	r5, [r4, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    8f38:	f005 0c07 	and.w	ip, r5, #7
    8f3c:	f1bc 0f01 	cmp.w	ip, #1
    8f40:	d10b      	bne.n	8f5a <async_start+0x42>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    8f42:	6427      	str	r7, [r4, #64]	; 0x40
	__asm__ volatile(
    8f44:	f386 8811 	msr	BASEPRI, r6
    8f48:	f3bf 8f6f 	isb	sy
	subdata->user_data = user_data;
    8f4c:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    8f50:	6843      	ldr	r3, [r0, #4]
    8f52:	585b      	ldr	r3, [r3, r1]
    8f54:	4798      	blx	r3
	return 0;
    8f56:	2000      	movs	r0, #0
}
    8f58:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    8f5a:	f005 05c0 	and.w	r5, r5, #192	; 0xc0
	} else if (current_ctx != ctx) {
    8f5e:	42af      	cmp	r7, r5
    8f60:	f386 8811 	msr	BASEPRI, r6
    8f64:	f3bf 8f6f 	isb	sy
		err = -EALREADY;
    8f68:	bf0c      	ite	eq
    8f6a:	f06f 0077 	mvneq.w	r0, #119	; 0x77
		err = -EPERM;
    8f6e:	f04f 30ff 	movne.w	r0, #4294967295
    8f72:	e7f1      	b.n	8f58 <async_start+0x40>

00008f74 <api_start>:
{
    8f74:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    8f76:	2480      	movs	r4, #128	; 0x80
    8f78:	9400      	str	r4, [sp, #0]
    8f7a:	f7ff ffcd 	bl	8f18 <async_start>
}
    8f7e:	b002      	add	sp, #8
    8f80:	bd10      	pop	{r4, pc}

00008f82 <onoff_started_callback>:
{
    8f82:	b410      	push	{r4}
	return &data->mgr[type];
    8f84:	6900      	ldr	r0, [r0, #16]
    8f86:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    8f88:	241c      	movs	r4, #28
    8f8a:	fb03 0004 	mla	r0, r3, r4, r0
    8f8e:	2100      	movs	r1, #0
}
    8f90:	f85d 4b04 	ldr.w	r4, [sp], #4
	notify(mgr, 0);
    8f94:	4710      	bx	r2

00008f96 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    8f96:	2000      	movs	r0, #0
    8f98:	f000 bc14 	b.w	97c4 <nrfx_clock_start>

00008f9c <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    8f9c:	2000      	movs	r0, #0
    8f9e:	f000 bc4d 	b.w	983c <nrfx_clock_stop>

00008fa2 <blocking_start_callback>:
{
    8fa2:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    8fa4:	f7fd b942 	b.w	622c <z_impl_k_sem_give>

00008fa8 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    8fa8:	6843      	ldr	r3, [r0, #4]
    8faa:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    8fac:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    8fb0:	600b      	str	r3, [r1, #0]
}
    8fb2:	2000      	movs	r0, #0
    8fb4:	4770      	bx	lr

00008fb6 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    8fb6:	6843      	ldr	r3, [r0, #4]
    8fb8:	685b      	ldr	r3, [r3, #4]
	const uint32_t set_mask = value & mask;
    8fba:	ea02 0001 	and.w	r0, r2, r1
	const uint32_t clear_mask = (~set_mask) & mask;
    8fbe:	ea21 0102 	bic.w	r1, r1, r2
    p_reg->OUTSET = set_mask;
    8fc2:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    8fc6:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    8fca:	2000      	movs	r0, #0
    8fcc:	4770      	bx	lr

00008fce <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    8fce:	6843      	ldr	r3, [r0, #4]
    8fd0:	685b      	ldr	r3, [r3, #4]
}
    8fd2:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    8fd4:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    8fd8:	4770      	bx	lr

00008fda <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    8fda:	6843      	ldr	r3, [r0, #4]
    8fdc:	685b      	ldr	r3, [r3, #4]
}
    8fde:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    8fe0:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    8fe4:	4770      	bx	lr

00008fe6 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    8fe6:	6843      	ldr	r3, [r0, #4]
    8fe8:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    8fea:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	const uint32_t set_mask = value & mask;
    8fee:	ea21 0003 	bic.w	r0, r1, r3
	const uint32_t clear_mask = (~value) & mask;
    8ff2:	400b      	ands	r3, r1
    p_reg->OUTSET = set_mask;
    8ff4:	f8c2 0508 	str.w	r0, [r2, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    8ff8:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
}
    8ffc:	2000      	movs	r0, #0
    8ffe:	4770      	bx	lr

00009000 <gpio_nrfx_manage_callback>:
{
    9000:	b510      	push	{r4, lr}
	return port->data;
    9002:	6903      	ldr	r3, [r0, #16]
	return list->head;
    9004:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    9006:	b1f8      	cbz	r0, 9048 <gpio_nrfx_manage_callback+0x48>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    9008:	4288      	cmp	r0, r1
    900a:	d119      	bne.n	9040 <gpio_nrfx_manage_callback+0x40>
Z_GENLIST_REMOVE(slist, snode)
    900c:	689c      	ldr	r4, [r3, #8]
	return node->next;
    900e:	6808      	ldr	r0, [r1, #0]
	list->head = node;
    9010:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    9012:	42a1      	cmp	r1, r4
    9014:	d100      	bne.n	9018 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    9016:	6098      	str	r0, [r3, #8]
	parent->next = child;
    9018:	2000      	movs	r0, #0
    901a:	6008      	str	r0, [r1, #0]
	if (set) {
    901c:	b12a      	cbz	r2, 902a <gpio_nrfx_manage_callback+0x2a>
	return list->head;
    901e:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    9020:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    9022:	689a      	ldr	r2, [r3, #8]
	list->head = node;
    9024:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    9026:	b902      	cbnz	r2, 902a <gpio_nrfx_manage_callback+0x2a>
	list->tail = node;
    9028:	6099      	str	r1, [r3, #8]
	return 0;
    902a:	2000      	movs	r0, #0
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    902c:	e010      	b.n	9050 <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    902e:	4281      	cmp	r1, r0
    9030:	d106      	bne.n	9040 <gpio_nrfx_manage_callback+0x40>
	return node->next;
    9032:	6808      	ldr	r0, [r1, #0]
	parent->next = child;
    9034:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    9036:	6898      	ldr	r0, [r3, #8]
    9038:	4281      	cmp	r1, r0
    903a:	d1ed      	bne.n	9018 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    903c:	609c      	str	r4, [r3, #8]
}
    903e:	e7eb      	b.n	9018 <gpio_nrfx_manage_callback+0x18>
	return node->next;
    9040:	4604      	mov	r4, r0
    9042:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    9044:	2800      	cmp	r0, #0
    9046:	d1f2      	bne.n	902e <gpio_nrfx_manage_callback+0x2e>
			if (!set) {
    9048:	2a00      	cmp	r2, #0
    904a:	d1e8      	bne.n	901e <gpio_nrfx_manage_callback+0x1e>
				return -EINVAL;
    904c:	f06f 0015 	mvn.w	r0, #21
}
    9050:	bd10      	pop	{r4, pc}

00009052 <irq_connect1>:
#ifdef CONFIG_SPI_0_NRF_SPI
SPI_NRFX_SPI_DEFINE(0);
#endif

#ifdef CONFIG_SPI_1_NRF_SPI
SPI_NRFX_SPI_DEFINE(1);
    9052:	2200      	movs	r2, #0
    9054:	2101      	movs	r1, #1
    9056:	2004      	movs	r0, #4
    9058:	f7f8 bfee 	b.w	2038 <z_arm_irq_priority_set>

0000905c <spi_context_get_next_buf.constprop.0>:
static inline void *spi_context_get_next_buf(const struct spi_buf **current,
    905c:	b510      	push	{r4, lr}
	while (*count) {
    905e:	680b      	ldr	r3, [r1, #0]
    9060:	b913      	cbnz	r3, 9068 <spi_context_get_next_buf.constprop.0+0xc>
	*buf_len = 0;
    9062:	6013      	str	r3, [r2, #0]
	return NULL;
    9064:	4618      	mov	r0, r3
    9066:	e005      	b.n	9074 <spi_context_get_next_buf.constprop.0+0x18>
		if (((*current)->len / dfs) != 0) {
    9068:	6803      	ldr	r3, [r0, #0]
    906a:	685c      	ldr	r4, [r3, #4]
    906c:	b11c      	cbz	r4, 9076 <spi_context_get_next_buf.constprop.0+0x1a>
			*buf_len = (*current)->len / dfs;
    906e:	6014      	str	r4, [r2, #0]
			return (*current)->buf;
    9070:	6803      	ldr	r3, [r0, #0]
    9072:	6818      	ldr	r0, [r3, #0]
}
    9074:	bd10      	pop	{r4, pc}
		++(*current);
    9076:	3308      	adds	r3, #8
    9078:	6003      	str	r3, [r0, #0]
		--(*count);
    907a:	680b      	ldr	r3, [r1, #0]
    907c:	3b01      	subs	r3, #1
    907e:	600b      	str	r3, [r1, #0]
    9080:	e7ed      	b.n	905e <spi_context_get_next_buf.constprop.0+0x2>

00009082 <gpio_pin_set_dt.isra.0>:
 *
 * @param spec GPIO specification from devicetree
 * @param value Value assigned to the pin.
 * @return a value from gpio_pin_set()
 */
static inline int gpio_pin_set_dt(const struct gpio_dt_spec *spec, int value)
    9082:	4603      	mov	r3, r0
    9084:	460a      	mov	r2, r1
{
	return gpio_pin_set(spec->port, spec->pin, value);
    9086:	6800      	ldr	r0, [r0, #0]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    9088:	7919      	ldrb	r1, [r3, #4]
    908a:	2301      	movs	r3, #1
    908c:	fa03 f101 	lsl.w	r1, r3, r1
    9090:	6903      	ldr	r3, [r0, #16]
    9092:	681b      	ldr	r3, [r3, #0]
    9094:	4219      	tst	r1, r3
		value = (value != 0) ? 0 : 1;
    9096:	bf18      	it	ne
    9098:	f082 0201 	eorne.w	r2, r2, #1
	if (value != 0)	{
    909c:	b112      	cbz	r2, 90a4 <gpio_pin_set_dt.isra.0+0x22>
	return api->port_set_bits_raw(port, pins);
    909e:	6883      	ldr	r3, [r0, #8]
    90a0:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
    90a2:	4718      	bx	r3
    90a4:	6883      	ldr	r3, [r0, #8]
    90a6:	691b      	ldr	r3, [r3, #16]
    90a8:	e7fb      	b.n	90a2 <gpio_pin_set_dt.isra.0+0x20>

000090aa <_spi_context_cs_control>:
{
    90aa:	b538      	push	{r3, r4, r5, lr}
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    90ac:	6803      	ldr	r3, [r0, #0]
{
    90ae:	4604      	mov	r4, r0
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    90b0:	b1e3      	cbz	r3, 90ec <_spi_context_cs_control+0x42>
    90b2:	6898      	ldr	r0, [r3, #8]
    90b4:	b1d0      	cbz	r0, 90ec <_spi_context_cs_control+0x42>
    90b6:	6805      	ldr	r5, [r0, #0]
    90b8:	b1c5      	cbz	r5, 90ec <_spi_context_cs_control+0x42>
		if (on) {
    90ba:	b149      	cbz	r1, 90d0 <_spi_context_cs_control+0x26>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 1);
    90bc:	2101      	movs	r1, #1
    90be:	f7ff ffe0 	bl	9082 <gpio_pin_set_dt.isra.0>
			k_busy_wait(ctx->config->cs->delay);
    90c2:	6823      	ldr	r3, [r4, #0]
    90c4:	689b      	ldr	r3, [r3, #8]
    90c6:	6898      	ldr	r0, [r3, #8]
}
    90c8:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_impl_k_busy_wait(usec_to_wait);
    90cc:	f000 be25 	b.w	9d1a <z_impl_k_busy_wait>
			if (!force_off &&
    90d0:	b912      	cbnz	r2, 90d8 <_spi_context_cs_control+0x2e>
    90d2:	889b      	ldrh	r3, [r3, #4]
    90d4:	04db      	lsls	r3, r3, #19
    90d6:	d409      	bmi.n	90ec <_spi_context_cs_control+0x42>
			k_busy_wait(ctx->config->cs->delay);
    90d8:	6880      	ldr	r0, [r0, #8]
    90da:	f000 fe1e 	bl	9d1a <z_impl_k_busy_wait>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    90de:	6823      	ldr	r3, [r4, #0]
    90e0:	2100      	movs	r1, #0
    90e2:	6898      	ldr	r0, [r3, #8]
}
    90e4:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    90e8:	f7ff bfcb 	b.w	9082 <gpio_pin_set_dt.isra.0>
}
    90ec:	bd38      	pop	{r3, r4, r5, pc}

000090ee <spi_context_unlock_unconditionally>:
{
    90ee:	b510      	push	{r4, lr}
	_spi_context_cs_control(ctx, false, true);
    90f0:	2201      	movs	r2, #1
    90f2:	2100      	movs	r1, #0
{
    90f4:	4604      	mov	r4, r0
	_spi_context_cs_control(ctx, false, true);
    90f6:	f7ff ffd8 	bl	90aa <_spi_context_cs_control>
	if (!k_sem_count_get(&ctx->lock)) {
    90fa:	69a3      	ldr	r3, [r4, #24]
    90fc:	b933      	cbnz	r3, 910c <spi_context_unlock_unconditionally+0x1e>
		ctx->owner = NULL;
    90fe:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    9100:	f104 0010 	add.w	r0, r4, #16
}
    9104:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    9108:	f7fd b890 	b.w	622c <z_impl_k_sem_give>
    910c:	bd10      	pop	{r4, pc}

0000910e <spi_nrfx_release>:
{
    910e:	b510      	push	{r4, lr}
	struct spi_nrfx_data *dev_data = dev->data;
    9110:	6900      	ldr	r0, [r0, #16]
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    9112:	6803      	ldr	r3, [r0, #0]
    9114:	428b      	cmp	r3, r1
    9116:	d106      	bne.n	9126 <spi_nrfx_release+0x18>
	if (dev_data->busy) {
    9118:	f890 405c 	ldrb.w	r4, [r0, #92]	; 0x5c
    911c:	b934      	cbnz	r4, 912c <spi_nrfx_release+0x1e>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    911e:	f7ff ffe6 	bl	90ee <spi_context_unlock_unconditionally>
	return 0;
    9122:	4620      	mov	r0, r4
}
    9124:	bd10      	pop	{r4, pc}
		return -EINVAL;
    9126:	f06f 0015 	mvn.w	r0, #21
    912a:	e7fb      	b.n	9124 <spi_nrfx_release+0x16>
		return -EBUSY;
    912c:	f06f 000f 	mvn.w	r0, #15
    9130:	e7f8      	b.n	9124 <spi_nrfx_release+0x16>

00009132 <irq_connect3>:
#ifdef CONFIG_SPI_2_NRF_SPIM
SPI_NRFX_SPIM_DEFINE(2);
#endif

#ifdef CONFIG_SPI_3_NRF_SPIM
SPI_NRFX_SPIM_DEFINE(3);
    9132:	2200      	movs	r2, #0
    9134:	2101      	movs	r1, #1
    9136:	202f      	movs	r0, #47	; 0x2f
    9138:	f7f8 bf7e 	b.w	2038 <z_arm_irq_priority_set>

0000913c <spi_context_get_next_buf.constprop.0>:
static inline void *spi_context_get_next_buf(const struct spi_buf **current,
    913c:	b510      	push	{r4, lr}
	while (*count) {
    913e:	680b      	ldr	r3, [r1, #0]
    9140:	b913      	cbnz	r3, 9148 <spi_context_get_next_buf.constprop.0+0xc>
	*buf_len = 0;
    9142:	6013      	str	r3, [r2, #0]
	return NULL;
    9144:	4618      	mov	r0, r3
    9146:	e005      	b.n	9154 <spi_context_get_next_buf.constprop.0+0x18>
		if (((*current)->len / dfs) != 0) {
    9148:	6803      	ldr	r3, [r0, #0]
    914a:	685c      	ldr	r4, [r3, #4]
    914c:	b11c      	cbz	r4, 9156 <spi_context_get_next_buf.constprop.0+0x1a>
			*buf_len = (*current)->len / dfs;
    914e:	6014      	str	r4, [r2, #0]
			return (*current)->buf;
    9150:	6803      	ldr	r3, [r0, #0]
    9152:	6818      	ldr	r0, [r3, #0]
}
    9154:	bd10      	pop	{r4, pc}
		++(*current);
    9156:	3308      	adds	r3, #8
    9158:	6003      	str	r3, [r0, #0]
		--(*count);
    915a:	680b      	ldr	r3, [r1, #0]
    915c:	3b01      	subs	r3, #1
    915e:	600b      	str	r3, [r1, #0]
    9160:	e7ed      	b.n	913e <spi_context_get_next_buf.constprop.0+0x2>

00009162 <gpio_pin_set_dt.isra.0>:
static inline int gpio_pin_set_dt(const struct gpio_dt_spec *spec, int value)
    9162:	4603      	mov	r3, r0
    9164:	460a      	mov	r2, r1
	return gpio_pin_set(spec->port, spec->pin, value);
    9166:	6800      	ldr	r0, [r0, #0]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    9168:	7919      	ldrb	r1, [r3, #4]
    916a:	2301      	movs	r3, #1
    916c:	fa03 f101 	lsl.w	r1, r3, r1
    9170:	6903      	ldr	r3, [r0, #16]
    9172:	681b      	ldr	r3, [r3, #0]
    9174:	4219      	tst	r1, r3
		value = (value != 0) ? 0 : 1;
    9176:	bf18      	it	ne
    9178:	f082 0201 	eorne.w	r2, r2, #1
	if (value != 0)	{
    917c:	b112      	cbz	r2, 9184 <gpio_pin_set_dt.isra.0+0x22>
	return api->port_set_bits_raw(port, pins);
    917e:	6883      	ldr	r3, [r0, #8]
    9180:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
    9182:	4718      	bx	r3
    9184:	6883      	ldr	r3, [r0, #8]
    9186:	691b      	ldr	r3, [r3, #16]
    9188:	e7fb      	b.n	9182 <gpio_pin_set_dt.isra.0+0x20>

0000918a <_spi_context_cs_control>:
{
    918a:	b538      	push	{r3, r4, r5, lr}
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    918c:	6803      	ldr	r3, [r0, #0]
{
    918e:	4604      	mov	r4, r0
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    9190:	b1e3      	cbz	r3, 91cc <_spi_context_cs_control+0x42>
    9192:	6898      	ldr	r0, [r3, #8]
    9194:	b1d0      	cbz	r0, 91cc <_spi_context_cs_control+0x42>
    9196:	6805      	ldr	r5, [r0, #0]
    9198:	b1c5      	cbz	r5, 91cc <_spi_context_cs_control+0x42>
		if (on) {
    919a:	b149      	cbz	r1, 91b0 <_spi_context_cs_control+0x26>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 1);
    919c:	2101      	movs	r1, #1
    919e:	f7ff ffe0 	bl	9162 <gpio_pin_set_dt.isra.0>
			k_busy_wait(ctx->config->cs->delay);
    91a2:	6823      	ldr	r3, [r4, #0]
    91a4:	689b      	ldr	r3, [r3, #8]
    91a6:	6898      	ldr	r0, [r3, #8]
}
    91a8:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_impl_k_busy_wait(usec_to_wait);
    91ac:	f000 bdb5 	b.w	9d1a <z_impl_k_busy_wait>
			if (!force_off &&
    91b0:	b912      	cbnz	r2, 91b8 <_spi_context_cs_control+0x2e>
    91b2:	889b      	ldrh	r3, [r3, #4]
    91b4:	04db      	lsls	r3, r3, #19
    91b6:	d409      	bmi.n	91cc <_spi_context_cs_control+0x42>
			k_busy_wait(ctx->config->cs->delay);
    91b8:	6880      	ldr	r0, [r0, #8]
    91ba:	f000 fdae 	bl	9d1a <z_impl_k_busy_wait>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    91be:	6823      	ldr	r3, [r4, #0]
    91c0:	2100      	movs	r1, #0
    91c2:	6898      	ldr	r0, [r3, #8]
}
    91c4:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    91c8:	f7ff bfcb 	b.w	9162 <gpio_pin_set_dt.isra.0>
}
    91cc:	bd38      	pop	{r3, r4, r5, pc}

000091ce <spi_context_unlock_unconditionally>:
{
    91ce:	b510      	push	{r4, lr}
	_spi_context_cs_control(ctx, false, true);
    91d0:	2201      	movs	r2, #1
    91d2:	2100      	movs	r1, #0
{
    91d4:	4604      	mov	r4, r0
	_spi_context_cs_control(ctx, false, true);
    91d6:	f7ff ffd8 	bl	918a <_spi_context_cs_control>
	if (!k_sem_count_get(&ctx->lock)) {
    91da:	69a3      	ldr	r3, [r4, #24]
    91dc:	b933      	cbnz	r3, 91ec <spi_context_unlock_unconditionally+0x1e>
		ctx->owner = NULL;
    91de:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    91e0:	f104 0010 	add.w	r0, r4, #16
}
    91e4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    91e8:	f7fd b820 	b.w	622c <z_impl_k_sem_give>
    91ec:	bd10      	pop	{r4, pc}

000091ee <spi_nrfx_release>:
{
    91ee:	b510      	push	{r4, lr}
	struct spi_nrfx_data *dev_data = dev->data;
    91f0:	6900      	ldr	r0, [r0, #16]
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    91f2:	6803      	ldr	r3, [r0, #0]
    91f4:	428b      	cmp	r3, r1
    91f6:	d106      	bne.n	9206 <spi_nrfx_release+0x18>
	if (dev_data->busy) {
    91f8:	f890 405c 	ldrb.w	r4, [r0, #92]	; 0x5c
    91fc:	b934      	cbnz	r4, 920c <spi_nrfx_release+0x1e>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    91fe:	f7ff ffe6 	bl	91ce <spi_context_unlock_unconditionally>
	return 0;
    9202:	4620      	mov	r0, r4
}
    9204:	bd10      	pop	{r4, pc}
		return -EINVAL;
    9206:	f06f 0015 	mvn.w	r0, #21
    920a:	e7fb      	b.n	9204 <spi_nrfx_release+0x16>
		return -EBUSY;
    920c:	f06f 000f 	mvn.w	r0, #15
    9210:	e7f8      	b.n	9204 <spi_nrfx_release+0x16>

00009212 <spi_nor_pages_layout>:
	*layout = &cfg->layout;
    9212:	6843      	ldr	r3, [r0, #4]
    9214:	3314      	adds	r3, #20
    9216:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    9218:	2301      	movs	r3, #1
    921a:	6013      	str	r3, [r2, #0]
}
    921c:	4770      	bx	lr

0000921e <release_device.isra.0>:
    921e:	f7fd b805 	b.w	622c <z_impl_k_sem_give>

00009222 <acquire_device.isra.0>:
	return z_impl_k_sem_take(sem, timeout);
    9222:	f04f 32ff 	mov.w	r2, #4294967295
    9226:	f04f 33ff 	mov.w	r3, #4294967295
    922a:	f7fd b81f 	b.w	626c <z_impl_k_sem_take>

0000922e <spi_nor_access>:
{
    922e:	b5f0      	push	{r4, r5, r6, r7, lr}
    9230:	b08b      	sub	sp, #44	; 0x2c
	const struct spi_nor_config *const driver_cfg = dev->config;
    9232:	6844      	ldr	r4, [r0, #4]
	struct spi_nor_data *const driver_data = dev->data;
    9234:	6907      	ldr	r7, [r0, #16]
{
    9236:	9e11      	ldr	r6, [sp, #68]	; 0x44
	struct spi_buf spi_buf[2] = {
    9238:	f8cd d018 	str.w	sp, [sp, #24]
	uint8_t buf[5] = { 0 };
    923c:	2000      	movs	r0, #0
    923e:	9000      	str	r0, [sp, #0]
    9240:	f88d 0004 	strb.w	r0, [sp, #4]
	struct spi_buf spi_buf[2] = {
    9244:	2001      	movs	r0, #1
    9246:	9007      	str	r0, [sp, #28]
    9248:	9810      	ldr	r0, [sp, #64]	; 0x40
	buf[0] = opcode;
    924a:	f88d 1000 	strb.w	r1, [sp]
	if (is_addressed) {
    924e:	07d1      	lsls	r1, r2, #31
	struct spi_buf spi_buf[2] = {
    9250:	e9cd 0608 	strd	r0, r6, [sp, #32]
	bool is_write = (access & NOR_ACCESS_WRITE) != 0U;
    9254:	f002 0580 	and.w	r5, r2, #128	; 0x80
	if (is_addressed) {
    9258:	d50d      	bpl.n	9276 <spi_nor_access+0x48>
				      && driver_data->flag_access_32bit));
    925a:	7d3a      	ldrb	r2, [r7, #20]
		union {
    925c:	ba1b      	rev	r3, r3
		} addr32 = {
    925e:	9304      	str	r3, [sp, #16]
		if (use_32bit) {
    9260:	07d3      	lsls	r3, r2, #31
    9262:	d51d      	bpl.n	92a0 <spi_nor_access+0x72>
			memcpy(&buf[1], &addr32.u8[0], 4);
    9264:	2204      	movs	r2, #4
    9266:	a904      	add	r1, sp, #16
    9268:	f10d 0001 	add.w	r0, sp, #1
    926c:	f7ff fde3 	bl	8e36 <memcpy>
			spi_buf[0].len += 4;
    9270:	9b07      	ldr	r3, [sp, #28]
    9272:	3304      	adds	r3, #4
    9274:	9307      	str	r3, [sp, #28]
		.count = (length != 0) ? 2 : 1,
    9276:	2e00      	cmp	r6, #0
	const struct spi_buf_set tx_set = {
    9278:	ab06      	add	r3, sp, #24
		.count = (length != 0) ? 2 : 1,
    927a:	bf0c      	ite	eq
    927c:	2201      	moveq	r2, #1
    927e:	2202      	movne	r2, #2
	const struct spi_buf_set rx_set = {
    9280:	e9cd 2303 	strd	r2, r3, [sp, #12]
	const struct spi_buf_set tx_set = {
    9284:	9302      	str	r3, [sp, #8]
 * @return a value from spi_write().
 */
static inline int spi_write_dt(const struct spi_dt_spec *spec,
			       const struct spi_buf_set *tx_bufs)
{
	return spi_write(spec->bus, &spec->config, tx_bufs);
    9286:	4621      	mov	r1, r4
	const struct spi_buf_set rx_set = {
    9288:	2302      	movs	r3, #2
    928a:	9305      	str	r3, [sp, #20]
	if (is_write) {
    928c:	f851 0b04 	ldr.w	r0, [r1], #4
    9290:	b185      	cbz	r5, 92b4 <spi_nor_access+0x86>
	return api->transceive(dev, config, tx_bufs, rx_bufs);
    9292:	6883      	ldr	r3, [r0, #8]
    9294:	681c      	ldr	r4, [r3, #0]
    9296:	2300      	movs	r3, #0
    9298:	aa02      	add	r2, sp, #8
    929a:	47a0      	blx	r4
}
    929c:	b00b      	add	sp, #44	; 0x2c
    929e:	bdf0      	pop	{r4, r5, r6, r7, pc}
			memcpy(&buf[1], &addr32.u8[1], 3);
    92a0:	2203      	movs	r2, #3
    92a2:	f10d 0111 	add.w	r1, sp, #17
    92a6:	f10d 0001 	add.w	r0, sp, #1
    92aa:	f7ff fdc4 	bl	8e36 <memcpy>
			spi_buf[0].len += 3;
    92ae:	9b07      	ldr	r3, [sp, #28]
    92b0:	3303      	adds	r3, #3
    92b2:	e7df      	b.n	9274 <spi_nor_access+0x46>
    92b4:	6883      	ldr	r3, [r0, #8]
    92b6:	681c      	ldr	r4, [r3, #0]
    92b8:	ab04      	add	r3, sp, #16
    92ba:	e7ed      	b.n	9298 <spi_nor_access+0x6a>

000092bc <spi_nor_write_protection_set>:
{
    92bc:	b507      	push	{r0, r1, r2, lr}
	ret = spi_nor_cmd_write(dev, (write_protect) ?
    92be:	2900      	cmp	r1, #0
    92c0:	f04f 0300 	mov.w	r3, #0
    92c4:	e9cd 3300 	strd	r3, r3, [sp]
    92c8:	f04f 0280 	mov.w	r2, #128	; 0x80
    92cc:	bf0c      	ite	eq
    92ce:	2106      	moveq	r1, #6
    92d0:	2104      	movne	r1, #4
    92d2:	f7ff ffac 	bl	922e <spi_nor_access>
}
    92d6:	b003      	add	sp, #12
    92d8:	f85d fb04 	ldr.w	pc, [sp], #4

000092dc <spi_nor_read>:
{
    92dc:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    92de:	461e      	mov	r6, r3
	return cfg->flash_size;
    92e0:	6843      	ldr	r3, [r0, #4]
	if ((addr < 0) || ((addr + size) > flash_size)) {
    92e2:	1e0d      	subs	r5, r1, #0
	return cfg->flash_size;
    92e4:	691b      	ldr	r3, [r3, #16]
{
    92e6:	4604      	mov	r4, r0
    92e8:	4617      	mov	r7, r2
	if ((addr < 0) || ((addr + size) > flash_size)) {
    92ea:	db14      	blt.n	9316 <spi_nor_read+0x3a>
    92ec:	19aa      	adds	r2, r5, r6
    92ee:	429a      	cmp	r2, r3
    92f0:	d811      	bhi.n	9316 <spi_nor_read+0x3a>
	acquire_device(dev);
    92f2:	6900      	ldr	r0, [r0, #16]
    92f4:	f7ff ff95 	bl	9222 <acquire_device.isra.0>
	ret = spi_nor_cmd_addr_read(dev, SPI_NOR_CMD_READ, addr, dest, size);
    92f8:	462b      	mov	r3, r5
    92fa:	e9cd 7600 	strd	r7, r6, [sp]
    92fe:	2201      	movs	r2, #1
    9300:	2103      	movs	r1, #3
    9302:	4620      	mov	r0, r4
    9304:	f7ff ff93 	bl	922e <spi_nor_access>
    9308:	4605      	mov	r5, r0
	release_device(dev);
    930a:	6920      	ldr	r0, [r4, #16]
    930c:	f7ff ff87 	bl	921e <release_device.isra.0>
}
    9310:	4628      	mov	r0, r5
    9312:	b003      	add	sp, #12
    9314:	bdf0      	pop	{r4, r5, r6, r7, pc}
		return -EINVAL;
    9316:	f06f 0515 	mvn.w	r5, #21
    931a:	e7f9      	b.n	9310 <spi_nor_read+0x34>

0000931c <spi_nor_wait_until_ready.isra.0>:
static int spi_nor_wait_until_ready(const struct device *dev)
    931c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    931e:	4604      	mov	r4, r0
		ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDSR, &reg, sizeof(reg));
    9320:	2501      	movs	r5, #1
    9322:	f10d 060f 	add.w	r6, sp, #15
    9326:	2300      	movs	r3, #0
    9328:	e9cd 6500 	strd	r6, r5, [sp]
    932c:	461a      	mov	r2, r3
    932e:	2105      	movs	r1, #5
    9330:	4620      	mov	r0, r4
    9332:	f7ff ff7c 	bl	922e <spi_nor_access>
	} while (!ret && (reg & SPI_NOR_WIP_BIT));
    9336:	b918      	cbnz	r0, 9340 <spi_nor_wait_until_ready.isra.0+0x24>
    9338:	f89d 300f 	ldrb.w	r3, [sp, #15]
    933c:	07db      	lsls	r3, r3, #31
    933e:	d4f2      	bmi.n	9326 <spi_nor_wait_until_ready.isra.0+0xa>
}
    9340:	b004      	add	sp, #16
    9342:	bd70      	pop	{r4, r5, r6, pc}

00009344 <spi_nor_write>:
{
    9344:	e92d 47f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, r9, sl, lr}
    9348:	4698      	mov	r8, r3
	return cfg->flash_size;
    934a:	6843      	ldr	r3, [r0, #4]
	if ((addr < 0) || ((size + addr) > flash_size)) {
    934c:	1e0c      	subs	r4, r1, #0
	return cfg->flash_size;
    934e:	691b      	ldr	r3, [r3, #16]
{
    9350:	4606      	mov	r6, r0
    9352:	4691      	mov	r9, r2
	if ((addr < 0) || ((size + addr) > flash_size)) {
    9354:	db58      	blt.n	9408 <spi_nor_write+0xc4>
    9356:	eb04 0208 	add.w	r2, r4, r8
    935a:	429a      	cmp	r2, r3
    935c:	d854      	bhi.n	9408 <spi_nor_write+0xc4>
	acquire_device(dev);
    935e:	6900      	ldr	r0, [r0, #16]
    9360:	f7ff ff5f 	bl	9222 <acquire_device.isra.0>
	ret = spi_nor_write_protection_set(dev, false);
    9364:	2100      	movs	r1, #0
    9366:	4630      	mov	r0, r6
    9368:	f7ff ffa8 	bl	92bc <spi_nor_write_protection_set>
	if (ret == 0) {
    936c:	4605      	mov	r5, r0
    936e:	b958      	cbnz	r0, 9388 <spi_nor_write+0x44>
			spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
    9370:	4682      	mov	sl, r0
		while (size > 0) {
    9372:	f1b8 0f00 	cmp.w	r8, #0
    9376:	d112      	bne.n	939e <spi_nor_write+0x5a>
	int ret2 = spi_nor_write_protection_set(dev, true);
    9378:	2101      	movs	r1, #1
    937a:	4630      	mov	r0, r6
    937c:	f7ff ff9e 	bl	92bc <spi_nor_write_protection_set>
    9380:	2d00      	cmp	r5, #0
    9382:	bf08      	it	eq
    9384:	4605      	moveq	r5, r0
    9386:	e003      	b.n	9390 <spi_nor_write+0x4c>
    9388:	2101      	movs	r1, #1
    938a:	4630      	mov	r0, r6
    938c:	f7ff ff96 	bl	92bc <spi_nor_write_protection_set>
	release_device(dev);
    9390:	6930      	ldr	r0, [r6, #16]
    9392:	f7ff ff44 	bl	921e <release_device.isra.0>
}
    9396:	4628      	mov	r0, r5
    9398:	b002      	add	sp, #8
    939a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
			if (to_write >= page_size) {
    939e:	f5b8 7f80 	cmp.w	r8, #256	; 0x100
    93a2:	4647      	mov	r7, r8
    93a4:	bf28      	it	cs
    93a6:	f44f 7780 	movcs.w	r7, #256	; 0x100
			if (((addr + to_write - 1U) / page_size)
    93aa:	19e3      	adds	r3, r4, r7
			!= (addr / page_size)) {
    93ac:	2c00      	cmp	r4, #0
			if (((addr + to_write - 1U) / page_size)
    93ae:	f103 33ff 	add.w	r3, r3, #4294967295
			!= (addr / page_size)) {
    93b2:	4622      	mov	r2, r4
			if (((addr + to_write - 1U) / page_size)
    93b4:	ea4f 2313 	mov.w	r3, r3, lsr #8
			!= (addr / page_size)) {
    93b8:	bfb8      	it	lt
    93ba:	f104 02ff 	addlt.w	r2, r4, #255	; 0xff
			if (((addr + to_write - 1U) / page_size)
    93be:	ebb3 2f22 	cmp.w	r3, r2, asr #8
    93c2:	d006      	beq.n	93d2 <spi_nor_write+0x8e>
				to_write = page_size - (addr % page_size);
    93c4:	4263      	negs	r3, r4
    93c6:	b2db      	uxtb	r3, r3
    93c8:	b2e7      	uxtb	r7, r4
    93ca:	bf58      	it	pl
    93cc:	425f      	negpl	r7, r3
    93ce:	f5c7 7780 	rsb	r7, r7, #256	; 0x100
			spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
    93d2:	2300      	movs	r3, #0
    93d4:	2280      	movs	r2, #128	; 0x80
    93d6:	2106      	movs	r1, #6
    93d8:	e9cd aa00 	strd	sl, sl, [sp]
    93dc:	4630      	mov	r0, r6
    93de:	f7ff ff26 	bl	922e <spi_nor_access>
			ret = spi_nor_cmd_addr_write(dev, SPI_NOR_CMD_PP, addr,
    93e2:	e9cd 9700 	strd	r9, r7, [sp]
    93e6:	4623      	mov	r3, r4
    93e8:	2281      	movs	r2, #129	; 0x81
    93ea:	2102      	movs	r1, #2
    93ec:	4630      	mov	r0, r6
    93ee:	f7ff ff1e 	bl	922e <spi_nor_access>
			if (ret != 0) {
    93f2:	b938      	cbnz	r0, 9404 <spi_nor_write+0xc0>
			spi_nor_wait_until_ready(dev);
    93f4:	4630      	mov	r0, r6
			size -= to_write;
    93f6:	eba8 0807 	sub.w	r8, r8, r7
			src = (const uint8_t *)src + to_write;
    93fa:	44b9      	add	r9, r7
			addr += to_write;
    93fc:	443c      	add	r4, r7
			spi_nor_wait_until_ready(dev);
    93fe:	f7ff ff8d 	bl	931c <spi_nor_wait_until_ready.isra.0>
    9402:	e7b6      	b.n	9372 <spi_nor_write+0x2e>
			ret = spi_nor_cmd_addr_write(dev, SPI_NOR_CMD_PP, addr,
    9404:	4605      	mov	r5, r0
    9406:	e7b7      	b.n	9378 <spi_nor_write+0x34>
		return -EINVAL;
    9408:	f06f 0515 	mvn.w	r5, #21
    940c:	e7c3      	b.n	9396 <spi_nor_write+0x52>

0000940e <is_regular_addr_valid>:
{
    940e:	b538      	push	{r3, r4, r5, lr}
    9410:	4605      	mov	r5, r0
    9412:	460c      	mov	r4, r1
	return is_within_bounds(addr, len, 0, nrfx_nvmc_flash_size_get());
    9414:	f000 fa6c 	bl	98f0 <nrfx_nvmc_flash_size_get>
			(addr < (boundary_start + boundary_size)) &&
    9418:	2d00      	cmp	r5, #0
    941a:	db07      	blt.n	942c <is_regular_addr_valid+0x1e>
	return (addr >= boundary_start &&
    941c:	42a8      	cmp	r0, r5
    941e:	d905      	bls.n	942c <is_regular_addr_valid+0x1e>
			(len <= (boundary_start + boundary_size - addr)));
    9420:	1b40      	subs	r0, r0, r5
			(addr < (boundary_start + boundary_size)) &&
    9422:	4284      	cmp	r4, r0
    9424:	bf8c      	ite	hi
    9426:	2000      	movhi	r0, #0
    9428:	2001      	movls	r0, #1
}
    942a:	bd38      	pop	{r3, r4, r5, pc}
			(addr < (boundary_start + boundary_size)) &&
    942c:	2000      	movs	r0, #0
    942e:	e7fc      	b.n	942a <is_regular_addr_valid+0x1c>

00009430 <flash_get_page_info>:

#include <zephyr/drivers/flash.h>

static int flash_get_page_info(const struct device *dev, off_t offs,
			       uint32_t index, struct flash_pages_info *info)
{
    9430:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    9434:	461c      	mov	r4, r3
    9436:	4690      	mov	r8, r2
	const struct flash_driver_api *api = dev->api;
	const struct flash_pages_layout *layout;
	size_t layout_size;
	uint32_t index_jmp;

	info->start_offset = 0;
    9438:	2300      	movs	r3, #0
	const struct flash_driver_api *api = dev->api;
    943a:	6882      	ldr	r2, [r0, #8]
	info->start_offset = 0;
    943c:	6023      	str	r3, [r4, #0]
	info->index = 0U;
    943e:	60a3      	str	r3, [r4, #8]

	api->page_layout(dev, &layout, &layout_size);
    9440:	6913      	ldr	r3, [r2, #16]
{
    9442:	460d      	mov	r5, r1
	api->page_layout(dev, &layout, &layout_size);
    9444:	aa01      	add	r2, sp, #4
    9446:	4669      	mov	r1, sp
    9448:	4798      	blx	r3

	while (layout_size--) {
    944a:	9b01      	ldr	r3, [sp, #4]
    944c:	1e5a      	subs	r2, r3, #1
    944e:	9201      	str	r2, [sp, #4]
    9450:	b923      	cbnz	r3, 945c <flash_get_page_info+0x2c>
		}

		layout++;
	}

	return -EINVAL; /* page at offs or idx doesn't exist */
    9452:	f06f 0015 	mvn.w	r0, #21
}
    9456:	b002      	add	sp, #8
    9458:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		info->size = layout->pages_size;
    945c:	9800      	ldr	r0, [sp, #0]
			index_jmp = index - info->index;
    945e:	68a2      	ldr	r2, [r4, #8]
		info->size = layout->pages_size;
    9460:	6847      	ldr	r7, [r0, #4]
			index_jmp = (offs - info->start_offset) / info->size;
    9462:	6821      	ldr	r1, [r4, #0]
		info->size = layout->pages_size;
    9464:	6067      	str	r7, [r4, #4]
		if (offs == 0) {
    9466:	b985      	cbnz	r5, 948a <flash_get_page_info+0x5a>
			index_jmp = index - info->index;
    9468:	eba8 0302 	sub.w	r3, r8, r2
		index_jmp = MIN(index_jmp, layout->pages_count);
    946c:	6806      	ldr	r6, [r0, #0]
    946e:	42b3      	cmp	r3, r6
    9470:	bf28      	it	cs
    9472:	4633      	movcs	r3, r6
		info->index += index_jmp;
    9474:	441a      	add	r2, r3
		info->start_offset += (index_jmp * info->size);
    9476:	fb03 1107 	mla	r1, r3, r7, r1
    947a:	6021      	str	r1, [r4, #0]
		info->index += index_jmp;
    947c:	60a2      	str	r2, [r4, #8]
		if (index_jmp < layout->pages_count) {
    947e:	6802      	ldr	r2, [r0, #0]
    9480:	429a      	cmp	r2, r3
    9482:	d806      	bhi.n	9492 <flash_get_page_info+0x62>
		layout++;
    9484:	3008      	adds	r0, #8
    9486:	9000      	str	r0, [sp, #0]
    9488:	e7df      	b.n	944a <flash_get_page_info+0x1a>
			index_jmp = (offs - info->start_offset) / info->size;
    948a:	1a6b      	subs	r3, r5, r1
    948c:	fbb3 f3f7 	udiv	r3, r3, r7
    9490:	e7ec      	b.n	946c <flash_get_page_info+0x3c>
			return 0;
    9492:	2000      	movs	r0, #0
    9494:	e7df      	b.n	9456 <flash_get_page_info+0x26>

00009496 <z_impl_flash_get_page_info_by_offs>:

int z_impl_flash_get_page_info_by_offs(const struct device *dev, off_t offs,
				       struct flash_pages_info *info)
{
    9496:	4613      	mov	r3, r2
	return flash_get_page_info(dev, offs, 0U, info);
    9498:	2200      	movs	r2, #0
    949a:	f7ff bfc9 	b.w	9430 <flash_get_page_info>

0000949e <flash_page_foreach>:
	return count;
}

void flash_page_foreach(const struct device *dev, flash_page_cb cb,
			void *data)
{
    949e:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	const struct flash_pages_layout *layout;
	struct flash_pages_info page_info;
	size_t block, num_blocks, page = 0, i;
	off_t off = 0;

	api->page_layout(dev, &layout, &num_blocks);
    94a2:	6883      	ldr	r3, [r0, #8]
{
    94a4:	b086      	sub	sp, #24
	api->page_layout(dev, &layout, &num_blocks);
    94a6:	691b      	ldr	r3, [r3, #16]
{
    94a8:	4688      	mov	r8, r1
    94aa:	4691      	mov	r9, r2
	api->page_layout(dev, &layout, &num_blocks);
    94ac:	a901      	add	r1, sp, #4
    94ae:	aa02      	add	r2, sp, #8
    94b0:	4798      	blx	r3
	off_t off = 0;
    94b2:	2400      	movs	r4, #0
	size_t block, num_blocks, page = 0, i;
    94b4:	46a2      	mov	sl, r4

	for (block = 0; block < num_blocks; block++) {
    94b6:	4625      	mov	r5, r4
    94b8:	9b02      	ldr	r3, [sp, #8]
    94ba:	42ab      	cmp	r3, r5
    94bc:	d802      	bhi.n	94c4 <flash_page_foreach+0x26>

			off += page_info.size;
			page++;
		}
	}
}
    94be:	b006      	add	sp, #24
    94c0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		const struct flash_pages_layout *l = &layout[block];
    94c4:	9f01      	ldr	r7, [sp, #4]
    94c6:	eb07 07c5 	add.w	r7, r7, r5, lsl #3
		for (i = 0; i < l->pages_count; i++) {
    94ca:	2600      	movs	r6, #0
		page_info.size = l->pages_size;
    94cc:	687b      	ldr	r3, [r7, #4]
    94ce:	9304      	str	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    94d0:	683a      	ldr	r2, [r7, #0]
    94d2:	42b2      	cmp	r2, r6
    94d4:	eb0a 0306 	add.w	r3, sl, r6
    94d8:	d802      	bhi.n	94e0 <flash_page_foreach+0x42>
	for (block = 0; block < num_blocks; block++) {
    94da:	3501      	adds	r5, #1
    94dc:	469a      	mov	sl, r3
    94de:	e7eb      	b.n	94b8 <flash_page_foreach+0x1a>
			page_info.start_offset = off;
    94e0:	9403      	str	r4, [sp, #12]
			page_info.index = page;
    94e2:	9305      	str	r3, [sp, #20]
			if (!cb(&page_info, data)) {
    94e4:	4649      	mov	r1, r9
    94e6:	a803      	add	r0, sp, #12
    94e8:	47c0      	blx	r8
    94ea:	2800      	cmp	r0, #0
    94ec:	d0e7      	beq.n	94be <flash_page_foreach+0x20>
			off += page_info.size;
    94ee:	9b04      	ldr	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    94f0:	3601      	adds	r6, #1
			off += page_info.size;
    94f2:	441c      	add	r4, r3
		for (i = 0; i < l->pages_count; i++) {
    94f4:	e7ec      	b.n	94d0 <flash_page_foreach+0x32>

000094f6 <uarte_nrfx_config_get>:
	struct uarte_nrfx_data *data = dev->data;
    94f6:	6902      	ldr	r2, [r0, #16]
{
    94f8:	460b      	mov	r3, r1
	*cfg = data->uart_config;
    94fa:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    94fe:	e883 0003 	stmia.w	r3, {r0, r1}
}
    9502:	2000      	movs	r0, #0
    9504:	4770      	bx	lr

00009506 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    9506:	6843      	ldr	r3, [r0, #4]
    9508:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    950a:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    950e:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    9512:	4770      	bx	lr

00009514 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    9514:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
    9516:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    9518:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    951a:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    951e:	b150      	cbz	r0, 9536 <uarte_nrfx_poll_in+0x22>
	*c = *data->rx_data;
    9520:	6952      	ldr	r2, [r2, #20]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    9522:	2000      	movs	r0, #0
    9524:	7812      	ldrb	r2, [r2, #0]
    9526:	700a      	strb	r2, [r1, #0]
    9528:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    952c:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    9530:	2201      	movs	r2, #1
    9532:	601a      	str	r2, [r3, #0]
	return 0;
    9534:	4770      	bx	lr
		return -1;
    9536:	f04f 30ff 	mov.w	r0, #4294967295
}
    953a:	4770      	bx	lr

0000953c <is_tx_ready.isra.0>:
	return config->uarte_regs;
    953c:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    953e:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    9540:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    9544:	b940      	cbnz	r0, 9558 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    9546:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    9548:	079b      	lsls	r3, r3, #30
    954a:	d406      	bmi.n	955a <is_tx_ready.isra.0+0x1e>
    954c:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    9550:	3800      	subs	r0, #0
    9552:	bf18      	it	ne
    9554:	2001      	movne	r0, #1
    9556:	4770      	bx	lr
    9558:	2001      	movs	r0, #1
}
    955a:	4770      	bx	lr

0000955c <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
    955c:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    955e:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    9560:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    9564:	05c9      	lsls	r1, r1, #23
    9566:	d518      	bpl.n	959a <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    9568:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    956c:	b1a9      	cbz	r1, 959a <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    956e:	f04f 0020 	mov.w	r0, #32
    9572:	f3ef 8111 	mrs	r1, BASEPRI
    9576:	f380 8812 	msr	BASEPRI_MAX, r0
    957a:	f3bf 8f6f 	isb	sy
    957e:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    9582:	b130      	cbz	r0, 9592 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    9584:	2000      	movs	r0, #0
    9586:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    958a:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    958e:	2001      	movs	r0, #1
    9590:	60d8      	str	r0, [r3, #12]
	__asm__ volatile(
    9592:	f381 8811 	msr	BASEPRI, r1
    9596:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    959a:	6852      	ldr	r2, [r2, #4]
    959c:	06d2      	lsls	r2, r2, #27
    959e:	d515      	bpl.n	95cc <uarte_nrfx_isr_int+0x70>
	__asm__ volatile(
    95a0:	f04f 0120 	mov.w	r1, #32
    95a4:	f3ef 8211 	mrs	r2, BASEPRI
    95a8:	f381 8812 	msr	BASEPRI_MAX, r1
    95ac:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    95b0:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    95b4:	b111      	cbz	r1, 95bc <uarte_nrfx_isr_int+0x60>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    95b6:	2100      	movs	r1, #0
    95b8:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    95bc:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    95c0:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    95c4:	f382 8811 	msr	BASEPRI, r2
    95c8:	f3bf 8f6f 	isb	sy
}
    95cc:	4770      	bx	lr

000095ce <uarte_1_init>:
#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    95ce:	b510      	push	{r4, lr}
    95d0:	2200      	movs	r2, #0
    95d2:	4604      	mov	r4, r0
    95d4:	2101      	movs	r1, #1
    95d6:	2028      	movs	r0, #40	; 0x28
    95d8:	f7f8 fd2e 	bl	2038 <z_arm_irq_priority_set>
    95dc:	2028      	movs	r0, #40	; 0x28
    95de:	f7f8 fcfb 	bl	1fd8 <arch_irq_enable>
    95e2:	4620      	mov	r0, r4
    95e4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    95e8:	f7fa bd1e 	b.w	4028 <uarte_instance_init.constprop.0>

000095ec <uarte_0_init>:
UART_NRF_UARTE_DEVICE(0);
    95ec:	b510      	push	{r4, lr}
    95ee:	2200      	movs	r2, #0
    95f0:	4604      	mov	r4, r0
    95f2:	2101      	movs	r1, #1
    95f4:	2002      	movs	r0, #2
    95f6:	f7f8 fd1f 	bl	2038 <z_arm_irq_priority_set>
    95fa:	2002      	movs	r0, #2
    95fc:	f7f8 fcec 	bl	1fd8 <arch_irq_enable>
    9600:	4620      	mov	r0, r4
    9602:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    9606:	f7fa bd0f 	b.w	4028 <uarte_instance_init.constprop.0>

0000960a <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    960a:	4770      	bx	lr

0000960c <pinctrl_lookup_state>:

#include <zephyr/drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    960c:	b570      	push	{r4, r5, r6, lr}
	*state = &config->states[0];
    960e:	6843      	ldr	r3, [r0, #4]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    9610:	f06f 4660 	mvn.w	r6, #3758096384	; 0xe0000000
	*state = &config->states[0];
    9614:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    9616:	7a05      	ldrb	r5, [r0, #8]
    9618:	6844      	ldr	r4, [r0, #4]
    961a:	4435      	add	r5, r6
    961c:	eb04 04c5 	add.w	r4, r4, r5, lsl #3
    9620:	42a3      	cmp	r3, r4
    9622:	d902      	bls.n	962a <pinctrl_lookup_state+0x1e>
		}

		(*state)++;
	}

	return -ENOENT;
    9624:	f06f 0001 	mvn.w	r0, #1
}
    9628:	bd70      	pop	{r4, r5, r6, pc}
		if (id == (*state)->id) {
    962a:	795c      	ldrb	r4, [r3, #5]
    962c:	428c      	cmp	r4, r1
    962e:	d001      	beq.n	9634 <pinctrl_lookup_state+0x28>
		(*state)++;
    9630:	3308      	adds	r3, #8
    9632:	e7ef      	b.n	9614 <pinctrl_lookup_state+0x8>
			return 0;
    9634:	2000      	movs	r0, #0
    9636:	e7f7      	b.n	9628 <pinctrl_lookup_state+0x1c>

00009638 <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    9638:	f7fd bae8 	b.w	6c0c <nrf_cc3xx_platform_init_no_rng>

0000963c <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    963c:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    963e:	f7f8 fb5b 	bl	1cf8 <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    9642:	f7f8 fc2f 	bl	1ea4 <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    9646:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    964a:	f7fd badf 	b.w	6c0c <nrf_cc3xx_platform_init_no_rng>

0000964e <boot_swap_info_off>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    964e:	6880      	ldr	r0, [r0, #8]
    9650:	3818      	subs	r0, #24
    9652:	f020 0007 	bic.w	r0, r0, #7
}
    9656:	3810      	subs	r0, #16
    9658:	4770      	bx	lr

0000965a <boot_magic_compatible_check>:
    switch (tbl_val) {
    965a:	2804      	cmp	r0, #4
    965c:	d009      	beq.n	9672 <boot_magic_compatible_check+0x18>
    965e:	2805      	cmp	r0, #5
    9660:	d103      	bne.n	966a <boot_magic_compatible_check+0x10>
        return val != BOOT_MAGIC_GOOD;
    9662:	1e48      	subs	r0, r1, #1
    9664:	bf18      	it	ne
    9666:	2001      	movne	r0, #1
    9668:	4770      	bx	lr
        return tbl_val == val;
    966a:	1a43      	subs	r3, r0, r1
    966c:	4258      	negs	r0, r3
    966e:	4158      	adcs	r0, r3
    9670:	4770      	bx	lr
    switch (tbl_val) {
    9672:	2001      	movs	r0, #1
}
    9674:	4770      	bx	lr

00009676 <bootutil_buffer_is_erased>:
{
    9676:	b538      	push	{r3, r4, r5, lr}
    9678:	4615      	mov	r5, r2
    if (buffer == NULL || len == 0) {
    967a:	460c      	mov	r4, r1
    967c:	b161      	cbz	r1, 9698 <bootutil_buffer_is_erased+0x22>
    967e:	b15a      	cbz	r2, 9698 <bootutil_buffer_is_erased+0x22>
    erased_val = flash_area_erased_val(area);
    9680:	f7ff fb7c 	bl	8d7c <flash_area_erased_val>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    9684:	4425      	add	r5, r4
    9686:	4621      	mov	r1, r4
        if (u8b[i] != erased_val) {
    9688:	f811 3b01 	ldrb.w	r3, [r1], #1
    968c:	4283      	cmp	r3, r0
    968e:	d103      	bne.n	9698 <bootutil_buffer_is_erased+0x22>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    9690:	42a9      	cmp	r1, r5
    9692:	d1f9      	bne.n	9688 <bootutil_buffer_is_erased+0x12>
    return true;
    9694:	2001      	movs	r0, #1
}
    9696:	bd38      	pop	{r3, r4, r5, pc}
        return false;
    9698:	2000      	movs	r0, #0
    969a:	e7fc      	b.n	9696 <bootutil_buffer_is_erased+0x20>

0000969c <boot_read_flag>:
{
    969c:	b538      	push	{r3, r4, r5, lr}
    969e:	460c      	mov	r4, r1
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    96a0:	2301      	movs	r3, #1
{
    96a2:	4611      	mov	r1, r2
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    96a4:	4622      	mov	r2, r4
{
    96a6:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    96a8:	f7ff fb21 	bl	8cee <flash_area_read>
    if (rc < 0) {
    96ac:	2800      	cmp	r0, #0
    96ae:	db0f      	blt.n	96d0 <boot_read_flag+0x34>
    if (bootutil_buffer_is_erased(fap, flag, sizeof *flag)) {
    96b0:	2201      	movs	r2, #1
    96b2:	4621      	mov	r1, r4
    96b4:	4628      	mov	r0, r5
    96b6:	f7ff ffde 	bl	9676 <bootutil_buffer_is_erased>
    96ba:	b938      	cbnz	r0, 96cc <boot_read_flag+0x30>
    if (flag != BOOT_FLAG_SET) {
    96bc:	7823      	ldrb	r3, [r4, #0]
    return BOOT_FLAG_SET;
    96be:	2b01      	cmp	r3, #1
        *flag = boot_flag_decode(*flag);
    96c0:	bf14      	ite	ne
    96c2:	2302      	movne	r3, #2
    96c4:	2301      	moveq	r3, #1
    96c6:	7023      	strb	r3, [r4, #0]
    96c8:	2000      	movs	r0, #0
}
    96ca:	bd38      	pop	{r3, r4, r5, pc}
    96cc:	2303      	movs	r3, #3
    96ce:	e7fa      	b.n	96c6 <boot_read_flag+0x2a>
        return BOOT_EFLASH;
    96d0:	2001      	movs	r0, #1
    96d2:	e7fa      	b.n	96ca <boot_read_flag+0x2e>

000096d4 <boot_write_trailer>:
{
    96d4:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    96d8:	461d      	mov	r5, r3
    96da:	4606      	mov	r6, r0
    96dc:	460f      	mov	r7, r1
    96de:	4690      	mov	r8, r2
    align = flash_area_align(fap);
    96e0:	f7ff fb45 	bl	8d6e <flash_area_align>
    align = ALIGN_UP(inlen, align);
    96e4:	1e6c      	subs	r4, r5, #1
    96e6:	4404      	add	r4, r0
    96e8:	4240      	negs	r0, r0
    96ea:	4004      	ands	r4, r0
    if (align > BOOT_MAX_ALIGN) {
    96ec:	2c08      	cmp	r4, #8
    96ee:	d81a      	bhi.n	9726 <boot_write_trailer+0x52>
    erased_val = flash_area_erased_val(fap);
    96f0:	4630      	mov	r0, r6
    96f2:	f7ff fb43 	bl	8d7c <flash_area_erased_val>
    memcpy(buf, inbuf, inlen);
    96f6:	462a      	mov	r2, r5
    erased_val = flash_area_erased_val(fap);
    96f8:	4681      	mov	r9, r0
    memcpy(buf, inbuf, inlen);
    96fa:	4641      	mov	r1, r8
    96fc:	4668      	mov	r0, sp
    96fe:	f7ff fb9a 	bl	8e36 <memcpy>
    memset(&buf[inlen], erased_val, align - inlen);
    9702:	1b62      	subs	r2, r4, r5
    9704:	4649      	mov	r1, r9
    9706:	eb0d 0005 	add.w	r0, sp, r5
    970a:	f7ff fb9f 	bl	8e4c <memset>
    rc = flash_area_write(fap, off, buf, align);
    970e:	4623      	mov	r3, r4
    9710:	466a      	mov	r2, sp
    9712:	4639      	mov	r1, r7
    9714:	4630      	mov	r0, r6
    9716:	f7ff faff 	bl	8d18 <flash_area_write>
    if (rc != 0) {
    971a:	3800      	subs	r0, #0
    971c:	bf18      	it	ne
    971e:	2001      	movne	r0, #1
}
    9720:	b003      	add	sp, #12
    9722:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        return -1;
    9726:	f04f 30ff 	mov.w	r0, #4294967295
    972a:	e7f9      	b.n	9720 <boot_write_trailer+0x4c>

0000972c <boot_write_trailer_flag>:
{
    972c:	b507      	push	{r0, r1, r2, lr}
    return boot_write_trailer(fap, off, buf, 1);
    972e:	2301      	movs	r3, #1
    const uint8_t buf[1] = { flag_val };
    9730:	f88d 2004 	strb.w	r2, [sp, #4]
    return boot_write_trailer(fap, off, buf, 1);
    9734:	aa01      	add	r2, sp, #4
    9736:	f7ff ffcd 	bl	96d4 <boot_write_trailer>
}
    973a:	b003      	add	sp, #12
    973c:	f85d fb04 	ldr.w	pc, [sp], #4

00009740 <boot_write_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    9740:	6881      	ldr	r1, [r0, #8]
    9742:	3918      	subs	r1, #24
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    9744:	2201      	movs	r2, #1
    9746:	f021 0107 	bic.w	r1, r1, #7
    974a:	f7ff bfef 	b.w	972c <boot_write_trailer_flag>

0000974e <boot_read_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    974e:	6882      	ldr	r2, [r0, #8]
    9750:	3a18      	subs	r2, #24
    return boot_read_flag(fap, image_ok, boot_image_ok_off(fap));
    9752:	f022 0207 	bic.w	r2, r2, #7
    9756:	f7ff bfa1 	b.w	969c <boot_read_flag>

0000975a <boot_read_swap_state_by_id>:
{
    975a:	b513      	push	{r0, r1, r4, lr}
    975c:	460c      	mov	r4, r1
    rc = flash_area_open(flash_area_id, &fap);
    975e:	b2c0      	uxtb	r0, r0
    9760:	a901      	add	r1, sp, #4
    9762:	f7f8 f939 	bl	19d8 <flash_area_open>
    if (rc != 0) {
    9766:	b950      	cbnz	r0, 977e <boot_read_swap_state_by_id+0x24>
    rc = boot_read_swap_state(fap, state);
    9768:	4621      	mov	r1, r4
    976a:	9801      	ldr	r0, [sp, #4]
    976c:	f7fb f84a 	bl	4804 <boot_read_swap_state>
    9770:	4604      	mov	r4, r0
    flash_area_close(fap);
    9772:	9801      	ldr	r0, [sp, #4]
    9774:	f7ff faba 	bl	8cec <flash_area_close>
}
    9778:	4620      	mov	r0, r4
    977a:	b002      	add	sp, #8
    977c:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    977e:	2401      	movs	r4, #1
    9780:	e7fa      	b.n	9778 <boot_read_swap_state_by_id+0x1e>

00009782 <boot_write_swap_info>:
{
    9782:	b513      	push	{r0, r1, r4, lr}
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    9784:	ea41 1102 	orr.w	r1, r1, r2, lsl #4
{
    9788:	4604      	mov	r4, r0
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    978a:	f88d 1007 	strb.w	r1, [sp, #7]
    off = boot_swap_info_off(fap);
    978e:	f7ff ff5e 	bl	964e <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    9792:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    9794:	4601      	mov	r1, r0
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    9796:	f10d 0207 	add.w	r2, sp, #7
    979a:	4620      	mov	r0, r4
    979c:	f7ff ff9a 	bl	96d4 <boot_write_trailer>
}
    97a0:	b002      	add	sp, #8
    97a2:	bd10      	pop	{r4, pc}

000097a4 <nrfx_isr>:
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    97a4:	4700      	bx	r0

000097a6 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    97a6:	f000 bab8 	b.w	9d1a <z_impl_k_busy_wait>

000097aa <nrfx_clock_enable>:
{
    97aa:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    97ac:	2000      	movs	r0, #0
    97ae:	f7f8 fc35 	bl	201c <arch_irq_is_enabled>
    97b2:	b908      	cbnz	r0, 97b8 <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    97b4:	f7f8 fc10 	bl	1fd8 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    97b8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    97bc:	2200      	movs	r2, #0
    97be:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    97c2:	bd08      	pop	{r3, pc}

000097c4 <nrfx_clock_start>:
{
    97c4:	b508      	push	{r3, lr}
    switch (domain)
    97c6:	b110      	cbz	r0, 97ce <nrfx_clock_start+0xa>
    97c8:	2801      	cmp	r0, #1
    97ca:	d02c      	beq.n	9826 <nrfx_clock_start+0x62>
}
    97cc:	bd08      	pop	{r3, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    97ce:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    97d2:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    97d6:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    97da:	03c8      	lsls	r0, r1, #15
    97dc:	d40b      	bmi.n	97f6 <nrfx_clock_start+0x32>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    97de:	f8d2 3414 	ldr.w	r3, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    97e2:	07d9      	lsls	r1, r3, #31
    97e4:	d50f      	bpl.n	9806 <nrfx_clock_start+0x42>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    97e6:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    97ea:	079b      	lsls	r3, r3, #30
    97ec:	d408      	bmi.n	9800 <nrfx_clock_start+0x3c>
    p_reg->INTENSET = mask;
    97ee:	2302      	movs	r3, #2
    97f0:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    97f4:	e7ea      	b.n	97cc <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    97f6:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    97fa:	2b01      	cmp	r3, #1
    97fc:	d004      	beq.n	9808 <nrfx_clock_start+0x44>
    97fe:	b113      	cbz	r3, 9806 <nrfx_clock_start+0x42>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    9800:	2000      	movs	r0, #0
    9802:	f7fb fa19 	bl	4c38 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    9806:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    9808:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    980c:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    9810:	2300      	movs	r3, #0
    9812:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    9816:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    981a:	2302      	movs	r3, #2
    981c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    9820:	2301      	movs	r3, #1
    9822:	6093      	str	r3, [r2, #8]
}
    9824:	e7d2      	b.n	97cc <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    9826:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    982a:	2200      	movs	r2, #0
    982c:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    9830:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    9834:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    9838:	6018      	str	r0, [r3, #0]
}
    983a:	e7c7      	b.n	97cc <nrfx_clock_start+0x8>

0000983c <nrfx_clock_stop>:
    clock_stop(domain);
    983c:	f7fb b9fc 	b.w	4c38 <clock_stop>

00009840 <nrf_gpio_reconfigure>:
{
    9840:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    9842:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9844:	a801      	add	r0, sp, #4
{
    9846:	e9dd 4708 	ldrd	r4, r7, [sp, #32]
    984a:	4616      	mov	r6, r2
    984c:	461d      	mov	r5, r3
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    984e:	f7fb fa9b 	bl	4d88 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number];
    9852:	9b01      	ldr	r3, [sp, #4]
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    9854:	f1b6 0c00 	subs.w	ip, r6, #0
    9858:	bf18      	it	ne
    985a:	f04f 0c01 	movne.w	ip, #1
    985e:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    9862:	1e0b      	subs	r3, r1, #0
    9864:	bf18      	it	ne
    9866:	2301      	movne	r3, #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    9868:	2d00      	cmp	r5, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    986a:	ea43 034c 	orr.w	r3, r3, ip, lsl #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    986e:	bf14      	ite	ne
    9870:	f04f 0c0c 	movne.w	ip, #12
    9874:	f04f 0c00 	moveq.w	ip, #0
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    9878:	2c00      	cmp	r4, #0
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    987a:	ea43 030c 	orr.w	r3, r3, ip
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    987e:	bf14      	ite	ne
    9880:	f44f 6ce0 	movne.w	ip, #1792	; 0x700
    9884:	f04f 0c00 	moveq.w	ip, #0
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    9888:	2f00      	cmp	r7, #0
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    988a:	ea43 030c 	orr.w	r3, r3, ip
    uint32_t cnf = reg->PIN_CNF[pin_number];
    988e:	f8d0 2700 	ldr.w	r2, [r0, #1792]	; 0x700
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    9892:	bf14      	ite	ne
    9894:	f44f 3c40 	movne.w	ip, #196608	; 0x30000
    9898:	f04f 0c00 	moveq.w	ip, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    989c:	ea43 030c 	orr.w	r3, r3, ip
    cnf &= ~to_update;
    98a0:	ea22 0303 	bic.w	r3, r2, r3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    98a4:	b101      	cbz	r1, 98a8 <nrf_gpio_reconfigure+0x68>
    98a6:	7809      	ldrb	r1, [r1, #0]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    98a8:	b10e      	cbz	r6, 98ae <nrf_gpio_reconfigure+0x6e>
    98aa:	7836      	ldrb	r6, [r6, #0]
    98ac:	0076      	lsls	r6, r6, #1
    98ae:	4319      	orrs	r1, r3
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    98b0:	b10d      	cbz	r5, 98b6 <nrf_gpio_reconfigure+0x76>
    98b2:	782d      	ldrb	r5, [r5, #0]
    98b4:	00ad      	lsls	r5, r5, #2
    98b6:	4331      	orrs	r1, r6
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    98b8:	b10c      	cbz	r4, 98be <nrf_gpio_reconfigure+0x7e>
    98ba:	7824      	ldrb	r4, [r4, #0]
    98bc:	0224      	lsls	r4, r4, #8
    98be:	4329      	orrs	r1, r5
           ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
    98c0:	b10f      	cbz	r7, 98c6 <nrf_gpio_reconfigure+0x86>
    98c2:	783f      	ldrb	r7, [r7, #0]
    98c4:	043f      	lsls	r7, r7, #16
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    98c6:	430c      	orrs	r4, r1
    98c8:	433c      	orrs	r4, r7
    reg->PIN_CNF[pin_number] = cnf;
    98ca:	f8c0 4700 	str.w	r4, [r0, #1792]	; 0x700
}
    98ce:	b003      	add	sp, #12
    98d0:	bdf0      	pop	{r4, r5, r6, r7, pc}

000098d2 <nrf_gpio_cfg_sense_set>:
{
    98d2:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    98d4:	f10d 030f 	add.w	r3, sp, #15
    98d8:	9301      	str	r3, [sp, #4]
    98da:	2300      	movs	r3, #0
{
    98dc:	f88d 100f 	strb.w	r1, [sp, #15]
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    98e0:	9300      	str	r3, [sp, #0]
    98e2:	461a      	mov	r2, r3
    98e4:	4619      	mov	r1, r3
    98e6:	f7ff ffab 	bl	9840 <nrf_gpio_reconfigure>
}
    98ea:	b005      	add	sp, #20
    98ec:	f85d fb04 	ldr.w	pc, [sp], #4

000098f0 <nrfx_nvmc_flash_size_get>:
    98f0:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    98f4:	691a      	ldr	r2, [r3, #16]
NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk)
    return p_reg->INFO.CODESIZE;
#else
    return p_reg->CODESIZE;
    98f6:	6958      	ldr	r0, [r3, #20]
}

uint32_t nrfx_nvmc_flash_size_get(void)
{
    return flash_total_size_get();
}
    98f8:	4350      	muls	r0, r2
    98fa:	4770      	bx	lr

000098fc <nrfx_nvmc_flash_page_size_get>:
    return p_reg->CODEPAGESIZE;
    98fc:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    9900:	6918      	ldr	r0, [r3, #16]

uint32_t nrfx_nvmc_flash_page_size_get(void)
{
    return flash_page_size_get();
}
    9902:	4770      	bx	lr

00009904 <nrfx_nvmc_flash_page_count_get>:
    return p_reg->CODESIZE;
    9904:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    9908:	6958      	ldr	r0, [r3, #20]

uint32_t nrfx_nvmc_flash_page_count_get(void)
{
    return flash_page_count_get();
}
    990a:	4770      	bx	lr

0000990c <nrf_gpio_cfg_default>:
{
    990c:	b507      	push	{r0, r1, r2, lr}
    990e:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9910:	a801      	add	r0, sp, #4
    9912:	f7fb fde3 	bl	54dc <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    9916:	9b01      	ldr	r3, [sp, #4]
    9918:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    991c:	2202      	movs	r2, #2
    991e:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
}
    9922:	b003      	add	sp, #12
    9924:	f85d fb04 	ldr.w	pc, [sp], #4

00009928 <nrf_gpio_pin_set>:
{
    9928:	b507      	push	{r0, r1, r2, lr}
    992a:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    992c:	a801      	add	r0, sp, #4
    992e:	f7fb fdd5 	bl	54dc <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    9932:	9a01      	ldr	r2, [sp, #4]
    9934:	2301      	movs	r3, #1
    9936:	4093      	lsls	r3, r2
    p_reg->OUTSET = set_mask;
    9938:	f8c0 3508 	str.w	r3, [r0, #1288]	; 0x508
}
    993c:	b003      	add	sp, #12
    993e:	f85d fb04 	ldr.w	pc, [sp], #4

00009942 <nrf_gpio_pin_clear>:
{
    9942:	b507      	push	{r0, r1, r2, lr}
    9944:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9946:	a801      	add	r0, sp, #4
    9948:	f7fb fdc8 	bl	54dc <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    994c:	9a01      	ldr	r2, [sp, #4]
    994e:	2301      	movs	r3, #1
    9950:	4093      	lsls	r3, r2
    p_reg->OUTCLR = clr_mask;
    9952:	f8c0 350c 	str.w	r3, [r0, #1292]	; 0x50c
}
    9956:	b003      	add	sp, #12
    9958:	f85d fb04 	ldr.w	pc, [sp], #4

0000995c <transfer_byte>:
{
    995c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    return p_reg->RXD;
    995e:	f8d0 3518 	ldr.w	r3, [r0, #1304]	; 0x518
    if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length)
    9962:	698a      	ldr	r2, [r1, #24]
    9964:	b2db      	uxtb	r3, r3
    volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
    9966:	f88d 3007 	strb.w	r3, [sp, #7]
    if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length)
    996a:	6a0b      	ldr	r3, [r1, #32]
    996c:	4293      	cmp	r3, r2
        p_cb->evt.xfer_desc.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
    996e:	bf3e      	ittt	cc
    9970:	694a      	ldrcc	r2, [r1, #20]
    9972:	f89d 4007 	ldrbcc.w	r4, [sp, #7]
    9976:	54d4      	strbcc	r4, [r2, r3]
    ++p_cb->bytes_transferred;
    9978:	6a0b      	ldr	r3, [r1, #32]
    if (p_cb->abort)
    997a:	f891 5024 	ldrb.w	r5, [r1, #36]	; 0x24
        if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    997e:	690c      	ldr	r4, [r1, #16]
    ++p_cb->bytes_transferred;
    9980:	1c5a      	adds	r2, r3, #1
    9982:	620a      	str	r2, [r1, #32]
    size_t bytes_used = p_cb->bytes_transferred + 1;
    9984:	3302      	adds	r3, #2
    if (p_cb->abort)
    9986:	b135      	cbz	r5, 9996 <transfer_byte+0x3a>
        if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    9988:	42a3      	cmp	r3, r4
        if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    998a:	698c      	ldr	r4, [r1, #24]
            p_cb->evt.xfer_desc.tx_length = bytes_used;
    998c:	bf38      	it	cc
    998e:	610b      	strcc	r3, [r1, #16]
        if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    9990:	429c      	cmp	r4, r3
            p_cb->evt.xfer_desc.rx_length = bytes_used;
    9992:	bf88      	it	hi
    9994:	618b      	strhi	r3, [r1, #24]
    if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    9996:	690d      	ldr	r5, [r1, #16]
    9998:	429d      	cmp	r5, r3
    999a:	d905      	bls.n	99a8 <transfer_byte+0x4c>
        nrf_spi_txd_set(p_spi, p_cb->evt.xfer_desc.p_tx_buffer[bytes_used]);
    999c:	68ca      	ldr	r2, [r1, #12]
    p_reg->TXD = data;
    999e:	5cd3      	ldrb	r3, [r2, r3]
    99a0:	f8c0 351c 	str.w	r3, [r0, #1308]	; 0x51c
    return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
    99a4:	2001      	movs	r0, #1
    99a6:	e00a      	b.n	99be <transfer_byte+0x62>
    else if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    99a8:	698c      	ldr	r4, [r1, #24]
    99aa:	429c      	cmp	r4, r3
    99ac:	d901      	bls.n	99b2 <transfer_byte+0x56>
    99ae:	7fcb      	ldrb	r3, [r1, #31]
    99b0:	e7f6      	b.n	99a0 <transfer_byte+0x44>
    return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
    99b2:	42aa      	cmp	r2, r5
    99b4:	d3f6      	bcc.n	99a4 <transfer_byte+0x48>
    99b6:	42a2      	cmp	r2, r4
    99b8:	bf2c      	ite	cs
    99ba:	2000      	movcs	r0, #0
    99bc:	2001      	movcc	r0, #1
}
    99be:	b003      	add	sp, #12
    99c0:	bd30      	pop	{r4, r5, pc}

000099c2 <nrf_gpio_pin_set>:
{
    99c2:	b507      	push	{r0, r1, r2, lr}
    99c4:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    99c6:	a801      	add	r0, sp, #4
    99c8:	f7fb ff1a 	bl	5800 <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    99cc:	9a01      	ldr	r2, [sp, #4]
    99ce:	2301      	movs	r3, #1
    99d0:	4093      	lsls	r3, r2
    p_reg->OUTSET = set_mask;
    99d2:	f8c0 3508 	str.w	r3, [r0, #1288]	; 0x508
}
    99d6:	b003      	add	sp, #12
    99d8:	f85d fb04 	ldr.w	pc, [sp], #4

000099dc <nrf_gpio_pin_clear>:
{
    99dc:	b507      	push	{r0, r1, r2, lr}
    99de:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    99e0:	a801      	add	r0, sp, #4
    99e2:	f7fb ff0d 	bl	5800 <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    99e6:	9a01      	ldr	r2, [sp, #4]
    99e8:	2301      	movs	r3, #1
    99ea:	4093      	lsls	r3, r2
    p_reg->OUTCLR = clr_mask;
    99ec:	f8c0 350c 	str.w	r3, [r0, #1292]	; 0x50c
}
    99f0:	b003      	add	sp, #12
    99f2:	f85d fb04 	ldr.w	pc, [sp], #4

000099f6 <spim_pin_uninit>:
    if (pin == NRF_SPIM_PIN_NOT_CONNECTED)
    99f6:	1c43      	adds	r3, r0, #1
{
    99f8:	b507      	push	{r0, r1, r2, lr}
    if (pin == NRF_SPIM_PIN_NOT_CONNECTED)
    99fa:	d009      	beq.n	9a10 <spim_pin_uninit+0x1a>
    nrf_gpio_cfg(
    99fc:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    99fe:	a801      	add	r0, sp, #4
    9a00:	f7fb fefe 	bl	5800 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    9a04:	9b01      	ldr	r3, [sp, #4]
    9a06:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    9a0a:	2202      	movs	r2, #2
    9a0c:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
}
    9a10:	b003      	add	sp, #12
    9a12:	f85d fb04 	ldr.w	pc, [sp], #4

00009a16 <set_ss_pin_state>:
    if (p_cb->use_hw_ss)
    9a16:	7f83      	ldrb	r3, [r0, #30]
    9a18:	075a      	lsls	r2, r3, #29
    9a1a:	d40b      	bmi.n	9a34 <set_ss_pin_state+0x1e>
    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    9a1c:	7fc0      	ldrb	r0, [r0, #31]
    9a1e:	28ff      	cmp	r0, #255	; 0xff
    9a20:	d008      	beq.n	9a34 <set_ss_pin_state+0x1e>
        nrf_gpio_pin_write(p_cb->ss_pin,
    9a22:	079b      	lsls	r3, r3, #30
    9a24:	bf58      	it	pl
    9a26:	f081 0101 	eorpl.w	r1, r1, #1
    if (value == 0)
    9a2a:	b909      	cbnz	r1, 9a30 <set_ss_pin_state+0x1a>
        nrf_gpio_pin_clear(pin_number);
    9a2c:	f7ff bfd6 	b.w	99dc <nrf_gpio_pin_clear>
        nrf_gpio_pin_set(pin_number);
    9a30:	f7ff bfc7 	b.w	99c2 <nrf_gpio_pin_set>
}
    9a34:	4770      	bx	lr

00009a36 <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    9a36:	f7fc b8e9 	b.w	5c0c <_DoInit>

00009a3a <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    9a3a:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    9a3c:	f7ff fffb 	bl	9a36 <SEGGER_RTT_Init>

	return 0;
}
    9a40:	2000      	movs	r0, #0
    9a42:	bd08      	pop	{r3, pc}

00009a44 <z_device_state_init>:

	while (dev < __device_end) {
		z_object_init(dev);
		++dev;
	}
}
    9a44:	4770      	bx	lr

00009a46 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    9a46:	b140      	cbz	r0, 9a5a <z_device_is_ready+0x14>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    9a48:	68c3      	ldr	r3, [r0, #12]
    9a4a:	7858      	ldrb	r0, [r3, #1]
    9a4c:	f010 0001 	ands.w	r0, r0, #1
    9a50:	bf1e      	ittt	ne
    9a52:	7818      	ldrbne	r0, [r3, #0]
    9a54:	fab0 f080 	clzne	r0, r0
    9a58:	0940      	lsrne	r0, r0, #5
}
    9a5a:	4770      	bx	lr

00009a5c <z_early_memset>:
	(void) memset(dst, c, n);
    9a5c:	f7ff b9f6 	b.w	8e4c <memset>

00009a60 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    9a60:	f7ff b9e9 	b.w	8e36 <memcpy>

00009a64 <create_free_list>:
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    9a64:	e9d0 3203 	ldrd	r3, r2, [r0, #12]
    9a68:	4313      	orrs	r3, r2
    9a6a:	f013 0303 	ands.w	r3, r3, #3
    9a6e:	d10c      	bne.n	9a8a <create_free_list+0x26>
	slab->free_list = NULL;
    9a70:	6143      	str	r3, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    9a72:	6881      	ldr	r1, [r0, #8]
    9a74:	4299      	cmp	r1, r3
    9a76:	d801      	bhi.n	9a7c <create_free_list+0x18>
	return 0;
    9a78:	2000      	movs	r0, #0
    9a7a:	4770      	bx	lr
		*(char **)p = slab->free_list;
    9a7c:	6941      	ldr	r1, [r0, #20]
    9a7e:	6011      	str	r1, [r2, #0]
		p += slab->block_size;
    9a80:	68c1      	ldr	r1, [r0, #12]
		slab->free_list = p;
    9a82:	6142      	str	r2, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    9a84:	3301      	adds	r3, #1
		p += slab->block_size;
    9a86:	440a      	add	r2, r1
	for (j = 0U; j < slab->num_blocks; j++) {
    9a88:	e7f3      	b.n	9a72 <create_free_list+0xe>
		return -EINVAL;
    9a8a:	f06f 0015 	mvn.w	r0, #21
}
    9a8e:	4770      	bx	lr

00009a90 <k_mem_slab_init>:
{
    9a90:	b510      	push	{r4, lr}
	slab->block_size = block_size;
    9a92:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->num_used = 0U;
    9a96:	2300      	movs	r3, #0
	slab->buffer = buffer;
    9a98:	6101      	str	r1, [r0, #16]
	slab->num_used = 0U;
    9a9a:	6183      	str	r3, [r0, #24]
{
    9a9c:	4604      	mov	r4, r0
	rc = create_free_list(slab);
    9a9e:	f7ff ffe1 	bl	9a64 <create_free_list>
	if (rc < 0) {
    9aa2:	2800      	cmp	r0, #0
	list->tail = (sys_dnode_t *)list;
    9aa4:	bfa8      	it	ge
    9aa6:	e9c4 4400 	strdge	r4, r4, [r4]
}
    9aaa:	bd10      	pop	{r4, pc}

00009aac <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    9aac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    9aae:	4604      	mov	r4, r0
    9ab0:	460d      	mov	r5, r1
	__asm__ volatile(
    9ab2:	f04f 0320 	mov.w	r3, #32
    9ab6:	f3ef 8611 	mrs	r6, BASEPRI
    9aba:	f383 8812 	msr	BASEPRI_MAX, r3
    9abe:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    9ac2:	6947      	ldr	r7, [r0, #20]
    9ac4:	b977      	cbnz	r7, 9ae4 <k_mem_slab_free+0x38>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    9ac6:	f000 f8b0 	bl	9c2a <z_unpend_first_thread>

		if (pending_thread != NULL) {
    9aca:	b158      	cbz	r0, 9ae4 <k_mem_slab_free+0x38>
			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    9acc:	682a      	ldr	r2, [r5, #0]
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    9ace:	6142      	str	r2, [r0, #20]
    9ad0:	6787      	str	r7, [r0, #120]	; 0x78
			z_ready_thread(pending_thread);
    9ad2:	f000 f89a 	bl	9c0a <z_ready_thread>
			z_reschedule(&slab->lock, key);
    9ad6:	4631      	mov	r1, r6
    9ad8:	f104 0008 	add.w	r0, r4, #8
	slab->num_used--;

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    9adc:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
			z_reschedule(&slab->lock, key);
    9ae0:	f7fc bd94 	b.w	660c <z_reschedule>
	**(char ***) mem = slab->free_list;
    9ae4:	682b      	ldr	r3, [r5, #0]
    9ae6:	6962      	ldr	r2, [r4, #20]
    9ae8:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    9aea:	682b      	ldr	r3, [r5, #0]
    9aec:	6163      	str	r3, [r4, #20]
	slab->num_used--;
    9aee:	69a3      	ldr	r3, [r4, #24]
    9af0:	3b01      	subs	r3, #1
    9af2:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    9af4:	f386 8811 	msr	BASEPRI, r6
    9af8:	f3bf 8f6f 	isb	sy
}
    9afc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00009afe <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    9afe:	f3ef 8005 	mrs	r0, IPSR
}
    9b02:	3800      	subs	r0, #0
    9b04:	bf18      	it	ne
    9b06:	2001      	movne	r0, #1
    9b08:	4770      	bx	lr

00009b0a <k_thread_name_get>:
}
    9b0a:	2000      	movs	r0, #0
    9b0c:	4770      	bx	lr

00009b0e <z_pm_save_idle_exit>:
{
    9b0e:	b508      	push	{r3, lr}
	pm_system_resume();
    9b10:	f7f7 ffe8 	bl	1ae4 <pm_system_resume>
}
    9b14:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    9b18:	f7ff bd77 	b.w	960a <sys_clock_idle_exit>

00009b1c <adjust_owner_prio.isra.0>:
	if (mutex->owner->base.prio != new_prio) {
    9b1c:	f990 300e 	ldrsb.w	r3, [r0, #14]
    9b20:	428b      	cmp	r3, r1
    9b22:	d001      	beq.n	9b28 <adjust_owner_prio.isra.0+0xc>
		return z_set_prio(mutex->owner, new_prio);
    9b24:	f7fc bd2c 	b.w	6580 <z_set_prio>
}
    9b28:	2000      	movs	r0, #0
    9b2a:	4770      	bx	lr

00009b2c <z_impl_k_mutex_init>:
{
    9b2c:	4603      	mov	r3, r0
	mutex->owner = NULL;
    9b2e:	2000      	movs	r0, #0
	mutex->lock_count = 0U;
    9b30:	e9c3 0002 	strd	r0, r0, [r3, #8]
    9b34:	e9c3 3300 	strd	r3, r3, [r3]
}
    9b38:	4770      	bx	lr

00009b3a <z_impl_k_sem_init>:
	CHECKIF(limit == 0U || limit > K_SEM_MAX_LIMIT || initial_count > limit) {
    9b3a:	b13a      	cbz	r2, 9b4c <z_impl_k_sem_init+0x12>
    9b3c:	428a      	cmp	r2, r1
    9b3e:	d305      	bcc.n	9b4c <z_impl_k_sem_init+0x12>
	sem->limit = limit;
    9b40:	e9c0 1202 	strd	r1, r2, [r0, #8]
    9b44:	e9c0 0000 	strd	r0, r0, [r0]
	return 0;
    9b48:	2000      	movs	r0, #0
    9b4a:	4770      	bx	lr
		return -EINVAL;
    9b4c:	f06f 0015 	mvn.w	r0, #21
}
    9b50:	4770      	bx	lr

00009b52 <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    9b52:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    9b56:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    9b58:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    9b5a:	2300      	movs	r3, #0
	node->prev = NULL;
    9b5c:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    9b60:	4770      	bx	lr

00009b62 <unpend_thread_no_timeout>:
{
    9b62:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    9b64:	f7ff fff5 	bl	9b52 <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    9b68:	7b43      	ldrb	r3, [r0, #13]
    9b6a:	f023 0302 	bic.w	r3, r3, #2
    9b6e:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    9b70:	2300      	movs	r3, #0
    9b72:	6083      	str	r3, [r0, #8]
}
    9b74:	bd08      	pop	{r3, pc}

00009b76 <z_thread_timeout>:
{
    9b76:	b510      	push	{r4, lr}
    9b78:	4601      	mov	r1, r0
	__asm__ volatile(
    9b7a:	f04f 0320 	mov.w	r3, #32
    9b7e:	f3ef 8411 	mrs	r4, BASEPRI
    9b82:	f383 8812 	msr	BASEPRI_MAX, r3
    9b86:	f3bf 8f6f 	isb	sy
		if (!killed) {
    9b8a:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
    9b8e:	f013 0f28 	tst.w	r3, #40	; 0x28
    9b92:	d10d      	bne.n	9bb0 <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
    9b94:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    9b98:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
    9b9a:	b10b      	cbz	r3, 9ba0 <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
    9b9c:	f7ff ffe1 	bl	9b62 <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    9ba0:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
    9ba4:	f023 0314 	bic.w	r3, r3, #20
    9ba8:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
    9bac:	f7fc fbf2 	bl	6394 <ready_thread>
	__asm__ volatile(
    9bb0:	f384 8811 	msr	BASEPRI, r4
    9bb4:	f3bf 8f6f 	isb	sy
}
    9bb8:	bd10      	pop	{r4, pc}

00009bba <add_to_waitq_locked>:
{
    9bba:	b538      	push	{r3, r4, r5, lr}
    9bbc:	4604      	mov	r4, r0
    9bbe:	460d      	mov	r5, r1
	unready_thread(thread);
    9bc0:	f7fc fc1c 	bl	63fc <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    9bc4:	7b63      	ldrb	r3, [r4, #13]
    9bc6:	f043 0302 	orr.w	r3, r3, #2
    9bca:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    9bcc:	b1e5      	cbz	r5, 9c08 <add_to_waitq_locked+0x4e>
		thread->base.pended_on = wait_q;
    9bce:	60a5      	str	r5, [r4, #8]
	return list->head == list;
    9bd0:	682b      	ldr	r3, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    9bd2:	429d      	cmp	r5, r3
    9bd4:	d109      	bne.n	9bea <add_to_waitq_locked+0x30>
	sys_dnode_t *const tail = list->tail;
    9bd6:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    9bd8:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    9bdc:	601c      	str	r4, [r3, #0]
	list->tail = node;
    9bde:	606c      	str	r4, [r5, #4]
}
    9be0:	e012      	b.n	9c08 <add_to_waitq_locked+0x4e>
	return (node == list->tail) ? NULL : node->next;
    9be2:	686a      	ldr	r2, [r5, #4]
    9be4:	4293      	cmp	r3, r2
    9be6:	d0f6      	beq.n	9bd6 <add_to_waitq_locked+0x1c>
    9be8:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    9bea:	2b00      	cmp	r3, #0
    9bec:	d0f3      	beq.n	9bd6 <add_to_waitq_locked+0x1c>
	int32_t b1 = thread_1->base.prio;
    9bee:	f994 200e 	ldrsb.w	r2, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    9bf2:	f993 100e 	ldrsb.w	r1, [r3, #14]
	if (b1 != b2) {
    9bf6:	428a      	cmp	r2, r1
    9bf8:	d0f3      	beq.n	9be2 <add_to_waitq_locked+0x28>
		if (z_sched_prio_cmp(thread, t) > 0) {
    9bfa:	4291      	cmp	r1, r2
    9bfc:	ddf1      	ble.n	9be2 <add_to_waitq_locked+0x28>
	sys_dnode_t *const prev = successor->prev;
    9bfe:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    9c00:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    9c04:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    9c06:	605c      	str	r4, [r3, #4]
}
    9c08:	bd38      	pop	{r3, r4, r5, pc}

00009c0a <z_ready_thread>:
{
    9c0a:	b510      	push	{r4, lr}
	__asm__ volatile(
    9c0c:	f04f 0320 	mov.w	r3, #32
    9c10:	f3ef 8411 	mrs	r4, BASEPRI
    9c14:	f383 8812 	msr	BASEPRI_MAX, r3
    9c18:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    9c1c:	f7fc fbba 	bl	6394 <ready_thread>
	__asm__ volatile(
    9c20:	f384 8811 	msr	BASEPRI, r4
    9c24:	f3bf 8f6f 	isb	sy
}
    9c28:	bd10      	pop	{r4, pc}

00009c2a <z_unpend_first_thread>:
{
    9c2a:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    9c2c:	f04f 0320 	mov.w	r3, #32
    9c30:	f3ef 8511 	mrs	r5, BASEPRI
    9c34:	f383 8812 	msr	BASEPRI_MAX, r3
    9c38:	f3bf 8f6f 	isb	sy
	return list->head == list;
    9c3c:	6804      	ldr	r4, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    9c3e:	42a0      	cmp	r0, r4
    9c40:	d00d      	beq.n	9c5e <z_unpend_first_thread+0x34>
		if (thread != NULL) {
    9c42:	b134      	cbz	r4, 9c52 <z_unpend_first_thread+0x28>
			unpend_thread_no_timeout(thread);
    9c44:	4620      	mov	r0, r4
    9c46:	f7ff ff8c 	bl	9b62 <unpend_thread_no_timeout>
    9c4a:	f104 0018 	add.w	r0, r4, #24
    9c4e:	f000 f81e 	bl	9c8e <z_abort_timeout>
	__asm__ volatile(
    9c52:	f385 8811 	msr	BASEPRI, r5
    9c56:	f3bf 8f6f 	isb	sy
}
    9c5a:	4620      	mov	r0, r4
    9c5c:	bd38      	pop	{r3, r4, r5, pc}
    9c5e:	2400      	movs	r4, #0
    9c60:	e7f7      	b.n	9c52 <z_unpend_first_thread+0x28>

00009c62 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    9c62:	4603      	mov	r3, r0
    9c64:	b920      	cbnz	r0, 9c70 <z_reschedule_irqlock+0xe>
    9c66:	f3ef 8205 	mrs	r2, IPSR
    9c6a:	b90a      	cbnz	r2, 9c70 <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    9c6c:	f7f8 ba2e 	b.w	20cc <arch_swap>
    9c70:	f383 8811 	msr	BASEPRI, r3
    9c74:	f3bf 8f6f 	isb	sy
}
    9c78:	4770      	bx	lr

00009c7a <z_reschedule_unlocked>:
	__asm__ volatile(
    9c7a:	f04f 0320 	mov.w	r3, #32
    9c7e:	f3ef 8011 	mrs	r0, BASEPRI
    9c82:	f383 8812 	msr	BASEPRI_MAX, r3
    9c86:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    9c8a:	f7ff bfea 	b.w	9c62 <z_reschedule_irqlock>

00009c8e <z_abort_timeout>:
{
    9c8e:	b510      	push	{r4, lr}
    9c90:	f04f 0220 	mov.w	r2, #32
    9c94:	f3ef 8411 	mrs	r4, BASEPRI
    9c98:	f382 8812 	msr	BASEPRI_MAX, r2
    9c9c:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    9ca0:	6803      	ldr	r3, [r0, #0]
    9ca2:	b13b      	cbz	r3, 9cb4 <z_abort_timeout+0x26>
			remove_timeout(to);
    9ca4:	f7fc fe9e 	bl	69e4 <remove_timeout>
			ret = 0;
    9ca8:	2000      	movs	r0, #0
	__asm__ volatile(
    9caa:	f384 8811 	msr	BASEPRI, r4
    9cae:	f3bf 8f6f 	isb	sy
}
    9cb2:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    9cb4:	f06f 0015 	mvn.w	r0, #21
    9cb8:	e7f7      	b.n	9caa <z_abort_timeout+0x1c>

00009cba <z_get_next_timeout_expiry>:
{
    9cba:	b510      	push	{r4, lr}
	__asm__ volatile(
    9cbc:	f04f 0320 	mov.w	r3, #32
    9cc0:	f3ef 8411 	mrs	r4, BASEPRI
    9cc4:	f383 8812 	msr	BASEPRI_MAX, r3
    9cc8:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    9ccc:	f7fc fe62 	bl	6994 <next_timeout>
	__asm__ volatile(
    9cd0:	f384 8811 	msr	BASEPRI, r4
    9cd4:	f3bf 8f6f 	isb	sy
}
    9cd8:	bd10      	pop	{r4, pc}

00009cda <z_set_timeout_expiry>:
{
    9cda:	b570      	push	{r4, r5, r6, lr}
    9cdc:	4604      	mov	r4, r0
    9cde:	460d      	mov	r5, r1
	__asm__ volatile(
    9ce0:	f04f 0320 	mov.w	r3, #32
    9ce4:	f3ef 8611 	mrs	r6, BASEPRI
    9ce8:	f383 8812 	msr	BASEPRI_MAX, r3
    9cec:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    9cf0:	f7fc fe50 	bl	6994 <next_timeout>
			      || (ticks <= next_to);
    9cf4:	2801      	cmp	r0, #1
    9cf6:	dd07      	ble.n	9d08 <z_set_timeout_expiry+0x2e>
    9cf8:	42a0      	cmp	r0, r4
    9cfa:	db05      	blt.n	9d08 <z_set_timeout_expiry+0x2e>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    9cfc:	42a0      	cmp	r0, r4
    9cfe:	4629      	mov	r1, r5
    9d00:	bfa8      	it	ge
    9d02:	4620      	movge	r0, r4
    9d04:	f7fa fc78 	bl	45f8 <sys_clock_set_timeout>
	__asm__ volatile(
    9d08:	f386 8811 	msr	BASEPRI, r6
    9d0c:	f3bf 8f6f 	isb	sy
}
    9d10:	bd70      	pop	{r4, r5, r6, pc}

00009d12 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    9d12:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    9d14:	f7fc ff5a 	bl	6bcc <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    9d18:	bd08      	pop	{r3, pc}

00009d1a <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    9d1a:	b108      	cbz	r0, 9d20 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    9d1c:	f7f8 bed8 	b.w	2ad0 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    9d20:	4770      	bx	lr

00009d22 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    9d22:	4770      	bx	lr

00009d24 <nrf_cc310_bl_ecdsa_verify_secp256r1>:
    9d24:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    9d28:	9f06      	ldr	r7, [sp, #24]
    9d2a:	4604      	mov	r4, r0
    9d2c:	4615      	mov	r5, r2
    9d2e:	461e      	mov	r6, r3
    9d30:	f7fd f974 	bl	701c <nrf_cc310_bl_ecdsa_verify_init_secp256r1>
    9d34:	b938      	cbnz	r0, 9d46 <nrf_cc310_bl_ecdsa_verify_secp256r1+0x22>
    9d36:	463b      	mov	r3, r7
    9d38:	4632      	mov	r2, r6
    9d3a:	4629      	mov	r1, r5
    9d3c:	4620      	mov	r0, r4
    9d3e:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    9d42:	f7fd b991 	b.w	7068 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1>
    9d46:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00009d4a <PkaInitAndMutexLock>:
    9d4a:	460a      	mov	r2, r1
    9d4c:	2100      	movs	r1, #0
    9d4e:	f7fd bc13 	b.w	7578 <PkaInitPka>

00009d52 <SaSi_PalMemCopy>:
    9d52:	f7ff b870 	b.w	8e36 <memcpy>

00009d56 <SaSi_PalMemSet>:
    9d56:	f7ff b879 	b.w	8e4c <memset>

00009d5a <SaSi_PalMemSetZero>:
    9d5a:	460a      	mov	r2, r1
    9d5c:	2100      	movs	r1, #0
    9d5e:	f7ff b875 	b.w	8e4c <memset>

00009d62 <CRYS_COMMON_ReverseMemcpy32>:
    9d62:	eb01 0282 	add.w	r2, r1, r2, lsl #2
    9d66:	3804      	subs	r0, #4
    9d68:	428a      	cmp	r2, r1
    9d6a:	d101      	bne.n	9d70 <CRYS_COMMON_ReverseMemcpy32+0xe>
    9d6c:	2000      	movs	r0, #0
    9d6e:	4770      	bx	lr
    9d70:	f852 3d04 	ldr.w	r3, [r2, #-4]!
    9d74:	ba1b      	rev	r3, r3
    9d76:	f840 3f04 	str.w	r3, [r0, #4]!
    9d7a:	e7f5      	b.n	9d68 <CRYS_COMMON_ReverseMemcpy32+0x6>
