/*
 * Copyright (c) 2020 TDK Invensense
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_DRIVERS_SENSOR_ICP20100_ICP20100_REG_H_
#define ZEPHYR_DRIVERS_SENSOR_ICP20100_ICP20100_REG_H_

/* BANK 0 */
#define REG_TRIM1_MSB			0x05
#define REG_TRIM2_LSB			0x06
#define REG_TRIM2_MSB			0x07
#define REG_DEVICE_ID			0x0C
#define REG_IO_DRIVE_STRENGTH	0x0D
#define REG_OTP_CONFIG1			0xAC
#define REG_OTP_MR_LSB			0xAD
#define REG_OTP_MR_MSB			0xAE
#define REG_OTP_MRA_LSB			0xAF
#define REG_OTP_MRA_MSB			0xB0
#define REG_OTP_MRB_LSB			0xB1
#define REG_OTP_MRB_MSB			0xB2
#define REG_OTP_ADDRESS			0xB5
#define REG_OTP_COMMAND			0xB6
#define REG_OTP_RDATA			0xB8
#define REG_OTP_STATUS			0xB9
#define REG_OTP_DBG2			0xBC
#define REG_OTP_STATUS2			0xBF
#define REG_MASTER_LOCK			0xBE
#define REG_MODE_SELECT			0xC0
#define REG_INTERRUPT_STATUS	0xC1
#define REG_INTERRUPT_MASK		0xC2
#define REG_FIFO_CONFIG			0xC3
#define REG_FIFO_FILL			0xC4
#define REG_SPI_MODE			0xC5
#define REG_PRESS_ABS_LSB		0xC7
#define REG_PRESS_ABS_MSB		0xC8
#define REG_PRESS_DELTA_LSB		0xC9
#define REG_PRESS_DELTA_MSB		0xCA
#define REG_DEVICE_STATUS		0xCD
#define REG_I3C_INFO			0xCE
#define REG_VERSION				0xD3
#define REG_PRESS_DATA_0		0xFA
#define REG_PRESS_DATA_1		0xFB
#define REG_PRESS_DATA_2		0xFC
#define REG_TEMP_DATA_0			0xFD
#define REG_TEMP_DATA_1			0xFE
#define REG_TEMP_DATA_2			0xFF

#define WHO_AM_I_ICP20100		0x63

/* #define REG_IO_DRIVE_STRENGTH */
#define BIT_IO_DS_2MA			0x00
#define BIT_IO_DS_4MA			0x01
#define BIT_IO_DS_8MA			0x02
#define BIT_IO_DS_12MA			0x03
#define BIT_IO_DS_1_8V			0x00
#define BIT_IO_DS_1_2V			0x04

/* #define REG_OTP_CONFIG1 */
#define BIT_OTP_CONFIG1_WRITE	0x02
#define BIT_OTP_CONFIG1_ENABLE	0x01

/* #define REG_OTP_STATUS */
#define BIT_OTP_STATUS_BUSY		0x01

/* #define REG_OTP_DBG2 */
#define BIT_OTP_DBG2_RESET		0x80

/* #define REG_OTP_STATUS2 */
#define BIT_OTP_STATUS2_BOOT	0x01

/* #define REG_MASTER_LOCK */
#define BIT_MASTER_LOCK_UNLOCK	0x1F
#define BIT_MASTER_LOCK_LOCK	0x00

/* #define REG_MODE_SELECT */
#define BIT_MODE_SELECT_MODE0	0x00
#define BIT_MODE_SELECT_MODE1	0x20
#define BIT_MODE_SELECT_MODE2	0x40
#define BIT_MODE_SELECT_MODE3	0x60
#define BIT_MODE_SELECT_MODE4	0x80
#define BIT_MODE_SELECT_FORCED	0x10
#define BIT_MODE_SELECT_CONTIN	0x08
#define BIT_MODE_SELECT_ACTIVE	0x04
#define BIT_MODE_SELECT_PRESF	0x00
#define BIT_MODE_SELECT_TEMPO	0x01
#define BIT_MODE_SELECT_TEMPF	0x02
#define BIT_MODE_SELECT_PRESO	0x03

/* #define REG_INTERRUPT_STATUS */
/* #define REG_INTERRUPT_MASK */
#define BIT_INT_STATUS_PRESSD	0x40
#define BIT_INT_STATUS_PRESSA	0x20
#define BIT_INT_STATUS_WMK_L	0x08
#define BIT_INT_STATUS_WMK_H	0x04
#define BIT_INT_STATUS_FIFO_U	0x02
#define BIT_INT_STATUS_FIFO_O	0x01

/* #define REG_FIFO_CONFIG */
#define BIT_FIFO_CFG_WM_H_DIS	0x00
#define BIT_FIFO_CFG_WM_H_1		0x10
#define BIT_FIFO_CFG_WM_H_2		0x20
#define BIT_FIFO_CFG_WM_H_3		0x30
#define BIT_FIFO_CFG_WM_H_4		0x40
#define BIT_FIFO_CFG_WM_H_5		0x50
#define BIT_FIFO_CFG_WM_H_6		0x60
#define BIT_FIFO_CFG_WM_H_7		0x70
#define BIT_FIFO_CFG_WM_H_8		0x80
#define BIT_FIFO_CFG_WM_H_9		0x90
#define BIT_FIFO_CFG_WM_H_10	0xA0
#define BIT_FIFO_CFG_WM_H_11	0xB0
#define BIT_FIFO_CFG_WM_H_12	0xC0
#define BIT_FIFO_CFG_WM_H_13	0xD0
#define BIT_FIFO_CFG_WM_H_14	0xE0
#define BIT_FIFO_CFG_WM_H_15	0xF0
#define BIT_FIFO_CFG_WM_L_DIS	0x00
#define BIT_FIFO_CFG_WM_L_1		0x01
#define BIT_FIFO_CFG_WM_L_2		0x02
#define BIT_FIFO_CFG_WM_L_3		0x03
#define BIT_FIFO_CFG_WM_L_4		0x04
#define BIT_FIFO_CFG_WM_L_5		0x05
#define BIT_FIFO_CFG_WM_L_6		0x06
#define BIT_FIFO_CFG_WM_L_7		0x07
#define BIT_FIFO_CFG_WM_L_8		0x08
#define BIT_FIFO_CFG_WM_L_9		0x09
#define BIT_FIFO_CFG_WM_L_10	0x0A
#define BIT_FIFO_CFG_WM_L_11	0x0B
#define BIT_FIFO_CFG_WM_L_12	0x0C
#define BIT_FIFO_CFG_WM_L_13	0x0D
#define BIT_FIFO_CFG_WM_L_14	0x0E
#define BIT_FIFO_CFG_WM_L_15	0x0F

/* #define REG_FIFO_FILL */
#define BIT_FIFO_FLUSH			0x80
#define BIT_FIFO_EMPTY			0x40
#define BIT_FIFO_FULL			0x20
#define BIT_FIFO_FILL_LVL_EMPT	0x00
#define BIT_FIFO_FILL_LVL_1		0x01
#define BIT_FIFO_FILL_LVL_2		0x02
#define BIT_FIFO_FILL_LVL_3		0x03
#define BIT_FIFO_FILL_LVL_4		0x04
#define BIT_FIFO_FILL_LVL_5		0x05
#define BIT_FIFO_FILL_LVL_6		0x06
#define BIT_FIFO_FILL_LVL_7		0x07
#define BIT_FIFO_FILL_LVL_8		0x08
#define BIT_FIFO_FILL_LVL_9		0x09
#define BIT_FIFO_FILL_LVL_10	0x0A
#define BIT_FIFO_FILL_LVL_11	0x0B
#define BIT_FIFO_FILL_LVL_12	0x0C
#define BIT_FIFO_FILL_LVL_13	0x0D
#define BIT_FIFO_FILL_LVL_14	0x0E
#define BIT_FIFO_FILL_LVL_15	0x0F
#define BIT_FIFO_FILL_LVL_FULL	0x10

/* #define REG_SPI_MODE */
#define BIT_SPI_MODE_4_WIRE		0x00
#define BIT_SPI_MODE_3_WIRE		0x01

/* #define REG_DEVICE_STATUS */
#define BIT_SYNC_STATUS_BUSY	0x00
#define BIT_SYNC_STATUS_READY	0x01

/* data definitions */
#define FIFO_PACKET_BYTE_SINGLE		3

/* pressure sensor */
#define PRESSURE_SCALE		40
#define PRESSURE_DIVIDER		131072
/* 25 degC */
#define PRESSURE_OFFSET			70

/* temperature sensor */
#define TEMP_SCALE			65
#define TEMP_DIVIDER		262144
/* 25 degC */
#define TEMP_OFFSET			25

#ifdef SUPPORT_RTC_MODE
#define BASE_SAMPLE_RATE		(RTC_FREQ_HZ / 32)
#else
#define BASE_SAMPLE_RATE		1000
#endif
#define GESTURE_ACCEL_RATE		50
#define ESI_GYRO_RATE			1000
#define MPU_INIT_SENSOR_RATE_LNM	12	/* min Hz in LNM */
#define MPU_INIT_SENSOR_RATE_LPM	3	/* min Hz in LPM */
#define MAX_FIFO_PACKET_READ		16
#define HARDWARE_FIFO_SIZE		96
#define FIFO_SIZE			(HARDWARE_FIFO_SIZE * 7 / 8)
#define POWER_UP_TIME			2000
#define REG_UP_TIME_USEC		100
#define IIO_BUFFER_BYTES		8
#define BYTES_PER_SENSOR		3
#define BYTES_FOR_TEMP			3

/*
 * INT configurations
 * Polarity: 0 -> Active Low, 1 -> Active High
 * Drive circuit: 0 -> Open Drain, 1 -> Push-Pull
 * Mode: 0 -> Pulse, 1 -> Latch
 */
#define INT_POLARITY			1
#define INT_DRIVE_CIRCUIT		1
#define INT_MODE			0

#endif /* __SENSOR_ICM42605_ICP20100_REG__ */
