/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   /Users/bryan/Documents/Projects/zephyr-apps/firefly_node/build__nrf54l15dk_nrf54l15_cpuapp_ns/firefly_node/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   /Users/bryan/ncs/nrf/dts/bindings, $ZEPHYR_BASE/dts/bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /entropy_bt_hci
 *   4   /psa-rng
 *   5   /soc
 *   6   /soc/peripheral@40000000
 *   7   /soc/cpuapp-ppb-bus
 *   8   /soc/cpuapp-ppb-bus/interrupt-controller@e000e100
 *   9   /soc/peripheral@40000000/gpiote@da000
 *   10  /soc/peripheral@40000000/gpio@d8200
 *   11  /soc/peripheral@40000000/gpiote@10c000
 *   12  /soc/peripheral@40000000/gpio@10a000
 *   13  /buttons
 *   14  /buttons/button_0
 *   15  /buttons/button_1
 *   16  /buttons/button_2
 *   17  /buttons/button_3
 *   18  /clocks
 *   19  /clocks/hfxo
 *   20  /clocks/lfxo
 *   21  /cpus
 *   22  /cpus/cpu@0
 *   23  /cpus/cpu@0/itm@e0000000
 *   24  /soc/peripheral@40000000/gpio@50400
 *   25  /leds
 *   26  /leds/led_0
 *   27  /leds/led_1
 *   28  /leds/led_2
 *   29  /leds/led_3
 *   30  /pin-controller
 *   31  /pin-controller/pwm20_default
 *   32  /pin-controller/pwm20_default/group1
 *   33  /pin-controller/pwm20_sleep
 *   34  /pin-controller/pwm20_sleep/group1
 *   35  /pin-controller/spi00_default
 *   36  /pin-controller/spi00_default/group1
 *   37  /pin-controller/spi00_sleep
 *   38  /pin-controller/spi00_sleep/group1
 *   39  /pin-controller/uart20_default
 *   40  /pin-controller/uart20_default/group1
 *   41  /pin-controller/uart20_default/group2
 *   42  /pin-controller/uart20_sleep
 *   43  /pin-controller/uart20_sleep/group1
 *   44  /pin-controller/uart30_default
 *   45  /pin-controller/uart30_default/group1
 *   46  /pin-controller/uart30_default/group2
 *   47  /pin-controller/uart30_sleep
 *   48  /pin-controller/uart30_sleep/group1
 *   49  /soc/peripheral@40000000/pwm@d2000
 *   50  /pwmleds
 *   51  /pwmleds/pwm_led_1
 *   52  /soc/ficr@ffc000
 *   53  /soc/memory@20000000
 *   54  /soc/cpuapp-ppb-bus/timer@e000e010
 *   55  /soc/peripheral@40000000/adc@d5000
 *   56  /soc/peripheral@40000000/clock@10e000
 *   57  /soc/peripheral@40000000/comparator@106000
 *   58  /soc/peripheral@40000000/dppic@42000
 *   59  /soc/peripheral@40000000/dppic@82000
 *   60  /soc/peripheral@40000000/dppic@c2000
 *   61  /soc/peripheral@40000000/dppic@102000
 *   62  /soc/peripheral@40000000/egu@87000
 *   63  /soc/peripheral@40000000/egu@c9000
 *   64  /soc/peripheral@40000000/grtc@e2000
 *   65  /soc/peripheral@40000000/i2c@c6000
 *   66  /soc/peripheral@40000000/i2c@c7000
 *   67  /soc/peripheral@40000000/i2c@c8000
 *   68  /soc/peripheral@40000000/i2c@104000
 *   69  /soc/peripheral@40000000/i2s@dd000
 *   70  /soc/peripheral@40000000/nfct@d6000
 *   71  /soc/peripheral@40000000/pdm@d0000
 *   72  /soc/peripheral@40000000/pdm@d1000
 *   73  /soc/peripheral@40000000/pwm@d3000
 *   74  /soc/peripheral@40000000/pwm@d4000
 *   75  /soc/peripheral@40000000/qdec@e0000
 *   76  /soc/peripheral@40000000/qdec@e1000
 *   77  /soc/peripheral@40000000/spi@c6000
 *   78  /soc/peripheral@40000000/spi@c7000
 *   79  /soc/peripheral@40000000/spi@c8000
 *   80  /soc/peripheral@40000000/spi@104000
 *   81  /soc/peripheral@40000000/temp@d7000
 *   82  /soc/peripheral@40000000/timer@55000
 *   83  /soc/peripheral@40000000/timer@85000
 *   84  /soc/peripheral@40000000/timer@ca000
 *   85  /soc/peripheral@40000000/timer@cb000
 *   86  /soc/peripheral@40000000/timer@cc000
 *   87  /soc/peripheral@40000000/timer@cd000
 *   88  /soc/peripheral@40000000/timer@ce000
 *   89  /soc/peripheral@40000000/uart@4a000
 *   90  /soc/peripheral@40000000/uart@c6000
 *   91  /soc/peripheral@40000000/uart@c7000
 *   92  /soc/peripheral@40000000/uart@c8000
 *   93  /soc/peripheral@40000000/uart@104000
 *   94  /soc/peripheral@40000000/watchdog@109000
 *   95  /soc/peripheral@40000000/power@10e000
 *   96  /soc/peripheral@40000000/power@10e000/gpregret1@51c
 *   97  /soc/peripheral@40000000/power@10e000/gpregret2@520
 *   98  /soc/peripheral@40000000/radio@8a000
 *   99  /soc/peripheral@40000000/radio@8a000/bt_hci_controller
 *   100 /soc/peripheral@40000000/radio@8a000/bt_hci_sdc
 *   101 /soc/peripheral@40000000/radio@8a000/ieee802154
 *   102 /soc/peripheral@40000000/regulator@120000
 *   103 /soc/peripheral@40000000/regulator@120000/regulator@120600
 *   104 /soc/peripheral@40000000/spi@4a000
 *   105 /soc/peripheral@40000000/spi@4a000/mx25r6435f@0
 *   106 /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions
 *   107 /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@0
 *   108 /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@8000
 *   109 /soc/peripheral@40000000/vpr@4c000
 *   110 /soc/peripheral@40000000/vpr@4c000/mailbox@0
 *   111 /soc/peripheral@40000000/vpr@4c000/mailbox@1
 *   112 /soc/rram-controller@5004b000
 *   113 /soc/rram-controller@5004b000/rram@0
 *   114 /soc/rram-controller@5004b000/rram@0/partitions
 *   115 /soc/rram-controller@5004b000/rram@0/partitions/partition@0
 *   116 /soc/rram-controller@5004b000/rram@0/partitions/partition@18000
 *   117 /soc/rram-controller@5004b000/rram@0/partitions/partition@20000
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"

/* Helpers for dealing with node labels: */
#define DT_N_NODELABEL_NUM 0
#define DT_N_FOREACH_NODELABEL(fn) 
#define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_CHILD_NUM 11
#define DT_N_CHILD_NUM_STATUS_OKAY 11
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_clocks) fn(DT_N_S_soc) fn(DT_N_S_chosen) fn(DT_N_S_psa_rng) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_aliases)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_psa_rng) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_psa_rng, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_psa_rng, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_clocks) fn(DT_N_S_soc) fn(DT_N_S_chosen) fn(DT_N_S_psa_rng) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_aliases)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_psa_rng) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_psa_rng, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_psa_rng, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_ORD 0
#define DT_N_ORD_STR_SORTABLE 00000

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /entropy_bt_hci */ \
	4, /* /psa-rng */ \
	5, /* /soc */ \
	13, /* /buttons */ \
	18, /* /clocks */ \
	21, /* /cpus */ \
	25, /* /leds */ \
	30, /* /pin-controller */ \
	50, /* /pwmleds */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_nordic_nrf54l15dk_nrf54l15_cpuapp DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_IRQ_LEVEL 0
#define DT_N_COMPAT_MATCHES_nordic_nrf54l15dk_nrf54l15_cpuapp 1
#define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_COMPAT_MODEL_IDX_0 "nrf54l15dk_nrf54l15-cpuapp"
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"nordic,nrf54l15dk_nrf54l15-cpuapp"}
#define DT_N_P_compatible_IDX_0 "nordic,nrf54l15dk_nrf54l15-cpuapp"
#define DT_N_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf54l15dk_nrf54l15-cpuapp
#define DT_N_P_compatible_IDX_0_STRING_TOKEN nordic_nrf54l15dk_nrf54l15_cpuapp
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF54L15DK_NRF54L15_CPUAPP
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_aliases_NODELABEL_NUM 0
#define DT_N_S_aliases_FOREACH_NODELABEL(fn) 
#define DT_N_S_aliases_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_CHILD_NUM 0
#define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1
#define DT_N_S_aliases_ORD_STR_SORTABLE 00001

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_IRQ_LEVEL 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_chosen_NODELABEL_NUM 0
#define DT_N_S_chosen_FOREACH_NODELABEL(fn) 
#define DT_N_S_chosen_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_CHILD_NUM 0
#define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2
#define DT_N_S_chosen_ORD_STR_SORTABLE 00002

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_IRQ_LEVEL 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /entropy_bt_hci
 *
 * Node identifier: DT_N_S_entropy_bt_hci
 *
 * Binding (compatible = zephyr,bt-hci-entropy):
 *   $ZEPHYR_BASE/dts/bindings/bluetooth/zephyr,bt-hci-entropy.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci"

/* Node's name with unit-address: */
#define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci"

/* Node parent (/) identifier: */
#define DT_N_S_entropy_bt_hci_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_entropy_bt_hci_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_entropy_bt_hci_NODELABEL_NUM 1
#define DT_N_S_entropy_bt_hci_FOREACH_NODELABEL(fn) fn(rng_hci)
#define DT_N_S_entropy_bt_hci_FOREACH_NODELABEL_VARGS(fn, ...) fn(rng_hci, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_entropy_bt_hci_CHILD_NUM 0
#define DT_N_S_entropy_bt_hci_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_entropy_bt_hci_ORD 3
#define DT_N_S_entropy_bt_hci_ORD_STR_SORTABLE 00003

/* Ordinals for what this node depends on directly: */
#define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_entropy_bt_hci_EXISTS 1
#define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci
#define DT_N_NODELABEL_rng_hci            DT_N_S_entropy_bt_hci

/* Macros for properties that are special in the specification: */
#define DT_N_S_entropy_bt_hci_REG_NUM 0
#define DT_N_S_entropy_bt_hci_RANGES_NUM 0
#define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) 
#define DT_N_S_entropy_bt_hci_IRQ_NUM 0
#define DT_N_S_entropy_bt_hci_IRQ_LEVEL 0
#define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_entropy_bt_hci_P_wakeup_source 0
#define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status "okay"
#define DT_N_S_entropy_bt_hci_P_status_STRING_UNQUOTED okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_IDX_0 "okay"
#define DT_N_S_entropy_bt_hci_P_status_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_LEN 1
#define DT_N_S_entropy_bt_hci_P_status_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"}
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_LEN 1
#define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init 0
#define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /psa-rng
 *
 * Node identifier: DT_N_S_psa_rng
 *
 * Binding (compatible = zephyr,psa-crypto-rng):
 *   $ZEPHYR_BASE/dts/bindings/rng/zephyr,psa-crypto-rng.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_psa_rng_PATH "/psa-rng"

/* Node's name with unit-address: */
#define DT_N_S_psa_rng_FULL_NAME "psa-rng"

/* Node parent (/) identifier: */
#define DT_N_S_psa_rng_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_psa_rng_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_psa_rng_NODELABEL_NUM 1
#define DT_N_S_psa_rng_FOREACH_NODELABEL(fn) fn(psa_rng)
#define DT_N_S_psa_rng_FOREACH_NODELABEL_VARGS(fn, ...) fn(psa_rng, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_psa_rng_CHILD_NUM 0
#define DT_N_S_psa_rng_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_psa_rng_FOREACH_CHILD(fn) 
#define DT_N_S_psa_rng_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_psa_rng_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_psa_rng_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_psa_rng_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_psa_rng_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_psa_rng_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_psa_rng_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_psa_rng_ORD 4
#define DT_N_S_psa_rng_ORD_STR_SORTABLE 00004

/* Ordinals for what this node depends on directly: */
#define DT_N_S_psa_rng_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_psa_rng_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_psa_rng_EXISTS 1
#define DT_N_INST_0_zephyr_psa_crypto_rng DT_N_S_psa_rng
#define DT_N_NODELABEL_psa_rng            DT_N_S_psa_rng

/* Macros for properties that are special in the specification: */
#define DT_N_S_psa_rng_REG_NUM 0
#define DT_N_S_psa_rng_RANGES_NUM 0
#define DT_N_S_psa_rng_FOREACH_RANGE(fn) 
#define DT_N_S_psa_rng_IRQ_NUM 0
#define DT_N_S_psa_rng_IRQ_LEVEL 0
#define DT_N_S_psa_rng_COMPAT_MATCHES_zephyr_psa_crypto_rng 1
#define DT_N_S_psa_rng_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_psa_rng_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_psa_rng_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_psa_rng_COMPAT_MODEL_IDX_0 "psa-crypto-rng"
#define DT_N_S_psa_rng_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_psa_rng_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_psa_rng_P_compatible {"zephyr,psa-crypto-rng"}
#define DT_N_S_psa_rng_P_compatible_IDX_0 "zephyr,psa-crypto-rng"
#define DT_N_S_psa_rng_P_compatible_IDX_0_STRING_UNQUOTED zephyr,psa-crypto-rng
#define DT_N_S_psa_rng_P_compatible_IDX_0_STRING_TOKEN zephyr_psa_crypto_rng
#define DT_N_S_psa_rng_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_PSA_CRYPTO_RNG
#define DT_N_S_psa_rng_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_psa_rng_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_psa_rng, compatible, 0)
#define DT_N_S_psa_rng_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_psa_rng, compatible, 0)
#define DT_N_S_psa_rng_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_psa_rng, compatible, 0, __VA_ARGS__)
#define DT_N_S_psa_rng_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_psa_rng, compatible, 0, __VA_ARGS__)
#define DT_N_S_psa_rng_P_compatible_LEN 1
#define DT_N_S_psa_rng_P_compatible_EXISTS 1
#define DT_N_S_psa_rng_P_status "okay"
#define DT_N_S_psa_rng_P_status_STRING_UNQUOTED okay
#define DT_N_S_psa_rng_P_status_STRING_TOKEN okay
#define DT_N_S_psa_rng_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_psa_rng_P_status_IDX_0 "okay"
#define DT_N_S_psa_rng_P_status_IDX_0_EXISTS 1
#define DT_N_S_psa_rng_P_status_ENUM_IDX 1
#define DT_N_S_psa_rng_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_psa_rng_P_status_ENUM_TOKEN okay
#define DT_N_S_psa_rng_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_psa_rng_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_psa_rng, status, 0)
#define DT_N_S_psa_rng_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_psa_rng, status, 0)
#define DT_N_S_psa_rng_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_psa_rng, status, 0, __VA_ARGS__)
#define DT_N_S_psa_rng_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_psa_rng, status, 0, __VA_ARGS__)
#define DT_N_S_psa_rng_P_status_LEN 1
#define DT_N_S_psa_rng_P_status_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_NODELABEL_NUM 0
#define DT_N_S_soc_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_CHILD_NUM 5
#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 5
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_ficr_ffc000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_rram_controller_5004b000) fn(DT_N_S_soc_S_cpuapp_ppb_bus)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ffc000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_cpuapp_ppb_bus)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_ficr_ffc000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_rram_controller_5004b000) fn(DT_N_S_soc_S_cpuapp_ppb_bus)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ffc000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_cpuapp_ppb_bus)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 5
#define DT_N_S_soc_ORD_STR_SORTABLE 00005

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	7, /* /soc/cpuapp-ppb-bus */ \
	52, /* /soc/ficr@ffc000 */ \
	53, /* /soc/memory@20000000 */ \
	112, /* /soc/rram-controller@5004b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_simple_bus DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_IRQ_LEVEL 0
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 1
#define DT_N_S_soc_P_compatible_EXISTS 1
#define DT_N_S_soc_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_PATH "/soc/peripheral@40000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_FULL_NAME "peripheral@40000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_NODELABEL(fn) fn(global_peripherals)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(global_peripherals, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_CHILD_NUM 51
#define DT_N_S_soc_S_peripheral_40000000_CHILD_NUM_STATUS_OKAY 14
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_ORD 6
#define DT_N_S_soc_S_peripheral_40000000_ORD_STR_SORTABLE 00006

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_REQUIRES_ORDS \
	5, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_SUPPORTS_ORDS \
	9, /* /soc/peripheral@40000000/gpiote@da000 */ \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	11, /* /soc/peripheral@40000000/gpiote@10c000 */ \
	12, /* /soc/peripheral@40000000/gpio@10a000 */ \
	24, /* /soc/peripheral@40000000/gpio@50400 */ \
	49, /* /soc/peripheral@40000000/pwm@d2000 */ \
	55, /* /soc/peripheral@40000000/adc@d5000 */ \
	56, /* /soc/peripheral@40000000/clock@10e000 */ \
	57, /* /soc/peripheral@40000000/comparator@106000 */ \
	58, /* /soc/peripheral@40000000/dppic@42000 */ \
	59, /* /soc/peripheral@40000000/dppic@82000 */ \
	60, /* /soc/peripheral@40000000/dppic@c2000 */ \
	61, /* /soc/peripheral@40000000/dppic@102000 */ \
	62, /* /soc/peripheral@40000000/egu@87000 */ \
	63, /* /soc/peripheral@40000000/egu@c9000 */ \
	64, /* /soc/peripheral@40000000/grtc@e2000 */ \
	65, /* /soc/peripheral@40000000/i2c@c6000 */ \
	66, /* /soc/peripheral@40000000/i2c@c7000 */ \
	67, /* /soc/peripheral@40000000/i2c@c8000 */ \
	68, /* /soc/peripheral@40000000/i2c@104000 */ \
	69, /* /soc/peripheral@40000000/i2s@dd000 */ \
	70, /* /soc/peripheral@40000000/nfct@d6000 */ \
	71, /* /soc/peripheral@40000000/pdm@d0000 */ \
	72, /* /soc/peripheral@40000000/pdm@d1000 */ \
	73, /* /soc/peripheral@40000000/pwm@d3000 */ \
	74, /* /soc/peripheral@40000000/pwm@d4000 */ \
	75, /* /soc/peripheral@40000000/qdec@e0000 */ \
	76, /* /soc/peripheral@40000000/qdec@e1000 */ \
	77, /* /soc/peripheral@40000000/spi@c6000 */ \
	78, /* /soc/peripheral@40000000/spi@c7000 */ \
	79, /* /soc/peripheral@40000000/spi@c8000 */ \
	80, /* /soc/peripheral@40000000/spi@104000 */ \
	81, /* /soc/peripheral@40000000/temp@d7000 */ \
	82, /* /soc/peripheral@40000000/timer@55000 */ \
	83, /* /soc/peripheral@40000000/timer@85000 */ \
	84, /* /soc/peripheral@40000000/timer@ca000 */ \
	85, /* /soc/peripheral@40000000/timer@cb000 */ \
	86, /* /soc/peripheral@40000000/timer@cc000 */ \
	87, /* /soc/peripheral@40000000/timer@cd000 */ \
	88, /* /soc/peripheral@40000000/timer@ce000 */ \
	89, /* /soc/peripheral@40000000/uart@4a000 */ \
	90, /* /soc/peripheral@40000000/uart@c6000 */ \
	91, /* /soc/peripheral@40000000/uart@c7000 */ \
	92, /* /soc/peripheral@40000000/uart@c8000 */ \
	93, /* /soc/peripheral@40000000/uart@104000 */ \
	94, /* /soc/peripheral@40000000/watchdog@109000 */ \
	95, /* /soc/peripheral@40000000/power@10e000 */ \
	98, /* /soc/peripheral@40000000/radio@8a000 */ \
	102, /* /soc/peripheral@40000000/regulator@120000 */ \
	104, /* /soc/peripheral@40000000/spi@4a000 */ \
	109, /* /soc/peripheral@40000000/vpr@4c000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_EXISTS 1
#define DT_N_NODELABEL_global_peripherals DT_N_S_soc_S_peripheral_40000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_RANGES_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1073741824 /* 0x40000000 */
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_LENGTH 268435456 /* 0x10000000 */
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_40000000, 0)
#define DT_N_S_soc_S_peripheral_40000000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/cpuapp-ppb-bus
 *
 * Node identifier: DT_N_S_soc_S_cpuapp_ppb_bus
 */

/* Node's full path: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_PATH "/soc/cpuapp-ppb-bus"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_FULL_NAME "cpuapp-ppb-bus"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_NODELABEL_NUM 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_NODELABEL(fn) fn(cpuapp_ppb)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_ppb, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_cpuapp_ppb_bus_CHILD_NUM 2
#define DT_N_S_soc_S_cpuapp_ppb_bus_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_ORD 7
#define DT_N_S_soc_S_cpuapp_ppb_bus_ORD_STR_SORTABLE 00007

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_REQUIRES_ORDS \
	5, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_SUPPORTS_ORDS \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */ \
	54, /* /soc/cpuapp-ppb-bus/timer@e000e010 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_EXISTS 1
#define DT_N_INST_1_simple_bus    DT_N_S_soc_S_cpuapp_ppb_bus
#define DT_N_NODELABEL_cpuapp_ppb DT_N_S_soc_S_cpuapp_ppb_bus

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_REG_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_RANGES_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_IRQ_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_IRQ_LEVEL 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible {"simple-bus"}
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_IDX_0 "simple-bus"
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_IDX_0_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_IDX_0_STRING_TOKEN simple_bus
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_IDX_0_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus, compatible, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_cpuapp_ppb_bus, compatible, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_LEN 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_compatible_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/cpuapp-ppb-bus/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v8m-nvic):
 *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_PATH "/soc/cpuapp-ppb-bus/interrupt-controller@e000e100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"

/* Node parent (/soc/cpuapp-ppb-bus) identifier: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_PARENT DT_N_S_soc_S_cpuapp_ppb_bus

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_NODELABEL_NUM 2
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_NODELABEL(fn) fn(cpuapp_nvic) fn(nvic)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_nvic, __VA_ARGS__) fn(nvic, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_CHILD_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_ORD 8
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00008

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	7, /* /soc/cpuapp-ppb-bus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	9, /* /soc/peripheral@40000000/gpiote@da000 */ \
	11, /* /soc/peripheral@40000000/gpiote@10c000 */ \
	49, /* /soc/peripheral@40000000/pwm@d2000 */ \
	55, /* /soc/peripheral@40000000/adc@d5000 */ \
	56, /* /soc/peripheral@40000000/clock@10e000 */ \
	57, /* /soc/peripheral@40000000/comparator@106000 */ \
	62, /* /soc/peripheral@40000000/egu@87000 */ \
	63, /* /soc/peripheral@40000000/egu@c9000 */ \
	64, /* /soc/peripheral@40000000/grtc@e2000 */ \
	65, /* /soc/peripheral@40000000/i2c@c6000 */ \
	66, /* /soc/peripheral@40000000/i2c@c7000 */ \
	67, /* /soc/peripheral@40000000/i2c@c8000 */ \
	68, /* /soc/peripheral@40000000/i2c@104000 */ \
	69, /* /soc/peripheral@40000000/i2s@dd000 */ \
	70, /* /soc/peripheral@40000000/nfct@d6000 */ \
	71, /* /soc/peripheral@40000000/pdm@d0000 */ \
	72, /* /soc/peripheral@40000000/pdm@d1000 */ \
	73, /* /soc/peripheral@40000000/pwm@d3000 */ \
	74, /* /soc/peripheral@40000000/pwm@d4000 */ \
	75, /* /soc/peripheral@40000000/qdec@e0000 */ \
	76, /* /soc/peripheral@40000000/qdec@e1000 */ \
	77, /* /soc/peripheral@40000000/spi@c6000 */ \
	78, /* /soc/peripheral@40000000/spi@c7000 */ \
	79, /* /soc/peripheral@40000000/spi@c8000 */ \
	80, /* /soc/peripheral@40000000/spi@104000 */ \
	81, /* /soc/peripheral@40000000/temp@d7000 */ \
	82, /* /soc/peripheral@40000000/timer@55000 */ \
	83, /* /soc/peripheral@40000000/timer@85000 */ \
	84, /* /soc/peripheral@40000000/timer@ca000 */ \
	85, /* /soc/peripheral@40000000/timer@cb000 */ \
	86, /* /soc/peripheral@40000000/timer@cc000 */ \
	87, /* /soc/peripheral@40000000/timer@cd000 */ \
	88, /* /soc/peripheral@40000000/timer@ce000 */ \
	89, /* /soc/peripheral@40000000/uart@4a000 */ \
	90, /* /soc/peripheral@40000000/uart@c6000 */ \
	91, /* /soc/peripheral@40000000/uart@c7000 */ \
	92, /* /soc/peripheral@40000000/uart@c8000 */ \
	93, /* /soc/peripheral@40000000/uart@104000 */ \
	94, /* /soc/peripheral@40000000/watchdog@109000 */ \
	95, /* /soc/peripheral@40000000/power@10e000 */ \
	98, /* /soc/peripheral@40000000/radio@8a000 */ \
	104, /* /soc/peripheral@40000000/spi@4a000 */ \
	111, /* /soc/peripheral@40000000/vpr@4c000/mailbox@1 */ \
	112, /* /soc/rram-controller@5004b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v8m_nvic   DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_cpuapp_nvic DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic        DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_RANGES_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_IRQ_LEVEL 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v8m-nvic"
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_wakeup_source 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v8m-nvic
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v8m_nvic
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V8M_NVIC
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/gpiote@da000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_PATH "/soc/peripheral@40000000/gpiote@da000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FULL_NAME "gpiote@da000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_CHILD_IDX 35

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_NODELABEL(fn) fn(gpiote20)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiote20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_ORD 9
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_ORD_STR_SORTABLE 00009

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_SUPPORTS_ORDS \
	10, /* /soc/peripheral@40000000/gpio@d8200 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000
#define DT_N_NODELABEL_gpiote20       DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_REG_IDX_0_VAL_ADDRESS 1074634752 /* 0x400da000 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_VAL_irq 218
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_reg {892928 /* 0xda000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_reg_IDX_0 892928
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_interrupts {218 /* 0xda */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_interrupts_IDX_0 218
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_instance 20
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000_P_instance_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/gpio@d8200
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_PATH "/soc/peripheral@40000000/gpio@d8200"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FULL_NAME "gpio@d8200"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_CHILD_IDX 34

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_NODELABEL(fn) fn(gpio1)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_ORD 10
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_ORD_STR_SORTABLE 00010

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	9, /* /soc/peripheral@40000000/gpiote@da000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_SUPPORTS_ORDS \
	13, /* /buttons */ \
	14, /* /buttons/button_0 */ \
	15, /* /buttons/button_1 */ \
	16, /* /buttons/button_2 */ \
	25, /* /leds */ \
	27, /* /leds/led_1 */ \
	29, /* /leds/led_3 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
#define DT_N_NODELABEL_gpio1        DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_REG_IDX_0_VAL_ADDRESS 1074627072 /* 0x400d8200 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_ngpios 16
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_reg {885248 /* 0xd8200 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_reg_IDX_0 885248
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_IDX_0 DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_gpiote_instance_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_port 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200_P_port_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/gpiote@10c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_PATH "/soc/peripheral@40000000/gpiote@10c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FULL_NAME "gpiote@10c000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_CHILD_IDX 47

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_NODELABEL(fn) fn(gpiote30)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiote30, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_ORD 11
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_ORD_STR_SORTABLE 00011

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_SUPPORTS_ORDS \
	12, /* /soc/peripheral@40000000/gpio@10a000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpiote DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000
#define DT_N_NODELABEL_gpiote30       DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_REG_IDX_0_VAL_ADDRESS 1074839552 /* 0x4010c000 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_VAL_irq 268
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_reg {1097728 /* 0x10c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_reg_IDX_0 1097728
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_interrupts {268 /* 0x10c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_interrupts_IDX_0 268
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_instance 30
#define DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000_P_instance_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/gpio@10a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_PATH "/soc/peripheral@40000000/gpio@10a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FULL_NAME "gpio@10a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_CHILD_IDX 46

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_NODELABEL(fn) fn(gpio0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_ORD 12
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_ORD_STR_SORTABLE 00012

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	11, /* /soc/peripheral@40000000/gpiote@10c000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_SUPPORTS_ORDS \
	13, /* /buttons */ \
	17, /* /buttons/button_3 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_gpio DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_REG_IDX_0_VAL_ADDRESS 1074831360 /* 0x4010a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_ngpios 5
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_reg {1089536 /* 0x10a000 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_reg_IDX_0 1089536
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_IDX_0 DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_gpiote_instance_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_port 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000_P_port_EXISTS 1

/*
 * Devicetree node: /buttons
 *
 * Node identifier: DT_N_S_buttons
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE/dts/bindings/input/gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_PATH "/buttons"

/* Node's name with unit-address: */
#define DT_N_S_buttons_FULL_NAME "buttons"

/* Node parent (/) identifier: */
#define DT_N_S_buttons_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_buttons_NODELABEL_NUM 0
#define DT_N_S_buttons_FOREACH_NODELABEL(fn) 
#define DT_N_S_buttons_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_CHILD_NUM 4
#define DT_N_S_buttons_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
#define DT_N_S_buttons_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_buttons_ORD 13
#define DT_N_S_buttons_ORD_STR_SORTABLE 00013

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_REQUIRES_ORDS \
	0, /* / */ \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	12, /* /soc/peripheral@40000000/gpio@10a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_SUPPORTS_ORDS \
	14, /* /buttons/button_0 */ \
	15, /* /buttons/button_1 */ \
	16, /* /buttons/button_2 */ \
	17, /* /buttons/button_3 */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_buttons

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_REG_NUM 0
#define DT_N_S_buttons_RANGES_NUM 0
#define DT_N_S_buttons_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_IRQ_NUM 0
#define DT_N_S_buttons_IRQ_LEVEL 0
#define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_buttons_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_P_wakeup_source 0
#define DT_N_S_buttons_P_wakeup_source_EXISTS 1
#define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_buttons_P_compatible {"gpio-keys"}
#define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_buttons_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys
#define DT_N_S_buttons_P_compatible_IDX_0_STRING_TOKEN gpio_keys
#define DT_N_S_buttons_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS
#define DT_N_S_buttons_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons, compatible, 0)
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons, compatible, 0)
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
#define DT_N_S_buttons_P_compatible_LEN 1
#define DT_N_S_buttons_P_compatible_EXISTS 1
#define DT_N_S_buttons_P_zephyr_deferred_init 0
#define DT_N_S_buttons_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_buttons_P_debounce_interval_ms 30
#define DT_N_S_buttons_P_debounce_interval_ms_EXISTS 1
#define DT_N_S_buttons_P_polling_mode 0
#define DT_N_S_buttons_P_polling_mode_EXISTS 1

/*
 * Devicetree node: /buttons/button_0
 *
 * Node identifier: DT_N_S_buttons_S_button_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_0_PATH "/buttons/button_0"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_0_FULL_NAME "button_0"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_buttons_S_button_0_NODELABEL_NUM 1
#define DT_N_S_buttons_S_button_0_FOREACH_NODELABEL(fn) fn(button0)
#define DT_N_S_buttons_S_button_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(button0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_0_CHILD_NUM 0
#define DT_N_S_buttons_S_button_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_0_ORD 14
#define DT_N_S_buttons_S_button_0_ORD_STR_SORTABLE 00014

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_0_REQUIRES_ORDS \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	13, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_0_EXISTS 1
#define DT_N_ALIAS_sw0         DT_N_S_buttons_S_button_0
#define DT_N_NODELABEL_button0 DT_N_S_buttons_S_button_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_0_REG_NUM 0
#define DT_N_S_buttons_S_button_0_RANGES_NUM 0
#define DT_N_S_buttons_S_button_0_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_0_IRQ_NUM 0
#define DT_N_S_buttons_S_button_0_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 13
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, gpios, 0)
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, gpios, 0)
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_label "Push button 0"
#define DT_N_S_buttons_S_button_0_P_label_STRING_UNQUOTED Push button 0
#define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN Push_button_0
#define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_0
#define DT_N_S_buttons_S_button_0_P_label_IDX_0 "Push button 0"
#define DT_N_S_buttons_S_button_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, label, 0)
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, label, 0)
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_label_LEN 1
#define DT_N_S_buttons_S_button_0_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_zephyr_code 11
#define DT_N_S_buttons_S_button_0_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /buttons/button_1
 *
 * Node identifier: DT_N_S_buttons_S_button_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_1_PATH "/buttons/button_1"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_1_FULL_NAME "button_1"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_1_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_buttons_S_button_1_NODELABEL_NUM 1
#define DT_N_S_buttons_S_button_1_FOREACH_NODELABEL(fn) fn(button1)
#define DT_N_S_buttons_S_button_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(button1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_1_CHILD_NUM 0
#define DT_N_S_buttons_S_button_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_1_ORD 15
#define DT_N_S_buttons_S_button_1_ORD_STR_SORTABLE 00015

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_1_REQUIRES_ORDS \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	13, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_1_EXISTS 1
#define DT_N_ALIAS_sw1         DT_N_S_buttons_S_button_1
#define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_1_REG_NUM 0
#define DT_N_S_buttons_S_button_1_RANGES_NUM 0
#define DT_N_S_buttons_S_button_1_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_1_IRQ_NUM 0
#define DT_N_S_buttons_S_button_1_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 9
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, gpios, 0)
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, gpios, 0)
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_label "Push button 1"
#define DT_N_S_buttons_S_button_1_P_label_STRING_UNQUOTED Push button 1
#define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN Push_button_1
#define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_1
#define DT_N_S_buttons_S_button_1_P_label_IDX_0 "Push button 1"
#define DT_N_S_buttons_S_button_1_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, label, 0)
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, label, 0)
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_label_LEN 1
#define DT_N_S_buttons_S_button_1_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_zephyr_code 2
#define DT_N_S_buttons_S_button_1_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /buttons/button_2
 *
 * Node identifier: DT_N_S_buttons_S_button_2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_2_PATH "/buttons/button_2"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_2_FULL_NAME "button_2"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_2_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_buttons_S_button_2_NODELABEL_NUM 1
#define DT_N_S_buttons_S_button_2_FOREACH_NODELABEL(fn) fn(button2)
#define DT_N_S_buttons_S_button_2_FOREACH_NODELABEL_VARGS(fn, ...) fn(button2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_2_CHILD_NUM 0
#define DT_N_S_buttons_S_button_2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_2_ORD 16
#define DT_N_S_buttons_S_button_2_ORD_STR_SORTABLE 00016

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_2_REQUIRES_ORDS \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	13, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_2_EXISTS 1
#define DT_N_ALIAS_sw2         DT_N_S_buttons_S_button_2
#define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_2_REG_NUM 0
#define DT_N_S_buttons_S_button_2_RANGES_NUM 0
#define DT_N_S_buttons_S_button_2_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_2_IRQ_NUM 0
#define DT_N_S_buttons_S_button_2_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 8
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, gpios, 0)
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, gpios, 0)
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_label "Push button 2"
#define DT_N_S_buttons_S_button_2_P_label_STRING_UNQUOTED Push button 2
#define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN Push_button_2
#define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_2
#define DT_N_S_buttons_S_button_2_P_label_IDX_0 "Push button 2"
#define DT_N_S_buttons_S_button_2_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, label, 0)
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, label, 0)
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_label_LEN 1
#define DT_N_S_buttons_S_button_2_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_zephyr_code 3
#define DT_N_S_buttons_S_button_2_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /buttons/button_3
 *
 * Node identifier: DT_N_S_buttons_S_button_3
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_3_PATH "/buttons/button_3"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_3_FULL_NAME "button_3"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_3_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_buttons_S_button_3_NODELABEL_NUM 1
#define DT_N_S_buttons_S_button_3_FOREACH_NODELABEL(fn) fn(button3)
#define DT_N_S_buttons_S_button_3_FOREACH_NODELABEL_VARGS(fn, ...) fn(button3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_3_CHILD_NUM 0
#define DT_N_S_buttons_S_button_3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_3_ORD 17
#define DT_N_S_buttons_S_button_3_ORD_STR_SORTABLE 00017

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_3_REQUIRES_ORDS \
	12, /* /soc/peripheral@40000000/gpio@10a000 */ \
	13, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_3_EXISTS 1
#define DT_N_ALIAS_sw3         DT_N_S_buttons_S_button_3
#define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_3_REG_NUM 0
#define DT_N_S_buttons_S_button_3_RANGES_NUM 0
#define DT_N_S_buttons_S_button_3_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_3_IRQ_NUM 0
#define DT_N_S_buttons_S_button_3_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_3_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 4
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, gpios, 0)
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, gpios, 0)
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_label "Push button 3"
#define DT_N_S_buttons_S_button_3_P_label_STRING_UNQUOTED Push button 3
#define DT_N_S_buttons_S_button_3_P_label_STRING_TOKEN Push_button_3
#define DT_N_S_buttons_S_button_3_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_3
#define DT_N_S_buttons_S_button_3_P_label_IDX_0 "Push button 3"
#define DT_N_S_buttons_S_button_3_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, label, 0)
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, label, 0)
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_label_LEN 1
#define DT_N_S_buttons_S_button_3_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_zephyr_code 4
#define DT_N_S_buttons_S_button_3_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /clocks
 *
 * Node identifier: DT_N_S_clocks
 */

/* Node's full path: */
#define DT_N_S_clocks_PATH "/clocks"

/* Node's name with unit-address: */
#define DT_N_S_clocks_FULL_NAME "clocks"

/* Node parent (/) identifier: */
#define DT_N_S_clocks_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_NODELABEL_NUM 0
#define DT_N_S_clocks_FOREACH_NODELABEL(fn) 
#define DT_N_S_clocks_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_CHILD_NUM 2
#define DT_N_S_clocks_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_clocks_FOREACH_CHILD(fn) fn(DT_N_S_clocks_S_lfxo) fn(DT_N_S_clocks_S_hfxo)
#define DT_N_S_clocks_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_clocks_S_lfxo) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_hfxo)
#define DT_N_S_clocks_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__) fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_clocks_S_lfxo) fn(DT_N_S_clocks_S_hfxo)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_clocks_S_lfxo) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_hfxo)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__) fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_clocks_ORD 18
#define DT_N_S_clocks_ORD_STR_SORTABLE 00018

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_SUPPORTS_ORDS \
	19, /* /clocks/hfxo */ \
	20, /* /clocks/lfxo */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_REG_NUM 0
#define DT_N_S_clocks_RANGES_NUM 0
#define DT_N_S_clocks_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_IRQ_NUM 0
#define DT_N_S_clocks_IRQ_LEVEL 0
#define DT_N_S_clocks_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /clocks/hfxo
 *
 * Node identifier: DT_N_S_clocks_S_hfxo
 *
 * Binding (compatible = nordic,nrf-hfxo):
 *   $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf-hfxo.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_hfxo_PATH "/clocks/hfxo"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_hfxo_FULL_NAME "hfxo"

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_hfxo_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_hfxo_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_hfxo_NODELABEL_NUM 1
#define DT_N_S_clocks_S_hfxo_FOREACH_NODELABEL(fn) fn(hfxo)
#define DT_N_S_clocks_S_hfxo_FOREACH_NODELABEL_VARGS(fn, ...) fn(hfxo, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_hfxo_CHILD_NUM 0
#define DT_N_S_clocks_S_hfxo_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_hfxo_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_hfxo_ORD 19
#define DT_N_S_clocks_S_hfxo_ORD_STR_SORTABLE 00019

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_hfxo_REQUIRES_ORDS \
	18, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_hfxo_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_hfxo_EXISTS 1
#define DT_N_INST_0_nordic_nrf_hfxo DT_N_S_clocks_S_hfxo
#define DT_N_NODELABEL_hfxo         DT_N_S_clocks_S_hfxo

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_hfxo_REG_NUM 0
#define DT_N_S_clocks_S_hfxo_RANGES_NUM 0
#define DT_N_S_clocks_S_hfxo_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_hfxo_IRQ_NUM 0
#define DT_N_S_clocks_S_hfxo_IRQ_LEVEL 0
#define DT_N_S_clocks_S_hfxo_COMPAT_MATCHES_nordic_nrf_hfxo 1
#define DT_N_S_clocks_S_hfxo_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_hfxo_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_clocks_S_hfxo_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_hfxo_COMPAT_MODEL_IDX_0 "nrf-hfxo"
#define DT_N_S_clocks_S_hfxo_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_hfxo_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_hfxo_P_wakeup_source 0
#define DT_N_S_clocks_S_hfxo_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_hfxo_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_compatible {"nordic,nrf-hfxo"}
#define DT_N_S_clocks_S_hfxo_P_compatible_IDX_0 "nordic,nrf-hfxo"
#define DT_N_S_clocks_S_hfxo_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-hfxo
#define DT_N_S_clocks_S_hfxo_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_hfxo
#define DT_N_S_clocks_S_hfxo_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_HFXO
#define DT_N_S_clocks_S_hfxo_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_hfxo, compatible, 0)
#define DT_N_S_clocks_S_hfxo_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_hfxo, compatible, 0)
#define DT_N_S_clocks_S_hfxo_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_hfxo, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_hfxo_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_hfxo, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_hfxo_P_compatible_LEN 1
#define DT_N_S_clocks_S_hfxo_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_hfxo_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_clock_frequency 32000000
#define DT_N_S_clocks_S_hfxo_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_load_capacitors "internal"
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_STRING_UNQUOTED internal
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_STRING_TOKEN internal
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_STRING_UPPER_TOKEN INTERNAL
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_IDX_0 "internal"
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_ENUM_IDX 0
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_ENUM_VAL_internal_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_ENUM_TOKEN internal
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_ENUM_UPPER_TOKEN INTERNAL
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_hfxo, load_capacitors, 0)
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_hfxo, load_capacitors, 0)
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_hfxo, load_capacitors, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_hfxo, load_capacitors, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_LEN 1
#define DT_N_S_clocks_S_hfxo_P_load_capacitors_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_load_capacitance_femtofarad 15000
#define DT_N_S_clocks_S_hfxo_P_load_capacitance_femtofarad_ENUM_IDX 44
#define DT_N_S_clocks_S_hfxo_P_load_capacitance_femtofarad_ENUM_VAL_15000_EXISTS 1
#define DT_N_S_clocks_S_hfxo_P_load_capacitance_femtofarad_EXISTS 1

/*
 * Devicetree node: /clocks/lfxo
 *
 * Node identifier: DT_N_S_clocks_S_lfxo
 *
 * Binding (compatible = nordic,nrf-lfxo):
 *   $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf-lfxo.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_lfxo_PATH "/clocks/lfxo"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_lfxo_FULL_NAME "lfxo"

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_lfxo_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_lfxo_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_lfxo_NODELABEL_NUM 1
#define DT_N_S_clocks_S_lfxo_FOREACH_NODELABEL(fn) fn(lfxo)
#define DT_N_S_clocks_S_lfxo_FOREACH_NODELABEL_VARGS(fn, ...) fn(lfxo, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_lfxo_CHILD_NUM 0
#define DT_N_S_clocks_S_lfxo_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_lfxo_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_lfxo_ORD 20
#define DT_N_S_clocks_S_lfxo_ORD_STR_SORTABLE 00020

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_lfxo_REQUIRES_ORDS \
	18, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_lfxo_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_lfxo_EXISTS 1
#define DT_N_INST_0_nordic_nrf_lfxo DT_N_S_clocks_S_lfxo
#define DT_N_NODELABEL_lfxo         DT_N_S_clocks_S_lfxo

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_lfxo_REG_NUM 0
#define DT_N_S_clocks_S_lfxo_RANGES_NUM 0
#define DT_N_S_clocks_S_lfxo_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_lfxo_IRQ_NUM 0
#define DT_N_S_clocks_S_lfxo_IRQ_LEVEL 0
#define DT_N_S_clocks_S_lfxo_COMPAT_MATCHES_nordic_nrf_lfxo 1
#define DT_N_S_clocks_S_lfxo_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_lfxo_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_clocks_S_lfxo_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_lfxo_COMPAT_MODEL_IDX_0 "nrf-lfxo"
#define DT_N_S_clocks_S_lfxo_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_lfxo_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_lfxo_P_wakeup_source 0
#define DT_N_S_clocks_S_lfxo_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_lfxo_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_compatible {"nordic,nrf-lfxo"}
#define DT_N_S_clocks_S_lfxo_P_compatible_IDX_0 "nordic,nrf-lfxo"
#define DT_N_S_clocks_S_lfxo_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-lfxo
#define DT_N_S_clocks_S_lfxo_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_lfxo
#define DT_N_S_clocks_S_lfxo_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_LFXO
#define DT_N_S_clocks_S_lfxo_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_lfxo, compatible, 0)
#define DT_N_S_clocks_S_lfxo_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_lfxo, compatible, 0)
#define DT_N_S_clocks_S_lfxo_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_lfxo, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_lfxo_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_lfxo, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_lfxo_P_compatible_LEN 1
#define DT_N_S_clocks_S_lfxo_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_lfxo_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_clock_frequency 32768
#define DT_N_S_clocks_S_lfxo_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_load_capacitors "internal"
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_STRING_UNQUOTED internal
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_STRING_TOKEN internal
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_STRING_UPPER_TOKEN INTERNAL
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_IDX_0 "internal"
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_ENUM_IDX 0
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_ENUM_VAL_internal_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_ENUM_TOKEN internal
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_ENUM_UPPER_TOKEN INTERNAL
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_lfxo, load_capacitors, 0)
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_lfxo, load_capacitors, 0)
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_lfxo, load_capacitors, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_lfxo, load_capacitors, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_LEN 1
#define DT_N_S_clocks_S_lfxo_P_load_capacitors_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_load_capacitance_femtofarad 15500
#define DT_N_S_clocks_S_lfxo_P_load_capacitance_femtofarad_ENUM_IDX 23
#define DT_N_S_clocks_S_lfxo_P_load_capacitance_femtofarad_ENUM_VAL_15500_EXISTS 1
#define DT_N_S_clocks_S_lfxo_P_load_capacitance_femtofarad_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_NODELABEL_NUM 0
#define DT_N_S_cpus_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_CHILD_NUM 1
#define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 21
#define DT_N_S_cpus_ORD_STR_SORTABLE 00021

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	22, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_IRQ_LEVEL 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m33f):
 *   $ZEPHYR_BASE/dts/bindings/cpu/arm,cortex-m33f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_NODELABEL_NUM 2
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL(fn) fn(cpuapp) fn(cpu)
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp, __VA_ARGS__) fn(cpu, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM 1
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 22
#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00022

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	21, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
	23, /* /cpus/cpu@0/itm@e0000000 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0
#define DT_N_NODELABEL_cpuapp       DT_N_S_cpus_S_cpu_0
#define DT_N_NODELABEL_cpu          DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m33f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m33f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M33F
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_clock_frequency 128000000
#define DT_N_S_cpus_S_cpu_0_P_clock_frequency_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/itm@e0000000
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0_S_itm_e0000000
 *
 * Binding (compatible = arm,armv8m-itm):
 *   $ZEPHYR_BASE/dts/bindings/debug/arm,armv8m-itm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PATH "/cpus/cpu@0/itm@e0000000"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME "itm@e0000000"

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PARENT DT_N_S_cpus_S_cpu_0

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_NODELABEL(fn) fn(itm)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(itm, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD 23
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD_STR_SORTABLE 00023

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REQUIRES_ORDS \
	22, /* /cpus/cpu@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_EXISTS 1
#define DT_N_INST_0_arm_armv8m_itm DT_N_S_cpus_S_cpu_0_S_itm_e0000000
#define DT_N_NODELABEL_itm         DT_N_S_cpus_S_cpu_0_S_itm_e0000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_ADDRESS 3758096384 /* 0xe0000000 */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MATCHES_arm_armv8m_itm 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0 "armv8m-itm"
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible {"arm,armv8m-itm"}
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0 "arm,armv8m-itm"
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-itm
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_itm
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_ITM
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg {3758096384 /* 0xe0000000 */, 4096 /* 0x1000 */}
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0 3758096384
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1 4096
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency 128000000
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/gpio@50400
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_gpio_50400
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_PATH "/soc/peripheral@40000000/gpio@50400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FULL_NAME "gpio@50400"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_NODELABEL(fn) fn(gpio2)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_ORD 24
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_ORD_STR_SORTABLE 00024

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_SUPPORTS_ORDS \
	25, /* /leds */ \
	26, /* /leds/led_0 */ \
	28, /* /leds/led_2 */ \
	104, /* /soc/peripheral@40000000/spi@4a000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_40000000_S_gpio_50400
#define DT_N_NODELABEL_gpio2        DT_N_S_soc_S_peripheral_40000000_S_gpio_50400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_REG_IDX_0_VAL_ADDRESS 1074070528 /* 0x40050400 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_ngpios 11
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_reg {328704 /* 0x50400 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_reg_IDX_0 328704
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_port 2
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_50400_P_port_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node's name with unit-address: */
#define DT_N_S_leds_FULL_NAME "leds"

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_NODELABEL_NUM 0
#define DT_N_S_leds_FOREACH_NODELABEL(fn) 
#define DT_N_S_leds_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_CHILD_NUM 4
#define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 25
#define DT_N_S_leds_ORD_STR_SORTABLE 00025

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */ \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	24, /* /soc/peripheral@40000000/gpio@50400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	26, /* /leds/led_0 */ \
	27, /* /leds/led_1 */ \
	28, /* /leds/led_2 */ \
	29, /* /leds/led_3 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_RANGES_NUM 0
#define DT_N_S_leds_FOREACH_RANGE(fn) 
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_IRQ_LEVEL 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node identifier: DT_N_S_leds_S_led_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_0_PATH "/leds/led_0"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_0_FULL_NAME "led_0"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_0_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_0_FOREACH_NODELABEL(fn) fn(led0)
#define DT_N_S_leds_S_led_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(led0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_0_CHILD_NUM 0
#define DT_N_S_leds_S_led_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_0_ORD 26
#define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00026

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
	24, /* /soc/peripheral@40000000/gpio@50400 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0     DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_RANGES_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_50400
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 9
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "Green LED 0"
#define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED Green LED 0
#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Green_LED_0
#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN GREEN_LED_0
#define DT_N_S_leds_S_led_0_P_label_IDX_0 "Green LED 0"
#define DT_N_S_leds_S_led_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_LEN 1
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_1
 *
 * Node identifier: DT_N_S_leds_S_led_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_1_PATH "/leds/led_1"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_1_FULL_NAME "led_1"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_1_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_1_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_1_FOREACH_NODELABEL(fn) fn(led1)
#define DT_N_S_leds_S_led_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(led1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_1_CHILD_NUM 0
#define DT_N_S_leds_S_led_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_1_ORD 27
#define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00027

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_1_EXISTS 1
#define DT_N_ALIAS_led1     DT_N_S_leds_S_led_1
#define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_1_REG_NUM 0
#define DT_N_S_leds_S_led_1_RANGES_NUM 0
#define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_1_IRQ_NUM 0
#define DT_N_S_leds_S_led_1_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 10
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, gpios, 0)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_gpios_LEN 1
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_STRING_UNQUOTED Green LED 1
#define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN Green_LED_1
#define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN GREEN_LED_1
#define DT_N_S_leds_S_led_1_P_label_IDX_0 "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, label, 0)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_label_LEN 1
#define DT_N_S_leds_S_led_1_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_2
 *
 * Node identifier: DT_N_S_leds_S_led_2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_2_PATH "/leds/led_2"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_2_FULL_NAME "led_2"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_2_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_2_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_2_FOREACH_NODELABEL(fn) fn(led2)
#define DT_N_S_leds_S_led_2_FOREACH_NODELABEL_VARGS(fn, ...) fn(led2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_2_CHILD_NUM 0
#define DT_N_S_leds_S_led_2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_2_ORD 28
#define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00028

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
	24, /* /soc/peripheral@40000000/gpio@50400 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_2_EXISTS 1
#define DT_N_ALIAS_led2     DT_N_S_leds_S_led_2
#define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_2_REG_NUM 0
#define DT_N_S_leds_S_led_2_RANGES_NUM 0
#define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_2_IRQ_NUM 0
#define DT_N_S_leds_S_led_2_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_50400
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 7
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, gpios, 0)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_gpios_LEN 1
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_STRING_UNQUOTED Green LED 2
#define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN Green_LED_2
#define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN GREEN_LED_2
#define DT_N_S_leds_S_led_2_P_label_IDX_0 "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, label, 0)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_label_LEN 1
#define DT_N_S_leds_S_led_2_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_3
 *
 * Node identifier: DT_N_S_leds_S_led_3
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_3_PATH "/leds/led_3"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_3_FULL_NAME "led_3"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_3_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_3_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_3_FOREACH_NODELABEL(fn) fn(led3)
#define DT_N_S_leds_S_led_3_FOREACH_NODELABEL_VARGS(fn, ...) fn(led3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_3_CHILD_NUM 0
#define DT_N_S_leds_S_led_3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_3_ORD 29
#define DT_N_S_leds_S_led_3_ORD_STR_SORTABLE 00029

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_3_REQUIRES_ORDS \
	10, /* /soc/peripheral@40000000/gpio@d8200 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_3_EXISTS 1
#define DT_N_ALIAS_led3     DT_N_S_leds_S_led_3
#define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_3_REG_NUM 0
#define DT_N_S_leds_S_led_3_RANGES_NUM 0
#define DT_N_S_leds_S_led_3_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_3_IRQ_NUM 0
#define DT_N_S_leds_S_led_3_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_3_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 14
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, gpios, 0)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_gpios_LEN 1
#define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_STRING_UNQUOTED Green LED 3
#define DT_N_S_leds_S_led_3_P_label_STRING_TOKEN Green_LED_3
#define DT_N_S_leds_S_led_3_P_label_STRING_UPPER_TOKEN GREEN_LED_3
#define DT_N_S_leds_S_led_3_P_label_IDX_0 "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, label, 0)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, label, 0)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_label_LEN 1
#define DT_N_S_leds_S_led_3_P_label_EXISTS 1

/*
 * Devicetree node: /pin-controller
 *
 * Node identifier: DT_N_S_pin_controller
 *
 * Binding (compatible = nordic,nrf-pinctrl):
 *   $ZEPHYR_BASE/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_PATH "/pin-controller"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_FULL_NAME "pin-controller"

/* Node parent (/) identifier: */
#define DT_N_S_pin_controller_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_NODELABEL_NUM 1
#define DT_N_S_pin_controller_FOREACH_NODELABEL(fn) fn(pinctrl)
#define DT_N_S_pin_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_CHILD_NUM 8
#define DT_N_S_pin_controller_CHILD_NUM_STATUS_OKAY 8
#define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart20_default) fn(DT_N_S_pin_controller_S_uart20_sleep) fn(DT_N_S_pin_controller_S_uart30_default) fn(DT_N_S_pin_controller_S_uart30_sleep) fn(DT_N_S_pin_controller_S_spi00_default) fn(DT_N_S_pin_controller_S_spi00_sleep) fn(DT_N_S_pin_controller_S_pwm20_default) fn(DT_N_S_pin_controller_S_pwm20_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart20_default) fn(DT_N_S_pin_controller_S_uart20_sleep) fn(DT_N_S_pin_controller_S_uart30_default) fn(DT_N_S_pin_controller_S_uart30_sleep) fn(DT_N_S_pin_controller_S_spi00_default) fn(DT_N_S_pin_controller_S_spi00_sleep) fn(DT_N_S_pin_controller_S_pwm20_default) fn(DT_N_S_pin_controller_S_pwm20_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi00_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm20_sleep, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_ORD 30
#define DT_N_S_pin_controller_ORD_STR_SORTABLE 00030

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_SUPPORTS_ORDS \
	31, /* /pin-controller/pwm20_default */ \
	33, /* /pin-controller/pwm20_sleep */ \
	35, /* /pin-controller/spi00_default */ \
	37, /* /pin-controller/spi00_sleep */ \
	39, /* /pin-controller/uart20_default */ \
	42, /* /pin-controller/uart20_sleep */ \
	44, /* /pin-controller/uart30_default */ \
	47, /* /pin-controller/uart30_sleep */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller
#define DT_N_NODELABEL_pinctrl         DT_N_S_pin_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_REG_NUM 0
#define DT_N_S_pin_controller_RANGES_NUM 0
#define DT_N_S_pin_controller_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_IRQ_NUM 0
#define DT_N_S_pin_controller_IRQ_LEVEL 0
#define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl"
#define DT_N_S_pin_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_P_wakeup_source 0
#define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"}
#define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl"
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL
#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_LEN 1
#define DT_N_S_pin_controller_P_compatible_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_deferred_init 0
#define DT_N_S_pin_controller_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /pin-controller/pwm20_default
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm20_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm20_default_PATH "/pin-controller/pwm20_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm20_default_FULL_NAME "pwm20_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_pwm20_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm20_default_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_pwm20_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_NODELABEL(fn) fn(pwm20_default)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm20_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm20_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_pwm20_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm20_default_ORD 31
#define DT_N_S_pin_controller_S_pwm20_default_ORD_STR_SORTABLE 00031

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm20_default_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm20_default_SUPPORTS_ORDS \
	32, /* /pin-controller/pwm20_default/group1 */ \
	49, /* /soc/peripheral@40000000/pwm@d2000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm20_default_EXISTS 1
#define DT_N_NODELABEL_pwm20_default DT_N_S_pin_controller_S_pwm20_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm20_default_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm20_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm20_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm20_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/pwm20_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm20_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_PATH "/pin-controller/pwm20_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/pwm20_default) identifier: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm20_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_ORD 32
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_ORD_STR_SORTABLE 00032

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_REQUIRES_ORDS \
	31, /* /pin-controller/pwm20_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels {369098794 /* 0x1600002a */}
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_IDX_0 369098794
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_LEN 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_pwm20_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/pwm20_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm20_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm20_sleep_PATH "/pin-controller/pwm20_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm20_sleep_FULL_NAME "pwm20_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_pwm20_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm20_sleep_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_pwm20_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_NODELABEL(fn) fn(pwm20_sleep)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm20_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm20_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_pwm20_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm20_sleep_ORD 33
#define DT_N_S_pin_controller_S_pwm20_sleep_ORD_STR_SORTABLE 00033

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm20_sleep_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm20_sleep_SUPPORTS_ORDS \
	34, /* /pin-controller/pwm20_sleep/group1 */ \
	49, /* /soc/peripheral@40000000/pwm@d2000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm20_sleep_EXISTS 1
#define DT_N_NODELABEL_pwm20_sleep DT_N_S_pin_controller_S_pwm20_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm20_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm20_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm20_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm20_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/pwm20_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm20_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_PATH "/pin-controller/pwm20_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/pwm20_sleep) identifier: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm20_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_ORD 34
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_ORD_STR_SORTABLE 00034

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_REQUIRES_ORDS \
	33, /* /pin-controller/pwm20_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels {369098794 /* 0x1600002a */}
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_IDX_0 369098794
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_LEN 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_pwm20_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi00_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi00_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi00_default_PATH "/pin-controller/spi00_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi00_default_FULL_NAME "spi00_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi00_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi00_default_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi00_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_NODELABEL(fn) fn(spi00_default)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi00_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi00_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi00_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi00_default_S_group1)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi00_default_S_group1)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi00_default_S_group1)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi00_default_S_group1)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi00_default_ORD 35
#define DT_N_S_pin_controller_S_spi00_default_ORD_STR_SORTABLE 00035

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi00_default_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi00_default_SUPPORTS_ORDS \
	36, /* /pin-controller/spi00_default/group1 */ \
	104, /* /soc/peripheral@40000000/spi@4a000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi00_default_EXISTS 1
#define DT_N_NODELABEL_spi00_default DT_N_S_pin_controller_S_spi00_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi00_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi00_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi00_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi00_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi00_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi00_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_PATH "/pin-controller/spi00_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi00_default) identifier: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_PARENT DT_N_S_pin_controller_S_spi00_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_ORD 36
#define DT_N_S_pin_controller_S_spi00_default_S_group1_ORD_STR_SORTABLE 00036

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_REQUIRES_ORDS \
	35, /* /pin-controller/spi00_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi00_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels {67108929 /* 0x4000041 */, 83886146 /* 0x5000042 */, 100663364 /* 0x6000044 */}
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_IDX_0 67108929
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_IDX_1 83886146
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_IDX_2 100663364
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi00_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi00_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi00_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi00_sleep_PATH "/pin-controller/spi00_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi00_sleep_FULL_NAME "spi00_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi00_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi00_sleep_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi00_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_NODELABEL(fn) fn(spi00_sleep)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi00_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi00_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi00_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi00_sleep_ORD 37
#define DT_N_S_pin_controller_S_spi00_sleep_ORD_STR_SORTABLE 00037

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi00_sleep_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi00_sleep_SUPPORTS_ORDS \
	38, /* /pin-controller/spi00_sleep/group1 */ \
	104, /* /soc/peripheral@40000000/spi@4a000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi00_sleep_EXISTS 1
#define DT_N_NODELABEL_spi00_sleep DT_N_S_pin_controller_S_spi00_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi00_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi00_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi00_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi00_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi00_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi00_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_PATH "/pin-controller/spi00_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi00_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi00_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_ORD 38
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_ORD_STR_SORTABLE 00038

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_REQUIRES_ORDS \
	37, /* /pin-controller/spi00_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels {67108929 /* 0x4000041 */, 83886146 /* 0x5000042 */, 100663364 /* 0x6000044 */}
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_IDX_0 67108929
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_IDX_1 83886146
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_IDX_2 100663364
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi00_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart20_default
 *
 * Node identifier: DT_N_S_pin_controller_S_uart20_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart20_default_PATH "/pin-controller/uart20_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart20_default_FULL_NAME "uart20_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart20_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart20_default_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart20_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_NODELABEL(fn) fn(uart20_default)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart20_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart20_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_uart20_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart20_default_S_group1) fn(DT_N_S_pin_controller_S_uart20_default_S_group2)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_default_S_group2)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart20_default_S_group1) fn(DT_N_S_pin_controller_S_uart20_default_S_group2)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_default_S_group2)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart20_default_S_group2, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart20_default_ORD 39
#define DT_N_S_pin_controller_S_uart20_default_ORD_STR_SORTABLE 00039

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart20_default_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart20_default_SUPPORTS_ORDS \
	40, /* /pin-controller/uart20_default/group1 */ \
	41, /* /pin-controller/uart20_default/group2 */ \
	90, /* /soc/peripheral@40000000/uart@c6000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart20_default_EXISTS 1
#define DT_N_NODELABEL_uart20_default DT_N_S_pin_controller_S_uart20_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart20_default_REG_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart20_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart20_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart20_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart20_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart20_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_PATH "/pin-controller/uart20_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart20_default) identifier: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_PARENT DT_N_S_pin_controller_S_uart20_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_ORD 40
#define DT_N_S_pin_controller_S_uart20_default_S_group1_ORD_STR_SORTABLE 00040

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_REQUIRES_ORDS \
	39, /* /pin-controller/uart20_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels {36 /* 0x24 */, 33554470 /* 0x2000026 */}
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_IDX_0 36
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_IDX_1 33554470
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart20_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart20_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_uart20_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_PATH "/pin-controller/uart20_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FULL_NAME "group2"

/* Node parent (/pin-controller/uart20_default) identifier: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_PARENT DT_N_S_pin_controller_S_uart20_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_ORD 41
#define DT_N_S_pin_controller_S_uart20_default_S_group2_ORD_STR_SORTABLE 00041

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_REQUIRES_ORDS \
	39, /* /pin-controller/uart20_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart20_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels {16777253 /* 0x1000025 */, 50331687 /* 0x3000027 */}
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_IDX_0 16777253
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_IDX_1 50331687
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 1)
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 1)
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_default_S_group2, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart20_default_S_group2_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart20_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_uart20_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart20_sleep_PATH "/pin-controller/uart20_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart20_sleep_FULL_NAME "uart20_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart20_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart20_sleep_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart20_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_NODELABEL(fn) fn(uart20_sleep)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart20_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart20_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_uart20_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart20_sleep_ORD 42
#define DT_N_S_pin_controller_S_uart20_sleep_ORD_STR_SORTABLE 00042

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart20_sleep_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart20_sleep_SUPPORTS_ORDS \
	43, /* /pin-controller/uart20_sleep/group1 */ \
	90, /* /soc/peripheral@40000000/uart@c6000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart20_sleep_EXISTS 1
#define DT_N_NODELABEL_uart20_sleep DT_N_S_pin_controller_S_uart20_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart20_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart20_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart20_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart20_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart20_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart20_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_PATH "/pin-controller/uart20_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart20_sleep) identifier: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart20_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_ORD 43
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_ORD_STR_SORTABLE 00043

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_REQUIRES_ORDS \
	42, /* /pin-controller/uart20_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels {36 /* 0x24 */, 16777253 /* 0x1000025 */, 33554470 /* 0x2000026 */, 50331687 /* 0x3000027 */}
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_0 36
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_1 16777253
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_2 33554470
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_3 50331687
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_LEN 4
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart20_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart30_default
 *
 * Node identifier: DT_N_S_pin_controller_S_uart30_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart30_default_PATH "/pin-controller/uart30_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart30_default_FULL_NAME "uart30_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart30_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart30_default_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart30_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_NODELABEL(fn) fn(uart30_default)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart30_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart30_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_uart30_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart30_default_S_group1) fn(DT_N_S_pin_controller_S_uart30_default_S_group2)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default_S_group2)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart30_default_S_group1) fn(DT_N_S_pin_controller_S_uart30_default_S_group2)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default_S_group2)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart30_default_S_group2, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart30_default_ORD 44
#define DT_N_S_pin_controller_S_uart30_default_ORD_STR_SORTABLE 00044

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart30_default_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart30_default_SUPPORTS_ORDS \
	45, /* /pin-controller/uart30_default/group1 */ \
	46, /* /pin-controller/uart30_default/group2 */ \
	93, /* /soc/peripheral@40000000/uart@104000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart30_default_EXISTS 1
#define DT_N_NODELABEL_uart30_default DT_N_S_pin_controller_S_uart30_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart30_default_REG_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart30_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart30_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart30_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart30_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart30_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_PATH "/pin-controller/uart30_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart30_default) identifier: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_PARENT DT_N_S_pin_controller_S_uart30_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_ORD 45
#define DT_N_S_pin_controller_S_uart30_default_S_group1_ORD_STR_SORTABLE 00045

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_REQUIRES_ORDS \
	44, /* /pin-controller/uart30_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels {0 /* 0x0 */, 33554434 /* 0x2000002 */}
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_IDX_0 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_IDX_1 33554434
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart30_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart30_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_uart30_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_PATH "/pin-controller/uart30_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FULL_NAME "group2"

/* Node parent (/pin-controller/uart30_default) identifier: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_PARENT DT_N_S_pin_controller_S_uart30_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_ORD 46
#define DT_N_S_pin_controller_S_uart30_default_S_group2_ORD_STR_SORTABLE 00046

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_REQUIRES_ORDS \
	44, /* /pin-controller/uart30_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart30_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels {16777217 /* 0x1000001 */, 50331651 /* 0x3000003 */}
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_IDX_0 16777217
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_IDX_1 50331651
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 1)
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 1)
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_default_S_group2, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart30_default_S_group2_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart30_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_uart30_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart30_sleep_PATH "/pin-controller/uart30_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart30_sleep_FULL_NAME "uart30_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart30_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart30_sleep_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart30_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_NODELABEL(fn) fn(uart30_sleep)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart30_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart30_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_uart30_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart30_sleep_ORD 47
#define DT_N_S_pin_controller_S_uart30_sleep_ORD_STR_SORTABLE 00047

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart30_sleep_REQUIRES_ORDS \
	30, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart30_sleep_SUPPORTS_ORDS \
	48, /* /pin-controller/uart30_sleep/group1 */ \
	93, /* /soc/peripheral@40000000/uart@104000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart30_sleep_EXISTS 1
#define DT_N_NODELABEL_uart30_sleep DT_N_S_pin_controller_S_uart30_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart30_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart30_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart30_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart30_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart30_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart30_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_PATH "/pin-controller/uart30_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart30_sleep) identifier: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart30_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_ORD 48
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_ORD_STR_SORTABLE 00048

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_REQUIRES_ORDS \
	47, /* /pin-controller/uart30_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels {0 /* 0x0 */, 16777217 /* 0x1000001 */, 33554434 /* 0x2000002 */, 50331651 /* 0x3000003 */}
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_0 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_1 16777217
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_2 33554434
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_3 50331651
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_LEN 4
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart30_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@d2000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PATH "/soc/peripheral@40000000/pwm@d2000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FULL_NAME "pwm@d2000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_CHILD_IDX 28

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_NODELABEL(fn) fn(pwm20)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_ORD 49
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_ORD_STR_SORTABLE 00049

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */ \
	31, /* /pin-controller/pwm20_default */ \
	33, /* /pin-controller/pwm20_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_SUPPORTS_ORDS \
	50, /* /pwmleds */ \
	51, /* /pwmleds/pwm_led_1 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000
#define DT_N_NODELABEL_pwm20       DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_REG_IDX_0_VAL_ADDRESS 1074601984 /* 0x400d2000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_VAL_irq 210
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm20_default
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm20_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_reg {860160 /* 0xd2000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_reg_IDX_0 860160
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_interrupts {210 /* 0xd2 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_interrupts_IDX_0 210
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm20_default
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm20_default
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm20_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm20_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /pwmleds
 *
 * Node identifier: DT_N_S_pwmleds
 *
 * Binding (compatible = pwm-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/pwm-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pwmleds_PATH "/pwmleds"

/* Node's name with unit-address: */
#define DT_N_S_pwmleds_FULL_NAME "pwmleds"

/* Node parent (/) identifier: */
#define DT_N_S_pwmleds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pwmleds_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_pwmleds_NODELABEL_NUM 0
#define DT_N_S_pwmleds_FOREACH_NODELABEL(fn) 
#define DT_N_S_pwmleds_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pwmleds_CHILD_NUM 1
#define DT_N_S_pwmleds_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pwmleds_FOREACH_CHILD(fn) fn(DT_N_S_pwmleds_S_pwm_led_1)
#define DT_N_S_pwmleds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_1)
#define DT_N_S_pwmleds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_1, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_1, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pwmleds_S_pwm_led_1)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_1)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_1, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pwmleds_ORD 50
#define DT_N_S_pwmleds_ORD_STR_SORTABLE 00050

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pwmleds_REQUIRES_ORDS \
	0, /* / */ \
	49, /* /soc/peripheral@40000000/pwm@d2000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pwmleds_SUPPORTS_ORDS \
	51, /* /pwmleds/pwm_led_1 */

/* Existence and alternate IDs: */
#define DT_N_S_pwmleds_EXISTS 1
#define DT_N_INST_0_pwm_leds DT_N_S_pwmleds

/* Macros for properties that are special in the specification: */
#define DT_N_S_pwmleds_REG_NUM 0
#define DT_N_S_pwmleds_RANGES_NUM 0
#define DT_N_S_pwmleds_FOREACH_RANGE(fn) 
#define DT_N_S_pwmleds_IRQ_NUM 0
#define DT_N_S_pwmleds_IRQ_LEVEL 0
#define DT_N_S_pwmleds_COMPAT_MATCHES_pwm_leds 1
#define DT_N_S_pwmleds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pwmleds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pwmleds_P_compatible {"pwm-leds"}
#define DT_N_S_pwmleds_P_compatible_IDX_0 "pwm-leds"
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UNQUOTED pwm-leds
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_TOKEN pwm_leds
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_LEDS
#define DT_N_S_pwmleds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds, compatible, 0)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds, compatible, 0)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_P_compatible_LEN 1
#define DT_N_S_pwmleds_P_compatible_EXISTS 1

/*
 * Devicetree node: /pwmleds/pwm_led_1
 *
 * Node identifier: DT_N_S_pwmleds_S_pwm_led_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pwmleds_S_pwm_led_1_PATH "/pwmleds/pwm_led_1"

/* Node's name with unit-address: */
#define DT_N_S_pwmleds_S_pwm_led_1_FULL_NAME "pwm_led_1"

/* Node parent (/pwmleds) identifier: */
#define DT_N_S_pwmleds_S_pwm_led_1_PARENT DT_N_S_pwmleds

/* Node's index in its parent's list of children: */
#define DT_N_S_pwmleds_S_pwm_led_1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pwmleds_S_pwm_led_1_NODELABEL_NUM 1
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_NODELABEL(fn) fn(pwm_led1)
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm_led1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pwmleds_S_pwm_led_1_CHILD_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD(fn) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pwmleds_S_pwm_led_1_ORD 51
#define DT_N_S_pwmleds_S_pwm_led_1_ORD_STR_SORTABLE 00051

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pwmleds_S_pwm_led_1_REQUIRES_ORDS \
	49, /* /soc/peripheral@40000000/pwm@d2000 */ \
	50, /* /pwmleds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pwmleds_S_pwm_led_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pwmleds_S_pwm_led_1_EXISTS 1
#define DT_N_ALIAS_pwm_led0     DT_N_S_pwmleds_S_pwm_led_1
#define DT_N_NODELABEL_pwm_led1 DT_N_S_pwmleds_S_pwm_led_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pwmleds_S_pwm_led_1_REG_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_1_RANGES_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_1_FOREACH_RANGE(fn) 
#define DT_N_S_pwmleds_S_pwm_led_1_IRQ_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_1_IRQ_LEVEL 0
#define DT_N_S_pwmleds_S_pwm_led_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pwmleds_S_pwm_led_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_VAL_channel 0
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_VAL_period 20000000
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_VAL_period_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_VAL_flags 0
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_pwm_led_1, pwms, 0)
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_1, pwms, 0)
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_1, pwms, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_1, pwms, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_LEN 1
#define DT_N_S_pwmleds_S_pwm_led_1_P_pwms_EXISTS 1

/*
 * Devicetree node: /soc/ficr@ffc000
 *
 * Node identifier: DT_N_S_soc_S_ficr_ffc000
 *
 * Binding (compatible = nordic,nrf-ficr):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-ficr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ficr_ffc000_PATH "/soc/ficr@ffc000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ficr_ffc000_FULL_NAME "ficr@ffc000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ficr_ffc000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ficr_ffc000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ficr_ffc000_NODELABEL_NUM 1
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_NODELABEL(fn) fn(ficr)
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ficr, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ficr_ffc000_CHILD_NUM 0
#define DT_N_S_soc_S_ficr_ffc000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ficr_ffc000_ORD 52
#define DT_N_S_soc_S_ficr_ffc000_ORD_STR_SORTABLE 00052

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ficr_ffc000_REQUIRES_ORDS \
	5, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ficr_ffc000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ficr_ffc000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ffc000
#define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_ffc000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ficr_ffc000_REG_NUM 1
#define DT_N_S_soc_S_ficr_ffc000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_REG_IDX_0_VAL_ADDRESS 16760832 /* 0xffc000 */
#define DT_N_S_soc_S_ficr_ffc000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ficr_ffc000_RANGES_NUM 0
#define DT_N_S_soc_S_ficr_ffc000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ficr_ffc000_IRQ_NUM 0
#define DT_N_S_soc_S_ficr_ffc000_IRQ_LEVEL 0
#define DT_N_S_soc_S_ficr_ffc000_COMPAT_MATCHES_nordic_nrf_ficr 1
#define DT_N_S_soc_S_ficr_ffc000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ficr_ffc000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_COMPAT_MODEL_IDX_0 "nrf-ficr"
#define DT_N_S_soc_S_ficr_ffc000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ficr_ffc000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ficr_ffc000_P_wakeup_source 0
#define DT_N_S_soc_S_ficr_ffc000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ficr_ffc000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_compatible {"nordic,nrf-ficr"}
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_IDX_0 "nordic,nrf-ficr"
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ficr
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ffc000, compatible, 0)
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ffc000, compatible, 0)
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ffc000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ffc000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_LEN 1
#define DT_N_S_soc_S_ficr_ffc000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_reg {16760832 /* 0xffc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ficr_ffc000_P_reg_IDX_0 16760832
#define DT_N_S_soc_S_ficr_ffc000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ficr_ffc000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ficr_ffc000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ficr_ffc000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE/dts/bindings/sram/mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_20000000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_20000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_20000000_FOREACH_NODELABEL(fn) fn(cpuapp_sram)
#define DT_N_S_soc_S_memory_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_sram, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_20000000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_20000000_ORD 53
#define DT_N_S_soc_S_memory_20000000_ORD_STR_SORTABLE 00053

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
	5, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram      DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_cpuapp_sram DT_N_S_soc_S_memory_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_memory_20000000_RANGES_NUM 1
#define DT_N_S_soc_S_memory_20000000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_memory_20000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_RANGES_IDX_0_VAL_LENGTH 262144 /* 0x40000 */
#define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_memory_20000000, 0)
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_status "okay"
#define DT_N_S_soc_S_memory_20000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_memory_20000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_memory_20000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_memory_20000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_memory_20000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_memory_20000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_memory_20000000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_memory_20000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, status, 0)
#define DT_N_S_soc_S_memory_20000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, status, 0)
#define DT_N_S_soc_S_memory_20000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_status_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_status_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/cpuapp-ppb-bus/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010
 *
 * Binding (compatible = arm,armv8m-systick):
 *   $ZEPHYR_BASE/dts/bindings/timer/arm,armv8m-systick.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_PATH "/soc/cpuapp-ppb-bus/timer@e000e010"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FULL_NAME "timer@e000e010"

/* Node parent (/soc/cpuapp-ppb-bus) identifier: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_PARENT DT_N_S_soc_S_cpuapp_ppb_bus

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_NODELABEL_NUM 2
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_NODELABEL(fn) fn(cpuapp_systick) fn(systick)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_systick, __VA_ARGS__) fn(systick, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_CHILD_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_ORD 54
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_ORD_STR_SORTABLE 00054

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_REQUIRES_ORDS \
	7, /* /soc/cpuapp-ppb-bus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010
#define DT_N_NODELABEL_cpuapp_systick  DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_RANGES_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_IRQ_LEVEL 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv8m-systick"
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_wakeup_source 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, status, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, status, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_LEN 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_status_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-systick
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_systick
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_SYSTICK
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/adc@d5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_adc_d5000
 *
 * Binding (compatible = nordic,nrf-saadc):
 *   $ZEPHYR_BASE/dts/bindings/adc/nordic,nrf-saadc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_PATH "/soc/peripheral@40000000/adc@d5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FULL_NAME "adc@d5000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_CHILD_IDX 31

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_NODELABEL(fn) fn(adc)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_ORD 55
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_ORD_STR_SORTABLE 00055

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_40000000_S_adc_d5000
#define DT_N_NODELABEL_adc           DT_N_S_soc_S_peripheral_40000000_S_adc_d5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_REG_IDX_0_VAL_ADDRESS 1074614272 /* 0x400d5000 */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_VAL_irq 213
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_COMPAT_MATCHES_nordic_nrf_saadc 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_COMPAT_MODEL_IDX_0 "nrf-saadc"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible {"nordic,nrf-saadc"}
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_IDX_0 "nordic,nrf-saadc"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-saadc
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_reg {872448 /* 0xd5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_reg_IDX_0 872448
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_interrupts {213 /* 0xd5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_interrupts_IDX_0 213
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_adc_d5000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/clock@10e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_clock_10e000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_PATH "/soc/peripheral@40000000/clock@10e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FULL_NAME "clock@10e000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_CHILD_IDX 48

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_NODELABEL(fn) fn(clock)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(clock, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_ORD 56
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_ORD_STR_SORTABLE 00056

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_40000000_S_clock_10e000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_peripheral_40000000_S_clock_10e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_REG_IDX_0_VAL_ADDRESS 1074847744 /* 0x4010e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_VAL_irq 270
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_COMPAT_MODEL_IDX_0 "nrf-clock"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-clock
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_reg {1105920 /* 0x10e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_reg_IDX_0 1105920
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_interrupts {270 /* 0x10e */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_interrupts_IDX_0 270
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_clock_10e000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/comparator@106000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_comparator_106000
 *
 * Binding (compatible = nordic,nrf-comp):
 *   $ZEPHYR_BASE/dts/bindings/comparator/nordic,nrf-comp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_PATH "/soc/peripheral@40000000/comparator@106000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FULL_NAME "comparator@106000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_CHILD_IDX 44

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_NODELABEL(fn) fn(comp)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_NODELABEL_VARGS(fn, ...) fn(comp, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_ORD 57
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_ORD_STR_SORTABLE 00057

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_comp DT_N_S_soc_S_peripheral_40000000_S_comparator_106000
#define DT_N_NODELABEL_comp         DT_N_S_soc_S_peripheral_40000000_S_comparator_106000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_REG_IDX_0_VAL_ADDRESS 1074814976 /* 0x40106000 */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_VAL_irq 262
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_COMPAT_MATCHES_nordic_nrf_comp 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_COMPAT_MODEL_IDX_0 "nrf-comp"
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible {"nordic,nrf-comp"}
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_IDX_0 "nordic,nrf-comp"
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-comp
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_comp
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_COMP
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_reg {1073152 /* 0x106000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_reg_IDX_0 1073152
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_interrupts {262 /* 0x106 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_interrupts_IDX_0 262
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_enable_hyst 0
#define DT_N_S_soc_S_peripheral_40000000_S_comparator_106000_P_enable_hyst_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/dppic@42000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_dppic_42000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_PATH "/soc/peripheral@40000000/dppic@42000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FULL_NAME "dppic@42000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_NODELABEL(fn) fn(dppic00)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dppic00, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_ORD 58
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_ORD_STR_SORTABLE 00058

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_40000000_S_dppic_42000
#define DT_N_NODELABEL_dppic00       DT_N_S_soc_S_peripheral_40000000_S_dppic_42000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_REG_IDX_0_VAL_ADDRESS 1074012160 /* 0x40042000 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_REG_IDX_0_VAL_SIZE 2056 /* 0x808 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_COMPAT_MODEL_IDX_0 "nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_reg {270336 /* 0x42000 */, 2056 /* 0x808 */}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_reg_IDX_0 270336
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_reg_IDX_1 2056
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_42000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/dppic@82000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_dppic_82000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_PATH "/soc/peripheral@40000000/dppic@82000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FULL_NAME "dppic@82000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_NODELABEL(fn) fn(dppic10)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dppic10, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_ORD 59
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_ORD_STR_SORTABLE 00059

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_dppic DT_N_S_soc_S_peripheral_40000000_S_dppic_82000
#define DT_N_NODELABEL_dppic10       DT_N_S_soc_S_peripheral_40000000_S_dppic_82000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_REG_IDX_0_VAL_ADDRESS 1074274304 /* 0x40082000 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_REG_IDX_0_VAL_SIZE 2056 /* 0x808 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_COMPAT_MODEL_IDX_0 "nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_reg {532480 /* 0x82000 */, 2056 /* 0x808 */}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_reg_IDX_0 532480
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_reg_IDX_1 2056
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_82000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/dppic@c2000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_PATH "/soc/peripheral@40000000/dppic@c2000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FULL_NAME "dppic@c2000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_NODELABEL(fn) fn(dppic20)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dppic20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_ORD 60
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_ORD_STR_SORTABLE 00060

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_dppic DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000
#define DT_N_NODELABEL_dppic20       DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_REG_IDX_0_VAL_ADDRESS 1074536448 /* 0x400c2000 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_REG_IDX_0_VAL_SIZE 2056 /* 0x808 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_COMPAT_MODEL_IDX_0 "nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_reg {794624 /* 0xc2000 */, 2056 /* 0x808 */}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_reg_IDX_0 794624
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_reg_IDX_1 2056
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/dppic@102000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_dppic_102000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_PATH "/soc/peripheral@40000000/dppic@102000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FULL_NAME "dppic@102000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_CHILD_IDX 40

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_NODELABEL(fn) fn(dppic30)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dppic30, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_ORD 61
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_ORD_STR_SORTABLE 00061

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_dppic DT_N_S_soc_S_peripheral_40000000_S_dppic_102000
#define DT_N_NODELABEL_dppic30       DT_N_S_soc_S_peripheral_40000000_S_dppic_102000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_REG_IDX_0_VAL_ADDRESS 1074798592 /* 0x40102000 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_REG_IDX_0_VAL_SIZE 2056 /* 0x808 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_COMPAT_MODEL_IDX_0 "nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_reg {1056768 /* 0x102000 */, 2056 /* 0x808 */}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_reg_IDX_0 1056768
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_reg_IDX_1 2056
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_102000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@87000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_87000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_PATH "/soc/peripheral@40000000/egu@87000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FULL_NAME "egu@87000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_NODELABEL(fn) fn(egu10)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu10, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_ORD 62
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_ORD_STR_SORTABLE 00062

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_87000
#define DT_N_NODELABEL_egu10       DT_N_S_soc_S_peripheral_40000000_S_egu_87000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_REG_IDX_0_VAL_ADDRESS 1074294784 /* 0x40087000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_VAL_irq 135
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_reg {552960 /* 0x87000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_reg_IDX_0 552960
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_interrupts {135 /* 0x87 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_interrupts_IDX_0 135
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_87000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@c9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_c9000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_PATH "/soc/peripheral@40000000/egu@c9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FULL_NAME "egu@c9000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_NODELABEL(fn) fn(egu20)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_ORD 63
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_ORD_STR_SORTABLE 00063

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_c9000
#define DT_N_NODELABEL_egu20       DT_N_S_soc_S_peripheral_40000000_S_egu_c9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_REG_IDX_0_VAL_ADDRESS 1074565120 /* 0x400c9000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_VAL_irq 201
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_reg {823296 /* 0xc9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_reg_IDX_0 823296
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_interrupts {201 /* 0xc9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_interrupts_IDX_0 201
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_egu_c9000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/grtc@e2000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000
 *
 * Binding (compatible = nordic,nrf-grtc):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-grtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_PATH "/soc/peripheral@40000000/grtc@e2000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FULL_NAME "grtc@e2000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_CHILD_IDX 39

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_NODELABEL(fn) fn(grtc)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_NODELABEL_VARGS(fn, ...) fn(grtc, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_ORD 64
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_ORD_STR_SORTABLE 00064

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_grtc DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000
#define DT_N_NODELABEL_grtc         DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_REG_IDX_0_VAL_ADDRESS 1074667520 /* 0x400e2000 */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_VAL_irq 227
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_VAL_irq 229
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_COMPAT_MATCHES_nordic_nrf_grtc 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_COMPAT_MODEL_IDX_0 "nrf-grtc"
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible {"nordic,nrf-grtc"}
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_IDX_0 "nordic,nrf-grtc"
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-grtc
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_grtc
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GRTC
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_reg {925696 /* 0xe2000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_reg_IDX_0 925696
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts {227 /* 0xe3 */, 1 /* 0x1 */, 229 /* 0xe5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_0 227
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_2 229
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_3 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels {0 /* 0x0 */, 1 /* 0x1 */, 2 /* 0x2 */, 3 /* 0x3 */, 4 /* 0x4 */, 5 /* 0x5 */, 6 /* 0x6 */, 7 /* 0x7 */, 8 /* 0x8 */, 9 /* 0x9 */, 10 /* 0xa */, 11 /* 0xb */}
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_2 2
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_3 3
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_3_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_4 4
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_4_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_5 5
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_5_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_6 6
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_6_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_7 7
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_7_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_8 8
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_8_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_9 9
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_9_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_10 10
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_10_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_11 11
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_IDX_11_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 1) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 2) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 3) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 4) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 5) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 6) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 7) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 8) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 9) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 10) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 11)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 11)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 11, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, owned_channels, 11, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_LEN 12
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_owned_channels_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels {3 /* 0x3 */, 4 /* 0x4 */, 7 /* 0x7 */, 8 /* 0x8 */, 9 /* 0x9 */, 10 /* 0xa */, 11 /* 0xb */}
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_0 3
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_1 4
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_2 7
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_3 8
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_3_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_4 9
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_4_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_5 10
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_5_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_6 11
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_IDX_6_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 1) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 2) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 3) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 4) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 5) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 6)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 6)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, child_owned_channels, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_LEN 7
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_child_owned_channels_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_cc_num 12
#define DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000_P_cc_num_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@c6000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_PATH "/soc/peripheral@40000000/i2c@c6000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FULL_NAME "i2c@c6000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_NODELABEL(fn) fn(i2c20)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_ORD 65
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_ORD_STR_SORTABLE 00065

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000
#define DT_N_NODELABEL_i2c20        DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_REG_IDX_0_VAL_ADDRESS 1074552832 /* 0x400c6000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_VAL_irq 198
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_reg {811008 /* 0xc6000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_reg_IDX_0 811008
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_interrupts {198 /* 0xc6 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_interrupts_IDX_0 198
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@c7000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_PATH "/soc/peripheral@40000000/i2c@c7000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FULL_NAME "i2c@c7000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_NODELABEL(fn) fn(i2c21)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_ORD 66
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_ORD_STR_SORTABLE 00066

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_twim DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000
#define DT_N_NODELABEL_i2c21        DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_REG_IDX_0_VAL_ADDRESS 1074556928 /* 0x400c7000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_VAL_irq 199
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_reg {815104 /* 0xc7000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_reg_IDX_0 815104
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_interrupts {199 /* 0xc7 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_interrupts_IDX_0 199
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@c8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_PATH "/soc/peripheral@40000000/i2c@c8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FULL_NAME "i2c@c8000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_NODELABEL(fn) fn(i2c22)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c22, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_ORD 67
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_ORD_STR_SORTABLE 00067

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_twim DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000
#define DT_N_NODELABEL_i2c22        DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_REG_IDX_0_VAL_ADDRESS 1074561024 /* 0x400c8000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_VAL_irq 200
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_reg {819200 /* 0xc8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_reg_IDX_0 819200
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_interrupts {200 /* 0xc8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_interrupts_IDX_0 200
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@104000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_104000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_PATH "/soc/peripheral@40000000/i2c@104000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FULL_NAME "i2c@104000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_CHILD_IDX 41

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_NODELABEL(fn) fn(i2c30)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c30, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_ORD 68
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_ORD_STR_SORTABLE 00068

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_twim DT_N_S_soc_S_peripheral_40000000_S_i2c_104000
#define DT_N_NODELABEL_i2c30        DT_N_S_soc_S_peripheral_40000000_S_i2c_104000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_REG_IDX_0_VAL_ADDRESS 1074806784 /* 0x40104000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_VAL_irq 260
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_reg {1064960 /* 0x104000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_reg_IDX_0 1064960
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_interrupts {260 /* 0x104 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_interrupts_IDX_0 260
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_104000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2s@dd000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000
 *
 * Binding (compatible = nordic,nrf-i2s):
 *   $ZEPHYR_BASE/dts/bindings/i2s/nordic,nrf-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_PATH "/soc/peripheral@40000000/i2s@dd000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FULL_NAME "i2s@dd000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_CHILD_IDX 36

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_NODELABEL(fn) fn(i2s20)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_ORD 69
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_ORD_STR_SORTABLE 00069

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000
#define DT_N_NODELABEL_i2s20       DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_REG_IDX_0_VAL_ADDRESS 1074647040 /* 0x400dd000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_VAL_irq 221
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_COMPAT_MATCHES_nordic_nrf_i2s 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_COMPAT_MODEL_IDX_0 "nrf-i2s"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible {"nordic,nrf-i2s"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_IDX_0 "nordic,nrf-i2s"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-i2s
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_reg {905216 /* 0xdd000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_reg_IDX_0 905216
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_interrupts {221 /* 0xdd */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_interrupts_IDX_0 221
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000_P_clock_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/nfct@d6000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000
 *
 * Binding (compatible = nordic,nrf-nfct):
 *   $ZEPHYR_BASE/dts/bindings/net/wireless/nordic,nrf-nfct.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_PATH "/soc/peripheral@40000000/nfct@d6000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FULL_NAME "nfct@d6000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_CHILD_IDX 32

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_NODELABEL(fn) fn(nfct)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(nfct, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_ORD 70
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_ORD_STR_SORTABLE 00070

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_nfct DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000
#define DT_N_NODELABEL_nfct         DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_REG_IDX_0_VAL_ADDRESS 1074618368 /* 0x400d6000 */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_VAL_irq 214
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_COMPAT_MATCHES_nordic_nrf_nfct 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_COMPAT_MODEL_IDX_0 "nrf-nfct"
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible {"nordic,nrf-nfct"}
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_IDX_0 "nordic,nrf-nfct"
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-nfct
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_nfct
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_NFCT
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_reg {876544 /* 0xd6000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_reg_IDX_0 876544
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_interrupts {214 /* 0xd6 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_interrupts_IDX_0 214
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pdm@d0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE/dts/bindings/audio/nordic,nrf-pdm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_PATH "/soc/peripheral@40000000/pdm@d0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FULL_NAME "pdm@d0000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_CHILD_IDX 26

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_NODELABEL(fn) fn(pdm20)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pdm20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_ORD 71
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_ORD_STR_SORTABLE 00071

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000
#define DT_N_NODELABEL_pdm20       DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_REG_IDX_0_VAL_ADDRESS 1074593792 /* 0x400d0000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_VAL_irq 208
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_COMPAT_MODEL_IDX_0 "nrf-pdm"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_reg {851968 /* 0xd0000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_reg_IDX_0 851968
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_interrupts {208 /* 0xd0 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_interrupts_IDX_0 208
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_clock_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_queue_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000_P_queue_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pdm@d1000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE/dts/bindings/audio/nordic,nrf-pdm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_PATH "/soc/peripheral@40000000/pdm@d1000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FULL_NAME "pdm@d1000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_CHILD_IDX 27

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_NODELABEL(fn) fn(pdm21)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pdm21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_ORD 72
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_ORD_STR_SORTABLE 00072

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_pdm DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000
#define DT_N_NODELABEL_pdm21       DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_REG_IDX_0_VAL_ADDRESS 1074597888 /* 0x400d1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_VAL_irq 209
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_COMPAT_MODEL_IDX_0 "nrf-pdm"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_reg {856064 /* 0xd1000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_reg_IDX_0 856064
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_interrupts {209 /* 0xd1 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_interrupts_IDX_0 209
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_clock_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_queue_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000_P_queue_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@d3000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_PATH "/soc/peripheral@40000000/pwm@d3000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FULL_NAME "pwm@d3000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_CHILD_IDX 29

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_NODELABEL(fn) fn(pwm21)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_ORD 73
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_ORD_STR_SORTABLE 00073

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000
#define DT_N_NODELABEL_pwm21       DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_REG_IDX_0_VAL_ADDRESS 1074606080 /* 0x400d3000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_VAL_irq 211
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_reg {864256 /* 0xd3000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_reg_IDX_0 864256
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_interrupts {211 /* 0xd3 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_interrupts_IDX_0 211
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@d4000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_PATH "/soc/peripheral@40000000/pwm@d4000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FULL_NAME "pwm@d4000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_CHILD_IDX 30

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_NODELABEL(fn) fn(pwm22)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm22, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_ORD 74
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_ORD_STR_SORTABLE 00074

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000
#define DT_N_NODELABEL_pwm22       DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_REG_IDX_0_VAL_ADDRESS 1074610176 /* 0x400d4000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_VAL_irq 212
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_reg {868352 /* 0xd4000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_reg_IDX_0 868352
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_interrupts {212 /* 0xd4 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_interrupts_IDX_0 212
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/qdec@e0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000
 *
 * Binding (compatible = nordic,nrf-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_PATH "/soc/peripheral@40000000/qdec@e0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FULL_NAME "qdec@e0000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_CHILD_IDX 37

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_NODELABEL(fn) fn(qdec20)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qdec20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_ORD 75
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_ORD_STR_SORTABLE 00075

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_qdec DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000
#define DT_N_NODELABEL_qdec20       DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_REG_IDX_0_VAL_ADDRESS 1074659328 /* 0x400e0000 */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_VAL_irq 224
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_COMPAT_MATCHES_nordic_nrf_qdec 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_COMPAT_MODEL_IDX_0 "nrf-qdec"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible {"nordic,nrf-qdec"}
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_IDX_0 "nordic,nrf-qdec"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_reg {917504 /* 0xe0000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_reg_IDX_0 917504
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_interrupts {224 /* 0xe0 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_interrupts_IDX_0 224
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/qdec@e1000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000
 *
 * Binding (compatible = nordic,nrf-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_PATH "/soc/peripheral@40000000/qdec@e1000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FULL_NAME "qdec@e1000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_CHILD_IDX 38

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_NODELABEL(fn) fn(qdec21)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qdec21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_ORD 76
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_ORD_STR_SORTABLE 00076

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_qdec DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000
#define DT_N_NODELABEL_qdec21       DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_REG_IDX_0_VAL_ADDRESS 1074663424 /* 0x400e1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_VAL_irq 225
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_COMPAT_MATCHES_nordic_nrf_qdec 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_COMPAT_MODEL_IDX_0 "nrf-qdec"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible {"nordic,nrf-qdec"}
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_IDX_0 "nordic,nrf-qdec"
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_reg {921600 /* 0xe1000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_reg_IDX_0 921600
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_interrupts {225 /* 0xe1 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_interrupts_IDX_0 225
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@c6000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_c6000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_PATH "/soc/peripheral@40000000/spi@c6000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FULL_NAME "spi@c6000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_NODELABEL(fn) fn(spi20)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_ORD 77
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_ORD_STR_SORTABLE 00077

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_40000000_S_spi_c6000
#define DT_N_NODELABEL_spi20        DT_N_S_soc_S_peripheral_40000000_S_spi_c6000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_REG_IDX_0_VAL_ADDRESS 1074552832 /* 0x400c6000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_VAL_irq 198
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_reg {811008 /* 0xc6000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_reg_IDX_0 811008
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_interrupts {198 /* 0xc6 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_interrupts_IDX_0 198
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_rx_delay_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_rx_delay 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_rx_delay_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_rx_delay_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c6000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@c7000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_c7000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_PATH "/soc/peripheral@40000000/spi@c7000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FULL_NAME "spi@c7000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_NODELABEL(fn) fn(spi21)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_ORD 78
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_ORD_STR_SORTABLE 00078

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_spim DT_N_S_soc_S_peripheral_40000000_S_spi_c7000
#define DT_N_NODELABEL_spi21        DT_N_S_soc_S_peripheral_40000000_S_spi_c7000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_REG_IDX_0_VAL_ADDRESS 1074556928 /* 0x400c7000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_VAL_irq 199
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_reg {815104 /* 0xc7000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_reg_IDX_0 815104
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_interrupts {199 /* 0xc7 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_interrupts_IDX_0 199
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_rx_delay_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_rx_delay 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_rx_delay_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_rx_delay_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c7000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@c8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_c8000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_PATH "/soc/peripheral@40000000/spi@c8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FULL_NAME "spi@c8000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_NODELABEL(fn) fn(spi22)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi22, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_ORD 79
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_ORD_STR_SORTABLE 00079

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_spim DT_N_S_soc_S_peripheral_40000000_S_spi_c8000
#define DT_N_NODELABEL_spi22        DT_N_S_soc_S_peripheral_40000000_S_spi_c8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_REG_IDX_0_VAL_ADDRESS 1074561024 /* 0x400c8000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_VAL_irq 200
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_reg {819200 /* 0xc8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_reg_IDX_0 819200
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_interrupts {200 /* 0xc8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_interrupts_IDX_0 200
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_rx_delay_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_rx_delay 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_rx_delay_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_rx_delay_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_c8000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@104000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_104000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_PATH "/soc/peripheral@40000000/spi@104000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FULL_NAME "spi@104000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_CHILD_IDX 42

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_NODELABEL(fn) fn(spi30)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi30, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_ORD 80
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_ORD_STR_SORTABLE 00080

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_spim DT_N_S_soc_S_peripheral_40000000_S_spi_104000
#define DT_N_NODELABEL_spi30        DT_N_S_soc_S_peripheral_40000000_S_spi_104000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_REG_IDX_0_VAL_ADDRESS 1074806784 /* 0x40104000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_VAL_irq 260
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_reg {1064960 /* 0x104000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_reg_IDX_0 1064960
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_interrupts {260 /* 0x104 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_interrupts_IDX_0 260
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_rx_delay_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_rx_delay 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_rx_delay_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_rx_delay_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_104000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/temp@d7000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_temp_d7000
 *
 * Binding (compatible = nordic,nrf-temp):
 *   $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-temp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_PATH "/soc/peripheral@40000000/temp@d7000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FULL_NAME "temp@d7000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_CHILD_IDX 33

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_NODELABEL(fn) fn(temp)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_NODELABEL_VARGS(fn, ...) fn(temp, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_ORD 81
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_ORD_STR_SORTABLE 00081

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_temp DT_N_S_soc_S_peripheral_40000000_S_temp_d7000
#define DT_N_NODELABEL_temp         DT_N_S_soc_S_peripheral_40000000_S_temp_d7000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_REG_IDX_0_VAL_ADDRESS 1074622464 /* 0x400d7000 */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_VAL_irq 215
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_COMPAT_MATCHES_nordic_nrf_temp 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_COMPAT_MODEL_IDX_0 "nrf-temp"
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible {"nordic,nrf-temp"}
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_IDX_0 "nordic,nrf-temp"
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-temp
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_temp
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TEMP
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_reg {880640 /* 0xd7000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_reg_IDX_0 880640
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_interrupts {215 /* 0xd7 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_interrupts_IDX_0 215
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_temp_d7000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@55000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_55000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_PATH "/soc/peripheral@40000000/timer@55000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FULL_NAME "timer@55000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_NODELABEL(fn) fn(timer00)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer00, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_ORD 82
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_ORD_STR_SORTABLE 00082

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_55000
#define DT_N_NODELABEL_timer00       DT_N_S_soc_S_peripheral_40000000_S_timer_55000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_REG_IDX_0_VAL_ADDRESS 1074089984 /* 0x40055000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_VAL_irq 85
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_reg {348160 /* 0x55000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_reg_IDX_0 348160
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_interrupts {85 /* 0x55 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_interrupts_IDX_0 85
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_max_frequency 128000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_55000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@85000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_85000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_PATH "/soc/peripheral@40000000/timer@85000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FULL_NAME "timer@85000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_NODELABEL(fn) fn(timer10)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer10, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_ORD 83
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_ORD_STR_SORTABLE 00083

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_85000
#define DT_N_NODELABEL_timer10       DT_N_S_soc_S_peripheral_40000000_S_timer_85000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_REG_IDX_0_VAL_ADDRESS 1074286592 /* 0x40085000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_VAL_irq 133
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_reg {544768 /* 0x85000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_reg_IDX_0 544768
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_interrupts {133 /* 0x85 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_interrupts_IDX_0 133
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_cc_num 8
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_max_frequency 32000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_85000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@ca000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_ca000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_PATH "/soc/peripheral@40000000/timer@ca000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FULL_NAME "timer@ca000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_NODELABEL(fn) fn(timer20)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_ORD 84
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_ORD_STR_SORTABLE 00084

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_ca000
#define DT_N_NODELABEL_timer20       DT_N_S_soc_S_peripheral_40000000_S_timer_ca000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_REG_IDX_0_VAL_ADDRESS 1074569216 /* 0x400ca000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_VAL_irq 202
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_reg {827392 /* 0xca000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_reg_IDX_0 827392
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_interrupts {202 /* 0xca */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_interrupts_IDX_0 202
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ca000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@cb000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_cb000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_PATH "/soc/peripheral@40000000/timer@cb000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FULL_NAME "timer@cb000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_NODELABEL(fn) fn(timer21)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_ORD 85
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_ORD_STR_SORTABLE 00085

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_cb000
#define DT_N_NODELABEL_timer21       DT_N_S_soc_S_peripheral_40000000_S_timer_cb000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_REG_IDX_0_VAL_ADDRESS 1074573312 /* 0x400cb000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_VAL_irq 203
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_reg {831488 /* 0xcb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_reg_IDX_0 831488
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_interrupts {203 /* 0xcb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_interrupts_IDX_0 203
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cb000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@cc000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_cc000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_PATH "/soc/peripheral@40000000/timer@cc000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FULL_NAME "timer@cc000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_NODELABEL(fn) fn(timer22)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer22, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_ORD 86
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_ORD_STR_SORTABLE 00086

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_cc000
#define DT_N_NODELABEL_timer22       DT_N_S_soc_S_peripheral_40000000_S_timer_cc000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_REG_IDX_0_VAL_ADDRESS 1074577408 /* 0x400cc000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_VAL_irq 204
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_reg {835584 /* 0xcc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_reg_IDX_0 835584
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_interrupts {204 /* 0xcc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_interrupts_IDX_0 204
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cc000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@cd000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_cd000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_PATH "/soc/peripheral@40000000/timer@cd000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FULL_NAME "timer@cd000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_NODELABEL(fn) fn(timer23)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer23, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_ORD 87
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_ORD_STR_SORTABLE 00087

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_EXISTS 1
#define DT_N_INST_5_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_cd000
#define DT_N_NODELABEL_timer23       DT_N_S_soc_S_peripheral_40000000_S_timer_cd000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_REG_IDX_0_VAL_ADDRESS 1074581504 /* 0x400cd000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_VAL_irq 205
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_reg {839680 /* 0xcd000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_reg_IDX_0 839680
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_interrupts {205 /* 0xcd */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_interrupts_IDX_0 205
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_cd000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@ce000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_ce000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_PATH "/soc/peripheral@40000000/timer@ce000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FULL_NAME "timer@ce000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_NODELABEL(fn) fn(timer24)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer24, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_ORD 88
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_ORD_STR_SORTABLE 00088

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_EXISTS 1
#define DT_N_INST_6_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_ce000
#define DT_N_NODELABEL_timer24       DT_N_S_soc_S_peripheral_40000000_S_timer_ce000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_REG_IDX_0_VAL_ADDRESS 1074585600 /* 0x400ce000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_VAL_irq 206
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_reg {843776 /* 0xce000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_reg_IDX_0 843776
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_interrupts {206 /* 0xce */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_interrupts_IDX_0 206
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_zli 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_ce000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@4a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_4a000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_PATH "/soc/peripheral@40000000/uart@4a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FULL_NAME "uart@4a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_NODELABEL(fn) fn(uart00)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart00, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_ORD 89
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_ORD_STR_SORTABLE 00089

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_4a000
#define DT_N_NODELABEL_uart00        DT_N_S_soc_S_peripheral_40000000_S_uart_4a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_REG_IDX_0_VAL_ADDRESS 1074044928 /* 0x4004a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_VAL_irq 74
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_reg {303104 /* 0x4a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_reg_IDX_0 303104
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_interrupts {74 /* 0x4a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_interrupts_IDX_0 74
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_endtx_stoptx_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_frame_timeout_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_4a000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@c6000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PATH "/soc/peripheral@40000000/uart@c6000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FULL_NAME "uart@c6000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_NODELABEL(fn) fn(uart20)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart20, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_ORD 90
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_ORD_STR_SORTABLE 00090

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */ \
	39, /* /pin-controller/uart20_default */ \
	42, /* /pin-controller/uart20_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
#define DT_N_NODELABEL_uart20        DT_N_S_soc_S_peripheral_40000000_S_uart_c6000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_REG_IDX_0_VAL_ADDRESS 1074552832 /* 0x400c6000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_VAL_irq 198
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart20_default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart20_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_reg {811008 /* 0xc6000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_reg_IDX_0 811008
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_interrupts {198 /* 0xc6 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_interrupts_IDX_0 198
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_current_speed 115200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_current_speed_ENUM_IDX 12
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_current_speed_ENUM_VAL_115200_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart20_default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart20_default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart20_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart20_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_endtx_stoptx_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_frame_timeout_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c6000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@c7000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_c7000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_PATH "/soc/peripheral@40000000/uart@c7000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FULL_NAME "uart@c7000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_NODELABEL(fn) fn(uart21)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart21, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_ORD 91
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_ORD_STR_SORTABLE 00091

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_c7000
#define DT_N_NODELABEL_uart21        DT_N_S_soc_S_peripheral_40000000_S_uart_c7000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_REG_IDX_0_VAL_ADDRESS 1074556928 /* 0x400c7000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_VAL_irq 199
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_reg {815104 /* 0xc7000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_reg_IDX_0 815104
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_interrupts {199 /* 0xc7 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_interrupts_IDX_0 199
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_endtx_stoptx_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_frame_timeout_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c7000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@c8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_c8000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_PATH "/soc/peripheral@40000000/uart@c8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FULL_NAME "uart@c8000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_NODELABEL(fn) fn(uart22)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart22, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_ORD 92
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_ORD_STR_SORTABLE 00092

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_c8000
#define DT_N_NODELABEL_uart22        DT_N_S_soc_S_peripheral_40000000_S_uart_c8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_REG_IDX_0_VAL_ADDRESS 1074561024 /* 0x400c8000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_VAL_irq 200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_reg {819200 /* 0xc8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_reg_IDX_0 819200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_interrupts {200 /* 0xc8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_interrupts_IDX_0 200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_endtx_stoptx_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_frame_timeout_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_c8000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@104000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_104000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PATH "/soc/peripheral@40000000/uart@104000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FULL_NAME "uart@104000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_CHILD_IDX 43

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_NODELABEL(fn) fn(uart30)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart30, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_ORD 93
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_ORD_STR_SORTABLE 00093

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */ \
	44, /* /pin-controller/uart30_default */ \
	47, /* /pin-controller/uart30_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_104000
#define DT_N_NODELABEL_uart30        DT_N_S_soc_S_peripheral_40000000_S_uart_104000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_REG_IDX_0_VAL_ADDRESS 1074806784 /* 0x40104000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_VAL_irq 260
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart30_default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart30_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_reg {1064960 /* 0x104000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_reg_IDX_0 1064960
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_interrupts {260 /* 0x104 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_interrupts_IDX_0 260
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_current_speed 115200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_current_speed_ENUM_IDX 12
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_current_speed_ENUM_VAL_115200_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart30_default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart30_default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart30_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart30_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_endtx_stoptx_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_frame_timeout_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_104000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/watchdog@109000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000
 *
 * Binding (compatible = nordic,nrf-wdt):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/nordic,nrf-wdt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_PATH "/soc/peripheral@40000000/watchdog@109000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FULL_NAME "watchdog@109000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_CHILD_IDX 45

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_NODELABEL(fn) fn(wdt31)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt31, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_ORD 94
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_ORD_STR_SORTABLE 00094

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_EXISTS 1
#define DT_N_ALIAS_watchdog0       DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000
#define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000
#define DT_N_NODELABEL_wdt31       DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_REG_IDX_0_VAL_ADDRESS 1074827264 /* 0x40109000 */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_REG_IDX_0_VAL_SIZE 1568 /* 0x620 */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_VAL_irq 265
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_COMPAT_MATCHES_nordic_nrf_wdt 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_COMPAT_MODEL_IDX_0 "nrf-wdt"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible {"nordic,nrf-wdt"}
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_IDX_0 "nordic,nrf-wdt"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_reg {1085440 /* 0x109000 */, 1568 /* 0x620 */}
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_reg_IDX_0 1085440
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_reg_IDX_1 1568
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_interrupts {265 /* 0x109 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_interrupts_IDX_0 265
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/power@10e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_power_10e000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-power.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_PATH "/soc/peripheral@40000000/power@10e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FULL_NAME "power@10e000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_CHILD_IDX 49

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_NODELABEL(fn) fn(power)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(power, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_CHILD_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_ORD 95
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_ORD_STR_SORTABLE 00095

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_SUPPORTS_ORDS \
	96, /* /soc/peripheral@40000000/power@10e000/gpregret1@51c */ \
	97, /* /soc/peripheral@40000000/power@10e000/gpregret2@520 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_40000000_S_power_10e000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_peripheral_40000000_S_power_10e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_REG_IDX_0_VAL_ADDRESS 1074847744 /* 0x4010e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_RANGES_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1105920 /* 0x10e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_RANGES_IDX_0_VAL_LENGTH 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_VAL_irq 270
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_COMPAT_MODEL_IDX_0 "nrf-power"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-power
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_reg {1105920 /* 0x10e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_reg_IDX_0 1105920
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_interrupts {270 /* 0x10e */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_interrupts_IDX_0 270
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/power@10e000/gpregret1@51c
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c
 *
 * Binding (compatible = nordic,nrf-gpregret):
 *   $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_PATH "/soc/peripheral@40000000/power@10e000/gpregret1@51c"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FULL_NAME "gpregret1@51c"

/* Node parent (/soc/peripheral@40000000/power@10e000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_PARENT DT_N_S_soc_S_peripheral_40000000_S_power_10e000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_NODELABEL(fn) fn(gpregret1)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpregret1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_ORD 96
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_ORD_STR_SORTABLE 00096

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_REQUIRES_ORDS \
	95, /* /soc/peripheral@40000000/power@10e000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c
#define DT_N_NODELABEL_gpregret1        DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_REG_IDX_0_VAL_ADDRESS 1074849052 /* 0x4010e51c */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_COMPAT_MATCHES_nordic_nrf_gpregret 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_COMPAT_MODEL_IDX_0 "nrf-gpregret"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible {"nordic,nrf-gpregret"}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_IDX_0 "nordic,nrf-gpregret"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_reg {1308 /* 0x51c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_reg_IDX_0 1308
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/power@10e000/gpregret2@520
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520
 *
 * Binding (compatible = nordic,nrf-gpregret):
 *   $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_PATH "/soc/peripheral@40000000/power@10e000/gpregret2@520"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FULL_NAME "gpregret2@520"

/* Node parent (/soc/peripheral@40000000/power@10e000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_PARENT DT_N_S_soc_S_peripheral_40000000_S_power_10e000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_NODELABEL(fn) fn(gpregret2)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpregret2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_ORD 97
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_ORD_STR_SORTABLE 00097

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_REQUIRES_ORDS \
	95, /* /soc/peripheral@40000000/power@10e000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520
#define DT_N_NODELABEL_gpregret2        DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_REG_IDX_0_VAL_ADDRESS 1074849056 /* 0x4010e520 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_COMPAT_MATCHES_nordic_nrf_gpregret 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_COMPAT_MODEL_IDX_0 "nrf-gpregret"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible {"nordic,nrf-gpregret"}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_IDX_0 "nordic,nrf-gpregret"
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_reg {1312 /* 0x520 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_reg_IDX_0 1312
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/radio@8a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_radio_8a000
 *
 * Binding (compatible = nordic,nrf-radio):
 *   $ZEPHYR_BASE/dts/bindings/net/wireless/nordic,nrf-radio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_PATH "/soc/peripheral@40000000/radio@8a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FULL_NAME "radio@8a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_NODELABEL(fn) fn(radio)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(radio, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_CHILD_NUM 3
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_ORD 98
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_ORD_STR_SORTABLE 00098

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_SUPPORTS_ORDS \
	99, /* /soc/peripheral@40000000/radio@8a000/bt_hci_controller */ \
	100, /* /soc/peripheral@40000000/radio@8a000/bt_hci_sdc */ \
	101, /* /soc/peripheral@40000000/radio@8a000/ieee802154 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_radio DT_N_S_soc_S_peripheral_40000000_S_radio_8a000
#define DT_N_NODELABEL_radio         DT_N_S_soc_S_peripheral_40000000_S_radio_8a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_REG_IDX_0_VAL_ADDRESS 1074307072 /* 0x4008a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_VAL_irq 138
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_COMPAT_MATCHES_nordic_nrf_radio 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_COMPAT_MODEL_IDX_0 "nrf-radio"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible {"nordic,nrf-radio"}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_IDX_0 "nordic,nrf-radio"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-radio
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_radio
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RADIO
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_reg {565248 /* 0x8a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_reg_IDX_0 565248
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_interrupts {138 /* 0x8a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_interrupts_IDX_0 138
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_dfe_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_dfe_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_ieee802154_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_ieee802154_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_ble_2mbps_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_ble_2mbps_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_ble_coded_phy_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_ble_coded_phy_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_tx_high_power_supported 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_tx_high_power_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_cs_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_P_cs_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/radio@8a000/bt_hci_controller
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller
 *
 * Binding (compatible = zephyr,bt-hci-ll-sw-split):
 *   $ZEPHYR_BASE/dts/bindings/bluetooth/zephyr,bt-hci-ll-sw-split.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_PATH "/soc/peripheral@40000000/radio@8a000/bt_hci_controller"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FULL_NAME "bt_hci_controller"

/* Node parent (/soc/peripheral@40000000/radio@8a000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_PARENT DT_N_S_soc_S_peripheral_40000000_S_radio_8a000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_NODELABEL(fn) fn(bt_hci_controller)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(bt_hci_controller, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_ORD 99
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_ORD_STR_SORTABLE 00099

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_REQUIRES_ORDS \
	98, /* /soc/peripheral@40000000/radio@8a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_EXISTS 1
#define DT_N_INST_0_zephyr_bt_hci_ll_sw_split DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller
#define DT_N_NODELABEL_bt_hci_controller      DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_COMPAT_MATCHES_zephyr_bt_hci_ll_sw_split 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_COMPAT_MODEL_IDX_0 "bt-hci-ll-sw-split"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible {"zephyr,bt-hci-ll-sw-split"}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_IDX_0 "zephyr,bt-hci-ll-sw-split"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-ll-sw-split
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_ll_sw_split
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_LL_SW_SPLIT
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name "Controller"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_STRING_UNQUOTED Controller
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_STRING_TOKEN Controller
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_STRING_UPPER_TOKEN CONTROLLER
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_IDX_0 "Controller"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_name, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_name, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_name_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus "BT_HCI_BUS_VIRTUAL"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_STRING_UNQUOTED BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_STRING_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_STRING_UPPER_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_IDX_0 "BT_HCI_BUS_VIRTUAL"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_ENUM_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_ENUM_VAL_BT_HCI_BUS_VIRTUAL_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_ENUM_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_ENUM_UPPER_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_bus, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_bus, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_bus_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks {"BT_HCI_QUIRK_NO_AUTO_DLE"}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_IDX_0 "BT_HCI_QUIRK_NO_AUTO_DLE"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_IDX_0_STRING_UNQUOTED BT_HCI_QUIRK_NO_AUTO_DLE
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_IDX_0_STRING_TOKEN BT_HCI_QUIRK_NO_AUTO_DLE
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_IDX_0_STRING_UPPER_TOKEN BT_HCI_QUIRK_NO_AUTO_DLE
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_quirks, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_quirks, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_quirks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, bt_hci_quirks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_quirks_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_vs_ext 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller_P_bt_hci_vs_ext_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/radio@8a000/bt_hci_sdc
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc
 *
 * Binding (compatible = nordic,bt-hci-sdc):
 *   /Users/bryan/ncs/nrf/dts/bindings/bluetooth/nordic,bt-hci-sdc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_PATH "/soc/peripheral@40000000/radio@8a000/bt_hci_sdc"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FULL_NAME "bt_hci_sdc"

/* Node parent (/soc/peripheral@40000000/radio@8a000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_PARENT DT_N_S_soc_S_peripheral_40000000_S_radio_8a000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_NODELABEL(fn) fn(bt_hci_sdc)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_NODELABEL_VARGS(fn, ...) fn(bt_hci_sdc, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_ORD 100
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_ORD_STR_SORTABLE 00100

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_REQUIRES_ORDS \
	98, /* /soc/peripheral@40000000/radio@8a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_EXISTS 1
#define DT_N_INST_0_nordic_bt_hci_sdc DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc
#define DT_N_NODELABEL_bt_hci_sdc     DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_COMPAT_MATCHES_nordic_bt_hci_sdc 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_COMPAT_MODEL_IDX_0 "bt-hci-sdc"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible {"nordic,bt-hci-sdc"}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_IDX_0 "nordic,bt-hci-sdc"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_IDX_0_STRING_UNQUOTED nordic,bt-hci-sdc
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_IDX_0_STRING_TOKEN nordic_bt_hci_sdc
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_BT_HCI_SDC
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name "SDC"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_STRING_UNQUOTED SDC
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_STRING_TOKEN SDC
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_STRING_UPPER_TOKEN SDC
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_IDX_0 "SDC"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_name, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_name, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_name_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus "BT_HCI_BUS_VIRTUAL"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_STRING_UNQUOTED BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_STRING_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_STRING_UPPER_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_IDX_0 "BT_HCI_BUS_VIRTUAL"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_ENUM_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_ENUM_VAL_BT_HCI_BUS_VIRTUAL_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_ENUM_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_ENUM_UPPER_TOKEN BT_HCI_BUS_VIRTUAL
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_bus, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_bus, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_bus_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_vs_ext 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc_P_bt_hci_vs_ext_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/radio@8a000/ieee802154
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154
 *
 * Binding (compatible = nordic,nrf-ieee802154):
 *   $ZEPHYR_BASE/dts/bindings/ieee802154/nordic,nrf-ieee802154.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_PATH "/soc/peripheral@40000000/radio@8a000/ieee802154"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FULL_NAME "ieee802154"

/* Node parent (/soc/peripheral@40000000/radio@8a000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_PARENT DT_N_S_soc_S_peripheral_40000000_S_radio_8a000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_NODELABEL(fn) fn(ieee802154)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_NODELABEL_VARGS(fn, ...) fn(ieee802154, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_ORD 101
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_ORD_STR_SORTABLE 00101

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_REQUIRES_ORDS \
	98, /* /soc/peripheral@40000000/radio@8a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ieee802154 DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154
#define DT_N_NODELABEL_ieee802154         DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_COMPAT_MATCHES_nordic_nrf_ieee802154 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_COMPAT_MODEL_IDX_0 "nrf-ieee802154"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible {"nordic,nrf-ieee802154"}
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_IDX_0 "nordic,nrf-ieee802154"
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ieee802154
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ieee802154
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IEEE802154
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/regulator@120000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_regulator_120000
 *
 * Binding (compatible = nordic,nrf54l-regulators):
 *   $ZEPHYR_BASE/dts/bindings/regulator/nordic,nrf54l-regulators.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_PATH "/soc/peripheral@40000000/regulator@120000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FULL_NAME "regulator@120000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_CHILD_IDX 50

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_NODELABEL(fn) fn(regulators)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_NODELABEL_VARGS(fn, ...) fn(regulators, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_CHILD_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_ORD 102
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_ORD_STR_SORTABLE 00102

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_SUPPORTS_ORDS \
	103, /* /soc/peripheral@40000000/regulator@120000/regulator@120600 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_EXISTS 1
#define DT_N_INST_0_nordic_nrf54l_regulators DT_N_S_soc_S_peripheral_40000000_S_regulator_120000
#define DT_N_NODELABEL_regulators            DT_N_S_soc_S_peripheral_40000000_S_regulator_120000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_REG_IDX_0_VAL_ADDRESS 1074921472 /* 0x40120000 */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_COMPAT_MATCHES_nordic_nrf54l_regulators 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_COMPAT_MODEL_IDX_0 "nrf54l-regulators"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible {"nordic,nrf54l-regulators"}
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_IDX_0 "nordic,nrf54l-regulators"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf54l-regulators
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf54l_regulators
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF54L_REGULATORS
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_reg {1179648 /* 0x120000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_reg_IDX_0 1179648
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/regulator@120000/regulator@120600
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600
 *
 * Binding (compatible = nordic,nrf5x-regulator):
 *   $ZEPHYR_BASE/dts/bindings/regulator/nordic,nrf5x-regulator.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_PATH "/soc/peripheral@40000000/regulator@120000/regulator@120600"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FULL_NAME "regulator@120600"

/* Node parent (/soc/peripheral@40000000/regulator@120000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_PARENT DT_N_S_soc_S_peripheral_40000000_S_regulator_120000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_NODELABEL(fn) fn(vregmain)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregmain, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_ORD 103
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_ORD_STR_SORTABLE 00103

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_REQUIRES_ORDS \
	102, /* /soc/peripheral@40000000/regulator@120000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_EXISTS 1
#define DT_N_INST_0_nordic_nrf5x_regulator DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600
#define DT_N_NODELABEL_vregmain            DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_REG_IDX_0_VAL_ADDRESS 1181184 /* 0x120600 */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_COMPAT_MATCHES_nordic_nrf5x_regulator 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_COMPAT_MODEL_IDX_0 "nrf5x-regulator"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible {"nordic,nrf5x-regulator"}
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_IDX_0 "nordic,nrf5x-regulator"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5x-regulator
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5x_regulator
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5X_REGULATOR
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_reg {1181184 /* 0x120600 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_reg_IDX_0 1181184
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name "VREGMAIN"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_STRING_UNQUOTED VREGMAIN
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_STRING_TOKEN VREGMAIN
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_STRING_UPPER_TOKEN VREGMAIN
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_IDX_0 "VREGMAIN"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_name_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_initial_mode 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600_P_regulator_initial_mode_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@4a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_4a000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PATH "/soc/peripheral@40000000/spi@4a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FULL_NAME "spi@4a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_NODELABEL(fn) fn(spi00)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi00, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_CHILD_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_ORD 104
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_ORD_STR_SORTABLE 00104

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */ \
	24, /* /soc/peripheral@40000000/gpio@50400 */ \
	35, /* /pin-controller/spi00_default */ \
	37, /* /pin-controller/spi00_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_SUPPORTS_ORDS \
	105, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_40000000_S_spi_4a000
#define DT_N_NODELABEL_spi00        DT_N_S_soc_S_peripheral_40000000_S_spi_4a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_REG_IDX_0_VAL_ADDRESS 1074044928 /* 0x4004a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_VAL_irq 74
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi00_default
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi00_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_reg {303104 /* 0x4a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_reg_IDX_0 303104
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_interrupts {74 /* 0x4a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_interrupts_IDX_0 74
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_50400
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_IDX_0_VAL_pin 5
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_IDX_0_VAL_flags 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, cs_gpios, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, cs_gpios, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi00_default
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi00_default
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi00_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi00_sleep
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_max_frequency 32000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_rx_delay_supported 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_rx_delay 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_rx_delay_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_rx_delay_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@4a000/mx25r6435f@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0
 *
 * Binding (compatible = jedec,spi-nor):
 *   $ZEPHYR_BASE/dts/bindings/mtd/jedec,spi-nor.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_PATH "/soc/peripheral@40000000/spi@4a000/mx25r6435f@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FULL_NAME "mx25r6435f@0"

/* Node parent (/soc/peripheral@40000000/spi@4a000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_PARENT DT_N_S_soc_S_peripheral_40000000_S_spi_4a000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_NODELABEL(fn) fn(mx25r64)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(mx25r64, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_CHILD_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_ORD 105
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_ORD_STR_SORTABLE 00105

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_REQUIRES_ORDS \
	104, /* /soc/peripheral@40000000/spi@4a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_SUPPORTS_ORDS \
	106, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_EXISTS 1
#define DT_N_INST_0_jedec_spi_nor DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0
#define DT_N_NODELABEL_mx25r64    DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0

/* Bus info (controller: '/soc/peripheral@40000000/spi@4a000', type: '['spi']') */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_BUS_spi 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_BUS DT_N_S_soc_S_peripheral_40000000_S_spi_4a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_COMPAT_MATCHES_jedec_spi_nor 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0 "JEDEC Solid State Technology Association"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0 "spi-nor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible {"jedec,spi-nor"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_IDX_0 "jedec,spi-nor"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UNQUOTED jedec,spi-nor
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_TOKEN jedec_spi_nor
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UPPER_TOKEN JEDEC_SPI_NOR
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_duplex 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_duplex_ENUM_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_duplex_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_duplex_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_frame_format 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_frame_format_ENUM_IDX 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_frame_format_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_frame_format_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_cpol 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_cpol_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_cpha 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_cpha_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_hold_cs 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_spi_hold_cs_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id {194 /* 0xc2 */, 40 /* 0x28 */, 23 /* 0x17 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_IDX_0 194
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_IDX_1 40
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_IDX_2 23
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 1) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 2)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 2)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_LEN 3
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_jedec_id_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_size 67108864
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 241 /* 0xf1 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 3 /* 0x3 */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 4 /* 0x4 */, 187 /* 0xbb */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 35 /* 0x23 */, 114 /* 0x72 */, 245 /* 0xf5 */, 0 /* 0x0 */, 130 /* 0x82 */, 237 /* 0xed */, 4 /* 0x4 */, 204 /* 0xcc */, 68 /* 0x44 */, 131 /* 0x83 */, 72 /* 0x48 */, 68 /* 0x44 */, 48 /* 0x30 */, 176 /* 0xb0 */, 48 /* 0x30 */, 176 /* 0xb0 */, 247 /* 0xf7 */, 196 /* 0xc4 */, 213 /* 0xd5 */, 92 /* 0x5c */, 0 /* 0x0 */, 190 /* 0xbe */, 41 /* 0x29 */, 255 /* 0xff */, 240 /* 0xf0 */, 208 /* 0xd0 */, 255 /* 0xff */, 255 /* 0xff */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0 229
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1 32
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2 241
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7 3
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8 68
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9 235
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10 8
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11 107
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12 8
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13 59
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14 4
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15 187
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16 238
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28 12
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29 32
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30 15
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31 82
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32 16
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33 216
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36 35
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37 114
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38 245
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40 130
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41 237
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42 4
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43 204
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44 68
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45 131
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46 72
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47 68
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48 48
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49 176
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50 48
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51 176
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52 247
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53 196
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54 213
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55 92
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57 190
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58 41
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60 240
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61 208
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63 255
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 0) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 1) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 2) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 3) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 4) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 5) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 6) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 7) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 8) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 9) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 10) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 11) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 12) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 13) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 14) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 15) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 16) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 17) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 18) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 19) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 20) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 21) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 22) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 23) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 24) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 25) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 26) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 27) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 28) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 29) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 30) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 31) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 32) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 33) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 34) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 35) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 36) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 37) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 38) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 39) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 40) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 41) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 42) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 43) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 44) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 45) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 46) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 47) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 48) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 49) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 50) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 51) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 52) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 53) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 54) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 55) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 56) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 57) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 58) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 59) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 60) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 61) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 62) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 63)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 63)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_LEN 64
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_sfdp_bfp_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_requires_ulbpr 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_requires_ulbpr_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_has_dpd 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_has_dpd_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_t_enter_dpd 10000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_t_enter_dpd_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_t_exit_dpd 35000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_P_t_exit_dpd_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE/dts/bindings/mtd/fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_PATH "/soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FULL_NAME "partitions"

/* Node parent (/soc/peripheral@40000000/spi@4a000/mx25r6435f@0) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_CHILD_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_ORD 106
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_ORD_STR_SORTABLE 00106

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_REQUIRES_ORDS \
	105, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_SUPPORTS_ORDS \
	107, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@0 */ \
	108, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@8000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_PATH "/soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FULL_NAME "partition@0"

/* Node parent (/soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(slot1_partition)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_ORD 107
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00107

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	106, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label "app1-secure"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED app1-secure
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_STRING_TOKEN app1_secure
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN APP1_SECURE
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_IDX_0 "app1-secure"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_reg_IDX_1 32768
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_PATH "/soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions/partition@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FULL_NAME "partition@8000"

/* Node parent (/soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_PARENT DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_NODELABEL(fn) fn(slot1_ns_partition)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_ns_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_ORD 108
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_ORD_STR_SORTABLE 00108

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_REQUIRES_ORDS \
	106, /* /soc/peripheral@40000000/spi@4a000/mx25r6435f@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_EXISTS 1
#define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_REG_IDX_0_VAL_ADDRESS 32768 /* 0x8000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_REG_IDX_0_VAL_SIZE 917504 /* 0xe0000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label "app1-nonsecure"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_STRING_UNQUOTED app1-nonsecure
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_STRING_TOKEN app1_nonsecure
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_STRING_UPPER_TOKEN APP1_NONSECURE
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_IDX_0 "app1-nonsecure"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, label, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, label, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_reg {32768 /* 0x8000 */, 917504 /* 0xe0000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_reg_IDX_1 917504
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/vpr@4c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000
 *
 * Binding (compatible = nordic,nrf-vpr-coprocessor):
 *   $ZEPHYR_BASE/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_PATH "/soc/peripheral@40000000/vpr@4c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FULL_NAME "vpr@4c000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_PARENT DT_N_S_soc_S_peripheral_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_NODELABEL(fn) fn(cpuflpr_vpr)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuflpr_vpr, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_CHILD_NUM 2
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_ORD 109
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_ORD_STR_SORTABLE 00109

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_REQUIRES_ORDS \
	6, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_SUPPORTS_ORDS \
	110, /* /soc/peripheral@40000000/vpr@4c000/mailbox@0 */ \
	111, /* /soc/peripheral@40000000/vpr@4c000/mailbox@1 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vpr_coprocessor DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000
#define DT_N_NODELABEL_cpuflpr_vpr             DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_REG_IDX_0_VAL_ADDRESS 1074053120 /* 0x4004c000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_RANGES_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 311296 /* 0x4c000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_RANGES_IDX_0_VAL_LENGTH 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_COMPAT_MATCHES_nordic_nrf_vpr_coprocessor 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_COMPAT_MODEL_IDX_0 "nrf-vpr-coprocessor"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible {"nordic,nrf-vpr-coprocessor"}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_IDX_0 "nordic,nrf-vpr-coprocessor"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vpr-coprocessor
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vpr_coprocessor
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VPR_COPROCESSOR
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_reg {311296 /* 0x4c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_reg_IDX_0 311296
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/vpr@4c000/mailbox@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0
 *
 * Binding (compatible = nordic,nrf-vevif-task-tx):
 *   $ZEPHYR_BASE/dts/bindings/mbox/nordic,nrf-vevif-task-tx.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_PATH "/soc/peripheral@40000000/vpr@4c000/mailbox@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FULL_NAME "mailbox@0"

/* Node parent (/soc/peripheral@40000000/vpr@4c000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_PARENT DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_NODELABEL(fn) fn(cpuapp_vevif_tx)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_vevif_tx, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_ORD 110
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_ORD_STR_SORTABLE 00110

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_REQUIRES_ORDS \
	109, /* /soc/peripheral@40000000/vpr@4c000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vevif_task_tx DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0
#define DT_N_NODELABEL_cpuapp_vevif_tx       DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_REG_IDX_0_VAL_ADDRESS 1074053120 /* 0x4004c000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_COMPAT_MATCHES_nordic_nrf_vevif_task_tx 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_COMPAT_MODEL_IDX_0 "nrf-vevif-task-tx"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible {"nordic,nrf-vevif-task-tx"}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_IDX_0 "nordic,nrf-vevif-task-tx"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vevif-task-tx
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vevif_task_tx
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VEVIF_TASK_TX
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_reg {0 /* 0x0 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_nordic_tasks 7
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_nordic_tasks_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_nordic_tasks_mask 8323072
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0_P_nordic_tasks_mask_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/vpr@4c000/mailbox@1
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1
 *
 * Binding (compatible = nordic,nrf-vevif-event-rx):
 *   $ZEPHYR_BASE/dts/bindings/mbox/nordic,nrf-vevif-event-rx.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_PATH "/soc/peripheral@40000000/vpr@4c000/mailbox@1"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FULL_NAME "mailbox@1"

/* Node parent (/soc/peripheral@40000000/vpr@4c000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_PARENT DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_NODELABEL(fn) fn(cpuapp_vevif_rx)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_vevif_rx, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_ORD 111
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_ORD_STR_SORTABLE 00111

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_REQUIRES_ORDS \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */ \
	109, /* /soc/peripheral@40000000/vpr@4c000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vevif_event_rx DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1
#define DT_N_NODELABEL_cpuapp_vevif_rx        DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_REG_IDX_0_VAL_ADDRESS 1074053120 /* 0x4004c000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_VAL_irq 76
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_COMPAT_MATCHES_nordic_nrf_vevif_event_rx 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_COMPAT_MODEL_IDX_0 "nrf-vevif-event-rx"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, status, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible {"nordic,nrf-vevif-event-rx"}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_IDX_0 "nordic,nrf-vevif-event-rx"
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vevif-event-rx
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vevif_event_rx
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VEVIF_EVENT_RX
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, compatible, 0)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_reg {0 /* 0x0 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_interrupts {76 /* 0x4c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_interrupts_IDX_0 76
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_nordic_events 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_nordic_events_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_nordic_events_mask 1048576
#define DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1_P_nordic_events_mask_EXISTS 1

/*
 * Devicetree node: /soc/rram-controller@5004b000
 *
 * Node identifier: DT_N_S_soc_S_rram_controller_5004b000
 *
 * Binding (compatible = nordic,rram-controller):
 *   $ZEPHYR_BASE/dts/bindings/flash_controller/nordic,rram-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rram_controller_5004b000_PATH "/soc/rram-controller@5004b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rram_controller_5004b000_FULL_NAME "rram-controller@5004b000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rram_controller_5004b000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rram_controller_5004b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_NODELABEL(fn) fn(rram_controller)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rram_controller, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rram_controller_5004b000_CHILD_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rram_controller_5004b000_ORD 112
#define DT_N_S_soc_S_rram_controller_5004b000_ORD_STR_SORTABLE 00112

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rram_controller_5004b000_REQUIRES_ORDS \
	5, /* /soc */ \
	8, /* /soc/cpuapp-ppb-bus/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rram_controller_5004b000_SUPPORTS_ORDS \
	113, /* /soc/rram-controller@5004b000/rram@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rram_controller_5004b000_EXISTS 1
#define DT_N_INST_0_nordic_rram_controller DT_N_S_soc_S_rram_controller_5004b000
#define DT_N_NODELABEL_rram_controller     DT_N_S_soc_S_rram_controller_5004b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rram_controller_5004b000_REG_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_REG_IDX_0_VAL_ADDRESS 1342484480 /* 0x5004b000 */
#define DT_N_S_soc_S_rram_controller_5004b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_rram_controller_5004b000_RANGES_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_VAL_irq 75
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rram_controller_5004b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_rram_controller_5004b000_COMPAT_MATCHES_nordic_rram_controller 1
#define DT_N_S_soc_S_rram_controller_5004b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_rram_controller_5004b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_COMPAT_MODEL_IDX_0 "rram-controller"
#define DT_N_S_soc_S_rram_controller_5004b000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rram_controller_5004b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rram_controller_5004b000_P_wakeup_source 0
#define DT_N_S_soc_S_rram_controller_5004b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rram_controller_5004b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible {"nordic,rram-controller"}
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_IDX_0 "nordic,rram-controller"
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,rram-controller
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_IDX_0_STRING_TOKEN nordic_rram_controller
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_RRAM_CONTROLLER
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rram_controller_5004b000, compatible, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000, compatible, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_LEN 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_reg {1342484480 /* 0x5004b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_rram_controller_5004b000_P_reg_IDX_0 1342484480
#define DT_N_S_soc_S_rram_controller_5004b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_rram_controller_5004b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_interrupts {75 /* 0x4b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_rram_controller_5004b000_P_interrupts_IDX_0 75
#define DT_N_S_soc_S_rram_controller_5004b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rram_controller_5004b000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/rram-controller@5004b000/rram@0
 *
 * Node identifier: DT_N_S_soc_S_rram_controller_5004b000_S_rram_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE/dts/bindings/mtd/soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_PATH "/soc/rram-controller@5004b000/rram@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FULL_NAME "rram@0"

/* Node parent (/soc/rram-controller@5004b000) identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_PARENT DT_N_S_soc_S_rram_controller_5004b000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_NODELABEL(fn) fn(cpuapp_rram)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpuapp_rram, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_CHILD_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_ORD 113
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_ORD_STR_SORTABLE 00113

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_REQUIRES_ORDS \
	112, /* /soc/rram-controller@5004b000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_SUPPORTS_ORDS \
	114, /* /soc/rram-controller@5004b000/rram@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash   DT_N_S_soc_S_rram_controller_5004b000_S_rram_0
#define DT_N_NODELABEL_cpuapp_rram DT_N_S_soc_S_rram_controller_5004b000_S_rram_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_REG_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_REG_IDX_0_VAL_SIZE 1560576 /* 0x17d000 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_RANGES_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_IRQ_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_wakeup_source 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, compatible, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, compatible, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_LEN 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_reg {0 /* 0x0 */, 1560576 /* 0x17d000 */}
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_reg_IDX_1 1560576
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_erase_block_size 4096
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_write_block_size 16
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_P_write_block_size_EXISTS 1

/*
 * Devicetree node: /soc/rram-controller@5004b000/rram@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE/dts/bindings/mtd/fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_PATH "/soc/rram-controller@5004b000/rram@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FULL_NAME "partitions"

/* Node parent (/soc/rram-controller@5004b000/rram@0) identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_PARENT DT_N_S_soc_S_rram_controller_5004b000_S_rram_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_CHILD_NUM 3
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_ORD 114
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_ORD_STR_SORTABLE 00114

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_REQUIRES_ORDS \
	113, /* /soc/rram-controller@5004b000/rram@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_SUPPORTS_ORDS \
	115, /* /soc/rram-controller@5004b000/rram@0/partitions/partition@0 */ \
	116, /* /soc/rram-controller@5004b000/rram@0/partitions/partition@18000 */ \
	117, /* /soc/rram-controller@5004b000/rram@0/partitions/partition@20000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_EXISTS 1
#define DT_N_INST_1_fixed_partitions DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/rram-controller@5004b000/rram@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_PATH "/soc/rram-controller@5004b000/rram@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FULL_NAME "partition@0"

/* Node parent (/soc/rram-controller@5004b000/rram@0/partitions) identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_ORD 115
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00115

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	114, /* /soc/rram-controller@5004b000/rram@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 98304 /* 0x18000 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 98304 /* 0x18000 */}
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_reg_IDX_1 98304
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/rram-controller@5004b000/rram@0/partitions/partition@18000
 *
 * Node identifier: DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_PATH "/soc/rram-controller@5004b000/rram@0/partitions/partition@18000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FULL_NAME "partition@18000"

/* Node parent (/soc/rram-controller@5004b000/rram@0/partitions) identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_PARENT DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_NODELABEL_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_NODELABEL(fn) fn(slot0_partition)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_CHILD_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_ORD 116
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_ORD_STR_SORTABLE 00116

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_REQUIRES_ORDS \
	114, /* /soc/rram-controller@5004b000/rram@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_REG_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_REG_IDX_0_VAL_ADDRESS 98304 /* 0x18000 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_RANGES_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_IRQ_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_IRQ_LEVEL 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label "app-secure"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_STRING_UNQUOTED app-secure
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_STRING_TOKEN app_secure
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_STRING_UPPER_TOKEN APP_SECURE
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_IDX_0 "app-secure"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, label, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, label, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_LEN 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_label_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_read_only 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_reg {98304 /* 0x18000 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_reg_IDX_0 98304
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_reg_IDX_1 32768
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/rram-controller@5004b000/rram@0/partitions/partition@20000
 *
 * Node identifier: DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_PATH "/soc/rram-controller@5004b000/rram@0/partitions/partition@20000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FULL_NAME "partition@20000"

/* Node parent (/soc/rram-controller@5004b000/rram@0/partitions) identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_PARENT DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_NODELABEL_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_NODELABEL(fn) fn(slot0_ns_partition)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_ns_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_CHILD_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_ORD 117
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_ORD_STR_SORTABLE 00117

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_REQUIRES_ORDS \
	114, /* /soc/rram-controller@5004b000/rram@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_EXISTS 1
#define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_REG_NUM 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_REG_IDX_0_VAL_ADDRESS 131072 /* 0x20000 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_REG_IDX_0_VAL_SIZE 917504 /* 0xe0000 */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_RANGES_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_IRQ_NUM 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_IRQ_LEVEL 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_PARTITION_ID 4

/* Generic property macros: */
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label "app-nonsecure"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_STRING_UNQUOTED app-nonsecure
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_STRING_TOKEN app_nonsecure
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_STRING_UPPER_TOKEN APP_NONSECURE
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_IDX_0 "app-nonsecure"
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, label, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, label, 0)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_LEN 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_label_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_read_only 0
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_reg {131072 /* 0x20000 */, 917504 /* 0xe0000 */}
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_reg_IDX_1 917504
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000_P_reg_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_bt_hci                  DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller
#define DT_CHOSEN_zephyr_bt_hci_EXISTS           1
#define DT_CHOSEN_zephyr_entropy                 DT_N_S_psa_rng
#define DT_CHOSEN_zephyr_entropy_EXISTS          1
#define DT_CHOSEN_zephyr_console                 DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
#define DT_CHOSEN_zephyr_console_EXISTS          1
#define DT_CHOSEN_zephyr_shell_uart              DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS       1
#define DT_CHOSEN_zephyr_uart_mcumgr             DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS      1
#define DT_CHOSEN_zephyr_bt_mon_uart             DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
#define DT_CHOSEN_zephyr_bt_mon_uart_EXISTS      1
#define DT_CHOSEN_zephyr_bt_c2h_uart             DT_N_S_soc_S_peripheral_40000000_S_uart_c6000
#define DT_CHOSEN_zephyr_bt_c2h_uart_EXISTS      1
#define DT_CHOSEN_zephyr_flash_controller        DT_N_S_soc_S_rram_controller_5004b000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS 1
#define DT_CHOSEN_zephyr_flash                   DT_N_S_soc_S_rram_controller_5004b000_S_rram_0
#define DT_CHOSEN_zephyr_flash_EXISTS            1
#define DT_CHOSEN_zephyr_ieee802154              DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154
#define DT_CHOSEN_zephyr_ieee802154_EXISTS       1
#define DT_CHOSEN_zephyr_code_partition          DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1
#define DT_CHOSEN_zephyr_sram                    DT_N_S_soc_S_memory_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS             1
#define DT_CHOSEN_nordic_pm_ext_flash            DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0
#define DT_CHOSEN_nordic_pm_ext_flash_EXISTS     1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart20_default) fn(DT_N_S_pin_controller_S_uart20_default_S_group1) fn(DT_N_S_pin_controller_S_uart20_default_S_group2) fn(DT_N_S_pin_controller_S_uart20_sleep) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart30_default) fn(DT_N_S_pin_controller_S_uart30_default_S_group1) fn(DT_N_S_pin_controller_S_uart30_default_S_group2) fn(DT_N_S_pin_controller_S_uart30_sleep) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi00_default) fn(DT_N_S_pin_controller_S_spi00_default_S_group1) fn(DT_N_S_pin_controller_S_spi00_sleep) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm20_default) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1) fn(DT_N_S_pin_controller_S_pwm20_sleep) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_lfxo) fn(DT_N_S_clocks_S_hfxo) fn(DT_N_S_soc) fn(DT_N_S_soc_S_ficr_ffc000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600) fn(DT_N_S_soc_S_rram_controller_5004b000) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_cpuapp_ppb_bus) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010) fn(DT_N_S_chosen) fn(DT_N_S_psa_rng) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_1) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_aliases)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart20_default) fn(DT_N_S_pin_controller_S_uart20_default_S_group1) fn(DT_N_S_pin_controller_S_uart20_default_S_group2) fn(DT_N_S_pin_controller_S_uart20_sleep) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart30_default) fn(DT_N_S_pin_controller_S_uart30_default_S_group1) fn(DT_N_S_pin_controller_S_uart30_default_S_group2) fn(DT_N_S_pin_controller_S_uart30_sleep) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi00_default) fn(DT_N_S_pin_controller_S_spi00_default_S_group1) fn(DT_N_S_pin_controller_S_spi00_sleep) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm20_default) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1) fn(DT_N_S_pin_controller_S_pwm20_sleep) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_lfxo) fn(DT_N_S_clocks_S_hfxo) fn(DT_N_S_soc) fn(DT_N_S_soc_S_ficr_ffc000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600) fn(DT_N_S_soc_S_rram_controller_5004b000) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_cpuapp_ppb_bus) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100) fn(DT_N_S_chosen) fn(DT_N_S_psa_rng) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_1) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_aliases)
#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__) fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_42000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_4a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_1, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vpr_4c000_S_mailbox_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_55000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_82000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_85000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_87000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_sdc, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_c2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_c8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_c8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_c9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ca000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cb000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cc000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_cd000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_ce000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_d1000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d3000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_nfct_d6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_dd000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_qdec_e1000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_grtc_e2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_102000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_104000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_104000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_104000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_comparator_106000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_10e000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_psa_rng, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_1, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__)
#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart20_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart30_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi00_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm20_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__) fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_psa_rng, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_1, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__)
#define DT_COMPAT_fixed_partitions_LABEL_app1_secure DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_app1_secure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_app1_nonsecure DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions_S_partition_8000
#define DT_COMPAT_fixed_partitions_LABEL_app1_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_app_secure DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_18000
#define DT_COMPAT_fixed_partitions_LABEL_app_secure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_app_nonsecure DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions_S_partition_20000
#define DT_COMPAT_fixed_partitions_LABEL_app_nonsecure_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_nordic_nrf54l15dk_nrf54l15_cpuapp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_itm 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_lfxo 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_hfxo 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1
#define DT_COMPAT_HAS_OKAY_jedec_spi_nor 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_radio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ieee802154 1
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_ll_sw_split 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pwm 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_temp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf54l_regulators 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5x_regulator 1
#define DT_COMPAT_HAS_OKAY_nordic_rram_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
#define DT_COMPAT_HAS_OKAY_zephyr_psa_crypto_rng 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_pwm_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_nordic_nrf54l15dk_nrf54l15_cpuapp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1
#define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_itm_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_lfxo_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_hfxo_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spim_NUM_OKAY 1
#define DT_N_INST_jedec_spi_nor_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 3
#define DT_N_INST_nordic_nrf_radio_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ieee802154_NUM_OKAY 1
#define DT_N_INST_zephyr_bt_hci_ll_sw_split_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_pwm_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_temp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf54l_regulators_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5x_regulator_NUM_OKAY 1
#define DT_N_INST_nordic_rram_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
#define DT_N_INST_zephyr_psa_crypto_rng_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_pwm_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_FOREACH_OKAY_nordic_nrf54l15dk_nrf54l15_cpuapp(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf54l15dk_nrf54l15_cpuapp(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf54l15dk_nrf54l15_cpuapp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf54l15dk_nrf54l15_cpuapp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci)
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cortex_m33f(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv8m_itm(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_FOREACH_OKAY_VARGS_arm_armv8m_itm(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv8m_itm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_itm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_lfxo(fn) fn(DT_N_S_clocks_S_lfxo)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_lfxo(fn, ...) fn(DT_N_S_clocks_S_lfxo, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_lfxo(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_lfxo(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_hfxo(fn) fn(DT_N_S_clocks_S_hfxo)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_hfxo(fn, ...) fn(DT_N_S_clocks_S_hfxo, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_hfxo(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_hfxo(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc) fn(DT_N_S_soc_S_cpuapp_ppb_bus)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_cpuapp_ppb_bus, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_ffc000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_ffc000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_spim(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_jedec_spi_nor(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0)
#define DT_FOREACH_OKAY_VARGS_jedec_spi_nor(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_jedec_spi_nor(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_jedec_spi_nor(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions)
#define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_4a000_S_mx25r6435f_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0_S_partitions, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_50400, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_d8200, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_10a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_radio(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_radio(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_radio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_radio(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ieee802154(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ieee802154(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_ieee802154, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ieee802154(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ieee802154(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_bt_hci_ll_sw_split(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller)
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_ll_sw_split(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_radio_8a000_S_bt_hci_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_ll_sw_split(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_ll_sw_split(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_uarte(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_c6000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_pwm(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pwm(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_d2000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pwm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pwm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_d5000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_temp(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_temp(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_temp_d7000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_temp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_temp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_da000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpiote_10c000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_109000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_10e000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf54l_regulators(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf54l_regulators(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf54l_regulators(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf54l_regulators(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf5x_regulator(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf5x_regulator(fn, ...) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_120000_S_regulator_120600, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf5x_regulator(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5x_regulator(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_rram_controller(fn) fn(DT_N_S_soc_S_rram_controller_5004b000)
#define DT_FOREACH_OKAY_VARGS_nordic_rram_controller(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_rram_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_rram_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_rram_controller_5004b000_S_rram_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_v8m_nvic(fn) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100)
#define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...) fn(DT_N_S_soc_S_cpuapp_ppb_bus_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_psa_crypto_rng(fn) fn(DT_N_S_psa_rng)
#define DT_FOREACH_OKAY_VARGS_zephyr_psa_crypto_rng(fn, ...) fn(DT_N_S_psa_rng, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_psa_crypto_rng(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_psa_crypto_rng(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_pwmleds)
#define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_pwmleds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_buttons)
#define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_buttons, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
#define DT_COMPAT_jedec_spi_nor_BUS_spi 1
