# 0 "C:/ncs/v3.0.2/zephyr/misc/empty_file.c"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts" 1






/dts-v1/;

# 1 "C:/ncs/v3.0.2/zephyr/dts/arm/nordic/nrf54l15_cpuapp.dtsi" 1 3 4






# 1 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l15.dtsi" 1 3 4






# 1 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l_05_10_15.dtsi" 1 3 4






# 1 "C:/ncs/v3.0.2/zephyr/dts/common/mem.h" 1 3 4
# 8 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l_05_10_15.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 1 3 4






# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/adc.h" 1 3 4
# 9 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/adc.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/dt-util.h" 1 3 4
# 19 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/dt-util.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_macro.h" 1 3 4
# 34 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_macro.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 1 3 4
# 18 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_loops.h" 1 3 4
# 1083 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_loops.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_listify.h" 1 3 4
# 1084 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_loops.h" 2 3 4
# 19 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 162 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal_is_eq.h" 1 3 4
# 163 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 193 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal_util_inc.h" 1 3 4
# 194 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 2 3 4


# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal_util_dec.h" 1 3 4
# 197 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 2 3 4


# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal_util_x2.h" 1 3 4
# 200 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 35 "C:/ncs/v3.0.2/zephyr/include/zephyr/sys/util_macro.h" 2 3 4
# 20 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/dt-util.h" 2 3 4
# 10 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/adc.h" 2 3 4
# 8 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/gpio/gpio.h" 1 3 4
# 9 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/i2c/i2c.h" 1 3 4
# 10 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h" 1 3 4
# 11 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h" 1 3 4
# 12 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/pwm/pwm.h" 1 3 4
# 13 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4

# 1 "C:/ncs/v3.0.2/zephyr/dts/common/freq.h" 1 3 4
# 15 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/dts/arm/nordic/override.dtsi" 1 3 4
# 16 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 2 3 4
# 24 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf_common.dtsi" 3 4
/ {
 pinctrl: pin-controller {




  compatible = "nordic,nrf-pinctrl";
 };

 rng_hci: entropy_bt_hci {
  compatible = "zephyr,bt-hci-entropy";
  status = "okay";
 };

 sw_pwm: sw-pwm {
  compatible = "nordic,nrf-sw-pwm";
  status = "disabled";
  generator = <&timer1>;
  clock-prescaler = <0>;
  #pwm-cells = <3>;
 };
};
# 9 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l_05_10_15.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h" 1 3 4
# 10 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v2.h" 1 3 4
# 10 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v2.h" 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc.h" 1 3 4
# 11 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v2.h" 2 3 4
# 11 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h" 2 3 4
# 10 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l_05_10_15.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/include/zephyr/dt-bindings/regulator/nrf5x.h" 1 3 4
# 11 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l_05_10_15.dtsi" 2 3 4

/delete-node/ &sw_pwm;





/ {
 #address-cells = <1>;
 #size-cells = <1>;

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpuapp: cpu@0 {
   compatible = "arm,cortex-m33f";
   reg = <0>;
   device_type = "cpu";
   clocks = <&hfpll>;
   #address-cells = <1>;
   #size-cells = <1>;
   itm: itm@e0000000 {
    compatible = "arm,armv8m-itm";
    reg = <0xe0000000 0x1000>;
    swo-ref-frequency = <(((128) * 1000) * 1000)>;
   };
  };

  cpuflpr: cpu@1 {
   compatible = "nordic,vpr";
   reg = <1>;
   device_type = "cpu";
   clocks = <&hfpll>;
   riscv,isa = "rv32emc";
   nordic,bus-width = <32>;
  };
 };

 clocks {
  pclk: pclk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <(((16) * 1000) * 1000)>;
  };

  lfxo: lfxo {
   compatible = "nordic,nrf-lfxo";
   #clock-cells = <0>;
   clock-frequency = <32768>;
  };

  hfxo: hfxo {
   compatible = "nordic,nrf-hfxo";
   #clock-cells = <0>;
   clock-frequency = <(((32) * 1000) * 1000)>;
  };

  hfpll: hfpll {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <(((128) * 1000) * 1000)>;
  };
 };

 soc {
  #address-cells = <1>;
  #size-cells = <1>;




  uicr: uicr@ffd000 {
   compatible = "nordic,nrf-uicr";
   reg = <0xffd000 0x1000>;
  };

  ficr: ficr@ffc000 {
   compatible = "nordic,nrf-ficr";
   reg = <0xffc000 0x1000>;
   #nordic,ficr-cells = <1>;
  };

  cpuapp_sram: memory@20000000 {
   compatible = "mmio-sram";
   #address-cells = <1>;
   #size-cells = <1>;
  };







  global_peripherals: peripheral@50000000 {
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x50000000 0x10000000>;


   dppic00: dppic@42000 {
    compatible = "nordic,nrf-dppic";
    reg = <0x42000 0x808>;
    status = "disabled";
   };

   ppib00: ppib@43000 {
    compatible = "nordic,nrf-ppib";
    reg = <0x43000 0x1000>;
    status = "disabled";
   };

   ppib01: ppib@44000 {
    compatible = "nordic,nrf-ppib";
    reg = <0x44000 0x1000>;
    status = "disabled";
   };

   spi00: spi@4a000 {






    compatible = "nordic,nrf-spim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x4a000 0x1000>;
    interrupts = <74 1>;
    max-frequency = <(((32) * 1000) * 1000)>;
    easydma-maxcnt-bits = <16>;
    rx-delay-supported;
    rx-delay = <1>;
    status = "disabled";
   };

   uart00: uart@4a000 {
    compatible = "nordic,nrf-uarte";
    reg = <0x4a000 0x1000>;
    interrupts = <74 1>;
    clocks = <&hfpll>;
    status = "disabled";
    endtx-stoptx-supported;
    frame-timeout-supported;
   };

   cpuflpr_vpr: vpr@4c000 {
    compatible = "nordic,nrf-vpr-coprocessor";
    reg = <0x4c000 0x1000>;
    ranges = <0x0 0x4c000 0x1000>;
    #address-cells = <1>;
    #size-cells = <1>;
    status = "disabled";

    cpuflpr_clic: interrupt-controller@f0000000 {
     compatible = "nordic,nrf-clic";
     reg = <0xf0000000 0x1780>;
     interrupt-controller;
     #interrupt-cells = <2>;
     #address-cells = <1>;
     status = "disabled";
    };
   };

   gpio2: gpio@50400 {
    compatible = "nordic,nrf-gpio";
    gpio-controller;
    reg = <0x50400 0x300>;
    #gpio-cells = <2>;
    ngpios = <11>;
    status = "disabled";
    port = <2>;
   };

   timer00: timer@55000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0x55000 0x1000>;
    cc-num = <6>;
    max-bit-width = <32>;
    interrupts = <85 1>;
    clocks = <&hfpll>;
    prescaler = <0>;
   };

   dppic10: dppic@82000 {
    compatible = "nordic,nrf-dppic";
    reg = <0x82000 0x808>;
    status = "disabled";
   };

   ppib10: ppib@83000 {
    compatible = "nordic,nrf-ppib";
    reg = <0x83000 0x1000>;
    status = "disabled";
   };

   ppib11: ppib@84000 {
    compatible = "nordic,nrf-ppib";
    reg = <0x84000 0x1000>;
    status = "disabled";
   };

   timer10: timer@85000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0x85000 0x1000>;
    cc-num = <8>;
    max-bit-width = <32>;
    interrupts = <133 1>;
    clocks = <&hfxo>;
    prescaler = <0>;
   };

   egu10: egu@87000 {
    compatible = "nordic,nrf-egu";
    reg = <0x87000 0x1000>;
    interrupts = <135 1>;
    status = "disabled";
   };

   radio: radio@8a000 {
    compatible = "nordic,nrf-radio";
    reg = <0x8a000 0x1000>;
    interrupts = <138 1>;
    status = "disabled";
    dfe-supported;
    ieee802154-supported;
    ble-2mbps-supported;
    ble-coded-phy-supported;
    cs-supported;

    ieee802154: ieee802154 {
     compatible = "nordic,nrf-ieee802154";
     status = "disabled";
    };

    bt_hci_sdc: bt_hci_sdc {
     compatible = "nordic,bt-hci-sdc";
     status = "disabled";
    };

    bt_hci_controller: bt_hci_controller {
     compatible = "zephyr,bt-hci-ll-sw-split";
     status = "disabled";
    };
   };

   dppic20: dppic@c2000 {
    compatible = "nordic,nrf-dppic";
    reg = <0xc2000 0x808>;
    status = "disabled";
   };

   ppib20: ppib@c3000 {
    compatible = "nordic,nrf-ppib";
    reg = <0xc3000 0x1000>;
    status = "disabled";
   };

   ppib21: ppib@c4000 {
    compatible = "nordic,nrf-ppib";
    reg = <0xc4000 0x1000>;
    status = "disabled";
   };

   ppib22: ppib@c5000 {
    compatible = "nordic,nrf-ppib";
    reg = <0xc5000 0x1000>;
    status = "disabled";
   };

   i2c20: i2c@c6000 {
    compatible = "nordic,nrf-twim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xc6000 0x1000>;
    interrupts = <198 1>;
    easydma-maxcnt-bits = <16>;
    status = "disabled";
    zephyr,pm-device-runtime-auto;
   };

   spi20: spi@c6000 {






    compatible = "nordic,nrf-spim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xc6000 0x1000>;
    interrupts = <198 1>;
    max-frequency = <(((8) * 1000) * 1000)>;
    easydma-maxcnt-bits = <16>;
    rx-delay-supported;
    rx-delay = <1>;
    status = "disabled";
   };

   uart20: uart@c6000 {
    compatible = "nordic,nrf-uarte";
    reg = <0xc6000 0x1000>;
    interrupts = <198 1>;
    status = "disabled";
    endtx-stoptx-supported;
    frame-timeout-supported;
   };

   i2c21: i2c@c7000 {
    compatible = "nordic,nrf-twim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xc7000 0x1000>;
    interrupts = <199 1>;
    easydma-maxcnt-bits = <16>;
    status = "disabled";
    zephyr,pm-device-runtime-auto;
   };

   spi21: spi@c7000 {






    compatible = "nordic,nrf-spim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xc7000 0x1000>;
    interrupts = <199 1>;
    max-frequency = <(((8) * 1000) * 1000)>;
    easydma-maxcnt-bits = <16>;
    rx-delay-supported;
    rx-delay = <1>;
    status = "disabled";
   };

   uart21: uart@c7000 {
    compatible = "nordic,nrf-uarte";
    reg = <0xc7000 0x1000>;
    interrupts = <199 1>;
    status = "disabled";
    endtx-stoptx-supported;
    frame-timeout-supported;
   };

   i2c22: i2c@c8000 {
    compatible = "nordic,nrf-twim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xc8000 0x1000>;
    interrupts = <200 1>;
    easydma-maxcnt-bits = <16>;
    status = "disabled";
    zephyr,pm-device-runtime-auto;
   };

   spi22: spi@c8000 {






    compatible = "nordic,nrf-spim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xc8000 0x1000>;
    interrupts = <200 1>;
    max-frequency = <(((8) * 1000) * 1000)>;
    easydma-maxcnt-bits = <16>;
    rx-delay-supported;
    rx-delay = <1>;
    status = "disabled";
   };

   uart22: uart@c8000 {
    compatible = "nordic,nrf-uarte";
    reg = <0xc8000 0x1000>;
    interrupts = <200 1>;
    status = "disabled";
    endtx-stoptx-supported;
    frame-timeout-supported;
   };

   egu20: egu@c9000 {
    compatible = "nordic,nrf-egu";
    reg = <0xc9000 0x1000>;
    interrupts = <201 1>;
    status = "disabled";
   };

   timer20: timer@ca000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0xca000 0x1000>;
    cc-num = <6>;
    max-bit-width = <32>;
    interrupts = <202 1>;
    prescaler = <0>;
   };

   timer21: timer@cb000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0xcb000 0x1000>;
    cc-num = <6>;
    max-bit-width = <32>;
    interrupts = <203 1>;
    prescaler = <0>;
   };

   timer22: timer@cc000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0xcc000 0x1000>;
    cc-num = <6>;
    max-bit-width = <32>;
    interrupts = <204 1>;
    prescaler = <0>;
   };

   timer23: timer@cd000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0xcd000 0x1000>;
    cc-num = <6>;
    max-bit-width = <32>;
    interrupts = <205 1>;
    prescaler = <0>;
   };

   timer24: timer@ce000 {
    compatible = "nordic,nrf-timer";
    status = "disabled";
    reg = <0xce000 0x1000>;
    cc-num = <6>;
    max-bit-width = <32>;
    interrupts = <206 1>;
    prescaler = <0>;
   };

   pdm20: pdm@d0000 {
    compatible = "nordic,nrf-pdm";
    status = "disabled";
    reg = <0xd0000 0x1000>;
    interrupts = <208 1>;
   };

   pdm21: pdm@d1000 {
    compatible = "nordic,nrf-pdm";
    status = "disabled";
    reg = <0xd1000 0x1000>;
    interrupts = <209 1>;
   };

   pwm20: pwm@d2000 {
    compatible = "nordic,nrf-pwm";
    status = "disabled";
    reg = <0xd2000 0x1000>;
    interrupts = <210 1>;
    #pwm-cells = <3>;
   };

   pwm21: pwm@d3000 {
    compatible = "nordic,nrf-pwm";
    status = "disabled";
    reg = <0xd3000 0x1000>;
    interrupts = <211 1>;
    #pwm-cells = <3>;
   };

   pwm22: pwm@d4000 {
    compatible = "nordic,nrf-pwm";
    status = "disabled";
    reg = <0xd4000 0x1000>;
    interrupts = <212 1>;
    #pwm-cells = <3>;
   };

   adc: adc@d5000 {
    compatible = "nordic,nrf-saadc";
    reg = <0xd5000 0x1000>;
    interrupts = <213 1>;
    status = "disabled";
    #io-channel-cells = <1>;
    zephyr,pm-device-runtime-auto;
   };

   nfct: nfct@d6000 {
    compatible = "nordic,nrf-nfct";
    reg = <0xd6000 0x1000>;
    interrupts = <214 1>;
    status = "disabled";
   };

   temp: temp@d7000 {
    compatible = "nordic,nrf-temp";
    reg = <0xd7000 0x1000>;
    interrupts = <215 1>;
    status = "disabled";
   };

   gpio1: gpio@d8200 {
    compatible = "nordic,nrf-gpio";
    gpio-controller;
    reg = <0xd8200 0x300>;
    #gpio-cells = <2>;
    ngpios = <16>;
    status = "disabled";
    port = <1>;
    gpiote-instance = <&gpiote20>;
   };

   gpiote20: gpiote@da000 {
    compatible = "nordic,nrf-gpiote";
    reg = <0xda000 0x1000>;
    status = "disabled";
    instance = <20>;
   };

   i2s20: i2s@dd000 {
    compatible = "nordic,nrf-i2s";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0xdd000 0x1000>;
    interrupts = <221 1>;
    status = "disabled";
   };

   qdec20: qdec@e0000 {
    compatible = "nordic,nrf-qdec";
    reg = <0xe0000 0x1000>;
    interrupts = <224 1>;
    status = "disabled";
   };

   qdec21: qdec@e1000 {
    compatible = "nordic,nrf-qdec";
    reg = <0xe1000 0x1000>;
    interrupts = <225 1>;
    status = "disabled";
   };

   grtc: grtc@e2000 {
    compatible = "nordic,nrf-grtc";
    reg = <0xe2000 0x1000>;
    cc-num = <12>;
    clocks = <&lfxo>, <&pclk>;
    clock-names = "lfclock", "hfclock";
    status = "disabled";
   };

   dppic30: dppic@102000 {
    compatible = "nordic,nrf-dppic";
    reg = <0x102000 0x808>;
    status = "disabled";
   };

   ppib30: ppib@103000 {
    compatible = "nordic,nrf-ppib";
    reg = <0x103000 0x1000>;
    status = "disabled";
   };

   i2c30: i2c@104000 {
    compatible = "nordic,nrf-twim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x104000 0x1000>;
    interrupts = <260 1>;
    easydma-maxcnt-bits = <16>;
    status = "disabled";
    zephyr,pm-device-runtime-auto;
   };

   spi30: spi@104000 {






    compatible = "nordic,nrf-spim";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x104000 0x1000>;
    interrupts = <260 1>;
    max-frequency = <(((8) * 1000) * 1000)>;
    easydma-maxcnt-bits = <16>;
    rx-delay-supported;
    rx-delay = <1>;
    status = "disabled";
   };

   uart30: uart@104000 {
    compatible = "nordic,nrf-uarte";
    reg = <0x104000 0x1000>;
    interrupts = <260 1>;
    status = "disabled";
    endtx-stoptx-supported;
    frame-timeout-supported;
   };

   clock: clock@10e000 {
    compatible = "nordic,nrf-clock";
    reg = <0x10e000 0x1000>;
    interrupts = <261 1>;
    status = "disabled";
   };

   power: power@10e000 {
    compatible = "nordic,nrf-power";
    reg = <0x10e000 0x1000>;
    ranges = <0x0 0x10e000 0x1000>;
    interrupts = <261 1>;
    status = "disabled";
    #address-cells = <1>;
    #size-cells = <1>;

    gpregret1: gpregret1@51c {
     #address-cells = <1>;
     #size-cells = <1>;
     compatible = "nordic,nrf-gpregret";
     reg = <0x51c 0x1>;
     status = "disabled";
    };

    gpregret2: gpregret2@520 {
     #address-cells = <1>;
     #size-cells = <1>;
     compatible = "nordic,nrf-gpregret";
     reg = <0x520 0x1>;
     status = "disabled";
    };
   };

   comp: comparator@106000 {




    compatible = "nordic,nrf-comp";
    reg = <0x106000 0x1000>;
    status = "disabled";
    interrupts = <262 1>;
   };




   wdt30: watchdog@108000 {
    compatible = "nordic,nrf-wdt";
    reg = <0x108000 0x620>;
    interrupts = <264 1>;
    status = "disabled";
   };


   wdt31: watchdog@109000 {
    compatible = "nordic,nrf-wdt";
    reg = <0x109000 0x620>;
    interrupts = <265 1>;
    status = "disabled";
   };

   gpio0: gpio@10a000 {
    compatible = "nordic,nrf-gpio";
    gpio-controller;
    reg = <0x10a000 0x300>;
    #gpio-cells = <2>;
    ngpios = <5>;
    status = "disabled";
    port = <0>;
    gpiote-instance = <&gpiote30>;
   };

   gpiote30: gpiote@10c000 {
    compatible = "nordic,nrf-gpiote";
    reg = <0x10c000 0x1000>;
    status = "disabled";
    instance = <30>;
   };

   regulators: regulator@120000 {
    compatible = "nordic,nrf54l-regulators";
    reg = <0x120000 0x1000>;
    status = "disabled";
    #address-cells = <1>;
    #size-cells = <1>;

    vregmain: regulator@120600 {
     compatible = "nordic,nrf5x-regulator";
     reg = <0x120600 0x1>;
     status = "disabled";
     regulator-name = "VREGMAIN";
     regulator-initial-mode = <0>;
    };
   };
  };

  rram_controller: rram-controller@5004b000 {
   compatible = "nordic,rram-controller";
   reg = <0x5004b000 0x1000>;
   #address-cells = <1>;
   #size-cells = <1>;
   interrupts = <75 1>;

   cpuapp_rram: rram@0 {
    compatible = "soc-nv-flash";
    erase-block-size = <4096>;
    write-block-size = <16>;
   };
  };

  cpuapp_ppb: cpuapp-ppb-bus {
   #address-cells = <1>;
   #size-cells = <1>;

   cpuapp_nvic: interrupt-controller@e000e100 {
    #address-cells = <1>;
    compatible = "arm,v8m-nvic";
    reg = <0xe000e100 0xc00>;
    arm,num-irq-priority-bits = <3>;
    interrupt-controller;
    #interrupt-cells = <2>;
   };

   cpuapp_systick: timer@e000e010 {
    compatible = "arm,armv8m-systick";
    reg = <0xe000e010 0x10>;
    status = "disabled";
   };
  };
 };
};
# 8 "C:/ncs/v3.0.2/zephyr/dts/common/nordic/nrf54l15.dtsi" 2 3 4

&cpuapp_sram {
 reg = <0x20000000 ((188) * 1024)>;
 ranges = <0x0 0x20000000 ((188) * 1024)>;
};


/ {
 soc {
  cpuflpr_sram: memory@2002f000 {
   compatible = "mmio-sram";
   reg = <0x2002f000 ((68) * 1024)>;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x2002f000 ((68) * 1024)>;
  };
 };
};

&cpuapp_rram {
 reg = <0x0 ((1428) * 1024)>;
};


&rram_controller {
 cpuflpr_rram: rram@165000 {
  compatible = "soc-nv-flash";
  reg = <0x165000 ((96) * 1024)>;
  erase-block-size = <4096>;
  write-block-size = <16>;
 };
};
# 8 "C:/ncs/v3.0.2/zephyr/dts/arm/nordic/nrf54l15_cpuapp.dtsi" 2 3 4
# 1 "C:/ncs/v3.0.2/zephyr/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi" 1 3 4






cpu: &cpuapp {};
systick: &cpuapp_systick {};
nvic: &cpuapp_nvic {};

/delete-node/ &cpuflpr;
/delete-node/ &cpuflpr_rram;
/delete-node/ &cpuflpr_sram;
/delete-node/ &cpuflpr_clic;

/ {
 chosen {
  zephyr,bt-hci = &bt_hci_sdc;
  zephyr,entropy = &psa_rng;
 };

 soc {
  compatible = "simple-bus";
  interrupt-parent = <&cpuapp_nvic>;
  ranges;
 };

 psa_rng: psa-rng {
  compatible = "zephyr,psa-crypto-rng";
  status = "okay";
 };
};

&bt_hci_sdc {
 status = "okay";
};

&cpuflpr_vpr {
 cpuapp_vevif_rx: mailbox@1 {
  compatible = "nordic,nrf-vevif-event-rx";
  reg = <0x1 0x1000>;
  status = "disabled";
  interrupts = <76 1>;
  #mbox-cells = <1>;
  nordic,events = <1>;
  nordic,events-mask = <0x00100000>;
 };

 cpuapp_vevif_tx: mailbox@0 {
  compatible = "nordic,nrf-vevif-task-tx";
  reg = <0x0 0x1000>;
  #mbox-cells = <1>;
  nordic,tasks = <7>;
  nordic,tasks-mask = <0x007f0000>;
  status = "disabled";
 };
};

&cpuapp_ppb {
 compatible = "simple-bus";
 ranges;
};

&grtc {



 interrupts = <228 1>,

  <229 1>;
};

&gpiote20 {



 interrupts = <219 1>;

};

&gpiote30 {



 interrupts = <269 1>;

};

&dppic00 {
 status = "okay";
};

&dppic10 {
 status = "okay";
};

&dppic20 {
 status = "okay";
};

&dppic30 {
 status = "okay";
};

&ppib00 {
 status = "okay";
};

&ppib01 {
 status = "okay";
};

&ppib10 {
 status = "okay";
};

&ppib11 {
 status = "okay";
};

&ppib20 {
 status = "okay";
};

&ppib21 {
 status = "okay";
};

&ppib22 {
 status = "okay";
};

&ppib30 {
 status = "okay";
};
# 9 "C:/ncs/v3.0.2/zephyr/dts/arm/nordic/nrf54l15_cpuapp.dtsi" 2 3 4


&pinctrl {

 uart20_default: uart20_default {
  group1 {
   psels = <((((((1) * 32U) + (4)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>;
  };
  group2 {
   psels = <((((((1) * 32U) + (5)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>;

  };
 };

 uart20_sleep: uart20_sleep {
  group1 {
   psels = <((((((1) * 32U) + (4)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };
 uart00_default: uart00_default {
  group1 {
   psels = <((((((2) * 32U) + (2)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>;
  };
  group2 {
   psels = <((((((2) * 32U) + (0)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>;
   bias-pull-up;
  };
 };

 uart00_sleep: uart00_sleep {
  group1 {
   psels = <((((((2) * 32U) + (2)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };

 /omit-if-no-ref/ uart30_default: uart30_default {
  group1 {
   psels = <((((((0) * 32U) + (0)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (2)) & 0x1FFU) << 0U) | ((2U & 0xFFU) << 24U))>;
  };
  group2 {
   psels = <((((((0) * 32U) + (1)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (3)) & 0x1FFU) << 0U) | ((3U & 0xFFU) << 24U))>;
   bias-pull-up;
  };
 };

 /omit-if-no-ref/ uart30_sleep: uart30_sleep {
  group1 {
   psels = <((((((0) * 32U) + (0)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (1)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (2)) & 0x1FFU) << 0U) | ((2U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (3)) & 0x1FFU) << 0U) | ((3U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };


 /omit-if-no-ref/ pwm20_default: pwm20_default {
  group1 {
   psels = <((((((1) * 32U) + (10)) & 0x1FFU) << 0U) | ((22U & 0xFFU) << 24U))>;
  };
 };

 /omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
  group1 {
   psels = <((((((1) * 32U) + (10)) & 0x1FFU) << 0U) | ((22U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };

 /omit-if-no-ref/ grtc_default: grtc_default {
  group1 {
   psels = <((((((1) * 32U) + (8)) & 0x1FFU) << 0U) | ((55U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (4)) & 0x1FFU) << 0U) | ((56U & 0xFFU) << 24U))>;
  };
 };

 /omit-if-no-ref/ grtc_sleep: grtc_sleep {
  group1 {
   psels = <((((((1) * 32U) + (8)) & 0x1FFU) << 0U) | ((55U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (4)) & 0x1FFU) << 0U) | ((56U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };

 i2c20_default: i2c20_default {
  group1 {
   psels = <((((((1) * 32U) + (12)) & 0x1FFU) << 0U) | ((11U & 0xFFU) << 24U))>, <((((((1) * 32U) + (13)) & 0x1FFU) << 0U) | ((12U & 0xFFU) << 24U))>;
  };
 };

 i2c20_sleep: i2c20_sleep {
  group1 {
   psels = <((((((1) * 32U) + (12)) & 0x1FFU) << 0U) | ((11U & 0xFFU) << 24U))>, <((((((1) * 32U) + (13)) & 0x1FFU) << 0U) | ((12U & 0xFFU) << 24U))>;
      low-power-enable;
  };
 };

 i2c30_default: i2c30_default {
  group1 {
   psels = <((((((1) * 32U) + (12)) & 0x1FFU) << 0U) | ((11U & 0xFFU) << 24U))>, <((((((0) * 32U) + (2)) & 0x1FFU) << 0U) | ((12U & 0xFFU) << 24U))>;
  };
 };

 i2c30_sleep: i2c30_sleep {
  group1 {
   psels = <((((((1) * 32U) + (12)) & 0x1FFU) << 0U) | ((11U & 0xFFU) << 24U))>, <((((((0) * 32U) + (3)) & 0x1FFU) << 0U) | ((12U & 0xFFU) << 24U))>;
      low-power-enable;
  };
 };


};



&lfxo {
 load-capacitors = "internal";
 load-capacitance-femtofarad = <15500>;
};

&hfxo {
 load-capacitors = "internal";
 load-capacitance-femtofarad = <15000>;
};
# 10 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts" 2
# 1 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi" 1
# 9 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi"
# 1 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi" 1






# 1 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi" 1





&pinctrl {
 /omit-if-no-ref/ uart20_default: uart20_default {
  group1 {
   psels = <((((((1) * 32U) + (4)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>,
    <((((((1) * 32U) + (6)) & 0x1FFU) << 0U) | ((2U & 0xFFU) << 24U))>;
  };
  group2 {
   psels = <((((((1) * 32U) + (5)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>,
    <((((((1) * 32U) + (7)) & 0x1FFU) << 0U) | ((3U & 0xFFU) << 24U))>;
   bias-pull-up;
  };
 };

 /omit-if-no-ref/ uart20_sleep: uart20_sleep {
  group1 {
   psels = <((((((1) * 32U) + (4)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>,
    <((((((1) * 32U) + (5)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>,
    <((((((1) * 32U) + (6)) & 0x1FFU) << 0U) | ((2U & 0xFFU) << 24U))>,
    <((((((1) * 32U) + (7)) & 0x1FFU) << 0U) | ((3U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };

 /omit-if-no-ref/ uart30_default: uart30_default {
  group1 {
   psels = <((((((0) * 32U) + (0)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (2)) & 0x1FFU) << 0U) | ((2U & 0xFFU) << 24U))>;
  };
  group2 {
   psels = <((((((0) * 32U) + (1)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (3)) & 0x1FFU) << 0U) | ((3U & 0xFFU) << 24U))>;
   bias-pull-up;
  };
 };

 /omit-if-no-ref/ uart30_sleep: uart30_sleep {
  group1 {
   psels = <((((((0) * 32U) + (0)) & 0x1FFU) << 0U) | ((0U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (1)) & 0x1FFU) << 0U) | ((1U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (2)) & 0x1FFU) << 0U) | ((2U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (3)) & 0x1FFU) << 0U) | ((3U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };

 /omit-if-no-ref/ spi00_default: spi00_default {
  group1 {
   psels = <((((((2) * 32U) + (1)) & 0x1FFU) << 0U) | ((4U & 0xFFU) << 24U))>,
    <((((((2) * 32U) + (2)) & 0x1FFU) << 0U) | ((5U & 0xFFU) << 24U))>,
    <((((((2) * 32U) + (4)) & 0x1FFU) << 0U) | ((6U & 0xFFU) << 24U))>;
  };
 };

 /omit-if-no-ref/ spi00_sleep: spi00_sleep {
  group1 {
   psels = <((((((2) * 32U) + (1)) & 0x1FFU) << 0U) | ((4U & 0xFFU) << 24U))>,
    <((((((2) * 32U) + (2)) & 0x1FFU) << 0U) | ((5U & 0xFFU) << 24U))>,
    <((((((2) * 32U) + (4)) & 0x1FFU) << 0U) | ((6U & 0xFFU) << 24U))>;
    low-power-enable;
  };
 };

 /omit-if-no-ref/ pwm20_default: pwm20_default {
  group1 {
   psels = <((((((1) * 32U) + (10)) & 0x1FFU) << 0U) | ((22U & 0xFFU) << 24U))>;
  };
 };

 /omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
  group1 {
   psels = <((((((1) * 32U) + (10)) & 0x1FFU) << 0U) | ((22U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };

 /omit-if-no-ref/ grtc_default: grtc_default {
  group1 {
   psels = <((((((1) * 32U) + (8)) & 0x1FFU) << 0U) | ((55U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (4)) & 0x1FFU) << 0U) | ((56U & 0xFFU) << 24U))>;
  };
 };

 /omit-if-no-ref/ grtc_sleep: grtc_sleep {
  group1 {
   psels = <((((((1) * 32U) + (8)) & 0x1FFU) << 0U) | ((55U & 0xFFU) << 24U))>,
    <((((((0) * 32U) + (4)) & 0x1FFU) << 0U) | ((56U & 0xFFU) << 24U))>;
   low-power-enable;
  };
 };
};
# 8 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi" 2

/ {
 leds {
  compatible = "gpio-leds";
  led0: led_0 {
   gpios = <&gpio2 0 (0 << 0)>;
   label = "Green LED 0";
  };
  led1: led_1 {
   gpios = <&gpio1 10 (0 << 0)>;
   label = "Green LED 1";
  };
  led2: led_2 {
   gpios = <&gpio2 7 (0 << 0)>;
   label = "Green LED 2";
  };
  led3: led_3 {
   gpios = <&gpio1 14 (0 << 0)>;
   label = "Green LED 3";
  };
 };

 pwmleds {
  compatible = "pwm-leds";






  pwm_led1: pwm_led_1 {
   pwms = <&pwm20 0 (((20) * 1000UL) * 1000UL) (0 << 0)>;
  };
 };

 buttons {
  compatible = "gpio-keys";
  button0: button_0 {
   gpios = <&gpio1 13 ((1 << 4) | (1 << 0))>;
   label = "Push button 0";
   zephyr,code = <11>;
  };
  button1: button_1 {
   gpios = <&gpio1 9 ((1 << 4) | (1 << 0))>;
   label = "Push button 1";
   zephyr,code = <2>;
  };
  button2: button_2 {
   gpios = <&gpio1 8 ((1 << 4) | (1 << 0))>;
   label = "Push button 2";
   zephyr,code = <3>;
  };
  button3: button_3 {
   gpios = <&gpio0 4 ((1 << 4) | (1 << 0))>;
   label = "Push button 3";
   zephyr,code = <4>;
  };
 };

 aliases {
  led0 = &led0;
  led1 = &led1;
  led2 = &led2;
  led3 = &led3;
  pwm-led0 = &pwm_led1;
  sw0 = &button0;
  sw1 = &button1;
  sw2 = &button2;
  sw3 = &button3;
  watchdog0 = &wdt31;
 };
};

&uart20 {
 current-speed = <115200>;
 pinctrl-0 = <&uart20_default>;
 pinctrl-1 = <&uart20_sleep>;
 pinctrl-names = "default", "sleep";
};

&uart30 {
 current-speed = <115200>;
 pinctrl-0 = <&uart30_default>;
 pinctrl-1 = <&uart30_sleep>;
 pinctrl-names = "default", "sleep";
};

&pwm20 {
 status = "okay";
 pinctrl-0 = <&pwm20_default>;
 pinctrl-1 = <&pwm20_sleep>;
 pinctrl-names = "default", "sleep";
};


wifi_spi: &spi22 {};
# 10 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi" 2

/ {
 chosen {
  zephyr,console = &uart20;
  zephyr,shell-uart = &uart20;
  zephyr,uart-mcumgr = &uart20;
  zephyr,bt-mon-uart = &uart20;
  zephyr,bt-c2h-uart = &uart20;
  zephyr,flash-controller = &rram_controller;
  zephyr,flash = &cpuapp_rram;
  zephyr,ieee802154 = &ieee802154;
 };
};

&cpuapp_sram {
 status = "okay";
};

&lfxo {
 load-capacitors = "internal";
 load-capacitance-femtofarad = <15500>;
};

&hfxo {
 load-capacitors = "internal";
 load-capacitance-femtofarad = <15000>;
};

&regulators {
 status = "okay";
};

&vregmain {
 status = "okay";
 regulator-initial-mode = <1>;
};

&grtc {
 owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;

 child-owned-channels = <3 4 7 8 9 10 11>;
 status = "okay";
};

&uart20 {
 status = "okay";
};

&gpio0 {
 status = "okay";
};

&gpio1 {
 status = "okay";
};

&gpio2 {
 status = "okay";
};

&gpiote20 {
 status = "okay";
};

&gpiote30 {
 status = "okay";
};

&radio {
 status = "okay";
};

&ieee802154 {
 status = "okay";
};

&temp {
 status = "okay";
};

&clock {
 status = "okay";
};

&spi00 {
 status = "okay";
 cs-gpios = <&gpio2 5 (1 << 0)>;
 pinctrl-0 = <&spi00_default>;
 pinctrl-1 = <&spi00_sleep>;
 pinctrl-names = "default", "sleep";

 mx25r64: mx25r6435f@0 {
  compatible = "jedec,spi-nor";
  status = "okay";
  reg = <0>;
  spi-max-frequency = <8000000>;
  jedec-id = [c2 28 17];
  sfdp-bfp = [
   e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
   ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
   10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
   30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
  ];
  size = <67108864>;
  has-dpd;
  t-enter-dpd = <10000>;
  t-exit-dpd = <35000>;
 };
};

&adc {
 status = "okay";
};
# 11 "C:/ncs/v3.0.2/zephyr/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts" 2

/ {
 compatible = "nordic,nrf54l15dk_nrf54l15-cpuapp";
 model = "Nordic nRF54L15 DK nRF54L15 Application MCU";

 chosen {
  zephyr,code-partition = &slot0_partition;
  zephyr,sram = &cpuapp_sram;
 };
};

&cpuapp_rram {
 partitions {
  compatible = "fixed-partitions";
  #address-cells = <1>;
  #size-cells = <1>;
  boot_partition: partition@0 {
   label = "mcuboot";
   reg = <0x0 ((64) * 1024)>;
  };
  slot0_partition: partition@10000 {
   label = "image-0";
   reg = <0x10000 ((324) * 1024)>;
  };
  slot0_ns_partition: partition@61000 {
   label = "image-0-nonsecure";
   reg = <0x61000 ((324) * 1024)>;
  };
  slot1_partition: partition@b2000 {
   label = "image-1";
   reg = <0xb2000 ((324) * 1024)>;
  };
  slot1_ns_partition: partition@103000 {
   label = "image-1-nonsecure";
   reg = <0x103000 ((324) * 1024)>;
  };

  storage_partition: partition@15c000 {
   label = "storage";
   reg = <0x15c000 ((36) * 1024)>;
  };
 };
};
# 0 "<command-line>" 2
# 1 "C:/ncs/v3.0.2/zephyr/misc/empty_file.c"
