/*
 * Copyright (c) 2024 Renesas Electronics Corporation
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_

#define SDRAM_TRAS_1CYCLES (1)
#define SDRAM_TRAS_2CYCLES (2)
#define SDRAM_TRAS_3CYCLES (3)
#define SDRAM_TRAS_4CYCLES (4)
#define SDRAM_TRAS_5CYCLES (5)
#define SDRAM_TRAS_6CYCLES (6)
#define SDRAM_TRAS_7CYCLES (7)

#define SDRAM_TRCD_1CYCLES (1)
#define SDRAM_TRCD_2CYCLES (2)
#define SDRAM_TRCD_3CYCLES (3)
#define SDRAM_TRCD_4CYCLES (4)

#define SDRAM_TRP_1CYCLES (1)
#define SDRAM_TRP_2CYCLES (2)
#define SDRAM_TRP_3CYCLES (3)
#define SDRAM_TRP_4CYCLES (4)
#define SDRAM_TRP_5CYCLES (5)
#define SDRAM_TRP_6CYCLES (6)
#define SDRAM_TRP_7CYCLES (7)
#define SDRAM_TRP_8CYCLES (8)

#define SDRAM_TWR_1CYCLES (1)
#define SDRAM_TWR_2CYCLES (2)

#define SDRAM_TCL_1CYCLES (1)
#define SDRAM_TCL_2CYCLES (2)
#define SDRAM_TCL_3CYCLES (3)

#define SDRAM_TREFW_1CYCLES  (1)
#define SDRAM_TREFW_2CYCLES  (2)
#define SDRAM_TREFW_3CYCLES  (3)
#define SDRAM_TREFW_4CYCLES  (4)
#define SDRAM_TREFW_5CYCLES  (5)
#define SDRAM_TREFW_6CYCLES  (6)
#define SDRAM_TREFW_7CYCLES  (7)
#define SDRAM_TREFW_8CYCLES  (8)
#define SDRAM_TREFW_9CYCLES  (9)
#define SDRAM_TREFW_10CYCLES (10)
#define SDRAM_TREFW_11CYCLES (11)
#define SDRAM_TREFW_12CYCLES (12)
#define SDRAM_TREFW_13CYCLES (13)
#define SDRAM_TREFW_14CYCLES (14)
#define SDRAM_TREFW_15CYCLES (15)
#define SDRAM_TREFW_16CYCLES (16)

#define SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES  (3)
#define SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES  (4)
#define SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES  (5)
#define SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES  (6)
#define SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES  (7)
#define SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES  (8)
#define SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES  (9)
#define SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES (10)
#define SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES (11)
#define SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES (12)
#define SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES (13)
#define SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES (14)
#define SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES (15)
#define SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES (16)
#define SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES (17)
#define SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES (18)
#define SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES (19)
#define SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES (20)

#define SDRAM_AUTO_REFREDSH_COUNT_1TIMES  (1)
#define SDRAM_AUTO_REFREDSH_COUNT_2TIMES  (2)
#define SDRAM_AUTO_REFREDSH_COUNT_3TIMES  (3)
#define SDRAM_AUTO_REFREDSH_COUNT_4TIMES  (4)
#define SDRAM_AUTO_REFREDSH_COUNT_5TIMES  (5)
#define SDRAM_AUTO_REFREDSH_COUNT_6TIMES  (6)
#define SDRAM_AUTO_REFREDSH_COUNT_7TIMES  (7)
#define SDRAM_AUTO_REFREDSH_COUNT_8TIMES  (8)
#define SDRAM_AUTO_REFREDSH_COUNT_9TIMES  (9)
#define SDRAM_AUTO_REFREDSH_COUNT_10TIMES (10)
#define SDRAM_AUTO_REFREDSH_COUNT_11TIMES (11)
#define SDRAM_AUTO_REFREDSH_COUNT_12TIMES (12)
#define SDRAM_AUTO_REFREDSH_COUNT_13TIMES (13)
#define SDRAM_AUTO_REFREDSH_COUNT_14TIMES (14)
#define SDRAM_AUTO_REFREDSH_COUNT_15TIMES (15)

#define SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES  (3)
#define SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES  (4)
#define SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES  (5)
#define SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES  (6)
#define SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES  (7)
#define SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES  (8)
#define SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES  (9)
#define SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES (10)

#endif
