/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * Copyright 2023 NXP
 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_LPADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_LPADC_H_

#define MCUX_LPADC_CH0A (0x0)
#define MCUX_LPADC_CH0B (0x20)
#define MCUX_LPADC_CH1A (0x1)
#define MCUX_LPADC_CH1B (0x21)
#define MCUX_LPADC_CH2A (0x2)
#define MCUX_LPADC_CH2B (0x22)
#define MCUX_LPADC_CH3A (0x3)
#define MCUX_LPADC_CH3B (0x23)
#define MCUX_LPADC_CH4A (0x4)
#define MCUX_LPADC_CH4B (0x24)
#define MCUX_LPADC_CH5A (0x5)
#define MCUX_LPADC_CH5B (0x25)
#define MCUX_LPADC_CH6A (0x6)
#define MCUX_LPADC_CH6B (0x26)
#define MCUX_LPADC_CH7A (0x7)
#define MCUX_LPADC_CH7B (0x27)
#define MCUX_LPADC_CH8A (0x8)
#define MCUX_LPADC_CH8B (0x28)


#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_LPADC_H_ */
