
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	20001870 	.word	0x20001870
}
   4:	00002199 	.word	0x00002199
   8:	0000570f 	.word	0x0000570f
   c:	000021f9 	.word	0x000021f9
  10:	000021f9 	.word	0x000021f9
  14:	000021f9 	.word	0x000021f9
  18:	000021f9 	.word	0x000021f9
  1c:	000021f9 	.word	0x000021f9
	...
  2c:	00001fad 	.word	0x00001fad
  30:	000021f9 	.word	0x000021f9
  34:	00000000 	.word	0x00000000
  38:	00001f55 	.word	0x00001f55
  3c:	000055f5 	.word	0x000055f5

00000040 <_irq_vector_table>:
  40:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  50:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  60:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  70:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  80:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  90:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  a0:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  b0:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  c0:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  d0:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  e0:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
  f0:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
 100:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
 110:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
 120:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
 130:	00002159 00002159 00002159 00002159     Y!..Y!..Y!..Y!..
 140:	00002159                                Y!..

00000144 <_vector_end>:
	...

00000200 <m_firmware_info>:
 200:	281ee6de 8fcebb4c 00005b02 0000003c     ...(L....[..<...
 210:	00008000 00000001 00000000 00000000     ................
 220:	9102ffff 00000000 00000000 00000000     ................
	...

Disassembly of section text:

0000023c <__aeabi_uldivmod>:
     23c:	b953      	cbnz	r3, 254 <__aeabi_uldivmod+0x18>
     23e:	b94a      	cbnz	r2, 254 <__aeabi_uldivmod+0x18>
     240:	2900      	cmp	r1, #0
     242:	bf08      	it	eq
     244:	2800      	cmpeq	r0, #0
     246:	bf1c      	itt	ne
     248:	f04f 31ff 	movne.w	r1, #4294967295
     24c:	f04f 30ff 	movne.w	r0, #4294967295
     250:	f000 b96c 	b.w	52c <__aeabi_idiv0>
     254:	f1ad 0c08 	sub.w	ip, sp, #8
     258:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     25c:	f000 f806 	bl	26c <__udivmoddi4>
     260:	f8dd e004 	ldr.w	lr, [sp, #4]
     264:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     268:	b004      	add	sp, #16
     26a:	4770      	bx	lr

0000026c <__udivmoddi4>:
     26c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     270:	9d08      	ldr	r5, [sp, #32]
     272:	4604      	mov	r4, r0
     274:	4688      	mov	r8, r1
     276:	2b00      	cmp	r3, #0
     278:	d17d      	bne.n	376 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xf6>
     27a:	428a      	cmp	r2, r1
     27c:	4617      	mov	r7, r2
     27e:	d93f      	bls.n	300 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x80>
     280:	fab2 f282 	clz	r2, r2
     284:	b142      	cbz	r2, 298 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x18>
     286:	f1c2 0020 	rsb	r0, r2, #32
     28a:	4091      	lsls	r1, r2
     28c:	4097      	lsls	r7, r2
     28e:	fa24 f000 	lsr.w	r0, r4, r0
     292:	4094      	lsls	r4, r2
     294:	ea40 0801 	orr.w	r8, r0, r1
     298:	ea4f 4c17 	mov.w	ip, r7, lsr #16
     29c:	0c23      	lsrs	r3, r4, #16
     29e:	fa1f fe87 	uxth.w	lr, r7
     2a2:	fbb8 f6fc 	udiv	r6, r8, ip
     2a6:	fb0c 8116 	mls	r1, ip, r6, r8
     2aa:	fb06 f00e 	mul.w	r0, r6, lr
     2ae:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
     2b2:	4298      	cmp	r0, r3
     2b4:	d905      	bls.n	2c2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x42>
     2b6:	18fb      	adds	r3, r7, r3
     2b8:	d202      	bcs.n	2c0 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x40>
     2ba:	4298      	cmp	r0, r3
     2bc:	f200 8124 	bhi.w	508 <CONFIG_FLASH_SIZE+0x108>
     2c0:	3e01      	subs	r6, #1
     2c2:	1a19      	subs	r1, r3, r0
     2c4:	b2a3      	uxth	r3, r4
     2c6:	fbb1 f0fc 	udiv	r0, r1, ip
     2ca:	fb0c 1110 	mls	r1, ip, r0, r1
     2ce:	fb00 fe0e 	mul.w	lr, r0, lr
     2d2:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
     2d6:	45a6      	cmp	lr, r4
     2d8:	d905      	bls.n	2e6 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x66>
     2da:	193c      	adds	r4, r7, r4
     2dc:	d202      	bcs.n	2e4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x64>
     2de:	45a6      	cmp	lr, r4
     2e0:	f200 810f 	bhi.w	502 <CONFIG_FLASH_SIZE+0x102>
     2e4:	3801      	subs	r0, #1
     2e6:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
     2ea:	eba4 040e 	sub.w	r4, r4, lr
     2ee:	2600      	movs	r6, #0
     2f0:	b11d      	cbz	r5, 2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     2f2:	40d4      	lsrs	r4, r2
     2f4:	2300      	movs	r3, #0
     2f6:	e9c5 4300 	strd	r4, r3, [r5]
     2fa:	4631      	mov	r1, r6
     2fc:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     300:	b902      	cbnz	r2, 304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     302:	deff      	udf	#255	; 0xff
     304:	fab2 f282 	clz	r2, r2
     308:	2a00      	cmp	r2, #0
     30a:	d150      	bne.n	3ae <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12e>
     30c:	1bcb      	subs	r3, r1, r7
     30e:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     312:	fa1f f887 	uxth.w	r8, r7
     316:	2601      	movs	r6, #1
     318:	0c21      	lsrs	r1, r4, #16
     31a:	fbb3 fcfe 	udiv	ip, r3, lr
     31e:	fb0e 301c 	mls	r0, lr, ip, r3
     322:	460b      	mov	r3, r1
     324:	fb08 f90c 	mul.w	r9, r8, ip
     328:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     32c:	4589      	cmp	r9, r1
     32e:	d90a      	bls.n	346 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc6>
     330:	1879      	adds	r1, r7, r1
     332:	bf2c      	ite	cs
     334:	2301      	movcs	r3, #1
     336:	2300      	movcc	r3, #0
     338:	4589      	cmp	r9, r1
     33a:	d902      	bls.n	342 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc2>
     33c:	2b00      	cmp	r3, #0
     33e:	f000 80d9 	beq.w	4f4 <CONFIG_FLASH_SIZE+0xf4>
     342:	f10c 3cff 	add.w	ip, ip, #4294967295
     346:	eba1 0109 	sub.w	r1, r1, r9
     34a:	b2a3      	uxth	r3, r4
     34c:	fbb1 f0fe 	udiv	r0, r1, lr
     350:	fb0e 1110 	mls	r1, lr, r0, r1
     354:	fb08 f800 	mul.w	r8, r8, r0
     358:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
     35c:	45a0      	cmp	r8, r4
     35e:	d905      	bls.n	36c <CONFIG_PM_PARTITION_SIZE_PROVISION+0xec>
     360:	193c      	adds	r4, r7, r4
     362:	d202      	bcs.n	36a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xea>
     364:	45a0      	cmp	r8, r4
     366:	f200 80c9 	bhi.w	4fc <CONFIG_FLASH_SIZE+0xfc>
     36a:	3801      	subs	r0, #1
     36c:	eba4 0408 	sub.w	r4, r4, r8
     370:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     374:	e7bc      	b.n	2f0 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x70>
     376:	428b      	cmp	r3, r1
     378:	d909      	bls.n	38e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x10e>
     37a:	2d00      	cmp	r5, #0
     37c:	f000 80b1 	beq.w	4e2 <CONFIG_FLASH_SIZE+0xe2>
     380:	2600      	movs	r6, #0
     382:	e9c5 0100 	strd	r0, r1, [r5]
     386:	4630      	mov	r0, r6
     388:	4631      	mov	r1, r6
     38a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     38e:	fab3 f683 	clz	r6, r3
     392:	2e00      	cmp	r6, #0
     394:	d146      	bne.n	424 <CONFIG_FLASH_SIZE+0x24>
     396:	428b      	cmp	r3, r1
     398:	f0c0 80a6 	bcc.w	4e8 <CONFIG_FLASH_SIZE+0xe8>
     39c:	4282      	cmp	r2, r0
     39e:	f240 80a3 	bls.w	4e8 <CONFIG_FLASH_SIZE+0xe8>
     3a2:	4630      	mov	r0, r6
     3a4:	2d00      	cmp	r5, #0
     3a6:	d0a8      	beq.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     3a8:	e9c5 4800 	strd	r4, r8, [r5]
     3ac:	e7a5      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     3ae:	4097      	lsls	r7, r2
     3b0:	f1c2 0320 	rsb	r3, r2, #32
     3b4:	fa01 f002 	lsl.w	r0, r1, r2
     3b8:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     3bc:	40d9      	lsrs	r1, r3
     3be:	fa24 f303 	lsr.w	r3, r4, r3
     3c2:	fa1f f887 	uxth.w	r8, r7
     3c6:	4094      	lsls	r4, r2
     3c8:	4303      	orrs	r3, r0
     3ca:	fbb1 f0fe 	udiv	r0, r1, lr
     3ce:	0c1e      	lsrs	r6, r3, #16
     3d0:	fb0e 1110 	mls	r1, lr, r0, r1
     3d4:	fb00 fc08 	mul.w	ip, r0, r8
     3d8:	ea46 4101 	orr.w	r1, r6, r1, lsl #16
     3dc:	458c      	cmp	ip, r1
     3de:	d909      	bls.n	3f4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x174>
     3e0:	1879      	adds	r1, r7, r1
     3e2:	bf2c      	ite	cs
     3e4:	2601      	movcs	r6, #1
     3e6:	2600      	movcc	r6, #0
     3e8:	458c      	cmp	ip, r1
     3ea:	d902      	bls.n	3f2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x172>
     3ec:	2e00      	cmp	r6, #0
     3ee:	f000 8093 	beq.w	518 <CONFIG_FLASH_SIZE+0x118>
     3f2:	3801      	subs	r0, #1
     3f4:	eba1 010c 	sub.w	r1, r1, ip
     3f8:	b29b      	uxth	r3, r3
     3fa:	fbb1 f6fe 	udiv	r6, r1, lr
     3fe:	fb0e 1116 	mls	r1, lr, r6, r1
     402:	fb06 fc08 	mul.w	ip, r6, r8
     406:	ea43 4101 	orr.w	r1, r3, r1, lsl #16
     40a:	458c      	cmp	ip, r1
     40c:	d905      	bls.n	41a <CONFIG_FLASH_SIZE+0x1a>
     40e:	1879      	adds	r1, r7, r1
     410:	d202      	bcs.n	418 <CONFIG_FLASH_SIZE+0x18>
     412:	458c      	cmp	ip, r1
     414:	f200 8087 	bhi.w	526 <CONFIG_FLASH_SIZE+0x126>
     418:	3e01      	subs	r6, #1
     41a:	eba1 030c 	sub.w	r3, r1, ip
     41e:	ea46 4600 	orr.w	r6, r6, r0, lsl #16
     422:	e779      	b.n	318 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x98>
     424:	f1c6 0720 	rsb	r7, r6, #32
     428:	fa03 f406 	lsl.w	r4, r3, r6
     42c:	fa02 fc06 	lsl.w	ip, r2, r6
     430:	fa01 fe06 	lsl.w	lr, r1, r6
     434:	40fa      	lsrs	r2, r7
     436:	fa20 f807 	lsr.w	r8, r0, r7
     43a:	40f9      	lsrs	r1, r7
     43c:	fa00 f306 	lsl.w	r3, r0, r6
     440:	4322      	orrs	r2, r4
     442:	ea48 040e 	orr.w	r4, r8, lr
     446:	ea4f 4812 	mov.w	r8, r2, lsr #16
     44a:	ea4f 4e14 	mov.w	lr, r4, lsr #16
     44e:	fa1f f982 	uxth.w	r9, r2
     452:	fbb1 faf8 	udiv	sl, r1, r8
     456:	fb08 111a 	mls	r1, r8, sl, r1
     45a:	fb0a f009 	mul.w	r0, sl, r9
     45e:	ea4e 4e01 	orr.w	lr, lr, r1, lsl #16
     462:	4570      	cmp	r0, lr
     464:	d90a      	bls.n	47c <CONFIG_FLASH_SIZE+0x7c>
     466:	eb12 0e0e 	adds.w	lr, r2, lr
     46a:	bf2c      	ite	cs
     46c:	2101      	movcs	r1, #1
     46e:	2100      	movcc	r1, #0
     470:	4570      	cmp	r0, lr
     472:	d901      	bls.n	478 <CONFIG_FLASH_SIZE+0x78>
     474:	2900      	cmp	r1, #0
     476:	d052      	beq.n	51e <CONFIG_FLASH_SIZE+0x11e>
     478:	f10a 3aff 	add.w	sl, sl, #4294967295
     47c:	ebae 0e00 	sub.w	lr, lr, r0
     480:	b2a4      	uxth	r4, r4
     482:	fbbe f0f8 	udiv	r0, lr, r8
     486:	fb08 ee10 	mls	lr, r8, r0, lr
     48a:	fb00 f909 	mul.w	r9, r0, r9
     48e:	ea44 4e0e 	orr.w	lr, r4, lr, lsl #16
     492:	45f1      	cmp	r9, lr
     494:	d905      	bls.n	4a2 <CONFIG_FLASH_SIZE+0xa2>
     496:	eb12 0e0e 	adds.w	lr, r2, lr
     49a:	d201      	bcs.n	4a0 <CONFIG_FLASH_SIZE+0xa0>
     49c:	45f1      	cmp	r9, lr
     49e:	d838      	bhi.n	512 <CONFIG_FLASH_SIZE+0x112>
     4a0:	3801      	subs	r0, #1
     4a2:	ea40 400a 	orr.w	r0, r0, sl, lsl #16
     4a6:	ebae 0e09 	sub.w	lr, lr, r9
     4aa:	fba0 890c 	umull	r8, r9, r0, ip
     4ae:	45ce      	cmp	lr, r9
     4b0:	4641      	mov	r1, r8
     4b2:	464c      	mov	r4, r9
     4b4:	d302      	bcc.n	4bc <CONFIG_FLASH_SIZE+0xbc>
     4b6:	d106      	bne.n	4c6 <CONFIG_FLASH_SIZE+0xc6>
     4b8:	4543      	cmp	r3, r8
     4ba:	d204      	bcs.n	4c6 <CONFIG_FLASH_SIZE+0xc6>
     4bc:	3801      	subs	r0, #1
     4be:	ebb8 010c 	subs.w	r1, r8, ip
     4c2:	eb69 0402 	sbc.w	r4, r9, r2
     4c6:	b315      	cbz	r5, 50e <CONFIG_FLASH_SIZE+0x10e>
     4c8:	1a5a      	subs	r2, r3, r1
     4ca:	eb6e 0e04 	sbc.w	lr, lr, r4
     4ce:	40f2      	lsrs	r2, r6
     4d0:	fa0e f707 	lsl.w	r7, lr, r7
     4d4:	fa2e f306 	lsr.w	r3, lr, r6
     4d8:	2600      	movs	r6, #0
     4da:	4317      	orrs	r7, r2
     4dc:	e9c5 7300 	strd	r7, r3, [r5]
     4e0:	e70b      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     4e2:	462e      	mov	r6, r5
     4e4:	4628      	mov	r0, r5
     4e6:	e708      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     4e8:	1a84      	subs	r4, r0, r2
     4ea:	eb61 0103 	sbc.w	r1, r1, r3
     4ee:	2001      	movs	r0, #1
     4f0:	4688      	mov	r8, r1
     4f2:	e757      	b.n	3a4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x124>
     4f4:	f1ac 0c02 	sub.w	ip, ip, #2
     4f8:	4439      	add	r1, r7
     4fa:	e724      	b.n	346 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc6>
     4fc:	3802      	subs	r0, #2
     4fe:	443c      	add	r4, r7
     500:	e734      	b.n	36c <CONFIG_PM_PARTITION_SIZE_PROVISION+0xec>
     502:	3802      	subs	r0, #2
     504:	443c      	add	r4, r7
     506:	e6ee      	b.n	2e6 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x66>
     508:	3e02      	subs	r6, #2
     50a:	443b      	add	r3, r7
     50c:	e6d9      	b.n	2c2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x42>
     50e:	462e      	mov	r6, r5
     510:	e6f3      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     512:	3802      	subs	r0, #2
     514:	4496      	add	lr, r2
     516:	e7c4      	b.n	4a2 <CONFIG_FLASH_SIZE+0xa2>
     518:	3802      	subs	r0, #2
     51a:	4439      	add	r1, r7
     51c:	e76a      	b.n	3f4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x174>
     51e:	f1aa 0a02 	sub.w	sl, sl, #2
     522:	4496      	add	lr, r2
     524:	e7aa      	b.n	47c <CONFIG_FLASH_SIZE+0x7c>
     526:	3e02      	subs	r6, #2
     528:	4439      	add	r1, r7
     52a:	e776      	b.n	41a <CONFIG_FLASH_SIZE+0x1a>

0000052c <__aeabi_idiv0>:
     52c:	4770      	bx	lr
     52e:	bf00      	nop

00000530 <__gnu_cmse_nonsecure_call>:
     530:	e92d 4fe0 	stmdb	sp!, {r5, r6, r7, r8, r9, sl, fp, lr}
     534:	4627      	mov	r7, r4
     536:	46a0      	mov	r8, r4
     538:	46a1      	mov	r9, r4
     53a:	46a2      	mov	sl, r4
     53c:	46a3      	mov	fp, r4
     53e:	46a4      	mov	ip, r4
     540:	ed2d 8b10 	vpush	{d8-d15}
     544:	f04f 0500 	mov.w	r5, #0
     548:	ec45 5b18 	vmov	d8, r5, r5
     54c:	ec45 5a19 	vmov	s18, s19, r5, r5
     550:	ec45 5a1a 	vmov	s20, s21, r5, r5
     554:	ec45 5a1b 	vmov	s22, s23, r5, r5
     558:	ec45 5a1c 	vmov	s24, s25, r5, r5
     55c:	ec45 5a1d 	vmov	s26, s27, r5, r5
     560:	ec45 5a1e 	vmov	s28, s29, r5, r5
     564:	ec45 5a1f 	vmov	s30, s31, r5, r5
     568:	eef1 5a10 	vmrs	r5, fpscr
     56c:	f64f 7660 	movw	r6, #65376	; 0xff60
     570:	f6c0 76ff 	movt	r6, #4095	; 0xfff
     574:	4035      	ands	r5, r6
     576:	eee1 5a10 	vmsr	fpscr, r5
     57a:	f384 8800 	msr	CPSR_f, r4
     57e:	4625      	mov	r5, r4
     580:	4626      	mov	r6, r4
     582:	47a4      	blxns	r4
     584:	ecbd 8b10 	vpop	{d8-d15}
     588:	e8bd 8fe0 	ldmia.w	sp!, {r5, r6, r7, r8, r9, sl, fp, pc}

0000058c <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     58c:	680b      	ldr	r3, [r1, #0]
     58e:	3301      	adds	r3, #1
     590:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     592:	4b01      	ldr	r3, [pc, #4]	; (598 <char_out+0xc>)
     594:	681b      	ldr	r3, [r3, #0]
     596:	4718      	bx	r3
     598:	20000000 	.word	0x20000000

0000059c <__printk_hook_install>:
	_char_out = fn;
     59c:	4b01      	ldr	r3, [pc, #4]	; (5a4 <__printk_hook_install+0x8>)
     59e:	6018      	str	r0, [r3, #0]
}
     5a0:	4770      	bx	lr
     5a2:	bf00      	nop
     5a4:	20000000 	.word	0x20000000

000005a8 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     5a8:	b507      	push	{r0, r1, r2, lr}
     5aa:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     5ac:	2100      	movs	r1, #0
{
     5ae:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
     5b0:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     5b2:	4803      	ldr	r0, [pc, #12]	; (5c0 <vprintk+0x18>)
     5b4:	a901      	add	r1, sp, #4
     5b6:	f000 fa65 	bl	a84 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     5ba:	b003      	add	sp, #12
     5bc:	f85d fb04 	ldr.w	pc, [sp], #4
     5c0:	0000058d 	.word	0x0000058d

000005c4 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     5c4:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5c8:	f8b0 9018 	ldrh.w	r9, [r0, #24]
{
     5cc:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     5ce:	f019 0808 	ands.w	r8, r9, #8
{
     5d2:	4693      	mov	fp, r2
	if (processing) {
     5d4:	d00e      	beq.n	5f4 <process_event+0x30>
		if (evt == EVT_COMPLETE) {
     5d6:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     5d8:	bf0c      	ite	eq
     5da:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     5de:	f049 0920 	orrne.w	r9, r9, #32
     5e2:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     5e6:	f38b 8811 	msr	BASEPRI, fp
     5ea:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     5ee:	b003      	add	sp, #12
     5f0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				transit(mgr, transition_complete);
     5f4:	f8df a198 	ldr.w	sl, [pc, #408]	; 790 <process_event+0x1cc>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5f8:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     5fc:	2902      	cmp	r1, #2
     5fe:	d107      	bne.n	610 <process_event+0x4c>
			evt = process_recheck(mgr);
     600:	4620      	mov	r0, r4
     602:	f004 fd20 	bl	5046 <process_recheck>
		if (evt == EVT_NOP) {
     606:	2800      	cmp	r0, #0
     608:	d0ed      	beq.n	5e6 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     60a:	2801      	cmp	r0, #1
     60c:	8b23      	ldrh	r3, [r4, #24]
     60e:	d14d      	bne.n	6ac <process_event+0xe8>
			res = mgr->last_res;
     610:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     612:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     614:	2f00      	cmp	r7, #0
     616:	da15      	bge.n	644 <process_event+0x80>
		*clients = mgr->clients;
     618:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     61a:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     61e:	e9c4 8800 	strd	r8, r8, [r4]
     622:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     626:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
     628:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     62a:	8b21      	ldrh	r1, [r4, #24]
     62c:	f001 0207 	and.w	r2, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     630:	454a      	cmp	r2, r9
     632:	d002      	beq.n	63a <process_event+0x76>
		if (do_monitors
     634:	68a3      	ldr	r3, [r4, #8]
     636:	2b00      	cmp	r3, #0
     638:	d159      	bne.n	6ee <process_event+0x12a>
		    || !sys_slist_is_empty(&clients)
     63a:	b90d      	cbnz	r5, 640 <process_event+0x7c>
		    || (transit != NULL)) {
     63c:	2e00      	cmp	r6, #0
     63e:	d071      	beq.n	724 <process_event+0x160>
     640:	2300      	movs	r3, #0
     642:	e055      	b.n	6f0 <process_event+0x12c>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     644:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     648:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     64a:	2a01      	cmp	r2, #1
     64c:	d81f      	bhi.n	68e <process_event+0xca>
		*clients = mgr->clients;
     64e:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     652:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     654:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
     656:	b289      	uxth	r1, r1
	list->tail = NULL;
     658:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     65c:	d10c      	bne.n	678 <process_event+0xb4>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     65e:	2d00      	cmp	r5, #0
     660:	462b      	mov	r3, r5
     662:	bf38      	it	cc
     664:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     666:	b12b      	cbz	r3, 674 <process_event+0xb0>
				mgr->refs += 1U;
     668:	8b62      	ldrh	r2, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     66a:	681b      	ldr	r3, [r3, #0]
     66c:	3201      	adds	r2, #1
     66e:	8362      	strh	r2, [r4, #26]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     670:	2b00      	cmp	r3, #0
     672:	d1f8      	bne.n	666 <process_event+0xa2>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     674:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
     678:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     67a:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     67c:	f004 fce3 	bl	5046 <process_recheck>
     680:	2800      	cmp	r0, #0
     682:	d0d1      	beq.n	628 <process_event+0x64>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     684:	8b23      	ldrh	r3, [r4, #24]
     686:	f043 0320 	orr.w	r3, r3, #32
     68a:	8323      	strh	r3, [r4, #24]
     68c:	e7cc      	b.n	628 <process_event+0x64>
	} else if (state == ONOFF_STATE_TO_OFF) {
     68e:	2b04      	cmp	r3, #4
     690:	d10a      	bne.n	6a8 <process_event+0xe4>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     692:	f021 0107 	bic.w	r1, r1, #7
     696:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
     698:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     69a:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     69c:	f004 fcd3 	bl	5046 <process_recheck>
     6a0:	b110      	cbz	r0, 6a8 <process_event+0xe4>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     6a2:	f041 0120 	orr.w	r1, r1, #32
     6a6:	8321      	strh	r1, [r4, #24]
     6a8:	2500      	movs	r5, #0
     6aa:	e7bd      	b.n	628 <process_event+0x64>
		} else if (evt == EVT_START) {
     6ac:	2803      	cmp	r0, #3
     6ae:	d109      	bne.n	6c4 <process_event+0x100>
			transit = mgr->transitions->start;
     6b0:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6b2:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     6b6:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6b8:	f043 0306 	orr.w	r3, r3, #6
}
     6bc:	2500      	movs	r5, #0
	mgr->flags = (state & ONOFF_STATE_MASK)
     6be:	8323      	strh	r3, [r4, #24]
		res = 0;
     6c0:	462f      	mov	r7, r5
     6c2:	e7b2      	b.n	62a <process_event+0x66>
		} else if (evt == EVT_STOP) {
     6c4:	2804      	cmp	r0, #4
     6c6:	d106      	bne.n	6d6 <process_event+0x112>
			transit = mgr->transitions->stop;
     6c8:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6ca:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     6ce:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6d0:	f043 0304 	orr.w	r3, r3, #4
     6d4:	e7f2      	b.n	6bc <process_event+0xf8>
		} else if (evt == EVT_RESET) {
     6d6:	2805      	cmp	r0, #5
     6d8:	d106      	bne.n	6e8 <process_event+0x124>
			transit = mgr->transitions->reset;
     6da:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6dc:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     6e0:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6e2:	f043 0305 	orr.w	r3, r3, #5
     6e6:	e7e9      	b.n	6bc <process_event+0xf8>
     6e8:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     6ea:	462e      	mov	r6, r5
     6ec:	e7e8      	b.n	6c0 <process_event+0xfc>
				   && !sys_slist_is_empty(&mgr->monitors);
     6ee:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     6f0:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     6f4:	8321      	strh	r1, [r4, #24]
     6f6:	f38b 8811 	msr	BASEPRI, fp
     6fa:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     6fe:	bb03      	cbnz	r3, 742 <process_event+0x17e>
	while (!sys_slist_is_empty(list)) {
     700:	2d00      	cmp	r5, #0
     702:	d134      	bne.n	76e <process_event+0x1aa>
			if (transit != NULL) {
     704:	b116      	cbz	r6, 70c <process_event+0x148>
				transit(mgr, transition_complete);
     706:	4651      	mov	r1, sl
     708:	4620      	mov	r0, r4
     70a:	47b0      	blx	r6
	__asm__ volatile(
     70c:	f04f 0320 	mov.w	r3, #32
     710:	f3ef 8b11 	mrs	fp, BASEPRI
     714:	f383 8811 	msr	BASEPRI, r3
     718:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     71c:	8b23      	ldrh	r3, [r4, #24]
     71e:	f023 0308 	bic.w	r3, r3, #8
     722:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     724:	8b23      	ldrh	r3, [r4, #24]
     726:	06da      	lsls	r2, r3, #27
     728:	d52a      	bpl.n	780 <process_event+0x1bc>
			evt = EVT_COMPLETE;
     72a:	2101      	movs	r1, #1
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     72c:	f023 0310 	bic.w	r3, r3, #16
     730:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     732:	f8b4 9018 	ldrh.w	r9, [r4, #24]
     736:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     73a:	2900      	cmp	r1, #0
     73c:	f47f af5e 	bne.w	5fc <process_event+0x38>
out:
     740:	e751      	b.n	5e6 <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     742:	68a1      	ldr	r1, [r4, #8]
     744:	2900      	cmp	r1, #0
     746:	d0db      	beq.n	700 <process_event+0x13c>
	return node->next;
     748:	680b      	ldr	r3, [r1, #0]
     74a:	2b00      	cmp	r3, #0
     74c:	bf38      	it	cc
     74e:	2300      	movcc	r3, #0
     750:	4699      	mov	r9, r3
		mon->callback(mgr, mon, state, res);
     752:	4620      	mov	r0, r4
     754:	463b      	mov	r3, r7
     756:	f8d1 b004 	ldr.w	fp, [r1, #4]
     75a:	9201      	str	r2, [sp, #4]
     75c:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     75e:	9a01      	ldr	r2, [sp, #4]
     760:	f1b9 0f00 	cmp.w	r9, #0
     764:	d0cc      	beq.n	700 <process_event+0x13c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     766:	4649      	mov	r1, r9
     768:	f8d9 3000 	ldr.w	r3, [r9]
     76c:	e7ed      	b.n	74a <process_event+0x186>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
     76e:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     770:	463b      	mov	r3, r7
     772:	4620      	mov	r0, r4
     774:	9201      	str	r2, [sp, #4]
     776:	682d      	ldr	r5, [r5, #0]
     778:	f004 fc81 	bl	507e <notify_one>
	while (!sys_slist_is_empty(list)) {
     77c:	9a01      	ldr	r2, [sp, #4]
     77e:	e7bf      	b.n	700 <process_event+0x13c>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     780:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     784:	bf1e      	ittt	ne
     786:	f023 0320 	bicne.w	r3, r3, #32
			evt = EVT_RECHECK;
     78a:	2102      	movne	r1, #2
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     78c:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
     78e:	e7d0      	b.n	732 <process_event+0x16e>
     790:	000050ab 	.word	0x000050ab

00000794 <extract_conversion>:
 * @return pointer to the first character that follows the specification.
 */
static inline const char *extract_conversion(struct conversion *conv,
					     const char *sp)
{
	*conv = (struct conversion) {
     794:	2200      	movs	r2, #0
{
     796:	b5f0      	push	{r4, r5, r6, r7, lr}
	*conv = (struct conversion) {
     798:	e9c0 2200 	strd	r2, r2, [r0]
     79c:	6082      	str	r2, [r0, #8]
	/* Skip over the opening %.  If the conversion specifier is %,
	 * that's the only thing that should be there, so
	 * fast-exit.
	 */
	++sp;
	if (*sp == '%') {
     79e:	784a      	ldrb	r2, [r1, #1]
{
     7a0:	4603      	mov	r3, r0
	if (*sp == '%') {
     7a2:	2a25      	cmp	r2, #37	; 0x25
     7a4:	d033      	beq.n	80e <CONFIG_ISR_STACK_SIZE+0xe>
	++sp;
     7a6:	3101      	adds	r1, #1
     7a8:	4608      	mov	r0, r1
		switch (*sp) {
     7aa:	f811 2b01 	ldrb.w	r2, [r1], #1
     7ae:	2a2b      	cmp	r2, #43	; 0x2b
     7b0:	d03d      	beq.n	82e <CONFIG_ISR_STACK_SIZE+0x2e>
     7b2:	d82f      	bhi.n	814 <CONFIG_ISR_STACK_SIZE+0x14>
     7b4:	2a20      	cmp	r2, #32
     7b6:	d03e      	beq.n	836 <CONFIG_ISR_STACK_SIZE+0x36>
     7b8:	2a23      	cmp	r2, #35	; 0x23
     7ba:	d040      	beq.n	83e <CONFIG_ISR_STACK_SIZE+0x3e>
	if (conv->flag_zero && conv->flag_dash) {
     7bc:	781a      	ldrb	r2, [r3, #0]
     7be:	f002 0144 	and.w	r1, r2, #68	; 0x44
     7c2:	2944      	cmp	r1, #68	; 0x44
     7c4:	d102      	bne.n	7cc <extract_conversion+0x38>
		conv->flag_zero = false;
     7c6:	f36f 1286 	bfc	r2, #6, #1
     7ca:	701a      	strb	r2, [r3, #0]
	if (*sp == '*') {
     7cc:	7802      	ldrb	r2, [r0, #0]
     7ce:	2a2a      	cmp	r2, #42	; 0x2a
     7d0:	d14c      	bne.n	86c <CONFIG_ISR_STACK_SIZE+0x6c>
		conv->width_present = true;
     7d2:	8819      	ldrh	r1, [r3, #0]
     7d4:	1c42      	adds	r2, r0, #1
     7d6:	f441 71c0 	orr.w	r1, r1, #384	; 0x180
     7da:	8019      	strh	r1, [r3, #0]
	if (*sp != '.') {
     7dc:	7811      	ldrb	r1, [r2, #0]
     7de:	292e      	cmp	r1, #46	; 0x2e
     7e0:	d14f      	bne.n	882 <CONFIG_ISR_STACK_SIZE+0x82>
	if (*sp == '*') {
     7e2:	7851      	ldrb	r1, [r2, #1]
     7e4:	292a      	cmp	r1, #42	; 0x2a
     7e6:	d045      	beq.n	874 <CONFIG_ISR_STACK_SIZE+0x74>
     7e8:	3201      	adds	r2, #1
	const char *sp = *str;
     7ea:	4615      	mov	r5, r2
	size_t val = 0;
     7ec:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
     7ee:	270a      	movs	r7, #10
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     7f0:	4610      	mov	r0, r2
     7f2:	f810 4b01 	ldrb.w	r4, [r0], #1
     7f6:	f1a4 0630 	sub.w	r6, r4, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     7fa:	2e09      	cmp	r6, #9
     7fc:	d953      	bls.n	8a6 <CONFIG_ISR_STACK_SIZE+0xa6>
	if (sp != wp) {
     7fe:	42aa      	cmp	r2, r5
		conv->prec_present = true;
     800:	bf1f      	itttt	ne
     802:	7858      	ldrbne	r0, [r3, #1]
		conv->prec_value = prec;
     804:	6099      	strne	r1, [r3, #8]
		conv->prec_present = true;
     806:	f040 0002 	orrne.w	r0, r0, #2
     80a:	7058      	strbne	r0, [r3, #1]
		if (prec != conv->prec_value) {
     80c:	e039      	b.n	882 <CONFIG_ISR_STACK_SIZE+0x82>
		conv->specifier = *sp++;
     80e:	1c88      	adds	r0, r1, #2
     810:	70da      	strb	r2, [r3, #3]
	sp = extract_prec(conv, sp);
	sp = extract_length(conv, sp);
	sp = extract_specifier(conv, sp);

	return sp;
}
     812:	bdf0      	pop	{r4, r5, r6, r7, pc}
		switch (*sp) {
     814:	2a2d      	cmp	r2, #45	; 0x2d
     816:	d005      	beq.n	824 <CONFIG_ISR_STACK_SIZE+0x24>
     818:	2a30      	cmp	r2, #48	; 0x30
     81a:	d1cf      	bne.n	7bc <extract_conversion+0x28>
			conv->flag_zero = true;
     81c:	781a      	ldrb	r2, [r3, #0]
     81e:	f042 0240 	orr.w	r2, r2, #64	; 0x40
     822:	e002      	b.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
			conv->flag_dash = true;
     824:	781a      	ldrb	r2, [r3, #0]
     826:	f042 0204 	orr.w	r2, r2, #4
			conv->flag_zero = true;
     82a:	701a      	strb	r2, [r3, #0]
			break;
     82c:	e7bc      	b.n	7a8 <extract_conversion+0x14>
			conv->flag_plus = true;
     82e:	781a      	ldrb	r2, [r3, #0]
     830:	f042 0208 	orr.w	r2, r2, #8
     834:	e7f9      	b.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
			conv->flag_space = true;
     836:	781a      	ldrb	r2, [r3, #0]
     838:	f042 0210 	orr.w	r2, r2, #16
     83c:	e7f5      	b.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
			conv->flag_hash = true;
     83e:	781a      	ldrb	r2, [r3, #0]
     840:	f042 0220 	orr.w	r2, r2, #32
     844:	e7f1      	b.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
		val = 10U * val + *sp++ - '0';
     846:	4622      	mov	r2, r4
     848:	fb07 5101 	mla	r1, r7, r1, r5
     84c:	3930      	subs	r1, #48	; 0x30
     84e:	4614      	mov	r4, r2
     850:	f814 5b01 	ldrb.w	r5, [r4], #1
     854:	f1a5 0630 	sub.w	r6, r5, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     858:	2e09      	cmp	r6, #9
     85a:	d9f4      	bls.n	846 <CONFIG_ISR_STACK_SIZE+0x46>
	if (sp != wp) {
     85c:	4290      	cmp	r0, r2
		conv->width_present = true;
     85e:	bf1f      	itttt	ne
     860:	7818      	ldrbne	r0, [r3, #0]
		conv->width_value = width;
     862:	6059      	strne	r1, [r3, #4]
		conv->width_present = true;
     864:	f040 0080 	orrne.w	r0, r0, #128	; 0x80
     868:	7018      	strbne	r0, [r3, #0]
		if (width != conv->width_value) {
     86a:	e7b7      	b.n	7dc <extract_conversion+0x48>
     86c:	4602      	mov	r2, r0
	size_t val = 0;
     86e:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
     870:	270a      	movs	r7, #10
     872:	e7ec      	b.n	84e <CONFIG_ISR_STACK_SIZE+0x4e>
		conv->prec_present = true;
     874:	7859      	ldrb	r1, [r3, #1]
		return ++sp;
     876:	3202      	adds	r2, #2
		conv->prec_present = true;
     878:	f021 0106 	bic.w	r1, r1, #6
     87c:	f041 0106 	orr.w	r1, r1, #6
     880:	7059      	strb	r1, [r3, #1]
	switch (*sp) {
     882:	4611      	mov	r1, r2
     884:	f811 0b01 	ldrb.w	r0, [r1], #1
     888:	286c      	cmp	r0, #108	; 0x6c
     88a:	d054      	beq.n	936 <CONFIG_ISR_STACK_SIZE+0x136>
     88c:	d810      	bhi.n	8b0 <CONFIG_ISR_STACK_SIZE+0xb0>
     88e:	2868      	cmp	r0, #104	; 0x68
     890:	d016      	beq.n	8c0 <CONFIG_ISR_STACK_SIZE+0xc0>
     892:	286a      	cmp	r0, #106	; 0x6a
     894:	d058      	beq.n	948 <CONFIG_ISR_STACK_SIZE+0x148>
     896:	284c      	cmp	r0, #76	; 0x4c
     898:	d05c      	beq.n	954 <CONFIG_ISR_STACK_SIZE+0x154>
		conv->length_mod = LENGTH_NONE;
     89a:	7859      	ldrb	r1, [r3, #1]
     89c:	f36f 01c6 	bfc	r1, #3, #4
     8a0:	7059      	strb	r1, [r3, #1]
		break;
     8a2:	4611      	mov	r1, r2
     8a4:	e015      	b.n	8d2 <CONFIG_ISR_STACK_SIZE+0xd2>
		val = 10U * val + *sp++ - '0';
     8a6:	fb07 4101 	mla	r1, r7, r1, r4
     8aa:	4602      	mov	r2, r0
     8ac:	3930      	subs	r1, #48	; 0x30
     8ae:	e79f      	b.n	7f0 <extract_conversion+0x5c>
	switch (*sp) {
     8b0:	2874      	cmp	r0, #116	; 0x74
     8b2:	785c      	ldrb	r4, [r3, #1]
     8b4:	d04b      	beq.n	94e <CONFIG_ISR_STACK_SIZE+0x14e>
     8b6:	287a      	cmp	r0, #122	; 0x7a
     8b8:	d1ef      	bne.n	89a <CONFIG_ISR_STACK_SIZE+0x9a>
		conv->length_mod = LENGTH_Z;
     8ba:	4622      	mov	r2, r4
     8bc:	2006      	movs	r0, #6
     8be:	e036      	b.n	92e <CONFIG_ISR_STACK_SIZE+0x12e>
		if (*++sp == 'h') {
     8c0:	7850      	ldrb	r0, [r2, #1]
     8c2:	785c      	ldrb	r4, [r3, #1]
     8c4:	2868      	cmp	r0, #104	; 0x68
     8c6:	d130      	bne.n	92a <CONFIG_ISR_STACK_SIZE+0x12a>
			conv->length_mod = LENGTH_HH;
     8c8:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     8ca:	f361 04c6 	bfi	r4, r1, #3, #4
     8ce:	705c      	strb	r4, [r3, #1]
			++sp;
     8d0:	1c91      	adds	r1, r2, #2
	conv->specifier = *sp++;
     8d2:	4608      	mov	r0, r1
     8d4:	f810 4b01 	ldrb.w	r4, [r0], #1
	switch (conv->specifier) {
     8d8:	2c78      	cmp	r4, #120	; 0x78
	conv->specifier = *sp++;
     8da:	70dc      	strb	r4, [r3, #3]
	switch (conv->specifier) {
     8dc:	f200 80b1 	bhi.w	a42 <CONFIG_ISR_STACK_SIZE+0x242>
     8e0:	2c57      	cmp	r4, #87	; 0x57
     8e2:	d842      	bhi.n	96a <CONFIG_ISR_STACK_SIZE+0x16a>
     8e4:	2c41      	cmp	r4, #65	; 0x41
     8e6:	d004      	beq.n	8f2 <CONFIG_ISR_STACK_SIZE+0xf2>
     8e8:	f1a4 0245 	sub.w	r2, r4, #69	; 0x45
     8ec:	2a02      	cmp	r2, #2
     8ee:	f200 80a8 	bhi.w	a42 <CONFIG_ISR_STACK_SIZE+0x242>
		conv->specifier_cat = SPECIFIER_FP;
     8f2:	2104      	movs	r1, #4
     8f4:	789a      	ldrb	r2, [r3, #2]
			|| (conv->specifier == 'A');
     8f6:	f004 04df 	and.w	r4, r4, #223	; 0xdf
     8fa:	f1a4 0541 	sub.w	r5, r4, #65	; 0x41
		conv->specifier_cat = SPECIFIER_FP;
     8fe:	f361 0202 	bfi	r2, r1, #0, #3
			|| (conv->specifier == 'A');
     902:	426c      	negs	r4, r5
		conv->specifier_a = (conv->specifier == 'a')
     904:	7859      	ldrb	r1, [r3, #1]
			|| (conv->specifier == 'A');
     906:	416c      	adcs	r4, r5
		conv->specifier_a = (conv->specifier == 'a')
     908:	f364 11c7 	bfi	r1, r4, #7, #1
		if (conv->specifier_a
     90c:	060e      	lsls	r6, r1, #24
		conv->specifier_cat = SPECIFIER_FP;
     90e:	709a      	strb	r2, [r3, #2]
		conv->specifier_a = (conv->specifier == 'a')
     910:	7059      	strb	r1, [r3, #1]
		if (conv->specifier_a
     912:	b2ca      	uxtb	r2, r1
     914:	f100 80b3 	bmi.w	a7e <CONFIG_ISR_STACK_SIZE+0x27e>
		if (conv->length_mod == LENGTH_L) {
     918:	f002 0178 	and.w	r1, r2, #120	; 0x78
     91c:	2918      	cmp	r1, #24
     91e:	f040 808d 	bne.w	a3c <CONFIG_ISR_STACK_SIZE+0x23c>
			conv->length_mod = LENGTH_NONE;
     922:	f36f 02c6 	bfc	r2, #3, #4
     926:	705a      	strb	r2, [r3, #1]
     928:	e078      	b.n	a1c <CONFIG_ISR_STACK_SIZE+0x21c>
			conv->length_mod = LENGTH_H;
     92a:	4622      	mov	r2, r4
     92c:	2002      	movs	r0, #2
			conv->length_mod = LENGTH_L;
     92e:	f360 02c6 	bfi	r2, r0, #3, #4
     932:	705a      	strb	r2, [r3, #1]
     934:	e7cd      	b.n	8d2 <CONFIG_ISR_STACK_SIZE+0xd2>
		if (*++sp == 'l') {
     936:	7850      	ldrb	r0, [r2, #1]
     938:	785c      	ldrb	r4, [r3, #1]
     93a:	286c      	cmp	r0, #108	; 0x6c
     93c:	d101      	bne.n	942 <CONFIG_ISR_STACK_SIZE+0x142>
			conv->length_mod = LENGTH_LL;
     93e:	2104      	movs	r1, #4
     940:	e7c3      	b.n	8ca <CONFIG_ISR_STACK_SIZE+0xca>
			conv->length_mod = LENGTH_L;
     942:	4622      	mov	r2, r4
     944:	2003      	movs	r0, #3
     946:	e7f2      	b.n	92e <CONFIG_ISR_STACK_SIZE+0x12e>
		conv->length_mod = LENGTH_J;
     948:	2005      	movs	r0, #5
     94a:	785a      	ldrb	r2, [r3, #1]
     94c:	e7ef      	b.n	92e <CONFIG_ISR_STACK_SIZE+0x12e>
		conv->length_mod = LENGTH_T;
     94e:	4622      	mov	r2, r4
     950:	2007      	movs	r0, #7
     952:	e7ec      	b.n	92e <CONFIG_ISR_STACK_SIZE+0x12e>
		conv->unsupported = true;
     954:	881a      	ldrh	r2, [r3, #0]
     956:	f422 42f0 	bic.w	r2, r2, #30720	; 0x7800
     95a:	f022 0202 	bic.w	r2, r2, #2
     95e:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
     962:	f042 0202 	orr.w	r2, r2, #2
     966:	801a      	strh	r2, [r3, #0]
		break;
     968:	e7b3      	b.n	8d2 <CONFIG_ISR_STACK_SIZE+0xd2>
     96a:	f1a4 0258 	sub.w	r2, r4, #88	; 0x58
     96e:	2a20      	cmp	r2, #32
     970:	d867      	bhi.n	a42 <CONFIG_ISR_STACK_SIZE+0x242>
     972:	a101      	add	r1, pc, #4	; (adr r1, 978 <CONFIG_ISR_STACK_SIZE+0x178>)
     974:	f851 f022 	ldr.w	pc, [r1, r2, lsl #2]
     978:	00000a21 	.word	0x00000a21
     97c:	00000a43 	.word	0x00000a43
     980:	00000a43 	.word	0x00000a43
     984:	00000a43 	.word	0x00000a43
     988:	00000a43 	.word	0x00000a43
     98c:	00000a43 	.word	0x00000a43
     990:	00000a43 	.word	0x00000a43
     994:	00000a43 	.word	0x00000a43
     998:	00000a43 	.word	0x00000a43
     99c:	000008f3 	.word	0x000008f3
     9a0:	00000a43 	.word	0x00000a43
     9a4:	00000a21 	.word	0x00000a21
     9a8:	000009fd 	.word	0x000009fd
     9ac:	000008f3 	.word	0x000008f3
     9b0:	000008f3 	.word	0x000008f3
     9b4:	000008f3 	.word	0x000008f3
     9b8:	00000a43 	.word	0x00000a43
     9bc:	000009fd 	.word	0x000009fd
     9c0:	00000a43 	.word	0x00000a43
     9c4:	00000a43 	.word	0x00000a43
     9c8:	00000a43 	.word	0x00000a43
     9cc:	00000a43 	.word	0x00000a43
     9d0:	00000a4d 	.word	0x00000a4d
     9d4:	00000a21 	.word	0x00000a21
     9d8:	00000a67 	.word	0x00000a67
     9dc:	00000a43 	.word	0x00000a43
     9e0:	00000a43 	.word	0x00000a43
     9e4:	00000a67 	.word	0x00000a67
     9e8:	00000a43 	.word	0x00000a43
     9ec:	00000a21 	.word	0x00000a21
     9f0:	00000a43 	.word	0x00000a43
     9f4:	00000a43 	.word	0x00000a43
     9f8:	00000a21 	.word	0x00000a21
		conv->specifier_cat = SPECIFIER_SINT;
     9fc:	2101      	movs	r1, #1
     9fe:	789a      	ldrb	r2, [r3, #2]
		conv->specifier_cat = SPECIFIER_UINT;
     a00:	f361 0202 	bfi	r2, r1, #0, #3
     a04:	709a      	strb	r2, [r3, #2]
		if (conv->length_mod == LENGTH_UPPER_L) {
     a06:	785a      	ldrb	r2, [r3, #1]
     a08:	f002 0278 	and.w	r2, r2, #120	; 0x78
     a0c:	2a40      	cmp	r2, #64	; 0x40
			conv->invalid = true;
     a0e:	bf02      	ittt	eq
     a10:	7819      	ldrbeq	r1, [r3, #0]
     a12:	f041 0101 	orreq.w	r1, r1, #1
     a16:	7019      	strbeq	r1, [r3, #0]
		if (conv->specifier == 'c') {
     a18:	2c63      	cmp	r4, #99	; 0x63
     a1a:	d004      	beq.n	a26 <CONFIG_ISR_STACK_SIZE+0x226>
	bool unsupported = false;
     a1c:	2200      	movs	r2, #0
     a1e:	e005      	b.n	a2c <CONFIG_ISR_STACK_SIZE+0x22c>
		conv->specifier_cat = SPECIFIER_UINT;
     a20:	2102      	movs	r1, #2
     a22:	789a      	ldrb	r2, [r3, #2]
     a24:	e7ec      	b.n	a00 <CONFIG_ISR_STACK_SIZE+0x200>
			unsupported = (conv->length_mod != LENGTH_NONE);
     a26:	3a00      	subs	r2, #0
     a28:	bf18      	it	ne
     a2a:	2201      	movne	r2, #1
	conv->unsupported |= unsupported;
     a2c:	7819      	ldrb	r1, [r3, #0]
     a2e:	f3c1 0440 	ubfx	r4, r1, #1, #1
     a32:	4322      	orrs	r2, r4
     a34:	f362 0141 	bfi	r1, r2, #1, #1
     a38:	7019      	strb	r1, [r3, #0]
	return sp;
     a3a:	e6ea      	b.n	812 <CONFIG_ISR_STACK_SIZE+0x12>
		} else if ((conv->length_mod != LENGTH_NONE)
     a3c:	f012 0f38 	tst.w	r2, #56	; 0x38
     a40:	d0ec      	beq.n	a1c <CONFIG_ISR_STACK_SIZE+0x21c>
			conv->invalid = true;
     a42:	781a      	ldrb	r2, [r3, #0]
     a44:	f042 0201 	orr.w	r2, r2, #1
     a48:	701a      	strb	r2, [r3, #0]
     a4a:	e7e7      	b.n	a1c <CONFIG_ISR_STACK_SIZE+0x21c>
		conv->specifier_cat = SPECIFIER_PTR;
     a4c:	2103      	movs	r1, #3
     a4e:	789a      	ldrb	r2, [r3, #2]
     a50:	f361 0202 	bfi	r2, r1, #0, #3
     a54:	709a      	strb	r2, [r3, #2]
		if (conv->length_mod == LENGTH_UPPER_L) {
     a56:	785a      	ldrb	r2, [r3, #1]
     a58:	f002 0278 	and.w	r2, r2, #120	; 0x78
     a5c:	f1a2 0140 	sub.w	r1, r2, #64	; 0x40
     a60:	424a      	negs	r2, r1
     a62:	414a      	adcs	r2, r1
     a64:	e7e2      	b.n	a2c <CONFIG_ISR_STACK_SIZE+0x22c>
		conv->specifier_cat = SPECIFIER_PTR;
     a66:	2103      	movs	r1, #3
     a68:	789a      	ldrb	r2, [r3, #2]
     a6a:	f361 0202 	bfi	r2, r1, #0, #3
     a6e:	709a      	strb	r2, [r3, #2]
		if (conv->length_mod != LENGTH_NONE) {
     a70:	785a      	ldrb	r2, [r3, #1]
     a72:	f012 0f78 	tst.w	r2, #120	; 0x78
     a76:	bf14      	ite	ne
     a78:	2201      	movne	r2, #1
     a7a:	2200      	moveq	r2, #0
     a7c:	e7d6      	b.n	a2c <CONFIG_ISR_STACK_SIZE+0x22c>
			unsupported = true;
     a7e:	2201      	movs	r2, #1
     a80:	e7d4      	b.n	a2c <CONFIG_ISR_STACK_SIZE+0x22c>
     a82:	bf00      	nop

00000a84 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     a84:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     a88:	468a      	mov	sl, r1
     a8a:	4614      	mov	r4, r2
     a8c:	469b      	mov	fp, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     a8e:	f04f 0900 	mov.w	r9, #0
{
     a92:	b0a1      	sub	sp, #132	; 0x84
     a94:	9003      	str	r0, [sp, #12]
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     a96:	7820      	ldrb	r0, [r4, #0]
     a98:	b908      	cbnz	r0, a9e <cbvprintf+0x1a>
			OUTC(' ');
			--width;
		}
	}

	return count;
     a9a:	4648      	mov	r0, r9
     a9c:	e189      	b.n	db2 <cbvprintf+0x32e>
		if (*fp != '%') {
     a9e:	2825      	cmp	r0, #37	; 0x25
     aa0:	d00a      	beq.n	ab8 <cbvprintf+0x34>
			OUTC(*fp++);
     aa2:	4651      	mov	r1, sl
     aa4:	9b03      	ldr	r3, [sp, #12]
     aa6:	4798      	blx	r3
     aa8:	2800      	cmp	r0, #0
     aaa:	f2c0 8182 	blt.w	db2 <cbvprintf+0x32e>
     aae:	1c63      	adds	r3, r4, #1
     ab0:	930b      	str	r3, [sp, #44]	; 0x2c
			OUTC('%');
     ab2:	f109 0901 	add.w	r9, r9, #1
		if (bps == NULL) {
     ab6:	e067      	b.n	b88 <cbvprintf+0x104>
		fp = extract_conversion(&conv, sp);
     ab8:	4621      	mov	r1, r4
     aba:	a816      	add	r0, sp, #88	; 0x58
     abc:	f7ff fe6a 	bl	794 <extract_conversion>
		if (conv.width_star) {
     ac0:	f89d 3059 	ldrb.w	r3, [sp, #89]	; 0x59
		fp = extract_conversion(&conv, sp);
     ac4:	900b      	str	r0, [sp, #44]	; 0x2c
		if (conv.width_star) {
     ac6:	07d8      	lsls	r0, r3, #31
     ac8:	d51c      	bpl.n	b04 <cbvprintf+0x80>
			width = va_arg(ap, int);
     aca:	f85b 2b04 	ldr.w	r2, [fp], #4
			if (width < 0) {
     ace:	2a00      	cmp	r2, #0
			width = va_arg(ap, int);
     ad0:	920a      	str	r2, [sp, #40]	; 0x28
			if (width < 0) {
     ad2:	da08      	bge.n	ae6 <cbvprintf+0x62>
				conv.flag_dash = true;
     ad4:	f89d 2058 	ldrb.w	r2, [sp, #88]	; 0x58
     ad8:	f042 0204 	orr.w	r2, r2, #4
     adc:	f88d 2058 	strb.w	r2, [sp, #88]	; 0x58
				width = -width;
     ae0:	9a0a      	ldr	r2, [sp, #40]	; 0x28
     ae2:	4252      	negs	r2, r2
		int width = -1;
     ae4:	920a      	str	r2, [sp, #40]	; 0x28
		if (conv.prec_star) {
     ae6:	0759      	lsls	r1, r3, #29
     ae8:	d514      	bpl.n	b14 <cbvprintf+0x90>
			int arg = va_arg(ap, int);
     aea:	f85b 5b04 	ldr.w	r5, [fp], #4
			if (arg < 0) {
     aee:	2d00      	cmp	r5, #0
     af0:	da13      	bge.n	b1a <cbvprintf+0x96>
				conv.prec_present = false;
     af2:	f89d 3059 	ldrb.w	r3, [sp, #89]	; 0x59
     af6:	f36f 0341 	bfc	r3, #1, #1
     afa:	f88d 3059 	strb.w	r3, [sp, #89]	; 0x59
		int precision = -1;
     afe:	f04f 35ff 	mov.w	r5, #4294967295
     b02:	e00a      	b.n	b1a <cbvprintf+0x96>
		} else if (conv.width_present) {
     b04:	f99d 2058 	ldrsb.w	r2, [sp, #88]	; 0x58
     b08:	2a00      	cmp	r2, #0
		int width = -1;
     b0a:	bfac      	ite	ge
     b0c:	f04f 32ff 	movge.w	r2, #4294967295
			width = conv.width_value;
     b10:	9a17      	ldrlt	r2, [sp, #92]	; 0x5c
     b12:	e7e7      	b.n	ae4 <cbvprintf+0x60>
		} else if (conv.prec_present) {
     b14:	079a      	lsls	r2, r3, #30
     b16:	d5f2      	bpl.n	afe <cbvprintf+0x7a>
			precision = conv.prec_value;
     b18:	9d18      	ldr	r5, [sp, #96]	; 0x60
		conv.pad0_value = 0;
     b1a:	2300      	movs	r3, #0
		conv.pad0_pre_exp = 0;
     b1c:	e9cd 3317 	strd	r3, r3, [sp, #92]	; 0x5c
		    && (conv.specifier_cat == SPECIFIER_FP)
     b20:	f89d 305a 	ldrb.w	r3, [sp, #90]	; 0x5a
     b24:	f89d 2059 	ldrb.w	r2, [sp, #89]	; 0x59
		if (IS_ENABLED(CONFIG_CBPRINTF_FP_SUPPORT)
     b28:	f003 0307 	and.w	r3, r3, #7
     b2c:	2b04      	cmp	r3, #4
     b2e:	d107      	bne.n	b40 <cbvprintf+0xbc>
		    && !conv.prec_present) {
     b30:	0793      	lsls	r3, r2, #30
     b32:	d405      	bmi.n	b40 <cbvprintf+0xbc>
			if (conv.specifier_a) {
     b34:	f99d 3059 	ldrsb.w	r3, [sp, #89]	; 0x59
				precision = 6;
     b38:	2b00      	cmp	r3, #0
     b3a:	bfb4      	ite	lt
     b3c:	250d      	movlt	r5, #13
     b3e:	2506      	movge	r5, #6
			= (enum specifier_cat_enum)conv.specifier_cat;
     b40:	f89d 305a 	ldrb.w	r3, [sp, #90]	; 0x5a
		union argument_value value = (union argument_value){
     b44:	2000      	movs	r0, #0
		enum specifier_cat_enum specifier_cat
     b46:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     b4a:	2b01      	cmp	r3, #1
		union argument_value value = (union argument_value){
     b4c:	f04f 0100 	mov.w	r1, #0
			= (enum length_mod_enum)conv.length_mod;
     b50:	f3c2 02c3 	ubfx	r2, r2, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     b54:	d126      	bne.n	ba4 <cbvprintf+0x120>
			switch (length_mod) {
     b56:	1ed3      	subs	r3, r2, #3
     b58:	2b04      	cmp	r3, #4
     b5a:	d817      	bhi.n	b8c <cbvprintf+0x108>
     b5c:	e8df f003 	tbb	[pc, r3]
     b60:	16323203 	.word	0x16323203
     b64:	16          	.byte	0x16
     b65:	00          	.byte	0x00
				value.sint = va_arg(ap, long);
     b66:	f85b 0b04 	ldr.w	r0, [fp], #4
				value.sint = (short)value.sint;
     b6a:	17c1      	asrs	r1, r0, #31
		if (conv.invalid || conv.unsupported) {
     b6c:	f89d 6058 	ldrb.w	r6, [sp, #88]	; 0x58
     b70:	07b7      	lsls	r7, r6, #30
     b72:	d047      	beq.n	c04 <cbvprintf+0x180>
			OUTS(sp, fp);
     b74:	4622      	mov	r2, r4
     b76:	4651      	mov	r1, sl
     b78:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
     b7a:	9803      	ldr	r0, [sp, #12]
     b7c:	f004 fc89 	bl	5492 <outs>
     b80:	2800      	cmp	r0, #0
     b82:	f2c0 8116 	blt.w	db2 <cbvprintf+0x32e>
     b86:	4481      	add	r9, r0
			continue;
     b88:	9c0b      	ldr	r4, [sp, #44]	; 0x2c
     b8a:	e784      	b.n	a96 <cbvprintf+0x12>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     b8c:	f85b 0b04 	ldr.w	r0, [fp], #4
			if (length_mod == LENGTH_HH) {
     b90:	2a01      	cmp	r2, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
     b92:	ea4f 71e0 	mov.w	r1, r0, asr #31
			if (length_mod == LENGTH_HH) {
     b96:	d101      	bne.n	b9c <cbvprintf+0x118>
				value.uint = (unsigned char)value.uint;
     b98:	b2c6      	uxtb	r6, r0
     b9a:	e00f      	b.n	bbc <cbvprintf+0x138>
			} else if (length_mod == LENGTH_H) {
     b9c:	2a02      	cmp	r2, #2
     b9e:	d1e5      	bne.n	b6c <cbvprintf+0xe8>
				value.sint = (short)value.sint;
     ba0:	b200      	sxth	r0, r0
     ba2:	e7e2      	b.n	b6a <cbvprintf+0xe6>
		} else if (specifier_cat == SPECIFIER_UINT) {
     ba4:	2b02      	cmp	r3, #2
     ba6:	d11f      	bne.n	be8 <cbvprintf+0x164>
			switch (length_mod) {
     ba8:	1ed3      	subs	r3, r2, #3
     baa:	2b04      	cmp	r3, #4
     bac:	d811      	bhi.n	bd2 <cbvprintf+0x14e>
     bae:	e8df f003 	tbb	[pc, r3]
     bb2:	0903      	.short	0x0903
     bb4:	1009      	.short	0x1009
     bb6:	10          	.byte	0x10
     bb7:	00          	.byte	0x00
				value.uint = va_arg(ap, unsigned long);
     bb8:	f85b 6b04 	ldr.w	r6, [fp], #4
				value.uint = (unsigned short)value.uint;
     bbc:	2300      	movs	r3, #0
     bbe:	4630      	mov	r0, r6
     bc0:	4619      	mov	r1, r3
     bc2:	e7d3      	b.n	b6c <cbvprintf+0xe8>
					(uint_value_type)va_arg(ap,
     bc4:	f10b 0b07 	add.w	fp, fp, #7
     bc8:	f02b 0b07 	bic.w	fp, fp, #7
				value.uint =
     bcc:	e8fb 0102 	ldrd	r0, r1, [fp], #8
				break;
     bd0:	e7cc      	b.n	b6c <cbvprintf+0xe8>
				value.uint =
     bd2:	2300      	movs	r3, #0
     bd4:	f85b 6b04 	ldr.w	r6, [fp], #4
			if (length_mod == LENGTH_HH) {
     bd8:	2a01      	cmp	r2, #1
				value.uint =
     bda:	4630      	mov	r0, r6
     bdc:	4619      	mov	r1, r3
			if (length_mod == LENGTH_HH) {
     bde:	d0db      	beq.n	b98 <cbvprintf+0x114>
			} else if (length_mod == LENGTH_H) {
     be0:	2a02      	cmp	r2, #2
     be2:	d1c3      	bne.n	b6c <cbvprintf+0xe8>
				value.uint = (unsigned short)value.uint;
     be4:	b2b6      	uxth	r6, r6
     be6:	e7e9      	b.n	bbc <cbvprintf+0x138>
		} else if (specifier_cat == SPECIFIER_FP) {
     be8:	2b04      	cmp	r3, #4
     bea:	d106      	bne.n	bfa <cbvprintf+0x176>
			if (length_mod == LENGTH_UPPER_L) {
     bec:	f10b 0b07 	add.w	fp, fp, #7
     bf0:	f02b 0b07 	bic.w	fp, fp, #7
     bf4:	e8fb 0102 	ldrd	r0, r1, [fp], #8
     bf8:	e7b8      	b.n	b6c <cbvprintf+0xe8>
		} else if (specifier_cat == SPECIFIER_PTR) {
     bfa:	2b03      	cmp	r3, #3
			value.ptr = va_arg(ap, void *);
     bfc:	bf08      	it	eq
     bfe:	f85b 0b04 	ldreq.w	r0, [fp], #4
     c02:	e7b3      	b.n	b6c <cbvprintf+0xe8>
		switch (conv.specifier) {
     c04:	f89d 705b 	ldrb.w	r7, [sp, #91]	; 0x5b
     c08:	2f78      	cmp	r7, #120	; 0x78
     c0a:	d8bd      	bhi.n	b88 <cbvprintf+0x104>
     c0c:	2f57      	cmp	r7, #87	; 0x57
     c0e:	d87f      	bhi.n	d10 <cbvprintf+0x28c>
     c10:	2f25      	cmp	r7, #37	; 0x25
     c12:	f000 80c7 	beq.w	da4 <cbvprintf+0x320>
     c16:	2f24      	cmp	r7, #36	; 0x24
     c18:	d9b6      	bls.n	b88 <cbvprintf+0x104>
     c1a:	2f41      	cmp	r7, #65	; 0x41
     c1c:	d003      	beq.n	c26 <cbvprintf+0x1a2>
     c1e:	f1a7 0345 	sub.w	r3, r7, #69	; 0x45
     c22:	2b02      	cmp	r3, #2
     c24:	d8b0      	bhi.n	b88 <cbvprintf+0x104>
	if ((u.u64 & SIGN_MASK) != 0U) {
     c26:	2800      	cmp	r0, #0
     c28:	f171 0300 	sbcs.w	r3, r1, #0
     c2c:	f2c0 815c 	blt.w	ee8 <cbvprintf+0x464>
	} else if (conv->flag_plus) {
     c30:	0732      	lsls	r2, r6, #28
     c32:	f100 815b 	bmi.w	eec <cbvprintf+0x468>
		*sign = ' ';
     c36:	f016 0610 	ands.w	r6, r6, #16
     c3a:	bf18      	it	ne
     c3c:	2620      	movne	r6, #32
	uint64_t fract = u.u64 & BIT64_MASK(FRACTION_BITS);
     c3e:	f3c1 0313 	ubfx	r3, r1, #0, #20
     c42:	9006      	str	r0, [sp, #24]
     c44:	9307      	str	r3, [sp, #28]
	int exp = (u.u64 >> FRACTION_BITS) & BIT_MASK(EXPONENT_BITS);
     c46:	f3c1 540a 	ubfx	r4, r1, #20, #11
	uint64_t fract = u.u64 & BIT64_MASK(FRACTION_BITS);
     c4a:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
     c4e:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
	bool is_subnormal = (exp == 0) && (fract != 0);
     c52:	2c00      	cmp	r4, #0
     c54:	f040 814c 	bne.w	ef0 <cbvprintf+0x46c>
     c58:	4603      	mov	r3, r0
     c5a:	9a07      	ldr	r2, [sp, #28]
     c5c:	4313      	orrs	r3, r2
     c5e:	bf14      	ite	ne
     c60:	f04f 0c01 	movne.w	ip, #1
     c64:	f04f 0c00 	moveq.w	ip, #0
	fract <<= EXPONENT_BITS;
     c68:	9907      	ldr	r1, [sp, #28]
		c = 'f';
     c6a:	2f46      	cmp	r7, #70	; 0x46
	fract <<= EXPONENT_BITS;
     c6c:	ea4f 23c1 	mov.w	r3, r1, lsl #11
     c70:	9906      	ldr	r1, [sp, #24]
		c = 'f';
     c72:	bf08      	it	eq
     c74:	2766      	moveq	r7, #102	; 0x66
	fract <<= EXPONENT_BITS;
     c76:	02ca      	lsls	r2, r1, #11
     c78:	ea43 5351 	orr.w	r3, r3, r1, lsr #21
	if ((exp | fract) != 0) {
     c7c:	ea44 0102 	orr.w	r1, r4, r2
     c80:	910c      	str	r1, [sp, #48]	; 0x30
     c82:	17e1      	asrs	r1, r4, #31
     c84:	4319      	orrs	r1, r3
     c86:	910d      	str	r1, [sp, #52]	; 0x34
     c88:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
     c8c:	4301      	orrs	r1, r0
	fract &= ~SIGN_MASK;
     c8e:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
	if ((exp | fract) != 0) {
     c92:	f000 81cf 	beq.w	1034 <CONFIG_MAIN_STACK_SIZE+0x34>
		if (is_subnormal) {
     c96:	f1bc 0f00 	cmp.w	ip, #0
     c9a:	f040 815d 	bne.w	f58 <cbvprintf+0x4d4>
		exp -= (1023 - 1);	/* +1 since .1 vs 1. */
     c9e:	f2a4 38fe 	subw	r8, r4, #1022	; 0x3fe
		fract |= BIT_63;
     ca2:	2400      	movs	r4, #0
     ca4:	9b13      	ldr	r3, [sp, #76]	; 0x4c
     ca6:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
     caa:	9313      	str	r3, [sp, #76]	; 0x4c
	while (exp <= -3) {
     cac:	f118 0f02 	cmn.w	r8, #2
     cb0:	f2c0 815e 	blt.w	f70 <cbvprintf+0x4ec>
	while (exp > 0) {
     cb4:	f1b8 0f00 	cmp.w	r8, #0
     cb8:	f300 8196 	bgt.w	fe8 <cbvprintf+0x564>
		_rlrshift(&fract);
     cbc:	a812      	add	r0, sp, #72	; 0x48
		exp++;
     cbe:	f108 0801 	add.w	r8, r8, #1
		_rlrshift(&fract);
     cc2:	f004 fb52 	bl	536a <_rlrshift>
	while (exp < (0 + 4)) {
     cc6:	f1b8 0f04 	cmp.w	r8, #4
     cca:	d1f7      	bne.n	cbc <cbvprintf+0x238>
	if ((c == 'g') || (c == 'G')) {
     ccc:	f007 03df 	and.w	r3, r7, #223	; 0xdf
     cd0:	2b47      	cmp	r3, #71	; 0x47
     cd2:	f040 81b5 	bne.w	1040 <CONFIG_MAIN_STACK_SIZE+0x40>
		if (decexp < (-4 + 1) || decexp > precision) {
     cd6:	1ce3      	adds	r3, r4, #3
     cd8:	db02      	blt.n	ce0 <cbvprintf+0x25c>
     cda:	42a5      	cmp	r5, r4
     cdc:	f280 81ad 	bge.w	103a <CONFIG_MAIN_STACK_SIZE+0x3a>
			c += 'e' - 'g';  /* e or E */
     ce0:	3f02      	subs	r7, #2
			if (precision > 0) {
     ce2:	2d00      	cmp	r5, #0
			c += 'e' - 'g';  /* e or E */
     ce4:	b2ff      	uxtb	r7, r7
			if (precision > 0) {
     ce6:	dd00      	ble.n	cea <cbvprintf+0x266>
				precision--;
     ce8:	3d01      	subs	r5, #1
		if (!conv->flag_hash && (precision > 0)) {
     cea:	f89d 3058 	ldrb.w	r3, [sp, #88]	; 0x58
     cee:	0698      	lsls	r0, r3, #26
     cf0:	f100 81a6 	bmi.w	1040 <CONFIG_MAIN_STACK_SIZE+0x40>
     cf4:	2d00      	cmp	r5, #0
     cf6:	bfd4      	ite	le
     cf8:	2300      	movle	r3, #0
     cfa:	2301      	movgt	r3, #1
	if (c == 'f') {
     cfc:	2f66      	cmp	r7, #102	; 0x66
	bool prune_zero = false;
     cfe:	9304      	str	r3, [sp, #16]
	if (c == 'f') {
     d00:	f040 81a0 	bne.w	1044 <CONFIG_MAIN_STACK_SIZE+0x44>
		if (exp < 0) {
     d04:	1963      	adds	r3, r4, r5
     d06:	f140 819e 	bpl.w	1046 <CONFIG_MAIN_STACK_SIZE+0x46>
			exp = 0;
     d0a:	f04f 0800 	mov.w	r8, #0
     d0e:	e19e      	b.n	104e <CONFIG_MAIN_STACK_SIZE+0x4e>
     d10:	f1a7 0358 	sub.w	r3, r7, #88	; 0x58
     d14:	2b20      	cmp	r3, #32
     d16:	f63f af37 	bhi.w	b88 <cbvprintf+0x104>
     d1a:	a401      	add	r4, pc, #4	; (adr r4, d20 <cbvprintf+0x29c>)
     d1c:	f854 f023 	ldr.w	pc, [r4, r3, lsl #2]
     d20:	00000e87 	.word	0x00000e87
     d24:	00000b89 	.word	0x00000b89
     d28:	00000b89 	.word	0x00000b89
     d2c:	00000b89 	.word	0x00000b89
     d30:	00000b89 	.word	0x00000b89
     d34:	00000b89 	.word	0x00000b89
     d38:	00000b89 	.word	0x00000b89
     d3c:	00000b89 	.word	0x00000b89
     d40:	00000b89 	.word	0x00000b89
     d44:	00000c27 	.word	0x00000c27
     d48:	00000b89 	.word	0x00000b89
     d4c:	00000dd3 	.word	0x00000dd3
     d50:	00000e35 	.word	0x00000e35
     d54:	00000c27 	.word	0x00000c27
     d58:	00000c27 	.word	0x00000c27
     d5c:	00000c27 	.word	0x00000c27
     d60:	00000b89 	.word	0x00000b89
     d64:	00000e35 	.word	0x00000e35
     d68:	00000b89 	.word	0x00000b89
     d6c:	00000b89 	.word	0x00000b89
     d70:	00000b89 	.word	0x00000b89
     d74:	00000b89 	.word	0x00000b89
     d78:	00000ebb 	.word	0x00000ebb
     d7c:	00000e87 	.word	0x00000e87
     d80:	00000e8b 	.word	0x00000e8b
     d84:	00000b89 	.word	0x00000b89
     d88:	00000b89 	.word	0x00000b89
     d8c:	00000db9 	.word	0x00000db9
     d90:	00000b89 	.word	0x00000b89
     d94:	00000e87 	.word	0x00000e87
     d98:	00000b89 	.word	0x00000b89
     d9c:	00000b89 	.word	0x00000b89
     da0:	00000e87 	.word	0x00000e87
			OUTC('%');
     da4:	4651      	mov	r1, sl
     da6:	4638      	mov	r0, r7
     da8:	9b03      	ldr	r3, [sp, #12]
     daa:	4798      	blx	r3
     dac:	2800      	cmp	r0, #0
     dae:	f6bf ae80 	bge.w	ab2 <cbvprintf+0x2e>
#undef OUTS
#undef OUTC
}
     db2:	b021      	add	sp, #132	; 0x84
     db4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			bps = (const char *)value.ptr;
     db8:	4604      	mov	r4, r0
			size_t len = strlen(bps);
     dba:	f004 fcd6 	bl	576a <strlen>
			if ((precision >= 0)
     dbe:	2d00      	cmp	r5, #0
     dc0:	db02      	blt.n	dc8 <cbvprintf+0x344>
     dc2:	42a8      	cmp	r0, r5
     dc4:	bf28      	it	cs
     dc6:	4628      	movcs	r0, r5
		char sign = 0;
     dc8:	2600      	movs	r6, #0
			bpe = bps + len;
     dca:	eb04 0800 	add.w	r8, r4, r0
		if (bps == NULL) {
     dce:	b934      	cbnz	r4, dde <cbvprintf+0x35a>
     dd0:	e6da      	b.n	b88 <cbvprintf+0x104>
		char sign = 0;
     dd2:	2600      	movs	r6, #0
			buf[0] = value.uint;
     dd4:	f88d 0064 	strb.w	r0, [sp, #100]	; 0x64
			bpe = buf + 1;
     dd8:	f10d 0865 	add.w	r8, sp, #101	; 0x65
				bps = encode_float(value.dbl, &conv, precision,
     ddc:	ac19      	add	r4, sp, #100	; 0x64
		size_t nj_len = (bpe - bps);
     dde:	eba8 0704 	sub.w	r7, r8, r4
		if (sign != 0) {
     de2:	b106      	cbz	r6, de6 <cbvprintf+0x362>
			nj_len += 1U;
     de4:	3701      	adds	r7, #1
		if (conv.altform_0c) {
     de6:	f89d 105a 	ldrb.w	r1, [sp, #90]	; 0x5a
     dea:	06cb      	lsls	r3, r1, #27
     dec:	f140 8206 	bpl.w	11fc <CONFIG_MAIN_STACK_SIZE+0x1fc>
			nj_len += 2U;
     df0:	3702      	adds	r7, #2
		nj_len += conv.pad0_value;
     df2:	9a17      	ldr	r2, [sp, #92]	; 0x5c
		if (conv.pad_fp) {
     df4:	0648      	lsls	r0, r1, #25
		nj_len += conv.pad0_value;
     df6:	4417      	add	r7, r2
		if (width > 0) {
     df8:	9b0a      	ldr	r3, [sp, #40]	; 0x28
			nj_len += conv.pad0_pre_exp;
     dfa:	bf44      	itt	mi
     dfc:	9a18      	ldrmi	r2, [sp, #96]	; 0x60
     dfe:	18bf      	addmi	r7, r7, r2
		if (width > 0) {
     e00:	2b00      	cmp	r3, #0
     e02:	f340 820e 	ble.w	1222 <CONFIG_MAIN_STACK_SIZE+0x222>
			if (!conv.flag_dash) {
     e06:	f89d 2058 	ldrb.w	r2, [sp, #88]	; 0x58
			width -= (int)nj_len;
     e0a:	1bdf      	subs	r7, r3, r7
			if (!conv.flag_dash) {
     e0c:	0751      	lsls	r1, r2, #29
     e0e:	f3c2 0580 	ubfx	r5, r2, #2, #1
     e12:	f100 8245 	bmi.w	12a0 <CONFIG_MAIN_STACK_SIZE+0x2a0>
				if (conv.flag_zero) {
     e16:	0653      	lsls	r3, r2, #25
     e18:	f140 823e 	bpl.w	1298 <CONFIG_MAIN_STACK_SIZE+0x298>
					if (sign != 0) {
     e1c:	b146      	cbz	r6, e30 <cbvprintf+0x3ac>
						OUTC(sign);
     e1e:	4651      	mov	r1, sl
     e20:	4630      	mov	r0, r6
     e22:	9b03      	ldr	r3, [sp, #12]
     e24:	4798      	blx	r3
     e26:	2800      	cmp	r0, #0
     e28:	dbc3      	blt.n	db2 <cbvprintf+0x32e>
						sign = 0;
     e2a:	462e      	mov	r6, r5
						OUTC(sign);
     e2c:	f109 0901 	add.w	r9, r9, #1
					pad = '0';
     e30:	2530      	movs	r5, #48	; 0x30
     e32:	e232      	b.n	129a <CONFIG_MAIN_STACK_SIZE+0x29a>
			if (conv.flag_plus) {
     e34:	0734      	lsls	r4, r6, #28
     e36:	d424      	bmi.n	e82 <cbvprintf+0x3fe>
				sign = ' ';
     e38:	f016 0610 	ands.w	r6, r6, #16
     e3c:	bf18      	it	ne
     e3e:	2620      	movne	r6, #32
			if (value.sint < 0) {
     e40:	2800      	cmp	r0, #0
     e42:	f171 0300 	sbcs.w	r3, r1, #0
     e46:	da03      	bge.n	e50 <cbvprintf+0x3cc>
				sign = '-';
     e48:	262d      	movs	r6, #45	; 0x2d
				value.uint = -value.sint;
     e4a:	4240      	negs	r0, r0
     e4c:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
			bps = encode_uint(value.uint, &conv, buf, bpe);
     e50:	f10d 037d 	add.w	r3, sp, #125	; 0x7d
     e54:	9300      	str	r3, [sp, #0]
     e56:	aa16      	add	r2, sp, #88	; 0x58
     e58:	ab19      	add	r3, sp, #100	; 0x64
     e5a:	f004 facf 	bl	53fc <encode_uint>
     e5e:	4604      	mov	r4, r0
			if (precision >= 0) {
     e60:	2d00      	cmp	r5, #0
     e62:	f10d 037d 	add.w	r3, sp, #125	; 0x7d
     e66:	db0a      	blt.n	e7e <cbvprintf+0x3fa>
				conv.flag_zero = false;
     e68:	f89d 1058 	ldrb.w	r1, [sp, #88]	; 0x58
				size_t len = bpe - bps;
     e6c:	1b1a      	subs	r2, r3, r4
				conv.flag_zero = false;
     e6e:	f36f 1186 	bfc	r1, #6, #1
				if (len < (size_t)precision) {
     e72:	4295      	cmp	r5, r2
				conv.flag_zero = false;
     e74:	f88d 1058 	strb.w	r1, [sp, #88]	; 0x58
				if (len < (size_t)precision) {
     e78:	d901      	bls.n	e7e <cbvprintf+0x3fa>
					conv.pad0_value = precision - (int)len;
     e7a:	1aad      	subs	r5, r5, r2
     e7c:	9517      	str	r5, [sp, #92]	; 0x5c
		const char *bpe = buf + sizeof(buf);
     e7e:	4698      	mov	r8, r3
     e80:	e7a5      	b.n	dce <cbvprintf+0x34a>
				sign = '+';
     e82:	262b      	movs	r6, #43	; 0x2b
     e84:	e7dc      	b.n	e40 <cbvprintf+0x3bc>
		switch (conv.specifier) {
     e86:	2600      	movs	r6, #0
     e88:	e7e2      	b.n	e50 <cbvprintf+0x3cc>
			if (value.ptr != NULL) {
     e8a:	2800      	cmp	r0, #0
     e8c:	f000 81b0 	beq.w	11f0 <CONFIG_MAIN_STACK_SIZE+0x1f0>
				bps = encode_uint((uintptr_t)value.ptr, &conv,
     e90:	f10d 037d 	add.w	r3, sp, #125	; 0x7d
     e94:	9300      	str	r3, [sp, #0]
     e96:	2100      	movs	r1, #0
     e98:	ab19      	add	r3, sp, #100	; 0x64
     e9a:	aa16      	add	r2, sp, #88	; 0x58
     e9c:	f004 faae 	bl	53fc <encode_uint>
				conv.altform_0c = true;
     ea0:	f8bd 305a 	ldrh.w	r3, [sp, #90]	; 0x5a
				bps = encode_uint((uintptr_t)value.ptr, &conv,
     ea4:	4604      	mov	r4, r0
				conv.altform_0c = true;
     ea6:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     eaa:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     eae:	f043 0310 	orr.w	r3, r3, #16
		char sign = 0;
     eb2:	2600      	movs	r6, #0
				conv.altform_0c = true;
     eb4:	f8ad 305a 	strh.w	r3, [sp, #90]	; 0x5a
				goto prec_int_pad0;
     eb8:	e7d2      	b.n	e60 <cbvprintf+0x3dc>
	switch ((enum length_mod_enum)conv->length_mod) {
     eba:	2a07      	cmp	r2, #7
     ebc:	f63f ae64 	bhi.w	b88 <cbvprintf+0x104>
     ec0:	e8df f002 	tbb	[pc, r2]
     ec4:	0f07040f 	.word	0x0f07040f
     ec8:	0f0f0a0a 	.word	0x0f0f0a0a
		*(signed char *)dp = (signed char)count;
     ecc:	f880 9000 	strb.w	r9, [r0]
		break;
     ed0:	e65a      	b.n	b88 <cbvprintf+0x104>
		*(short *)dp = (short)count;
     ed2:	f8a0 9000 	strh.w	r9, [r0]
		break;
     ed6:	e657      	b.n	b88 <cbvprintf+0x104>
		*(intmax_t *)dp = (intmax_t)count;
     ed8:	464a      	mov	r2, r9
     eda:	17d3      	asrs	r3, r2, #31
     edc:	e9c0 2300 	strd	r2, r3, [r0]
		break;
     ee0:	e652      	b.n	b88 <cbvprintf+0x104>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     ee2:	f8c0 9000 	str.w	r9, [r0]
		break;
     ee6:	e64f      	b.n	b88 <cbvprintf+0x104>
		*sign = '-';
     ee8:	262d      	movs	r6, #45	; 0x2d
     eea:	e6a8      	b.n	c3e <cbvprintf+0x1ba>
		*sign = '+';
     eec:	262b      	movs	r6, #43	; 0x2b
     eee:	e6a6      	b.n	c3e <cbvprintf+0x1ba>
	if (exp == BIT_MASK(EXPONENT_BITS)) {
     ef0:	f240 73ff 	movw	r3, #2047	; 0x7ff
     ef4:	429c      	cmp	r4, r3
     ef6:	d12b      	bne.n	f50 <cbvprintf+0x4cc>
		if (fract == 0) {
     ef8:	e9dd 3406 	ldrd	r3, r4, [sp, #24]
     efc:	4323      	orrs	r3, r4
     efe:	f1a7 0741 	sub.w	r7, r7, #65	; 0x41
     f02:	d117      	bne.n	f34 <cbvprintf+0x4b0>
			if (isupper((int)c)) {
     f04:	2f19      	cmp	r7, #25
				*buf++ = 'I';
     f06:	bf95      	itete	ls
     f08:	f644 6349 	movwls	r3, #20041	; 0x4e49
				*buf++ = 'i';
     f0c:	f646 6369 	movwhi	r3, #28265	; 0x6e69
				*buf++ = 'I';
     f10:	f8ad 3064 	strhls.w	r3, [sp, #100]	; 0x64
				*buf++ = 'i';
     f14:	f8ad 3064 	strhhi.w	r3, [sp, #100]	; 0x64
				*buf++ = 'F';
     f18:	bf94      	ite	ls
     f1a:	2346      	movls	r3, #70	; 0x46
				*buf++ = 'f';
     f1c:	2366      	movhi	r3, #102	; 0x66
				*buf++ = 'n';
     f1e:	f88d 3066 	strb.w	r3, [sp, #102]	; 0x66
		conv->flag_zero = false;
     f22:	f89d 3058 	ldrb.w	r3, [sp, #88]	; 0x58
		*bpe = buf;
     f26:	f10d 0867 	add.w	r8, sp, #103	; 0x67
		conv->flag_zero = false;
     f2a:	f36f 1386 	bfc	r3, #6, #1
     f2e:	f88d 3058 	strb.w	r3, [sp, #88]	; 0x58
		return bps;
     f32:	e753      	b.n	ddc <cbvprintf+0x358>
			if (isupper((int)c)) {
     f34:	2f19      	cmp	r7, #25
				*buf++ = 'N';
     f36:	bf95      	itete	ls
     f38:	f244 134e 	movwls	r3, #16718	; 0x414e
				*buf++ = 'n';
     f3c:	f246 136e 	movwhi	r3, #24942	; 0x616e
				*buf++ = 'N';
     f40:	f8ad 3064 	strhls.w	r3, [sp, #100]	; 0x64
				*buf++ = 'n';
     f44:	f8ad 3064 	strhhi.w	r3, [sp, #100]	; 0x64
				*buf++ = 'N';
     f48:	bf94      	ite	ls
     f4a:	234e      	movls	r3, #78	; 0x4e
				*buf++ = 'n';
     f4c:	236e      	movhi	r3, #110	; 0x6e
     f4e:	e7e6      	b.n	f1e <cbvprintf+0x49a>
	bool is_subnormal = (exp == 0) && (fract != 0);
     f50:	f04f 0c00 	mov.w	ip, #0
     f54:	e688      	b.n	c68 <cbvprintf+0x1e4>
				exp--;
     f56:	3c01      	subs	r4, #1
			while (((fract <<= 1) & BIT_63) == 0) {
     f58:	1892      	adds	r2, r2, r2
     f5a:	415b      	adcs	r3, r3
     f5c:	2a00      	cmp	r2, #0
     f5e:	f173 0100 	sbcs.w	r1, r3, #0
     f62:	daf8      	bge.n	f56 <cbvprintf+0x4d2>
     f64:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
     f68:	e699      	b.n	c9e <cbvprintf+0x21a>
			_rlrshift(&fract);
     f6a:	a812      	add	r0, sp, #72	; 0x48
     f6c:	f004 f9fd 	bl	536a <_rlrshift>
		while ((fract >> 32) >= (MAX_FP1 / 5)) {
     f70:	e9dd 2c12 	ldrd	r2, ip, [sp, #72]	; 0x48
     f74:	2300      	movs	r3, #0
     f76:	f8cd c020 	str.w	ip, [sp, #32]
     f7a:	9309      	str	r3, [sp, #36]	; 0x24
     f7c:	e9dd 0108 	ldrd	r0, r1, [sp, #32]
     f80:	2900      	cmp	r1, #0
     f82:	bf08      	it	eq
     f84:	f1b0 3f33 	cmpeq.w	r0, #858993459	; 0x33333333
     f88:	f108 0801 	add.w	r8, r8, #1
     f8c:	d2ed      	bcs.n	f6a <cbvprintf+0x4e6>
		fract *= 5U;
     f8e:	2005      	movs	r0, #5
     f90:	fba2 2300 	umull	r2, r3, r2, r0
     f94:	e9cd 2304 	strd	r2, r3, [sp, #16]
     f98:	9b05      	ldr	r3, [sp, #20]
		decexp--;
     f9a:	3c01      	subs	r4, #1
		fract *= 5U;
     f9c:	fb00 330c 	mla	r3, r0, ip, r3
		while ((fract >> 32) <= (MAX_FP1 / 2)) {
     fa0:	f04f 0c00 	mov.w	ip, #0
		fract *= 5U;
     fa4:	9305      	str	r3, [sp, #20]
     fa6:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
     faa:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
		while ((fract >> 32) <= (MAX_FP1 / 2)) {
     fae:	2100      	movs	r1, #0
     fb0:	2300      	movs	r3, #0
     fb2:	f06f 4200 	mvn.w	r2, #2147483648	; 0x80000000
     fb6:	9805      	ldr	r0, [sp, #20]
     fb8:	428b      	cmp	r3, r1
     fba:	bf08      	it	eq
     fbc:	4282      	cmpeq	r2, r0
     fbe:	d208      	bcs.n	fd2 <cbvprintf+0x54e>
     fc0:	f1bc 0f00 	cmp.w	ip, #0
     fc4:	f43f ae72 	beq.w	cac <cbvprintf+0x228>
     fc8:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
     fcc:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
     fd0:	e66c      	b.n	cac <cbvprintf+0x228>
			fract <<= 1;
     fd2:	9b04      	ldr	r3, [sp, #16]
			exp--;
     fd4:	f04f 0c01 	mov.w	ip, #1
			fract <<= 1;
     fd8:	18db      	adds	r3, r3, r3
     fda:	9304      	str	r3, [sp, #16]
     fdc:	9b05      	ldr	r3, [sp, #20]
			exp--;
     fde:	f108 38ff 	add.w	r8, r8, #4294967295
			fract <<= 1;
     fe2:	415b      	adcs	r3, r3
     fe4:	9305      	str	r3, [sp, #20]
			exp--;
     fe6:	e7e2      	b.n	fae <cbvprintf+0x52a>
		_ldiv5(&fract);
     fe8:	a812      	add	r0, sp, #72	; 0x48
     fea:	f004 f9cf 	bl	538c <_ldiv5>
		while ((fract >> 32) <= (MAX_FP1 / 2)) {
     fee:	f04f 0c00 	mov.w	ip, #0
     ff2:	9b12      	ldr	r3, [sp, #72]	; 0x48
     ff4:	f8dd e04c 	ldr.w	lr, [sp, #76]	; 0x4c
		exp--;
     ff8:	f108 38ff 	add.w	r8, r8, #4294967295
		decexp++;
     ffc:	3401      	adds	r4, #1
		while ((fract >> 32) <= (MAX_FP1 / 2)) {
     ffe:	9304      	str	r3, [sp, #16]
    1000:	2300      	movs	r3, #0
    1002:	2100      	movs	r1, #0
    1004:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    1008:	4299      	cmp	r1, r3
    100a:	bf08      	it	eq
    100c:	4570      	cmpeq	r0, lr
    100e:	d207      	bcs.n	1020 <CONFIG_MAIN_STACK_SIZE+0x20>
    1010:	f1bc 0f00 	cmp.w	ip, #0
    1014:	f43f ae4e 	beq.w	cb4 <cbvprintf+0x230>
    1018:	9b04      	ldr	r3, [sp, #16]
    101a:	e9cd 3e12 	strd	r3, lr, [sp, #72]	; 0x48
    101e:	e649      	b.n	cb4 <cbvprintf+0x230>
			fract <<= 1;
    1020:	9b04      	ldr	r3, [sp, #16]
			exp--;
    1022:	f04f 0c01 	mov.w	ip, #1
			fract <<= 1;
    1026:	18db      	adds	r3, r3, r3
    1028:	9304      	str	r3, [sp, #16]
    102a:	eb4e 0e0e 	adc.w	lr, lr, lr
			exp--;
    102e:	f108 38ff 	add.w	r8, r8, #4294967295
    1032:	e7e5      	b.n	1000 <CONFIG_MAIN_STACK_SIZE>
    1034:	2400      	movs	r4, #0
    1036:	46a0      	mov	r8, r4
    1038:	e640      	b.n	cbc <cbvprintf+0x238>
			c = 'f';
    103a:	2766      	movs	r7, #102	; 0x66
			precision -= decexp;
    103c:	1b2d      	subs	r5, r5, r4
    103e:	e654      	b.n	cea <cbvprintf+0x266>
	bool prune_zero = false;
    1040:	2300      	movs	r3, #0
    1042:	e65b      	b.n	cfc <cbvprintf+0x278>
		exp = precision + 1;
    1044:	1c6b      	adds	r3, r5, #1
	if (exp > 16) {
    1046:	2b10      	cmp	r3, #16
    1048:	bfa8      	it	ge
    104a:	2310      	movge	r3, #16
    104c:	4698      	mov	r8, r3
    104e:	2210      	movs	r2, #16
	uint64_t ltemp = BIT64(59);
    1050:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
    1054:	9211      	str	r2, [sp, #68]	; 0x44
    1056:	2200      	movs	r2, #0
    1058:	e9cd 2314 	strd	r2, r3, [sp, #80]	; 0x50
	while (exp--) {
    105c:	f1b8 0801 	subs.w	r8, r8, #1
    1060:	d222      	bcs.n	10a8 <CONFIG_MAIN_STACK_SIZE+0xa8>
	fract += ltemp;
    1062:	9b12      	ldr	r3, [sp, #72]	; 0x48
    1064:	9a14      	ldr	r2, [sp, #80]	; 0x50
    1066:	9915      	ldr	r1, [sp, #84]	; 0x54
    1068:	189b      	adds	r3, r3, r2
    106a:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    106c:	eb41 0202 	adc.w	r2, r1, r2
    1070:	e9cd 3212 	strd	r3, r2, [sp, #72]	; 0x48
	if ((fract >> 32) & (0x0FU << 28)) {
    1074:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
    1078:	930e      	str	r3, [sp, #56]	; 0x38
    107a:	2300      	movs	r3, #0
    107c:	930f      	str	r3, [sp, #60]	; 0x3c
    107e:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	; 0x38
    1082:	4313      	orrs	r3, r2
    1084:	d006      	beq.n	1094 <CONFIG_MAIN_STACK_SIZE+0x94>
		_ldiv5(&fract);
    1086:	a812      	add	r0, sp, #72	; 0x48
    1088:	f004 f980 	bl	538c <_ldiv5>
		_rlrshift(&fract);
    108c:	a812      	add	r0, sp, #72	; 0x48
    108e:	f004 f96c 	bl	536a <_rlrshift>
		decexp++;
    1092:	3401      	adds	r4, #1
	if (c == 'f') {
    1094:	2f66      	cmp	r7, #102	; 0x66
    1096:	d17d      	bne.n	1194 <CONFIG_MAIN_STACK_SIZE+0x194>
		if (decexp > 0) {
    1098:	2c00      	cmp	r4, #0
    109a:	dc0c      	bgt.n	10b6 <CONFIG_MAIN_STACK_SIZE+0xb6>
			*buf++ = '0';
    109c:	2330      	movs	r3, #48	; 0x30
    109e:	f10d 0865 	add.w	r8, sp, #101	; 0x65
    10a2:	f88d 3064 	strb.w	r3, [sp, #100]	; 0x64
    10a6:	e015      	b.n	10d4 <CONFIG_MAIN_STACK_SIZE+0xd4>
		_ldiv5(&ltemp);
    10a8:	a814      	add	r0, sp, #80	; 0x50
    10aa:	f004 f96f 	bl	538c <_ldiv5>
		_rlrshift(&ltemp);
    10ae:	a814      	add	r0, sp, #80	; 0x50
    10b0:	f004 f95b 	bl	536a <_rlrshift>
    10b4:	e7d2      	b.n	105c <CONFIG_MAIN_STACK_SIZE+0x5c>
	char *buf = bps;
    10b6:	f10d 0864 	add.w	r8, sp, #100	; 0x64
			while (decexp > 0 && digit_count > 0) {
    10ba:	9a11      	ldr	r2, [sp, #68]	; 0x44
    10bc:	2a00      	cmp	r2, #0
    10be:	dd07      	ble.n	10d0 <CONFIG_MAIN_STACK_SIZE+0xd0>
				*buf++ = _get_digit(&fract, &digit_count);
    10c0:	a911      	add	r1, sp, #68	; 0x44
    10c2:	a812      	add	r0, sp, #72	; 0x48
    10c4:	f004 f983 	bl	53ce <_get_digit>
			while (decexp > 0 && digit_count > 0) {
    10c8:	3c01      	subs	r4, #1
				*buf++ = _get_digit(&fract, &digit_count);
    10ca:	f808 0b01 	strb.w	r0, [r8], #1
			while (decexp > 0 && digit_count > 0) {
    10ce:	d1f4      	bne.n	10ba <CONFIG_MAIN_STACK_SIZE+0xba>
			conv->pad0_value = decexp;
    10d0:	9417      	str	r4, [sp, #92]	; 0x5c
			decexp = 0;
    10d2:	2400      	movs	r4, #0
		if (conv->flag_hash || (precision > 0)) {
    10d4:	f89d 2058 	ldrb.w	r2, [sp, #88]	; 0x58
    10d8:	0691      	lsls	r1, r2, #26
    10da:	d401      	bmi.n	10e0 <CONFIG_MAIN_STACK_SIZE+0xe0>
    10dc:	2d00      	cmp	r5, #0
    10de:	dd1b      	ble.n	1118 <CONFIG_MAIN_STACK_SIZE+0x118>
			*buf++ = '.';
    10e0:	222e      	movs	r2, #46	; 0x2e
    10e2:	f808 2b01 	strb.w	r2, [r8], #1
		if (decexp < 0 && precision > 0) {
    10e6:	b194      	cbz	r4, 110e <CONFIG_MAIN_STACK_SIZE+0x10e>
    10e8:	2d00      	cmp	r5, #0
    10ea:	dd15      	ble.n	1118 <CONFIG_MAIN_STACK_SIZE+0x118>
			conv->pad0_value = -decexp;
    10ec:	4262      	negs	r2, r4
    10ee:	42aa      	cmp	r2, r5
    10f0:	bfa8      	it	ge
    10f2:	462a      	movge	r2, r5
			conv->pad_postdp = (conv->pad0_value > 0);
    10f4:	2a00      	cmp	r2, #0
			conv->pad0_value = -decexp;
    10f6:	9217      	str	r2, [sp, #92]	; 0x5c
			precision -= conv->pad0_value;
    10f8:	eba5 0502 	sub.w	r5, r5, r2
			conv->pad_postdp = (conv->pad0_value > 0);
    10fc:	bfd4      	ite	le
    10fe:	2200      	movle	r2, #0
    1100:	2201      	movgt	r2, #1
    1102:	f89d 105a 	ldrb.w	r1, [sp, #90]	; 0x5a
    1106:	f362 1145 	bfi	r1, r2, #5, #1
    110a:	f88d 105a 	strb.w	r1, [sp, #90]	; 0x5a
	while (precision > 0 && digit_count > 0) {
    110e:	2d00      	cmp	r5, #0
    1110:	dd02      	ble.n	1118 <CONFIG_MAIN_STACK_SIZE+0x118>
    1112:	9a11      	ldr	r2, [sp, #68]	; 0x44
    1114:	2a00      	cmp	r2, #0
    1116:	dc53      	bgt.n	11c0 <CONFIG_MAIN_STACK_SIZE+0x1c0>
	if (prune_zero) {
    1118:	9b04      	ldr	r3, [sp, #16]
    111a:	2b00      	cmp	r3, #0
    111c:	d15b      	bne.n	11d6 <CONFIG_MAIN_STACK_SIZE+0x1d6>
	conv->pad0_pre_exp = precision;
    111e:	9518      	str	r5, [sp, #96]	; 0x60
	if ((c == 'e') || (c == 'E')) {
    1120:	f007 02df 	and.w	r2, r7, #223	; 0xdf
    1124:	2a45      	cmp	r2, #69	; 0x45
    1126:	d123      	bne.n	1170 <CONFIG_MAIN_STACK_SIZE+0x170>
		if (decexp < 0) {
    1128:	2c00      	cmp	r4, #0
			*buf++ = '-';
    112a:	bfb4      	ite	lt
    112c:	222d      	movlt	r2, #45	; 0x2d
			*buf++ = '+';
    112e:	222b      	movge	r2, #43	; 0x2b
		*buf++ = c;
    1130:	4641      	mov	r1, r8
			decexp = -decexp;
    1132:	bfb8      	it	lt
    1134:	4264      	neglt	r4, r4
		if (decexp >= 100) {
    1136:	2c63      	cmp	r4, #99	; 0x63
		*buf++ = c;
    1138:	f801 7b02 	strb.w	r7, [r1], #2
			*buf++ = '-';
    113c:	f888 2001 	strb.w	r2, [r8, #1]
		if (decexp >= 100) {
    1140:	dd0a      	ble.n	1158 <CONFIG_MAIN_STACK_SIZE+0x158>
			*buf++ = (decexp / 100) + '0';
    1142:	2064      	movs	r0, #100	; 0x64
    1144:	fb94 f2f0 	sdiv	r2, r4, r0
			decexp %= 100;
    1148:	fb00 4412 	mls	r4, r0, r2, r4
			*buf++ = (decexp / 100) + '0';
    114c:	f102 0530 	add.w	r5, r2, #48	; 0x30
    1150:	f108 0103 	add.w	r1, r8, #3
    1154:	f888 5002 	strb.w	r5, [r8, #2]
		*buf++ = (decexp / 10) + '0';
    1158:	200a      	movs	r0, #10
    115a:	fb94 f2f0 	sdiv	r2, r4, r0
    115e:	4688      	mov	r8, r1
		*buf++ = (decexp % 10) + '0';
    1160:	fb00 4412 	mls	r4, r0, r2, r4
		*buf++ = (decexp / 10) + '0';
    1164:	f102 0530 	add.w	r5, r2, #48	; 0x30
		*buf++ = (decexp % 10) + '0';
    1168:	3430      	adds	r4, #48	; 0x30
		*buf++ = (decexp / 10) + '0';
    116a:	f808 5b02 	strb.w	r5, [r8], #2
		*buf++ = (decexp % 10) + '0';
    116e:	704c      	strb	r4, [r1, #1]
		|| (conv->pad0_pre_exp > 0);
    1170:	9a17      	ldr	r2, [sp, #92]	; 0x5c
    1172:	2a00      	cmp	r2, #0
    1174:	dc3a      	bgt.n	11ec <CONFIG_MAIN_STACK_SIZE+0x1ec>
    1176:	9a18      	ldr	r2, [sp, #96]	; 0x60
    1178:	2a00      	cmp	r2, #0
    117a:	bfd4      	ite	le
    117c:	2200      	movle	r2, #0
    117e:	2201      	movgt	r2, #1
	conv->pad_fp = (conv->pad0_value > 0)
    1180:	f89d 105a 	ldrb.w	r1, [sp, #90]	; 0x5a
    1184:	f362 1186 	bfi	r1, r2, #6, #1
	*buf = 0;
    1188:	2200      	movs	r2, #0
	conv->pad_fp = (conv->pad0_value > 0)
    118a:	f88d 105a 	strb.w	r1, [sp, #90]	; 0x5a
	*buf = 0;
    118e:	f888 2000 	strb.w	r2, [r8]
	return bps;
    1192:	e623      	b.n	ddc <cbvprintf+0x358>
		*buf = _get_digit(&fract, &digit_count);
    1194:	a911      	add	r1, sp, #68	; 0x44
    1196:	a812      	add	r0, sp, #72	; 0x48
    1198:	f004 f919 	bl	53ce <_get_digit>
		if (conv->flag_hash || (precision > 0)) {
    119c:	f89d 3058 	ldrb.w	r3, [sp, #88]	; 0x58
		if (*buf++ != '0') {
    11a0:	2830      	cmp	r0, #48	; 0x30
			decexp--;
    11a2:	bf18      	it	ne
    11a4:	f104 34ff 	addne.w	r4, r4, #4294967295
		if (conv->flag_hash || (precision > 0)) {
    11a8:	069a      	lsls	r2, r3, #26
		*buf = _get_digit(&fract, &digit_count);
    11aa:	f88d 0064 	strb.w	r0, [sp, #100]	; 0x64
		if (conv->flag_hash || (precision > 0)) {
    11ae:	d401      	bmi.n	11b4 <CONFIG_MAIN_STACK_SIZE+0x1b4>
    11b0:	2d00      	cmp	r5, #0
    11b2:	dd0d      	ble.n	11d0 <CONFIG_MAIN_STACK_SIZE+0x1d0>
			*buf++ = '.';
    11b4:	232e      	movs	r3, #46	; 0x2e
    11b6:	f10d 0866 	add.w	r8, sp, #102	; 0x66
    11ba:	f88d 3065 	strb.w	r3, [sp, #101]	; 0x65
    11be:	e7a6      	b.n	110e <CONFIG_MAIN_STACK_SIZE+0x10e>
		*buf++ = _get_digit(&fract, &digit_count);
    11c0:	a911      	add	r1, sp, #68	; 0x44
    11c2:	a812      	add	r0, sp, #72	; 0x48
    11c4:	f004 f903 	bl	53ce <_get_digit>
		precision--;
    11c8:	3d01      	subs	r5, #1
		*buf++ = _get_digit(&fract, &digit_count);
    11ca:	f808 0b01 	strb.w	r0, [r8], #1
		precision--;
    11ce:	e79e      	b.n	110e <CONFIG_MAIN_STACK_SIZE+0x10e>
		if (*buf++ != '0') {
    11d0:	f10d 0865 	add.w	r8, sp, #101	; 0x65
    11d4:	e7a0      	b.n	1118 <CONFIG_MAIN_STACK_SIZE+0x118>
		conv->pad0_pre_exp = 0;
    11d6:	2200      	movs	r2, #0
    11d8:	9218      	str	r2, [sp, #96]	; 0x60
		while (*--buf == '0') {
    11da:	4641      	mov	r1, r8
    11dc:	f818 2d01 	ldrb.w	r2, [r8, #-1]!
    11e0:	2a30      	cmp	r2, #48	; 0x30
    11e2:	d0fa      	beq.n	11da <CONFIG_MAIN_STACK_SIZE+0x1da>
		if (*buf != '.') {
    11e4:	2a2e      	cmp	r2, #46	; 0x2e
    11e6:	bf18      	it	ne
    11e8:	4688      	movne	r8, r1
    11ea:	e799      	b.n	1120 <CONFIG_MAIN_STACK_SIZE+0x120>
		|| (conv->pad0_pre_exp > 0);
    11ec:	2201      	movs	r2, #1
    11ee:	e7c7      	b.n	1180 <CONFIG_MAIN_STACK_SIZE+0x180>
			bpe = bps + 5;
    11f0:	f8df 81d8 	ldr.w	r8, [pc, #472]	; 13cc <CONFIG_MAIN_STACK_SIZE+0x3cc>
		char sign = 0;
    11f4:	4606      	mov	r6, r0
			bps = "(nil)";
    11f6:	f1a8 0405 	sub.w	r4, r8, #5
    11fa:	e5f0      	b.n	dde <cbvprintf+0x35a>
		} else if (conv.altform_0) {
    11fc:	070d      	lsls	r5, r1, #28
			nj_len += 1U;
    11fe:	bf48      	it	mi
    1200:	3701      	addmi	r7, #1
    1202:	e5f6      	b.n	df2 <cbvprintf+0x36e>
					OUTC(pad);
    1204:	4651      	mov	r1, sl
    1206:	4628      	mov	r0, r5
    1208:	9b03      	ldr	r3, [sp, #12]
    120a:	4798      	blx	r3
    120c:	2800      	cmp	r0, #0
    120e:	f6ff add0 	blt.w	db2 <cbvprintf+0x32e>
    1212:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    1214:	eba7 0903 	sub.w	r9, r7, r3
				while (width-- > 0) {
    1218:	2b00      	cmp	r3, #0
    121a:	f103 33ff 	add.w	r3, r3, #4294967295
    121e:	930a      	str	r3, [sp, #40]	; 0x28
    1220:	dcf0      	bgt.n	1204 <CONFIG_MAIN_STACK_SIZE+0x204>
		if (sign != 0) {
    1222:	b146      	cbz	r6, 1236 <CONFIG_MAIN_STACK_SIZE+0x236>
			OUTC(sign);
    1224:	4651      	mov	r1, sl
    1226:	4630      	mov	r0, r6
    1228:	9b03      	ldr	r3, [sp, #12]
    122a:	4798      	blx	r3
    122c:	2800      	cmp	r0, #0
    122e:	f6ff adc0 	blt.w	db2 <cbvprintf+0x32e>
    1232:	f109 0901 	add.w	r9, r9, #1
		if (IS_ENABLED(CONFIG_CBPRINTF_FP_SUPPORT) && conv.pad_fp) {
    1236:	f89d 205a 	ldrb.w	r2, [sp, #90]	; 0x5a
    123a:	0655      	lsls	r5, r2, #25
    123c:	f140 8081 	bpl.w	1342 <CONFIG_MAIN_STACK_SIZE+0x342>
			if (conv.specifier_a) {
    1240:	f99d 2059 	ldrsb.w	r2, [sp, #89]	; 0x59
    1244:	2a00      	cmp	r2, #0
    1246:	db2d      	blt.n	12a4 <CONFIG_MAIN_STACK_SIZE+0x2a4>
    1248:	eba9 0904 	sub.w	r9, r9, r4
				while (isdigit((int)*cp)) {
    124c:	7820      	ldrb	r0, [r4, #0]
    124e:	4625      	mov	r5, r4
    1250:	f1a0 0230 	sub.w	r2, r0, #48	; 0x30
    1254:	2a09      	cmp	r2, #9
    1256:	eb09 0604 	add.w	r6, r9, r4
    125a:	f104 0401 	add.w	r4, r4, #1
    125e:	d945      	bls.n	12ec <CONFIG_MAIN_STACK_SIZE+0x2ec>
				if (!conv.pad_postdp) {
    1260:	f89d 205a 	ldrb.w	r2, [sp, #90]	; 0x5a
				pad_len = conv.pad0_value;
    1264:	9c17      	ldr	r4, [sp, #92]	; 0x5c
				if (!conv.pad_postdp) {
    1266:	0690      	lsls	r0, r2, #26
    1268:	d406      	bmi.n	1278 <CONFIG_MAIN_STACK_SIZE+0x278>
    126a:	19a7      	adds	r7, r4, r6
					while (pad_len-- > 0) {
    126c:	2c00      	cmp	r4, #0
    126e:	eba7 0604 	sub.w	r6, r7, r4
    1272:	f104 34ff 	add.w	r4, r4, #4294967295
    1276:	dc3f      	bgt.n	12f8 <CONFIG_MAIN_STACK_SIZE+0x2f8>
				if (*cp == '.') {
    1278:	7828      	ldrb	r0, [r5, #0]
    127a:	282e      	cmp	r0, #46	; 0x2e
    127c:	d10a      	bne.n	1294 <CONFIG_MAIN_STACK_SIZE+0x294>
					OUTC(*cp++);
    127e:	4651      	mov	r1, sl
    1280:	9b03      	ldr	r3, [sp, #12]
    1282:	4798      	blx	r3
						OUTC('0');
    1284:	2800      	cmp	r0, #0
    1286:	f6ff ad94 	blt.w	db2 <cbvprintf+0x32e>
					while (pad_len-- > 0) {
    128a:	2c00      	cmp	r4, #0
						OUTC('0');
    128c:	f106 0601 	add.w	r6, r6, #1
					while (pad_len-- > 0) {
    1290:	dc39      	bgt.n	1306 <CONFIG_MAIN_STACK_SIZE+0x306>
					OUTC(*cp++);
    1292:	3501      	adds	r5, #1
    1294:	1b76      	subs	r6, r6, r5
    1296:	e042      	b.n	131e <CONFIG_MAIN_STACK_SIZE+0x31e>
				char pad = ' ';
    1298:	2520      	movs	r5, #32
					pad = '0';
    129a:	970a      	str	r7, [sp, #40]	; 0x28
    129c:	444f      	add	r7, r9
    129e:	e7b8      	b.n	1212 <CONFIG_MAIN_STACK_SIZE+0x212>
			width -= (int)nj_len;
    12a0:	970a      	str	r7, [sp, #40]	; 0x28
    12a2:	e7be      	b.n	1222 <CONFIG_MAIN_STACK_SIZE+0x222>
			if (conv.specifier_a) {
    12a4:	4625      	mov	r5, r4
    12a6:	eba9 0904 	sub.w	r9, r9, r4
    12aa:	462f      	mov	r7, r5
    12ac:	eb09 0405 	add.w	r4, r9, r5
				while (*cp != 'p') {
    12b0:	f815 0b01 	ldrb.w	r0, [r5], #1
    12b4:	2870      	cmp	r0, #112	; 0x70
    12b6:	d113      	bne.n	12e0 <CONFIG_MAIN_STACK_SIZE+0x2e0>
			while (pad_len-- > 0) {
    12b8:	9d18      	ldr	r5, [sp, #96]	; 0x60
    12ba:	4425      	add	r5, r4
    12bc:	1b2a      	subs	r2, r5, r4
    12be:	2a00      	cmp	r2, #0
    12c0:	dc36      	bgt.n	1330 <CONFIG_MAIN_STACK_SIZE+0x330>
			OUTS(cp, bpe);
    12c2:	4643      	mov	r3, r8
    12c4:	463a      	mov	r2, r7
    12c6:	4651      	mov	r1, sl
    12c8:	9803      	ldr	r0, [sp, #12]
    12ca:	f004 f8e2 	bl	5492 <outs>
    12ce:	2800      	cmp	r0, #0
    12d0:	f6ff ad6f 	blt.w	db2 <cbvprintf+0x32e>
    12d4:	4420      	add	r0, r4
    12d6:	9b0a      	ldr	r3, [sp, #40]	; 0x28
			while (pad_len-- > 0) {
    12d8:	4681      	mov	r9, r0
    12da:	4403      	add	r3, r0
    12dc:	461d      	mov	r5, r3
    12de:	e06f      	b.n	13c0 <CONFIG_MAIN_STACK_SIZE+0x3c0>
					OUTC(*cp++);
    12e0:	4651      	mov	r1, sl
    12e2:	9b03      	ldr	r3, [sp, #12]
    12e4:	4798      	blx	r3
    12e6:	2800      	cmp	r0, #0
    12e8:	dadf      	bge.n	12aa <CONFIG_MAIN_STACK_SIZE+0x2aa>
    12ea:	e562      	b.n	db2 <cbvprintf+0x32e>
					OUTC(*cp++);
    12ec:	4651      	mov	r1, sl
    12ee:	9b03      	ldr	r3, [sp, #12]
    12f0:	4798      	blx	r3
    12f2:	2800      	cmp	r0, #0
    12f4:	daaa      	bge.n	124c <CONFIG_MAIN_STACK_SIZE+0x24c>
    12f6:	e55c      	b.n	db2 <cbvprintf+0x32e>
						OUTC('0');
    12f8:	4651      	mov	r1, sl
    12fa:	2030      	movs	r0, #48	; 0x30
    12fc:	9b03      	ldr	r3, [sp, #12]
    12fe:	4798      	blx	r3
    1300:	2800      	cmp	r0, #0
    1302:	dab3      	bge.n	126c <CONFIG_MAIN_STACK_SIZE+0x26c>
    1304:	e555      	b.n	db2 <cbvprintf+0x32e>
						OUTC('0');
    1306:	4651      	mov	r1, sl
    1308:	2030      	movs	r0, #48	; 0x30
    130a:	9b03      	ldr	r3, [sp, #12]
    130c:	4798      	blx	r3
    130e:	3c01      	subs	r4, #1
    1310:	e7b8      	b.n	1284 <CONFIG_MAIN_STACK_SIZE+0x284>
					OUTC(*cp++);
    1312:	4651      	mov	r1, sl
    1314:	9b03      	ldr	r3, [sp, #12]
    1316:	4798      	blx	r3
    1318:	2800      	cmp	r0, #0
    131a:	f6ff ad4a 	blt.w	db2 <cbvprintf+0x32e>
    131e:	462f      	mov	r7, r5
    1320:	1974      	adds	r4, r6, r5
				while (isdigit((int)*cp)) {
    1322:	f815 0b01 	ldrb.w	r0, [r5], #1
    1326:	f1a0 0230 	sub.w	r2, r0, #48	; 0x30
    132a:	2a09      	cmp	r2, #9
    132c:	d9f1      	bls.n	1312 <CONFIG_MAIN_STACK_SIZE+0x312>
    132e:	e7c3      	b.n	12b8 <CONFIG_MAIN_STACK_SIZE+0x2b8>
				OUTC('0');
    1330:	4651      	mov	r1, sl
    1332:	2030      	movs	r0, #48	; 0x30
    1334:	9b03      	ldr	r3, [sp, #12]
    1336:	4798      	blx	r3
    1338:	2800      	cmp	r0, #0
    133a:	f6ff ad3a 	blt.w	db2 <cbvprintf+0x32e>
    133e:	3401      	adds	r4, #1
    1340:	e7bc      	b.n	12bc <CONFIG_MAIN_STACK_SIZE+0x2bc>
			if (conv.altform_0c | conv.altform_0) {
    1342:	06d1      	lsls	r1, r2, #27
    1344:	d401      	bmi.n	134a <CONFIG_MAIN_STACK_SIZE+0x34a>
    1346:	0712      	lsls	r2, r2, #28
    1348:	d508      	bpl.n	135c <CONFIG_MAIN_STACK_SIZE+0x35c>
				OUTC('0');
    134a:	4651      	mov	r1, sl
    134c:	2030      	movs	r0, #48	; 0x30
    134e:	9b03      	ldr	r3, [sp, #12]
    1350:	4798      	blx	r3
    1352:	2800      	cmp	r0, #0
    1354:	f6ff ad2d 	blt.w	db2 <cbvprintf+0x32e>
    1358:	f109 0901 	add.w	r9, r9, #1
			if (conv.altform_0c) {
    135c:	f89d 205a 	ldrb.w	r2, [sp, #90]	; 0x5a
    1360:	06d3      	lsls	r3, r2, #27
    1362:	d509      	bpl.n	1378 <CONFIG_MAIN_STACK_SIZE+0x378>
				OUTC(conv.specifier);
    1364:	4651      	mov	r1, sl
    1366:	f89d 005b 	ldrb.w	r0, [sp, #91]	; 0x5b
    136a:	9b03      	ldr	r3, [sp, #12]
    136c:	4798      	blx	r3
    136e:	2800      	cmp	r0, #0
    1370:	f6ff ad1f 	blt.w	db2 <cbvprintf+0x32e>
    1374:	f109 0901 	add.w	r9, r9, #1
			while (pad_len-- > 0) {
    1378:	9d17      	ldr	r5, [sp, #92]	; 0x5c
    137a:	444d      	add	r5, r9
    137c:	eba5 0209 	sub.w	r2, r5, r9
    1380:	2a00      	cmp	r2, #0
    1382:	dc0a      	bgt.n	139a <CONFIG_MAIN_STACK_SIZE+0x39a>
			OUTS(bps, bpe);
    1384:	4643      	mov	r3, r8
    1386:	4622      	mov	r2, r4
    1388:	4651      	mov	r1, sl
    138a:	9803      	ldr	r0, [sp, #12]
    138c:	f004 f881 	bl	5492 <outs>
    1390:	2800      	cmp	r0, #0
    1392:	f6ff ad0e 	blt.w	db2 <cbvprintf+0x32e>
    1396:	4448      	add	r0, r9
    1398:	e79d      	b.n	12d6 <CONFIG_MAIN_STACK_SIZE+0x2d6>
				OUTC('0');
    139a:	4651      	mov	r1, sl
    139c:	2030      	movs	r0, #48	; 0x30
    139e:	9b03      	ldr	r3, [sp, #12]
    13a0:	4798      	blx	r3
    13a2:	2800      	cmp	r0, #0
    13a4:	f6ff ad05 	blt.w	db2 <cbvprintf+0x32e>
    13a8:	f109 0901 	add.w	r9, r9, #1
    13ac:	e7e6      	b.n	137c <CONFIG_MAIN_STACK_SIZE+0x37c>
			OUTC(' ');
    13ae:	4651      	mov	r1, sl
    13b0:	2020      	movs	r0, #32
    13b2:	9b03      	ldr	r3, [sp, #12]
    13b4:	4798      	blx	r3
    13b6:	2800      	cmp	r0, #0
    13b8:	f6ff acfb 	blt.w	db2 <cbvprintf+0x32e>
    13bc:	f109 0901 	add.w	r9, r9, #1
		while (width > 0) {
    13c0:	eba5 0309 	sub.w	r3, r5, r9
    13c4:	2b00      	cmp	r3, #0
    13c6:	dcf2      	bgt.n	13ae <CONFIG_MAIN_STACK_SIZE+0x3ae>
    13c8:	f7ff bbde 	b.w	b88 <cbvprintf+0x104>
    13cc:	00006146 	.word	0x00006146

000013d0 <nordicsemi_nrf91_init>:
    13d0:	f04f 0220 	mov.w	r2, #32
    13d4:	f3ef 8311 	mrs	r3, BASEPRI
    13d8:	f382 8811 	msr	BASEPRI, r2
    13dc:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    13e0:	2101      	movs	r1, #1
    13e2:	4a04      	ldr	r2, [pc, #16]	; (13f4 <nordicsemi_nrf91_init+0x24>)
    13e4:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
	__asm__ volatile(
    13e8:	f383 8811 	msr	BASEPRI, r3
    13ec:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    13f0:	2000      	movs	r0, #0
    13f2:	4770      	bx	lr
    13f4:	50039000 	.word	0x50039000

000013f8 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    13f8:	b120      	cbz	r0, 1404 <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    13fa:	4b03      	ldr	r3, [pc, #12]	; (1408 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    13fc:	0180      	lsls	r0, r0, #6
    13fe:	f043 0301 	orr.w	r3, r3, #1
    1402:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    1404:	4770      	bx	lr
    1406:	bf00      	nop
    1408:	00005ea0 	.word	0x00005ea0

0000140c <sys_reboot>:

extern void sys_arch_reboot(int type);
extern void sys_clock_disable(void);

void sys_reboot(int type)
{
    140c:	b507      	push	{r0, r1, r2, lr}
    140e:	9001      	str	r0, [sp, #4]
	__asm__ volatile(
    1410:	f04f 0220 	mov.w	r2, #32
    1414:	f3ef 8311 	mrs	r3, BASEPRI
    1418:	f382 8811 	msr	BASEPRI, r2
    141c:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
#ifdef CONFIG_SYS_CLOCK_EXISTS
	sys_clock_disable();
    1420:	f004 f8ea 	bl	55f8 <sys_clock_disable>
#endif

	sys_arch_reboot(type);
    1424:	9801      	ldr	r0, [sp, #4]
    1426:	f001 f805 	bl	2434 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
    142a:	4803      	ldr	r0, [pc, #12]	; (1438 <sys_reboot+0x2c>)
    142c:	f003 fdfe 	bl	502c <printk>
 *
 * @return N/A
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
    1430:	f000 fe40 	bl	20b4 <arch_cpu_idle>
    1434:	e7fc      	b.n	1430 <sys_reboot+0x24>
    1436:	bf00      	nop
    1438:	00006147 	.word	0x00006147

0000143c <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    143c:	b508      	push	{r3, lr}
	if (z_syscall_trap()) {
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
    143e:	4806      	ldr	r0, [pc, #24]	; (1458 <uart_console_init+0x1c>)
    1440:	f001 fe5e 	bl	3100 <z_impl_device_get_binding>

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
    1444:	4b05      	ldr	r3, [pc, #20]	; (145c <uart_console_init+0x20>)
    1446:	6018      	str	r0, [r3, #0]
	__stdout_hook_install(console_out);
    1448:	4805      	ldr	r0, [pc, #20]	; (1460 <uart_console_init+0x24>)
    144a:	f001 fa57 	bl	28fc <__stdout_hook_install>
	__printk_hook_install(console_out);
    144e:	4804      	ldr	r0, [pc, #16]	; (1460 <uart_console_init+0x24>)
    1450:	f7ff f8a4 	bl	59c <__printk_hook_install>

	uart_console_hook_install();

	return 0;
}
    1454:	2000      	movs	r0, #0
    1456:	bd08      	pop	{r3, pc}
    1458:	00006170 	.word	0x00006170
    145c:	20000260 	.word	0x20000260
    1460:	00001465 	.word	0x00001465

00001464 <console_out>:
	if ('\n' == c) {
    1464:	280a      	cmp	r0, #10
{
    1466:	b538      	push	{r3, r4, r5, lr}
    1468:	4604      	mov	r4, r0
    146a:	4d07      	ldr	r5, [pc, #28]	; (1488 <console_out+0x24>)
	if ('\n' == c) {
    146c:	d104      	bne.n	1478 <console_out+0x14>
    146e:	6828      	ldr	r0, [r5, #0]
						unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    1470:	6883      	ldr	r3, [r0, #8]
    1472:	210d      	movs	r1, #13
    1474:	685b      	ldr	r3, [r3, #4]
    1476:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
    1478:	6828      	ldr	r0, [r5, #0]
    147a:	6883      	ldr	r3, [r0, #8]
    147c:	b2e1      	uxtb	r1, r4
    147e:	685b      	ldr	r3, [r3, #4]
    1480:	4798      	blx	r3
}
    1482:	4620      	mov	r0, r4
    1484:	bd38      	pop	{r3, r4, r5, pc}
    1486:	bf00      	nop
    1488:	20000260 	.word	0x20000260

0000148c <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = DEVICE_GET(clock_nrf)->data;
	size_t offset = (size_t)(mgr - data->mgr);
    148c:	4a0e      	ldr	r2, [pc, #56]	; (14c8 <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    148e:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1490:	1a84      	subs	r4, r0, r2
{
    1492:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    1494:	200c      	movs	r0, #12
{
    1496:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
    1498:	2140      	movs	r1, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    149a:	10a3      	asrs	r3, r4, #2
    149c:	4c0b      	ldr	r4, [pc, #44]	; (14cc <onoff_stop+0x40>)
    149e:	435c      	muls	r4, r3
    14a0:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
    14a2:	fb00 2004 	mla	r0, r0, r4, r2
    14a6:	4408      	add	r0, r1
    14a8:	f004 f818 	bl	54dc <set_off_state>
	if (err < 0) {
    14ac:	1e01      	subs	r1, r0, #0
    14ae:	db05      	blt.n	14bc <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
    14b0:	4b07      	ldr	r3, [pc, #28]	; (14d0 <onoff_stop+0x44>)
    14b2:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    14b6:	6863      	ldr	r3, [r4, #4]
    14b8:	4798      	blx	r3
	return 0;
    14ba:	2100      	movs	r1, #0
	int res;

	res = stop(DEVICE_GET(clock_nrf), get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
    14bc:	4628      	mov	r0, r5
    14be:	4633      	mov	r3, r6
}
    14c0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    14c4:	4718      	bx	r3
    14c6:	bf00      	nop
    14c8:	20000274 	.word	0x20000274
    14cc:	b6db6db7 	.word	0xb6db6db7
    14d0:	00005ebc 	.word	0x00005ebc

000014d4 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    14d4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
    14d8:	250c      	movs	r5, #12
	size_t offset = (size_t)(mgr - data->mgr);
    14da:	4e10      	ldr	r6, [pc, #64]	; (151c <onoff_start+0x48>)
{
    14dc:	4680      	mov	r8, r0
	size_t offset = (size_t)(mgr - data->mgr);
    14de:	1b84      	subs	r4, r0, r6
    14e0:	10a3      	asrs	r3, r4, #2
    14e2:	4c0f      	ldr	r4, [pc, #60]	; (1520 <onoff_start+0x4c>)
{
    14e4:	460f      	mov	r7, r1
	size_t offset = (size_t)(mgr - data->mgr);
    14e6:	435c      	muls	r4, r3
    14e8:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
    14ea:	4365      	muls	r5, r4
    14ec:	f105 0040 	add.w	r0, r5, #64	; 0x40
    14f0:	2140      	movs	r1, #64	; 0x40
    14f2:	4430      	add	r0, r6
    14f4:	f004 f80b 	bl	550e <set_starting_state>
	if (err < 0) {
    14f8:	1e01      	subs	r1, r0, #0
    14fa:	db09      	blt.n	1510 <onoff_start+0x3c>
	subdata->cb = cb;
    14fc:	4a09      	ldr	r2, [pc, #36]	; (1524 <onoff_start+0x50>)
    14fe:	1973      	adds	r3, r6, r5
	subdata->user_data = user_data;
    1500:	e9c3 270e 	strd	r2, r7, [r3, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    1504:	4b08      	ldr	r3, [pc, #32]	; (1528 <onoff_start+0x54>)
    1506:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(DEVICE_GET(clock_nrf), get_subsys(mgr),
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
    150a:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
    150e:	4718      	bx	r3
		notify(mgr, err);
    1510:	4640      	mov	r0, r8
    1512:	463b      	mov	r3, r7
}
    1514:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
    1518:	4718      	bx	r3
    151a:	bf00      	nop
    151c:	20000274 	.word	0x20000274
    1520:	b6db6db7 	.word	0xb6db6db7
    1524:	00005571 	.word	0x00005571
    1528:	00005ebc 	.word	0x00005ebc

0000152c <clk_init>:
		break;
	}
}

static int clk_init(const struct device *dev)
{
    152c:	b570      	push	{r4, r5, r6, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    152e:	2200      	movs	r2, #0
    1530:	2101      	movs	r1, #1
{
    1532:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1534:	2005      	movs	r0, #5
    1536:	f000 fd67 	bl	2008 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    153a:	2005      	movs	r0, #5
    153c:	f000 fd46 	bl	1fcc <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1540:	480f      	ldr	r0, [pc, #60]	; (1580 <clk_init+0x54>)
    1542:	f001 fcc9 	bl	2ed8 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1546:	4b0f      	ldr	r3, [pc, #60]	; (1584 <clk_init+0x58>)
    1548:	4298      	cmp	r0, r3
    154a:	d115      	bne.n	1578 <clk_init+0x4c>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    154c:	f004 f9f9 	bl	5942 <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
    1550:	68e6      	ldr	r6, [r4, #12]

		err = onoff_manager_init(get_onoff_manager(dev, i),
    1552:	490d      	ldr	r1, [pc, #52]	; (1588 <clk_init+0x5c>)
    1554:	4630      	mov	r0, r6
    1556:	f003 fdc6 	bl	50e6 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    155a:	2800      	cmp	r0, #0
    155c:	db0b      	blt.n	1576 <clk_init+0x4a>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    155e:	2501      	movs	r5, #1
    1560:	6435      	str	r5, [r6, #64]	; 0x40
						get_sub_data(dev, i);
    1562:	68e4      	ldr	r4, [r4, #12]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1564:	4908      	ldr	r1, [pc, #32]	; (1588 <clk_init+0x5c>)
    1566:	f104 001c 	add.w	r0, r4, #28
    156a:	f003 fdbc 	bl	50e6 <onoff_manager_init>
		if (err < 0) {
    156e:	2800      	cmp	r0, #0
    1570:	db01      	blt.n	1576 <clk_init+0x4a>
	}

	return 0;
    1572:	2000      	movs	r0, #0
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1574:	64e5      	str	r5, [r4, #76]	; 0x4c
}
    1576:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    1578:	f06f 0004 	mvn.w	r0, #4
    157c:	e7fb      	b.n	1576 <clk_init+0x4a>
    157e:	bf00      	nop
    1580:	000015c9 	.word	0x000015c9
    1584:	0bad0000 	.word	0x0bad0000
    1588:	00005ecc 	.word	0x00005ecc

0000158c <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    158c:	b573      	push	{r0, r1, r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    158e:	230c      	movs	r3, #12
static void clkstarted_handle(const struct device *dev,
    1590:	4601      	mov	r1, r0
	sub_data->cb = NULL;
    1592:	2600      	movs	r6, #0
	clock_control_cb_t callback = sub_data->cb;
    1594:	434b      	muls	r3, r1
    1596:	480a      	ldr	r0, [pc, #40]	; (15c0 <clkstarted_handle.constprop.0+0x34>)
    1598:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
    159a:	3340      	adds	r3, #64	; 0x40
	void *user_data = sub_data->user_data;
    159c:	e9d4 520e 	ldrd	r5, r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    15a0:	4418      	add	r0, r3
	sub_data->cb = NULL;
    15a2:	63a6      	str	r6, [r4, #56]	; 0x38
	void *user_data = sub_data->user_data;
    15a4:	9201      	str	r2, [sp, #4]
	set_on_state(&sub_data->flags);
    15a6:	f003 ffd0 	bl	554a <set_on_state>
	if (callback) {
    15aa:	b135      	cbz	r5, 15ba <clkstarted_handle.constprop.0+0x2e>
		callback(dev, (clock_control_subsys_t)type, user_data);
    15ac:	462b      	mov	r3, r5
    15ae:	9a01      	ldr	r2, [sp, #4]
    15b0:	4804      	ldr	r0, [pc, #16]	; (15c4 <clkstarted_handle.constprop.0+0x38>)
}
    15b2:	b002      	add	sp, #8
    15b4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    15b8:	4718      	bx	r3
}
    15ba:	b002      	add	sp, #8
    15bc:	bd70      	pop	{r4, r5, r6, pc}
    15be:	bf00      	nop
    15c0:	20000274 	.word	0x20000274
    15c4:	200000b4 	.word	0x200000b4

000015c8 <clock_event_handler>:
	switch (event) {
    15c8:	b110      	cbz	r0, 15d0 <clock_event_handler+0x8>
    15ca:	2801      	cmp	r0, #1
    15cc:	d004      	beq.n	15d8 <clock_event_handler+0x10>
    15ce:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    15d0:	4b03      	ldr	r3, [pc, #12]	; (15e0 <clock_event_handler+0x18>)
    15d2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    15d4:	075b      	lsls	r3, r3, #29
    15d6:	d101      	bne.n	15dc <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    15d8:	f7ff bfd8 	b.w	158c <clkstarted_handle.constprop.0>
}
    15dc:	4770      	bx	lr
    15de:	bf00      	nop
    15e0:	20000274 	.word	0x20000274

000015e4 <generic_hfclk_start>:
{
    15e4:	b508      	push	{r3, lr}
    15e6:	f04f 0320 	mov.w	r3, #32
    15ea:	f3ef 8111 	mrs	r1, BASEPRI
    15ee:	f383 8811 	msr	BASEPRI, r3
    15f2:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    15f6:	4a12      	ldr	r2, [pc, #72]	; (1640 <generic_hfclk_start+0x5c>)
    15f8:	6813      	ldr	r3, [r2, #0]
    15fa:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    15fe:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    1602:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1604:	d00c      	beq.n	1620 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    1606:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    160a:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    160e:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1612:	f013 0301 	ands.w	r3, r3, #1
    1616:	d003      	beq.n	1620 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    1618:	480a      	ldr	r0, [pc, #40]	; (1644 <generic_hfclk_start+0x60>)
    161a:	f003 ff96 	bl	554a <set_on_state>
			already_started = true;
    161e:	2301      	movs	r3, #1
	__asm__ volatile(
    1620:	f381 8811 	msr	BASEPRI, r1
    1624:	f3bf 8f6f 	isb	sy
	if (already_started) {
    1628:	b123      	cbz	r3, 1634 <generic_hfclk_start+0x50>
}
    162a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(DEVICE_GET(clock_nrf),
    162e:	2000      	movs	r0, #0
    1630:	f7ff bfac 	b.w	158c <clkstarted_handle.constprop.0>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    1634:	2001      	movs	r0, #1
}
    1636:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    163a:	f001 bc5d 	b.w	2ef8 <nrfx_clock_start>
    163e:	bf00      	nop
    1640:	200002c4 	.word	0x200002c4
    1644:	200002b4 	.word	0x200002b4

00001648 <generic_hfclk_stop>:
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    1648:	4b07      	ldr	r3, [pc, #28]	; (1668 <generic_hfclk_stop+0x20>)
    164a:	e8d3 2fef 	ldaex	r2, [r3]
    164e:	f022 0102 	bic.w	r1, r2, #2
    1652:	e8c3 1fe0 	stlex	r0, r1, [r3]
    1656:	2800      	cmp	r0, #0
    1658:	d1f7      	bne.n	164a <generic_hfclk_stop+0x2>
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    165a:	07d3      	lsls	r3, r2, #31
    165c:	d402      	bmi.n	1664 <generic_hfclk_stop+0x1c>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    165e:	2001      	movs	r0, #1
    1660:	f001 bc7c 	b.w	2f5c <nrfx_clock_stop>
}
    1664:	4770      	bx	lr
    1666:	bf00      	nop
    1668:	200002c4 	.word	0x200002c4

0000166c <api_blocking_start>:
{
    166c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    166e:	2200      	movs	r2, #0
    1670:	2301      	movs	r3, #1
    1672:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1676:	466b      	mov	r3, sp
    1678:	4a08      	ldr	r2, [pc, #32]	; (169c <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    167a:	f8cd d000 	str.w	sp, [sp]
    167e:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1682:	f003 ff9c 	bl	55be <api_start>
	if (err < 0) {
    1686:	2800      	cmp	r0, #0
    1688:	db05      	blt.n	1696 <api_blocking_start+0x2a>
		parm0.val = timeout;
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    168a:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    168e:	2300      	movs	r3, #0
    1690:	4668      	mov	r0, sp
    1692:	f002 fb53 	bl	3d3c <z_impl_k_sem_take>
}
    1696:	b005      	add	sp, #20
    1698:	f85d fb04 	ldr.w	pc, [sp], #4
    169c:	00005585 	.word	0x00005585

000016a0 <z_nrf_clock_control_lf_on>:
{
    16a0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    16a4:	2201      	movs	r2, #1
    16a6:	4606      	mov	r6, r0
    16a8:	4939      	ldr	r1, [pc, #228]	; (1790 <z_nrf_clock_control_lf_on+0xf0>)
    16aa:	e8d1 3fef 	ldaex	r3, [r1]
    16ae:	e8c1 2fe0 	stlex	r0, r2, [r1]
    16b2:	2800      	cmp	r0, #0
    16b4:	d1f9      	bne.n	16aa <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
    16b6:	b933      	cbnz	r3, 16c6 <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    16b8:	4936      	ldr	r1, [pc, #216]	; (1794 <z_nrf_clock_control_lf_on+0xf4>)
		err = onoff_request(mgr, &cli);
    16ba:	4837      	ldr	r0, [pc, #220]	; (1798 <z_nrf_clock_control_lf_on+0xf8>)
    16bc:	604b      	str	r3, [r1, #4]
    16be:	60cb      	str	r3, [r1, #12]
    16c0:	608a      	str	r2, [r1, #8]
    16c2:	f003 fd23 	bl	510c <onoff_request>
	switch (start_mode) {
    16c6:	1e73      	subs	r3, r6, #1
    16c8:	2b01      	cmp	r3, #1
    16ca:	d832      	bhi.n	1732 <z_nrf_clock_control_lf_on+0x92>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    16cc:	2e01      	cmp	r6, #1
    16ce:	d107      	bne.n	16e0 <z_nrf_clock_control_lf_on+0x40>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    16d0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    16d4:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    16d8:	f003 0303 	and.w	r3, r3, #3
    16dc:	2b02      	cmp	r3, #2
    16de:	d028      	beq.n	1732 <z_nrf_clock_control_lf_on+0x92>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    16e0:	f004 fa26 	bl	5b30 <k_is_in_isr>
    16e4:	4604      	mov	r4, r0
    16e6:	b918      	cbnz	r0, 16f0 <z_nrf_clock_control_lf_on+0x50>
	return !z_sys_post_kernel;
    16e8:	4b2c      	ldr	r3, [pc, #176]	; (179c <z_nrf_clock_control_lf_on+0xfc>)
	int key = isr_mode ? irq_lock() : 0;
    16ea:	781b      	ldrb	r3, [r3, #0]
    16ec:	2b00      	cmp	r3, #0
    16ee:	d147      	bne.n	1780 <z_nrf_clock_control_lf_on+0xe0>
	__asm__ volatile(
    16f0:	f04f 0320 	mov.w	r3, #32
    16f4:	f3ef 8511 	mrs	r5, BASEPRI
    16f8:	f383 8811 	msr	BASEPRI, r3
    16fc:	f3bf 8f6f 	isb	sy
    1700:	2401      	movs	r4, #1
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1702:	4f27      	ldr	r7, [pc, #156]	; (17a0 <z_nrf_clock_control_lf_on+0x100>)
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1704:	f8df 809c 	ldr.w	r8, [pc, #156]	; 17a4 <z_nrf_clock_control_lf_on+0x104>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1708:	f8df 909c 	ldr.w	r9, [pc, #156]	; 17a8 <z_nrf_clock_control_lf_on+0x108>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    170c:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    1710:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1714:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    1718:	03d2      	lsls	r2, r2, #15
    171a:	d50c      	bpl.n	1736 <z_nrf_clock_control_lf_on+0x96>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    171c:	f003 0303 	and.w	r3, r3, #3
    1720:	2b02      	cmp	r3, #2
    1722:	d001      	beq.n	1728 <z_nrf_clock_control_lf_on+0x88>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1724:	2e01      	cmp	r6, #1
    1726:	d106      	bne.n	1736 <z_nrf_clock_control_lf_on+0x96>
	if (isr_mode) {
    1728:	b324      	cbz	r4, 1774 <z_nrf_clock_control_lf_on+0xd4>
	__asm__ volatile(
    172a:	f385 8811 	msr	BASEPRI, r5
    172e:	f3bf 8f6f 	isb	sy
}
    1732:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode) {
    1736:	b1c4      	cbz	r4, 176a <z_nrf_clock_control_lf_on+0xca>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1738:	4628      	mov	r0, r5
    173a:	f000 fcc9 	bl	20d0 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    173e:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    1742:	f8d2 3518 	ldr.w	r3, [r2, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    1746:	b2db      	uxtb	r3, r3
    1748:	2b01      	cmp	r3, #1
    174a:	d1df      	bne.n	170c <z_nrf_clock_control_lf_on+0x6c>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    174c:	6839      	ldr	r1, [r7, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
    174e:	2900      	cmp	r1, #0
    1750:	d0dc      	beq.n	170c <z_nrf_clock_control_lf_on+0x6c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1752:	2100      	movs	r1, #0
    1754:	6039      	str	r1, [r7, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1756:	6839      	ldr	r1, [r7, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
    1758:	2102      	movs	r1, #2
    175a:	f8c2 1518 	str.w	r1, [r2, #1304]	; 0x518
    175e:	2220      	movs	r2, #32
    1760:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1764:	f8c9 3000 	str.w	r3, [r9]
}
    1768:	e7d0      	b.n	170c <z_nrf_clock_control_lf_on+0x6c>
	return z_impl_k_sleep(timeout);
    176a:	2100      	movs	r1, #0
    176c:	2021      	movs	r0, #33	; 0x21
    176e:	f002 fa9f 	bl	3cb0 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1772:	e7e4      	b.n	173e <z_nrf_clock_control_lf_on+0x9e>
    p_reg->INTENSET = mask;
    1774:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1778:	2202      	movs	r2, #2
    177a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    177e:	e7d8      	b.n	1732 <z_nrf_clock_control_lf_on+0x92>
    p_reg->INTENCLR = mask;
    1780:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1784:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
    1786:	4605      	mov	r5, r0
    1788:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    178c:	e7b9      	b.n	1702 <z_nrf_clock_control_lf_on+0x62>
    178e:	bf00      	nop
    1790:	200002c8 	.word	0x200002c8
    1794:	20000264 	.word	0x20000264
    1798:	20000290 	.word	0x20000290
    179c:	2000086d 	.word	0x2000086d
    17a0:	50005104 	.word	0x50005104
    17a4:	e000e100 	.word	0xe000e100
    17a8:	50005008 	.word	0x50005008

000017ac <handle_next_cycle_case>:
 * counter progresses during that time it means that 1 cycle elapsed and
 * interrupt is set pending.
 */
static void handle_next_cycle_case(uint32_t t)
{
	set_comparator(t + 2);
    17ac:	1c82      	adds	r2, r0, #2

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
    17ae:	4b08      	ldr	r3, [pc, #32]	; (17d0 <handle_next_cycle_case+0x24>)
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    17b0:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    17b4:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
    17b8:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	while (t != counter()) {
    17bc:	4290      	cmp	r0, r2
    17be:	d100      	bne.n	17c2 <handle_next_cycle_case+0x16>
		 * generated. Trigger interrupt.
		 */
		t = counter();
		set_comparator(t + 2);
	}
}
    17c0:	4770      	bx	lr
    17c2:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		set_comparator(t + 2);
    17c6:	1c82      	adds	r2, r0, #2
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    17c8:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    17cc:	e7f2      	b.n	17b4 <handle_next_cycle_case+0x8>
    17ce:	bf00      	nop
    17d0:	50015000 	.word	0x50015000

000017d4 <rtc_nrf_isr>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    17d4:	2200      	movs	r2, #0
    17d6:	4b07      	ldr	r3, [pc, #28]	; (17f4 <rtc_nrf_isr+0x20>)
    17d8:	601a      	str	r2, [r3, #0]
    17da:	681b      	ldr	r3, [r3, #0]
{
	ARG_UNUSED(arg);
	event_clear();

	uint32_t t = get_comparator();
	uint32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
    17dc:	4a06      	ldr	r2, [pc, #24]	; (17f8 <rtc_nrf_isr+0x24>)
    return p_reg->CC[ch];
    17de:	4b07      	ldr	r3, [pc, #28]	; (17fc <rtc_nrf_isr+0x28>)
    17e0:	f8d3 0540 	ldr.w	r0, [r3, #1344]	; 0x540
    17e4:	6813      	ldr	r3, [r2, #0]
	return (a - b) & COUNTER_MAX;
    17e6:	1ac0      	subs	r0, r0, r3
    17e8:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000

	last_count += dticks * CYC_PER_TICK;
    17ec:	4403      	add	r3, r0
    17ee:	6013      	str	r3, [r2, #0]
		 * so it won't get preempted by the interrupt.
		 */
		set_absolute_alarm(last_count + CYC_PER_TICK);
	}

	z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : (dticks > 0));
    17f0:	f002 bc48 	b.w	4084 <z_clock_announce>
    17f4:	50015140 	.word	0x50015140
    17f8:	200002cc 	.word	0x200002cc
    17fc:	50015000 	.word	0x50015000

00001800 <z_clock_driver_init>:
}

int z_clock_driver_init(const struct device *device)
{
    1800:	b538      	push	{r3, r4, r5, lr}
}

NRF_STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_reg, uint32_t val)
{
    NRFX_ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
    p_reg->PRESCALER = val;
    1802:	2400      	movs	r4, #0
    1804:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    1808:	4d0e      	ldr	r5, [pc, #56]	; (1844 <z_clock_driver_init+0x44>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    180a:	4b0f      	ldr	r3, [pc, #60]	; (1848 <z_clock_driver_init+0x48>)
    p_reg->PRESCALER = val;
    180c:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    1810:	601c      	str	r4, [r3, #0]
    1812:	681b      	ldr	r3, [r3, #0]
    1814:	4b0d      	ldr	r3, [pc, #52]	; (184c <z_clock_driver_init+0x4c>)
	nrf_rtc_prescaler_set(RTC, 0);
	event_clear();
	NVIC_ClearPendingIRQ(RTC_IRQn);
	int_enable();

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    1816:	2101      	movs	r1, #1
    1818:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    p_reg->INTENSET = mask;
    181c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    1820:	4622      	mov	r2, r4
    1822:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    1826:	2015      	movs	r0, #21
    1828:	f000 fbee 	bl	2008 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    182c:	2015      	movs	r0, #21
    182e:	f000 fbcd 	bl	1fcc <arch_irq_enable>
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    1832:	2301      	movs	r3, #1
    1834:	4a06      	ldr	r2, [pc, #24]	; (1850 <z_clock_driver_init+0x50>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		set_comparator(counter() + CYC_PER_TICK);
	}

	z_nrf_clock_control_lf_on(mode);
    1836:	2002      	movs	r0, #2
    1838:	6013      	str	r3, [r2, #0]
    183a:	602b      	str	r3, [r5, #0]
    183c:	f7ff ff30 	bl	16a0 <z_nrf_clock_control_lf_on>

	return 0;
}
    1840:	4620      	mov	r0, r4
    1842:	bd38      	pop	{r3, r4, r5, pc}
    1844:	50015000 	.word	0x50015000
    1848:	50015140 	.word	0x50015140
    184c:	e000e100 	.word	0xe000e100
    1850:	50015008 	.word	0x50015008

00001854 <z_clock_set_timeout>:

void z_clock_set_timeout(int32_t ticks, bool idle)
{
    1854:	b5f8      	push	{r3, r4, r5, r6, r7, lr}

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    1856:	4b2e      	ldr	r3, [pc, #184]	; (1910 <z_clock_set_timeout+0xbc>)
    1858:	f1b0 3fff 	cmp.w	r0, #4294967295
    185c:	bf08      	it	eq
    185e:	4618      	moveq	r0, r3
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    1860:	3801      	subs	r0, #1
    1862:	2800      	cmp	r0, #0
    1864:	dd41      	ble.n	18ea <z_clock_set_timeout+0x96>
    1866:	4298      	cmp	r0, r3
    1868:	bfa8      	it	ge
    186a:	4618      	movge	r0, r3
     return p_reg->COUNTER;
    186c:	4b29      	ldr	r3, [pc, #164]	; (1914 <z_clock_set_timeout+0xc0>)

	uint32_t unannounced = counter_sub(counter(), last_count);
    186e:	492a      	ldr	r1, [pc, #168]	; (1918 <z_clock_set_timeout+0xc4>)
    1870:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
    1874:	6809      	ldr	r1, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    1876:	2600      	movs	r6, #0
	return (a - b) & COUNTER_MAX;
    1878:	1a52      	subs	r2, r2, r1
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
		ticks = 0;
    187a:	f412 0f00 	tst.w	r2, #8388608	; 0x800000
    187e:	bf18      	it	ne
    1880:	2000      	movne	r0, #0
	return (a - b) & COUNTER_MAX;
    1882:	f022 447f 	bic.w	r4, r2, #4278190080	; 0xff000000
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    1886:	3401      	adds	r4, #1
    1888:	4420      	add	r0, r4
	 */
	if (cyc > MAX_CYCLES) {
		cyc = MAX_CYCLES;
	}

	cyc += last_count;
    188a:	4c21      	ldr	r4, [pc, #132]	; (1910 <z_clock_set_timeout+0xbc>)
    188c:	4d23      	ldr	r5, [pc, #140]	; (191c <z_clock_set_timeout+0xc8>)
    188e:	42a0      	cmp	r0, r4
    1890:	bf94      	ite	ls
    1892:	180c      	addls	r4, r1, r0
    1894:	190c      	addhi	r4, r1, r4
    p_reg->INTENCLR = mask;
    1896:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    189a:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
     return p_reg->COUNTER;
    189e:	f8d3 1504 	ldr.w	r1, [r3, #1284]	; 0x504
    return p_reg->CC[ch];
    18a2:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    18a6:	602e      	str	r6, [r5, #0]
    18a8:	682f      	ldr	r7, [r5, #0]
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    18aa:	f021 477f 	bic.w	r7, r1, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    18ae:	f8c3 7540 	str.w	r7, [r3, #1344]	; 0x540
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    18b2:	f8c3 0344 	str.w	r0, [r3, #836]	; 0x344
	return (a - b) & COUNTER_MAX;
    18b6:	1a53      	subs	r3, r2, r1
    18b8:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
	if (counter_sub(prev_val, now) == 1) {
    18bc:	2b01      	cmp	r3, #1
    18be:	d104      	bne.n	18ca <z_clock_set_timeout+0x76>
	z_impl_k_busy_wait(usec_to_wait);
    18c0:	200f      	movs	r0, #15
    18c2:	f004 f93b 	bl	5b3c <z_impl_k_busy_wait>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    18c6:	602e      	str	r6, [r5, #0]
    18c8:	682b      	ldr	r3, [r5, #0]
    18ca:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    18ce:	4b14      	ldr	r3, [pc, #80]	; (1920 <z_clock_set_timeout+0xcc>)
    18d0:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
     return p_reg->COUNTER;
    18d4:	4b0f      	ldr	r3, [pc, #60]	; (1914 <z_clock_set_timeout+0xc0>)
    18d6:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    18da:	1a22      	subs	r2, r4, r0
    18dc:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
	if (diff == 1) {
    18e0:	2a01      	cmp	r2, #1
    18e2:	d104      	bne.n	18ee <z_clock_set_timeout+0x9a>
		handle_next_cycle_case(t);
    18e4:	f7ff ff62 	bl	17ac <handle_next_cycle_case>
    18e8:	e00b      	b.n	1902 <z_clock_set_timeout+0xae>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    18ea:	2000      	movs	r0, #0
    18ec:	e7be      	b.n	186c <z_clock_set_timeout+0x18>
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    18ee:	f024 427f 	bic.w	r2, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    18f2:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
     return p_reg->COUNTER;
    18f6:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    18fa:	1a24      	subs	r4, r4, r0
    18fc:	3c02      	subs	r4, #2
	if (diff > MAX_CYCLES) {
    18fe:	0223      	lsls	r3, r4, #8
    1900:	d4f0      	bmi.n	18e4 <z_clock_set_timeout+0x90>
    p_reg->INTENSET = mask;
    1902:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    1906:	4b03      	ldr	r3, [pc, #12]	; (1914 <z_clock_set_timeout+0xc0>)
    1908:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
	set_protected_absolute_alarm(cyc);
}
    190c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    190e:	bf00      	nop
    1910:	007fffff 	.word	0x007fffff
    1914:	50015000 	.word	0x50015000
    1918:	200002cc 	.word	0x200002cc
    191c:	50015140 	.word	0x50015140
    1920:	e000e100 	.word	0xe000e100

00001924 <z_clock_elapsed>:
	__asm__ volatile(
    1924:	f04f 0220 	mov.w	r2, #32
    1928:	f3ef 8311 	mrs	r3, BASEPRI
    192c:	f382 8811 	msr	BASEPRI, r2
    1930:	f3bf 8f6f 	isb	sy
     return p_reg->COUNTER;
    1934:	4a06      	ldr	r2, [pc, #24]	; (1950 <z_clock_elapsed+0x2c>)
    1936:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	k_spinlock_key_t key = k_spin_lock(&lock);
	uint32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
    193a:	4a06      	ldr	r2, [pc, #24]	; (1954 <z_clock_elapsed+0x30>)
	return (a - b) & COUNTER_MAX;
    193c:	6812      	ldr	r2, [r2, #0]
    193e:	1a80      	subs	r0, r0, r2
    1940:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	__asm__ volatile(
    1944:	f383 8811 	msr	BASEPRI, r3
    1948:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&lock, key);
	return ret;
}
    194c:	4770      	bx	lr
    194e:	bf00      	nop
    1950:	50015000 	.word	0x50015000
    1954:	200002cc 	.word	0x200002cc

00001958 <config_regions>:
}
#endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */


static void config_regions(bool ram, size_t start, size_t end, uint32_t perm)
{
    1958:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	const size_t region_size = ram ? RAM_SECURE_ATTRIBUTION_REGION_SIZE
					: FLASH_SECURE_ATTRIBUTION_REGION_SIZE;
    195a:	2800      	cmp	r0, #0
{
    195c:	461c      	mov	r4, r3

	for (size_t i = start; i < end; i++) {
    195e:	460d      	mov	r5, r1
					: FLASH_SECURE_ATTRIBUTION_REGION_SIZE;
    1960:	bf14      	ite	ne
    1962:	f44f 5300 	movne.w	r3, #8192	; 0x2000
    1966:	f44f 4300 	moveq.w	r3, #32768	; 0x8000
	for (size_t i = start; i < end; i++) {
    196a:	4e20      	ldr	r6, [pc, #128]	; (19ec <config_regions+0x94>)
    196c:	4295      	cmp	r5, r2
    196e:	d332      	bcc.n	19d6 <config_regions+0x7e>
		} else {
			NRF_SPU->FLASHREGION[i].PERM = perm;
		}
	}

	PRINT("%02u %02u 0x%05x 0x%05x \t", start, end - 1,
    1970:	fb02 f003 	mul.w	r0, r2, r3
    1974:	3a01      	subs	r2, #1
    1976:	434b      	muls	r3, r1
    1978:	9000      	str	r0, [sp, #0]
    197a:	481d      	ldr	r0, [pc, #116]	; (19f0 <config_regions+0x98>)
    197c:	f003 fb56 	bl	502c <printk>
				region_size * start, region_size * end);
	PRINT("%s", perm & (ram ? SRAM_SECURE : FLASH_SECURE) ? "Secure\t\t" :
    1980:	4b1c      	ldr	r3, [pc, #112]	; (19f4 <config_regions+0x9c>)
    1982:	f014 0f10 	tst.w	r4, #16
    1986:	491c      	ldr	r1, [pc, #112]	; (19f8 <config_regions+0xa0>)
    1988:	481c      	ldr	r0, [pc, #112]	; (19fc <config_regions+0xa4>)
    198a:	bf08      	it	eq
    198c:	4619      	moveq	r1, r3
    198e:	f003 fb4d 	bl	502c <printk>
								"Non-Secure\t");
	PRINT("%c", perm & (ram ? SRAM_READ : FLASH_READ)  ? 'r' : '-');
    1992:	f014 0f04 	tst.w	r4, #4
    1996:	bf14      	ite	ne
    1998:	2172      	movne	r1, #114	; 0x72
    199a:	212d      	moveq	r1, #45	; 0x2d
    199c:	4818      	ldr	r0, [pc, #96]	; (1a00 <config_regions+0xa8>)
    199e:	f003 fb45 	bl	502c <printk>
	PRINT("%c", perm & (ram ? SRAM_WRITE : FLASH_WRITE) ? 'w' : '-');
    19a2:	f014 0f02 	tst.w	r4, #2
    19a6:	bf14      	ite	ne
    19a8:	2177      	movne	r1, #119	; 0x77
    19aa:	212d      	moveq	r1, #45	; 0x2d
    19ac:	4814      	ldr	r0, [pc, #80]	; (1a00 <config_regions+0xa8>)
    19ae:	f003 fb3d 	bl	502c <printk>
	PRINT("%c", perm & (ram ? SRAM_EXEC : FLASH_EXEC)  ? 'x' : '-');
    19b2:	f014 0f01 	tst.w	r4, #1
    19b6:	bf0c      	ite	eq
    19b8:	212d      	moveq	r1, #45	; 0x2d
    19ba:	2178      	movne	r1, #120	; 0x78
    19bc:	4810      	ldr	r0, [pc, #64]	; (1a00 <config_regions+0xa8>)
    19be:	f003 fb35 	bl	502c <printk>
	PRINT("%c", perm & (ram ? SRAM_LOCK : FLASH_LOCK)  ? 'l' : '-');
    19c2:	216c      	movs	r1, #108	; 0x6c
    19c4:	480e      	ldr	r0, [pc, #56]	; (1a00 <config_regions+0xa8>)
    19c6:	f003 fb31 	bl	502c <printk>
	PRINT("\n");
    19ca:	480e      	ldr	r0, [pc, #56]	; (1a04 <config_regions+0xac>)
}
    19cc:	b003      	add	sp, #12
    19ce:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
	PRINT("\n");
    19d2:	f003 bb2b 	b.w	502c <printk>
		if (ram) {
    19d6:	b128      	cbz	r0, 19e4 <config_regions+0x8c>
			NRF_SPU->RAMREGION[i].PERM = perm;
    19d8:	f505 77e0 	add.w	r7, r5, #448	; 0x1c0
			NRF_SPU->FLASHREGION[i].PERM = perm;
    19dc:	f846 4027 	str.w	r4, [r6, r7, lsl #2]
	for (size_t i = start; i < end; i++) {
    19e0:	3501      	adds	r5, #1
    19e2:	e7c3      	b.n	196c <config_regions+0x14>
			NRF_SPU->FLASHREGION[i].PERM = perm;
    19e4:	f505 77c0 	add.w	r7, r5, #384	; 0x180
    19e8:	e7f8      	b.n	19dc <config_regions+0x84>
    19ea:	bf00      	nop
    19ec:	50003000 	.word	0x50003000
    19f0:	00006196 	.word	0x00006196
    19f4:	0000618a 	.word	0x0000618a
    19f8:	00006181 	.word	0x00006181
    19fc:	00006315 	.word	0x00006315
    1a00:	000061b0 	.word	0x000061b0
    1a04:	000064eb 	.word	0x000064eb

00001a08 <spm_config_peripheral.constprop.0>:
		     SPU_PERIPHID_PERM_SECUREMAPPING_Split;

	return present && (usel || split);
}

static int spm_config_peripheral(uint8_t id, bool dma_present)
    1a08:	b508      	push	{r3, lr}
	 * Assign DMA capabilities and lock down the attribution.
	 *
	 * Note: the function assumes that the peripheral ID matches
	 * the IRQ line.
	 */
	NVIC_DisableIRQ(id);
    1a0a:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    1a0c:	2b00      	cmp	r3, #0
    1a0e:	db0c      	blt.n	1a2a <spm_config_peripheral.constprop.0+0x22>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1a10:	2201      	movs	r2, #1
    1a12:	f000 011f 	and.w	r1, r0, #31
    1a16:	408a      	lsls	r2, r1
    1a18:	095b      	lsrs	r3, r3, #5
    1a1a:	4910      	ldr	r1, [pc, #64]	; (1a5c <spm_config_peripheral.constprop.0+0x54>)
    1a1c:	3320      	adds	r3, #32
    1a1e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    1a22:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1a26:	f3bf 8f6f 	isb	sy
	const uint32_t perm = NRF_SPU->PERIPHID[id].PERM;
    1a2a:	0083      	lsls	r3, r0, #2
    1a2c:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    1a30:	f503 5340 	add.w	r3, r3, #12288	; 0x3000
	if (id == NRFX_PERIPHERAL_ID_GET(NRF_GPIOTE1_NS)) {
    1a34:	2831      	cmp	r0, #49	; 0x31
	const uint32_t perm = NRF_SPU->PERIPHID[id].PERM;
    1a36:	f8d3 2800 	ldr.w	r2, [r3, #2048]	; 0x800
	if (id == NRFX_PERIPHERAL_ID_GET(NRF_GPIOTE1_NS)) {
    1a3a:	d006      	beq.n	1a4a <spm_config_peripheral.constprop.0+0x42>
	return present && (usel || split);
    1a3c:	2a00      	cmp	r2, #0
    1a3e:	da07      	bge.n	1a50 <spm_config_peripheral.constprop.0+0x48>
	bool usel = (perm & SPU_PERIPHID_PERM_SECUREMAPPING_Msk) ==
    1a40:	f002 0203 	and.w	r2, r2, #3
	return present && (usel || split);
    1a44:	3a02      	subs	r2, #2
    1a46:	2a01      	cmp	r2, #1
    1a48:	d802      	bhi.n	1a50 <spm_config_peripheral.constprop.0+0x48>

	if (usel_or_split(id)) {
		NRF_SPU->PERIPHID[id].PERM = PERIPH_PRESENT | PERIPH_NONSEC |
    1a4a:	4a05      	ldr	r2, [pc, #20]	; (1a60 <spm_config_peripheral.constprop.0+0x58>)
    1a4c:	f8c3 2800 	str.w	r2, [r3, #2048]	; 0x800
	}

	/* Even for non-present peripherals we force IRQs to be routed
	 * to Non-Secure state.
	 */
	irq_target_state_set(id, IRQ_TARGET_STATE_NON_SECURE);
    1a50:	2101      	movs	r1, #1
    1a52:	f003 fe24 	bl	569e <irq_target_state_set>
	return 0;
}
    1a56:	2000      	movs	r0, #0
    1a58:	bd08      	pop	{r3, pc}
    1a5a:	bf00      	nop
    1a5c:	e000e100 	.word	0xe000e100
    1a60:	80000100 	.word	0x80000100

00001a64 <spm_jump>:
	tz_nonsecure_fpu_access_enable();
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
}

void spm_jump(void)
{
    1a64:	b530      	push	{r4, r5, lr}
	 * The assumption is that the MSP is located at VTOR_NS[0].
	 */
	uint32_t *vtor_ns = (uint32_t *)NON_SECURE_APP_ADDRESS;

	PRINT("SPM: NS image at 0x%x\n", (uint32_t)vtor_ns);
	PRINT("SPM: NS MSP at 0x%x\n", vtor_ns[0]);
    1a66:	f44f 4440 	mov.w	r4, #49152	; 0xc000
	PRINT("SPM: NS reset vector at 0x%x\n", vtor_ns[1]);
    1a6a:	f24c 0504 	movw	r5, #49156	; 0xc004
{
    1a6e:	b085      	sub	sp, #20
	PRINT("SPM: NS image at 0x%x\n", (uint32_t)vtor_ns);
    1a70:	f44f 4140 	mov.w	r1, #49152	; 0xc000
    1a74:	482c      	ldr	r0, [pc, #176]	; (1b28 <spm_jump+0xc4>)
    1a76:	f003 fad9 	bl	502c <printk>
	PRINT("SPM: NS MSP at 0x%x\n", vtor_ns[0]);
    1a7a:	6821      	ldr	r1, [r4, #0]
    1a7c:	482b      	ldr	r0, [pc, #172]	; (1b2c <spm_jump+0xc8>)
    1a7e:	f003 fad5 	bl	502c <printk>
	PRINT("SPM: NS reset vector at 0x%x\n", vtor_ns[1]);
    1a82:	6829      	ldr	r1, [r5, #0]
    1a84:	482a      	ldr	r0, [pc, #168]	; (1b30 <spm_jump+0xcc>)
    1a86:	f003 fad1 	bl	502c <printk>

	/* Configure Non-Secure stack */
	tz_nonsecure_setup_conf_t spm_ns_conf = {
    1a8a:	2210      	movs	r2, #16
    1a8c:	2100      	movs	r1, #0
    1a8e:	4668      	mov	r0, sp
    1a90:	f003 fed0 	bl	5834 <memset>
		.vtor_ns = (uint32_t)vtor_ns,
		.msp_ns = vtor_ns[0],
    1a94:	6823      	ldr	r3, [r4, #0]
	tz_nonsecure_state_setup(spm_ns_conf);
    1a96:	4668      	mov	r0, sp
	tz_nonsecure_setup_conf_t spm_ns_conf = {
    1a98:	9300      	str	r3, [sp, #0]
    1a9a:	9402      	str	r4, [sp, #8]
	tz_nonsecure_state_setup(spm_ns_conf);
    1a9c:	f000 feb8 	bl	2810 <tz_nonsecure_state_setup>
	tz_nonsecure_exception_prio_config(1);
    1aa0:	2001      	movs	r0, #1
    1aa2:	f000 fee5 	bl	2870 <tz_nonsecure_exception_prio_config>
	tz_nbanked_exception_target_state_set(0);
    1aa6:	2000      	movs	r0, #0
    1aa8:	f000 fece 	bl	2848 <tz_nbanked_exception_target_state_set>
	tz_nonsecure_system_reset_req_block(
    1aac:	2000      	movs	r0, #0
    1aae:	f000 fef3 	bl	2898 <tz_nonsecure_system_reset_req_block>
	tz_sau_configure(0, 1);
    1ab2:	2101      	movs	r1, #1
    1ab4:	2000      	movs	r0, #0
    1ab6:	f000 ff0d 	bl	28d4 <tz_sau_configure>
	tz_nonsecure_fpu_access_enable();
    1aba:	f000 ff01 	bl	28c0 <tz_nonsecure_fpu_access_enable>

	spm_configure_ns(&spm_ns_conf);

	/* Generate function pointer for Non-Secure function call. */
	TZ_NONSECURE_FUNC_PTR_DECLARE(reset_ns);
	reset_ns = TZ_NONSECURE_FUNC_PTR_CREATE(vtor_ns[1]);
    1abe:	682c      	ldr	r4, [r5, #0]

	if (TZ_NONSECURE_FUNC_PTR_IS_NS(reset_ns)) {
		PRINT("SPM: prepare to jump to Non-Secure image.\n");
    1ac0:	481c      	ldr	r0, [pc, #112]	; (1b34 <spm_jump+0xd0>)
    1ac2:	f003 fab3 	bl	502c <printk>
		/* Note: Move UARTE0 before jumping, if it is
		 * to be used on the Non-Secure domain.
		 */

		/* Configure UARTE0 as non-secure */
		spm_config_peripheral(
    1ac6:	2008      	movs	r0, #8
    1ac8:	f7ff ff9e 	bl	1a08 <spm_config_peripheral.constprop.0>
	reset_ns = TZ_NONSECURE_FUNC_PTR_CREATE(vtor_ns[1]);
    1acc:	f024 0401 	bic.w	r4, r4, #1
  __ASM volatile ("dsb 0xF":::"memory");
    1ad0:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1ad4:	f3bf 8f6f 	isb	sy

		__DSB();
		__ISB();

		/* Jump to Non-Secure firmware */
		reset_ns();
    1ad8:	0864      	lsrs	r4, r4, #1
    1ada:	0064      	lsls	r4, r4, #1
    1adc:	4620      	mov	r0, r4
    1ade:	4621      	mov	r1, r4
    1ae0:	4622      	mov	r2, r4
    1ae2:	4623      	mov	r3, r4
    1ae4:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1ae8:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1aec:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    1af0:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1af4:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1af8:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1afc:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    1b00:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1b04:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1b08:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1b0c:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    1b10:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1b14:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1b18:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1b1c:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    1b20:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    1b24:	f7fe fd04 	bl	530 <__gnu_cmse_nonsecure_call>

		CODE_UNREACHABLE;
    1b28:	000061b3 	.word	0x000061b3
    1b2c:	000061ca 	.word	0x000061ca
    1b30:	000061df 	.word	0x000061df
    1b34:	000061fd 	.word	0x000061fd

00001b38 <spm_config>:
		      (uint32_t)reset_ns);
	}
}

void spm_config(void)
{
    1b38:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	PRINT("Flash regions\t\tDomain\t\tPermissions\n");
    1b3c:	483b      	ldr	r0, [pc, #236]	; (1c2c <spm_config+0xf4>)
    1b3e:	f003 fa75 	bl	502c <printk>
	config_regions(false, 0, NON_SECURE_FLASH_REGION_INDEX,
    1b42:	2100      	movs	r1, #0
    1b44:	f240 1317 	movw	r3, #279	; 0x117
    1b48:	4608      	mov	r0, r1
    1b4a:	2201      	movs	r2, #1
    1b4c:	f7ff ff04 	bl	1958 <config_regions>
	config_regions(false, NON_SECURE_FLASH_REGION_INDEX,
    1b50:	f240 1307 	movw	r3, #263	; 0x107
    1b54:	2220      	movs	r2, #32
    1b56:	2101      	movs	r1, #1
    1b58:	2000      	movs	r0, #0
    1b5a:	f7ff fefd 	bl	1958 <config_regions>
	PRINT("\n");
    1b5e:	4834      	ldr	r0, [pc, #208]	; (1c30 <spm_config+0xf8>)
    1b60:	f003 fa64 	bl	502c <printk>
	uint32_t nsc_size = FLASH_NSC_SIZE_FROM_ADDR(__sg_start);
    1b64:	4b33      	ldr	r3, [pc, #204]	; (1c34 <spm_config+0xfc>)
                                            bool               lock_conf)
{
    NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
    NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));

    p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
    1b66:	4a34      	ldr	r2, [pc, #208]	; (1c38 <spm_config+0x100>)
    1b68:	f3c3 31c4 	ubfx	r1, r3, #15, #5
    1b6c:	f3c3 030e 	ubfx	r3, r3, #0, #15
    1b70:	f5c3 4300 	rsb	r3, r3, #32768	; 0x8000
        (lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
    p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
    1b74:	f3c3 1343 	ubfx	r3, r3, #5, #4
    p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
    1b78:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
    1b7c:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
	PRINT("Non-secure callable region 0 placed in flash region %d with size %d.\n",
    1b80:	f8d2 1500 	ldr.w	r1, [r2, #1280]	; 0x500
    1b84:	f8d2 2504 	ldr.w	r2, [r2, #1284]	; 0x504
    1b88:	482c      	ldr	r0, [pc, #176]	; (1c3c <spm_config+0x104>)
    1b8a:	0152      	lsls	r2, r2, #5
    1b8c:	f003 fa4e 	bl	502c <printk>
	PRINT("\n");
    1b90:	4827      	ldr	r0, [pc, #156]	; (1c30 <spm_config+0xf8>)
    1b92:	f003 fa4b 	bl	502c <printk>
	int err = spm_secure_services_init();
    1b96:	f003 fd30 	bl	55fa <spm_secure_services_init>
	if (err != 0) {
    1b9a:	4601      	mov	r1, r0
    1b9c:	b110      	cbz	r0, 1ba4 <spm_config+0x6c>
		PRINT("Could not initialize secure services (err %d).\n", err);
    1b9e:	4828      	ldr	r0, [pc, #160]	; (1c40 <spm_config+0x108>)
    1ba0:	f003 fa44 	bl	502c <printk>
	NRF_SPU->DPPI[0].PERM = mask;
    1ba4:	2400      	movs	r4, #0
	PRINT("SRAM region\t\tDomain\t\tPermissions\n");
    1ba6:	4827      	ldr	r0, [pc, #156]	; (1c44 <spm_config+0x10c>)
    1ba8:	f003 fa40 	bl	502c <printk>
	config_regions(true, 0, NON_SECURE_RAM_REGION_INDEX,
    1bac:	f240 1317 	movw	r3, #279	; 0x117
    1bb0:	2208      	movs	r2, #8
    1bb2:	2100      	movs	r1, #0
    1bb4:	2001      	movs	r0, #1
    1bb6:	f7ff fecf 	bl	1958 <config_regions>
	NRF_SPU->DPPI[0].PERM = mask;
    1bba:	4d1f      	ldr	r5, [pc, #124]	; (1c38 <spm_config+0x100>)
	config_regions(true, NON_SECURE_RAM_REGION_INDEX,
    1bbc:	f240 1307 	movw	r3, #263	; 0x107
    1bc0:	2220      	movs	r2, #32
    1bc2:	2108      	movs	r1, #8
    1bc4:	2001      	movs	r0, #1
    1bc6:	f7ff fec7 	bl	1958 <config_regions>
	PRINT("\n");
    1bca:	4819      	ldr	r0, [pc, #100]	; (1c30 <spm_config+0xf8>)
    1bcc:	f003 fa2e 	bl	502c <printk>
	NRF_SPU->DPPI[0].PERM = mask;
    1bd0:	f8c5 4480 	str.w	r4, [r5, #1152]	; 0x480
	PRINT("Peripheral\t\tDomain\t\tStatus\n");
    1bd4:	481c      	ldr	r0, [pc, #112]	; (1c48 <spm_config+0x110>)
    1bd6:	f003 fa29 	bl	502c <printk>
		PRINT("%02u %-21s%s", i, periph[i].name,
    1bda:	4f1c      	ldr	r7, [pc, #112]	; (1c4c <spm_config+0x114>)
		NRF_SPU->GPIOPORT[0].PERM = 0;
    1bdc:	f8c5 44c0 	str.w	r4, [r5, #1216]	; 0x4c0
		PRINT("%02u %-21s%s", i, periph[i].name,
    1be0:	f8df 807c 	ldr.w	r8, [pc, #124]	; 1c60 <spm_config+0x128>
    1be4:	4d1a      	ldr	r5, [pc, #104]	; (1c50 <spm_config+0x118>)
    1be6:	f8df 907c 	ldr.w	r9, [pc, #124]	; 1c64 <spm_config+0x12c>
    1bea:	796e      	ldrb	r6, [r5, #5]
    1bec:	4621      	mov	r1, r4
    1bee:	2e00      	cmp	r6, #0
    1bf0:	bf14      	ite	ne
    1bf2:	463b      	movne	r3, r7
    1bf4:	4643      	moveq	r3, r8
    1bf6:	4648      	mov	r0, r9
    1bf8:	682a      	ldr	r2, [r5, #0]
    1bfa:	f003 fa17 	bl	502c <printk>
		if (!periph[i].nonsecure) {
    1bfe:	b966      	cbnz	r6, 1c1a <spm_config+0xe2>
			PRINT("\tSKIP\n");
    1c00:	4814      	ldr	r0, [pc, #80]	; (1c54 <spm_config+0x11c>)
	for (size_t i = 0; i < ARRAY_SIZE(periph); i++) {
    1c02:	3401      	adds	r4, #1
			PRINT("\tOK\n");
    1c04:	f003 fa12 	bl	502c <printk>
	for (size_t i = 0; i < ARRAY_SIZE(periph); i++) {
    1c08:	2c1a      	cmp	r4, #26
    1c0a:	f105 0508 	add.w	r5, r5, #8
    1c0e:	d1ec      	bne.n	1bea <spm_config+0xb2>
	PRINT("\n");
    1c10:	4807      	ldr	r0, [pc, #28]	; (1c30 <spm_config+0xf8>)
	spm_config_flash();
	spm_config_sram();
	spm_config_peripherals();
}
    1c12:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	PRINT("\n");
    1c16:	f003 ba09 	b.w	502c <printk>
		err = spm_config_peripheral(periph[i].id, false);
    1c1a:	7928      	ldrb	r0, [r5, #4]
    1c1c:	f7ff fef4 	bl	1a08 <spm_config_peripheral.constprop.0>
		if (err) {
    1c20:	b108      	cbz	r0, 1c26 <spm_config+0xee>
			PRINT("\tERROR\n");
    1c22:	480d      	ldr	r0, [pc, #52]	; (1c58 <spm_config+0x120>)
    1c24:	e7ed      	b.n	1c02 <spm_config+0xca>
			PRINT("\tOK\n");
    1c26:	480d      	ldr	r0, [pc, #52]	; (1c5c <spm_config+0x124>)
    1c28:	e7eb      	b.n	1c02 <spm_config+0xca>
    1c2a:	bf00      	nop
    1c2c:	00006233 	.word	0x00006233
    1c30:	000064eb 	.word	0x000064eb
    1c34:	00007fe0 	.word	0x00007fe0
    1c38:	50003000 	.word	0x50003000
    1c3c:	00006257 	.word	0x00006257
    1c40:	0000629d 	.word	0x0000629d
    1c44:	000062cd 	.word	0x000062cd
    1c48:	000062ef 	.word	0x000062ef
    1c4c:	00006228 	.word	0x00006228
    1c50:	00005ed8 	.word	0x00005ed8
    1c54:	00006318 	.word	0x00006318
    1c58:	0000631f 	.word	0x0000631f
    1c5c:	00006327 	.word	0x00006327
    1c60:	0000618e 	.word	0x0000618e
    1c64:	0000630b 	.word	0x0000630b

00001c68 <__acle_se_spm_request_read_nse>:
};


__TZ_NONSECURE_ENTRY_FUNC
int spm_request_read_nse(void *destination, uint32_t addr, size_t len)
{
    1c68:	b510      	push	{r4, lr}
		 .size = FICR_PUBLIC_SIZE},
		{.start = FICR_RESTRICTED_ADDR,
		 .size = FICR_RESTRICTED_SIZE},
	};

	if (destination == NULL || len <= 0) {
    1c6a:	2800      	cmp	r0, #0
    1c6c:	d04b      	beq.n	1d06 <__acle_se_spm_request_read_nse+0x9e>
    1c6e:	2a00      	cmp	r2, #0
    1c70:	d049      	beq.n	1d06 <__acle_se_spm_request_read_nse+0x9e>

	for (size_t i = 0; i < ARRAY_SIZE(ranges); i++) {
		uint32_t start = ranges[i].start;
		uint32_t size = ranges[i].size;

		if (addr >= start && addr + len <= start + size) {
    1c72:	4b26      	ldr	r3, [pc, #152]	; (1d0c <__acle_se_spm_request_read_nse+0xa4>)
    1c74:	4299      	cmp	r1, r3
    1c76:	d93c      	bls.n	1cf2 <__acle_se_spm_request_read_nse+0x8a>
    1c78:	1854      	adds	r4, r2, r1
    1c7a:	f603 231d 	addw	r3, r3, #2589	; 0xa1d
    1c7e:	429c      	cmp	r4, r3
    1c80:	d83a      	bhi.n	1cf8 <__acle_se_spm_request_read_nse+0x90>
			memcpy(destination, (const void *)addr, len);
    1c82:	f003 fdac 	bl	57de <memcpy>
			return 0;
    1c86:	2000      	movs	r0, #0
		}
	}

	return -EPERM;
}
    1c88:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    1c8c:	4671      	mov	r1, lr
    1c8e:	4672      	mov	r2, lr
    1c90:	4673      	mov	r3, lr
    1c92:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1c96:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1c9a:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    1c9e:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1ca2:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1ca6:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1caa:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    1cae:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1cb2:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1cb6:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1cba:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    1cbe:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1cc2:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1cc6:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1cca:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    1cce:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    1cd2:	f38e 8c00 	msr	CPSR_fs, lr
    1cd6:	b410      	push	{r4}
    1cd8:	eef1 ca10 	vmrs	ip, fpscr
    1cdc:	f64f 7460 	movw	r4, #65376	; 0xff60
    1ce0:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    1ce4:	ea0c 0c04 	and.w	ip, ip, r4
    1ce8:	eee1 ca10 	vmsr	fpscr, ip
    1cec:	bc10      	pop	{r4}
    1cee:	46f4      	mov	ip, lr
    1cf0:	4774      	bxns	lr
		if (addr >= start && addr + len <= start + size) {
    1cf2:	4b07      	ldr	r3, [pc, #28]	; (1d10 <__acle_se_spm_request_read_nse+0xa8>)
    1cf4:	4299      	cmp	r1, r3
    1cf6:	d903      	bls.n	1d00 <__acle_se_spm_request_read_nse+0x98>
    1cf8:	4b06      	ldr	r3, [pc, #24]	; (1d14 <__acle_se_spm_request_read_nse+0xac>)
    1cfa:	1854      	adds	r4, r2, r1
    1cfc:	429c      	cmp	r4, r3
    1cfe:	d9c0      	bls.n	1c82 <__acle_se_spm_request_read_nse+0x1a>
	return -EPERM;
    1d00:	f04f 30ff 	mov.w	r0, #4294967295
    1d04:	e7c0      	b.n	1c88 <__acle_se_spm_request_read_nse+0x20>
		return -EINVAL;
    1d06:	f06f 0015 	mvn.w	r0, #21
    1d0a:	e7bd      	b.n	1c88 <__acle_se_spm_request_read_nse+0x20>
    1d0c:	00ff0203 	.word	0x00ff0203
    1d10:	00ff012f 	.word	0x00ff012f
    1d14:	00ff0138 	.word	0x00ff0138

00001d18 <__acle_se_spm_firmware_info_nse>:


#ifdef CONFIG_SPM_SERVICE_FIND_FIRMWARE_INFO
__TZ_NONSECURE_ENTRY_FUNC
int spm_firmware_info_nse(uint32_t fw_address, struct fw_info *info)
{
    1d18:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1d1c:	4681      	mov	r9, r0
	const struct fw_info *tmp_info;

	if (info == NULL) {
    1d1e:	460e      	mov	r6, r1
{
    1d20:	b085      	sub	sp, #20
	if (info == NULL) {
    1d22:	2900      	cmp	r1, #0
    1d24:	d054      	beq.n	1dd0 <__acle_se_spm_firmware_info_nse+0xb8>
 */
static inline const struct fw_info *fw_info_find(uint32_t firmware_address)
{
	const struct fw_info *finfo;

	for (uint32_t i = 0; i < FW_INFO_OFFSET_COUNT; i++) {
    1d26:	f04f 0800 	mov.w	r8, #0
    1d2a:	f8df b0b8 	ldr.w	fp, [pc, #184]	; 1de4 <__acle_se_spm_firmware_info_nse+0xcc>
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    1d2e:	f8df a0b8 	ldr.w	sl, [pc, #184]	; 1de8 <__acle_se_spm_firmware_info_nse+0xd0>
    1d32:	af01      	add	r7, sp, #4
		finfo = fw_info_check(firmware_address +
						fw_info_allowed_offsets[i]);
    1d34:	f85b 5b04 	ldr.w	r5, [fp], #4
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    1d38:	e89a 0007 	ldmia.w	sl, {r0, r1, r2}
		finfo = fw_info_check(firmware_address +
    1d3c:	444d      	add	r5, r9
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    1d3e:	e887 0007 	stmia.w	r7, {r0, r1, r2}
	if (memcmp(finfo->magic, fw_info_magic, CONFIG_FW_INFO_MAGIC_LEN)
    1d42:	220c      	movs	r2, #12
    1d44:	4639      	mov	r1, r7
    1d46:	4628      	mov	r0, r5
    1d48:	f003 fd22 	bl	5790 <memcmp>
    1d4c:	4604      	mov	r4, r0
    1d4e:	b908      	cbnz	r0, 1d54 <__acle_se_spm_firmware_info_nse+0x3c>
		if (finfo) {
    1d50:	2d00      	cmp	r5, #0
    1d52:	d140      	bne.n	1dd6 <__acle_se_spm_firmware_info_nse+0xbe>
	for (uint32_t i = 0; i < FW_INFO_OFFSET_COUNT; i++) {
    1d54:	f108 0801 	add.w	r8, r8, #1
    1d58:	f1b8 0f05 	cmp.w	r8, #5
    1d5c:	d1ea      	bne.n	1d34 <__acle_se_spm_firmware_info_nse+0x1c>
	if (tmp_info != NULL) {
		memcpy(info, tmp_info, sizeof(*tmp_info));
		return 0;
	}

	return -EFAULT;
    1d5e:	f06f 040d 	mvn.w	r4, #13
}
    1d62:	4620      	mov	r0, r4
    1d64:	b005      	add	sp, #20
    1d66:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1d6a:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1d6e:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    1d72:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1d76:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1d7a:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1d7e:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    1d82:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1d86:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1d8a:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1d8e:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    1d92:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1d96:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1d9a:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1d9e:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    1da2:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1da6:	4671      	mov	r1, lr
    1da8:	4672      	mov	r2, lr
    1daa:	4673      	mov	r3, lr
    1dac:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    1db0:	f38e 8c00 	msr	CPSR_fs, lr
    1db4:	b410      	push	{r4}
    1db6:	eef1 ca10 	vmrs	ip, fpscr
    1dba:	f64f 7460 	movw	r4, #65376	; 0xff60
    1dbe:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    1dc2:	ea0c 0c04 	and.w	ip, ip, r4
    1dc6:	eee1 ca10 	vmsr	fpscr, ip
    1dca:	bc10      	pop	{r4}
    1dcc:	46f4      	mov	ip, lr
    1dce:	4774      	bxns	lr
		return -EINVAL;
    1dd0:	f06f 0415 	mvn.w	r4, #21
    1dd4:	e7c5      	b.n	1d62 <__acle_se_spm_firmware_info_nse+0x4a>
		memcpy(info, tmp_info, sizeof(*tmp_info));
    1dd6:	223c      	movs	r2, #60	; 0x3c
    1dd8:	4629      	mov	r1, r5
    1dda:	4630      	mov	r0, r6
    1ddc:	f003 fcff 	bl	57de <memcpy>
		return 0;
    1de0:	e7bf      	b.n	1d62 <__acle_se_spm_firmware_info_nse+0x4a>
    1de2:	bf00      	nop
    1de4:	00005fa8 	.word	0x00005fa8
    1de8:	00005e50 	.word	0x00005e50

00001dec <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    1dec:	4801      	ldr	r0, [pc, #4]	; (1df4 <nrf_cc3xx_platform_abort_init+0x8>)
    1dee:	f002 bbe3 	b.w	45b8 <nrf_cc3xx_platform_set_abort>
    1df2:	bf00      	nop
    1df4:	00005fbc 	.word	0x00005fbc

00001df8 <mutex_unlock_platform>:
}


/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1df8:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1dfa:	b130      	cbz	r0, 1e0a <mutex_unlock_platform+0x12>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    /* Ensure that the mutex has been initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1dfc:	6843      	ldr	r3, [r0, #4]
    1dfe:	b13b      	cbz	r3, 1e10 <mutex_unlock_platform+0x18>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    }

    p_mutex = (struct k_mutex *)mutex->mutex;
    1e00:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_unlock(mutex);
    1e02:	f001 fba5 	bl	3550 <z_impl_k_mutex_unlock>

    k_mutex_unlock(p_mutex);
    return NRF_CC3XX_PLATFORM_SUCCESS;
    1e06:	2000      	movs	r0, #0
}
    1e08:	bd08      	pop	{r3, pc}
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1e0a:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1e0e:	e7fb      	b.n	1e08 <mutex_unlock_platform+0x10>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1e10:	4800      	ldr	r0, [pc, #0]	; (1e14 <mutex_unlock_platform+0x1c>)
    1e12:	e7f9      	b.n	1e08 <mutex_unlock_platform+0x10>
    1e14:	ffff8fea 	.word	0xffff8fea

00001e18 <mutex_free_platform>:
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1e18:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    1e1a:	4604      	mov	r4, r0
    1e1c:	b918      	cbnz	r0, 1e26 <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    1e1e:	4b0b      	ldr	r3, [pc, #44]	; (1e4c <mutex_free_platform+0x34>)
    1e20:	480b      	ldr	r0, [pc, #44]	; (1e50 <mutex_free_platform+0x38>)
    1e22:	685b      	ldr	r3, [r3, #4]
    1e24:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1e26:	6861      	ldr	r1, [r4, #4]
    1e28:	b159      	cbz	r1, 1e42 <mutex_free_platform+0x2a>
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    1e2a:	f011 0102 	ands.w	r1, r1, #2
    1e2e:	6820      	ldr	r0, [r4, #0]
    1e30:	d008      	beq.n	1e44 <mutex_free_platform+0x2c>
        k_mem_slab_free(&mutex_slab, mutex->mutex);
    1e32:	4601      	mov	r1, r0
    1e34:	4807      	ldr	r0, [pc, #28]	; (1e54 <mutex_free_platform+0x3c>)
    1e36:	f001 fae9 	bl	340c <k_mem_slab_free>
        mutex->mutex = NULL;
    1e3a:	2300      	movs	r3, #0
    1e3c:	6023      	str	r3, [r4, #0]
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    1e3e:	2300      	movs	r3, #0
    1e40:	6063      	str	r3, [r4, #4]
}
    1e42:	bd10      	pop	{r4, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1e44:	2214      	movs	r2, #20
    1e46:	f003 fcf5 	bl	5834 <memset>
    1e4a:	e7f8      	b.n	1e3e <mutex_free_platform+0x26>
    1e4c:	20000068 	.word	0x20000068
    1e50:	00006428 	.word	0x00006428
    1e54:	200002d0 	.word	0x200002d0

00001e58 <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1e58:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    1e5a:	4604      	mov	r4, r0
    1e5c:	b918      	cbnz	r0, 1e66 <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    1e5e:	4b14      	ldr	r3, [pc, #80]	; (1eb0 <mutex_init_platform+0x58>)
    1e60:	4814      	ldr	r0, [pc, #80]	; (1eb4 <mutex_init_platform+0x5c>)
    1e62:	685b      	ldr	r3, [r3, #4]
    1e64:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID &&
    1e66:	6863      	ldr	r3, [r4, #4]
    1e68:	b9cb      	cbnz	r3, 1e9e <mutex_init_platform+0x46>
    1e6a:	6823      	ldr	r3, [r4, #0]
    1e6c:	b9bb      	cbnz	r3, 1e9e <mutex_init_platform+0x46>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    1e6e:	f04f 32ff 	mov.w	r2, #4294967295
    1e72:	f04f 33ff 	mov.w	r3, #4294967295
    1e76:	4621      	mov	r1, r4
    1e78:	480f      	ldr	r0, [pc, #60]	; (1eb8 <mutex_init_platform+0x60>)
    1e7a:	f001 fa95 	bl	33a8 <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    1e7e:	b908      	cbnz	r0, 1e84 <mutex_init_platform+0x2c>
    1e80:	6823      	ldr	r3, [r4, #0]
    1e82:	b91b      	cbnz	r3, 1e8c <mutex_init_platform+0x34>
            platform_abort_apis.abort_fn(
    1e84:	4b0a      	ldr	r3, [pc, #40]	; (1eb0 <mutex_init_platform+0x58>)
    1e86:	480d      	ldr	r0, [pc, #52]	; (1ebc <mutex_init_platform+0x64>)
    1e88:	685b      	ldr	r3, [r3, #4]
    1e8a:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1e8c:	2214      	movs	r2, #20
    1e8e:	2100      	movs	r1, #0
    1e90:	6820      	ldr	r0, [r4, #0]
    1e92:	f003 fccf 	bl	5834 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    1e96:	6863      	ldr	r3, [r4, #4]
    1e98:	f043 0302 	orr.w	r3, r3, #2
    1e9c:	6063      	str	r3, [r4, #4]
    p_mutex = (struct k_mutex *)mutex->mutex;
    1e9e:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    1ea0:	f003 fd93 	bl	59ca <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    1ea4:	6863      	ldr	r3, [r4, #4]
    1ea6:	f043 0301 	orr.w	r3, r3, #1
    1eaa:	6063      	str	r3, [r4, #4]
}
    1eac:	bd10      	pop	{r4, pc}
    1eae:	bf00      	nop
    1eb0:	20000068 	.word	0x20000068
    1eb4:	00006428 	.word	0x00006428
    1eb8:	200002d0 	.word	0x200002d0
    1ebc:	0000644e 	.word	0x0000644e

00001ec0 <mutex_lock_platform>:
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1ec0:	b508      	push	{r3, lr}
    if(mutex == NULL) {
    1ec2:	b168      	cbz	r0, 1ee0 <mutex_lock_platform+0x20>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1ec4:	6843      	ldr	r3, [r0, #4]
    1ec6:	b173      	cbz	r3, 1ee6 <mutex_lock_platform+0x26>
    p_mutex = (struct k_mutex *)mutex->mutex;
    1ec8:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_lock(mutex, timeout);
    1eca:	f04f 33ff 	mov.w	r3, #4294967295
    1ece:	f04f 32ff 	mov.w	r2, #4294967295
    1ed2:	f001 fac5 	bl	3460 <z_impl_k_mutex_lock>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
    1ed6:	4b05      	ldr	r3, [pc, #20]	; (1eec <mutex_lock_platform+0x2c>)
    if (ret == 0) {
    1ed8:	2800      	cmp	r0, #0
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
    1eda:	bf18      	it	ne
    1edc:	4618      	movne	r0, r3
}
    1ede:	bd08      	pop	{r3, pc}
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1ee0:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1ee4:	e7fb      	b.n	1ede <mutex_lock_platform+0x1e>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1ee6:	4802      	ldr	r0, [pc, #8]	; (1ef0 <mutex_lock_platform+0x30>)
    1ee8:	e7f9      	b.n	1ede <mutex_lock_platform+0x1e>
    1eea:	bf00      	nop
    1eec:	ffff8fe9 	.word	0xffff8fe9
    1ef0:	ffff8fea 	.word	0xffff8fea

00001ef4 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    1ef4:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    1ef6:	4906      	ldr	r1, [pc, #24]	; (1f10 <nrf_cc3xx_platform_mutex_init+0x1c>)
    1ef8:	2340      	movs	r3, #64	; 0x40
    1efa:	2214      	movs	r2, #20
    1efc:	4805      	ldr	r0, [pc, #20]	; (1f14 <nrf_cc3xx_platform_mutex_init+0x20>)
    1efe:	f003 fd49 	bl	5994 <k_mem_slab_init>
            mutex_slab_buffer,
            sizeof(struct k_mutex),
            NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    1f02:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    1f06:	4904      	ldr	r1, [pc, #16]	; (1f18 <nrf_cc3xx_platform_mutex_init+0x24>)
    1f08:	4804      	ldr	r0, [pc, #16]	; (1f1c <nrf_cc3xx_platform_mutex_init+0x28>)
    1f0a:	f002 bba7 	b.w	465c <nrf_cc3xx_platform_set_mutexes>
    1f0e:	bf00      	nop
    1f10:	200002ec 	.word	0x200002ec
    1f14:	200002d0 	.word	0x200002d0
    1f18:	00005fd4 	.word	0x00005fd4
    1f1c:	00005fc4 	.word	0x00005fc4

00001f20 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    1f20:	4a09      	ldr	r2, [pc, #36]	; (1f48 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    1f22:	490a      	ldr	r1, [pc, #40]	; (1f4c <arch_swap+0x2c>)
	_current->arch.basepri = key;
    1f24:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    1f26:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    1f28:	6798      	str	r0, [r3, #120]	; 0x78
	_current->arch.swap_return_value = _k_neg_eagain;
    1f2a:	67d9      	str	r1, [r3, #124]	; 0x7c

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1f2c:	4908      	ldr	r1, [pc, #32]	; (1f50 <arch_swap+0x30>)
    1f2e:	684b      	ldr	r3, [r1, #4]
    1f30:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1f34:	604b      	str	r3, [r1, #4]
    1f36:	2300      	movs	r3, #0
    1f38:	f383 8811 	msr	BASEPRI, r3
    1f3c:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    1f40:	6893      	ldr	r3, [r2, #8]
}
    1f42:	6fd8      	ldr	r0, [r3, #124]	; 0x7c
    1f44:	4770      	bx	lr
    1f46:	bf00      	nop
    1f48:	2000080c 	.word	0x2000080c
    1f4c:	00006048 	.word	0x00006048
    1f50:	e000ed00 	.word	0xe000ed00

00001f54 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    1f54:	4913      	ldr	r1, [pc, #76]	; (1fa4 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    1f56:	688a      	ldr	r2, [r1, #8]

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    1f58:	f04f 0038 	mov.w	r0, #56	; 0x38
    add r0, r2
    1f5c:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    1f5e:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    1f62:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1f66:	2020      	movs	r0, #32
    msr BASEPRI, r0
    1f68:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    1f6c:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    1f70:	4f0d      	ldr	r7, [pc, #52]	; (1fa8 <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    1f72:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    1f76:	6a8a      	ldr	r2, [r1, #40]	; 0x28

    str r2, [r1, #_kernel_offset_to_current]
    1f78:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    1f7a:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    1f7c:	6f90      	ldr	r0, [r2, #120]	; 0x78
    movs r3, #0
    1f7e:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    1f80:	6793      	str	r3, [r2, #120]	; 0x78
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    1f82:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    1f86:	f102 0038 	add.w	r0, r2, #56	; 0x38
    ldmia r0, {v1-v8, ip}
    1f8a:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    1f8e:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    1f92:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    1f96:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    1f98:	f003 fbaf 	bl	56fa <configure_builtin_stack_guard>
    pop {r2, lr}
    1f9c:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (_IntExit or z_arm_svc)
     */
    bx lr
    1fa0:	4770      	bx	lr
    1fa2:	0000      	.short	0x0000
    ldr r1, =_kernel
    1fa4:	2000080c 	.word	0x2000080c
    ldr v4, =_SCS_ICSR
    1fa8:	e000ed04 	.word	0xe000ed04

00001fac <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
    1fac:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1fb0:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1fb2:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    1fb6:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    1fba:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1fbc:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1fc0:	2902      	cmp	r1, #2
    beq _oops
    1fc2:	d0ff      	beq.n	1fc4 <_oops>

00001fc4 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1fc4:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    1fc6:	f003 fb9e 	bl	5706 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    1fca:	bd01      	pop	{r0, pc}

00001fcc <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1fcc:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    1fce:	2b00      	cmp	r3, #0
    1fd0:	db08      	blt.n	1fe4 <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1fd2:	2201      	movs	r2, #1
    1fd4:	f000 001f 	and.w	r0, r0, #31
    1fd8:	fa02 f000 	lsl.w	r0, r2, r0
    1fdc:	4a02      	ldr	r2, [pc, #8]	; (1fe8 <arch_irq_enable+0x1c>)
    1fde:	095b      	lsrs	r3, r3, #5
    1fe0:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    1fe4:	4770      	bx	lr
    1fe6:	bf00      	nop
    1fe8:	e000e100 	.word	0xe000e100

00001fec <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    1fec:	4b05      	ldr	r3, [pc, #20]	; (2004 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x4>)
    1fee:	0942      	lsrs	r2, r0, #5
    1ff0:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1ff4:	2301      	movs	r3, #1
    1ff6:	f000 001f 	and.w	r0, r0, #31
    1ffa:	fa03 f000 	lsl.w	r0, r3, r0
}
    1ffe:	4010      	ands	r0, r2
    2000:	4770      	bx	lr
    2002:	bf00      	nop
    2004:	e000e100 	.word	0xe000e100

00002008 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    2008:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    200a:	2b00      	cmp	r3, #0
	prio += _IRQ_PRIO_OFFSET;
    200c:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2010:	bfac      	ite	ge
    2012:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2016:	4b06      	ldrlt	r3, [pc, #24]	; (2030 <z_arm_irq_priority_set+0x28>)
    2018:	ea4f 1141 	mov.w	r1, r1, lsl #5
    201c:	b2c9      	uxtb	r1, r1
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    201e:	bfab      	itete	ge
    2020:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2024:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2028:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    202c:	5419      	strblt	r1, [r3, r0]
}
    202e:	4770      	bx	lr
    2030:	e000ed14 	.word	0xe000ed14

00002034 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    2034:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    2038:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    203a:	490b      	ldr	r1, [pc, #44]	; (2068 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    203c:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    2040:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    2042:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    2046:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    204a:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    204c:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    2050:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    2054:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    2058:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    205c:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    205e:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    2060:	6582      	str	r2, [r0, #88]	; 0x58
	thread->arch.basepri = 0;
    2062:	6783      	str	r3, [r0, #120]	; 0x78
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    2064:	4770      	bx	lr
    2066:	bf00      	nop
    2068:	0000519f 	.word	0x0000519f

0000206c <arch_switch_to_main_thread>:
#endif
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    206c:	b508      	push	{r3, lr}
    206e:	4604      	mov	r4, r0
    2070:	460e      	mov	r6, r1
    2072:	4615      	mov	r5, r2
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
    2074:	2300      	movs	r3, #0
    2076:	eee1 3a10 	vmsr	fpscr, r3
	z_arm_configure_static_mpu_regions();
    207a:	f000 fa51 	bl	2520 <z_arm_configure_static_mpu_regions>
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    207e:	4b09      	ldr	r3, [pc, #36]	; (20a4 <arch_switch_to_main_thread+0x38>)
    2080:	609c      	str	r4, [r3, #8]
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    2082:	6ea3      	ldr	r3, [r4, #104]	; 0x68
    2084:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    2088:	4628      	mov	r0, r5
    208a:	f386 8809 	msr	PSP, r6
    208e:	2100      	movs	r1, #0
    2090:	b663      	cpsie	if
    2092:	f381 8811 	msr	BASEPRI, r1
    2096:	f3bf 8f6f 	isb	sy
    209a:	2200      	movs	r2, #0
    209c:	2300      	movs	r3, #0
    209e:	f003 f87e 	bl	519e <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    20a2:	bf00      	nop
    20a4:	2000080c 	.word	0x2000080c

000020a8 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    20a8:	4901      	ldr	r1, [pc, #4]	; (20b0 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    20aa:	2210      	movs	r2, #16
	str	r2, [r1]
    20ac:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    20ae:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    20b0:	e000ed10 	.word	0xe000ed10

000020b4 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    20b4:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    20b6:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    20b8:	f380 8811 	msr	BASEPRI, r0
	isb
    20bc:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    20c0:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    20c4:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    20c6:	b662      	cpsie	i
	isb
    20c8:	f3bf 8f6f 	isb	sy

	bx	lr
    20cc:	4770      	bx	lr
    20ce:	bf00      	nop

000020d0 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    20d0:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    20d2:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    20d4:	f381 8811 	msr	BASEPRI, r1

	wfe
    20d8:	bf20      	wfe

	msr	BASEPRI, r0
    20da:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    20de:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    20e0:	4770      	bx	lr
    20e2:	bf00      	nop

000020e4 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    20e4:	bf30      	wfi
    b z_SysNmiOnReset
    20e6:	f7ff bffd 	b.w	20e4 <z_SysNmiOnReset>
    20ea:	bf00      	nop

000020ec <z_arm_prep_c>:
#else
#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
#endif
static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    20ec:	4a17      	ldr	r2, [pc, #92]	; (214c <z_arm_prep_c+0x60>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    20ee:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    20f0:	4b17      	ldr	r3, [pc, #92]	; (2150 <z_arm_prep_c+0x64>)
    20f2:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    20f6:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    20f8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    20fc:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    2100:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2104:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    2108:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
    210c:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2110:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
    2114:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	FPU->FPCCR &= (~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk));
    2118:	4a0e      	ldr	r2, [pc, #56]	; (2154 <z_arm_prep_c+0x68>)
    211a:	6853      	ldr	r3, [r2, #4]
    211c:	f023 4340 	bic.w	r3, r3, #3221225472	; 0xc0000000
    2120:	6053      	str	r3, [r2, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    2122:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2126:	f3bf 8f6f 	isb	sy
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
    212a:	2300      	movs	r3, #0
    212c:	eee1 3a10 	vmsr	fpscr, r3
  __ASM volatile ("MRS %0, control" : "=r" (result) );
    2130:	f3ef 8314 	mrs	r3, CONTROL
	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
    2134:	f023 0304 	bic.w	r3, r3, #4
  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
    2138:	f383 8814 	msr	CONTROL, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    213c:	f001 f844 	bl	31c8 <z_bss_zero>
	z_data_copy();
    2140:	f001 f84c 	bl	31dc <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    2144:	f000 f9be 	bl	24c4 <z_arm_interrupt_init>
	z_cstart();
    2148:	f001 f886 	bl	3258 <z_cstart>
    214c:	00000000 	.word	0x00000000
    2150:	e000ed00 	.word	0xe000ed00
    2154:	e000ef30 	.word	0xe000ef30

00002158 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    2158:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    215a:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    215c:	4a0b      	ldr	r2, [pc, #44]	; (218c <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    215e:	6a50      	ldr	r0, [r2, #36]	; 0x24
	cmp r0, #0
    2160:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_sys_power_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    2162:	bf1e      	ittt	ne
	movne	r1, #0
    2164:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    2166:	6251      	strne	r1, [r2, #36]	; 0x24
		blne	z_sys_power_save_idle_exit
    2168:	f003 fc12 	blne	5990 <z_sys_power_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    216c:	b662      	cpsie	i
#endif

#endif /* CONFIG_SYS_POWER_MANAGEMENT */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    216e:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    2172:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    2176:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	 * interface function.
	 */
	cpsie i
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    217a:	4905      	ldr	r1, [pc, #20]	; (2190 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    217c:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    217e:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    2180:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    2182:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    2186:	4903      	ldr	r1, [pc, #12]	; (2194 <_isr_wrapper+0x3c>)
	bx r1
    2188:	4708      	bx	r1
    218a:	0000      	.short	0x0000
	ldr r2, =_kernel
    218c:	2000080c 	.word	0x2000080c
	ldr r1, =_sw_isr_table
    2190:	00005c44 	.word	0x00005c44
	ldr r1, =z_arm_int_exit
    2194:	00002419 	.word	0x00002419

00002198 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    2198:	2000      	movs	r0, #0
    msr CONTROL, r0
    219a:	f380 8814 	msr	CONTROL, r0
    isb
    219e:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
    /* Clear SPLIM registers */
    movs.n r0, #0
    21a2:	2000      	movs	r0, #0
    msr MSPLIM, r0
    21a4:	f380 880a 	msr	MSPLIM, r0
    msr PSPLIM, r0
    21a8:	f380 880b 	msr	PSPLIM, r0
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
    21ac:	f003 f98b 	bl	54c6 <z_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    21b0:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    21b2:	490e      	ldr	r1, [pc, #56]	; (21ec <__start+0x54>)
    str r0, [r1]
    21b4:	6008      	str	r0, [r1, #0]
    dsb
    21b6:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    21ba:	480d      	ldr	r0, [pc, #52]	; (21f0 <__start+0x58>)
    msr msp, r0
    21bc:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    21c0:	f000 f95a 	bl	2478 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    21c4:	2020      	movs	r0, #32
    msr BASEPRI, r0
    21c6:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    21ca:	480a      	ldr	r0, [pc, #40]	; (21f4 <__start+0x5c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    21cc:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    21d0:	1840      	adds	r0, r0, r1
    msr PSP, r0
    21d2:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    21d6:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    21da:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    21dc:	4308      	orrs	r0, r1
    msr CONTROL, r0
    21de:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    21e2:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    21e6:	f7ff ff81 	bl	20ec <z_arm_prep_c>
    21ea:	0000      	.short	0x0000
    ldr r1, =_SCS_MPU_CTRL
    21ec:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    21f0:	20001870 	.word	0x20001870
    ldr r0, =z_interrupt_stacks
    21f4:	200019b0 	.word	0x200019b0

000021f8 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    21f8:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    21fc:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    2200:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    2202:	4672      	mov	r2, lr
	bl z_arm_fault
    2204:	f000 f870 	bl	22e8 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    2208:	bd01      	pop	{r0, pc}
    220a:	bf00      	nop

0000220c <mem_manage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    220c:	4b0c      	ldr	r3, [pc, #48]	; (2240 <mem_manage_fault.isra.0+0x34>)
    220e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    2210:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    2212:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2214:	0792      	lsls	r2, r2, #30
    2216:	d508      	bpl.n	222a <mem_manage_fault.isra.0+0x1e>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		mmfar = SCB->MMFAR;
    2218:	6b5a      	ldr	r2, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    221a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    221c:	0612      	lsls	r2, r2, #24
    221e:	d504      	bpl.n	222a <mem_manage_fault.isra.0+0x1e>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault) {
    2220:	b118      	cbz	r0, 222a <mem_manage_fault.isra.0+0x1e>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    2222:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2224:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    2228:	629a      	str	r2, [r3, #40]	; 0x28

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf);
    222a:	2000      	movs	r0, #0
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    222c:	4b04      	ldr	r3, [pc, #16]	; (2240 <mem_manage_fault.isra.0+0x34>)
    222e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    2230:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_MSTKERR_Msk) {
    2232:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    2234:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2236:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    223a:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    223c:	7008      	strb	r0, [r1, #0]

	return reason;
}
    223e:	4770      	bx	lr
    2240:	e000ed00 	.word	0xe000ed00

00002244 <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    2244:	4b0d      	ldr	r3, [pc, #52]	; (227c <bus_fault.isra.0+0x38>)
    2246:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    2248:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    224a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    224c:	0592      	lsls	r2, r2, #22
    224e:	d508      	bpl.n	2262 <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    2250:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    2252:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2254:	0412      	lsls	r2, r2, #16
    2256:	d504      	bpl.n	2262 <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault) {
    2258:	b118      	cbz	r0, 2262 <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    225a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    225c:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    2260:	629a      	str	r2, [r3, #40]	; 0x28
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;

	*recoverable = memory_fault_recoverable(esf);
    2262:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    2264:	4b05      	ldr	r3, [pc, #20]	; (227c <bus_fault.isra.0+0x38>)
    2266:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    2268:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    226a:	05d2      	lsls	r2, r2, #23
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    226c:	bf58      	it	pl
    226e:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2270:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2272:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    2276:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    2278:	7008      	strb	r0, [r1, #0]

	return reason;
}
    227a:	4770      	bx	lr
    227c:	e000ed00 	.word	0xe000ed00

00002280 <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    2280:	4b09      	ldr	r3, [pc, #36]	; (22a8 <usage_fault.isra.0+0x28>)
    2282:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    2284:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    2286:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    2288:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    228a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    228c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    228e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    2290:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    2292:	f410 1080 	ands.w	r0, r0, #1048576	; 0x100000
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    2296:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    229a:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
    229e:	bf18      	it	ne
    22a0:	2002      	movne	r0, #2
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    22a2:	629a      	str	r2, [r3, #40]	; 0x28
}
    22a4:	4770      	bx	lr
    22a6:	bf00      	nop
    22a8:	e000ed00 	.word	0xe000ed00

000022ac <secure_fault.isra.0>:
 */
static void secure_fault(const z_arch_esf_t *esf)
{
	PR_FAULT_INFO("***** SECURE FAULT *****");

	STORE_xFAR(sfar, SAU->SFAR);
    22ac:	4b0d      	ldr	r3, [pc, #52]	; (22e4 <secure_fault.isra.0+0x38>)
    22ae:	699a      	ldr	r2, [r3, #24]
	if ((SAU->SFSR & SAU_SFSR_SFARVALID_Msk) != 0) {
    22b0:	695a      	ldr	r2, [r3, #20]
		PR_EXC("  Address: 0x%x", sfar);
	}

	/* bits are sticky: they stack and must be reset */
	if ((SAU->SFSR & SAU_SFSR_INVEP_Msk) != 0) {
    22b2:	695a      	ldr	r2, [r3, #20]
    22b4:	07d0      	lsls	r0, r2, #31
    22b6:	d40f      	bmi.n	22d8 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid entry point");
	} else if ((SAU->SFSR & SAU_SFSR_INVIS_Msk) != 0) {
    22b8:	695a      	ldr	r2, [r3, #20]
    22ba:	0791      	lsls	r1, r2, #30
    22bc:	d40c      	bmi.n	22d8 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid integrity signature");
	} else if ((SAU->SFSR & SAU_SFSR_INVER_Msk) != 0) {
    22be:	695a      	ldr	r2, [r3, #20]
    22c0:	0752      	lsls	r2, r2, #29
    22c2:	d409      	bmi.n	22d8 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid exception return");
	} else if ((SAU->SFSR & SAU_SFSR_AUVIOL_Msk) != 0) {
    22c4:	695a      	ldr	r2, [r3, #20]
    22c6:	0710      	lsls	r0, r2, #28
    22c8:	d406      	bmi.n	22d8 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Attribution unit violation");
	} else if ((SAU->SFSR & SAU_SFSR_INVTRAN_Msk) != 0) {
    22ca:	695a      	ldr	r2, [r3, #20]
    22cc:	06d1      	lsls	r1, r2, #27
    22ce:	d403      	bmi.n	22d8 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid transition");
	} else if ((SAU->SFSR & SAU_SFSR_LSPERR_Msk) != 0) {
    22d0:	695a      	ldr	r2, [r3, #20]
    22d2:	0692      	lsls	r2, r2, #26
		PR_FAULT_INFO("  Lazy state preservation");
	} else if ((SAU->SFSR & SAU_SFSR_LSERR_Msk) != 0) {
    22d4:	bf58      	it	pl
    22d6:	695a      	ldrpl	r2, [r3, #20]
		PR_FAULT_INFO("  Lazy state error");
	}

	/* clear SFSR sticky bits */
	SAU->SFSR |= 0xFF;
    22d8:	695a      	ldr	r2, [r3, #20]
    22da:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    22de:	615a      	str	r2, [r3, #20]
}
    22e0:	4770      	bx	lr
    22e2:	bf00      	nop
    22e4:	e000edd0 	.word	0xe000edd0

000022e8 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    22e8:	b5f0      	push	{r4, r5, r6, r7, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    22ea:	4b41      	ldr	r3, [pc, #260]	; (23f0 <z_arm_fault+0x108>)
    22ec:	2500      	movs	r5, #0
    22ee:	685b      	ldr	r3, [r3, #4]
{
    22f0:	b08b      	sub	sp, #44	; 0x2c
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    22f2:	f3c3 0308 	ubfx	r3, r3, #0, #9
    22f6:	f385 8811 	msr	BASEPRI, r5
    22fa:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    22fe:	f002 447f 	and.w	r4, r2, #4278190080	; 0xff000000
    2302:	f1b4 4f7f 	cmp.w	r4, #4278190080	; 0xff000000
    2306:	d11e      	bne.n	2346 <z_arm_fault+0x5e>
	if ((exc_return & EXC_RETURN_EXCEPTION_SECURE_Secure) == 0U) {
    2308:	f012 0401 	ands.w	r4, r2, #1
    230c:	d01a      	beq.n	2344 <z_arm_fault+0x5c>
	if (exc_return & EXC_RETURN_RETURN_STACK_Secure) {
    230e:	0656      	lsls	r6, r2, #25
    2310:	f002 0408 	and.w	r4, r2, #8
    2314:	d467      	bmi.n	23e6 <z_arm_fault+0xfe>
		if (exc_return & EXC_RETURN_SPSEL_PROCESS) {
    2316:	f082 0204 	eor.w	r2, r2, #4
    231a:	f3c2 0580 	ubfx	r5, r2, #2, #1
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    231e:	b164      	cbz	r4, 233a <z_arm_fault+0x52>
  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
    2320:	f3ef 8689 	mrs	r6, PSP_NS
	*recoverable = false;
    2324:	2200      	movs	r2, #0
    2326:	3b03      	subs	r3, #3
    2328:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    232c:	2b04      	cmp	r3, #4
    232e:	d84b      	bhi.n	23c8 <z_arm_fault+0xe0>
    2330:	e8df f003 	tbb	[pc, r3]
    2334:	41504c0b 	.word	0x41504c0b
    2338:	48          	.byte	0x48
    2339:	00          	.byte	0x00
  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
    233a:	f3ef 8688 	mrs	r6, MSP_NS
  return(result);
    233e:	e7f1      	b.n	2324 <z_arm_fault+0x3c>
			ptr_esf =  (z_arch_esf_t *)psp;
    2340:	460e      	mov	r6, r1
    2342:	e7ef      	b.n	2324 <z_arm_fault+0x3c>
	*nested_exc = false;
    2344:	4625      	mov	r5, r4
		return NULL;
    2346:	462e      	mov	r6, r5
    2348:	e7ec      	b.n	2324 <z_arm_fault+0x3c>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    234a:	4b29      	ldr	r3, [pc, #164]	; (23f0 <z_arm_fault+0x108>)
    234c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    234e:	0792      	lsls	r2, r2, #30
    2350:	d43a      	bmi.n	23c8 <z_arm_fault+0xe0>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    2352:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    2354:	f014 4480 	ands.w	r4, r4, #1073741824	; 0x40000000
    2358:	d008      	beq.n	236c <z_arm_fault+0x84>
		if (SCB_MMFSR != 0) {
    235a:	3328      	adds	r3, #40	; 0x28
    235c:	781b      	ldrb	r3, [r3, #0]
    235e:	b1eb      	cbz	r3, 239c <z_arm_fault+0xb4>
			reason = mem_manage_fault(esf, 1, recoverable);
    2360:	2001      	movs	r0, #1
    2362:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    2366:	f7ff ff51 	bl	220c <mem_manage_fault.isra.0>
    236a:	4604      	mov	r4, r0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    236c:	f89d 3007 	ldrb.w	r3, [sp, #7]
    2370:	b993      	cbnz	r3, 2398 <z_arm_fault+0xb0>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    2372:	2220      	movs	r2, #32
    2374:	4631      	mov	r1, r6
    2376:	a802      	add	r0, sp, #8
    2378:	f003 fa31 	bl	57de <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    237c:	9b09      	ldr	r3, [sp, #36]	; 0x24
    237e:	b36d      	cbz	r5, 23dc <z_arm_fault+0xf4>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    2380:	f3c3 0208 	ubfx	r2, r3, #0, #9
    2384:	b922      	cbnz	r2, 2390 <z_arm_fault+0xa8>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    2386:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    238a:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    238e:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    2390:	4620      	mov	r0, r4
    2392:	a902      	add	r1, sp, #8
    2394:	f003 f9b5 	bl	5702 <z_arm_fatal_error>
}
    2398:	b00b      	add	sp, #44	; 0x2c
    239a:	bdf0      	pop	{r4, r5, r6, r7, pc}
		} else if (SCB_BFSR != 0) {
    239c:	4b15      	ldr	r3, [pc, #84]	; (23f4 <z_arm_fault+0x10c>)
    239e:	781b      	ldrb	r3, [r3, #0]
    23a0:	b12b      	cbz	r3, 23ae <z_arm_fault+0xc6>
			reason = bus_fault(esf, 1, recoverable);
    23a2:	2001      	movs	r0, #1
    23a4:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
    23a8:	f7ff ff4c 	bl	2244 <bus_fault.isra.0>
    23ac:	e7dd      	b.n	236a <z_arm_fault+0x82>
		} else if (SCB_UFSR != 0) {
    23ae:	4b12      	ldr	r3, [pc, #72]	; (23f8 <z_arm_fault+0x110>)
    23b0:	881f      	ldrh	r7, [r3, #0]
    23b2:	b2bf      	uxth	r7, r7
    23b4:	b117      	cbz	r7, 23bc <z_arm_fault+0xd4>
		reason = usage_fault(esf);
    23b6:	f7ff ff63 	bl	2280 <usage_fault.isra.0>
    23ba:	e7d6      	b.n	236a <z_arm_fault+0x82>
		} else if (SAU->SFSR != 0) {
    23bc:	4b0f      	ldr	r3, [pc, #60]	; (23fc <z_arm_fault+0x114>)
    23be:	695c      	ldr	r4, [r3, #20]
    23c0:	2c00      	cmp	r4, #0
    23c2:	d0d3      	beq.n	236c <z_arm_fault+0x84>
		secure_fault(esf);
    23c4:	f7ff ff72 	bl	22ac <secure_fault.isra.0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    23c8:	2400      	movs	r4, #0
    23ca:	e7cf      	b.n	236c <z_arm_fault+0x84>
		reason = mem_manage_fault(esf, 0, recoverable);
    23cc:	2000      	movs	r0, #0
    23ce:	f10d 0107 	add.w	r1, sp, #7
    23d2:	e7c8      	b.n	2366 <z_arm_fault+0x7e>
		reason = bus_fault(esf, 0, recoverable);
    23d4:	2000      	movs	r0, #0
    23d6:	f10d 0107 	add.w	r1, sp, #7
    23da:	e7e5      	b.n	23a8 <z_arm_fault+0xc0>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    23dc:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    23e0:	f023 0301 	bic.w	r3, r3, #1
    23e4:	e7d3      	b.n	238e <z_arm_fault+0xa6>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    23e6:	2c00      	cmp	r4, #0
    23e8:	d1aa      	bne.n	2340 <z_arm_fault+0x58>
			ptr_esf = (z_arch_esf_t *)msp;
    23ea:	4606      	mov	r6, r0
			*nested_exc = true;
    23ec:	2501      	movs	r5, #1
    23ee:	e799      	b.n	2324 <z_arm_fault+0x3c>
    23f0:	e000ed00 	.word	0xe000ed00
    23f4:	e000ed29 	.word	0xe000ed29
    23f8:	e000ed2a 	.word	0xe000ed2a
    23fc:	e000edd0 	.word	0xe000edd0

00002400 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    2400:	4b04      	ldr	r3, [pc, #16]	; (2414 <z_arm_fault_init+0x14>)
    2402:	695a      	ldr	r2, [r3, #20]
    2404:	f042 0210 	orr.w	r2, r2, #16
    2408:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    240a:	695a      	ldr	r2, [r3, #20]
    240c:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    2410:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    2412:	4770      	bx	lr
    2414:	e000ed00 	.word	0xe000ed00

00002418 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    2418:	4b04      	ldr	r3, [pc, #16]	; (242c <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    241a:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    241c:	6a98      	ldr	r0, [r3, #40]	; 0x28
	cmp r0, r1
    241e:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    2420:	d003      	beq.n	242a <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    2422:	4903      	ldr	r1, [pc, #12]	; (2430 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    2424:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    2428:	600a      	str	r2, [r1, #0]

0000242a <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    242a:	4770      	bx	lr
	ldr r3, =_kernel
    242c:	2000080c 	.word	0x2000080c
	ldr r1, =_SCS_ICSR
    2430:	e000ed04 	.word	0xe000ed04

00002434 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    2434:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2438:	4905      	ldr	r1, [pc, #20]	; (2450 <sys_arch_reboot+0x1c>)
    243a:	4b06      	ldr	r3, [pc, #24]	; (2454 <sys_arch_reboot+0x20>)
    243c:	68ca      	ldr	r2, [r1, #12]
    243e:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2442:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2444:	60cb      	str	r3, [r1, #12]
    2446:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    244a:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    244c:	e7fd      	b.n	244a <sys_arch_reboot+0x16>
    244e:	bf00      	nop
    2450:	e000ed00 	.word	0xe000ed00
    2454:	05fa0004 	.word	0x05fa0004

00002458 <z_arm_clear_arm_mpu_config>:
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);

	for (i = 0; i < num_regions; i++) {
    2458:	2300      	movs	r3, #0
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
  mpu->RNR = rnr;
  mpu->RLAR = 0U;
    245a:	4618      	mov	r0, r3
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    245c:	4a05      	ldr	r2, [pc, #20]	; (2474 <z_arm_clear_arm_mpu_config+0x1c>)
    245e:	6811      	ldr	r1, [r2, #0]
	int num_regions =
    2460:	f3c1 2107 	ubfx	r1, r1, #8, #8
	for (i = 0; i < num_regions; i++) {
    2464:	428b      	cmp	r3, r1
    2466:	d100      	bne.n	246a <z_arm_clear_arm_mpu_config+0x12>
		ARM_MPU_ClrRegion(i);
	}
}
    2468:	4770      	bx	lr
  mpu->RNR = rnr;
    246a:	6093      	str	r3, [r2, #8]
  mpu->RLAR = 0U;
    246c:	6110      	str	r0, [r2, #16]
	for (i = 0; i < num_regions; i++) {
    246e:	3301      	adds	r3, #1
    2470:	e7f8      	b.n	2464 <z_arm_clear_arm_mpu_config+0xc>
    2472:	bf00      	nop
    2474:	e000ed90 	.word	0xe000ed90

00002478 <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    2478:	b510      	push	{r4, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    247a:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    247c:	2400      	movs	r4, #0
    247e:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    2482:	f7ff ffe9 	bl	2458 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    2486:	4a0e      	ldr	r2, [pc, #56]	; (24c0 <z_arm_init_arch_hw_at_boot+0x48>)
	z_arm_clear_arm_mpu_config();
    2488:	4623      	mov	r3, r4
    248a:	4611      	mov	r1, r2
		NVIC->ICER[i] = 0xFFFFFFFF;
    248c:	f04f 34ff 	mov.w	r4, #4294967295
    2490:	f103 0020 	add.w	r0, r3, #32
    2494:	3301      	adds	r3, #1
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    2496:	2b10      	cmp	r3, #16
		NVIC->ICER[i] = 0xFFFFFFFF;
    2498:	f842 4020 	str.w	r4, [r2, r0, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    249c:	d1f8      	bne.n	2490 <z_arm_init_arch_hw_at_boot+0x18>
    249e:	2300      	movs	r3, #0
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    24a0:	f04f 30ff 	mov.w	r0, #4294967295
    24a4:	f103 0260 	add.w	r2, r3, #96	; 0x60
    24a8:	3301      	adds	r3, #1
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    24aa:	2b10      	cmp	r3, #16
		NVIC->ICPR[i] = 0xFFFFFFFF;
    24ac:	f841 0022 	str.w	r0, [r1, r2, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    24b0:	d1f8      	bne.n	24a4 <z_arm_init_arch_hw_at_boot+0x2c>
  __ASM volatile ("cpsie i" : : : "memory");
    24b2:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    24b4:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    24b8:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    24bc:	bd10      	pop	{r4, pc}
    24be:	bf00      	nop
    24c0:	e000e100 	.word	0xe000e100

000024c4 <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    24c4:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    24c6:	2120      	movs	r1, #32
    24c8:	4803      	ldr	r0, [pc, #12]	; (24d8 <z_arm_interrupt_init+0x14>)
    24ca:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    24cc:	3301      	adds	r3, #1
    24ce:	2b41      	cmp	r3, #65	; 0x41
    24d0:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    24d4:	d1f9      	bne.n	24ca <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    24d6:	4770      	bx	lr
    24d8:	e000e100 	.word	0xe000e100

000024dc <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    24dc:	b508      	push	{r3, lr}
	if (_current == thread) {
    24de:	4b0e      	ldr	r3, [pc, #56]	; (2518 <z_impl_k_thread_abort+0x3c>)
    24e0:	689b      	ldr	r3, [r3, #8]
    24e2:	4283      	cmp	r3, r0
    24e4:	d107      	bne.n	24f6 <z_impl_k_thread_abort+0x1a>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    24e6:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    24ea:	b193      	cbz	r3, 2512 <z_impl_k_thread_abort+0x36>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    24ec:	4a0b      	ldr	r2, [pc, #44]	; (251c <z_impl_k_thread_abort+0x40>)
    24ee:	6853      	ldr	r3, [r2, #4]
    24f0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    24f4:	6053      	str	r3, [r2, #4]
		} else {
			z_self_abort(); /* Never returns */
		}
	}

	z_thread_single_abort(thread);
    24f6:	f001 fa39 	bl	396c <z_thread_single_abort>
	__asm__ volatile(
    24fa:	f04f 0320 	mov.w	r3, #32
    24fe:	f3ef 8011 	mrs	r0, BASEPRI
    2502:	f383 8811 	msr	BASEPRI, r3
    2506:	f3bf 8f6f 	isb	sy

	/* The abort handler might have altered the ready queue. */
	z_reschedule_unlocked();
}
    250a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void) z_pend_curr_irqlock(arch_irq_lock(), wait_q, timeout);
}

static inline void z_reschedule_unlocked(void)
{
	(void) z_reschedule_irqlock(arch_irq_lock());
    250e:	f003 ba63 	b.w	59d8 <z_reschedule_irqlock>
			z_self_abort(); /* Never returns */
    2512:	f001 fccb 	bl	3eac <z_self_abort>
    2516:	bf00      	nop
    2518:	2000080c 	.word	0x2000080c
    251c:	e000ed00 	.word	0xe000ed00

00002520 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    2520:	b510      	push	{r4, lr}
		.size = (uint32_t)&_nocache_ram_size,
		.attr = K_MEM_PARTITION_P_RW_U_NA_NOCACHE,
		};
#endif /* CONFIG_NOCACHE_MEMORY */
#if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
		const struct k_mem_partition ramfunc_region =
    2522:	4b0e      	ldr	r3, [pc, #56]	; (255c <z_arm_configure_static_mpu_regions+0x3c>)
{
    2524:	b088      	sub	sp, #32
		const struct k_mem_partition ramfunc_region =
    2526:	9302      	str	r3, [sp, #8]
    2528:	4b0d      	ldr	r3, [pc, #52]	; (2560 <z_arm_configure_static_mpu_regions+0x40>)
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    252a:	4c0e      	ldr	r4, [pc, #56]	; (2564 <z_arm_configure_static_mpu_regions+0x44>)
		const struct k_mem_partition ramfunc_region =
    252c:	9303      	str	r3, [sp, #12]
    252e:	4b0e      	ldr	r3, [pc, #56]	; (2568 <z_arm_configure_static_mpu_regions+0x48>)
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    2530:	4a0e      	ldr	r2, [pc, #56]	; (256c <z_arm_configure_static_mpu_regions+0x4c>)
		const struct k_mem_partition ramfunc_region =
    2532:	9304      	str	r3, [sp, #16]
	const struct k_mem_partition *static_regions[] = {
    2534:	ab02      	add	r3, sp, #8
    2536:	9301      	str	r3, [sp, #4]
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    2538:	a801      	add	r0, sp, #4
    253a:	4623      	mov	r3, r4
    253c:	2101      	movs	r1, #1
    253e:	f000 f907 	bl	2750 <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of k_mem_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct k_mem_partition dyn_region_areas[] = {
    2542:	2300      	movs	r3, #0
    2544:	9307      	str	r3, [sp, #28]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    2546:	4b0a      	ldr	r3, [pc, #40]	; (2570 <z_arm_configure_static_mpu_regions+0x50>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    2548:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    254a:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    254c:	a805      	add	r0, sp, #20
	const struct k_mem_partition dyn_region_areas[] = {
    254e:	9305      	str	r3, [sp, #20]
    2550:	9406      	str	r4, [sp, #24]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    2552:	f000 f907 	bl	2764 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    2556:	b008      	add	sp, #32
    2558:	bd10      	pop	{r4, pc}
    255a:	bf00      	nop
    255c:	20000000 	.word	0x20000000
    2560:	00000000 	.word	0x00000000
    2564:	20010000 	.word	0x20010000
    2568:	00010006 	.word	0x00010006
    256c:	20000000 	.word	0x20000000
    2570:	20000158 	.word	0x20000158

00002574 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    2574:	b510      	push	{r4, lr}
	ARM_MPU_SetRegion(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
    2576:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    2578:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    257a:	f023 021f 	bic.w	r2, r3, #31
		| (region_conf->attr.rbar &
    257e:	f004 031f 	and.w	r3, r4, #31
    2582:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    2584:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    2586:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    2588:	f023 031f 	bic.w	r3, r3, #31
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/   
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
  mpu->RNR = rnr;
    258c:	4904      	ldr	r1, [pc, #16]	; (25a0 <region_init+0x2c>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    258e:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    2592:	f043 0301 	orr.w	r3, r3, #1
    2596:	6088      	str	r0, [r1, #8]
  mpu->RBAR = rbar;
    2598:	60ca      	str	r2, [r1, #12]
  mpu->RLAR = rlar;
    259a:	610b      	str	r3, [r1, #16]
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    259c:	bd10      	pop	{r4, pc}
    259e:	bf00      	nop
    25a0:	e000ed90 	.word	0xe000ed90

000025a4 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct k_mem_partition
    25a4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    25a8:	4607      	mov	r7, r0
    25aa:	4688      	mov	r8, r1
    25ac:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    25ae:	2600      	movs	r6, #0
	MPU->RNR = index;
    25b0:	4d4a      	ldr	r5, [pc, #296]	; (26dc <mpu_configure_regions_and_partition.constprop.0+0x138>)
static int mpu_configure_regions_and_partition(const struct k_mem_partition
    25b2:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
    25b4:	4546      	cmp	r6, r8
    25b6:	da0b      	bge.n	25d0 <mpu_configure_regions_and_partition.constprop.0+0x2c>
		if (regions[i]->size == 0U) {
    25b8:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
    25bc:	f8d3 9004 	ldr.w	r9, [r3, #4]
    25c0:	f1b9 0f00 	cmp.w	r9, #0
    25c4:	d03a      	beq.n	263c <mpu_configure_regions_and_partition.constprop.0+0x98>
		&&
    25c6:	f1b9 0f1f 	cmp.w	r9, #31
    25ca:	d805      	bhi.n	25d8 <mpu_configure_regions_and_partition.constprop.0+0x34>

			reg_index =
				mpu_configure_region(reg_index, regions[i]);

			if (reg_index == -EINVAL) {
				return reg_index;
    25cc:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
    25d0:	4620      	mov	r0, r4
    25d2:	b005      	add	sp, #20
    25d4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		&&
    25d8:	f019 0f1f 	tst.w	r9, #31
    25dc:	d1f6      	bne.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
		((part->start &
    25de:	f8d3 a000 	ldr.w	sl, [r3]
		&&
    25e2:	f01a 0f1f 	tst.w	sl, #31
    25e6:	d1f1      	bne.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    25e8:	4650      	mov	r0, sl
    25ea:	f003 f8b4 	bl	5756 <arm_cmse_mpu_region_get>
    25ee:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    25f0:	eb09 000a 	add.w	r0, r9, sl
    25f4:	3801      	subs	r0, #1
    25f6:	f003 f8ae 	bl	5756 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    25fa:	4583      	cmp	fp, r0
    25fc:	d1e6      	bne.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
		if ((u_reg_index == -EINVAL) ||
    25fe:	f11b 0f16 	cmn.w	fp, #22
    2602:	d0e3      	beq.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
			(u_reg_index > (reg_index - 1))) {
    2604:	1e63      	subs	r3, r4, #1
		if ((u_reg_index == -EINVAL) ||
    2606:	455b      	cmp	r3, fp
    2608:	dbe0      	blt.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
    260a:	f8c5 b008 	str.w	fp, [r5, #8]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    260e:	68e8      	ldr	r0, [r5, #12]
	MPU->RNR = index;
    2610:	f8c5 b008 	str.w	fp, [r5, #8]
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    2614:	692b      	ldr	r3, [r5, #16]
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    2616:	f857 1026 	ldr.w	r1, [r7, r6, lsl #2]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    261a:	f020 001f 	bic.w	r0, r0, #31
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    261e:	f043 0a1f 	orr.w	sl, r3, #31
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    2622:	e9d1 3200 	ldrd	r3, r2, [r1]
    2626:	441a      	add	r2, r3
		if ((regions[i]->start == u_reg_base) &&
    2628:	4298      	cmp	r0, r3
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    262a:	f102 39ff 	add.w	r9, r2, #4294967295
		if ((regions[i]->start == u_reg_base) &&
    262e:	d118      	bne.n	2662 <mpu_configure_regions_and_partition.constprop.0+0xbe>
    2630:	45ca      	cmp	sl, r9
    2632:	d105      	bne.n	2640 <mpu_configure_regions_and_partition.constprop.0+0x9c>
			mpu_configure_region(u_reg_index, regions[i]);
    2634:	fa5f f08b 	uxtb.w	r0, fp
    2638:	f003 f870 	bl	571c <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    263c:	3601      	adds	r6, #1
    263e:	e7b9      	b.n	25b4 <mpu_configure_regions_and_partition.constprop.0+0x10>
	MPU->RNR = index;
    2640:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    2644:	68eb      	ldr	r3, [r5, #12]
		| (base & MPU_RBAR_BASE_Msk);
    2646:	f022 021f 	bic.w	r2, r2, #31
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    264a:	f003 031f 	and.w	r3, r3, #31
		| (base & MPU_RBAR_BASE_Msk);
    264e:	431a      	orrs	r2, r3
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    2650:	60ea      	str	r2, [r5, #12]
				mpu_configure_region(reg_index, regions[i]);
    2652:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, regions[i]);
    2654:	f003 f862 	bl	571c <mpu_configure_region>
			if (reg_index == -EINVAL) {
    2658:	f110 0f16 	cmn.w	r0, #22
    265c:	d0b6      	beq.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
			reg_index++;
    265e:	1c44      	adds	r4, r0, #1
    2660:	e7ec      	b.n	263c <mpu_configure_regions_and_partition.constprop.0+0x98>
	MPU->RNR = index;
    2662:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    2666:	692a      	ldr	r2, [r5, #16]
    2668:	3b01      	subs	r3, #1
    266a:	f023 031f 	bic.w	r3, r3, #31
    266e:	f002 021f 	and.w	r2, r2, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    2672:	4313      	orrs	r3, r2
		} else if (reg_last == u_reg_last) {
    2674:	45ca      	cmp	sl, r9
    2676:	b2e0      	uxtb	r0, r4
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    2678:	612b      	str	r3, [r5, #16]
		} else if (reg_last == u_reg_last) {
    267a:	d0eb      	beq.n	2654 <mpu_configure_regions_and_partition.constprop.0+0xb0>
				mpu_configure_region(reg_index, regions[i]);
    267c:	f003 f84e 	bl	571c <mpu_configure_region>
			if (reg_index == -EINVAL) {
    2680:	f110 0f16 	cmn.w	r0, #22
    2684:	d0a2      	beq.n	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
    2686:	f8c5 b008 	str.w	fp, [r5, #8]
	attr->rbar = MPU->RBAR &
    268a:	68ea      	ldr	r2, [r5, #12]
    268c:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i]->start +
    2690:	f10a 3aff 	add.w	sl, sl, #4294967295
	attr->rbar = MPU->RBAR &
    2694:	f362 0304 	bfi	r3, r2, #0, #5
    2698:	f88d 3008 	strb.w	r3, [sp, #8]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    269c:	692b      	ldr	r3, [r5, #16]
    269e:	f89d 2008 	ldrb.w	r2, [sp, #8]
    26a2:	085b      	lsrs	r3, r3, #1
    26a4:	f363 1247 	bfi	r2, r3, #5, #3
			fill_region.base = regions[i]->start +
    26a8:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    26ac:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i]->start +
    26b0:	e9d3 1300 	ldrd	r1, r3, [r3]
    26b4:	440b      	add	r3, r1
    26b6:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i]->start +
    26b8:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
    26bc:	3001      	adds	r0, #1
			REGION_LIMIT_ADDR((regions[i]->start +
    26be:	4453      	add	r3, sl
    26c0:	eba3 0309 	sub.w	r3, r3, r9
    26c4:	b2c0      	uxtb	r0, r0
    26c6:	f023 031f 	bic.w	r3, r3, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1U)) {
    26ca:	280f      	cmp	r0, #15
			fill_region.attr.r_limit =
    26cc:	9303      	str	r3, [sp, #12]
    26ce:	f63f af7d 	bhi.w	25cc <mpu_configure_regions_and_partition.constprop.0+0x28>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    26d2:	4669      	mov	r1, sp
    26d4:	f7ff ff4e 	bl	2574 <region_init>
    26d8:	e7c1      	b.n	265e <mpu_configure_regions_and_partition.constprop.0+0xba>
    26da:	bf00      	nop
    26dc:	e000ed90 	.word	0xe000ed90

000026e0 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    26e0:	2205      	movs	r2, #5
    26e2:	4b03      	ldr	r3, [pc, #12]	; (26f0 <arm_core_mpu_enable+0x10>)
    26e4:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    26e6:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    26ea:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    26ee:	4770      	bx	lr
    26f0:	e000ed90 	.word	0xe000ed90

000026f4 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
    26f4:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    26f8:	2200      	movs	r2, #0
    26fa:	4b01      	ldr	r3, [pc, #4]	; (2700 <arm_core_mpu_disable+0xc>)
    26fc:	605a      	str	r2, [r3, #4]
}
    26fe:	4770      	bx	lr
    2700:	e000ed90 	.word	0xe000ed90

00002704 <arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
static int arm_mpu_init(const struct device *arg)
{
    2704:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    2706:	4c0e      	ldr	r4, [pc, #56]	; (2740 <arm_mpu_init+0x3c>)
    2708:	6825      	ldr	r5, [r4, #0]
    270a:	2d10      	cmp	r5, #16
    270c:	d814      	bhi.n	2738 <arm_mpu_init+0x34>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    270e:	f7ff fff1 	bl	26f4 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2712:	2000      	movs	r0, #0
	MPU->MAIR0 =
    2714:	4b0b      	ldr	r3, [pc, #44]	; (2744 <arm_mpu_init+0x40>)
    2716:	4a0c      	ldr	r2, [pc, #48]	; (2748 <arm_mpu_init+0x44>)
    2718:	631a      	str	r2, [r3, #48]	; 0x30
    271a:	4285      	cmp	r5, r0
    271c:	d105      	bne.n	272a <arm_mpu_init+0x26>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    271e:	4b0b      	ldr	r3, [pc, #44]	; (274c <arm_mpu_init+0x48>)
    2720:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    2722:	f7ff ffdd 	bl	26e0 <arm_core_mpu_enable>
	__ASSERT(
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */
	return 0;
    2726:	2000      	movs	r0, #0
}
    2728:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    272a:	6861      	ldr	r1, [r4, #4]
    272c:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    2730:	f7ff ff20 	bl	2574 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2734:	3001      	adds	r0, #1
    2736:	e7f0      	b.n	271a <arm_mpu_init+0x16>
		return -1;
    2738:	f04f 30ff 	mov.w	r0, #4294967295
    273c:	e7f4      	b.n	2728 <arm_mpu_init+0x24>
    273e:	bf00      	nop
    2740:	00005fe8 	.word	0x00005fe8
    2744:	e000ed90 	.word	0xe000ed90
    2748:	0044ffaa 	.word	0x0044ffaa
    274c:	2000086c 	.word	0x2000086c

00002750 <arm_core_mpu_configure_static_mpu_regions>:
{
    2750:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct k_mem_partition
	*static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    2752:	4c03      	ldr	r4, [pc, #12]	; (2760 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    2754:	7822      	ldrb	r2, [r4, #0]
    2756:	f7ff ff25 	bl	25a4 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    275a:	7020      	strb	r0, [r4, #0]
}
    275c:	bd10      	pop	{r4, pc}
    275e:	bf00      	nop
    2760:	2000086c 	.word	0x2000086c

00002764 <arm_core_mpu_mark_areas_for_dynamic_regions>:
{
    2764:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2768:	4d26      	ldr	r5, [pc, #152]	; (2804 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>)
    276a:	468a      	mov	sl, r1
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    276c:	4606      	mov	r6, r0
    276e:	f04f 0800 	mov.w	r8, #0
    2772:	46ab      	mov	fp, r5
	MPU->RNR = index;
    2774:	4f24      	ldr	r7, [pc, #144]	; (2808 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa4>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    2776:	45d0      	cmp	r8, sl
    2778:	da1b      	bge.n	27b2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
    277a:	f8d6 9004 	ldr.w	r9, [r6, #4]
    277e:	f1b9 0f00 	cmp.w	r9, #0
    2782:	d039      	beq.n	27f8 <arm_core_mpu_mark_areas_for_dynamic_regions+0x94>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    2784:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    2786:	4608      	mov	r0, r1
    2788:	9101      	str	r1, [sp, #4]
    278a:	f002 ffe4 	bl	5756 <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    278e:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    2790:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    2792:	eb09 0001 	add.w	r0, r9, r1
    2796:	3801      	subs	r0, #1
    2798:	f002 ffdd 	bl	5756 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    279c:	4284      	cmp	r4, r0
    279e:	f04f 0214 	mov.w	r2, #20
    27a2:	4b1a      	ldr	r3, [pc, #104]	; (280c <arm_core_mpu_mark_areas_for_dynamic_regions+0xa8>)
    27a4:	d008      	beq.n	27b8 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
    27a6:	f06f 0315 	mvn.w	r3, #21
    27aa:	fb02 f808 	mul.w	r8, r2, r8
    27ae:	f84b 3008 	str.w	r3, [fp, r8]
}
    27b2:	b003      	add	sp, #12
    27b4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    27b8:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    27bc:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    27be:	d0f8      	beq.n	27b2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    27c0:	7819      	ldrb	r1, [r3, #0]
    27c2:	42a1      	cmp	r1, r4
    27c4:	ddf5      	ble.n	27b2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = MPU->RBAR &
    27c6:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = index;
    27ca:	60bc      	str	r4, [r7, #8]
	MPU->RNR = index;
    27cc:	60bc      	str	r4, [r7, #8]
	attr->rbar = MPU->RBAR &
    27ce:	68fc      	ldr	r4, [r7, #12]
    27d0:	f100 0108 	add.w	r1, r0, #8
    27d4:	7b00      	ldrb	r0, [r0, #12]
    27d6:	f364 0004 	bfi	r0, r4, #0, #5
    27da:	7108      	strb	r0, [r1, #4]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    27dc:	6938      	ldr	r0, [r7, #16]
    27de:	790c      	ldrb	r4, [r1, #4]
    27e0:	0840      	lsrs	r0, r0, #1
    27e2:	f360 1447 	bfi	r4, r0, #5, #3
    27e6:	710c      	strb	r4, [r1, #4]
	region_conf->base = (MPU->RBAR & MPU_RBAR_BASE_Msk);
    27e8:	68f9      	ldr	r1, [r7, #12]
    27ea:	f021 011f 	bic.w	r1, r1, #31
    27ee:	6069      	str	r1, [r5, #4]
	region_conf->attr.r_limit = MPU->RLAR & MPU_RLAR_LIMIT_Msk;
    27f0:	6939      	ldr	r1, [r7, #16]
    27f2:	f021 011f 	bic.w	r1, r1, #31
    27f6:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    27f8:	f108 0801 	add.w	r8, r8, #1
    27fc:	3514      	adds	r5, #20
    27fe:	360c      	adds	r6, #12
    2800:	e7b9      	b.n	2776 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    2802:	bf00      	nop
    2804:	200007ec 	.word	0x200007ec
    2808:	e000ed90 	.word	0xe000ed90
    280c:	2000086c 	.word	0x2000086c

00002810 <tz_nonsecure_state_setup>:
}
#endif /* CONFIG_ARMV8_M_MAINLINE */

void tz_nonsecure_state_setup(const tz_nonsecure_setup_conf_t *p_ns_conf)
{
	configure_nonsecure_vtor_offset(p_ns_conf->vtor_ns);
    2810:	6882      	ldr	r2, [r0, #8]
	SCB_NS->VTOR = vtor_ns;
    2812:	4b0c      	ldr	r3, [pc, #48]	; (2844 <tz_nonsecure_state_setup+0x34>)
    2814:	609a      	str	r2, [r3, #8]
  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
    2816:	6803      	ldr	r3, [r0, #0]
    2818:	f383 8888 	msr	MSP_NS, r3
  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
    281c:	6843      	ldr	r3, [r0, #4]
    281e:	f383 8889 	msr	PSP_NS, r3
	configure_nonsecure_psp(p_ns_conf->psp_ns);
	/* Select which stack-pointer to use (MSP or PSP) and
	 * the privilege level for thread mode.
	 */
	configure_nonsecure_control(p_ns_conf->control_ns.spsel,
		p_ns_conf->control_ns.npriv);
    2822:	7b02      	ldrb	r2, [r0, #12]
    2824:	f002 0101 	and.w	r1, r2, #1
  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
    2828:	f3ef 8394 	mrs	r3, CONTROL_NS
	control_ns &= ~(CONTROL_SPSEL_Msk | CONTROL_nPRIV_Msk);
    282c:	f023 0303 	bic.w	r3, r3, #3
	if (spsel_ns) {
    2830:	0792      	lsls	r2, r2, #30
		control_ns |= CONTROL_SPSEL_Msk;
    2832:	bf48      	it	mi
    2834:	f043 0302 	orrmi.w	r3, r3, #2
	if (npriv_ns) {
    2838:	b109      	cbz	r1, 283e <tz_nonsecure_state_setup+0x2e>
		control_ns |= CONTROL_nPRIV_Msk;
    283a:	f043 0301 	orr.w	r3, r3, #1
  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
    283e:	f383 8894 	msr	CONTROL_NS, r3
}
    2842:	4770      	bx	lr
    2844:	e002ed00 	.word	0xe002ed00

00002848 <tz_nbanked_exception_target_state_set>:

void tz_nbanked_exception_target_state_set(int secure_state)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2848:	4a08      	ldr	r2, [pc, #32]	; (286c <tz_nbanked_exception_target_state_set+0x24>)
    284a:	68d3      	ldr	r3, [r2, #12]
	if (secure_state) {
    284c:	b148      	cbz	r0, 2862 <tz_nbanked_exception_target_state_set+0x1a>
		aircr_payload &= ~(SCB_AIRCR_BFHFNMINS_Msk);
    284e:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
    2852:	041b      	lsls	r3, r3, #16
    2854:	0c1b      	lsrs	r3, r3, #16
	} else {
		aircr_payload |= SCB_AIRCR_BFHFNMINS_Msk;
	}
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    2856:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    285a:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
    285e:	60d3      	str	r3, [r2, #12]
}
    2860:	4770      	bx	lr
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2862:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_BFHFNMINS_Msk;
    2864:	f443 5300 	orr.w	r3, r3, #8192	; 0x2000
    2868:	e7f5      	b.n	2856 <tz_nbanked_exception_target_state_set+0xe>
    286a:	bf00      	nop
    286c:	e000ed00 	.word	0xe000ed00

00002870 <tz_nonsecure_exception_prio_config>:

void tz_nonsecure_exception_prio_config(int secure_boost)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2870:	4a08      	ldr	r2, [pc, #32]	; (2894 <tz_nonsecure_exception_prio_config+0x24>)
    2872:	68d3      	ldr	r3, [r2, #12]
	if (secure_boost) {
    2874:	b140      	cbz	r0, 2888 <tz_nonsecure_exception_prio_config+0x18>
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2876:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_PRIS_Msk;
    2878:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
	} else {
		aircr_payload &= ~(SCB_AIRCR_PRIS_Msk);
	}
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    287c:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    2880:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
    2884:	60d3      	str	r3, [r2, #12]
}
    2886:	4770      	bx	lr
		aircr_payload &= ~(SCB_AIRCR_PRIS_Msk);
    2888:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
    288c:	041b      	lsls	r3, r3, #16
    288e:	0c1b      	lsrs	r3, r3, #16
    2890:	e7f4      	b.n	287c <tz_nonsecure_exception_prio_config+0xc>
    2892:	bf00      	nop
    2894:	e000ed00 	.word	0xe000ed00

00002898 <tz_nonsecure_system_reset_req_block>:

void tz_nonsecure_system_reset_req_block(int block)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2898:	4a08      	ldr	r2, [pc, #32]	; (28bc <tz_nonsecure_system_reset_req_block+0x24>)
    289a:	68d3      	ldr	r3, [r2, #12]
	if (block) {
    289c:	b140      	cbz	r0, 28b0 <tz_nonsecure_system_reset_req_block+0x18>
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    289e:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_SYSRESETREQS_Msk;
    28a0:	f043 0308 	orr.w	r3, r3, #8
	} else {
		aircr_payload &= ~(SCB_AIRCR_SYSRESETREQS_Msk);
	}
	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    28a4:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    28a8:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)
    28ac:	60d3      	str	r3, [r2, #12]
}
    28ae:	4770      	bx	lr
		aircr_payload &= ~(SCB_AIRCR_SYSRESETREQS_Msk);
    28b0:	f023 0308 	bic.w	r3, r3, #8
    28b4:	041b      	lsls	r3, r3, #16
    28b6:	0c1b      	lsrs	r3, r3, #16
    28b8:	e7f4      	b.n	28a4 <tz_nonsecure_system_reset_req_block+0xc>
    28ba:	bf00      	nop
    28bc:	e000ed00 	.word	0xe000ed00

000028c0 <tz_nonsecure_fpu_access_enable>:

#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
void tz_nonsecure_fpu_access_enable(void)
{
	SCB->NSACR |=
    28c0:	4a03      	ldr	r2, [pc, #12]	; (28d0 <tz_nonsecure_fpu_access_enable+0x10>)
    28c2:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
    28c6:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
    28ca:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
		(1UL << SCB_NSACR_CP10_Pos) | (1UL << SCB_NSACR_CP11_Pos);
}
    28ce:	4770      	bx	lr
    28d0:	e000ed00 	.word	0xe000ed00

000028d4 <tz_sau_configure>:
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

void tz_sau_configure(int enable, int allns)
{
	if (enable) {
    28d4:	4b08      	ldr	r3, [pc, #32]	; (28f8 <tz_sau_configure+0x24>)
  \brief   Enable SAU
  \details Enables the Security Attribution Unit (SAU).
 */
__STATIC_INLINE void TZ_SAU_Enable(void)
{
    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
    28d6:	681a      	ldr	r2, [r3, #0]
    28d8:	b118      	cbz	r0, 28e2 <tz_sau_configure+0xe>
    28da:	f042 0201 	orr.w	r2, r2, #1
	} else {
		TZ_SAU_Disable();
		if (allns) {
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
		} else {
			SAU->CTRL &= ~(SAU_CTRL_ALLNS_Msk);
    28de:	601a      	str	r2, [r3, #0]
		}
	}
}
    28e0:	4770      	bx	lr
  \brief   Disable SAU
  \details Disables the Security Attribution Unit (SAU).
 */
__STATIC_INLINE void TZ_SAU_Disable(void)
{
    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
    28e2:	f022 0201 	bic.w	r2, r2, #1
    28e6:	601a      	str	r2, [r3, #0]
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
    28e8:	681a      	ldr	r2, [r3, #0]
		if (allns) {
    28ea:	b111      	cbz	r1, 28f2 <tz_sau_configure+0x1e>
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
    28ec:	f042 0202 	orr.w	r2, r2, #2
    28f0:	e7f5      	b.n	28de <tz_sau_configure+0xa>
			SAU->CTRL &= ~(SAU_CTRL_ALLNS_Msk);
    28f2:	f022 0202 	bic.w	r2, r2, #2
    28f6:	e7f2      	b.n	28de <tz_sau_configure+0xa>
    28f8:	e000edd0 	.word	0xe000edd0

000028fc <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    28fc:	4b01      	ldr	r3, [pc, #4]	; (2904 <__stdout_hook_install+0x8>)
    28fe:	6018      	str	r0, [r3, #0]
}
    2900:	4770      	bx	lr
    2902:	bf00      	nop
    2904:	20000024 	.word	0x20000024

00002908 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    2908:	b5f0      	push	{r4, r5, r6, r7, lr}
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    290a:	794b      	ldrb	r3, [r1, #5]
    290c:	2b01      	cmp	r3, #1
    290e:	d029      	beq.n	2964 <uarte_nrfx_configure+0x5c>
    2910:	2b03      	cmp	r3, #3
    2912:	d124      	bne.n	295e <uarte_nrfx_configure+0x56>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    2914:	2610      	movs	r6, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    2916:	798b      	ldrb	r3, [r1, #6]
    2918:	2b03      	cmp	r3, #3
    291a:	d120      	bne.n	295e <uarte_nrfx_configure+0x56>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    291c:	79cc      	ldrb	r4, [r1, #7]
    291e:	b124      	cbz	r4, 292a <uarte_nrfx_configure+0x22>
    2920:	2c01      	cmp	r4, #1
    2922:	d11c      	bne.n	295e <uarte_nrfx_configure+0x56>
	case UART_CFG_FLOW_CTRL_NONE:
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
		break;
	case UART_CFG_FLOW_CTRL_RTS_CTS:
		if (get_dev_config(dev)->rts_cts_pins_set) {
    2924:	6843      	ldr	r3, [r0, #4]
    2926:	791b      	ldrb	r3, [r3, #4]
    2928:	b1cb      	cbz	r3, 295e <uarte_nrfx_configure+0x56>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    292a:	790a      	ldrb	r2, [r1, #4]
    292c:	b112      	cbz	r2, 2934 <uarte_nrfx_configure+0x2c>
    292e:	2a02      	cmp	r2, #2
    2930:	d115      	bne.n	295e <uarte_nrfx_configure+0x56>
	case UART_CFG_PARITY_NONE:
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
		break;
	case UART_CFG_PARITY_EVEN:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    2932:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    2934:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    2936:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    2938:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    293c:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    293e:	d065      	beq.n	2a0c <uarte_nrfx_configure+0x104>
    2940:	d82d      	bhi.n	299e <uarte_nrfx_configure+0x96>
    2942:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    2946:	d064      	beq.n	2a12 <uarte_nrfx_configure+0x10a>
    2948:	d816      	bhi.n	2978 <uarte_nrfx_configure+0x70>
    294a:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    294e:	d062      	beq.n	2a16 <uarte_nrfx_configure+0x10e>
    2950:	d80a      	bhi.n	2968 <uarte_nrfx_configure+0x60>
    2952:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    2956:	d061      	beq.n	2a1c <uarte_nrfx_configure+0x114>
    2958:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    295c:	d061      	beq.n	2a22 <uarte_nrfx_configure+0x11a>
    295e:	f06f 0022 	mvn.w	r0, #34	; 0x22
    2962:	e052      	b.n	2a0a <uarte_nrfx_configure+0x102>
	switch (cfg->stop_bits) {
    2964:	2600      	movs	r6, #0
    2966:	e7d6      	b.n	2916 <uarte_nrfx_configure+0xe>
	switch (baudrate) {
    2968:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    296c:	d05c      	beq.n	2a28 <uarte_nrfx_configure+0x120>
    296e:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    2972:	d1f4      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    2974:	4b37      	ldr	r3, [pc, #220]	; (2a54 <uarte_nrfx_configure+0x14c>)
    2976:	e03c      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    2978:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    297c:	d057      	beq.n	2a2e <uarte_nrfx_configure+0x126>
    297e:	d807      	bhi.n	2990 <uarte_nrfx_configure+0x88>
    2980:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    2984:	d055      	beq.n	2a32 <uarte_nrfx_configure+0x12a>
    2986:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    298a:	d1e8      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    298c:	4b32      	ldr	r3, [pc, #200]	; (2a58 <uarte_nrfx_configure+0x150>)
    298e:	e030      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    2990:	f647 2712 	movw	r7, #31250	; 0x7a12
    2994:	42bb      	cmp	r3, r7
    2996:	d1e2      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    2998:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    299c:	e029      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    299e:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    29a2:	d048      	beq.n	2a36 <uarte_nrfx_configure+0x12e>
    29a4:	d813      	bhi.n	29ce <uarte_nrfx_configure+0xc6>
    29a6:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    29aa:	d047      	beq.n	2a3c <uarte_nrfx_configure+0x134>
    29ac:	d809      	bhi.n	29c2 <uarte_nrfx_configure+0xba>
    29ae:	f64d 27c0 	movw	r7, #56000	; 0xdac0
    29b2:	42bb      	cmp	r3, r7
    29b4:	d044      	beq.n	2a40 <uarte_nrfx_configure+0x138>
    29b6:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    29ba:	d1d0      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    29bc:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    29c0:	e017      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    29c2:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    29c6:	d1ca      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    29c8:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    29cc:	e011      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    29ce:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    29d2:	d038      	beq.n	2a46 <uarte_nrfx_configure+0x13e>
    29d4:	d808      	bhi.n	29e8 <uarte_nrfx_configure+0xe0>
    29d6:	4f21      	ldr	r7, [pc, #132]	; (2a5c <uarte_nrfx_configure+0x154>)
    29d8:	42bb      	cmp	r3, r7
    29da:	d037      	beq.n	2a4c <uarte_nrfx_configure+0x144>
    29dc:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    29e0:	d1bd      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    29e2:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    29e6:	e004      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    29e8:	4f1d      	ldr	r7, [pc, #116]	; (2a60 <uarte_nrfx_configure+0x158>)
    29ea:	42bb      	cmp	r3, r7
    29ec:	d1b7      	bne.n	295e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    29ee:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    29f2:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;
    29f6:	68c3      	ldr	r3, [r0, #12]
                    | (uint32_t)p_cfg->hwfc;
    29f8:	4334      	orrs	r4, r6
    29fa:	4322      	orrs	r2, r4
    29fc:	3304      	adds	r3, #4
    29fe:	c903      	ldmia	r1, {r0, r1}
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    2a00:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    2a04:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    2a08:	2000      	movs	r0, #0
}
    2a0a:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    2a0c:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    2a10:	e7ef      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2a12:	4b14      	ldr	r3, [pc, #80]	; (2a64 <uarte_nrfx_configure+0x15c>)
    2a14:	e7ed      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    2a16:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    2a1a:	e7ea      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = 0x00014000;
    2a1c:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    2a20:	e7e7      	b.n	29f2 <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    2a22:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    2a26:	e7e4      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    2a28:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    2a2c:	e7e1      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2a2e:	4b0e      	ldr	r3, [pc, #56]	; (2a68 <uarte_nrfx_configure+0x160>)
    2a30:	e7df      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    2a32:	4b0e      	ldr	r3, [pc, #56]	; (2a6c <uarte_nrfx_configure+0x164>)
    2a34:	e7dd      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    2a36:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    2a3a:	e7da      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    2a3c:	4b0c      	ldr	r3, [pc, #48]	; (2a70 <uarte_nrfx_configure+0x168>)
    2a3e:	e7d8      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2a40:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    2a44:	e7d5      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    2a46:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    2a4a:	e7d2      	b.n	29f2 <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    2a4c:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2a50:	e7cf      	b.n	29f2 <uarte_nrfx_configure+0xea>
    2a52:	bf00      	nop
    2a54:	0013b000 	.word	0x0013b000
    2a58:	004ea000 	.word	0x004ea000
    2a5c:	0003d090 	.word	0x0003d090
    2a60:	000f4240 	.word	0x000f4240
    2a64:	00275000 	.word	0x00275000
    2a68:	0075c000 	.word	0x0075c000
    2a6c:	003af000 	.word	0x003af000
    2a70:	013a9000 	.word	0x013a9000

00002a74 <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    2a74:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2a78:	4606      	mov	r6, r0
    2a7a:	4688      	mov	r8, r1
	struct uarte_nrfx_data *data = get_dev_data(dev);
    2a7c:	68c7      	ldr	r7, [r0, #12]
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2a7e:	f003 f857 	bl	5b30 <k_is_in_isr>
    2a82:	b9b8      	cbnz	r0, 2ab4 <uarte_nrfx_poll_out+0x40>
	return !z_sys_post_kernel;
    2a84:	4b28      	ldr	r3, [pc, #160]	; (2b28 <uarte_nrfx_poll_out+0xb4>)
    2a86:	781b      	ldrb	r3, [r3, #0]
    2a88:	f083 0301 	eor.w	r3, r3, #1
	return config->uarte_regs;
    2a8c:	6872      	ldr	r2, [r6, #4]
    2a8e:	6815      	ldr	r5, [r2, #0]
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
	if (data->pm_state != DEVICE_PM_ACTIVE_STATE) {
		return;
	}
#endif
	if (isr_mode) {
    2a90:	b193      	cbz	r3, 2ab8 <uarte_nrfx_poll_out+0x44>
    2a92:	f04f 0320 	mov.w	r3, #32
    2a96:	f3ef 8411 	mrs	r4, BASEPRI
    2a9a:	f383 8811 	msr	BASEPRI, r3
    2a9e:	f3bf 8f6f 	isb	sy
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
    2aa2:	4630      	mov	r0, r6
    2aa4:	f002 ff1b 	bl	58de <is_tx_ready>
    2aa8:	bb38      	cbnz	r0, 2afa <uarte_nrfx_poll_out+0x86>
	__asm__ volatile(
    2aaa:	f384 8811 	msr	BASEPRI, r4
    2aae:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    2ab2:	e7ee      	b.n	2a92 <uarte_nrfx_poll_out+0x1e>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2ab4:	2301      	movs	r3, #1
    2ab6:	e7e9      	b.n	2a8c <uarte_nrfx_poll_out+0x18>
    2ab8:	2464      	movs	r4, #100	; 0x64
	} else {
		do {
			/* wait arbitrary time before back off. */
			bool res;

			NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    2aba:	4630      	mov	r0, r6
    2abc:	f002 ff0f 	bl	58de <is_tx_ready>
    2ac0:	b970      	cbnz	r0, 2ae0 <uarte_nrfx_poll_out+0x6c>
    2ac2:	2001      	movs	r0, #1
    2ac4:	f002 ff3b 	bl	593e <nrfx_busy_wait>
    2ac8:	3c01      	subs	r4, #1
    2aca:	d1f6      	bne.n	2aba <uarte_nrfx_poll_out+0x46>
	return z_impl_k_sleep(timeout);
    2acc:	2100      	movs	r1, #0
    2ace:	2021      	movs	r0, #33	; 0x21
    2ad0:	f001 f8ee 	bl	3cb0 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    2ad4:	e7f0      	b.n	2ab8 <uarte_nrfx_poll_out+0x44>
	__asm__ volatile(
    2ad6:	f384 8811 	msr	BASEPRI, r4
    2ada:	f3bf 8f6f 	isb	sy
}
    2ade:	e7f5      	b.n	2acc <uarte_nrfx_poll_out+0x58>
	__asm__ volatile(
    2ae0:	f04f 0320 	mov.w	r3, #32
    2ae4:	f3ef 8411 	mrs	r4, BASEPRI
    2ae8:	f383 8811 	msr	BASEPRI, r3
    2aec:	f3bf 8f6f 	isb	sy

			if (res) {
				key = irq_lock();
				if (is_tx_ready(dev)) {
    2af0:	4630      	mov	r0, r6
    2af2:	f002 fef4 	bl	58de <is_tx_ready>
    2af6:	2800      	cmp	r0, #0
    2af8:	d0ed      	beq.n	2ad6 <uarte_nrfx_poll_out+0x62>
NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t  const * p_buffer,
                                               size_t           length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    p_reg->TXD.MAXCNT = length;
    2afa:	2301      	movs	r3, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2afc:	2200      	movs	r2, #0
	}

	/* At this point we should have irq locked and any previous transfer
	 * completed. Transfer can be started, no need to wait for completion.
	 */
	data->char_out = c;
    2afe:	f807 8f0c 	strb.w	r8, [r7, #12]!
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2b02:	f8c5 7544 	str.w	r7, [r5, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2b06:	f8c5 3548 	str.w	r3, [r5, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2b0a:	f8c5 2120 	str.w	r2, [r5, #288]	; 0x120
    2b0e:	f8d5 1120 	ldr.w	r1, [r5, #288]	; 0x120
    2b12:	f8c5 2158 	str.w	r2, [r5, #344]	; 0x158
    2b16:	f8d5 2158 	ldr.w	r2, [r5, #344]	; 0x158
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2b1a:	60ab      	str	r3, [r5, #8]
	__asm__ volatile(
    2b1c:	f384 8811 	msr	BASEPRI, r4
    2b20:	f3bf 8f6f 	isb	sy
	tx_start(uarte, &data->char_out, 1);

	irq_unlock(key);
}
    2b24:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    2b28:	2000086d 	.word	0x2000086d

00002b2c <uarte_instance_init.isra.0>:
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2b2c:	f04f 0c00 	mov.w	ip, #0
	return config->uarte_regs;
    2b30:	6843      	ldr	r3, [r0, #4]
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));

	return 0;
}

static int uarte_instance_init(const struct device *dev,
    2b32:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
			       const struct uarte_init_config *config,
			       uint8_t interrupts_active)
{
	int err;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);
    2b36:	68c6      	ldr	r6, [r0, #12]
	return config->uarte_regs;
    2b38:	681c      	ldr	r4, [r3, #0]
static int uarte_instance_init(const struct device *dev,
    2b3a:	460f      	mov	r7, r1
    2b3c:	f8c4 c500 	str.w	ip, [r4, #1280]	; 0x500
    2b40:	4605      	mov	r5, r0

	nrf_uarte_disable(uarte);

	data->dev = dev;
    2b42:	6030      	str	r0, [r6, #0]

	nrf_gpio_pin_write(config->pseltxd, 1);
    2b44:	6808      	ldr	r0, [r1, #0]

NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
{
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);

    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2b46:	2101      	movs	r1, #1
}


NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
{
    p_reg->OUTSET = set_mask;
    2b48:	4b3d      	ldr	r3, [pc, #244]	; (2c40 <uarte_instance_init.isra.0+0x114>)
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    2b4a:	f000 021f 	and.w	r2, r0, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2b4e:	4091      	lsls	r1, r2
    p_reg->OUTSET = set_mask;
    2b50:	6099      	str	r1, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2b52:	2103      	movs	r1, #3
    2b54:	3280      	adds	r2, #128	; 0x80
    2b56:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
	nrf_gpio_cfg_output(config->pseltxd);

	if (config->pselrxd !=  NRF_UARTE_PSEL_DISCONNECTED) {
    2b5a:	687a      	ldr	r2, [r7, #4]
    2b5c:	1c51      	adds	r1, r2, #1
    *p_pin = pin_number & 0x1F;
    2b5e:	bf1e      	ittt	ne
    2b60:	f002 011f 	andne.w	r1, r2, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2b64:	3180      	addne	r1, #128	; 0x80
    2b66:	f843 c021 	strne.w	ip, [r3, r1, lsl #2]
		nrf_gpio_cfg_input(config->pselrxd, NRF_GPIO_PIN_NOPULL);
	}

	nrf_uarte_txrx_pins_set(uarte, config->pseltxd, config->pselrxd);

	if (config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
    2b6a:	68b9      	ldr	r1, [r7, #8]
    p_reg->PSEL.TXD = pseltxd;
    2b6c:	f8c4 050c 	str.w	r0, [r4, #1292]	; 0x50c
    2b70:	1c48      	adds	r0, r1, #1
    2b72:	bf18      	it	ne
    2b74:	2000      	movne	r0, #0
    p_reg->PSEL.RXD = pselrxd;
    2b76:	f8c4 2514 	str.w	r2, [r4, #1300]	; 0x514
    *p_pin = pin_number & 0x1F;
    2b7a:	bf1e      	ittt	ne
    2b7c:	f001 021f 	andne.w	r2, r1, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2b80:	3280      	addne	r2, #128	; 0x80
    2b82:	f843 0022 	strne.w	r0, [r3, r2, lsl #2]
		nrf_gpio_cfg_input(config->pselcts, NRF_GPIO_PIN_NOPULL);
	}

	if (config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
    2b86:	68f8      	ldr	r0, [r7, #12]
    2b88:	1c42      	adds	r2, r0, #1
    2b8a:	d00c      	beq.n	2ba6 <uarte_instance_init.isra.0+0x7a>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2b8c:	f04f 0c01 	mov.w	ip, #1
    *p_pin = pin_number & 0x1F;
    2b90:	f000 021f 	and.w	r2, r0, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2b94:	fa0c fc02 	lsl.w	ip, ip, r2
    p_reg->OUTSET = set_mask;
    2b98:	f8c3 c008 	str.w	ip, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2b9c:	f04f 0c03 	mov.w	ip, #3
    2ba0:	3280      	adds	r2, #128	; 0x80
    2ba2:	f843 c022 	str.w	ip, [r3, r2, lsl #2]
    p_reg->PSEL.RTS = pselrts;
    2ba6:	f8c4 0508 	str.w	r0, [r4, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    2baa:	f8c4 1510 	str.w	r1, [r4, #1296]	; 0x510
		nrf_gpio_cfg_output(config->pselrts);
	}

	nrf_uarte_hwfc_pins_set(uarte, config->pselrts, config->pselcts);

	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    2bae:	68e9      	ldr	r1, [r5, #12]
    2bb0:	4628      	mov	r0, r5
    2bb2:	3104      	adds	r1, #4
    2bb4:	f7ff fea8 	bl	2908 <uarte_nrfx_configure>
	if (err) {
    2bb8:	4680      	mov	r8, r0
    2bba:	2800      	cmp	r0, #0
    2bbc:	d139      	bne.n	2c32 <uarte_instance_init.isra.0+0x106>

#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
	data->pm_state = DEVICE_PM_ACTIVE_STATE;
#endif

	if (get_dev_config(dev)->ppi_endtx) {
    2bbe:	686b      	ldr	r3, [r5, #4]
    2bc0:	799b      	ldrb	r3, [r3, #6]
    2bc2:	b19b      	cbz	r3, 2bec <uarte_instance_init.isra.0+0xc0>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    2bc4:	f106 000e 	add.w	r0, r6, #14
    2bc8:	f000 fa3e 	bl	3048 <nrfx_dppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    2bcc:	4b1d      	ldr	r3, [pc, #116]	; (2c44 <uarte_instance_init.isra.0+0x118>)
    2bce:	4298      	cmp	r0, r3
    2bd0:	d132      	bne.n	2c38 <uarte_instance_init.isra.0+0x10c>
}

__STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
{
    NRFX_ASSERT(eep);
    *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2bd2:	7bb3      	ldrb	r3, [r6, #14]
    2bd4:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
    2bd8:	f8c4 31a0 	str.w	r3, [r4, #416]	; 0x1a0
}

__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
{
    NRFX_ASSERT(tep);
    *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2bdc:	f8c4 308c 	str.w	r3, [r4, #140]	; 0x8c
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    2be0:	2301      	movs	r3, #1
    2be2:	7bb2      	ldrb	r2, [r6, #14]
    2be4:	4093      	lsls	r3, r2
    p_reg->CHENCLR = 0xFFFFFFFFuL;
}

NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
    p_reg->CHENSET = mask;
    2be6:	4a18      	ldr	r2, [pc, #96]	; (2c48 <uarte_instance_init.isra.0+0x11c>)
    2be8:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2bec:	2308      	movs	r3, #8
    2bee:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
#endif
	{
		/* Enable receiver and transmitter */
		nrf_uarte_enable(uarte);

		if (config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
    2bf2:	687b      	ldr	r3, [r7, #4]
    2bf4:	3301      	adds	r3, #1
    2bf6:	d00c      	beq.n	2c12 <uarte_instance_init.isra.0+0xe6>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2bf8:	2300      	movs	r3, #0
    2bfa:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    2bfe:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);

			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    2c02:	f106 030d 	add.w	r3, r6, #13

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    2c06:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    2c0a:	2301      	movs	r3, #1
    2c0c:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2c10:	6023      	str	r3, [r4, #0]
			nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
		}
	}

	if (!get_dev_config(dev)->ppi_endtx) {
    2c12:	686b      	ldr	r3, [r5, #4]
    2c14:	799b      	ldrb	r3, [r3, #6]
    2c16:	b91b      	cbnz	r3, 2c20 <uarte_instance_init.isra.0+0xf4>
    p_reg->INTENSET = mask;
    2c18:	f44f 7380 	mov.w	r3, #256	; 0x100
    2c1c:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    p_reg->TXD.MAXCNT = length;
    2c20:	2300      	movs	r3, #0

	/* Set TXSTOPPED event by requesting fake (zero-length) transfer.
	 * Pointer to RAM variable (data->tx_buffer) is set because otherwise
	 * such operation may result in HardFault or RAM corruption.
	 */
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    2c22:	360c      	adds	r6, #12
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2c24:	f8c4 6544 	str.w	r6, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2c28:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2c2c:	2301      	movs	r3, #1
    2c2e:	60a3      	str	r3, [r4, #8]
    2c30:	60e3      	str	r3, [r4, #12]

	/* switch off transmitter to save an energy */
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);

	return 0;
}
    2c32:	4640      	mov	r0, r8
    2c34:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		return -EIO;
    2c38:	f06f 0804 	mvn.w	r8, #4
    2c3c:	e7f9      	b.n	2c32 <uarte_instance_init.isra.0+0x106>
    2c3e:	bf00      	nop
    2c40:	50842500 	.word	0x50842500
    2c44:	0bad0000 	.word	0x0bad0000
    2c48:	50017000 	.word	0x50017000

00002c4c <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    2c4c:	b530      	push	{r4, r5, lr}
    2c4e:	b085      	sub	sp, #20
    2c50:	466c      	mov	r4, sp
    2c52:	4605      	mov	r5, r0
    2c54:	4b08      	ldr	r3, [pc, #32]	; (2c78 <uarte_0_init+0x2c>)
    2c56:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    2c58:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
    2c5c:	2200      	movs	r2, #0
    2c5e:	2101      	movs	r1, #1
    2c60:	2008      	movs	r0, #8
    2c62:	f7ff f9d1 	bl	2008 <z_arm_irq_priority_set>
    2c66:	2008      	movs	r0, #8
    2c68:	f7ff f9b0 	bl	1fcc <arch_irq_enable>
    2c6c:	4621      	mov	r1, r4
    2c6e:	4628      	mov	r0, r5
    2c70:	f7ff ff5c 	bl	2b2c <uarte_instance_init.isra.0>
    2c74:	b005      	add	sp, #20
    2c76:	bd30      	pop	{r4, r5, pc}
    2c78:	00005e5c 	.word	0x00005e5c

00002c7c <uarte_1_init>:
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    2c7c:	b530      	push	{r4, r5, lr}
    2c7e:	b085      	sub	sp, #20
    2c80:	466c      	mov	r4, sp
    2c82:	4605      	mov	r5, r0
    2c84:	4b08      	ldr	r3, [pc, #32]	; (2ca8 <uarte_1_init+0x2c>)
    2c86:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    2c88:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
    2c8c:	2200      	movs	r2, #0
    2c8e:	2101      	movs	r1, #1
    2c90:	2009      	movs	r0, #9
    2c92:	f7ff f9b9 	bl	2008 <z_arm_irq_priority_set>
    2c96:	2009      	movs	r0, #9
    2c98:	f7ff f998 	bl	1fcc <arch_irq_enable>
    2c9c:	4621      	mov	r1, r4
    2c9e:	4628      	mov	r0, r5
    2ca0:	f7ff ff44 	bl	2b2c <uarte_instance_init.isra.0>
    2ca4:	b005      	add	sp, #20
    2ca6:	bd30      	pop	{r4, r5, pc}
    2ca8:	00005e6c 	.word	0x00005e6c

00002cac <check_ext_api_requests>:
	}
};
#endif

static int check_ext_api_requests(const struct device *dev)
{
    2cac:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	(void)dev;

	const struct fw_info_ext_api_request *ext_api_req =
			skip_ext_apis(&m_firmware_info);

	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2cb0:	2500      	movs	r5, #0
			skip_ext_apis(&m_firmware_info);
    2cb2:	4c21      	ldr	r4, [pc, #132]	; (2d38 <check_ext_api_requests+0x8c>)
	const uint32_t ext_api_magic[] = {EXT_API_MAGIC};
    2cb4:	4e21      	ldr	r6, [pc, #132]	; (2d3c <check_ext_api_requests+0x90>)
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2cb6:	f854 8c04 	ldr.w	r8, [r4, #-4]
			/* EXT_API hard requirement not met. */
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
			k_panic();
		} else {
			/* EXT_API soft requirement not met. */
			printk("WARNING: Optional EXT_API request not "
    2cba:	f8df 9088 	ldr.w	r9, [pc, #136]	; 2d44 <check_ext_api_requests+0x98>
{
    2cbe:	b085      	sub	sp, #20
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2cc0:	45a8      	cmp	r8, r5
    2cc2:	d803      	bhi.n	2ccc <check_ext_api_requests+0x20>
		}
		ADVANCE_EXT_API_REQ(ext_api_req);
	}

	return 0;
}
    2cc4:	2000      	movs	r0, #0
    2cc6:	b005      	add	sp, #20
    2cc8:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		if (fw_info_ext_api_check((uint32_t)*(ext_api_req->ext_api))
    2ccc:	6a63      	ldr	r3, [r4, #36]	; 0x24
    2cce:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
    2cd2:	681f      	ldr	r7, [r3, #0]
    2cd4:	ab01      	add	r3, sp, #4
    2cd6:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (memcmp(ext_api->magic, ext_api_magic, CONFIG_FW_INFO_MAGIC_LEN)
    2cda:	220c      	movs	r2, #12
    2cdc:	4619      	mov	r1, r3
    2cde:	4638      	mov	r0, r7
    2ce0:	f002 fd56 	bl	5790 <memcmp>
    2ce4:	b990      	cbnz	r0, 2d0c <check_ext_api_requests+0x60>
    2ce6:	b18f      	cbz	r7, 2d0c <check_ext_api_requests+0x60>
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    2ce8:	6a63      	ldr	r3, [r4, #36]	; 0x24
	const uint32_t req_id = ext_api_req->request.ext_api_id;
    2cea:	6921      	ldr	r1, [r4, #16]
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    2cec:	681b      	ldr	r3, [r3, #0]
	return ((ext_api->ext_api_id == req_id)
    2cee:	691a      	ldr	r2, [r3, #16]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    2cf0:	4291      	cmp	r1, r2
    2cf2:	d10b      	bne.n	2d0c <check_ext_api_requests+0x60>
		&&  (ext_api->ext_api_version >= req_min_version)
    2cf4:	699a      	ldr	r2, [r3, #24]
	const uint32_t req_min_version = ext_api_req->request.ext_api_version;
    2cf6:	69a1      	ldr	r1, [r4, #24]
		&&  (ext_api->ext_api_version >= req_min_version)
    2cf8:	4291      	cmp	r1, r2
    2cfa:	d807      	bhi.n	2d0c <check_ext_api_requests+0x60>
	const uint32_t req_max_version = ext_api_req->ext_api_max_version;
    2cfc:	69e1      	ldr	r1, [r4, #28]
		&&  (ext_api->ext_api_version <  req_max_version)
    2cfe:	4291      	cmp	r1, r2
    2d00:	d904      	bls.n	2d0c <check_ext_api_requests+0x60>
	const uint32_t req_flags = ext_api_req->request.ext_api_flags;
    2d02:	6962      	ldr	r2, [r4, #20]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    2d04:	695b      	ldr	r3, [r3, #20]
    2d06:	ea32 0303 	bics.w	r3, r2, r3
    2d0a:	d00a      	beq.n	2d22 <check_ext_api_requests+0x76>
		} else if (ext_api_req->required) {
    2d0c:	6a27      	ldr	r7, [r4, #32]
    2d0e:	b167      	cbz	r7, 2d2a <check_ext_api_requests+0x7e>
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
    2d10:	480b      	ldr	r0, [pc, #44]	; (2d40 <check_ext_api_requests+0x94>)
    2d12:	f002 f98b 	bl	502c <printk>
			k_panic();
    2d16:	4040      	eors	r0, r0
    2d18:	f380 8811 	msr	BASEPRI, r0
    2d1c:	f04f 0004 	mov.w	r0, #4
    2d20:	df02      	svc	2
		ADVANCE_EXT_API_REQ(ext_api_req);
    2d22:	68e3      	ldr	r3, [r4, #12]
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2d24:	3501      	adds	r5, #1
		ADVANCE_EXT_API_REQ(ext_api_req);
    2d26:	441c      	add	r4, r3
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2d28:	e7ca      	b.n	2cc0 <check_ext_api_requests+0x14>
			printk("WARNING: Optional EXT_API request not "
    2d2a:	4648      	mov	r0, r9
    2d2c:	f002 f97e 	bl	502c <printk>
			*ext_api_req->ext_api = NULL;
    2d30:	6a63      	ldr	r3, [r4, #36]	; 0x24
    2d32:	601f      	str	r7, [r3, #0]
    2d34:	e7f5      	b.n	2d22 <check_ext_api_requests+0x76>
    2d36:	bf00      	nop
    2d38:	0000023c 	.word	0x0000023c
    2d3c:	00005e7c 	.word	0x00005e7c
    2d40:	00006491 	.word	0x00006491
    2d44:	000064ba 	.word	0x000064ba

00002d48 <nrf91_errata_14>:
    #ifndef NRF91_SERIES
        return false;
    #else
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
    2d48:	4b05      	ldr	r3, [pc, #20]	; (2d60 <nrf91_errata_14+0x18>)
    2d4a:	6818      	ldr	r0, [r3, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2d4c:	3b04      	subs	r3, #4
        #endif
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            if (var1 == 0x09)
    2d4e:	681b      	ldr	r3, [r3, #0]
    2d50:	2b09      	cmp	r3, #9
    2d52:	d103      	bne.n	2d5c <nrf91_errata_14+0x14>
            {
                switch(var2)
    2d54:	1e43      	subs	r3, r0, #1
    2d56:	4258      	negs	r0, r3
    2d58:	4158      	adcs	r0, r3
    2d5a:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    2d5c:	2000      	movs	r0, #0
    #endif
}
    2d5e:	4770      	bx	lr
    2d60:	00ff0134 	.word	0x00ff0134

00002d64 <SystemInit>:
        /* Perform Secure-mode initialization routines. */

        /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
        * Nordic SPU should handle Secure Attribution tasks */
        #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
    2d64:	4a4f      	ldr	r2, [pc, #316]	; (2ea4 <SystemInit+0x140>)
{
    2d66:	b508      	push	{r3, lr}
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
    2d68:	6813      	ldr	r3, [r2, #0]
    2d6a:	f043 0302 	orr.w	r3, r3, #2
    2d6e:	6013      	str	r3, [r2, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2d70:	4b4d      	ldr	r3, [pc, #308]	; (2ea8 <SystemInit+0x144>)
            if (var1 == 0x09)
    2d72:	681b      	ldr	r3, [r3, #0]
    2d74:	2b09      	cmp	r3, #9
        #endif
        
        /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_6()){
            NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
    2d76:	bf01      	itttt	eq
    2d78:	f04f 2350 	moveq.w	r3, #1342197760	; 0x50005000
    2d7c:	2200      	moveq	r2, #0
    2d7e:	f8c3 2114 	streq.w	r2, [r3, #276]	; 0x114
            NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
    2d82:	f8c3 2118 	streq.w	r2, [r3, #280]	; 0x118
        }

        /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_14()){
    2d86:	f7ff ffdf 	bl	2d48 <nrf91_errata_14>
    2d8a:	b130      	cbz	r0, 2d9a <SystemInit+0x36>
            *((volatile uint32_t *)0x50004A38) = 0x01ul;
    2d8c:	2301      	movs	r3, #1
    2d8e:	4a47      	ldr	r2, [pc, #284]	; (2eac <SystemInit+0x148>)
    2d90:	6013      	str	r3, [r2, #0]
            NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
    2d92:	f6a2 2238 	subw	r2, r2, #2616	; 0xa38
    2d96:	f8c2 3578 	str.w	r3, [r2, #1400]	; 0x578
{
    #ifndef NRF91_SERIES
        return false;
    #else
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2d9a:	4b43      	ldr	r3, [pc, #268]	; (2ea8 <SystemInit+0x144>)
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
        #endif
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            if (var1 == 0x09)
    2d9c:	681b      	ldr	r3, [r3, #0]
    2d9e:	2b09      	cmp	r3, #9
    2da0:	d107      	bne.n	2db2 <SystemInit+0x4e>
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
    2da2:	4b43      	ldr	r3, [pc, #268]	; (2eb0 <SystemInit+0x14c>)
            {
                switch(var2)
    2da4:	681b      	ldr	r3, [r3, #0]
    2da6:	2b01      	cmp	r3, #1
        }

        /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_15()){
            NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
    2da8:	bf1e      	ittt	ne
    2daa:	2201      	movne	r2, #1
    2dac:	4b41      	ldrne	r3, [pc, #260]	; (2eb4 <SystemInit+0x150>)
    2dae:	f8c3 2578 	strne.w	r2, [r3, #1400]	; 0x578
        }

        /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_20()){
    2db2:	f7ff ffc9 	bl	2d48 <nrf91_errata_14>
    2db6:	b110      	cbz	r0, 2dbe <SystemInit+0x5a>
            *((volatile uint32_t *)0x5003AEE4) = 0xE;
    2db8:	220e      	movs	r2, #14
    2dba:	4b3f      	ldr	r3, [pc, #252]	; (2eb8 <SystemInit+0x154>)
    2dbc:	601a      	str	r2, [r3, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2dbe:	4b3a      	ldr	r3, [pc, #232]	; (2ea8 <SystemInit+0x144>)
            if (var1 == 0x09)
    2dc0:	681b      	ldr	r3, [r3, #0]
    2dc2:	2b09      	cmp	r3, #9
    2dc4:	d104      	bne.n	2dd0 <SystemInit+0x6c>
        }

        /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_31()){
            *((volatile uint32_t *)0x5000470Cul) = 0x0;
    2dc6:	2200      	movs	r2, #0
    2dc8:	4b3c      	ldr	r3, [pc, #240]	; (2ebc <SystemInit+0x158>)
    2dca:	601a      	str	r2, [r3, #0]
            *((volatile uint32_t *)0x50004710ul) = 0x1;
    2dcc:	2201      	movs	r2, #1
    2dce:	605a      	str	r2, [r3, #4]
{
    2dd0:	2200      	movs	r2, #0
    2dd2:	00d3      	lsls	r3, r2, #3
    2dd4:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2dd8:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
    2ddc:	3101      	adds	r1, #1
    2dde:	d008      	beq.n	2df2 <SystemInit+0x8e>
          #if defined ( __ICCARM__ )
              #pragma diag_suppress=Pa082
          #endif
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    2de0:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2de4:	3201      	adds	r2, #1
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    2de6:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2dea:	f5b2 7f80 	cmp.w	r2, #256	; 0x100
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    2dee:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2df0:	d1ef      	bne.n	2dd2 <SystemInit+0x6e>
    }
    
    
    bool uicr_HFXOSRC_erased()
    {
        if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
    2df2:	4b33      	ldr	r3, [pc, #204]	; (2ec0 <SystemInit+0x15c>)
    2df4:	69da      	ldr	r2, [r3, #28]
        if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
    2df6:	07d1      	lsls	r1, r2, #31
    2df8:	d53b      	bpl.n	2e72 <SystemInit+0x10e>
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2dfa:	4b32      	ldr	r3, [pc, #200]	; (2ec4 <SystemInit+0x160>)
    2dfc:	4619      	mov	r1, r3
    2dfe:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    2e02:	2a01      	cmp	r2, #1
    2e04:	d1fb      	bne.n	2dfe <SystemInit+0x9a>
          NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
    2e06:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2e0a:	f8d1 3400 	ldr.w	r3, [r1, #1024]	; 0x400
    2e0e:	2b01      	cmp	r3, #1
    2e10:	d1fb      	bne.n	2e0a <SystemInit+0xa6>
        if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
    2e12:	4b2b      	ldr	r3, [pc, #172]	; (2ec0 <SystemInit+0x15c>)
    2e14:	69da      	ldr	r2, [r3, #28]
          if (uicr_HFXOSRC_erased()){
    2e16:	07d2      	lsls	r2, r2, #31
    2e18:	d508      	bpl.n	2e2c <SystemInit+0xc8>
            uicr_erased_value = NRF_UICR_S->HFXOSRC;
    2e1a:	69da      	ldr	r2, [r3, #28]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2e1c:	4929      	ldr	r1, [pc, #164]	; (2ec4 <SystemInit+0x160>)
            uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
    2e1e:	f022 0201 	bic.w	r2, r2, #1
            NRF_UICR_S->HFXOSRC = uicr_new_value;
    2e22:	61da      	str	r2, [r3, #28]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2e24:	f8d1 2400 	ldr.w	r2, [r1, #1024]	; 0x400
    2e28:	2a01      	cmp	r2, #1
    2e2a:	d1fb      	bne.n	2e24 <SystemInit+0xc0>
        if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
    2e2c:	6a1a      	ldr	r2, [r3, #32]
    2e2e:	3201      	adds	r2, #1
    2e30:	d10a      	bne.n	2e48 <SystemInit+0xe4>
            uicr_erased_value = NRF_UICR_S->HFXOCNT;
    2e32:	6a1a      	ldr	r2, [r3, #32]
            uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
    2e34:	f022 02ff 	bic.w	r2, r2, #255	; 0xff
    2e38:	f042 0220 	orr.w	r2, r2, #32
            NRF_UICR_S->HFXOCNT = uicr_new_value;
    2e3c:	621a      	str	r2, [r3, #32]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2e3e:	4a21      	ldr	r2, [pc, #132]	; (2ec4 <SystemInit+0x160>)
    2e40:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    2e44:	2b01      	cmp	r3, #1
    2e46:	d1fb      	bne.n	2e40 <SystemInit+0xdc>
          NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
    2e48:	2200      	movs	r2, #0
    2e4a:	4b1e      	ldr	r3, [pc, #120]	; (2ec4 <SystemInit+0x160>)
    2e4c:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2e50:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    2e54:	2a01      	cmp	r2, #1
    2e56:	d1fb      	bne.n	2e50 <SystemInit+0xec>
  __ASM volatile ("dsb 0xF":::"memory");
    2e58:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2e5c:	491a      	ldr	r1, [pc, #104]	; (2ec8 <SystemInit+0x164>)
    2e5e:	4b1b      	ldr	r3, [pc, #108]	; (2ecc <SystemInit+0x168>)
    2e60:	68ca      	ldr	r2, [r1, #12]
    2e62:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2e66:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2e68:	60cb      	str	r3, [r1, #12]
    2e6a:	f3bf 8f4f 	dsb	sy
    __NOP();
    2e6e:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2e70:	e7fd      	b.n	2e6e <SystemInit+0x10a>
        if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
    2e72:	6a1b      	ldr	r3, [r3, #32]
    2e74:	3301      	adds	r3, #1
    2e76:	d0c0      	beq.n	2dfa <SystemInit+0x96>
        SCB->NSACR |= (3UL << 10);
    2e78:	4b13      	ldr	r3, [pc, #76]	; (2ec8 <SystemInit+0x164>)
    2e7a:	f8d3 208c 	ldr.w	r2, [r3, #140]	; 0x8c
    2e7e:	f442 6240 	orr.w	r2, r2, #3072	; 0xc00
    2e82:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
      SCB->CPACR |= (3UL << 20) | (3UL << 22);
    2e86:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2e8a:	f442 0270 	orr.w	r2, r2, #15728640	; 0xf00000
    2e8e:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    2e92:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2e96:	f3bf 8f6f 	isb	sy
    SystemCoreClock = __SYSTEM_CLOCK;
    2e9a:	4b0d      	ldr	r3, [pc, #52]	; (2ed0 <SystemInit+0x16c>)
    2e9c:	4a0d      	ldr	r2, [pc, #52]	; (2ed4 <SystemInit+0x170>)
    2e9e:	601a      	str	r2, [r3, #0]
}
    2ea0:	bd08      	pop	{r3, pc}
    2ea2:	bf00      	nop
    2ea4:	e000edd0 	.word	0xe000edd0
    2ea8:	00ff0130 	.word	0x00ff0130
    2eac:	50004a38 	.word	0x50004a38
    2eb0:	00ff0134 	.word	0x00ff0134
    2eb4:	50004000 	.word	0x50004000
    2eb8:	5003aee4 	.word	0x5003aee4
    2ebc:	5000470c 	.word	0x5000470c
    2ec0:	00ff8000 	.word	0x00ff8000
    2ec4:	50039000 	.word	0x50039000
    2ec8:	e000ed00 	.word	0xe000ed00
    2ecc:	05fa0004 	.word	0x05fa0004
    2ed0:	20000048 	.word	0x20000048
    2ed4:	03d09000 	.word	0x03d09000

00002ed8 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    2ed8:	4b04      	ldr	r3, [pc, #16]	; (2eec <nrfx_clock_init+0x14>)
    2eda:	791a      	ldrb	r2, [r3, #4]
    2edc:	b922      	cbnz	r2, 2ee8 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    2ede:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    2ee0:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    2ee2:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    2ee4:	4802      	ldr	r0, [pc, #8]	; (2ef0 <nrfx_clock_init+0x18>)
    2ee6:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    2ee8:	4802      	ldr	r0, [pc, #8]	; (2ef4 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2eea:	4770      	bx	lr
    2eec:	20000800 	.word	0x20000800
    2ef0:	0bad0000 	.word	0x0bad0000
    2ef4:	0bad000c 	.word	0x0bad000c

00002ef8 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2ef8:	b110      	cbz	r0, 2f00 <nrfx_clock_start+0x8>
    2efa:	2801      	cmp	r0, #1
    2efc:	d020      	beq.n	2f40 <nrfx_clock_start+0x48>
    2efe:	4770      	bx	lr
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2f00:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    2f04:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2f08:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    2f0c:	03c9      	lsls	r1, r1, #15
    2f0e:	d511      	bpl.n	2f34 <nrfx_clock_start+0x3c>
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    2f10:	f003 0303 	and.w	r3, r3, #3
    2f14:	2b02      	cmp	r3, #2
    2f16:	d10d      	bne.n	2f34 <nrfx_clock_start+0x3c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2f18:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f1c:	2200      	movs	r2, #0
    2f1e:	4b0d      	ldr	r3, [pc, #52]	; (2f54 <nrfx_clock_start+0x5c>)
    2f20:	601a      	str	r2, [r3, #0]
    2f22:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2f24:	2202      	movs	r2, #2
    2f26:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2f2a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2f2e:	2201      	movs	r2, #1
    2f30:	609a      	str	r2, [r3, #8]
}
    2f32:	4770      	bx	lr
    p_reg->LFCLKSRC = (uint32_t)(source);
    2f34:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2f38:	2201      	movs	r2, #1
    2f3a:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    2f3e:	e7ed      	b.n	2f1c <nrfx_clock_start+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f40:	2200      	movs	r2, #0
    2f42:	4b05      	ldr	r3, [pc, #20]	; (2f58 <nrfx_clock_start+0x60>)
    2f44:	601a      	str	r2, [r3, #0]
    2f46:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2f48:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2f4c:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2f50:	6018      	str	r0, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    2f52:	4770      	bx	lr
    2f54:	50005104 	.word	0x50005104
    2f58:	50005100 	.word	0x50005100

00002f5c <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    2f5c:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2f5e:	b110      	cbz	r0, 2f66 <nrfx_clock_stop+0xa>
    2f60:	2801      	cmp	r0, #1
    2f62:	d018      	beq.n	2f96 <nrfx_clock_stop+0x3a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2f64:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    2f66:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2f6a:	2202      	movs	r2, #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2f6c:	2101      	movs	r1, #1
    2f6e:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2f72:	461c      	mov	r4, r3
    p_reg->INTENCLR = mask;
    2f74:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f78:	4a15      	ldr	r2, [pc, #84]	; (2fd0 <nrfx_clock_stop+0x74>)
    2f7a:	6010      	str	r0, [r2, #0]
    2f7c:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2f7e:	4a15      	ldr	r2, [pc, #84]	; (2fd4 <nrfx_clock_stop+0x78>)
    2f80:	6011      	str	r1, [r2, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2f82:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    2f86:	03db      	lsls	r3, r3, #15
    2f88:	d5ec      	bpl.n	2f64 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    2f8a:	2001      	movs	r0, #1
    2f8c:	f002 fcd7 	bl	593e <nrfx_busy_wait>
    2f90:	3d01      	subs	r5, #1
    2f92:	d1f6      	bne.n	2f82 <nrfx_clock_stop+0x26>
    2f94:	e7e6      	b.n	2f64 <nrfx_clock_stop+0x8>
    p_reg->INTENCLR = mask;
    2f96:	f04f 2450 	mov.w	r4, #1342197760	; 0x50005000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f9a:	2200      	movs	r2, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2f9c:	f242 7510 	movw	r5, #10000	; 0x2710
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2fa0:	4b0d      	ldr	r3, [pc, #52]	; (2fd8 <nrfx_clock_stop+0x7c>)
    p_reg->INTENCLR = mask;
    2fa2:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2fa6:	601a      	str	r2, [r3, #0]
    2fa8:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2faa:	4b0c      	ldr	r3, [pc, #48]	; (2fdc <nrfx_clock_stop+0x80>)
    2fac:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2fae:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2fb2:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2fb6:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2fba:	03d2      	lsls	r2, r2, #15
    2fbc:	d5d2      	bpl.n	2f64 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    2fbe:	2b00      	cmp	r3, #0
    2fc0:	d0d0      	beq.n	2f64 <nrfx_clock_stop+0x8>
    2fc2:	2001      	movs	r0, #1
    2fc4:	f002 fcbb 	bl	593e <nrfx_busy_wait>
    2fc8:	3d01      	subs	r5, #1
    2fca:	d1f0      	bne.n	2fae <nrfx_clock_stop+0x52>
    2fcc:	e7ca      	b.n	2f64 <nrfx_clock_stop+0x8>
    2fce:	bf00      	nop
    2fd0:	50005104 	.word	0x50005104
    2fd4:	5000500c 	.word	0x5000500c
    2fd8:	50005100 	.word	0x50005100
    2fdc:	50005004 	.word	0x50005004

00002fe0 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2fe0:	4b16      	ldr	r3, [pc, #88]	; (303c <nrfx_power_clock_irq_handler+0x5c>)
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    2fe2:	b510      	push	{r4, lr}
    2fe4:	681a      	ldr	r2, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    2fe6:	b152      	cbz	r2, 2ffe <nrfx_power_clock_irq_handler+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2fe8:	2000      	movs	r0, #0
    2fea:	6018      	str	r0, [r3, #0]
    2fec:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2fee:	2201      	movs	r2, #1
    2ff0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2ff4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    2ff8:	4b11      	ldr	r3, [pc, #68]	; (3040 <nrfx_power_clock_irq_handler+0x60>)
    2ffa:	681b      	ldr	r3, [r3, #0]
    2ffc:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2ffe:	4b11      	ldr	r3, [pc, #68]	; (3044 <nrfx_power_clock_irq_handler+0x64>)
    3000:	681a      	ldr	r2, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    3002:	b18a      	cbz	r2, 3028 <nrfx_power_clock_irq_handler+0x48>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3004:	2200      	movs	r2, #0
    3006:	601a      	str	r2, [r3, #0]
    3008:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    300a:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    300e:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3012:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    3016:	f002 0203 	and.w	r2, r2, #3
    301a:	2a01      	cmp	r2, #1
    301c:	f04f 0102 	mov.w	r1, #2
    3020:	d103      	bne.n	302a <nrfx_power_clock_irq_handler+0x4a>
    p_reg->LFCLKSRC = (uint32_t)(source);
    3022:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3026:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    3028:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    302a:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    302e:	4b04      	ldr	r3, [pc, #16]	; (3040 <nrfx_power_clock_irq_handler+0x60>)
    3030:	2001      	movs	r0, #1
}
    3032:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3036:	681b      	ldr	r3, [r3, #0]
    3038:	4718      	bx	r3
    303a:	bf00      	nop
    303c:	50005100 	.word	0x50005100
    3040:	20000800 	.word	0x20000800
    3044:	50005104 	.word	0x50005104

00003048 <nrfx_dppi_channel_alloc>:
nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel)
{
    nrfx_err_t err_code;

    // Get mask of available DPPI channels
    uint32_t remaining_channels = DPPI_AVAILABLE_CHANNELS_MASK & ~(m_allocated_channels);
    3048:	4a0b      	ldr	r2, [pc, #44]	; (3078 <nrfx_dppi_channel_alloc+0x30>)
{
    304a:	b570      	push	{r4, r5, r6, lr}
    uint32_t remaining_channels = DPPI_AVAILABLE_CHANNELS_MASK & ~(m_allocated_channels);
    304c:	6816      	ldr	r6, [r2, #0]
    304e:	43f1      	mvns	r1, r6
    3050:	b289      	uxth	r1, r1
    uint8_t channel = 0;

    if (!remaining_channels)
    3052:	b171      	cbz	r1, 3072 <nrfx_dppi_channel_alloc+0x2a>
    3054:	2500      	movs	r5, #0
    3056:	b2ec      	uxtb	r4, r5
        NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }

    // Find first free channel
    while (!(remaining_channels & DPPI_BIT_SET(channel)))
    3058:	fa21 f304 	lsr.w	r3, r1, r4
    305c:	07db      	lsls	r3, r3, #31
    305e:	f105 0501 	add.w	r5, r5, #1
    3062:	d5f8      	bpl.n	3056 <nrfx_dppi_channel_alloc+0xe>
    {
        channel++;
    }

    m_allocated_channels |= DPPI_BIT_SET(channel);
    3064:	2301      	movs	r3, #1
    3066:	40a3      	lsls	r3, r4
    3068:	4333      	orrs	r3, r6
    *p_channel = channel;
    306a:	7004      	strb	r4, [r0, #0]

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Allocated channel: %d.", channel);
    return err_code;
    306c:	4803      	ldr	r0, [pc, #12]	; (307c <nrfx_dppi_channel_alloc+0x34>)
    m_allocated_channels |= DPPI_BIT_SET(channel);
    306e:	6013      	str	r3, [r2, #0]
}
    3070:	bd70      	pop	{r4, r5, r6, pc}
        return err_code;
    3072:	4803      	ldr	r0, [pc, #12]	; (3080 <nrfx_dppi_channel_alloc+0x38>)
    3074:	e7fc      	b.n	3070 <nrfx_dppi_channel_alloc+0x28>
    3076:	bf00      	nop
    3078:	20000808 	.word	0x20000808
    307c:	0bad0000 	.word	0x0bad0000
    3080:	0bad0002 	.word	0x0bad0002

00003084 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    3084:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3086:	4b10      	ldr	r3, [pc, #64]	; (30c8 <z_sys_init_run_level+0x44>)
			/* Initialization failed.
			 * Set the init status bit so device is not declared ready.
			 */
			sys_bitfield_set_bit(
				(mem_addr_t) __device_init_status_start,
				(dev - __device_start));
    3088:	4f10      	ldr	r7, [pc, #64]	; (30cc <z_sys_init_run_level+0x48>)
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    308a:	f853 5020 	ldr.w	r5, [r3, r0, lsl #2]
    308e:	3001      	adds	r0, #1
    3090:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    3094:	42ae      	cmp	r6, r5
    3096:	d800      	bhi.n	309a <z_sys_init_run_level+0x16>
		}
	}
}
    3098:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if ((entry->init(dev) != 0) && (dev != NULL)) {
    309a:	e9d5 3400 	ldrd	r3, r4, [r5]
    309e:	4620      	mov	r0, r4
    30a0:	4798      	blx	r3
    30a2:	b170      	cbz	r0, 30c2 <z_sys_init_run_level+0x3e>
    30a4:	b16c      	cbz	r4, 30c2 <z_sys_init_run_level+0x3e>

static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
	uint32_t temp = *(volatile uint32_t *)addr;

	*(volatile uint32_t *)addr = temp | (1 << bit);
    30a6:	2301      	movs	r3, #1
				(dev - __device_start));
    30a8:	1be4      	subs	r4, r4, r7
	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
{
	/* Doing memory offsets in terms of 32-bit values to prevent
	 * alignment issues
	 */
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    30aa:	4a09      	ldr	r2, [pc, #36]	; (30d0 <z_sys_init_run_level+0x4c>)
    30ac:	1124      	asrs	r4, r4, #4
    30ae:	0961      	lsrs	r1, r4, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    30b0:	f852 0021 	ldr.w	r0, [r2, r1, lsl #2]
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    30b4:	f004 041f 	and.w	r4, r4, #31
	*(volatile uint32_t *)addr = temp | (1 << bit);
    30b8:	fa03 f404 	lsl.w	r4, r3, r4
    30bc:	4304      	orrs	r4, r0
    30be:	f842 4021 	str.w	r4, [r2, r1, lsl #2]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    30c2:	3508      	adds	r5, #8
    30c4:	e7e6      	b.n	3094 <z_sys_init_run_level+0x10>
    30c6:	bf00      	nop
    30c8:	00006034 	.word	0x00006034
    30cc:	200000b4 	.word	0x200000b4
    30d0:	20000104 	.word	0x20000104

000030d4 <z_device_ready>:

bool z_device_ready(const struct device *dev)
{
	/* Set bit indicates device failed initialization */
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
					(dev - __device_start)));
    30d4:	4b08      	ldr	r3, [pc, #32]	; (30f8 <z_device_ready+0x24>)
    30d6:	1ac0      	subs	r0, r0, r3
    30d8:	1100      	asrs	r0, r0, #4
}

static ALWAYS_INLINE
	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
{
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    30da:	4b08      	ldr	r3, [pc, #32]	; (30fc <z_device_ready+0x28>)
    30dc:	0942      	lsrs	r2, r0, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    30de:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
	return temp & (1 << bit);
    30e2:	2301      	movs	r3, #1
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    30e4:	f000 001f 	and.w	r0, r0, #31
	return temp & (1 << bit);
    30e8:	fa03 f000 	lsl.w	r0, r3, r0
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
    30ec:	4210      	tst	r0, r2
}
    30ee:	bf0c      	ite	eq
    30f0:	4618      	moveq	r0, r3
    30f2:	2000      	movne	r0, #0
    30f4:	4770      	bx	lr
    30f6:	bf00      	nop
    30f8:	200000b4 	.word	0x200000b4
    30fc:	20000104 	.word	0x20000104

00003100 <z_impl_device_get_binding>:
	for (dev = __device_start; dev != __device_end; dev++) {
    3100:	4911      	ldr	r1, [pc, #68]	; (3148 <z_impl_device_get_binding+0x48>)
{
    3102:	b570      	push	{r4, r5, r6, lr}
    3104:	4605      	mov	r5, r0
    3106:	460e      	mov	r6, r1
	for (dev = __device_start; dev != __device_end; dev++) {
    3108:	4c10      	ldr	r4, [pc, #64]	; (314c <z_impl_device_get_binding+0x4c>)
    310a:	428c      	cmp	r4, r1
    310c:	d104      	bne.n	3118 <z_impl_device_get_binding+0x18>
	for (dev = __device_start; dev != __device_end; dev++) {
    310e:	4c0f      	ldr	r4, [pc, #60]	; (314c <z_impl_device_get_binding+0x4c>)
    3110:	42b4      	cmp	r4, r6
    3112:	d10a      	bne.n	312a <z_impl_device_get_binding+0x2a>
	return NULL;
    3114:	2400      	movs	r4, #0
    3116:	e014      	b.n	3142 <z_impl_device_get_binding+0x42>
		if (z_device_ready(dev) && (dev->name == name)) {
    3118:	4620      	mov	r0, r4
    311a:	f7ff ffdb 	bl	30d4 <z_device_ready>
    311e:	b110      	cbz	r0, 3126 <z_impl_device_get_binding+0x26>
    3120:	6823      	ldr	r3, [r4, #0]
    3122:	42ab      	cmp	r3, r5
    3124:	d00d      	beq.n	3142 <z_impl_device_get_binding+0x42>
	for (dev = __device_start; dev != __device_end; dev++) {
    3126:	3410      	adds	r4, #16
    3128:	e7ef      	b.n	310a <z_impl_device_get_binding+0xa>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    312a:	4620      	mov	r0, r4
    312c:	f7ff ffd2 	bl	30d4 <z_device_ready>
    3130:	b908      	cbnz	r0, 3136 <z_impl_device_get_binding+0x36>
	for (dev = __device_start; dev != __device_end; dev++) {
    3132:	3410      	adds	r4, #16
    3134:	e7ec      	b.n	3110 <z_impl_device_get_binding+0x10>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    3136:	4628      	mov	r0, r5
    3138:	6821      	ldr	r1, [r4, #0]
    313a:	f002 fb1d 	bl	5778 <strcmp>
    313e:	2800      	cmp	r0, #0
    3140:	d1f7      	bne.n	3132 <z_impl_device_get_binding+0x32>
}
    3142:	4620      	mov	r0, r4
    3144:	bd70      	pop	{r4, r5, r6, pc}
    3146:	bf00      	nop
    3148:	20000104 	.word	0x20000104
    314c:	200000b4 	.word	0x200000b4

00003150 <idle>:
#else
#define IDLE_YIELD_IF_COOP() do { } while (false)
#endif

void idle(void *p1, void *unused2, void *unused3)
{
    3150:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3152:	4605      	mov	r5, r0
		 */
		int key = arch_irq_lock();
		struct k_thread *to_abort = cpu->pending_abort;

		if (to_abort) {
			cpu->pending_abort = NULL;
    3154:	2700      	movs	r7, #0
	_kernel.idle = ticks;
    3156:	4e1b      	ldr	r6, [pc, #108]	; (31c4 <idle+0x74>)
	__asm__ volatile(
    3158:	f04f 0220 	mov.w	r2, #32
    315c:	f3ef 8311 	mrs	r3, BASEPRI
    3160:	f382 8811 	msr	BASEPRI, r2
    3164:	f3bf 8f6f 	isb	sy
		struct k_thread *to_abort = cpu->pending_abort;
    3168:	6928      	ldr	r0, [r5, #16]
		if (to_abort) {
    316a:	b188      	cbz	r0, 3190 <idle+0x40>
			cpu->pending_abort = NULL;
    316c:	612f      	str	r7, [r5, #16]
	__asm__ volatile(
    316e:	f383 8811 	msr	BASEPRI, r3
    3172:	f3bf 8f6f 	isb	sy
			 * is continued below.
			 */
			LOG_DBG("idle %p aborting thread %p",
				_current, to_abort);

			z_thread_single_abort(to_abort);
    3176:	f000 fbf9 	bl	396c <z_thread_single_abort>
	__asm__ volatile(
    317a:	f04f 0320 	mov.w	r3, #32
    317e:	f3ef 8011 	mrs	r0, BASEPRI
    3182:	f383 8811 	msr	BASEPRI, r3
    3186:	f3bf 8f6f 	isb	sy
    318a:	f002 fc25 	bl	59d8 <z_reschedule_irqlock>
			 * in order to abort the thread, and we now need to
			 * figure out what to do next, it's not necessarily
			 * the case that there are no other runnable threads.
			 */
			z_reschedule_unlocked();
			continue;
    318e:	e7e3      	b.n	3158 <idle+0x8>
	__asm__ volatile(
    3190:	f383 8811 	msr	BASEPRI, r3
    3194:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    3198:	f04f 0220 	mov.w	r2, #32
    319c:	f3ef 8311 	mrs	r3, BASEPRI
    31a0:	f382 8811 	msr	BASEPRI, r2
    31a4:	f3bf 8f6f 	isb	sy
	int32_t ticks = z_get_next_timeout_expiry();
    31a8:	f002 fce2 	bl	5b70 <z_get_next_timeout_expiry>
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    31ac:	2101      	movs	r1, #1
	int32_t ticks = z_get_next_timeout_expiry();
    31ae:	4604      	mov	r4, r0
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    31b0:	2802      	cmp	r0, #2
    31b2:	bfd8      	it	le
    31b4:	4608      	movle	r0, r1
    31b6:	f002 fceb 	bl	5b90 <z_set_timeout_expiry>
	_kernel.idle = ticks;
    31ba:	6274      	str	r4, [r6, #36]	; 0x24
	arch_cpu_idle();
    31bc:	f7fe ff7a 	bl	20b4 <arch_cpu_idle>
}
    31c0:	e7ca      	b.n	3158 <idle+0x8>
    31c2:	bf00      	nop
    31c4:	2000080c 	.word	0x2000080c

000031c8 <z_bss_zero>:
 *
 * @return N/A
 */
void z_bss_zero(void)
{
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    31c8:	4802      	ldr	r0, [pc, #8]	; (31d4 <z_bss_zero+0xc>)
    31ca:	4a03      	ldr	r2, [pc, #12]	; (31d8 <z_bss_zero+0x10>)
    31cc:	2100      	movs	r1, #0
    31ce:	1a12      	subs	r2, r2, r0
    31d0:	f002 bb30 	b.w	5834 <memset>
    31d4:	20000158 	.word	0x20000158
    31d8:	20000870 	.word	0x20000870

000031dc <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    31dc:	b508      	push	{r3, lr}
	(void)memcpy(&__data_ram_start, &__data_rom_start,
		 __data_ram_end - __data_ram_start);
    31de:	4806      	ldr	r0, [pc, #24]	; (31f8 <z_data_copy+0x1c>)
	(void)memcpy(&__data_ram_start, &__data_rom_start,
    31e0:	4a06      	ldr	r2, [pc, #24]	; (31fc <z_data_copy+0x20>)
    31e2:	4907      	ldr	r1, [pc, #28]	; (3200 <z_data_copy+0x24>)
    31e4:	1a12      	subs	r2, r2, r0
    31e6:	f002 fafa 	bl	57de <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    31ea:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&_ramfunc_ram_start, &_ramfunc_rom_start,
    31ee:	4a05      	ldr	r2, [pc, #20]	; (3204 <z_data_copy+0x28>)
    31f0:	4905      	ldr	r1, [pc, #20]	; (3208 <z_data_copy+0x2c>)
    31f2:	4806      	ldr	r0, [pc, #24]	; (320c <z_data_copy+0x30>)
    31f4:	f002 baf3 	b.w	57de <memcpy>
    31f8:	20000000 	.word	0x20000000
    31fc:	20000158 	.word	0x20000158
    3200:	00006548 	.word	0x00006548
    3204:	00000000 	.word	0x00000000
    3208:	00006548 	.word	0x00006548
    320c:	20000000 	.word	0x20000000

00003210 <bg_thread_main>:
	static const unsigned int boot_delay = CONFIG_BOOT_DELAY;
#else
	static const unsigned int boot_delay;
#endif

	z_sys_post_kernel = true;
    3210:	2201      	movs	r2, #1
{
    3212:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    3214:	4b0b      	ldr	r3, [pc, #44]	; (3244 <bg_thread_main+0x34>)

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3216:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    3218:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    321a:	f7ff ff33 	bl	3084 <z_sys_init_run_level>
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    321e:	4a0a      	ldr	r2, [pc, #40]	; (3248 <bg_thread_main+0x38>)
    3220:	490a      	ldr	r1, [pc, #40]	; (324c <bg_thread_main+0x3c>)
    3222:	480b      	ldr	r0, [pc, #44]	; (3250 <bg_thread_main+0x40>)
    3224:	f001 ff02 	bl	502c <printk>
	__do_global_ctors_aux();
	__do_init_array_aux();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    3228:	2003      	movs	r0, #3
    322a:	f7ff ff2b 	bl	3084 <z_sys_init_run_level>

	z_init_static_threads();
    322e:	f000 fddf 	bl	3df0 <z_init_static_threads>
	z_timestamp_main = k_cycle_get_32();
#endif

	extern void main(void);

	main();
    3232:	f001 fed5 	bl	4fe0 <main>

	/* Mark nonessenrial since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    3236:	4a07      	ldr	r2, [pc, #28]	; (3254 <bg_thread_main+0x44>)
    3238:	7b13      	ldrb	r3, [r2, #12]
    323a:	f023 0301 	bic.w	r3, r3, #1
    323e:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    3240:	bd08      	pop	{r3, pc}
    3242:	bf00      	nop
    3244:	2000086d 	.word	0x2000086d
    3248:	00006189 	.word	0x00006189
    324c:	000064f8 	.word	0x000064f8
    3250:	00006517 	.word	0x00006517
    3254:	200001d8 	.word	0x200001d8

00003258 <z_cstart>:
 * cleared/zeroed.
 *
 * @return Does not return
 */
FUNC_NORETURN void z_cstart(void)
{
    3258:	e92d 4880 	stmdb	sp!, {r7, fp, lr}
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    325c:	4b37      	ldr	r3, [pc, #220]	; (333c <z_cstart+0xe4>)
    325e:	b0a7      	sub	sp, #156	; 0x9c
	uint32_t msp =
    3260:	f503 6900 	add.w	r9, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    3264:	f389 8808 	msr	MSP, r9
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    3268:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    326c:	2400      	movs	r4, #0
    326e:	23e0      	movs	r3, #224	; 0xe0
    3270:	4d33      	ldr	r5, [pc, #204]	; (3340 <z_cstart+0xe8>)
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3272:	f04f 0b01 	mov.w	fp, #1
    3276:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    327a:	77ec      	strb	r4, [r5, #31]
    327c:	762c      	strb	r4, [r5, #24]
    327e:	766c      	strb	r4, [r5, #25]
    3280:	76ac      	strb	r4, [r5, #26]
    3282:	76ec      	strb	r4, [r5, #27]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    3284:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	_kernel.ready_q.cache = &z_main_thread;
    3286:	4e2f      	ldr	r6, [pc, #188]	; (3344 <z_cstart+0xec>)
    3288:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    328c:	626b      	str	r3, [r5, #36]	; 0x24
		      SCB_SHCSR_BUSFAULTENA_Msk;
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	/* Enable Secure Fault */
	SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk;
    328e:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3290:	f8df a0cc 	ldr.w	sl, [pc, #204]	; 3360 <z_cstart+0x108>
    3294:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
    3298:	626b      	str	r3, [r5, #36]	; 0x24
	/* Clear BFAR before setting BusFaults to target Non-Secure state. */
	SCB->BFAR = 0;
    329a:	63ac      	str	r4, [r5, #56]	; 0x38

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    329c:	f7ff f8b0 	bl	2400 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    32a0:	f7fe ff02 	bl	20a8 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    32a4:	f04f 33ff 	mov.w	r3, #4294967295
    32a8:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    32aa:	62eb      	str	r3, [r5, #44]	; 0x2c
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    32ac:	f240 1301 	movw	r3, #257	; 0x101
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    32b0:	4d25      	ldr	r5, [pc, #148]	; (3348 <z_cstart+0xf0>)
	dummy_thread->base.user_options = K_ESSENTIAL;
    32b2:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    32b6:	ab06      	add	r3, sp, #24
    32b8:	60ab      	str	r3, [r5, #8]

	z_dummy_thread_init(&dummy_thread);
#endif

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    32ba:	4620      	mov	r0, r4
	dummy_thread->stack_info.size = 0U;
    32bc:	e9cd 4420 	strd	r4, r4, [sp, #128]	; 0x80
    32c0:	f7ff fee0 	bl	3084 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    32c4:	2001      	movs	r0, #1
    32c6:	f7ff fedd 	bl	3084 <z_sys_init_run_level>
	z_sched_init();
    32ca:	f000 fc97 	bl	3bfc <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    32ce:	4b1f      	ldr	r3, [pc, #124]	; (334c <z_cstart+0xf4>)
	_kernel.ready_q.cache = &z_main_thread;
    32d0:	62ae      	str	r6, [r5, #40]	; 0x28
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    32d2:	f44f 5280 	mov.w	r2, #4096	; 0x1000
    32d6:	491e      	ldr	r1, [pc, #120]	; (3350 <z_cstart+0xf8>)
    32d8:	9305      	str	r3, [sp, #20]
    32da:	4630      	mov	r0, r6
    32dc:	4653      	mov	r3, sl
    32de:	e9cd 4b03 	strd	r4, fp, [sp, #12]
    32e2:	e9cd 4401 	strd	r4, r4, [sp, #4]
    32e6:	9400      	str	r4, [sp, #0]
    32e8:	f000 fd52 	bl	3d90 <z_setup_new_thread>
	sys_trace_thread_resume(thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    32ec:	7b73      	ldrb	r3, [r6, #13]
    32ee:	4680      	mov	r8, r0
    32f0:	f023 0304 	bic.w	r3, r3, #4
	z_ready_thread(&z_main_thread);
    32f4:	4630      	mov	r0, r6
    32f6:	7373      	strb	r3, [r6, #13]
    32f8:	f002 fb9a 	bl	5a30 <z_ready_thread>
	z_setup_new_thread(thread, stack,
    32fc:	230f      	movs	r3, #15
    32fe:	4f15      	ldr	r7, [pc, #84]	; (3354 <z_cstart+0xfc>)
    3300:	f44f 72a0 	mov.w	r2, #320	; 0x140
    3304:	e9cd 4302 	strd	r4, r3, [sp, #8]
    3308:	4913      	ldr	r1, [pc, #76]	; (3358 <z_cstart+0x100>)
    330a:	4b14      	ldr	r3, [pc, #80]	; (335c <z_cstart+0x104>)
    330c:	4638      	mov	r0, r7
    330e:	e9cd b404 	strd	fp, r4, [sp, #16]
    3312:	e9cd 5400 	strd	r5, r4, [sp]
    3316:	f000 fd3b 	bl	3d90 <z_setup_new_thread>
    331a:	7b7b      	ldrb	r3, [r7, #13]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    331c:	4652      	mov	r2, sl
    331e:	f023 0304 	bic.w	r3, r3, #4
    3322:	737b      	strb	r3, [r7, #13]
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    3324:	f105 031c 	add.w	r3, r5, #28
    3328:	4641      	mov	r1, r8
    332a:	4630      	mov	r0, r6
	list->tail = (sys_dnode_t *)list;
    332c:	e9c5 3307 	strd	r3, r3, [r5, #28]
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    3330:	60ef      	str	r7, [r5, #12]
		_kernel.cpus[i].id = i;
    3332:	762c      	strb	r4, [r5, #24]
		_kernel.cpus[i].irq_stack =
    3334:	f8c5 9004 	str.w	r9, [r5, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3338:	f7fe fe98 	bl	206c <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    333c:	200019b0 	.word	0x200019b0
    3340:	e000ed00 	.word	0xe000ed00
    3344:	200001d8 	.word	0x200001d8
    3348:	2000080c 	.word	0x2000080c
    334c:	0000653e 	.word	0x0000653e
    3350:	20000870 	.word	0x20000870
    3354:	20000158 	.word	0x20000158
    3358:	20001870 	.word	0x20001870
    335c:	00003151 	.word	0x00003151
    3360:	00003211 	.word	0x00003211

00003364 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
    3364:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    3366:	4b0e      	ldr	r3, [pc, #56]	; (33a0 <init_mem_slab_module+0x3c>)
    3368:	4c0e      	ldr	r4, [pc, #56]	; (33a4 <init_mem_slab_module+0x40>)
    336a:	42a3      	cmp	r3, r4
    336c:	d301      	bcc.n	3372 <init_mem_slab_module+0xe>
		}
		SYS_TRACING_OBJ_INIT(k_mem_slab, slab);
		z_object_init(slab);
	}

out:
    336e:	2000      	movs	r0, #0
	return rc;
}
    3370:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    3372:	e9d3 0103 	ldrd	r0, r1, [r3, #12]
    3376:	ea41 0200 	orr.w	r2, r1, r0
    337a:	f012 0203 	ands.w	r2, r2, #3
    337e:	d10b      	bne.n	3398 <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
    3380:	689d      	ldr	r5, [r3, #8]
	slab->free_list = NULL;
    3382:	615a      	str	r2, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    3384:	42aa      	cmp	r2, r5
    3386:	d101      	bne.n	338c <init_mem_slab_module+0x28>
	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    3388:	331c      	adds	r3, #28
    338a:	e7ee      	b.n	336a <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
    338c:	695e      	ldr	r6, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    338e:	3201      	adds	r2, #1
		*(char **)p = slab->free_list;
    3390:	600e      	str	r6, [r1, #0]
		slab->free_list = p;
    3392:	6159      	str	r1, [r3, #20]
		p += slab->block_size;
    3394:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
    3396:	e7f5      	b.n	3384 <init_mem_slab_module+0x20>
		return -EINVAL;
    3398:	f06f 0015 	mvn.w	r0, #21
	return rc;
    339c:	e7e8      	b.n	3370 <init_mem_slab_module+0xc>
    339e:	bf00      	nop
    33a0:	20000108 	.word	0x20000108
    33a4:	20000108 	.word	0x20000108

000033a8 <k_mem_slab_alloc>:
out:
	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    33a8:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
    33aa:	460c      	mov	r4, r1
    33ac:	4616      	mov	r6, r2
    33ae:	461f      	mov	r7, r3
    33b0:	f04f 0320 	mov.w	r3, #32
    33b4:	f3ef 8111 	mrs	r1, BASEPRI
    33b8:	f383 8811 	msr	BASEPRI, r3
    33bc:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	int result;

	if (slab->free_list != NULL) {
    33c0:	6943      	ldr	r3, [r0, #20]
    33c2:	b15b      	cbz	r3, 33dc <k_mem_slab_alloc+0x34>
		/* take a free block */
		*mem = slab->free_list;
    33c4:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    33c6:	681b      	ldr	r3, [r3, #0]
    33c8:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    33ca:	6983      	ldr	r3, [r0, #24]
    33cc:	3301      	adds	r3, #1
    33ce:	6183      	str	r3, [r0, #24]
		result = 0;
    33d0:	2000      	movs	r0, #0
	__asm__ volatile(
    33d2:	f381 8811 	msr	BASEPRI, r1
    33d6:	f3bf 8f6f 	isb	sy
		return result;
	}

	k_spin_unlock(&lock, key);

	return result;
    33da:	e011      	b.n	3400 <k_mem_slab_alloc+0x58>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    33dc:	ea56 0207 	orrs.w	r2, r6, r7
    33e0:	d103      	bne.n	33ea <k_mem_slab_alloc+0x42>
		result = -ENOMEM;
    33e2:	f06f 000b 	mvn.w	r0, #11
		*mem = NULL;
    33e6:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
    33e8:	e7f3      	b.n	33d2 <k_mem_slab_alloc+0x2a>
		result = z_pend_curr(&lock, key, &slab->wait_q, timeout);
    33ea:	4602      	mov	r2, r0
    33ec:	e9cd 6700 	strd	r6, r7, [sp]
    33f0:	4804      	ldr	r0, [pc, #16]	; (3404 <k_mem_slab_alloc+0x5c>)
    33f2:	f000 fb7d 	bl	3af0 <z_pend_curr>
		if (result == 0) {
    33f6:	b918      	cbnz	r0, 3400 <k_mem_slab_alloc+0x58>
			*mem = _current->base.swap_data;
    33f8:	4b03      	ldr	r3, [pc, #12]	; (3408 <k_mem_slab_alloc+0x60>)
    33fa:	689b      	ldr	r3, [r3, #8]
    33fc:	695b      	ldr	r3, [r3, #20]
    33fe:	6023      	str	r3, [r4, #0]
}
    3400:	b002      	add	sp, #8
    3402:	bdd0      	pop	{r4, r6, r7, pc}
    3404:	2000086e 	.word	0x2000086e
    3408:	2000080c 	.word	0x2000080c

0000340c <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    340c:	b570      	push	{r4, r5, r6, lr}
    340e:	4604      	mov	r4, r0
    3410:	460d      	mov	r5, r1
	__asm__ volatile(
    3412:	f04f 0320 	mov.w	r3, #32
    3416:	f3ef 8611 	mrs	r6, BASEPRI
    341a:	f383 8811 	msr	BASEPRI, r3
    341e:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    3422:	f002 fb60 	bl	5ae6 <z_unpend_first_thread>

	if (pending_thread != NULL) {
    3426:	b158      	cbz	r0, 3440 <k_mem_slab_free+0x34>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    3428:	2100      	movs	r1, #0
		z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    342a:	682a      	ldr	r2, [r5, #0]
    342c:	67c1      	str	r1, [r0, #124]	; 0x7c
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    342e:	6142      	str	r2, [r0, #20]
		z_ready_thread(pending_thread);
    3430:	f002 fafe 	bl	5a30 <z_ready_thread>
		z_reschedule(&lock, key);
    3434:	4631      	mov	r1, r6
		**(char ***)mem = slab->free_list;
		slab->free_list = *(char **)mem;
		slab->num_used--;
		k_spin_unlock(&lock, key);
	}
}
    3436:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule(&lock, key);
    343a:	4808      	ldr	r0, [pc, #32]	; (345c <k_mem_slab_free+0x50>)
    343c:	f000 b910 	b.w	3660 <z_reschedule>
		**(char ***)mem = slab->free_list;
    3440:	682b      	ldr	r3, [r5, #0]
    3442:	6962      	ldr	r2, [r4, #20]
    3444:	601a      	str	r2, [r3, #0]
		slab->free_list = *(char **)mem;
    3446:	682b      	ldr	r3, [r5, #0]
    3448:	6163      	str	r3, [r4, #20]
		slab->num_used--;
    344a:	69a3      	ldr	r3, [r4, #24]
    344c:	3b01      	subs	r3, #1
    344e:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    3450:	f386 8811 	msr	BASEPRI, r6
    3454:	f3bf 8f6f 	isb	sy
}
    3458:	bd70      	pop	{r4, r5, r6, pc}
    345a:	bf00      	nop
    345c:	2000086e 	.word	0x2000086e

00003460 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    3460:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    3464:	4604      	mov	r4, r0
    3466:	4616      	mov	r6, r2
    3468:	461f      	mov	r7, r3
	__asm__ volatile(
    346a:	f04f 0320 	mov.w	r3, #32
    346e:	f3ef 8811 	mrs	r8, BASEPRI
    3472:	f383 8811 	msr	BASEPRI, r3
    3476:	f3bf 8f6f 	isb	sy
	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	sys_trace_mutex_lock(mutex);
	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    347a:	68c3      	ldr	r3, [r0, #12]
    347c:	4a32      	ldr	r2, [pc, #200]	; (3548 <z_impl_k_mutex_lock+0xe8>)
    347e:	b16b      	cbz	r3, 349c <z_impl_k_mutex_lock+0x3c>
    3480:	6880      	ldr	r0, [r0, #8]
    3482:	6891      	ldr	r1, [r2, #8]
    3484:	4288      	cmp	r0, r1
    3486:	d019      	beq.n	34bc <z_impl_k_mutex_lock+0x5c>
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    3488:	ea56 0307 	orrs.w	r3, r6, r7
    348c:	d118      	bne.n	34c0 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    348e:	f388 8811 	msr	BASEPRI, r8
    3492:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
		return -EBUSY;
    3496:	f06f 000f 	mvn.w	r0, #15
    349a:	e00c      	b.n	34b6 <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
    349c:	6891      	ldr	r1, [r2, #8]
    349e:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
    34a2:	3301      	adds	r3, #1
    34a4:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    34a6:	6893      	ldr	r3, [r2, #8]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    34a8:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
    34aa:	60a3      	str	r3, [r4, #8]
    34ac:	f388 8811 	msr	BASEPRI, r8
    34b0:	f3bf 8f6f 	isb	sy
		return 0;
    34b4:	2000      	movs	r0, #0
		k_spin_unlock(&lock, key);
	}

	sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
	return -EAGAIN;
}
    34b6:	b002      	add	sp, #8
    34b8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    34bc:	6921      	ldr	r1, [r4, #16]
    34be:	e7f0      	b.n	34a2 <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    34c0:	f990 300e 	ldrsb.w	r3, [r0, #14]
    34c4:	f991 100e 	ldrsb.w	r1, [r1, #14]
    34c8:	4299      	cmp	r1, r3
    34ca:	bfa8      	it	ge
    34cc:	4619      	movge	r1, r3
    34ce:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    34d2:	4299      	cmp	r1, r3
    34d4:	da2c      	bge.n	3530 <z_impl_k_mutex_lock+0xd0>
		return z_set_prio(mutex->owner, new_prio);
    34d6:	f000 fb4d 	bl	3b74 <z_set_prio>
    34da:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    34dc:	4622      	mov	r2, r4
    34de:	4641      	mov	r1, r8
    34e0:	e9cd 6700 	strd	r6, r7, [sp]
    34e4:	4819      	ldr	r0, [pc, #100]	; (354c <z_impl_k_mutex_lock+0xec>)
    34e6:	f000 fb03 	bl	3af0 <z_pend_curr>
	if (got_mutex == 0) {
    34ea:	2800      	cmp	r0, #0
    34ec:	d0e3      	beq.n	34b6 <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
    34ee:	f04f 0320 	mov.w	r3, #32
    34f2:	f3ef 8611 	mrs	r6, BASEPRI
    34f6:	f383 8811 	msr	BASEPRI, r3
    34fa:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    34fe:	6823      	ldr	r3, [r4, #0]
    3500:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3502:	42a3      	cmp	r3, r4
    3504:	d007      	beq.n	3516 <z_impl_k_mutex_lock+0xb6>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    3506:	b133      	cbz	r3, 3516 <z_impl_k_mutex_lock+0xb6>
    3508:	f993 300e 	ldrsb.w	r3, [r3, #14]
    350c:	4299      	cmp	r1, r3
    350e:	bfa8      	it	ge
    3510:	4619      	movge	r1, r3
    3512:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    3516:	68a0      	ldr	r0, [r4, #8]
	if (mutex->owner->base.prio != new_prio) {
    3518:	f990 300e 	ldrsb.w	r3, [r0, #14]
    351c:	4299      	cmp	r1, r3
    351e:	d109      	bne.n	3534 <z_impl_k_mutex_lock+0xd4>
	if (resched) {
    3520:	b16d      	cbz	r5, 353e <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
    3522:	4631      	mov	r1, r6
    3524:	4809      	ldr	r0, [pc, #36]	; (354c <z_impl_k_mutex_lock+0xec>)
    3526:	f000 f89b 	bl	3660 <z_reschedule>
	return -EAGAIN;
    352a:	f06f 000a 	mvn.w	r0, #10
    352e:	e7c2      	b.n	34b6 <z_impl_k_mutex_lock+0x56>
	bool resched = false;
    3530:	2500      	movs	r5, #0
    3532:	e7d3      	b.n	34dc <z_impl_k_mutex_lock+0x7c>
		return z_set_prio(mutex->owner, new_prio);
    3534:	f000 fb1e 	bl	3b74 <z_set_prio>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    3538:	2800      	cmp	r0, #0
    353a:	d1f2      	bne.n	3522 <z_impl_k_mutex_lock+0xc2>
    353c:	e7f0      	b.n	3520 <z_impl_k_mutex_lock+0xc0>
	__asm__ volatile(
    353e:	f386 8811 	msr	BASEPRI, r6
    3542:	f3bf 8f6f 	isb	sy
    3546:	e7f0      	b.n	352a <z_impl_k_mutex_lock+0xca>
    3548:	2000080c 	.word	0x2000080c
    354c:	2000086e 	.word	0x2000086e

00003550 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    3550:	b538      	push	{r3, r4, r5, lr}
	struct k_thread *new_owner;

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	CHECKIF(mutex->owner == NULL) {
    3552:	6883      	ldr	r3, [r0, #8]
{
    3554:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    3556:	2b00      	cmp	r3, #0
    3558:	d036      	beq.n	35c8 <z_impl_k_mutex_unlock+0x78>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    355a:	4a1e      	ldr	r2, [pc, #120]	; (35d4 <z_impl_k_mutex_unlock+0x84>)
    355c:	6892      	ldr	r2, [r2, #8]
    355e:	4293      	cmp	r3, r2
    3560:	d135      	bne.n	35ce <z_impl_k_mutex_unlock+0x7e>
{
#ifdef CONFIG_PREEMPT_ENABLED
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1, "");

	--_current->base.sched_locked;
    3562:	7bda      	ldrb	r2, [r3, #15]
    3564:	3a01      	subs	r2, #1
    3566:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count - 1U != 0U) {
    3568:	68c3      	ldr	r3, [r0, #12]
    356a:	2b01      	cmp	r3, #1
    356c:	d005      	beq.n	357a <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    356e:	3b01      	subs	r3, #1
    3570:	60c3      	str	r3, [r0, #12]
		k_spin_unlock(&lock, key);
	}


k_mutex_unlock_return:
	k_sched_unlock();
    3572:	f000 f8d9 	bl	3728 <k_sched_unlock>
	sys_trace_end_call(SYS_TRACE_ID_MUTEX_UNLOCK);

	return 0;
    3576:	2000      	movs	r0, #0
}
    3578:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    357a:	f04f 0320 	mov.w	r3, #32
    357e:	f3ef 8511 	mrs	r5, BASEPRI
    3582:	f383 8811 	msr	BASEPRI, r3
    3586:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    358a:	6901      	ldr	r1, [r0, #16]
    358c:	6880      	ldr	r0, [r0, #8]
	if (mutex->owner->base.prio != new_prio) {
    358e:	f990 300e 	ldrsb.w	r3, [r0, #14]
    3592:	4299      	cmp	r1, r3
    3594:	d001      	beq.n	359a <z_impl_k_mutex_unlock+0x4a>
		return z_set_prio(mutex->owner, new_prio);
    3596:	f000 faed 	bl	3b74 <z_set_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    359a:	4620      	mov	r0, r4
    359c:	f002 faa3 	bl	5ae6 <z_unpend_first_thread>
	mutex->owner = new_owner;
    35a0:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    35a2:	b158      	cbz	r0, 35bc <z_impl_k_mutex_unlock+0x6c>
		mutex->owner_orig_prio = new_owner->base.prio;
    35a4:	f990 200e 	ldrsb.w	r2, [r0, #14]
    35a8:	6122      	str	r2, [r4, #16]
    35aa:	2200      	movs	r2, #0
    35ac:	67c2      	str	r2, [r0, #124]	; 0x7c
		z_ready_thread(new_owner);
    35ae:	f002 fa3f 	bl	5a30 <z_ready_thread>
		z_reschedule(&lock, key);
    35b2:	4629      	mov	r1, r5
    35b4:	4808      	ldr	r0, [pc, #32]	; (35d8 <z_impl_k_mutex_unlock+0x88>)
    35b6:	f000 f853 	bl	3660 <z_reschedule>
    35ba:	e7da      	b.n	3572 <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    35bc:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    35be:	f385 8811 	msr	BASEPRI, r5
    35c2:	f3bf 8f6f 	isb	sy
    35c6:	e7d4      	b.n	3572 <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    35c8:	f06f 0015 	mvn.w	r0, #21
    35cc:	e7d4      	b.n	3578 <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
    35ce:	f04f 30ff 	mov.w	r0, #4294967295
    35d2:	e7d1      	b.n	3578 <z_impl_k_mutex_unlock+0x28>
    35d4:	2000080c 	.word	0x2000080c
    35d8:	2000086e 	.word	0x2000086e

000035dc <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    35dc:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    35de:	4c08      	ldr	r4, [pc, #32]	; (3600 <z_reset_time_slice+0x24>)
    35e0:	6823      	ldr	r3, [r4, #0]
    35e2:	b15b      	cbz	r3, 35fc <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
    35e4:	f7fe f99e 	bl	1924 <z_clock_elapsed>
    35e8:	6822      	ldr	r2, [r4, #0]
    35ea:	4906      	ldr	r1, [pc, #24]	; (3604 <z_reset_time_slice+0x28>)
    35ec:	4410      	add	r0, r2
    35ee:	6148      	str	r0, [r1, #20]
		z_set_timeout_expiry(slice_time, false);
	}
}
    35f0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		z_set_timeout_expiry(slice_time, false);
    35f4:	2100      	movs	r1, #0
    35f6:	4610      	mov	r0, r2
    35f8:	f002 baca 	b.w	5b90 <z_set_timeout_expiry>
}
    35fc:	bd10      	pop	{r4, pc}
    35fe:	bf00      	nop
    3600:	20000848 	.word	0x20000848
    3604:	2000080c 	.word	0x2000080c

00003608 <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    3608:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    360a:	460c      	mov	r4, r1
	__asm__ volatile(
    360c:	f04f 0320 	mov.w	r3, #32
    3610:	f3ef 8511 	mrs	r5, BASEPRI
    3614:	f383 8811 	msr	BASEPRI, r3
    3618:	f3bf 8f6f 	isb	sy
		} else {
			return t * (to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    361c:	f44f 4100 	mov.w	r1, #32768	; 0x8000
    3620:	f240 36e7 	movw	r6, #999	; 0x3e7
    3624:	2700      	movs	r7, #0
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    3626:	2200      	movs	r2, #0
    3628:	fbe1 6700 	umlal	r6, r7, r1, r0
    362c:	4b09      	ldr	r3, [pc, #36]	; (3654 <k_sched_time_slice_set+0x4c>)
    362e:	4630      	mov	r0, r6
    3630:	615a      	str	r2, [r3, #20]
    3632:	4639      	mov	r1, r7
    3634:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3638:	2300      	movs	r3, #0
    363a:	f7fc fdff 	bl	23c <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    363e:	4b06      	ldr	r3, [pc, #24]	; (3658 <k_sched_time_slice_set+0x50>)
    3640:	6018      	str	r0, [r3, #0]
		slice_max_prio = prio;
    3642:	4b06      	ldr	r3, [pc, #24]	; (365c <k_sched_time_slice_set+0x54>)
    3644:	601c      	str	r4, [r3, #0]
		z_reset_time_slice();
    3646:	f7ff ffc9 	bl	35dc <z_reset_time_slice>
	__asm__ volatile(
    364a:	f385 8811 	msr	BASEPRI, r5
    364e:	f3bf 8f6f 	isb	sy
	}
}
    3652:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3654:	2000080c 	.word	0x2000080c
    3658:	20000848 	.word	0x20000848
    365c:	20000844 	.word	0x20000844

00003660 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    3660:	b949      	cbnz	r1, 3676 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    3662:	f3ef 8005 	mrs	r0, IPSR
    3666:	b930      	cbnz	r0, 3676 <z_reschedule+0x16>
	return _kernel.ready_q.cache;
    3668:	4b05      	ldr	r3, [pc, #20]	; (3680 <z_reschedule+0x20>)
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    366a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    366c:	689b      	ldr	r3, [r3, #8]
    366e:	429a      	cmp	r2, r3
    3670:	d001      	beq.n	3676 <z_reschedule+0x16>
	ret = arch_swap(key);
    3672:	f7fe bc55 	b.w	1f20 <arch_swap>
    3676:	f381 8811 	msr	BASEPRI, r1
    367a:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    367e:	4770      	bx	lr
    3680:	2000080c 	.word	0x2000080c

00003684 <k_sched_lock>:
	__asm__ volatile(
    3684:	f04f 0320 	mov.w	r3, #32
    3688:	f3ef 8111 	mrs	r1, BASEPRI
    368c:	f383 8811 	msr	BASEPRI, r3
    3690:	f3bf 8f6f 	isb	sy
	--_current->base.sched_locked;
    3694:	4b04      	ldr	r3, [pc, #16]	; (36a8 <k_sched_lock+0x24>)
    3696:	689a      	ldr	r2, [r3, #8]
    3698:	7bd3      	ldrb	r3, [r2, #15]
    369a:	3b01      	subs	r3, #1
    369c:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    369e:	f381 8811 	msr	BASEPRI, r1
    36a2:	f3bf 8f6f 	isb	sy
void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
		z_sched_lock();
	}
}
    36a6:	4770      	bx	lr
    36a8:	2000080c 	.word	0x2000080c

000036ac <z_priq_dumb_remove>:
}

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
#if defined(CONFIG_SWAP_NONATOMIC) && defined(CONFIG_SCHED_DUMB)
	if (pq == &_kernel.ready_q.runq && thread == _current &&
    36ac:	4b09      	ldr	r3, [pc, #36]	; (36d4 <z_priq_dumb_remove+0x28>)
    36ae:	f103 022c 	add.w	r2, r3, #44	; 0x2c
    36b2:	4282      	cmp	r2, r0
    36b4:	d105      	bne.n	36c2 <z_priq_dumb_remove+0x16>
    36b6:	689b      	ldr	r3, [r3, #8]
    36b8:	428b      	cmp	r3, r1
    36ba:	d102      	bne.n	36c2 <z_priq_dumb_remove+0x16>
    36bc:	7b4b      	ldrb	r3, [r1, #13]
    36be:	06db      	lsls	r3, r3, #27
    36c0:	d106      	bne.n	36d0 <z_priq_dumb_remove+0x24>
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	node->prev->next = node->next;
    36c2:	e9d1 3200 	ldrd	r3, r2, [r1]
    36c6:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    36c8:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    36ca:	2300      	movs	r3, #0
	node->prev = NULL;
    36cc:	e9c1 3300 	strd	r3, r3, [r1]
#endif

	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
}
    36d0:	4770      	bx	lr
    36d2:	bf00      	nop
    36d4:	2000080c 	.word	0x2000080c

000036d8 <update_cache>:
{
    36d8:	b538      	push	{r3, r4, r5, lr}
    36da:	4c12      	ldr	r4, [pc, #72]	; (3724 <update_cache+0x4c>)
    36dc:	4601      	mov	r1, r0
	if (_current_cpu->pending_abort != NULL) {
    36de:	6923      	ldr	r3, [r4, #16]
    36e0:	68a2      	ldr	r2, [r4, #8]
    36e2:	b10b      	cbz	r3, 36e8 <update_cache+0x10>
	return thread ? thread : _current_cpu->idle_thread;
    36e4:	68e5      	ldr	r5, [r4, #12]
    36e6:	e00c      	b.n	3702 <update_cache+0x2a>
	thread = _priq_run_best(&_kernel.ready_q.runq);
    36e8:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    36ec:	f002 f996 	bl	5a1c <z_priq_dumb_best>
    36f0:	4605      	mov	r5, r0
	if (_current->base.thread_state & _THREAD_ABORTING) {
    36f2:	7b53      	ldrb	r3, [r2, #13]
    36f4:	0698      	lsls	r0, r3, #26
		_current->base.thread_state |= _THREAD_DEAD;
    36f6:	bf44      	itt	mi
    36f8:	f043 0308 	orrmi.w	r3, r3, #8
    36fc:	7353      	strbmi	r3, [r2, #13]
	return thread ? thread : _current_cpu->idle_thread;
    36fe:	2d00      	cmp	r5, #0
    3700:	d0f0      	beq.n	36e4 <update_cache+0xc>
	if (preempt_ok != 0) {
    3702:	b949      	cbnz	r1, 3718 <update_cache+0x40>
	if (z_is_thread_prevented_from_running(_current)) {
    3704:	7b53      	ldrb	r3, [r2, #13]
    3706:	06db      	lsls	r3, r3, #27
    3708:	d106      	bne.n	3718 <update_cache+0x40>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    370a:	69ab      	ldr	r3, [r5, #24]
    370c:	b923      	cbnz	r3, 3718 <update_cache+0x40>
	if (is_preempt(_current) || is_metairq(thread)) {
    370e:	89d3      	ldrh	r3, [r2, #14]
    3710:	2b7f      	cmp	r3, #127	; 0x7f
    3712:	d901      	bls.n	3718 <update_cache+0x40>
		_kernel.ready_q.cache = _current;
    3714:	62a2      	str	r2, [r4, #40]	; 0x28
}
    3716:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    3718:	4295      	cmp	r5, r2
    371a:	d001      	beq.n	3720 <update_cache+0x48>
			z_reset_time_slice();
    371c:	f7ff ff5e 	bl	35dc <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    3720:	62a5      	str	r5, [r4, #40]	; 0x28
}
    3722:	e7f8      	b.n	3716 <update_cache+0x3e>
    3724:	2000080c 	.word	0x2000080c

00003728 <k_sched_unlock>:
{
    3728:	b510      	push	{r4, lr}
	__asm__ volatile(
    372a:	f04f 0320 	mov.w	r3, #32
    372e:	f3ef 8411 	mrs	r4, BASEPRI
    3732:	f383 8811 	msr	BASEPRI, r3
    3736:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    373a:	4b08      	ldr	r3, [pc, #32]	; (375c <k_sched_unlock+0x34>)
		update_cache(0);
    373c:	2000      	movs	r0, #0
		++_current->base.sched_locked;
    373e:	689a      	ldr	r2, [r3, #8]
    3740:	7bd3      	ldrb	r3, [r2, #15]
    3742:	3301      	adds	r3, #1
    3744:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    3746:	f7ff ffc7 	bl	36d8 <update_cache>
	__asm__ volatile(
    374a:	f384 8811 	msr	BASEPRI, r4
    374e:	f3bf 8f6f 	isb	sy
}
    3752:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    3756:	f002 b94b 	b.w	59f0 <z_reschedule_unlocked>
    375a:	bf00      	nop
    375c:	2000080c 	.word	0x2000080c

00003760 <ready_thread>:
{
    3760:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    3762:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    3766:	7b43      	ldrb	r3, [r0, #13]
    3768:	2a00      	cmp	r2, #0
    376a:	db2c      	blt.n	37c6 <ready_thread+0x66>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    376c:	06db      	lsls	r3, r3, #27
    376e:	d12a      	bne.n	37c6 <ready_thread+0x66>

int z_abort_timeout(struct _timeout *to);

static inline bool z_is_inactive_timeout(const struct _timeout *t)
{
	return !sys_dnode_is_linked(&t->node);
    3770:	6983      	ldr	r3, [r0, #24]
    3772:	bb43      	cbnz	r3, 37c6 <ready_thread+0x66>
	return list->head == list;
    3774:	4a15      	ldr	r2, [pc, #84]	; (37cc <ready_thread+0x6c>)
    3776:	4611      	mov	r1, r2
    3778:	f851 4f2c 	ldr.w	r4, [r1, #44]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    377c:	428c      	cmp	r4, r1
    377e:	bf18      	it	ne
    3780:	4623      	movne	r3, r4
    3782:	2b00      	cmp	r3, #0
    3784:	bf38      	it	cc
    3786:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3788:	6b14      	ldr	r4, [r2, #48]	; 0x30
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    378a:	b1b3      	cbz	r3, 37ba <ready_thread+0x5a>
	if (thread_1->base.prio < thread_2->base.prio) {
    378c:	f990 600e 	ldrsb.w	r6, [r0, #14]
    3790:	f993 500e 	ldrsb.w	r5, [r3, #14]
    3794:	42ae      	cmp	r6, r5
    3796:	db03      	blt.n	37a0 <ready_thread+0x40>
	return (node == list->tail) ? NULL : node->next;
    3798:	42a3      	cmp	r3, r4
    379a:	d00e      	beq.n	37ba <ready_thread+0x5a>
    379c:	681b      	ldr	r3, [r3, #0]
    379e:	e7f4      	b.n	378a <ready_thread+0x2a>
	node->prev = successor->prev;
    37a0:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    37a2:	e9c0 3200 	strd	r3, r2, [r0]
	successor->prev->next = node;
    37a6:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    37a8:	6058      	str	r0, [r3, #4]
	thread->base.thread_state |= states;
    37aa:	7b43      	ldrb	r3, [r0, #13]
    37ac:	f063 037f 	orn	r3, r3, #127	; 0x7f
    37b0:	7343      	strb	r3, [r0, #13]
}
    37b2:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    37b4:	2000      	movs	r0, #0
    37b6:	f7ff bf8f 	b.w	36d8 <update_cache>
	node->prev = list->tail;
    37ba:	e9c0 1400 	strd	r1, r4, [r0]
	list->tail->next = node;
    37be:	6b13      	ldr	r3, [r2, #48]	; 0x30
    37c0:	6018      	str	r0, [r3, #0]
	list->tail = node;
    37c2:	6310      	str	r0, [r2, #48]	; 0x30
}
    37c4:	e7f1      	b.n	37aa <ready_thread+0x4a>
}
    37c6:	bc70      	pop	{r4, r5, r6}
    37c8:	4770      	bx	lr
    37ca:	bf00      	nop
    37cc:	2000080c 	.word	0x2000080c

000037d0 <z_sched_start>:
{
    37d0:	b510      	push	{r4, lr}
	__asm__ volatile(
    37d2:	f04f 0220 	mov.w	r2, #32
    37d6:	f3ef 8411 	mrs	r4, BASEPRI
    37da:	f382 8811 	msr	BASEPRI, r2
    37de:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    37e2:	7b42      	ldrb	r2, [r0, #13]
    37e4:	0751      	lsls	r1, r2, #29
    37e6:	d404      	bmi.n	37f2 <z_sched_start+0x22>
	__asm__ volatile(
    37e8:	f384 8811 	msr	BASEPRI, r4
    37ec:	f3bf 8f6f 	isb	sy
}
    37f0:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    37f2:	f022 0204 	bic.w	r2, r2, #4
    37f6:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    37f8:	f7ff ffb2 	bl	3760 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    37fc:	4621      	mov	r1, r4
}
    37fe:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    3802:	4801      	ldr	r0, [pc, #4]	; (3808 <z_sched_start+0x38>)
    3804:	f7ff bf2c 	b.w	3660 <z_reschedule>
    3808:	2000086e 	.word	0x2000086e

0000380c <move_thread_to_end_of_prio_q>:
{
    380c:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    380e:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    3812:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3814:	2b00      	cmp	r3, #0
    3816:	da02      	bge.n	381e <move_thread_to_end_of_prio_q+0x12>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    3818:	4817      	ldr	r0, [pc, #92]	; (3878 <move_thread_to_end_of_prio_q+0x6c>)
    381a:	f7ff ff47 	bl	36ac <z_priq_dumb_remove>
	return list->head == list;
    381e:	4a17      	ldr	r2, [pc, #92]	; (387c <move_thread_to_end_of_prio_q+0x70>)
    3820:	4610      	mov	r0, r2
    3822:	f850 3f2c 	ldr.w	r3, [r0, #44]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3826:	6b14      	ldr	r4, [r2, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3828:	4283      	cmp	r3, r0
    382a:	bf08      	it	eq
    382c:	2300      	moveq	r3, #0
    382e:	2b00      	cmp	r3, #0
    3830:	bf38      	it	cc
    3832:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3834:	b1d3      	cbz	r3, 386c <move_thread_to_end_of_prio_q+0x60>
	if (thread_1->base.prio < thread_2->base.prio) {
    3836:	f991 600e 	ldrsb.w	r6, [r1, #14]
    383a:	f993 500e 	ldrsb.w	r5, [r3, #14]
    383e:	42ae      	cmp	r6, r5
    3840:	db03      	blt.n	384a <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
    3842:	42a3      	cmp	r3, r4
    3844:	d012      	beq.n	386c <move_thread_to_end_of_prio_q+0x60>
    3846:	681b      	ldr	r3, [r3, #0]
    3848:	e7f4      	b.n	3834 <move_thread_to_end_of_prio_q+0x28>
	node->prev = successor->prev;
    384a:	6858      	ldr	r0, [r3, #4]
	node->next = successor;
    384c:	e9c1 3000 	strd	r3, r0, [r1]
	successor->prev->next = node;
    3850:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    3852:	6059      	str	r1, [r3, #4]
	thread->base.thread_state |= states;
    3854:	7b4b      	ldrb	r3, [r1, #13]
	update_cache(thread == _current);
    3856:	6890      	ldr	r0, [r2, #8]
    3858:	f063 037f 	orn	r3, r3, #127	; 0x7f
    385c:	734b      	strb	r3, [r1, #13]
    385e:	1a43      	subs	r3, r0, r1
    3860:	4258      	negs	r0, r3
    3862:	4158      	adcs	r0, r3
}
    3864:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    3868:	f7ff bf36 	b.w	36d8 <update_cache>
	node->prev = list->tail;
    386c:	e9c1 0400 	strd	r0, r4, [r1]
	list->tail->next = node;
    3870:	6b13      	ldr	r3, [r2, #48]	; 0x30
    3872:	6019      	str	r1, [r3, #0]
	list->tail = node;
    3874:	6311      	str	r1, [r2, #48]	; 0x30
}
    3876:	e7ed      	b.n	3854 <move_thread_to_end_of_prio_q+0x48>
    3878:	20000838 	.word	0x20000838
    387c:	2000080c 	.word	0x2000080c

00003880 <z_time_slice>:
{
    3880:	4601      	mov	r1, r0
    3882:	b570      	push	{r4, r5, r6, lr}
	__asm__ volatile(
    3884:	f04f 0320 	mov.w	r3, #32
    3888:	f3ef 8411 	mrs	r4, BASEPRI
    388c:	f383 8811 	msr	BASEPRI, r3
    3890:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    3894:	4b16      	ldr	r3, [pc, #88]	; (38f0 <z_time_slice+0x70>)
    3896:	4a17      	ldr	r2, [pc, #92]	; (38f4 <z_time_slice+0x74>)
    3898:	6898      	ldr	r0, [r3, #8]
    389a:	6815      	ldr	r5, [r2, #0]
    389c:	42a8      	cmp	r0, r5
    389e:	461d      	mov	r5, r3
    38a0:	d106      	bne.n	38b0 <z_time_slice+0x30>
			z_reset_time_slice();
    38a2:	f7ff fe9b 	bl	35dc <z_reset_time_slice>
	__asm__ volatile(
    38a6:	f384 8811 	msr	BASEPRI, r4
    38aa:	f3bf 8f6f 	isb	sy
}
    38ae:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    38b0:	2600      	movs	r6, #0
    38b2:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    38b4:	4a10      	ldr	r2, [pc, #64]	; (38f8 <z_time_slice+0x78>)
    38b6:	6812      	ldr	r2, [r2, #0]
    38b8:	b1ba      	cbz	r2, 38ea <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    38ba:	89c2      	ldrh	r2, [r0, #14]
    38bc:	2a7f      	cmp	r2, #127	; 0x7f
    38be:	d814      	bhi.n	38ea <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    38c0:	7b42      	ldrb	r2, [r0, #13]
    38c2:	06d2      	lsls	r2, r2, #27
    38c4:	d111      	bne.n	38ea <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    38c6:	4a0d      	ldr	r2, [pc, #52]	; (38fc <z_time_slice+0x7c>)
    38c8:	f990 600e 	ldrsb.w	r6, [r0, #14]
    38cc:	6812      	ldr	r2, [r2, #0]
    38ce:	4296      	cmp	r6, r2
    38d0:	db0b      	blt.n	38ea <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    38d2:	4a0b      	ldr	r2, [pc, #44]	; (3900 <z_time_slice+0x80>)
    38d4:	4290      	cmp	r0, r2
    38d6:	d008      	beq.n	38ea <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    38d8:	695a      	ldr	r2, [r3, #20]
    38da:	428a      	cmp	r2, r1
    38dc:	dc02      	bgt.n	38e4 <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    38de:	f7ff ff95 	bl	380c <move_thread_to_end_of_prio_q>
    38e2:	e7de      	b.n	38a2 <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    38e4:	1a52      	subs	r2, r2, r1
    38e6:	615a      	str	r2, [r3, #20]
    38e8:	e7dd      	b.n	38a6 <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    38ea:	2300      	movs	r3, #0
    38ec:	616b      	str	r3, [r5, #20]
    38ee:	e7da      	b.n	38a6 <z_time_slice+0x26>
    38f0:	2000080c 	.word	0x2000080c
    38f4:	20000840 	.word	0x20000840
    38f8:	20000848 	.word	0x20000848
    38fc:	20000844 	.word	0x20000844
    3900:	20000158 	.word	0x20000158

00003904 <z_impl_k_thread_suspend>:
{
    3904:	b570      	push	{r4, r5, r6, lr}
    3906:	4604      	mov	r4, r0
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    3908:	3018      	adds	r0, #24
    390a:	f002 f91b 	bl	5b44 <z_abort_timeout>
	__asm__ volatile(
    390e:	f04f 0320 	mov.w	r3, #32
    3912:	f3ef 8611 	mrs	r6, BASEPRI
    3916:	f383 8811 	msr	BASEPRI, r3
    391a:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    391e:	f994 300d 	ldrsb.w	r3, [r4, #13]
    3922:	2b00      	cmp	r3, #0
    3924:	da07      	bge.n	3936 <z_impl_k_thread_suspend+0x32>
			_priq_run_remove(&_kernel.ready_q.runq, thread);
    3926:	4621      	mov	r1, r4
    3928:	480e      	ldr	r0, [pc, #56]	; (3964 <z_impl_k_thread_suspend+0x60>)
    392a:	f7ff febf 	bl	36ac <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    392e:	7b63      	ldrb	r3, [r4, #13]
    3930:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3934:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    3936:	4d0c      	ldr	r5, [pc, #48]	; (3968 <z_impl_k_thread_suspend+0x64>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3938:	7b63      	ldrb	r3, [r4, #13]
    393a:	68a8      	ldr	r0, [r5, #8]
    393c:	f043 0310 	orr.w	r3, r3, #16
    3940:	7363      	strb	r3, [r4, #13]
    3942:	1b03      	subs	r3, r0, r4
    3944:	4258      	negs	r0, r3
    3946:	4158      	adcs	r0, r3
    3948:	f7ff fec6 	bl	36d8 <update_cache>
	__asm__ volatile(
    394c:	f386 8811 	msr	BASEPRI, r6
    3950:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    3954:	68ab      	ldr	r3, [r5, #8]
    3956:	42a3      	cmp	r3, r4
    3958:	d103      	bne.n	3962 <z_impl_k_thread_suspend+0x5e>
}
    395a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    395e:	f002 b847 	b.w	59f0 <z_reschedule_unlocked>
}
    3962:	bd70      	pop	{r4, r5, r6, pc}
    3964:	20000838 	.word	0x20000838
    3968:	2000080c 	.word	0x2000080c

0000396c <z_thread_single_abort>:
{
    396c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3970:	4604      	mov	r4, r0
	__asm__ volatile(
    3972:	f04f 0320 	mov.w	r3, #32
    3976:	f3ef 8211 	mrs	r2, BASEPRI
    397a:	f383 8811 	msr	BASEPRI, r3
    397e:	f3bf 8f6f 	isb	sy
	if ((thread->base.thread_state &
    3982:	7b43      	ldrb	r3, [r0, #13]
    3984:	f013 0f28 	tst.w	r3, #40	; 0x28
    3988:	d005      	beq.n	3996 <z_thread_single_abort+0x2a>
	__asm__ volatile(
    398a:	f382 8811 	msr	BASEPRI, r2
    398e:	f3bf 8f6f 	isb	sy
}
    3992:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	thread->base.thread_state |= _THREAD_ABORTING;
    3996:	f043 0320 	orr.w	r3, r3, #32
    399a:	7343      	strb	r3, [r0, #13]
    399c:	f382 8811 	msr	BASEPRI, r2
    39a0:	f3bf 8f6f 	isb	sy
    39a4:	3018      	adds	r0, #24
    39a6:	f002 f8cd 	bl	5b44 <z_abort_timeout>
	__asm__ volatile(
    39aa:	f04f 0320 	mov.w	r3, #32
    39ae:	f3ef 8611 	mrs	r6, BASEPRI
    39b2:	f383 8811 	msr	BASEPRI, r3
    39b6:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    39ba:	7b63      	ldrb	r3, [r4, #13]
    39bc:	06d8      	lsls	r0, r3, #27
    39be:	d116      	bne.n	39ee <z_thread_single_abort+0x82>
		if (z_is_thread_ready(thread)) {
    39c0:	69a2      	ldr	r2, [r4, #24]
    39c2:	b9a2      	cbnz	r2, 39ee <z_thread_single_abort+0x82>
			if (z_is_thread_queued(thread)) {
    39c4:	0619      	lsls	r1, r3, #24
    39c6:	d507      	bpl.n	39d8 <z_thread_single_abort+0x6c>
				_priq_run_remove(&_kernel.ready_q.runq,
    39c8:	4621      	mov	r1, r4
    39ca:	4826      	ldr	r0, [pc, #152]	; (3a64 <z_thread_single_abort+0xf8>)
    39cc:	f7ff fe6e 	bl	36ac <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    39d0:	7b63      	ldrb	r3, [r4, #13]
    39d2:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    39d6:	7363      	strb	r3, [r4, #13]
			update_cache(thread == _current);
    39d8:	4b23      	ldr	r3, [pc, #140]	; (3a68 <z_thread_single_abort+0xfc>)
    39da:	6898      	ldr	r0, [r3, #8]
    39dc:	1b02      	subs	r2, r0, r4
    39de:	4250      	negs	r0, r2
    39e0:	4150      	adcs	r0, r2
    39e2:	f7ff fe79 	bl	36d8 <update_cache>
			waiter->base.pended_on = NULL;
    39e6:	2700      	movs	r7, #0
	sys_dlist_init(&w->waitq);
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    39e8:	f104 0830 	add.w	r8, r4, #48	; 0x30
    39ec:	e01d      	b.n	3a2a <z_thread_single_abort+0xbe>
			if (z_is_thread_pending(thread)) {
    39ee:	079b      	lsls	r3, r3, #30
    39f0:	d5f9      	bpl.n	39e6 <z_thread_single_abort+0x7a>
				_priq_wait_remove(&pended_on(thread)->waitq,
    39f2:	4621      	mov	r1, r4
    39f4:	68a0      	ldr	r0, [r4, #8]
    39f6:	f7ff fe59 	bl	36ac <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    39fa:	7b63      	ldrb	r3, [r4, #13]
    39fc:	f023 0302 	bic.w	r3, r3, #2
    3a00:	7363      	strb	r3, [r4, #13]
				thread->base.pended_on = NULL;
    3a02:	2300      	movs	r3, #0
    3a04:	60a3      	str	r3, [r4, #8]
    3a06:	e7ee      	b.n	39e6 <z_thread_single_abort+0x7a>
    3a08:	f105 0018 	add.w	r0, r5, #24
    3a0c:	f002 f89a 	bl	5b44 <z_abort_timeout>
			_priq_wait_remove(&pended_on(waiter)->waitq, waiter);
    3a10:	68a8      	ldr	r0, [r5, #8]
    3a12:	4629      	mov	r1, r5
    3a14:	f7ff fe4a 	bl	36ac <z_priq_dumb_remove>
    3a18:	7b6b      	ldrb	r3, [r5, #13]
			ready_thread(waiter);
    3a1a:	4628      	mov	r0, r5
    3a1c:	f023 0302 	bic.w	r3, r3, #2
    3a20:	736b      	strb	r3, [r5, #13]
			waiter->base.pended_on = NULL;
    3a22:	60af      	str	r7, [r5, #8]
    3a24:	67ef      	str	r7, [r5, #124]	; 0x7c
			ready_thread(waiter);
    3a26:	f7ff fe9b 	bl	3760 <ready_thread>
	return list->head == list;
    3a2a:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3a2c:	4545      	cmp	r5, r8
    3a2e:	d001      	beq.n	3a34 <z_thread_single_abort+0xc8>
		while ((waiter = z_waitq_head(&thread->base.join_waiters)) !=
    3a30:	2d00      	cmp	r5, #0
    3a32:	d1e9      	bne.n	3a08 <z_thread_single_abort+0x9c>
		if (z_is_idle_thread_object(_current)) {
    3a34:	4b0c      	ldr	r3, [pc, #48]	; (3a68 <z_thread_single_abort+0xfc>)
    3a36:	689a      	ldr	r2, [r3, #8]
    3a38:	4b0c      	ldr	r3, [pc, #48]	; (3a6c <z_thread_single_abort+0x100>)
    3a3a:	429a      	cmp	r2, r3
    3a3c:	d102      	bne.n	3a44 <z_thread_single_abort+0xd8>
			update_cache(1);
    3a3e:	2001      	movs	r0, #1
    3a40:	f7ff fe4a 	bl	36d8 <update_cache>
		thread->base.thread_state |= _THREAD_DEAD;
    3a44:	7b63      	ldrb	r3, [r4, #13]
    3a46:	f043 0308 	orr.w	r3, r3, #8
    3a4a:	7363      	strb	r3, [r4, #13]
		fn_abort = thread->fn_abort;
    3a4c:	6e23      	ldr	r3, [r4, #96]	; 0x60
	__asm__ volatile(
    3a4e:	f386 8811 	msr	BASEPRI, r6
    3a52:	f3bf 8f6f 	isb	sy
	if (fn_abort != NULL) {
    3a56:	2b00      	cmp	r3, #0
    3a58:	d09b      	beq.n	3992 <z_thread_single_abort+0x26>
		fn_abort(thread);
    3a5a:	4620      	mov	r0, r4
}
    3a5c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		fn_abort(thread);
    3a60:	4718      	bx	r3
    3a62:	bf00      	nop
    3a64:	20000838 	.word	0x20000838
    3a68:	2000080c 	.word	0x2000080c
    3a6c:	20000158 	.word	0x20000158

00003a70 <unready_thread>:
{
    3a70:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    3a72:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    3a76:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3a78:	2b00      	cmp	r3, #0
    3a7a:	da06      	bge.n	3a8a <unready_thread+0x1a>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    3a7c:	4807      	ldr	r0, [pc, #28]	; (3a9c <unready_thread+0x2c>)
    3a7e:	f7ff fe15 	bl	36ac <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    3a82:	7b4b      	ldrb	r3, [r1, #13]
    3a84:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3a88:	734b      	strb	r3, [r1, #13]
	update_cache(thread == _current);
    3a8a:	4b05      	ldr	r3, [pc, #20]	; (3aa0 <unready_thread+0x30>)
    3a8c:	6898      	ldr	r0, [r3, #8]
    3a8e:	1a43      	subs	r3, r0, r1
    3a90:	4258      	negs	r0, r3
    3a92:	4158      	adcs	r0, r3
}
    3a94:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    3a98:	f7ff be1e 	b.w	36d8 <update_cache>
    3a9c:	20000838 	.word	0x20000838
    3aa0:	2000080c 	.word	0x2000080c

00003aa4 <pend>:
{
    3aa4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3aa8:	4606      	mov	r6, r0
    3aaa:	4614      	mov	r4, r2
    3aac:	461d      	mov	r5, r3
	__asm__ volatile(
    3aae:	f04f 0320 	mov.w	r3, #32
    3ab2:	f3ef 8711 	mrs	r7, BASEPRI
    3ab6:	f383 8811 	msr	BASEPRI, r3
    3aba:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    3abe:	f001 ffe7 	bl	5a90 <add_to_waitq_locked>
	__asm__ volatile(
    3ac2:	f387 8811 	msr	BASEPRI, r7
    3ac6:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3aca:	1c6b      	adds	r3, r5, #1
    3acc:	bf08      	it	eq
    3ace:	f1b4 3fff 	cmpeq.w	r4, #4294967295
    3ad2:	d008      	beq.n	3ae6 <pend+0x42>
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
    3ad4:	4622      	mov	r2, r4
    3ad6:	462b      	mov	r3, r5
    3ad8:	f106 0018 	add.w	r0, r6, #24
    3adc:	4903      	ldr	r1, [pc, #12]	; (3aec <pend+0x48>)
}
    3ade:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    3ae2:	f000 ba47 	b.w	3f74 <z_add_timeout>
    3ae6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3aea:	bf00      	nop
    3aec:	00005a51 	.word	0x00005a51

00003af0 <z_pend_curr>:
{
    3af0:	b510      	push	{r4, lr}
    3af2:	460c      	mov	r4, r1
	pending_current = _current;
    3af4:	4b06      	ldr	r3, [pc, #24]	; (3b10 <z_pend_curr+0x20>)
{
    3af6:	4611      	mov	r1, r2
	pending_current = _current;
    3af8:	6898      	ldr	r0, [r3, #8]
    3afa:	4b06      	ldr	r3, [pc, #24]	; (3b14 <z_pend_curr+0x24>)
    3afc:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    3afe:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    3b02:	f7ff ffcf 	bl	3aa4 <pend>
    3b06:	4620      	mov	r0, r4
}
    3b08:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    3b0c:	f7fe ba08 	b.w	1f20 <arch_swap>
    3b10:	2000080c 	.word	0x2000080c
    3b14:	20000840 	.word	0x20000840

00003b18 <z_tick_sleep.part.0>:
	z_impl_k_yield();
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(int32_t ticks)
    3b18:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3b1a:	4605      	mov	r5, r0
#else
	ticks += _TICK_ALIGN;
	timeout = (k_ticks_t) ticks;
#endif

	expected_wakeup_time = ticks + z_tick_get_32();
    3b1c:	f002 f853 	bl	5bc6 <z_tick_get_32>
    3b20:	182c      	adds	r4, r5, r0
	__asm__ volatile(
    3b22:	f04f 0320 	mov.w	r3, #32
    3b26:	f3ef 8711 	mrs	r7, BASEPRI
    3b2a:	f383 8811 	msr	BASEPRI, r3
    3b2e:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    3b32:	4e0d      	ldr	r6, [pc, #52]	; (3b68 <z_tick_sleep.part.0+0x50>)
    3b34:	4b0d      	ldr	r3, [pc, #52]	; (3b6c <z_tick_sleep.part.0+0x54>)
    3b36:	68b0      	ldr	r0, [r6, #8]
    3b38:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
    3b3a:	f7ff ff99 	bl	3a70 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    3b3e:	68b0      	ldr	r0, [r6, #8]
    3b40:	490b      	ldr	r1, [pc, #44]	; (3b70 <z_tick_sleep.part.0+0x58>)
    3b42:	462a      	mov	r2, r5
    3b44:	17eb      	asrs	r3, r5, #31
    3b46:	3018      	adds	r0, #24
    3b48:	f000 fa14 	bl	3f74 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    3b4c:	68b2      	ldr	r2, [r6, #8]
    3b4e:	4638      	mov	r0, r7
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3b50:	7b53      	ldrb	r3, [r2, #13]
    3b52:	f043 0310 	orr.w	r3, r3, #16
    3b56:	7353      	strb	r3, [r2, #13]
    3b58:	f7fe f9e2 	bl	1f20 <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = expected_wakeup_time - z_tick_get_32();
    3b5c:	f002 f833 	bl	5bc6 <z_tick_get_32>
    3b60:	1a20      	subs	r0, r4, r0
		return ticks;
	}
#endif

	return 0;
}
    3b62:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
    3b66:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3b68:	2000080c 	.word	0x2000080c
    3b6c:	20000840 	.word	0x20000840
    3b70:	00005a51 	.word	0x00005a51

00003b74 <z_set_prio>:
{
    3b74:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3b78:	4604      	mov	r4, r0
    3b7a:	f04f 0320 	mov.w	r3, #32
    3b7e:	f3ef 8811 	mrs	r8, BASEPRI
    3b82:	f383 8811 	msr	BASEPRI, r3
    3b86:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3b8a:	7b43      	ldrb	r3, [r0, #13]
    3b8c:	b24e      	sxtb	r6, r1
    3b8e:	06db      	lsls	r3, r3, #27
    3b90:	d12e      	bne.n	3bf0 <z_set_prio+0x7c>
	return !sys_dnode_is_linked(&t->node);
    3b92:	6985      	ldr	r5, [r0, #24]
		if (need_sched) {
    3b94:	bb65      	cbnz	r5, 3bf0 <z_set_prio+0x7c>
				_priq_run_remove(&_kernel.ready_q.runq, thread);
    3b96:	4f18      	ldr	r7, [pc, #96]	; (3bf8 <z_set_prio+0x84>)
    3b98:	4621      	mov	r1, r4
    3b9a:	f107 002c 	add.w	r0, r7, #44	; 0x2c
    3b9e:	f7ff fd85 	bl	36ac <z_priq_dumb_remove>
	return list->head == list;
    3ba2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3ba4:	6b3a      	ldr	r2, [r7, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3ba6:	4283      	cmp	r3, r0
    3ba8:	bf18      	it	ne
    3baa:	461d      	movne	r5, r3
    3bac:	2d00      	cmp	r5, #0
    3bae:	bf38      	it	cc
    3bb0:	2500      	movcc	r5, #0
				thread->base.prio = prio;
    3bb2:	73a6      	strb	r6, [r4, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3bb4:	b1b5      	cbz	r5, 3be4 <z_set_prio+0x70>
	if (thread_1->base.prio < thread_2->base.prio) {
    3bb6:	f995 100e 	ldrsb.w	r1, [r5, #14]
    3bba:	42b1      	cmp	r1, r6
    3bbc:	dc03      	bgt.n	3bc6 <z_set_prio+0x52>
	return (node == list->tail) ? NULL : node->next;
    3bbe:	42aa      	cmp	r2, r5
    3bc0:	d010      	beq.n	3be4 <z_set_prio+0x70>
    3bc2:	682d      	ldr	r5, [r5, #0]
    3bc4:	e7f6      	b.n	3bb4 <z_set_prio+0x40>
	node->prev = successor->prev;
    3bc6:	686a      	ldr	r2, [r5, #4]
	node->next = successor;
    3bc8:	e9c4 5200 	strd	r5, r2, [r4]
	successor->prev->next = node;
    3bcc:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    3bce:	606c      	str	r4, [r5, #4]
			update_cache(1);
    3bd0:	2001      	movs	r0, #1
    3bd2:	f7ff fd81 	bl	36d8 <update_cache>
    3bd6:	2001      	movs	r0, #1
	__asm__ volatile(
    3bd8:	f388 8811 	msr	BASEPRI, r8
    3bdc:	f3bf 8f6f 	isb	sy
}
    3be0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	node->prev = list->tail;
    3be4:	e9c4 0200 	strd	r0, r2, [r4]
	list->tail->next = node;
    3be8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
    3bea:	601c      	str	r4, [r3, #0]
	list->tail = node;
    3bec:	633c      	str	r4, [r7, #48]	; 0x30
}
    3bee:	e7ef      	b.n	3bd0 <z_set_prio+0x5c>
			thread->base.prio = prio;
    3bf0:	2000      	movs	r0, #0
    3bf2:	73a6      	strb	r6, [r4, #14]
    3bf4:	e7f0      	b.n	3bd8 <z_set_prio+0x64>
    3bf6:	bf00      	nop
    3bf8:	2000080c 	.word	0x2000080c

00003bfc <z_sched_init>:
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    3bfc:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    3bfe:	4b04      	ldr	r3, [pc, #16]	; (3c10 <z_sched_init+0x14>)
    3c00:	4608      	mov	r0, r1
    3c02:	f103 022c 	add.w	r2, r3, #44	; 0x2c
	list->tail = (sys_dnode_t *)list;
    3c06:	e9c3 220b 	strd	r2, r2, [r3, #44]	; 0x2c
    3c0a:	f7ff bcfd 	b.w	3608 <k_sched_time_slice_set>
    3c0e:	bf00      	nop
    3c10:	2000080c 	.word	0x2000080c

00003c14 <z_impl_k_yield>:
{
    3c14:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (!z_is_idle_thread_object(_current)) {
    3c16:	4c24      	ldr	r4, [pc, #144]	; (3ca8 <z_impl_k_yield+0x94>)
    3c18:	4b24      	ldr	r3, [pc, #144]	; (3cac <z_impl_k_yield+0x98>)
    3c1a:	68a2      	ldr	r2, [r4, #8]
    3c1c:	429a      	cmp	r2, r3
    3c1e:	d030      	beq.n	3c82 <z_impl_k_yield+0x6e>
	__asm__ volatile(
    3c20:	f04f 0320 	mov.w	r3, #32
    3c24:	f3ef 8511 	mrs	r5, BASEPRI
    3c28:	f383 8811 	msr	BASEPRI, r3
    3c2c:	f3bf 8f6f 	isb	sy
				_priq_run_remove(&_kernel.ready_q.runq,
    3c30:	68a1      	ldr	r1, [r4, #8]
    3c32:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    3c36:	f7ff fd39 	bl	36ac <z_priq_dumb_remove>
	return list->head == list;
    3c3a:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
			_priq_run_add(&_kernel.ready_q.runq, _current);
    3c3c:	68a2      	ldr	r2, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3c3e:	4283      	cmp	r3, r0
    3c40:	bf08      	it	eq
    3c42:	2300      	moveq	r3, #0
    3c44:	2b00      	cmp	r3, #0
    3c46:	bf38      	it	cc
    3c48:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3c4a:	6b21      	ldr	r1, [r4, #48]	; 0x30
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3c4c:	b32b      	cbz	r3, 3c9a <z_impl_k_yield+0x86>
	if (thread_1->base.prio < thread_2->base.prio) {
    3c4e:	f992 700e 	ldrsb.w	r7, [r2, #14]
    3c52:	f993 600e 	ldrsb.w	r6, [r3, #14]
    3c56:	42b7      	cmp	r7, r6
    3c58:	db03      	blt.n	3c62 <z_impl_k_yield+0x4e>
	return (node == list->tail) ? NULL : node->next;
    3c5a:	428b      	cmp	r3, r1
    3c5c:	d01d      	beq.n	3c9a <z_impl_k_yield+0x86>
    3c5e:	681b      	ldr	r3, [r3, #0]
    3c60:	e7f4      	b.n	3c4c <z_impl_k_yield+0x38>
	node->prev = successor->prev;
    3c62:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    3c64:	e9c2 3100 	strd	r3, r1, [r2]
	successor->prev->next = node;
    3c68:	600a      	str	r2, [r1, #0]
	successor->prev = node;
    3c6a:	605a      	str	r2, [r3, #4]
	thread->base.thread_state |= states;
    3c6c:	7b53      	ldrb	r3, [r2, #13]
			update_cache(1);
    3c6e:	2001      	movs	r0, #1
    3c70:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3c74:	7353      	strb	r3, [r2, #13]
    3c76:	f7ff fd2f 	bl	36d8 <update_cache>
	__asm__ volatile(
    3c7a:	f385 8811 	msr	BASEPRI, r5
    3c7e:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    3c82:	f04f 0320 	mov.w	r3, #32
    3c86:	f3ef 8011 	mrs	r0, BASEPRI
    3c8a:	f383 8811 	msr	BASEPRI, r3
    3c8e:	f3bf 8f6f 	isb	sy
}
    3c92:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    3c96:	f7fe b943 	b.w	1f20 <arch_swap>
	node->prev = list->tail;
    3c9a:	e9c2 0100 	strd	r0, r1, [r2]
	list->tail->next = node;
    3c9e:	6b23      	ldr	r3, [r4, #48]	; 0x30
    3ca0:	601a      	str	r2, [r3, #0]
	list->tail = node;
    3ca2:	6322      	str	r2, [r4, #48]	; 0x30
}
    3ca4:	e7e2      	b.n	3c6c <z_impl_k_yield+0x58>
    3ca6:	bf00      	nop
    3ca8:	2000080c 	.word	0x2000080c
    3cac:	20000158 	.word	0x20000158

00003cb0 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    3cb0:	460b      	mov	r3, r1

	__ASSERT(!arch_is_in_isr(), "");
	sys_trace_void(SYS_TRACE_ID_SLEEP);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3cb2:	3301      	adds	r3, #1
    3cb4:	bf08      	it	eq
    3cb6:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    3cba:	b510      	push	{r4, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3cbc:	d106      	bne.n	3ccc <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    3cbe:	4b0b      	ldr	r3, [pc, #44]	; (3cec <z_impl_k_sleep+0x3c>)
    3cc0:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    3cc2:	f7ff fe1f 	bl	3904 <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    3cc6:	f04f 30ff 	mov.w	r0, #4294967295
#endif

	ticks = z_tick_sleep(ticks);
	sys_trace_end_call(SYS_TRACE_ID_SLEEP);
	return k_ticks_to_ms_floor64(ticks);
}
    3cca:	bd10      	pop	{r4, pc}
	ticks = z_tick_sleep(ticks);
    3ccc:	4604      	mov	r4, r0
	if (ticks == 0) {
    3cce:	b948      	cbnz	r0, 3ce4 <z_impl_k_sleep+0x34>
	z_impl_k_yield();
    3cd0:	f7ff ffa0 	bl	3c14 <z_impl_k_yield>
		} else {
			return (t * to_hz + off) / from_hz;
    3cd4:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
    3cd8:	fb84 3400 	smull	r3, r4, r4, r0
    3cdc:	0bd8      	lsrs	r0, r3, #15
    3cde:	ea40 4044 	orr.w	r0, r0, r4, lsl #17
	return k_ticks_to_ms_floor64(ticks);
    3ce2:	e7f2      	b.n	3cca <z_impl_k_sleep+0x1a>
    3ce4:	f7ff ff18 	bl	3b18 <z_tick_sleep.part.0>
    3ce8:	4604      	mov	r4, r0
    3cea:	e7f3      	b.n	3cd4 <z_impl_k_sleep+0x24>
    3cec:	2000080c 	.word	0x2000080c

00003cf0 <z_impl_k_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    3cf0:	4b01      	ldr	r3, [pc, #4]	; (3cf8 <z_impl_k_current_get+0x8>)
    3cf2:	6898      	ldr	r0, [r3, #8]
    3cf4:	4770      	bx	lr
    3cf6:	bf00      	nop
    3cf8:	2000080c 	.word	0x2000080c

00003cfc <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    3cfc:	b538      	push	{r3, r4, r5, lr}
    3cfe:	4604      	mov	r4, r0
    3d00:	f04f 0320 	mov.w	r3, #32
    3d04:	f3ef 8511 	mrs	r5, BASEPRI
    3d08:	f383 8811 	msr	BASEPRI, r3
    3d0c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	sys_trace_semaphore_give(sem);
	thread = z_unpend_first_thread(&sem->wait_q);
    3d10:	f001 fee9 	bl	5ae6 <z_unpend_first_thread>

	if (thread != NULL) {
    3d14:	b148      	cbz	r0, 3d2a <z_impl_k_sem_give+0x2e>
    3d16:	2200      	movs	r2, #0
    3d18:	67c2      	str	r2, [r0, #124]	; 0x7c
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    3d1a:	f001 fe89 	bl	5a30 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    3d1e:	4629      	mov	r1, r5
	sys_trace_end_call(SYS_TRACE_ID_SEMA_GIVE);
}
    3d20:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    3d24:	4804      	ldr	r0, [pc, #16]	; (3d38 <z_impl_k_sem_give+0x3c>)
    3d26:	f7ff bc9b 	b.w	3660 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    3d2a:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    3d2e:	429a      	cmp	r2, r3
    3d30:	bf18      	it	ne
    3d32:	3301      	addne	r3, #1
    3d34:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    3d36:	e7f2      	b.n	3d1e <z_impl_k_sem_give+0x22>
    3d38:	2000086e 	.word	0x2000086e

00003d3c <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    3d3c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3d3e:	4614      	mov	r4, r2
    3d40:	461d      	mov	r5, r3
    3d42:	f04f 0320 	mov.w	r3, #32
    3d46:	f3ef 8111 	mrs	r1, BASEPRI
    3d4a:	f383 8811 	msr	BASEPRI, r3
    3d4e:	f3bf 8f6f 	isb	sy
		  K_TIMEOUT_EQ(timeout, K_NO_WAIT)), "");

	k_spinlock_key_t key = k_spin_lock(&lock);
	sys_trace_semaphore_take(sem);

	if (likely(sem->count > 0U)) {
    3d52:	6883      	ldr	r3, [r0, #8]
    3d54:	b143      	cbz	r3, 3d68 <z_impl_k_sem_take+0x2c>
		sem->count--;
    3d56:	3b01      	subs	r3, #1
    3d58:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    3d5a:	f381 8811 	msr	BASEPRI, r1
    3d5e:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    3d62:	2000      	movs	r0, #0
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);

out:
	sys_trace_end_call(SYS_TRACE_ID_SEMA_TAKE);
	return ret;
}
    3d64:	b003      	add	sp, #12
    3d66:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    3d68:	ea54 0305 	orrs.w	r3, r4, r5
    3d6c:	d106      	bne.n	3d7c <z_impl_k_sem_take+0x40>
    3d6e:	f381 8811 	msr	BASEPRI, r1
    3d72:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    3d76:	f06f 000f 	mvn.w	r0, #15
    3d7a:	e7f3      	b.n	3d64 <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    3d7c:	4602      	mov	r2, r0
    3d7e:	e9cd 4500 	strd	r4, r5, [sp]
    3d82:	4802      	ldr	r0, [pc, #8]	; (3d8c <z_impl_k_sem_take+0x50>)
    3d84:	f7ff feb4 	bl	3af0 <z_pend_curr>
	return ret;
    3d88:	e7ec      	b.n	3d64 <z_impl_k_sem_take+0x28>
    3d8a:	bf00      	nop
    3d8c:	2000086e 	.word	0x2000086e

00003d90 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    3d90:	e92d 41b0 	stmdb	sp!, {r4, r5, r7, r8, lr}
	sys_dlist_init(&w->waitq);
    3d94:	f100 0530 	add.w	r5, r0, #48	; 0x30
    3d98:	b085      	sub	sp, #20
	list->tail = (sys_dnode_t *)list;
    3d9a:	e9c0 550c 	strd	r5, r5, [r0, #48]	; 0x30
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */

	thread_base->user_options = (uint8_t)options;
    3d9e:	9d0e      	ldr	r5, [sp, #56]	; 0x38
{
    3da0:	4604      	mov	r4, r0
	thread_base->user_options = (uint8_t)options;
    3da2:	7305      	strb	r5, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    3da4:	2504      	movs	r5, #4
    3da6:	7345      	strb	r5, [r0, #13]

	thread_base->prio = priority;
    3da8:	9d0d      	ldr	r5, [sp, #52]	; 0x34
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3daa:	3207      	adds	r2, #7
	thread_base->prio = priority;
    3dac:	7385      	strb	r5, [r0, #14]

	thread_base->sched_locked = 0U;
    3dae:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3db0:	f022 0207 	bic.w	r2, r2, #7
	new_thread->stack_info.size = stack_buf_size;
    3db4:	e9c0 121a 	strd	r1, r2, [r0, #104]	; 0x68
	stack_ptr = (char *)stack + stack_obj_size;
    3db8:	eb01 0802 	add.w	r8, r1, r2
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3dbc:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	node->prev = NULL;
    3dbe:	e9c0 5506 	strd	r5, r5, [r0, #24]
	thread_base->sched_locked = 0U;
    3dc2:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    3dc4:	6705      	str	r5, [r0, #112]	; 0x70
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3dc6:	9202      	str	r2, [sp, #8]
    3dc8:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    3dca:	9201      	str	r2, [sp, #4]
    3dcc:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    3dce:	9200      	str	r2, [sp, #0]
    3dd0:	4642      	mov	r2, r8
    3dd2:	f7fe f92f 	bl	2034 <arch_new_thread>
	if (!_current) {
    3dd6:	4b05      	ldr	r3, [pc, #20]	; (3dec <z_setup_new_thread+0x5c>)
	new_thread->fn_abort = NULL;
    3dd8:	e9c4 5517 	strd	r5, r5, [r4, #92]	; 0x5c
	if (!_current) {
    3ddc:	689b      	ldr	r3, [r3, #8]
    3dde:	b103      	cbz	r3, 3de2 <z_setup_new_thread+0x52>
	new_thread->resource_pool = _current->resource_pool;
    3de0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
}
    3de2:	4640      	mov	r0, r8
    3de4:	6763      	str	r3, [r4, #116]	; 0x74
    3de6:	b005      	add	sp, #20
    3de8:	e8bd 81b0 	ldmia.w	sp!, {r4, r5, r7, r8, pc}
    3dec:	2000080c 	.word	0x2000080c

00003df0 <z_init_static_threads>:
{
    3df0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    3df4:	4e2a      	ldr	r6, [pc, #168]	; (3ea0 <z_init_static_threads+0xb0>)
    3df6:	4d2b      	ldr	r5, [pc, #172]	; (3ea4 <z_init_static_threads+0xb4>)
    3df8:	46b0      	mov	r8, r6
{
    3dfa:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    3dfc:	42b5      	cmp	r5, r6
    3dfe:	f105 0430 	add.w	r4, r5, #48	; 0x30
    3e02:	d310      	bcc.n	3e26 <z_init_static_threads+0x36>
	k_sched_lock();
    3e04:	f7ff fc3e 	bl	3684 <k_sched_lock>
    3e08:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    3e0c:	f240 36e7 	movw	r6, #999	; 0x3e7
    3e10:	2700      	movs	r7, #0
	_FOREACH_STATIC_THREAD(thread_data) {
    3e12:	4c24      	ldr	r4, [pc, #144]	; (3ea4 <z_init_static_threads+0xb4>)
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
    3e14:	f8df a090 	ldr.w	sl, [pc, #144]	; 3ea8 <z_init_static_threads+0xb8>
    3e18:	4544      	cmp	r4, r8
    3e1a:	d321      	bcc.n	3e60 <z_init_static_threads+0x70>
}
    3e1c:	b006      	add	sp, #24
    3e1e:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    3e22:	f7ff bc81 	b.w	3728 <k_sched_unlock>
		z_setup_new_thread(
    3e26:	f854 3c04 	ldr.w	r3, [r4, #-4]
    3e2a:	9305      	str	r3, [sp, #20]
    3e2c:	f854 3c10 	ldr.w	r3, [r4, #-16]
    3e30:	9304      	str	r3, [sp, #16]
    3e32:	f854 3c14 	ldr.w	r3, [r4, #-20]
    3e36:	9303      	str	r3, [sp, #12]
    3e38:	f854 3c18 	ldr.w	r3, [r4, #-24]
    3e3c:	9302      	str	r3, [sp, #8]
    3e3e:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    3e42:	9301      	str	r3, [sp, #4]
    3e44:	f854 3c20 	ldr.w	r3, [r4, #-32]
    3e48:	9300      	str	r3, [sp, #0]
    3e4a:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    3e4e:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    3e52:	f7ff ff9d 	bl	3d90 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3e56:	f854 3c30 	ldr.w	r3, [r4, #-48]
    3e5a:	65dd      	str	r5, [r3, #92]	; 0x5c
    3e5c:	4625      	mov	r5, r4
    3e5e:	e7cd      	b.n	3dfc <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    3e60:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3e62:	1c5a      	adds	r2, r3, #1
    3e64:	d00d      	beq.n	3e82 <z_init_static_threads+0x92>
    3e66:	4630      	mov	r0, r6
    3e68:	4639      	mov	r1, r7
					    K_MSEC(thread_data->init_delay));
    3e6a:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3e6e:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3e72:	42b9      	cmp	r1, r7
    3e74:	bf08      	it	eq
    3e76:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    3e78:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3e7a:	d104      	bne.n	3e86 <z_init_static_threads+0x96>
	z_sched_start(thread);
    3e7c:	4628      	mov	r0, r5
    3e7e:	f7ff fca7 	bl	37d0 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    3e82:	3430      	adds	r4, #48	; 0x30
    3e84:	e7c8      	b.n	3e18 <z_init_static_threads+0x28>
    3e86:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3e8a:	2300      	movs	r3, #0
    3e8c:	f7fc f9d6 	bl	23c <__aeabi_uldivmod>
    3e90:	4602      	mov	r2, r0
    3e92:	460b      	mov	r3, r1
    3e94:	f105 0018 	add.w	r0, r5, #24
    3e98:	4651      	mov	r1, sl
    3e9a:	f000 f86b 	bl	3f74 <z_add_timeout>
    3e9e:	e7f0      	b.n	3e82 <z_init_static_threads+0x92>
    3ea0:	20000108 	.word	0x20000108
    3ea4:	20000108 	.word	0x20000108
    3ea8:	00005a51 	.word	0x00005a51

00003eac <z_self_abort>:
#include <syscall_handler.h>
#include <logging/log.h>
LOG_MODULE_DECLARE(os);

FUNC_NORETURN void z_self_abort(void)
{
    3eac:	b508      	push	{r3, lr}
	__asm__ volatile(
    3eae:	f04f 0320 	mov.w	r3, #32
    3eb2:	f3ef 8411 	mrs	r4, BASEPRI
    3eb6:	f383 8811 	msr	BASEPRI, r3
    3eba:	f3bf 8f6f 	isb	sy
	 * while we set this up
	 */
	key = arch_irq_lock();
	cpu = _current_cpu;
	__ASSERT(cpu->pending_abort == NULL, "already have a thread to abort");
	cpu->pending_abort = _current;
    3ebe:	4b04      	ldr	r3, [pc, #16]	; (3ed0 <z_self_abort+0x24>)
    3ec0:	6898      	ldr	r0, [r3, #8]
    3ec2:	6118      	str	r0, [r3, #16]
	z_impl_k_thread_suspend(thread);
    3ec4:	f7ff fd1e 	bl	3904 <z_impl_k_thread_suspend>
    3ec8:	4620      	mov	r0, r4
    3eca:	f7fe f829 	bl	1f20 <arch_swap>
		_current, cpu->idle_thread);

	k_thread_suspend(_current);
	z_swap_irqlock(key);
	__ASSERT(false, "should never get here");
	CODE_UNREACHABLE;
    3ece:	bf00      	nop
    3ed0:	2000080c 	.word	0x2000080c

00003ed4 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? z_clock_elapsed() : 0U;
    3ed4:	4b03      	ldr	r3, [pc, #12]	; (3ee4 <elapsed+0x10>)
    3ed6:	681b      	ldr	r3, [r3, #0]
    3ed8:	b90b      	cbnz	r3, 3ede <elapsed+0xa>
    3eda:	f7fd bd23 	b.w	1924 <z_clock_elapsed>
}
    3ede:	2000      	movs	r0, #0
    3ee0:	4770      	bx	lr
    3ee2:	bf00      	nop
    3ee4:	2000084c 	.word	0x2000084c

00003ee8 <remove_timeout>:
{
    3ee8:	b530      	push	{r4, r5, lr}
    3eea:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3eec:	b168      	cbz	r0, 3f0a <remove_timeout+0x22>
    3eee:	4a0a      	ldr	r2, [pc, #40]	; (3f18 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    3ef0:	6852      	ldr	r2, [r2, #4]
    3ef2:	4290      	cmp	r0, r2
    3ef4:	d009      	beq.n	3f0a <remove_timeout+0x22>
	if (next(t) != NULL) {
    3ef6:	b143      	cbz	r3, 3f0a <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    3ef8:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    3efc:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    3f00:	1912      	adds	r2, r2, r4
    3f02:	eb45 0101 	adc.w	r1, r5, r1
    3f06:	e9c3 2104 	strd	r2, r1, [r3, #16]
	node->prev->next = node->next;
    3f0a:	6842      	ldr	r2, [r0, #4]
    3f0c:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    3f0e:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    3f10:	2300      	movs	r3, #0
	node->prev = NULL;
    3f12:	e9c0 3300 	strd	r3, r3, [r0]
}
    3f16:	bd30      	pop	{r4, r5, pc}
    3f18:	2000004c 	.word	0x2000004c

00003f1c <next_timeout>:
	return list->head == list;
    3f1c:	4b13      	ldr	r3, [pc, #76]	; (3f6c <next_timeout+0x50>)

static int32_t next_timeout(void)
{
    3f1e:	b510      	push	{r4, lr}
    3f20:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3f22:	429c      	cmp	r4, r3
    3f24:	bf08      	it	eq
    3f26:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3f28:	f7ff ffd4 	bl	3ed4 <elapsed>
	int32_t ret = to == NULL ? MAX_WAIT
    3f2c:	b1cc      	cbz	r4, 3f62 <next_timeout+0x46>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3f2e:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    3f32:	1a12      	subs	r2, r2, r0
    3f34:	eb63 73e0 	sbc.w	r3, r3, r0, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    3f38:	2a01      	cmp	r2, #1
    3f3a:	f173 0100 	sbcs.w	r1, r3, #0
    3f3e:	db13      	blt.n	3f68 <next_timeout+0x4c>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3f40:	4610      	mov	r0, r2
    3f42:	f06f 4200 	mvn.w	r2, #2147483648	; 0x80000000
    3f46:	4619      	mov	r1, r3
    3f48:	2300      	movs	r3, #0
    3f4a:	4282      	cmp	r2, r0
    3f4c:	eb73 0401 	sbcs.w	r4, r3, r1
    3f50:	da00      	bge.n	3f54 <next_timeout+0x38>
    3f52:	4610      	mov	r0, r2

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    3f54:	4b06      	ldr	r3, [pc, #24]	; (3f70 <next_timeout+0x54>)
    3f56:	695b      	ldr	r3, [r3, #20]
    3f58:	b113      	cbz	r3, 3f60 <next_timeout+0x44>
    3f5a:	4298      	cmp	r0, r3
    3f5c:	bfa8      	it	ge
    3f5e:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    3f60:	bd10      	pop	{r4, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    3f62:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    3f66:	e7f5      	b.n	3f54 <next_timeout+0x38>
    3f68:	2000      	movs	r0, #0
    3f6a:	e7f3      	b.n	3f54 <next_timeout+0x38>
    3f6c:	2000004c 	.word	0x2000004c
    3f70:	2000080c 	.word	0x2000080c

00003f74 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    3f74:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3f78:	9101      	str	r1, [sp, #4]
    3f7a:	4619      	mov	r1, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3f7c:	1c4b      	adds	r3, r1, #1
    3f7e:	bf08      	it	eq
    3f80:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    3f84:	4682      	mov	sl, r0
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3f86:	d06b      	beq.n	4060 <z_add_timeout+0xec>
#ifdef CONFIG_LEGACY_TIMEOUT_API
	k_ticks_t ticks = timeout;
#else
	k_ticks_t ticks = timeout.ticks + 1;

	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    3f88:	f06f 0301 	mvn.w	r3, #1
    3f8c:	f04f 3bff 	mov.w	fp, #4294967295
	k_ticks_t ticks = timeout.ticks + 1;
    3f90:	1c54      	adds	r4, r2, #1
    3f92:	f141 0500 	adc.w	r5, r1, #0
	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    3f96:	ebb3 0804 	subs.w	r8, r3, r4
    3f9a:	eb6b 0905 	sbc.w	r9, fp, r5
    3f9e:	f1b8 0f00 	cmp.w	r8, #0
    3fa2:	f179 0300 	sbcs.w	r3, r9, #0
    3fa6:	db0f      	blt.n	3fc8 <z_add_timeout+0x54>
		ticks = Z_TICK_ABS(ticks) - (curr_tick + elapsed());
    3fa8:	f7ff ff94 	bl	3ed4 <elapsed>
    3fac:	f06f 0301 	mvn.w	r3, #1
    3fb0:	4a32      	ldr	r2, [pc, #200]	; (407c <z_add_timeout+0x108>)
    3fb2:	e9d2 1c00 	ldrd	r1, ip, [r2]
    3fb6:	1a5b      	subs	r3, r3, r1
    3fb8:	eb6b 020c 	sbc.w	r2, fp, ip
    3fbc:	1b1e      	subs	r6, r3, r4
    3fbe:	eb62 0705 	sbc.w	r7, r2, r5
    3fc2:	1a34      	subs	r4, r6, r0
    3fc4:	eb67 75e0 	sbc.w	r5, r7, r0, asr #31
	}
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    3fc8:	9b01      	ldr	r3, [sp, #4]
    3fca:	f8ca 3008 	str.w	r3, [sl, #8]
    3fce:	f04f 0320 	mov.w	r3, #32
    3fd2:	f3ef 8611 	mrs	r6, BASEPRI
    3fd6:	f383 8811 	msr	BASEPRI, r3
    3fda:	f3bf 8f6f 	isb	sy
	ticks = MAX(1, ticks);

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		to->dticks = ticks + elapsed();
    3fde:	f7ff ff79 	bl	3ed4 <elapsed>
	ticks = MAX(1, ticks);
    3fe2:	2c01      	cmp	r4, #1
    3fe4:	f175 0300 	sbcs.w	r3, r5, #0
    3fe8:	bfbc      	itt	lt
    3fea:	2401      	movlt	r4, #1
    3fec:	2500      	movlt	r5, #0
	return list->head == list;
    3fee:	4b24      	ldr	r3, [pc, #144]	; (4080 <z_add_timeout+0x10c>)
		to->dticks = ticks + elapsed();
    3ff0:	1824      	adds	r4, r4, r0
    3ff2:	681a      	ldr	r2, [r3, #0]
    3ff4:	eb45 75e0 	adc.w	r5, r5, r0, asr #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3ff8:	429a      	cmp	r2, r3
    3ffa:	e9ca 4504 	strd	r4, r5, [sl, #16]
    3ffe:	d001      	beq.n	4004 <z_add_timeout+0x90>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4000:	685f      	ldr	r7, [r3, #4]
		for (t = first(); t != NULL; t = next(t)) {
    4002:	b952      	cbnz	r2, 401a <z_add_timeout+0xa6>
	node->prev = list->tail;
    4004:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    4006:	f8ca 3000 	str.w	r3, [sl]
	node->prev = list->tail;
    400a:	f8ca 2004 	str.w	r2, [sl, #4]
	list->tail->next = node;
    400e:	685a      	ldr	r2, [r3, #4]
    4010:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    4014:	f8c3 a004 	str.w	sl, [r3, #4]
}
    4018:	e014      	b.n	4044 <z_add_timeout+0xd0>
			if (t->dticks > to->dticks) {
    401a:	e9d2 8904 	ldrd	r8, r9, [r2, #16]
    401e:	e9da 4504 	ldrd	r4, r5, [sl, #16]
    4022:	4544      	cmp	r4, r8
    4024:	eb75 0109 	sbcs.w	r1, r5, r9
    4028:	da1d      	bge.n	4066 <z_add_timeout+0xf2>
				t->dticks -= to->dticks;
    402a:	ebb8 0004 	subs.w	r0, r8, r4
    402e:	eb69 0105 	sbc.w	r1, r9, r5
    4032:	e9c2 0104 	strd	r0, r1, [r2, #16]
	node->prev = successor->prev;
    4036:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    4038:	e9ca 2100 	strd	r2, r1, [sl]
	successor->prev->next = node;
    403c:	f8c1 a000 	str.w	sl, [r1]
	successor->prev = node;
    4040:	f8c2 a004 	str.w	sl, [r2, #4]
	return list->head == list;
    4044:	681a      	ldr	r2, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4046:	429a      	cmp	r2, r3
    4048:	d006      	beq.n	4058 <z_add_timeout+0xe4>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    404a:	4592      	cmp	sl, r2
    404c:	d104      	bne.n	4058 <z_add_timeout+0xe4>
			z_clock_set_timeout(next_timeout(), false);
    404e:	f7ff ff65 	bl	3f1c <next_timeout>
    4052:	2100      	movs	r1, #0
    4054:	f7fd fbfe 	bl	1854 <z_clock_set_timeout>
	__asm__ volatile(
    4058:	f386 8811 	msr	BASEPRI, r6
    405c:	f3bf 8f6f 	isb	sy
		}
	}
}
    4060:	b003      	add	sp, #12
    4062:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			to->dticks -= t->dticks;
    4066:	ebb4 0008 	subs.w	r0, r4, r8
    406a:	eb65 0109 	sbc.w	r1, r5, r9
	return (node == list->tail) ? NULL : node->next;
    406e:	42ba      	cmp	r2, r7
    4070:	e9ca 0104 	strd	r0, r1, [sl, #16]
    4074:	d0c6      	beq.n	4004 <z_add_timeout+0x90>
    4076:	6812      	ldr	r2, [r2, #0]
    4078:	e7c3      	b.n	4002 <z_add_timeout+0x8e>
    407a:	bf00      	nop
    407c:	20000258 	.word	0x20000258
    4080:	2000004c 	.word	0x2000004c

00004084 <z_clock_announce>:
		}
	}
}

void z_clock_announce(int32_t ticks)
{
    4084:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4088:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    408a:	f7ff fbf9 	bl	3880 <z_time_slice>
	__asm__ volatile(
    408e:	f04f 0320 	mov.w	r3, #32
    4092:	f3ef 8411 	mrs	r4, BASEPRI
    4096:	f383 8811 	msr	BASEPRI, r3
    409a:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    409e:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 4150 <z_clock_announce+0xcc>
    40a2:	4d2a      	ldr	r5, [pc, #168]	; (414c <z_clock_announce+0xc8>)
    40a4:	4651      	mov	r1, sl
	return list->head == list;
    40a6:	f8df b0ac 	ldr.w	fp, [pc, #172]	; 4154 <z_clock_announce+0xd0>
    40aa:	602e      	str	r6, [r5, #0]
    40ac:	f8d5 c000 	ldr.w	ip, [r5]
    40b0:	f8db 0000 	ldr.w	r0, [fp]
    40b4:	4662      	mov	r2, ip
    40b6:	e9da 8900 	ldrd	r8, r9, [sl]
    40ba:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    40bc:	4558      	cmp	r0, fp
    40be:	e9cd 2300 	strd	r2, r3, [sp]
    40c2:	d00d      	beq.n	40e0 <z_clock_announce+0x5c>

	while (first() != NULL && first()->dticks <= announce_remaining) {
    40c4:	b160      	cbz	r0, 40e0 <z_clock_announce+0x5c>
    40c6:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    40ca:	45b4      	cmp	ip, r6
    40cc:	41bb      	sbcs	r3, r7
    40ce:	da1d      	bge.n	410c <z_clock_announce+0x88>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    40d0:	9b00      	ldr	r3, [sp, #0]
    40d2:	ebb6 0c03 	subs.w	ip, r6, r3
    40d6:	9b01      	ldr	r3, [sp, #4]
    40d8:	eb67 0603 	sbc.w	r6, r7, r3
    40dc:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
	announce_remaining = 0;
    40e0:	2600      	movs	r6, #0
	curr_tick += announce_remaining;
    40e2:	9b00      	ldr	r3, [sp, #0]
	announce_remaining = 0;
    40e4:	602e      	str	r6, [r5, #0]
	curr_tick += announce_remaining;
    40e6:	eb13 0208 	adds.w	r2, r3, r8
    40ea:	9b01      	ldr	r3, [sp, #4]
    40ec:	eb43 0309 	adc.w	r3, r3, r9
    40f0:	e9c1 2300 	strd	r2, r3, [r1]

	z_clock_set_timeout(next_timeout(), false);
    40f4:	f7ff ff12 	bl	3f1c <next_timeout>
    40f8:	4631      	mov	r1, r6
    40fa:	f7fd fbab 	bl	1854 <z_clock_set_timeout>
	__asm__ volatile(
    40fe:	f384 8811 	msr	BASEPRI, r4
    4102:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    4106:	b003      	add	sp, #12
    4108:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		t->dticks = 0;
    410c:	2200      	movs	r2, #0
    410e:	2300      	movs	r3, #0
		curr_tick += dt;
    4110:	eb18 0806 	adds.w	r8, r8, r6
    4114:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    4118:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    411c:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    4120:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    4124:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    4126:	f7ff fedf 	bl	3ee8 <remove_timeout>
    412a:	f384 8811 	msr	BASEPRI, r4
    412e:	f3bf 8f6f 	isb	sy
		t->fn(t);
    4132:	6883      	ldr	r3, [r0, #8]
    4134:	4798      	blx	r3
	__asm__ volatile(
    4136:	f04f 0320 	mov.w	r3, #32
    413a:	f3ef 8411 	mrs	r4, BASEPRI
    413e:	f383 8811 	msr	BASEPRI, r3
    4142:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    4146:	4902      	ldr	r1, [pc, #8]	; (4150 <z_clock_announce+0xcc>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    4148:	e7b0      	b.n	40ac <z_clock_announce+0x28>
    414a:	bf00      	nop
    414c:	2000084c 	.word	0x2000084c
    4150:	20000258 	.word	0x20000258
    4154:	2000004c 	.word	0x2000004c

00004158 <z_tick_get>:

int64_t z_tick_get(void)
{
    4158:	b510      	push	{r4, lr}
    415a:	f04f 0320 	mov.w	r3, #32
    415e:	f3ef 8411 	mrs	r4, BASEPRI
    4162:	f383 8811 	msr	BASEPRI, r3
    4166:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + z_clock_elapsed();
    416a:	f7fd fbdb 	bl	1924 <z_clock_elapsed>
    416e:	4b06      	ldr	r3, [pc, #24]	; (4188 <z_tick_get+0x30>)
    4170:	e9d3 2300 	ldrd	r2, r3, [r3]
    4174:	1812      	adds	r2, r2, r0
    4176:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    417a:	f384 8811 	msr	BASEPRI, r4
    417e:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    4182:	4610      	mov	r0, r2
    4184:	4619      	mov	r1, r3
    4186:	bd10      	pop	{r4, pc}
    4188:	20000258 	.word	0x20000258

0000418c <statics_init>:
	z_waitq_init(&h->wait_q);
	sys_heap_init(&h->heap, mem, bytes);
}

static int statics_init(const struct device *unused)
{
    418c:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(unused);
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    418e:	4c06      	ldr	r4, [pc, #24]	; (41a8 <statics_init+0x1c>)
    4190:	4d06      	ldr	r5, [pc, #24]	; (41ac <statics_init+0x20>)
    4192:	42ac      	cmp	r4, r5
    4194:	d301      	bcc.n	419a <statics_init+0xe>
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
	}
	return 0;
}
    4196:	2000      	movs	r0, #0
    4198:	bd38      	pop	{r3, r4, r5, pc}
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
    419a:	4620      	mov	r0, r4
    419c:	e9d4 1201 	ldrd	r1, r2, [r4, #4]
    41a0:	f001 fd15 	bl	5bce <k_heap_init>
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    41a4:	3414      	adds	r4, #20
    41a6:	e7f4      	b.n	4192 <statics_init+0x6>
    41a8:	20000108 	.word	0x20000108
    41ac:	20000108 	.word	0x20000108

000041b0 <CC_PalMemCopyPlat>:
    41b0:	f001 bafe 	b.w	57b0 <memmove>

000041b4 <CC_PalMemSetZeroPlat>:
    41b4:	460a      	mov	r2, r1
    41b6:	2100      	movs	r1, #0
    41b8:	f001 bb3c 	b.w	5834 <memset>

000041bc <CC_PalInit>:
    41bc:	b510      	push	{r4, lr}
    41be:	4811      	ldr	r0, [pc, #68]	; (4204 <CC_PalInit+0x48>)
    41c0:	f000 f848 	bl	4254 <CC_PalMutexCreate>
    41c4:	b100      	cbz	r0, 41c8 <CC_PalInit+0xc>
    41c6:	bd10      	pop	{r4, pc}
    41c8:	480f      	ldr	r0, [pc, #60]	; (4208 <CC_PalInit+0x4c>)
    41ca:	f000 f843 	bl	4254 <CC_PalMutexCreate>
    41ce:	2800      	cmp	r0, #0
    41d0:	d1f9      	bne.n	41c6 <CC_PalInit+0xa>
    41d2:	4c0e      	ldr	r4, [pc, #56]	; (420c <CC_PalInit+0x50>)
    41d4:	4620      	mov	r0, r4
    41d6:	f000 f83d 	bl	4254 <CC_PalMutexCreate>
    41da:	2800      	cmp	r0, #0
    41dc:	d1f3      	bne.n	41c6 <CC_PalInit+0xa>
    41de:	4b0c      	ldr	r3, [pc, #48]	; (4210 <CC_PalInit+0x54>)
    41e0:	480c      	ldr	r0, [pc, #48]	; (4214 <CC_PalInit+0x58>)
    41e2:	601c      	str	r4, [r3, #0]
    41e4:	f000 f836 	bl	4254 <CC_PalMutexCreate>
    41e8:	4601      	mov	r1, r0
    41ea:	2800      	cmp	r0, #0
    41ec:	d1eb      	bne.n	41c6 <CC_PalInit+0xa>
    41ee:	f000 f82d 	bl	424c <CC_PalDmaInit>
    41f2:	4604      	mov	r4, r0
    41f4:	b108      	cbz	r0, 41fa <CC_PalInit+0x3e>
    41f6:	4620      	mov	r0, r4
    41f8:	bd10      	pop	{r4, pc}
    41fa:	f000 f851 	bl	42a0 <CC_PalPowerSaveModeInit>
    41fe:	4620      	mov	r0, r4
    4200:	e7fa      	b.n	41f8 <CC_PalInit+0x3c>
    4202:	bf00      	nop
    4204:	20000060 	.word	0x20000060
    4208:	20000054 	.word	0x20000054
    420c:	2000005c 	.word	0x2000005c
    4210:	20000064 	.word	0x20000064
    4214:	20000058 	.word	0x20000058

00004218 <CC_PalTerminate>:
    4218:	b508      	push	{r3, lr}
    421a:	4808      	ldr	r0, [pc, #32]	; (423c <CC_PalTerminate+0x24>)
    421c:	f000 f824 	bl	4268 <CC_PalMutexDestroy>
    4220:	4807      	ldr	r0, [pc, #28]	; (4240 <CC_PalTerminate+0x28>)
    4222:	f000 f821 	bl	4268 <CC_PalMutexDestroy>
    4226:	4807      	ldr	r0, [pc, #28]	; (4244 <CC_PalTerminate+0x2c>)
    4228:	f000 f81e 	bl	4268 <CC_PalMutexDestroy>
    422c:	4806      	ldr	r0, [pc, #24]	; (4248 <CC_PalTerminate+0x30>)
    422e:	f000 f81b 	bl	4268 <CC_PalMutexDestroy>
    4232:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    4236:	f000 b80b 	b.w	4250 <CC_PalDmaTerminate>
    423a:	bf00      	nop
    423c:	20000060 	.word	0x20000060
    4240:	20000054 	.word	0x20000054
    4244:	2000005c 	.word	0x2000005c
    4248:	20000058 	.word	0x20000058

0000424c <CC_PalDmaInit>:
    424c:	2000      	movs	r0, #0
    424e:	4770      	bx	lr

00004250 <CC_PalDmaTerminate>:
    4250:	4770      	bx	lr
    4252:	bf00      	nop

00004254 <CC_PalMutexCreate>:
    4254:	b508      	push	{r3, lr}
    4256:	4b03      	ldr	r3, [pc, #12]	; (4264 <CC_PalMutexCreate+0x10>)
    4258:	6802      	ldr	r2, [r0, #0]
    425a:	681b      	ldr	r3, [r3, #0]
    425c:	6810      	ldr	r0, [r2, #0]
    425e:	4798      	blx	r3
    4260:	2000      	movs	r0, #0
    4262:	bd08      	pop	{r3, pc}
    4264:	20000078 	.word	0x20000078

00004268 <CC_PalMutexDestroy>:
    4268:	b508      	push	{r3, lr}
    426a:	4b03      	ldr	r3, [pc, #12]	; (4278 <CC_PalMutexDestroy+0x10>)
    426c:	6802      	ldr	r2, [r0, #0]
    426e:	685b      	ldr	r3, [r3, #4]
    4270:	6810      	ldr	r0, [r2, #0]
    4272:	4798      	blx	r3
    4274:	2000      	movs	r0, #0
    4276:	bd08      	pop	{r3, pc}
    4278:	20000078 	.word	0x20000078

0000427c <CC_PalMutexLock>:
    427c:	4b02      	ldr	r3, [pc, #8]	; (4288 <CC_PalMutexLock+0xc>)
    427e:	6802      	ldr	r2, [r0, #0]
    4280:	689b      	ldr	r3, [r3, #8]
    4282:	6810      	ldr	r0, [r2, #0]
    4284:	4718      	bx	r3
    4286:	bf00      	nop
    4288:	20000078 	.word	0x20000078

0000428c <CC_PalMutexUnlock>:
    428c:	b508      	push	{r3, lr}
    428e:	4b03      	ldr	r3, [pc, #12]	; (429c <CC_PalMutexUnlock+0x10>)
    4290:	6802      	ldr	r2, [r0, #0]
    4292:	68db      	ldr	r3, [r3, #12]
    4294:	6810      	ldr	r0, [r2, #0]
    4296:	4798      	blx	r3
    4298:	2000      	movs	r0, #0
    429a:	bd08      	pop	{r3, pc}
    429c:	20000078 	.word	0x20000078

000042a0 <CC_PalPowerSaveModeInit>:
    42a0:	b570      	push	{r4, r5, r6, lr}
    42a2:	4c09      	ldr	r4, [pc, #36]	; (42c8 <CC_PalPowerSaveModeInit+0x28>)
    42a4:	4d09      	ldr	r5, [pc, #36]	; (42cc <CC_PalPowerSaveModeInit+0x2c>)
    42a6:	6920      	ldr	r0, [r4, #16]
    42a8:	68ab      	ldr	r3, [r5, #8]
    42aa:	4798      	blx	r3
    42ac:	b118      	cbz	r0, 42b6 <CC_PalPowerSaveModeInit+0x16>
    42ae:	4b08      	ldr	r3, [pc, #32]	; (42d0 <CC_PalPowerSaveModeInit+0x30>)
    42b0:	4808      	ldr	r0, [pc, #32]	; (42d4 <CC_PalPowerSaveModeInit+0x34>)
    42b2:	685b      	ldr	r3, [r3, #4]
    42b4:	4798      	blx	r3
    42b6:	2100      	movs	r1, #0
    42b8:	4a07      	ldr	r2, [pc, #28]	; (42d8 <CC_PalPowerSaveModeInit+0x38>)
    42ba:	68eb      	ldr	r3, [r5, #12]
    42bc:	6011      	str	r1, [r2, #0]
    42be:	6920      	ldr	r0, [r4, #16]
    42c0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    42c4:	4718      	bx	r3
    42c6:	bf00      	nop
    42c8:	20000088 	.word	0x20000088
    42cc:	20000078 	.word	0x20000078
    42d0:	20000068 	.word	0x20000068
    42d4:	0000604c 	.word	0x0000604c
    42d8:	20000850 	.word	0x20000850

000042dc <CC_PalPowerSaveModeSelect>:
    42dc:	b570      	push	{r4, r5, r6, lr}
    42de:	4d1a      	ldr	r5, [pc, #104]	; (4348 <CC_PalPowerSaveModeSelect+0x6c>)
    42e0:	4e1a      	ldr	r6, [pc, #104]	; (434c <CC_PalPowerSaveModeSelect+0x70>)
    42e2:	4604      	mov	r4, r0
    42e4:	68b2      	ldr	r2, [r6, #8]
    42e6:	6928      	ldr	r0, [r5, #16]
    42e8:	4790      	blx	r2
    42ea:	b9f0      	cbnz	r0, 432a <CC_PalPowerSaveModeSelect+0x4e>
    42ec:	b15c      	cbz	r4, 4306 <CC_PalPowerSaveModeSelect+0x2a>
    42ee:	4c18      	ldr	r4, [pc, #96]	; (4350 <CC_PalPowerSaveModeSelect+0x74>)
    42f0:	6823      	ldr	r3, [r4, #0]
    42f2:	b1ab      	cbz	r3, 4320 <CC_PalPowerSaveModeSelect+0x44>
    42f4:	2b01      	cmp	r3, #1
    42f6:	d01a      	beq.n	432e <CC_PalPowerSaveModeSelect+0x52>
    42f8:	3b01      	subs	r3, #1
    42fa:	6023      	str	r3, [r4, #0]
    42fc:	6928      	ldr	r0, [r5, #16]
    42fe:	68f3      	ldr	r3, [r6, #12]
    4300:	4798      	blx	r3
    4302:	2000      	movs	r0, #0
    4304:	bd70      	pop	{r4, r5, r6, pc}
    4306:	4c12      	ldr	r4, [pc, #72]	; (4350 <CC_PalPowerSaveModeSelect+0x74>)
    4308:	6821      	ldr	r1, [r4, #0]
    430a:	b939      	cbnz	r1, 431c <CC_PalPowerSaveModeSelect+0x40>
    430c:	2001      	movs	r0, #1
    430e:	4b11      	ldr	r3, [pc, #68]	; (4354 <CC_PalPowerSaveModeSelect+0x78>)
    4310:	4a11      	ldr	r2, [pc, #68]	; (4358 <CC_PalPowerSaveModeSelect+0x7c>)
    4312:	f8c3 0500 	str.w	r0, [r3, #1280]	; 0x500
    4316:	6813      	ldr	r3, [r2, #0]
    4318:	2b00      	cmp	r3, #0
    431a:	d1fc      	bne.n	4316 <CC_PalPowerSaveModeSelect+0x3a>
    431c:	3101      	adds	r1, #1
    431e:	6021      	str	r1, [r4, #0]
    4320:	68f3      	ldr	r3, [r6, #12]
    4322:	6928      	ldr	r0, [r5, #16]
    4324:	4798      	blx	r3
    4326:	2000      	movs	r0, #0
    4328:	bd70      	pop	{r4, r5, r6, pc}
    432a:	480c      	ldr	r0, [pc, #48]	; (435c <CC_PalPowerSaveModeSelect+0x80>)
    432c:	bd70      	pop	{r4, r5, r6, pc}
    432e:	4a0a      	ldr	r2, [pc, #40]	; (4358 <CC_PalPowerSaveModeSelect+0x7c>)
    4330:	6813      	ldr	r3, [r2, #0]
    4332:	2b00      	cmp	r3, #0
    4334:	d1fc      	bne.n	4330 <CC_PalPowerSaveModeSelect+0x54>
    4336:	4a07      	ldr	r2, [pc, #28]	; (4354 <CC_PalPowerSaveModeSelect+0x78>)
    4338:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    433c:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    4340:	f000 f820 	bl	4384 <CC_HalMaskInterrupt>
    4344:	6823      	ldr	r3, [r4, #0]
    4346:	e7d7      	b.n	42f8 <CC_PalPowerSaveModeSelect+0x1c>
    4348:	20000088 	.word	0x20000088
    434c:	20000078 	.word	0x20000078
    4350:	20000850 	.word	0x20000850
    4354:	50840000 	.word	0x50840000
    4358:	50841910 	.word	0x50841910
    435c:	ffff8fe9 	.word	0xffff8fe9

00004360 <CC_HalInit>:
    4360:	2000      	movs	r0, #0
    4362:	4770      	bx	lr

00004364 <CC_HalTerminate>:
    4364:	2000      	movs	r0, #0
    4366:	4770      	bx	lr

00004368 <CC_HalClearInterruptBit>:
    4368:	0543      	lsls	r3, r0, #21
    436a:	d503      	bpl.n	4374 <CC_HalClearInterruptBit+0xc>
    436c:	f04f 32ff 	mov.w	r2, #4294967295
    4370:	4b02      	ldr	r3, [pc, #8]	; (437c <CC_HalClearInterruptBit+0x14>)
    4372:	601a      	str	r2, [r3, #0]
    4374:	4b02      	ldr	r3, [pc, #8]	; (4380 <CC_HalClearInterruptBit+0x18>)
    4376:	6018      	str	r0, [r3, #0]
    4378:	4770      	bx	lr
    437a:	bf00      	nop
    437c:	50841108 	.word	0x50841108
    4380:	50841a08 	.word	0x50841a08

00004384 <CC_HalMaskInterrupt>:
    4384:	4b01      	ldr	r3, [pc, #4]	; (438c <CC_HalMaskInterrupt+0x8>)
    4386:	6018      	str	r0, [r3, #0]
    4388:	4770      	bx	lr
    438a:	bf00      	nop
    438c:	50841a04 	.word	0x50841a04

00004390 <CC_HalWaitInterruptRND>:
    4390:	b108      	cbz	r0, 4396 <CC_HalWaitInterruptRND+0x6>
    4392:	f000 b803 	b.w	439c <CC_PalWaitInterruptRND>
    4396:	f44f 0075 	mov.w	r0, #16056320	; 0xf50000
    439a:	4770      	bx	lr

0000439c <CC_PalWaitInterruptRND>:
    439c:	4602      	mov	r2, r0
    439e:	4807      	ldr	r0, [pc, #28]	; (43bc <CC_PalWaitInterruptRND+0x20>)
    43a0:	6803      	ldr	r3, [r0, #0]
    43a2:	4213      	tst	r3, r2
    43a4:	d0fc      	beq.n	43a0 <CC_PalWaitInterruptRND+0x4>
    43a6:	b121      	cbz	r1, 43b2 <CC_PalWaitInterruptRND+0x16>
    43a8:	4b05      	ldr	r3, [pc, #20]	; (43c0 <CC_PalWaitInterruptRND+0x24>)
    43aa:	4806      	ldr	r0, [pc, #24]	; (43c4 <CC_PalWaitInterruptRND+0x28>)
    43ac:	681b      	ldr	r3, [r3, #0]
    43ae:	600b      	str	r3, [r1, #0]
    43b0:	6003      	str	r3, [r0, #0]
    43b2:	4b05      	ldr	r3, [pc, #20]	; (43c8 <CC_PalWaitInterruptRND+0x2c>)
    43b4:	2000      	movs	r0, #0
    43b6:	601a      	str	r2, [r3, #0]
    43b8:	4770      	bx	lr
    43ba:	bf00      	nop
    43bc:	50841a00 	.word	0x50841a00
    43c0:	50841104 	.word	0x50841104
    43c4:	50841108 	.word	0x50841108
    43c8:	50841a08 	.word	0x50841a08

000043cc <mbedtls_platform_setup>:
    43cc:	f000 b89e 	b.w	450c <nrf_cc3xx_platform_init>

000043d0 <mbedtls_platform_zeroize>:
    43d0:	b138      	cbz	r0, 43e2 <mbedtls_platform_zeroize+0x12>
    43d2:	b131      	cbz	r1, 43e2 <mbedtls_platform_zeroize+0x12>
    43d4:	2200      	movs	r2, #0
    43d6:	4401      	add	r1, r0
    43d8:	4603      	mov	r3, r0
    43da:	3001      	adds	r0, #1
    43dc:	4281      	cmp	r1, r0
    43de:	701a      	strb	r2, [r3, #0]
    43e0:	d1fa      	bne.n	43d8 <mbedtls_platform_zeroize+0x8>
    43e2:	4770      	bx	lr

000043e4 <mbedtls_hardware_poll>:
    43e4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    43e8:	f5ad 7d1a 	sub.w	sp, sp, #616	; 0x268
    43ec:	460e      	mov	r6, r1
    43ee:	9205      	str	r2, [sp, #20]
    43f0:	2100      	movs	r1, #0
    43f2:	4614      	mov	r4, r2
    43f4:	a812      	add	r0, sp, #72	; 0x48
    43f6:	f44f 7208 	mov.w	r2, #544	; 0x220
    43fa:	461d      	mov	r5, r3
    43fc:	f001 fa1a 	bl	5834 <memset>
    4400:	2100      	movs	r1, #0
    4402:	2228      	movs	r2, #40	; 0x28
    4404:	a808      	add	r0, sp, #32
    4406:	9106      	str	r1, [sp, #24]
    4408:	f001 fa14 	bl	5834 <memset>
    440c:	2e00      	cmp	r6, #0
    440e:	d03c      	beq.n	448a <mbedtls_hardware_poll+0xa6>
    4410:	2d00      	cmp	r5, #0
    4412:	d03a      	beq.n	448a <mbedtls_hardware_poll+0xa6>
    4414:	2c00      	cmp	r4, #0
    4416:	d038      	beq.n	448a <mbedtls_hardware_poll+0xa6>
    4418:	2104      	movs	r1, #4
    441a:	a806      	add	r0, sp, #24
    441c:	f7ff feca 	bl	41b4 <CC_PalMemSetZeroPlat>
    4420:	a808      	add	r0, sp, #32
    4422:	2128      	movs	r1, #40	; 0x28
    4424:	f7ff fec6 	bl	41b4 <CC_PalMemSetZeroPlat>
    4428:	a808      	add	r0, sp, #32
    442a:	f000 f831 	bl	4490 <RNG_PLAT_SetUserRngParameters>
    442e:	b178      	cbz	r0, 4450 <mbedtls_hardware_poll+0x6c>
    4430:	f04f 37ff 	mov.w	r7, #4294967295
    4434:	f44f 7108 	mov.w	r1, #544	; 0x220
    4438:	a812      	add	r0, sp, #72	; 0x48
    443a:	f7ff ffc9 	bl	43d0 <mbedtls_platform_zeroize>
    443e:	2104      	movs	r1, #4
    4440:	a806      	add	r0, sp, #24
    4442:	f7ff ffc5 	bl	43d0 <mbedtls_platform_zeroize>
    4446:	4638      	mov	r0, r7
    4448:	f50d 7d1a 	add.w	sp, sp, #616	; 0x268
    444c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4450:	ab12      	add	r3, sp, #72	; 0x48
    4452:	f10d 081c 	add.w	r8, sp, #28
    4456:	4602      	mov	r2, r0
    4458:	e9cd 5301 	strd	r5, r3, [sp, #4]
    445c:	9003      	str	r0, [sp, #12]
    445e:	ab05      	add	r3, sp, #20
    4460:	a908      	add	r1, sp, #32
    4462:	f8cd 8000 	str.w	r8, [sp]
    4466:	a806      	add	r0, sp, #24
    4468:	f000 fd14 	bl	4e94 <LLF_RND_GetTrngSource>
    446c:	2800      	cmp	r0, #0
    446e:	d1df      	bne.n	4430 <mbedtls_hardware_poll+0x4c>
    4470:	682b      	ldr	r3, [r5, #0]
    4472:	42a3      	cmp	r3, r4
    4474:	d3dc      	bcc.n	4430 <mbedtls_hardware_poll+0x4c>
    4476:	f8d8 1000 	ldr.w	r1, [r8]
    447a:	4607      	mov	r7, r0
    447c:	4622      	mov	r2, r4
    447e:	4630      	mov	r0, r6
    4480:	3108      	adds	r1, #8
    4482:	f7ff fe95 	bl	41b0 <CC_PalMemCopyPlat>
    4486:	602c      	str	r4, [r5, #0]
    4488:	e7d4      	b.n	4434 <mbedtls_hardware_poll+0x50>
    448a:	f04f 37ff 	mov.w	r7, #4294967295
    448e:	e7da      	b.n	4446 <mbedtls_hardware_poll+0x62>

00004490 <RNG_PLAT_SetUserRngParameters>:
    4490:	231c      	movs	r3, #28
    4492:	b530      	push	{r4, r5, lr}
    4494:	b083      	sub	sp, #12
    4496:	a901      	add	r1, sp, #4
    4498:	4604      	mov	r4, r0
    449a:	9301      	str	r3, [sp, #4]
    449c:	f000 f9ce 	bl	483c <CC_PalTrngParamGet>
    44a0:	4605      	mov	r5, r0
    44a2:	b938      	cbnz	r0, 44b4 <RNG_PLAT_SetUserRngParameters+0x24>
    44a4:	9b01      	ldr	r3, [sp, #4]
    44a6:	2b1c      	cmp	r3, #28
    44a8:	d007      	beq.n	44ba <RNG_PLAT_SetUserRngParameters+0x2a>
    44aa:	4d16      	ldr	r5, [pc, #88]	; (4504 <RNG_PLAT_SetUserRngParameters+0x74>)
    44ac:	4620      	mov	r0, r4
    44ae:	211c      	movs	r1, #28
    44b0:	f7ff fe80 	bl	41b4 <CC_PalMemSetZeroPlat>
    44b4:	4628      	mov	r0, r5
    44b6:	b003      	add	sp, #12
    44b8:	bd30      	pop	{r4, r5, pc}
    44ba:	2101      	movs	r1, #1
    44bc:	e9d4 3200 	ldrd	r3, r2, [r4]
    44c0:	3b00      	subs	r3, #0
    44c2:	bf18      	it	ne
    44c4:	2301      	movne	r3, #1
    44c6:	61e1      	str	r1, [r4, #28]
    44c8:	b10a      	cbz	r2, 44ce <RNG_PLAT_SetUserRngParameters+0x3e>
    44ca:	f043 0302 	orr.w	r3, r3, #2
    44ce:	68a2      	ldr	r2, [r4, #8]
    44d0:	b932      	cbnz	r2, 44e0 <RNG_PLAT_SetUserRngParameters+0x50>
    44d2:	68e2      	ldr	r2, [r4, #12]
    44d4:	b942      	cbnz	r2, 44e8 <RNG_PLAT_SetUserRngParameters+0x58>
    44d6:	e9c4 3208 	strd	r3, r2, [r4, #32]
    44da:	b98b      	cbnz	r3, 4500 <RNG_PLAT_SetUserRngParameters+0x70>
    44dc:	4d0a      	ldr	r5, [pc, #40]	; (4508 <RNG_PLAT_SetUserRngParameters+0x78>)
    44de:	e7e5      	b.n	44ac <RNG_PLAT_SetUserRngParameters+0x1c>
    44e0:	68e2      	ldr	r2, [r4, #12]
    44e2:	f043 0304 	orr.w	r3, r3, #4
    44e6:	b13a      	cbz	r2, 44f8 <RNG_PLAT_SetUserRngParameters+0x68>
    44e8:	2200      	movs	r2, #0
    44ea:	4628      	mov	r0, r5
    44ec:	f043 0308 	orr.w	r3, r3, #8
    44f0:	e9c4 3208 	strd	r3, r2, [r4, #32]
    44f4:	b003      	add	sp, #12
    44f6:	bd30      	pop	{r4, r5, pc}
    44f8:	4615      	mov	r5, r2
    44fa:	e9c4 3208 	strd	r3, r2, [r4, #32]
    44fe:	e7d9      	b.n	44b4 <RNG_PLAT_SetUserRngParameters+0x24>
    4500:	4615      	mov	r5, r2
    4502:	e7d7      	b.n	44b4 <RNG_PLAT_SetUserRngParameters+0x24>
    4504:	00f00c37 	.word	0x00f00c37
    4508:	00f00c0e 	.word	0x00f00c0e

0000450c <nrf_cc3xx_platform_init>:
    450c:	b510      	push	{r4, lr}
    450e:	4c0c      	ldr	r4, [pc, #48]	; (4540 <nrf_cc3xx_platform_init+0x34>)
    4510:	6823      	ldr	r3, [r4, #0]
    4512:	b113      	cbz	r3, 451a <nrf_cc3xx_platform_init+0xe>
    4514:	4b0b      	ldr	r3, [pc, #44]	; (4544 <nrf_cc3xx_platform_init+0x38>)
    4516:	681b      	ldr	r3, [r3, #0]
    4518:	b92b      	cbnz	r3, 4526 <nrf_cc3xx_platform_init+0x1a>
    451a:	f000 f94f 	bl	47bc <CC_LibInit>
    451e:	b930      	cbnz	r0, 452e <nrf_cc3xx_platform_init+0x22>
    4520:	2201      	movs	r2, #1
    4522:	4b08      	ldr	r3, [pc, #32]	; (4544 <nrf_cc3xx_platform_init+0x38>)
    4524:	601a      	str	r2, [r3, #0]
    4526:	2301      	movs	r3, #1
    4528:	2000      	movs	r0, #0
    452a:	6023      	str	r3, [r4, #0]
    452c:	bd10      	pop	{r4, pc}
    452e:	3801      	subs	r0, #1
    4530:	2806      	cmp	r0, #6
    4532:	d901      	bls.n	4538 <nrf_cc3xx_platform_init+0x2c>
    4534:	4804      	ldr	r0, [pc, #16]	; (4548 <nrf_cc3xx_platform_init+0x3c>)
    4536:	bd10      	pop	{r4, pc}
    4538:	4b04      	ldr	r3, [pc, #16]	; (454c <nrf_cc3xx_platform_init+0x40>)
    453a:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    453e:	bd10      	pop	{r4, pc}
    4540:	20000854 	.word	0x20000854
    4544:	20000858 	.word	0x20000858
    4548:	ffff8ffe 	.word	0xffff8ffe
    454c:	0000606c 	.word	0x0000606c

00004550 <nrf_cc3xx_platform_init_no_rng>:
    4550:	b510      	push	{r4, lr}
    4552:	4c0a      	ldr	r4, [pc, #40]	; (457c <nrf_cc3xx_platform_init_no_rng+0x2c>)
    4554:	6823      	ldr	r3, [r4, #0]
    4556:	b11b      	cbz	r3, 4560 <nrf_cc3xx_platform_init_no_rng+0x10>
    4558:	2301      	movs	r3, #1
    455a:	2000      	movs	r0, #0
    455c:	6023      	str	r3, [r4, #0]
    455e:	bd10      	pop	{r4, pc}
    4560:	f000 f898 	bl	4694 <CC_LibInitNoRng>
    4564:	2800      	cmp	r0, #0
    4566:	d0f7      	beq.n	4558 <nrf_cc3xx_platform_init_no_rng+0x8>
    4568:	3801      	subs	r0, #1
    456a:	2806      	cmp	r0, #6
    456c:	d803      	bhi.n	4576 <nrf_cc3xx_platform_init_no_rng+0x26>
    456e:	4b04      	ldr	r3, [pc, #16]	; (4580 <nrf_cc3xx_platform_init_no_rng+0x30>)
    4570:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    4574:	bd10      	pop	{r4, pc}
    4576:	4803      	ldr	r0, [pc, #12]	; (4584 <nrf_cc3xx_platform_init_no_rng+0x34>)
    4578:	bd10      	pop	{r4, pc}
    457a:	bf00      	nop
    457c:	20000854 	.word	0x20000854
    4580:	0000606c 	.word	0x0000606c
    4584:	ffff8ffe 	.word	0xffff8ffe

00004588 <nrf_cc3xx_platform_abort>:
    4588:	f3bf 8f4f 	dsb	sy
    458c:	4905      	ldr	r1, [pc, #20]	; (45a4 <nrf_cc3xx_platform_abort+0x1c>)
    458e:	4b06      	ldr	r3, [pc, #24]	; (45a8 <nrf_cc3xx_platform_abort+0x20>)
    4590:	68ca      	ldr	r2, [r1, #12]
    4592:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    4596:	4313      	orrs	r3, r2
    4598:	60cb      	str	r3, [r1, #12]
    459a:	f3bf 8f4f 	dsb	sy
    459e:	bf00      	nop
    45a0:	e7fd      	b.n	459e <nrf_cc3xx_platform_abort+0x16>
    45a2:	bf00      	nop
    45a4:	e000ed00 	.word	0xe000ed00
    45a8:	05fa0004 	.word	0x05fa0004

000045ac <CC_PalAbort>:
    45ac:	4b01      	ldr	r3, [pc, #4]	; (45b4 <CC_PalAbort+0x8>)
    45ae:	685b      	ldr	r3, [r3, #4]
    45b0:	4718      	bx	r3
    45b2:	bf00      	nop
    45b4:	20000068 	.word	0x20000068

000045b8 <nrf_cc3xx_platform_set_abort>:
    45b8:	4b02      	ldr	r3, [pc, #8]	; (45c4 <nrf_cc3xx_platform_set_abort+0xc>)
    45ba:	e9d0 1200 	ldrd	r1, r2, [r0]
    45be:	e9c3 1200 	strd	r1, r2, [r3]
    45c2:	4770      	bx	lr
    45c4:	20000068 	.word	0x20000068

000045c8 <mutex_unlock>:
    45c8:	b148      	cbz	r0, 45de <mutex_unlock+0x16>
    45ca:	6843      	ldr	r3, [r0, #4]
    45cc:	b12b      	cbz	r3, 45da <mutex_unlock+0x12>
    45ce:	f3bf 8f5f 	dmb	sy
    45d2:	2300      	movs	r3, #0
    45d4:	6003      	str	r3, [r0, #0]
    45d6:	4618      	mov	r0, r3
    45d8:	4770      	bx	lr
    45da:	4802      	ldr	r0, [pc, #8]	; (45e4 <mutex_unlock+0x1c>)
    45dc:	4770      	bx	lr
    45de:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    45e2:	4770      	bx	lr
    45e4:	ffff8fea 	.word	0xffff8fea

000045e8 <mutex_free>:
    45e8:	b510      	push	{r4, lr}
    45ea:	4604      	mov	r4, r0
    45ec:	b128      	cbz	r0, 45fa <mutex_free+0x12>
    45ee:	6863      	ldr	r3, [r4, #4]
    45f0:	b113      	cbz	r3, 45f8 <mutex_free+0x10>
    45f2:	2300      	movs	r3, #0
    45f4:	6023      	str	r3, [r4, #0]
    45f6:	6063      	str	r3, [r4, #4]
    45f8:	bd10      	pop	{r4, pc}
    45fa:	4b02      	ldr	r3, [pc, #8]	; (4604 <mutex_free+0x1c>)
    45fc:	4802      	ldr	r0, [pc, #8]	; (4608 <mutex_free+0x20>)
    45fe:	685b      	ldr	r3, [r3, #4]
    4600:	4798      	blx	r3
    4602:	e7f4      	b.n	45ee <mutex_free+0x6>
    4604:	20000068 	.word	0x20000068
    4608:	00006088 	.word	0x00006088

0000460c <mutex_init>:
    460c:	b510      	push	{r4, lr}
    460e:	4604      	mov	r4, r0
    4610:	b130      	cbz	r0, 4620 <mutex_init+0x14>
    4612:	2200      	movs	r2, #0
    4614:	6863      	ldr	r3, [r4, #4]
    4616:	6022      	str	r2, [r4, #0]
    4618:	f043 0301 	orr.w	r3, r3, #1
    461c:	6063      	str	r3, [r4, #4]
    461e:	bd10      	pop	{r4, pc}
    4620:	4801      	ldr	r0, [pc, #4]	; (4628 <mutex_init+0x1c>)
    4622:	f7ff ffc3 	bl	45ac <CC_PalAbort>
    4626:	e7f4      	b.n	4612 <mutex_init+0x6>
    4628:	000060b0 	.word	0x000060b0

0000462c <mutex_lock>:
    462c:	b180      	cbz	r0, 4650 <mutex_lock+0x24>
    462e:	6843      	ldr	r3, [r0, #4]
    4630:	b163      	cbz	r3, 464c <mutex_lock+0x20>
    4632:	2201      	movs	r2, #1
    4634:	e8d0 3fef 	ldaex	r3, [r0]
    4638:	e8c0 2fe1 	stlex	r1, r2, [r0]
    463c:	2900      	cmp	r1, #0
    463e:	d1f9      	bne.n	4634 <mutex_lock+0x8>
    4640:	2b01      	cmp	r3, #1
    4642:	d0f7      	beq.n	4634 <mutex_lock+0x8>
    4644:	f3bf 8f5f 	dmb	sy
    4648:	2000      	movs	r0, #0
    464a:	4770      	bx	lr
    464c:	4802      	ldr	r0, [pc, #8]	; (4658 <mutex_lock+0x2c>)
    464e:	4770      	bx	lr
    4650:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    4654:	4770      	bx	lr
    4656:	bf00      	nop
    4658:	ffff8fea 	.word	0xffff8fea

0000465c <nrf_cc3xx_platform_set_mutexes>:
    465c:	b470      	push	{r4, r5, r6}
    465e:	4b0b      	ldr	r3, [pc, #44]	; (468c <nrf_cc3xx_platform_set_mutexes+0x30>)
    4660:	6806      	ldr	r6, [r0, #0]
    4662:	68c2      	ldr	r2, [r0, #12]
    4664:	e9d0 5401 	ldrd	r5, r4, [r0, #4]
    4668:	e9c3 4202 	strd	r4, r2, [r3, #8]
    466c:	e9c3 6500 	strd	r6, r5, [r3]
    4670:	e9d1 0203 	ldrd	r0, r2, [r1, #12]
    4674:	680e      	ldr	r6, [r1, #0]
    4676:	4b06      	ldr	r3, [pc, #24]	; (4690 <nrf_cc3xx_platform_set_mutexes+0x34>)
    4678:	e9d1 5401 	ldrd	r5, r4, [r1, #4]
    467c:	e9c3 6500 	strd	r6, r5, [r3]
    4680:	e9c3 4002 	strd	r4, r0, [r3, #8]
    4684:	611a      	str	r2, [r3, #16]
    4686:	bc70      	pop	{r4, r5, r6}
    4688:	4770      	bx	lr
    468a:	bf00      	nop
    468c:	20000078 	.word	0x20000078
    4690:	20000088 	.word	0x20000088

00004694 <CC_LibInitNoRng>:
    4694:	b510      	push	{r4, lr}
    4696:	f7ff fe63 	bl	4360 <CC_HalInit>
    469a:	b120      	cbz	r0, 46a6 <CC_LibInitNoRng+0x12>
    469c:	2403      	movs	r4, #3
    469e:	f7ff fdbb 	bl	4218 <CC_PalTerminate>
    46a2:	4620      	mov	r0, r4
    46a4:	bd10      	pop	{r4, pc}
    46a6:	f7ff fd89 	bl	41bc <CC_PalInit>
    46aa:	b990      	cbnz	r0, 46d2 <CC_LibInitNoRng+0x3e>
    46ac:	f7ff fe16 	bl	42dc <CC_PalPowerSaveModeSelect>
    46b0:	b990      	cbnz	r0, 46d8 <CC_LibInitNoRng+0x44>
    46b2:	4b0f      	ldr	r3, [pc, #60]	; (46f0 <CC_LibInitNoRng+0x5c>)
    46b4:	681b      	ldr	r3, [r3, #0]
    46b6:	0e1b      	lsrs	r3, r3, #24
    46b8:	2bf0      	cmp	r3, #240	; 0xf0
    46ba:	d108      	bne.n	46ce <CC_LibInitNoRng+0x3a>
    46bc:	4a0d      	ldr	r2, [pc, #52]	; (46f4 <CC_LibInitNoRng+0x60>)
    46be:	4b0e      	ldr	r3, [pc, #56]	; (46f8 <CC_LibInitNoRng+0x64>)
    46c0:	6812      	ldr	r2, [r2, #0]
    46c2:	429a      	cmp	r2, r3
    46c4:	d00a      	beq.n	46dc <CC_LibInitNoRng+0x48>
    46c6:	2407      	movs	r4, #7
    46c8:	f7ff fe4c 	bl	4364 <CC_HalTerminate>
    46cc:	e7e7      	b.n	469e <CC_LibInitNoRng+0xa>
    46ce:	2406      	movs	r4, #6
    46d0:	e7fa      	b.n	46c8 <CC_LibInitNoRng+0x34>
    46d2:	2404      	movs	r4, #4
    46d4:	4620      	mov	r0, r4
    46d6:	bd10      	pop	{r4, pc}
    46d8:	2400      	movs	r4, #0
    46da:	e7f5      	b.n	46c8 <CC_LibInitNoRng+0x34>
    46dc:	2001      	movs	r0, #1
    46de:	f7ff fdfd 	bl	42dc <CC_PalPowerSaveModeSelect>
    46e2:	4604      	mov	r4, r0
    46e4:	2800      	cmp	r0, #0
    46e6:	d1f7      	bne.n	46d8 <CC_LibInitNoRng+0x44>
    46e8:	4b04      	ldr	r3, [pc, #16]	; (46fc <CC_LibInitNoRng+0x68>)
    46ea:	6018      	str	r0, [r3, #0]
    46ec:	e7d9      	b.n	46a2 <CC_LibInitNoRng+0xe>
    46ee:	bf00      	nop
    46f0:	50841928 	.word	0x50841928
    46f4:	50841a24 	.word	0x50841a24
    46f8:	20e00000 	.word	0x20e00000
    46fc:	50841a0c 	.word	0x50841a0c

00004700 <CC_LibInitRngModule>:
    4700:	b530      	push	{r4, r5, lr}
    4702:	f5ad 7d15 	sub.w	sp, sp, #596	; 0x254
    4706:	f44f 7208 	mov.w	r2, #544	; 0x220
    470a:	2100      	movs	r1, #0
    470c:	a80c      	add	r0, sp, #48	; 0x30
    470e:	f001 f891 	bl	5834 <memset>
    4712:	2100      	movs	r1, #0
    4714:	2228      	movs	r2, #40	; 0x28
    4716:	a802      	add	r0, sp, #8
    4718:	9101      	str	r1, [sp, #4]
    471a:	f001 f88b 	bl	5834 <memset>
    471e:	a802      	add	r0, sp, #8
    4720:	f7ff feb6 	bl	4490 <RNG_PLAT_SetUserRngParameters>
    4724:	b120      	cbz	r0, 4730 <CC_LibInitRngModule+0x30>
    4726:	2405      	movs	r4, #5
    4728:	4620      	mov	r0, r4
    472a:	f50d 7d15 	add.w	sp, sp, #596	; 0x254
    472e:	bd30      	pop	{r4, r5, pc}
    4730:	4d1d      	ldr	r5, [pc, #116]	; (47a8 <CC_LibInitRngModule+0xa8>)
    4732:	f04f 31ff 	mov.w	r1, #4294967295
    4736:	6828      	ldr	r0, [r5, #0]
    4738:	f7ff fda0 	bl	427c <CC_PalMutexLock>
    473c:	4604      	mov	r4, r0
    473e:	b9e8      	cbnz	r0, 477c <CC_LibInitRngModule+0x7c>
    4740:	2000      	movs	r0, #0
    4742:	f7ff fdcb 	bl	42dc <CC_PalPowerSaveModeSelect>
    4746:	bb58      	cbnz	r0, 47a0 <CC_LibInitRngModule+0xa0>
    4748:	aa0c      	add	r2, sp, #48	; 0x30
    474a:	a902      	add	r1, sp, #8
    474c:	a801      	add	r0, sp, #4
    474e:	f000 fbed 	bl	4f2c <LLF_RND_RunTrngStartupTest>
    4752:	4604      	mov	r4, r0
    4754:	2001      	movs	r0, #1
    4756:	f7ff fdc1 	bl	42dc <CC_PalPowerSaveModeSelect>
    475a:	b9e8      	cbnz	r0, 4798 <CC_LibInitRngModule+0x98>
    475c:	6828      	ldr	r0, [r5, #0]
    475e:	f7ff fd95 	bl	428c <CC_PalMutexUnlock>
    4762:	b928      	cbnz	r0, 4770 <CC_LibInitRngModule+0x70>
    4764:	2c00      	cmp	r4, #0
    4766:	d1de      	bne.n	4726 <CC_LibInitRngModule+0x26>
    4768:	4620      	mov	r0, r4
    476a:	f50d 7d15 	add.w	sp, sp, #596	; 0x254
    476e:	bd30      	pop	{r4, r5, pc}
    4770:	480e      	ldr	r0, [pc, #56]	; (47ac <CC_LibInitRngModule+0xac>)
    4772:	f7ff ff1b 	bl	45ac <CC_PalAbort>
    4776:	2c00      	cmp	r4, #0
    4778:	d0f6      	beq.n	4768 <CC_LibInitRngModule+0x68>
    477a:	e7d4      	b.n	4726 <CC_LibInitRngModule+0x26>
    477c:	480c      	ldr	r0, [pc, #48]	; (47b0 <CC_LibInitRngModule+0xb0>)
    477e:	f7ff ff15 	bl	45ac <CC_PalAbort>
    4782:	2c01      	cmp	r4, #1
    4784:	d1dc      	bne.n	4740 <CC_LibInitRngModule+0x40>
    4786:	6828      	ldr	r0, [r5, #0]
    4788:	f7ff fd80 	bl	428c <CC_PalMutexUnlock>
    478c:	2800      	cmp	r0, #0
    478e:	d0ca      	beq.n	4726 <CC_LibInitRngModule+0x26>
    4790:	4806      	ldr	r0, [pc, #24]	; (47ac <CC_LibInitRngModule+0xac>)
    4792:	f7ff ff0b 	bl	45ac <CC_PalAbort>
    4796:	e7c6      	b.n	4726 <CC_LibInitRngModule+0x26>
    4798:	4806      	ldr	r0, [pc, #24]	; (47b4 <CC_LibInitRngModule+0xb4>)
    479a:	f7ff ff07 	bl	45ac <CC_PalAbort>
    479e:	e7dd      	b.n	475c <CC_LibInitRngModule+0x5c>
    47a0:	4805      	ldr	r0, [pc, #20]	; (47b8 <CC_LibInitRngModule+0xb8>)
    47a2:	f7ff ff03 	bl	45ac <CC_PalAbort>
    47a6:	e7cf      	b.n	4748 <CC_LibInitRngModule+0x48>
    47a8:	20000064 	.word	0x20000064
    47ac:	000060ec 	.word	0x000060ec
    47b0:	000060d4 	.word	0x000060d4
    47b4:	00006124 	.word	0x00006124
    47b8:	00006104 	.word	0x00006104

000047bc <CC_LibInit>:
    47bc:	b508      	push	{r3, lr}
    47be:	f7ff fdcf 	bl	4360 <CC_HalInit>
    47c2:	b118      	cbz	r0, 47cc <CC_LibInit+0x10>
    47c4:	f7ff fd28 	bl	4218 <CC_PalTerminate>
    47c8:	2003      	movs	r0, #3
    47ca:	bd08      	pop	{r3, pc}
    47cc:	f7ff fcf6 	bl	41bc <CC_PalInit>
    47d0:	b9c0      	cbnz	r0, 4804 <CC_LibInit+0x48>
    47d2:	f7ff fd83 	bl	42dc <CC_PalPowerSaveModeSelect>
    47d6:	b9b8      	cbnz	r0, 4808 <CC_LibInit+0x4c>
    47d8:	4b14      	ldr	r3, [pc, #80]	; (482c <CC_LibInit+0x70>)
    47da:	681b      	ldr	r3, [r3, #0]
    47dc:	0e1b      	lsrs	r3, r3, #24
    47de:	2bf0      	cmp	r3, #240	; 0xf0
    47e0:	d10a      	bne.n	47f8 <CC_LibInit+0x3c>
    47e2:	4a13      	ldr	r2, [pc, #76]	; (4830 <CC_LibInit+0x74>)
    47e4:	4b13      	ldr	r3, [pc, #76]	; (4834 <CC_LibInit+0x78>)
    47e6:	6812      	ldr	r2, [r2, #0]
    47e8:	429a      	cmp	r2, r3
    47ea:	d017      	beq.n	481c <CC_LibInit+0x60>
    47ec:	f7ff fdba 	bl	4364 <CC_HalTerminate>
    47f0:	f7ff fd12 	bl	4218 <CC_PalTerminate>
    47f4:	2007      	movs	r0, #7
    47f6:	bd08      	pop	{r3, pc}
    47f8:	f7ff fdb4 	bl	4364 <CC_HalTerminate>
    47fc:	f7ff fd0c 	bl	4218 <CC_PalTerminate>
    4800:	2006      	movs	r0, #6
    4802:	bd08      	pop	{r3, pc}
    4804:	2004      	movs	r0, #4
    4806:	bd08      	pop	{r3, pc}
    4808:	f7ff fdac 	bl	4364 <CC_HalTerminate>
    480c:	f7ff fd04 	bl	4218 <CC_PalTerminate>
    4810:	f7ff ff76 	bl	4700 <CC_LibInitRngModule>
    4814:	2800      	cmp	r0, #0
    4816:	bf18      	it	ne
    4818:	2005      	movne	r0, #5
    481a:	bd08      	pop	{r3, pc}
    481c:	2001      	movs	r0, #1
    481e:	f7ff fd5d 	bl	42dc <CC_PalPowerSaveModeSelect>
    4822:	2800      	cmp	r0, #0
    4824:	d1f0      	bne.n	4808 <CC_LibInit+0x4c>
    4826:	4b04      	ldr	r3, [pc, #16]	; (4838 <CC_LibInit+0x7c>)
    4828:	6018      	str	r0, [r3, #0]
    482a:	e7f1      	b.n	4810 <CC_LibInit+0x54>
    482c:	50841928 	.word	0x50841928
    4830:	50841a24 	.word	0x50841a24
    4834:	20e00000 	.word	0x20e00000
    4838:	50841a0c 	.word	0x50841a0c

0000483c <CC_PalTrngParamGet>:
    483c:	2800      	cmp	r0, #0
    483e:	d066      	beq.n	490e <CC_PalTrngParamGet+0xd2>
    4840:	2900      	cmp	r1, #0
    4842:	d064      	beq.n	490e <CC_PalTrngParamGet+0xd2>
    4844:	680b      	ldr	r3, [r1, #0]
    4846:	2b1c      	cmp	r3, #28
    4848:	d161      	bne.n	490e <CC_PalTrngParamGet+0xd2>
    484a:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    484e:	4a3b      	ldr	r2, [pc, #236]	; (493c <CC_PalTrngParamGet+0x100>)
    4850:	f8d3 1c10 	ldr.w	r1, [r3, #3088]	; 0xc10
    4854:	4291      	cmp	r1, r2
    4856:	d05c      	beq.n	4912 <CC_PalTrngParamGet+0xd6>
    4858:	f8d3 2c10 	ldr.w	r2, [r3, #3088]	; 0xc10
    485c:	3201      	adds	r2, #1
    485e:	d058      	beq.n	4912 <CC_PalTrngParamGet+0xd6>
    4860:	f8d3 2c10 	ldr.w	r2, [r3, #3088]	; 0xc10
    4864:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    4868:	6002      	str	r2, [r0, #0]
    486a:	f8d3 1c14 	ldr.w	r1, [r3, #3092]	; 0xc14
    486e:	4a34      	ldr	r2, [pc, #208]	; (4940 <CC_PalTrngParamGet+0x104>)
    4870:	4291      	cmp	r1, r2
    4872:	d060      	beq.n	4936 <CC_PalTrngParamGet+0xfa>
    4874:	f8d3 2c14 	ldr.w	r2, [r3, #3092]	; 0xc14
    4878:	3201      	adds	r2, #1
    487a:	d05c      	beq.n	4936 <CC_PalTrngParamGet+0xfa>
    487c:	f8d3 2c14 	ldr.w	r2, [r3, #3092]	; 0xc14
    4880:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    4884:	6042      	str	r2, [r0, #4]
    4886:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    488a:	f512 7f94 	cmn.w	r2, #296	; 0x128
    488e:	d04f      	beq.n	4930 <CC_PalTrngParamGet+0xf4>
    4890:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    4894:	3201      	adds	r2, #1
    4896:	d04b      	beq.n	4930 <CC_PalTrngParamGet+0xf4>
    4898:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    489c:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    48a0:	6082      	str	r2, [r0, #8]
    48a2:	f8d3 1c1c 	ldr.w	r1, [r3, #3100]	; 0xc1c
    48a6:	4a27      	ldr	r2, [pc, #156]	; (4944 <CC_PalTrngParamGet+0x108>)
    48a8:	4291      	cmp	r1, r2
    48aa:	d03e      	beq.n	492a <CC_PalTrngParamGet+0xee>
    48ac:	f8d3 2c1c 	ldr.w	r2, [r3, #3100]	; 0xc1c
    48b0:	3201      	adds	r2, #1
    48b2:	d03a      	beq.n	492a <CC_PalTrngParamGet+0xee>
    48b4:	f8d3 2c1c 	ldr.w	r2, [r3, #3100]	; 0xc1c
    48b8:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    48bc:	60c2      	str	r2, [r0, #12]
    48be:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    48c2:	3270      	adds	r2, #112	; 0x70
    48c4:	d02f      	beq.n	4926 <CC_PalTrngParamGet+0xea>
    48c6:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    48ca:	3201      	adds	r2, #1
    48cc:	d02b      	beq.n	4926 <CC_PalTrngParamGet+0xea>
    48ce:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    48d2:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    48d6:	6102      	str	r2, [r0, #16]
    48d8:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    48dc:	32af      	adds	r2, #175	; 0xaf
    48de:	d020      	beq.n	4922 <CC_PalTrngParamGet+0xe6>
    48e0:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    48e4:	3201      	adds	r2, #1
    48e6:	d01c      	beq.n	4922 <CC_PalTrngParamGet+0xe6>
    48e8:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    48ec:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    48f0:	6142      	str	r2, [r0, #20]
    48f2:	f8d3 1c08 	ldr.w	r1, [r3, #3080]	; 0xc08
    48f6:	4a14      	ldr	r2, [pc, #80]	; (4948 <CC_PalTrngParamGet+0x10c>)
    48f8:	4291      	cmp	r1, r2
    48fa:	d00d      	beq.n	4918 <CC_PalTrngParamGet+0xdc>
    48fc:	f8d3 2c08 	ldr.w	r2, [r3, #3080]	; 0xc08
    4900:	3201      	adds	r2, #1
    4902:	d009      	beq.n	4918 <CC_PalTrngParamGet+0xdc>
    4904:	f8d3 3c08 	ldr.w	r3, [r3, #3080]	; 0xc08
    4908:	6183      	str	r3, [r0, #24]
    490a:	2000      	movs	r0, #0
    490c:	4770      	bx	lr
    490e:	2001      	movs	r0, #1
    4910:	4770      	bx	lr
    4912:	f640 02fc 	movw	r2, #2300	; 0x8fc
    4916:	e7a5      	b.n	4864 <CC_PalTrngParamGet+0x28>
    4918:	f240 3337 	movw	r3, #823	; 0x337
    491c:	6183      	str	r3, [r0, #24]
    491e:	2000      	movs	r0, #0
    4920:	4770      	bx	lr
    4922:	2251      	movs	r2, #81	; 0x51
    4924:	e7e2      	b.n	48ec <CC_PalTrngParamGet+0xb0>
    4926:	2290      	movs	r2, #144	; 0x90
    4928:	e7d3      	b.n	48d2 <CC_PalTrngParamGet+0x96>
    492a:	f642 1204 	movw	r2, #10500	; 0x2904
    492e:	e7c3      	b.n	48b8 <CC_PalTrngParamGet+0x7c>
    4930:	f640 62d8 	movw	r2, #3800	; 0xed8
    4934:	e7b2      	b.n	489c <CC_PalTrngParamGet+0x60>
    4936:	f242 02d0 	movw	r2, #8400	; 0x20d0
    493a:	e7a1      	b.n	4880 <CC_PalTrngParamGet+0x44>
    493c:	fffff8fc 	.word	0xfffff8fc
    4940:	ffff20d0 	.word	0xffff20d0
    4944:	ffff2904 	.word	0xffff2904
    4948:	fffff337 	.word	0xfffff337

0000494c <startTrngHW>:
    494c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4950:	2800      	cmp	r0, #0
    4952:	d077      	beq.n	4a44 <startTrngHW+0xf8>
    4954:	460c      	mov	r4, r1
    4956:	2900      	cmp	r1, #0
    4958:	d074      	beq.n	4a44 <startTrngHW+0xf8>
    495a:	461d      	mov	r5, r3
    495c:	2b00      	cmp	r3, #0
    495e:	d071      	beq.n	4a44 <startTrngHW+0xf8>
    4960:	4606      	mov	r6, r0
    4962:	b11a      	cbz	r2, 496c <startTrngHW+0x20>
    4964:	2201      	movs	r2, #1
    4966:	2300      	movs	r3, #0
    4968:	602a      	str	r2, [r5, #0]
    496a:	6003      	str	r3, [r0, #0]
    496c:	682b      	ldr	r3, [r5, #0]
    496e:	2b00      	cmp	r3, #0
    4970:	d064      	beq.n	4a3c <startTrngHW+0xf0>
    4972:	4629      	mov	r1, r5
    4974:	4620      	mov	r0, r4
    4976:	f000 fb15 	bl	4fa4 <LLF_RND_GetFastestRosc>
    497a:	4607      	mov	r7, r0
    497c:	2800      	cmp	r0, #0
    497e:	d15e      	bne.n	4a3e <startTrngHW+0xf2>
    4980:	4621      	mov	r1, r4
    4982:	6828      	ldr	r0, [r5, #0]
    4984:	f000 faf0 	bl	4f68 <LLF_RND_GetRoscSampleCnt>
    4988:	4607      	mov	r7, r0
    498a:	2800      	cmp	r0, #0
    498c:	d157      	bne.n	4a3e <startTrngHW+0xf2>
    498e:	682b      	ldr	r3, [r5, #0]
    4990:	2b08      	cmp	r3, #8
    4992:	d066      	beq.n	4a62 <startTrngHW+0x116>
    4994:	2b04      	cmp	r3, #4
    4996:	d067      	beq.n	4a68 <startTrngHW+0x11c>
    4998:	f1a3 0802 	sub.w	r8, r3, #2
    499c:	fab8 f888 	clz	r8, r8
    49a0:	ea4f 1858 	mov.w	r8, r8, lsr #5
    49a4:	2301      	movs	r3, #1
    49a6:	469c      	mov	ip, r3
    49a8:	4a31      	ldr	r2, [pc, #196]	; (4a70 <startTrngHW+0x124>)
    49aa:	4932      	ldr	r1, [pc, #200]	; (4a74 <startTrngHW+0x128>)
    49ac:	6013      	str	r3, [r2, #0]
    49ae:	4610      	mov	r0, r2
    49b0:	600b      	str	r3, [r1, #0]
    49b2:	3a94      	subs	r2, #148	; 0x94
    49b4:	f8c0 c000 	str.w	ip, [r0]
    49b8:	6a63      	ldr	r3, [r4, #36]	; 0x24
    49ba:	6013      	str	r3, [r2, #0]
    49bc:	6811      	ldr	r1, [r2, #0]
    49be:	428b      	cmp	r3, r1
    49c0:	d1f8      	bne.n	49b4 <startTrngHW+0x68>
    49c2:	f04f 0900 	mov.w	r9, #0
    49c6:	4b2c      	ldr	r3, [pc, #176]	; (4a78 <startTrngHW+0x12c>)
    49c8:	f04f 30ff 	mov.w	r0, #4294967295
    49cc:	f8c3 9000 	str.w	r9, [r3]
    49d0:	f7ff fcca 	bl	4368 <CC_HalClearInterruptBit>
    49d4:	4b29      	ldr	r3, [pc, #164]	; (4a7c <startTrngHW+0x130>)
    49d6:	4a2a      	ldr	r2, [pc, #168]	; (4a80 <startTrngHW+0x134>)
    49d8:	4648      	mov	r0, r9
    49da:	601a      	str	r2, [r3, #0]
    49dc:	f7ff fcd2 	bl	4384 <CC_HalMaskInterrupt>
    49e0:	4a28      	ldr	r2, [pc, #160]	; (4a84 <startTrngHW+0x138>)
    49e2:	4b29      	ldr	r3, [pc, #164]	; (4a88 <startTrngHW+0x13c>)
    49e4:	f8c2 8000 	str.w	r8, [r2]
    49e8:	6818      	ldr	r0, [r3, #0]
    49ea:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
    49ee:	f7ff fcc9 	bl	4384 <CC_HalMaskInterrupt>
    49f2:	220a      	movs	r2, #10
    49f4:	4b25      	ldr	r3, [pc, #148]	; (4a8c <startTrngHW+0x140>)
    49f6:	601a      	str	r2, [r3, #0]
    49f8:	9a08      	ldr	r2, [sp, #32]
    49fa:	6923      	ldr	r3, [r4, #16]
    49fc:	2a01      	cmp	r2, #1
    49fe:	6a61      	ldr	r1, [r4, #36]	; 0x24
    4a00:	d024      	beq.n	4a4c <startTrngHW+0x100>
    4a02:	4a23      	ldr	r2, [pc, #140]	; (4a90 <startTrngHW+0x144>)
    4a04:	fba2 2303 	umull	r2, r3, r2, r3
    4a08:	091b      	lsrs	r3, r3, #4
    4a0a:	2201      	movs	r2, #1
    4a0c:	fb03 f301 	mul.w	r3, r3, r1
    4a10:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4a14:	491f      	ldr	r1, [pc, #124]	; (4a94 <startTrngHW+0x148>)
    4a16:	03db      	lsls	r3, r3, #15
    4a18:	099b      	lsrs	r3, r3, #6
    4a1a:	600b      	str	r3, [r1, #0]
    4a1c:	4b16      	ldr	r3, [pc, #88]	; (4a78 <startTrngHW+0x12c>)
    4a1e:	4638      	mov	r0, r7
    4a20:	601a      	str	r2, [r3, #0]
    4a22:	6833      	ldr	r3, [r6, #0]
    4a24:	682a      	ldr	r2, [r5, #0]
    4a26:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    4a2a:	ea43 6302 	orr.w	r3, r3, r2, lsl #24
    4a2e:	6033      	str	r3, [r6, #0]
    4a30:	682a      	ldr	r2, [r5, #0]
    4a32:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
    4a36:	6033      	str	r3, [r6, #0]
    4a38:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4a3c:	4f16      	ldr	r7, [pc, #88]	; (4a98 <startTrngHW+0x14c>)
    4a3e:	4638      	mov	r0, r7
    4a40:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4a44:	4f15      	ldr	r7, [pc, #84]	; (4a9c <startTrngHW+0x150>)
    4a46:	4638      	mov	r0, r7
    4a48:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4a4c:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    4a50:	f8d3 2c0c 	ldr.w	r2, [r3, #3084]	; 0xc0c
    4a54:	3201      	adds	r2, #1
    4a56:	d002      	beq.n	4a5e <startTrngHW+0x112>
    4a58:	f8d3 3c0c 	ldr.w	r3, [r3, #3084]	; 0xc0c
    4a5c:	e7d1      	b.n	4a02 <startTrngHW+0xb6>
    4a5e:	2316      	movs	r3, #22
    4a60:	e7d3      	b.n	4a0a <startTrngHW+0xbe>
    4a62:	f04f 0803 	mov.w	r8, #3
    4a66:	e79d      	b.n	49a4 <startTrngHW+0x58>
    4a68:	f04f 0802 	mov.w	r8, #2
    4a6c:	e79a      	b.n	49a4 <startTrngHW+0x58>
    4a6e:	bf00      	nop
    4a70:	508411c4 	.word	0x508411c4
    4a74:	50841140 	.word	0x50841140
    4a78:	5084112c 	.word	0x5084112c
    4a7c:	50841100 	.word	0x50841100
    4a80:	0ffffffe 	.word	0x0ffffffe
    4a84:	5084110c 	.word	0x5084110c
    4a88:	50841a04 	.word	0x50841a04
    4a8c:	50841138 	.word	0x50841138
    4a90:	aaaaaaab 	.word	0xaaaaaaab
    4a94:	508411d8 	.word	0x508411d8
    4a98:	00f10c31 	.word	0x00f10c31
    4a9c:	00f10c35 	.word	0x00f10c35

00004aa0 <LLF_RND_RepetitionCounterTest.part.0>:
    4aa0:	b4f0      	push	{r4, r5, r6, r7}
    4aa2:	2400      	movs	r4, #0
    4aa4:	00c9      	lsls	r1, r1, #3
    4aa6:	4626      	mov	r6, r4
    4aa8:	4627      	mov	r7, r4
    4aaa:	f101 3cff 	add.w	ip, r1, #4294967295
    4aae:	e006      	b.n	4abe <LLF_RND_RepetitionCounterTest.part.0+0x1e>
    4ab0:	429f      	cmp	r7, r3
    4ab2:	d015      	beq.n	4ae0 <LLF_RND_RepetitionCounterTest.part.0+0x40>
    4ab4:	2601      	movs	r6, #1
    4ab6:	4565      	cmp	r5, ip
    4ab8:	d818      	bhi.n	4aec <LLF_RND_RepetitionCounterTest.part.0+0x4c>
    4aba:	462c      	mov	r4, r5
    4abc:	461f      	mov	r7, r3
    4abe:	0963      	lsrs	r3, r4, #5
    4ac0:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    4ac4:	f004 011f 	and.w	r1, r4, #31
    4ac8:	40cb      	lsrs	r3, r1
    4aca:	291f      	cmp	r1, #31
    4acc:	f104 0501 	add.w	r5, r4, #1
    4ad0:	bf18      	it	ne
    4ad2:	f003 0301 	andne.w	r3, r3, #1
    4ad6:	2c00      	cmp	r4, #0
    4ad8:	d1ea      	bne.n	4ab0 <LLF_RND_RepetitionCounterTest.part.0+0x10>
    4ada:	2601      	movs	r6, #1
    4adc:	4635      	mov	r5, r6
    4ade:	e7ec      	b.n	4aba <LLF_RND_RepetitionCounterTest.part.0+0x1a>
    4ae0:	3601      	adds	r6, #1
    4ae2:	4296      	cmp	r6, r2
    4ae4:	d1e7      	bne.n	4ab6 <LLF_RND_RepetitionCounterTest.part.0+0x16>
    4ae6:	4803      	ldr	r0, [pc, #12]	; (4af4 <LLF_RND_RepetitionCounterTest.part.0+0x54>)
    4ae8:	bcf0      	pop	{r4, r5, r6, r7}
    4aea:	4770      	bx	lr
    4aec:	2000      	movs	r0, #0
    4aee:	bcf0      	pop	{r4, r5, r6, r7}
    4af0:	4770      	bx	lr
    4af2:	bf00      	nop
    4af4:	00f10c36 	.word	0x00f10c36

00004af8 <LLF_RND_AdaptiveProportionTest>:
    4af8:	2800      	cmp	r0, #0
    4afa:	d05f      	beq.n	4bbc <LLF_RND_AdaptiveProportionTest+0xc4>
    4afc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4b00:	1e4c      	subs	r4, r1, #1
    4b02:	f5b4 7f04 	cmp.w	r4, #528	; 0x210
    4b06:	d226      	bcs.n	4b56 <LLF_RND_AdaptiveProportionTest+0x5e>
    4b08:	b32b      	cbz	r3, 4b56 <LLF_RND_AdaptiveProportionTest+0x5e>
    4b0a:	b322      	cbz	r2, 4b56 <LLF_RND_AdaptiveProportionTest+0x5e>
    4b0c:	00cc      	lsls	r4, r1, #3
    4b0e:	2b01      	cmp	r3, #1
    4b10:	f104 3eff 	add.w	lr, r4, #4294967295
    4b14:	d02f      	beq.n	4b76 <LLF_RND_AdaptiveProportionTest+0x7e>
    4b16:	2100      	movs	r1, #0
    4b18:	468c      	mov	ip, r1
    4b1a:	460f      	mov	r7, r1
    4b1c:	460d      	mov	r5, r1
    4b1e:	f103 38ff 	add.w	r8, r3, #4294967295
    4b22:	094c      	lsrs	r4, r1, #5
    4b24:	f850 4024 	ldr.w	r4, [r0, r4, lsl #2]
    4b28:	f001 061f 	and.w	r6, r1, #31
    4b2c:	40f4      	lsrs	r4, r6
    4b2e:	2e1f      	cmp	r6, #31
    4b30:	bf18      	it	ne
    4b32:	f004 0401 	andne.w	r4, r4, #1
    4b36:	b921      	cbnz	r1, 4b42 <LLF_RND_AdaptiveProportionTest+0x4a>
    4b38:	2501      	movs	r5, #1
    4b3a:	46ac      	mov	ip, r5
    4b3c:	4629      	mov	r1, r5
    4b3e:	4627      	mov	r7, r4
    4b40:	e7ef      	b.n	4b22 <LLF_RND_AdaptiveProportionTest+0x2a>
    4b42:	42ab      	cmp	r3, r5
    4b44:	d013      	beq.n	4b6e <LLF_RND_AdaptiveProportionTest+0x76>
    4b46:	42a7      	cmp	r7, r4
    4b48:	d101      	bne.n	4b4e <LLF_RND_AdaptiveProportionTest+0x56>
    4b4a:	f10c 0c01 	add.w	ip, ip, #1
    4b4e:	4545      	cmp	r5, r8
    4b50:	d104      	bne.n	4b5c <LLF_RND_AdaptiveProportionTest+0x64>
    4b52:	4562      	cmp	r2, ip
    4b54:	d202      	bcs.n	4b5c <LLF_RND_AdaptiveProportionTest+0x64>
    4b56:	481a      	ldr	r0, [pc, #104]	; (4bc0 <LLF_RND_AdaptiveProportionTest+0xc8>)
    4b58:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4b5c:	463c      	mov	r4, r7
    4b5e:	3101      	adds	r1, #1
    4b60:	458e      	cmp	lr, r1
    4b62:	f105 0501 	add.w	r5, r5, #1
    4b66:	d2ea      	bcs.n	4b3e <LLF_RND_AdaptiveProportionTest+0x46>
    4b68:	2000      	movs	r0, #0
    4b6a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4b6e:	2500      	movs	r5, #0
    4b70:	f04f 0c01 	mov.w	ip, #1
    4b74:	e7f3      	b.n	4b5e <LLF_RND_AdaptiveProportionTest+0x66>
    4b76:	2600      	movs	r6, #0
    4b78:	46b4      	mov	ip, r6
    4b7a:	4637      	mov	r7, r6
    4b7c:	4631      	mov	r1, r6
    4b7e:	094b      	lsrs	r3, r1, #5
    4b80:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    4b84:	f001 051f 	and.w	r5, r1, #31
    4b88:	40eb      	lsrs	r3, r5
    4b8a:	2d1f      	cmp	r5, #31
    4b8c:	bf18      	it	ne
    4b8e:	f003 0301 	andne.w	r3, r3, #1
    4b92:	b139      	cbz	r1, 4ba4 <LLF_RND_AdaptiveProportionTest+0xac>
    4b94:	b95f      	cbnz	r7, 4bae <LLF_RND_AdaptiveProportionTest+0xb6>
    4b96:	459c      	cmp	ip, r3
    4b98:	d001      	beq.n	4b9e <LLF_RND_AdaptiveProportionTest+0xa6>
    4b9a:	4663      	mov	r3, ip
    4b9c:	e008      	b.n	4bb0 <LLF_RND_AdaptiveProportionTest+0xb8>
    4b9e:	4663      	mov	r3, ip
    4ba0:	3601      	adds	r6, #1
    4ba2:	e005      	b.n	4bb0 <LLF_RND_AdaptiveProportionTest+0xb8>
    4ba4:	2601      	movs	r6, #1
    4ba6:	4631      	mov	r1, r6
    4ba8:	469c      	mov	ip, r3
    4baa:	2701      	movs	r7, #1
    4bac:	e7e7      	b.n	4b7e <LLF_RND_AdaptiveProportionTest+0x86>
    4bae:	463e      	mov	r6, r7
    4bb0:	42b2      	cmp	r2, r6
    4bb2:	d3d0      	bcc.n	4b56 <LLF_RND_AdaptiveProportionTest+0x5e>
    4bb4:	3101      	adds	r1, #1
    4bb6:	42a1      	cmp	r1, r4
    4bb8:	d1f6      	bne.n	4ba8 <LLF_RND_AdaptiveProportionTest+0xb0>
    4bba:	e7d5      	b.n	4b68 <LLF_RND_AdaptiveProportionTest+0x70>
    4bbc:	4800      	ldr	r0, [pc, #0]	; (4bc0 <LLF_RND_AdaptiveProportionTest+0xc8>)
    4bbe:	4770      	bx	lr
    4bc0:	00f10c37 	.word	0x00f10c37

00004bc4 <getTrngSource>:
    4bc4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4bc8:	b08d      	sub	sp, #52	; 0x34
    4bca:	9e18      	ldr	r6, [sp, #96]	; 0x60
    4bcc:	4607      	mov	r7, r0
    4bce:	460c      	mov	r4, r1
    4bd0:	9d17      	ldr	r5, [sp, #92]	; 0x5c
    4bd2:	2e00      	cmp	r6, #0
    4bd4:	d14c      	bne.n	4c70 <getTrngSource+0xac>
    4bd6:	f8d1 b010 	ldr.w	fp, [r1, #16]
    4bda:	2100      	movs	r1, #0
    4bdc:	601d      	str	r5, [r3, #0]
    4bde:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4be0:	6019      	str	r1, [r3, #0]
    4be2:	2a00      	cmp	r2, #0
    4be4:	f000 811e 	beq.w	4e24 <getTrngSource+0x260>
    4be8:	4a9a      	ldr	r2, [pc, #616]	; (4e54 <getTrngSource+0x290>)
    4bea:	4b9b      	ldr	r3, [pc, #620]	; (4e58 <getTrngSource+0x294>)
    4bec:	6811      	ldr	r1, [r2, #0]
    4bee:	6a62      	ldr	r2, [r4, #36]	; 0x24
    4bf0:	681b      	ldr	r3, [r3, #0]
    4bf2:	429a      	cmp	r2, r3
    4bf4:	d147      	bne.n	4c86 <getTrngSource+0xc2>
    4bf6:	290a      	cmp	r1, #10
    4bf8:	d145      	bne.n	4c86 <getTrngSource+0xc2>
    4bfa:	78fb      	ldrb	r3, [r7, #3]
    4bfc:	9304      	str	r3, [sp, #16]
    4bfe:	2304      	movs	r3, #4
    4c00:	46b8      	mov	r8, r7
    4c02:	9302      	str	r3, [sp, #8]
    4c04:	4b95      	ldr	r3, [pc, #596]	; (4e5c <getTrngSource+0x298>)
    4c06:	fba3 230b 	umull	r2, r3, r3, fp
    4c0a:	ea4f 0a93 	mov.w	sl, r3, lsr #2
    4c0e:	eb0a 034a 	add.w	r3, sl, sl, lsl #1
    4c12:	f105 0208 	add.w	r2, r5, #8
    4c16:	9203      	str	r2, [sp, #12]
    4c18:	ebab 0a43 	sub.w	sl, fp, r3, lsl #1
    4c1c:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4c1e:	f8c3 b000 	str.w	fp, [r3]
    4c22:	f1bb 0f00 	cmp.w	fp, #0
    4c26:	f000 80c3 	beq.w	4db0 <getTrngSource+0x1ec>
    4c2a:	465d      	mov	r5, fp
    4c2c:	f04f 0900 	mov.w	r9, #0
    4c30:	9e03      	ldr	r6, [sp, #12]
    4c32:	f000 f9c7 	bl	4fc4 <LLF_RND_TurnOffTrng>
    4c36:	2300      	movs	r3, #0
    4c38:	9305      	str	r3, [sp, #20]
    4c3a:	f1b8 0f00 	cmp.w	r8, #0
    4c3e:	f000 80e5 	beq.w	4e0c <getTrngSource+0x248>
    4c42:	2c00      	cmp	r4, #0
    4c44:	f000 80e2 	beq.w	4e0c <getTrngSource+0x248>
    4c48:	9b04      	ldr	r3, [sp, #16]
    4c4a:	2b00      	cmp	r3, #0
    4c4c:	f000 80dc 	beq.w	4e08 <getTrngSource+0x244>
    4c50:	4620      	mov	r0, r4
    4c52:	a904      	add	r1, sp, #16
    4c54:	f000 f9a6 	bl	4fa4 <LLF_RND_GetFastestRosc>
    4c58:	b1b8      	cbz	r0, 4c8a <getTrngSource+0xc6>
    4c5a:	4b81      	ldr	r3, [pc, #516]	; (4e60 <getTrngSource+0x29c>)
    4c5c:	4298      	cmp	r0, r3
    4c5e:	f040 80a7 	bne.w	4db0 <getTrngSource+0x1ec>
    4c62:	9002      	str	r0, [sp, #8]
    4c64:	f000 f9ae 	bl	4fc4 <LLF_RND_TurnOffTrng>
    4c68:	9802      	ldr	r0, [sp, #8]
    4c6a:	b00d      	add	sp, #52	; 0x34
    4c6c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4c70:	f44f 017f 	mov.w	r1, #16711680	; 0xff0000
    4c74:	f8d1 0c0c 	ldr.w	r0, [r1, #3084]	; 0xc0c
    4c78:	3001      	adds	r0, #1
    4c7a:	bf0c      	ite	eq
    4c7c:	f44f 7b04 	moveq.w	fp, #528	; 0x210
    4c80:	f8d1 bc0c 	ldrne.w	fp, [r1, #3084]	; 0xc0c
    4c84:	e7a9      	b.n	4bda <getTrngSource+0x16>
    4c86:	4877      	ldr	r0, [pc, #476]	; (4e64 <getTrngSource+0x2a0>)
    4c88:	e7eb      	b.n	4c62 <getTrngSource+0x9e>
    4c8a:	4621      	mov	r1, r4
    4c8c:	9804      	ldr	r0, [sp, #16]
    4c8e:	f000 f96b 	bl	4f68 <LLF_RND_GetRoscSampleCnt>
    4c92:	2800      	cmp	r0, #0
    4c94:	d1e1      	bne.n	4c5a <getTrngSource+0x96>
    4c96:	9f04      	ldr	r7, [sp, #16]
    4c98:	2f08      	cmp	r7, #8
    4c9a:	f000 80b9 	beq.w	4e10 <getTrngSource+0x24c>
    4c9e:	2f04      	cmp	r7, #4
    4ca0:	f000 80b8 	beq.w	4e14 <getTrngSource+0x250>
    4ca4:	f1a7 0702 	sub.w	r7, r7, #2
    4ca8:	fab7 f787 	clz	r7, r7
    4cac:	097f      	lsrs	r7, r7, #5
    4cae:	2301      	movs	r3, #1
    4cb0:	4619      	mov	r1, r3
    4cb2:	486d      	ldr	r0, [pc, #436]	; (4e68 <getTrngSource+0x2a4>)
    4cb4:	6003      	str	r3, [r0, #0]
    4cb6:	f840 3c84 	str.w	r3, [r0, #-132]
    4cba:	4b6b      	ldr	r3, [pc, #428]	; (4e68 <getTrngSource+0x2a4>)
    4cbc:	4866      	ldr	r0, [pc, #408]	; (4e58 <getTrngSource+0x294>)
    4cbe:	6019      	str	r1, [r3, #0]
    4cc0:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4cc2:	6003      	str	r3, [r0, #0]
    4cc4:	6800      	ldr	r0, [r0, #0]
    4cc6:	4283      	cmp	r3, r0
    4cc8:	d1f7      	bne.n	4cba <getTrngSource+0xf6>
    4cca:	2300      	movs	r3, #0
    4ccc:	4a67      	ldr	r2, [pc, #412]	; (4e6c <getTrngSource+0x2a8>)
    4cce:	f04f 30ff 	mov.w	r0, #4294967295
    4cd2:	6013      	str	r3, [r2, #0]
    4cd4:	f7ff fb48 	bl	4368 <CC_HalClearInterruptBit>
    4cd8:	2300      	movs	r3, #0
    4cda:	4965      	ldr	r1, [pc, #404]	; (4e70 <getTrngSource+0x2ac>)
    4cdc:	4618      	mov	r0, r3
    4cde:	4b65      	ldr	r3, [pc, #404]	; (4e74 <getTrngSource+0x2b0>)
    4ce0:	6019      	str	r1, [r3, #0]
    4ce2:	f7ff fb4f 	bl	4384 <CC_HalMaskInterrupt>
    4ce6:	4964      	ldr	r1, [pc, #400]	; (4e78 <getTrngSource+0x2b4>)
    4ce8:	4b64      	ldr	r3, [pc, #400]	; (4e7c <getTrngSource+0x2b8>)
    4cea:	600f      	str	r7, [r1, #0]
    4cec:	6818      	ldr	r0, [r3, #0]
    4cee:	4f5b      	ldr	r7, [pc, #364]	; (4e5c <getTrngSource+0x298>)
    4cf0:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
    4cf4:	f7ff fb46 	bl	4384 <CC_HalMaskInterrupt>
    4cf8:	210a      	movs	r1, #10
    4cfa:	2201      	movs	r2, #1
    4cfc:	4b55      	ldr	r3, [pc, #340]	; (4e54 <getTrngSource+0x290>)
    4cfe:	4860      	ldr	r0, [pc, #384]	; (4e80 <getTrngSource+0x2bc>)
    4d00:	6019      	str	r1, [r3, #0]
    4d02:	6921      	ldr	r1, [r4, #16]
    4d04:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4d06:	fba7 c101 	umull	ip, r1, r7, r1
    4d0a:	0909      	lsrs	r1, r1, #4
    4d0c:	fb03 f301 	mul.w	r3, r3, r1
    4d10:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4d14:	03db      	lsls	r3, r3, #15
    4d16:	099b      	lsrs	r3, r3, #6
    4d18:	6003      	str	r3, [r0, #0]
    4d1a:	4b54      	ldr	r3, [pc, #336]	; (4e6c <getTrngSource+0x2a8>)
    4d1c:	a805      	add	r0, sp, #20
    4d1e:	601a      	str	r2, [r3, #0]
    4d20:	9904      	ldr	r1, [sp, #16]
    4d22:	f8d8 2000 	ldr.w	r2, [r8]
    4d26:	020b      	lsls	r3, r1, #8
    4d28:	ea43 6301 	orr.w	r3, r3, r1, lsl #24
    4d2c:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    4d30:	4313      	orrs	r3, r2
    4d32:	f8c8 3000 	str.w	r3, [r8]
    4d36:	f000 f907 	bl	4f48 <LLF_RND_WaitRngInterrupt>
    4d3a:	2800      	cmp	r0, #0
    4d3c:	d18d      	bne.n	4c5a <getTrngSource+0x96>
    4d3e:	4b51      	ldr	r3, [pc, #324]	; (4e84 <getTrngSource+0x2c0>)
    4d40:	fba7 2705 	umull	r2, r7, r7, r5
    4d44:	681a      	ldr	r2, [r3, #0]
    4d46:	3314      	adds	r3, #20
    4d48:	9206      	str	r2, [sp, #24]
    4d4a:	f853 2c10 	ldr.w	r2, [r3, #-16]
    4d4e:	ebb9 0f97 	cmp.w	r9, r7, lsr #2
    4d52:	9207      	str	r2, [sp, #28]
    4d54:	f853 2c0c 	ldr.w	r2, [r3, #-12]
    4d58:	9208      	str	r2, [sp, #32]
    4d5a:	f853 2c08 	ldr.w	r2, [r3, #-8]
    4d5e:	9209      	str	r2, [sp, #36]	; 0x24
    4d60:	f853 2c04 	ldr.w	r2, [r3, #-4]
    4d64:	920a      	str	r2, [sp, #40]	; 0x28
    4d66:	681b      	ldr	r3, [r3, #0]
    4d68:	930b      	str	r3, [sp, #44]	; 0x2c
    4d6a:	d102      	bne.n	4d72 <getTrngSource+0x1ae>
    4d6c:	f1ba 0f00 	cmp.w	sl, #0
    4d70:	d141      	bne.n	4df6 <getTrngSource+0x232>
    4d72:	2218      	movs	r2, #24
    4d74:	4630      	mov	r0, r6
    4d76:	eb0d 0102 	add.w	r1, sp, r2
    4d7a:	f7ff fa19 	bl	41b0 <CC_PalMemCopyPlat>
    4d7e:	3d18      	subs	r5, #24
    4d80:	3618      	adds	r6, #24
    4d82:	f109 0901 	add.w	r9, r9, #1
    4d86:	2d00      	cmp	r5, #0
    4d88:	f47f af53 	bne.w	4c32 <getTrngSource+0x6e>
    4d8c:	f5bb 7f04 	cmp.w	fp, #528	; 0x210
    4d90:	d85d      	bhi.n	4e4e <getTrngSource+0x28a>
    4d92:	9d03      	ldr	r5, [sp, #12]
    4d94:	4659      	mov	r1, fp
    4d96:	4628      	mov	r0, r5
    4d98:	6962      	ldr	r2, [r4, #20]
    4d9a:	f7ff fe81 	bl	4aa0 <LLF_RND_RepetitionCounterTest.part.0>
    4d9e:	2800      	cmp	r0, #0
    4da0:	d04b      	beq.n	4e3a <getTrngSource+0x276>
    4da2:	2300      	movs	r3, #0
    4da4:	9a16      	ldr	r2, [sp, #88]	; 0x58
    4da6:	6013      	str	r3, [r2, #0]
    4da8:	4b2d      	ldr	r3, [pc, #180]	; (4e60 <getTrngSource+0x29c>)
    4daa:	4298      	cmp	r0, r3
    4dac:	f43f af59 	beq.w	4c62 <getTrngSource+0x9e>
    4db0:	9d04      	ldr	r5, [sp, #16]
    4db2:	2d08      	cmp	r5, #8
    4db4:	d034      	beq.n	4e20 <getTrngSource+0x25c>
    4db6:	2200      	movs	r2, #0
    4db8:	ab04      	add	r3, sp, #16
    4dba:	4621      	mov	r1, r4
    4dbc:	4640      	mov	r0, r8
    4dbe:	006d      	lsls	r5, r5, #1
    4dc0:	9200      	str	r2, [sp, #0]
    4dc2:	9504      	str	r5, [sp, #16]
    4dc4:	f7ff fdc2 	bl	494c <startTrngHW>
    4dc8:	4b2f      	ldr	r3, [pc, #188]	; (4e88 <getTrngSource+0x2c4>)
    4dca:	4298      	cmp	r0, r3
    4dcc:	d024      	beq.n	4e18 <getTrngSource+0x254>
    4dce:	2800      	cmp	r0, #0
    4dd0:	f47f af47 	bne.w	4c62 <getTrngSource+0x9e>
    4dd4:	f8d8 2000 	ldr.w	r2, [r8]
    4dd8:	0a13      	lsrs	r3, r2, #8
    4dda:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
    4dde:	4313      	orrs	r3, r2
    4de0:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    4de4:	f8c8 3000 	str.w	r3, [r8]
    4de8:	9b02      	ldr	r3, [sp, #8]
    4dea:	3b01      	subs	r3, #1
    4dec:	9302      	str	r3, [sp, #8]
    4dee:	f47f af15 	bne.w	4c1c <getTrngSource+0x58>
    4df2:	2000      	movs	r0, #0
    4df4:	e735      	b.n	4c62 <getTrngSource+0x9e>
    4df6:	4630      	mov	r0, r6
    4df8:	4652      	mov	r2, sl
    4dfa:	a906      	add	r1, sp, #24
    4dfc:	f7ff f9d8 	bl	41b0 <CC_PalMemCopyPlat>
    4e00:	eba5 050a 	sub.w	r5, r5, sl
    4e04:	4456      	add	r6, sl
    4e06:	e7bc      	b.n	4d82 <getTrngSource+0x1be>
    4e08:	481f      	ldr	r0, [pc, #124]	; (4e88 <getTrngSource+0x2c4>)
    4e0a:	e726      	b.n	4c5a <getTrngSource+0x96>
    4e0c:	481f      	ldr	r0, [pc, #124]	; (4e8c <getTrngSource+0x2c8>)
    4e0e:	e724      	b.n	4c5a <getTrngSource+0x96>
    4e10:	2703      	movs	r7, #3
    4e12:	e74c      	b.n	4cae <getTrngSource+0xea>
    4e14:	2702      	movs	r7, #2
    4e16:	e74a      	b.n	4cae <getTrngSource+0xea>
    4e18:	6a23      	ldr	r3, [r4, #32]
    4e1a:	2b00      	cmp	r3, #0
    4e1c:	f43f af21 	beq.w	4c62 <getTrngSource+0x9e>
    4e20:	481b      	ldr	r0, [pc, #108]	; (4e90 <getTrngSource+0x2cc>)
    4e22:	e71e      	b.n	4c62 <getTrngSource+0x9e>
    4e24:	2201      	movs	r2, #1
    4e26:	4621      	mov	r1, r4
    4e28:	4638      	mov	r0, r7
    4e2a:	9600      	str	r6, [sp, #0]
    4e2c:	ab04      	add	r3, sp, #16
    4e2e:	f7ff fd8d 	bl	494c <startTrngHW>
    4e32:	2800      	cmp	r0, #0
    4e34:	f43f aee3 	beq.w	4bfe <getTrngSource+0x3a>
    4e38:	e713      	b.n	4c62 <getTrngSource+0x9e>
    4e3a:	f44f 6380 	mov.w	r3, #1024	; 0x400
    4e3e:	4659      	mov	r1, fp
    4e40:	4628      	mov	r0, r5
    4e42:	69a2      	ldr	r2, [r4, #24]
    4e44:	f7ff fe58 	bl	4af8 <LLF_RND_AdaptiveProportionTest>
    4e48:	2800      	cmp	r0, #0
    4e4a:	d1aa      	bne.n	4da2 <getTrngSource+0x1de>
    4e4c:	e7d1      	b.n	4df2 <getTrngSource+0x22e>
    4e4e:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4e50:	601d      	str	r5, [r3, #0]
    4e52:	e7ad      	b.n	4db0 <getTrngSource+0x1ec>
    4e54:	50841138 	.word	0x50841138
    4e58:	50841130 	.word	0x50841130
    4e5c:	aaaaaaab 	.word	0xaaaaaaab
    4e60:	00f10c02 	.word	0x00f10c02
    4e64:	00f10c30 	.word	0x00f10c30
    4e68:	508411c4 	.word	0x508411c4
    4e6c:	5084112c 	.word	0x5084112c
    4e70:	0ffffffe 	.word	0x0ffffffe
    4e74:	50841100 	.word	0x50841100
    4e78:	5084110c 	.word	0x5084110c
    4e7c:	50841a04 	.word	0x50841a04
    4e80:	508411d8 	.word	0x508411d8
    4e84:	50841114 	.word	0x50841114
    4e88:	00f10c31 	.word	0x00f10c31
    4e8c:	00f10c35 	.word	0x00f10c35
    4e90:	00f10c32 	.word	0x00f10c32

00004e94 <LLF_RND_GetTrngSource>:
    4e94:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4e98:	4e1f      	ldr	r6, [pc, #124]	; (4f18 <LLF_RND_GetTrngSource+0x84>)
    4e9a:	b084      	sub	sp, #16
    4e9c:	4604      	mov	r4, r0
    4e9e:	460d      	mov	r5, r1
    4ea0:	6830      	ldr	r0, [r6, #0]
    4ea2:	f04f 31ff 	mov.w	r1, #4294967295
    4ea6:	4690      	mov	r8, r2
    4ea8:	9f0c      	ldr	r7, [sp, #48]	; 0x30
    4eaa:	f7ff f9e7 	bl	427c <CC_PalMutexLock>
    4eae:	b9d8      	cbnz	r0, 4ee8 <LLF_RND_GetTrngSource+0x54>
    4eb0:	2000      	movs	r0, #0
    4eb2:	f7ff fa13 	bl	42dc <CC_PalPowerSaveModeSelect>
    4eb6:	b9f8      	cbnz	r0, 4ef8 <LLF_RND_GetTrngSource+0x64>
    4eb8:	2300      	movs	r3, #0
    4eba:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    4ebc:	4620      	mov	r0, r4
    4ebe:	9200      	str	r2, [sp, #0]
    4ec0:	9302      	str	r3, [sp, #8]
    4ec2:	4642      	mov	r2, r8
    4ec4:	4629      	mov	r1, r5
    4ec6:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    4ec8:	9701      	str	r7, [sp, #4]
    4eca:	f7ff fe7b 	bl	4bc4 <getTrngSource>
    4ece:	4604      	mov	r4, r0
    4ed0:	2001      	movs	r0, #1
    4ed2:	f7ff fa03 	bl	42dc <CC_PalPowerSaveModeSelect>
    4ed6:	b9d0      	cbnz	r0, 4f0e <LLF_RND_GetTrngSource+0x7a>
    4ed8:	6830      	ldr	r0, [r6, #0]
    4eda:	f7ff f9d7 	bl	428c <CC_PalMutexUnlock>
    4ede:	b978      	cbnz	r0, 4f00 <LLF_RND_GetTrngSource+0x6c>
    4ee0:	4620      	mov	r0, r4
    4ee2:	b004      	add	sp, #16
    4ee4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4ee8:	480c      	ldr	r0, [pc, #48]	; (4f1c <LLF_RND_GetTrngSource+0x88>)
    4eea:	f7ff fb5f 	bl	45ac <CC_PalAbort>
    4eee:	2000      	movs	r0, #0
    4ef0:	f7ff f9f4 	bl	42dc <CC_PalPowerSaveModeSelect>
    4ef4:	2800      	cmp	r0, #0
    4ef6:	d0df      	beq.n	4eb8 <LLF_RND_GetTrngSource+0x24>
    4ef8:	4809      	ldr	r0, [pc, #36]	; (4f20 <LLF_RND_GetTrngSource+0x8c>)
    4efa:	f7ff fb57 	bl	45ac <CC_PalAbort>
    4efe:	e7db      	b.n	4eb8 <LLF_RND_GetTrngSource+0x24>
    4f00:	4808      	ldr	r0, [pc, #32]	; (4f24 <LLF_RND_GetTrngSource+0x90>)
    4f02:	f7ff fb53 	bl	45ac <CC_PalAbort>
    4f06:	4620      	mov	r0, r4
    4f08:	b004      	add	sp, #16
    4f0a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4f0e:	4806      	ldr	r0, [pc, #24]	; (4f28 <LLF_RND_GetTrngSource+0x94>)
    4f10:	f7ff fb4c 	bl	45ac <CC_PalAbort>
    4f14:	e7e0      	b.n	4ed8 <LLF_RND_GetTrngSource+0x44>
    4f16:	bf00      	nop
    4f18:	20000064 	.word	0x20000064
    4f1c:	000060d4 	.word	0x000060d4
    4f20:	00006104 	.word	0x00006104
    4f24:	000060ec 	.word	0x000060ec
    4f28:	00006124 	.word	0x00006124

00004f2c <LLF_RND_RunTrngStartupTest>:
    4f2c:	b510      	push	{r4, lr}
    4f2e:	2401      	movs	r4, #1
    4f30:	b086      	sub	sp, #24
    4f32:	ab05      	add	r3, sp, #20
    4f34:	e9cd 2401 	strd	r2, r4, [sp, #4]
    4f38:	9300      	str	r3, [sp, #0]
    4f3a:	2200      	movs	r2, #0
    4f3c:	ab04      	add	r3, sp, #16
    4f3e:	f7ff fe41 	bl	4bc4 <getTrngSource>
    4f42:	b006      	add	sp, #24
    4f44:	bd10      	pop	{r4, pc}
    4f46:	bf00      	nop

00004f48 <LLF_RND_WaitRngInterrupt>:
    4f48:	4601      	mov	r1, r0
    4f4a:	b508      	push	{r3, lr}
    4f4c:	f44f 6080 	mov.w	r0, #1024	; 0x400
    4f50:	f7ff fa1e 	bl	4390 <CC_HalWaitInterruptRND>
    4f54:	2300      	movs	r3, #0
    4f56:	4902      	ldr	r1, [pc, #8]	; (4f60 <LLF_RND_WaitRngInterrupt+0x18>)
    4f58:	4a02      	ldr	r2, [pc, #8]	; (4f64 <LLF_RND_WaitRngInterrupt+0x1c>)
    4f5a:	600b      	str	r3, [r1, #0]
    4f5c:	6013      	str	r3, [r2, #0]
    4f5e:	bd08      	pop	{r3, pc}
    4f60:	508411c8 	.word	0x508411c8
    4f64:	5084112c 	.word	0x5084112c

00004f68 <LLF_RND_GetRoscSampleCnt>:
    4f68:	3801      	subs	r0, #1
    4f6a:	2807      	cmp	r0, #7
    4f6c:	d805      	bhi.n	4f7a <LLF_RND_GetRoscSampleCnt+0x12>
    4f6e:	e8df f000 	tbb	[pc, r0]
    4f72:	0e0a      	.short	0x0e0a
    4f74:	04041204 	.word	0x04041204
    4f78:	0604      	.short	0x0604
    4f7a:	4809      	ldr	r0, [pc, #36]	; (4fa0 <LLF_RND_GetRoscSampleCnt+0x38>)
    4f7c:	4770      	bx	lr
    4f7e:	68cb      	ldr	r3, [r1, #12]
    4f80:	2000      	movs	r0, #0
    4f82:	624b      	str	r3, [r1, #36]	; 0x24
    4f84:	4770      	bx	lr
    4f86:	680b      	ldr	r3, [r1, #0]
    4f88:	2000      	movs	r0, #0
    4f8a:	624b      	str	r3, [r1, #36]	; 0x24
    4f8c:	4770      	bx	lr
    4f8e:	684b      	ldr	r3, [r1, #4]
    4f90:	2000      	movs	r0, #0
    4f92:	624b      	str	r3, [r1, #36]	; 0x24
    4f94:	4770      	bx	lr
    4f96:	688b      	ldr	r3, [r1, #8]
    4f98:	2000      	movs	r0, #0
    4f9a:	624b      	str	r3, [r1, #36]	; 0x24
    4f9c:	4770      	bx	lr
    4f9e:	bf00      	nop
    4fa0:	00f10c31 	.word	0x00f10c31

00004fa4 <LLF_RND_GetFastestRosc>:
    4fa4:	680b      	ldr	r3, [r1, #0]
    4fa6:	e002      	b.n	4fae <LLF_RND_GetFastestRosc+0xa>
    4fa8:	2b08      	cmp	r3, #8
    4faa:	600b      	str	r3, [r1, #0]
    4fac:	d806      	bhi.n	4fbc <LLF_RND_GetFastestRosc+0x18>
    4fae:	6a02      	ldr	r2, [r0, #32]
    4fb0:	4213      	tst	r3, r2
    4fb2:	ea4f 0343 	mov.w	r3, r3, lsl #1
    4fb6:	d0f7      	beq.n	4fa8 <LLF_RND_GetFastestRosc+0x4>
    4fb8:	2000      	movs	r0, #0
    4fba:	4770      	bx	lr
    4fbc:	4800      	ldr	r0, [pc, #0]	; (4fc0 <LLF_RND_GetFastestRosc+0x1c>)
    4fbe:	4770      	bx	lr
    4fc0:	00f10c31 	.word	0x00f10c31

00004fc4 <LLF_RND_TurnOffTrng>:
    4fc4:	2300      	movs	r3, #0
    4fc6:	4904      	ldr	r1, [pc, #16]	; (4fd8 <LLF_RND_TurnOffTrng+0x14>)
    4fc8:	4a04      	ldr	r2, [pc, #16]	; (4fdc <LLF_RND_TurnOffTrng+0x18>)
    4fca:	600b      	str	r3, [r1, #0]
    4fcc:	f44f 6080 	mov.w	r0, #1024	; 0x400
    4fd0:	6013      	str	r3, [r2, #0]
    4fd2:	f7ff b9c9 	b.w	4368 <CC_HalClearInterruptBit>
    4fd6:	bf00      	nop
    4fd8:	5084112c 	.word	0x5084112c
    4fdc:	508411c4 	.word	0x508411c4

00004fe0 <main>:
 *  0 kB  |---------------------|
 */


void main(void)
{
    4fe0:	b508      	push	{r3, lr}
	spm_config();
    4fe2:	f7fc fda9 	bl	1b38 <spm_config>
	spm_jump();
}
    4fe6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	spm_jump();
    4fea:	f7fc bd3b 	b.w	1a64 <spm_jump>

00004fee <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    4fee:	b160      	cbz	r0, 500a <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    4ff0:	6843      	ldr	r3, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    4ff2:	f003 0303 	and.w	r3, r3, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    4ff6:	2b01      	cmp	r3, #1
    4ff8:	d003      	beq.n	5002 <sys_notify_validate+0x14>
    4ffa:	2b03      	cmp	r3, #3
    4ffc:	d105      	bne.n	500a <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    4ffe:	6803      	ldr	r3, [r0, #0]
    5000:	b11b      	cbz	r3, 500a <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5002:	2300      	movs	r3, #0
    5004:	6083      	str	r3, [r0, #8]
    5006:	4618      	mov	r0, r3
    5008:	4770      	bx	lr
		return -EINVAL;
    500a:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    500e:	4770      	bx	lr

00005010 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5010:	2200      	movs	r2, #0
    5012:	6843      	ldr	r3, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    5014:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    5016:	f003 0303 	and.w	r3, r3, #3
	switch (method) {
    501a:	2b03      	cmp	r3, #3
	sys_notify_generic_callback rv = 0;
    501c:	bf14      	ite	ne
    501e:	4613      	movne	r3, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5020:	6803      	ldreq	r3, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    5022:	6042      	str	r2, [r0, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5024:	4618      	mov	r0, r3
    5026:	4770      	bx	lr

00005028 <arch_printk_char_out>:
}
    5028:	2000      	movs	r0, #0
    502a:	4770      	bx	lr

0000502c <printk>:
 * @param fmt formatted string to output
 *
 * @return N/A
 */
void printk(const char *fmt, ...)
{
    502c:	b40f      	push	{r0, r1, r2, r3}
    502e:	b507      	push	{r0, r1, r2, lr}
    5030:	a904      	add	r1, sp, #16
    5032:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    5036:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    5038:	f7fb fab6 	bl	5a8 <vprintk>
	}
	va_end(ap);
}
    503c:	b003      	add	sp, #12
    503e:	f85d eb04 	ldr.w	lr, [sp], #4
    5042:	b004      	add	sp, #16
    5044:	4770      	bx	lr

00005046 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5046:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    5048:	f013 0307 	ands.w	r3, r3, #7
    504c:	d105      	bne.n	505a <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    504e:	6803      	ldr	r3, [r0, #0]
    5050:	2b00      	cmp	r3, #0
		evt = EVT_START;
    5052:	bf0c      	ite	eq
    5054:	2000      	moveq	r0, #0
    5056:	2003      	movne	r0, #3
    5058:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    505a:	2b02      	cmp	r3, #2
    505c:	d105      	bne.n	506a <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    505e:	8b43      	ldrh	r3, [r0, #26]
    5060:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    5062:	bf14      	ite	ne
    5064:	2000      	movne	r0, #0
    5066:	2004      	moveq	r0, #4
    5068:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    506a:	2b01      	cmp	r3, #1
    506c:	d105      	bne.n	507a <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    506e:	6803      	ldr	r3, [r0, #0]
    5070:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    5072:	bf0c      	ite	eq
    5074:	2000      	moveq	r0, #0
    5076:	2005      	movne	r0, #5
    5078:	4770      	bx	lr
	int evt = EVT_NOP;
    507a:	2000      	movs	r0, #0
}
    507c:	4770      	bx	lr

0000507e <notify_one>:
{
    507e:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5080:	460d      	mov	r5, r1
    5082:	4606      	mov	r6, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5084:	4619      	mov	r1, r3
    5086:	1d28      	adds	r0, r5, #4
{
    5088:	9201      	str	r2, [sp, #4]
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    508a:	9300      	str	r3, [sp, #0]
    508c:	f7ff ffc0 	bl	5010 <sys_notify_finalize>
	if (cb) {
    5090:	4604      	mov	r4, r0
    5092:	b140      	cbz	r0, 50a6 <notify_one+0x28>
		cb(mgr, cli, state, res);
    5094:	e9dd 3200 	ldrd	r3, r2, [sp]
    5098:	4629      	mov	r1, r5
    509a:	4630      	mov	r0, r6
    509c:	46a4      	mov	ip, r4
}
    509e:	b002      	add	sp, #8
    50a0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		cb(mgr, cli, state, res);
    50a4:	4760      	bx	ip
}
    50a6:	b002      	add	sp, #8
    50a8:	bd70      	pop	{r4, r5, r6, pc}

000050aa <transition_complete>:
{
    50aa:	b410      	push	{r4}
	__asm__ volatile(
    50ac:	f04f 0420 	mov.w	r4, #32
    50b0:	f3ef 8211 	mrs	r2, BASEPRI
    50b4:	f384 8811 	msr	BASEPRI, r4
    50b8:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    50bc:	6141      	str	r1, [r0, #20]
}
    50be:	f85d 4b04 	ldr.w	r4, [sp], #4
	process_event(mgr, EVT_COMPLETE, key);
    50c2:	2101      	movs	r1, #1
    50c4:	f7fb ba7e 	b.w	5c4 <process_event>

000050c8 <validate_args>:
{
    50c8:	b510      	push	{r4, lr}
    50ca:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    50cc:	b140      	cbz	r0, 50e0 <validate_args+0x18>
    50ce:	b139      	cbz	r1, 50e0 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    50d0:	1d08      	adds	r0, r1, #4
    50d2:	f7ff ff8c 	bl	4fee <sys_notify_validate>
	if ((rv == 0)
    50d6:	b928      	cbnz	r0, 50e4 <validate_args+0x1c>
	    && ((cli->notify.flags
    50d8:	68a3      	ldr	r3, [r4, #8]
    50da:	f033 0303 	bics.w	r3, r3, #3
    50de:	d001      	beq.n	50e4 <validate_args+0x1c>
		rv = -EINVAL;
    50e0:	f06f 0015 	mvn.w	r0, #21
}
    50e4:	bd10      	pop	{r4, pc}

000050e6 <onoff_manager_init>:
{
    50e6:	b538      	push	{r3, r4, r5, lr}
    50e8:	460c      	mov	r4, r1
	if ((mgr == NULL)
    50ea:	4605      	mov	r5, r0
    50ec:	b158      	cbz	r0, 5106 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    50ee:	b151      	cbz	r1, 5106 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    50f0:	680b      	ldr	r3, [r1, #0]
    50f2:	b143      	cbz	r3, 5106 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    50f4:	684b      	ldr	r3, [r1, #4]
    50f6:	b133      	cbz	r3, 5106 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    50f8:	221c      	movs	r2, #28
    50fa:	2100      	movs	r1, #0
    50fc:	f000 fb9a 	bl	5834 <memset>
	return 0;
    5100:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5102:	612c      	str	r4, [r5, #16]
}
    5104:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    5106:	f06f 0015 	mvn.w	r0, #21
    510a:	e7fb      	b.n	5104 <onoff_manager_init+0x1e>

0000510c <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    510c:	b570      	push	{r4, r5, r6, lr}
    510e:	4604      	mov	r4, r0
    5110:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5112:	f7ff ffd9 	bl	50c8 <validate_args>

	if (rv < 0) {
    5116:	1e05      	subs	r5, r0, #0
    5118:	db31      	blt.n	517e <onoff_request+0x72>
    511a:	f04f 0320 	mov.w	r3, #32
    511e:	f3ef 8111 	mrs	r1, BASEPRI
    5122:	f383 8811 	msr	BASEPRI, r3
    5126:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    512a:	f64f 75ff 	movw	r5, #65535	; 0xffff
    512e:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5130:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    5132:	42ab      	cmp	r3, r5
    5134:	f000 0207 	and.w	r2, r0, #7
    5138:	d02e      	beq.n	5198 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    513a:	2a02      	cmp	r2, #2
    513c:	d10e      	bne.n	515c <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    513e:	3301      	adds	r3, #1
    5140:	8363      	strh	r3, [r4, #26]
	rv = state;
    5142:	4615      	mov	r5, r2
		notify = true;
    5144:	2301      	movs	r3, #1
	__asm__ volatile(
    5146:	f381 8811 	msr	BASEPRI, r1
    514a:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    514e:	b1b3      	cbz	r3, 517e <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    5150:	2300      	movs	r3, #0
    5152:	4631      	mov	r1, r6
    5154:	4620      	mov	r0, r4
    5156:	f7ff ff92 	bl	507e <notify_one>
    515a:	e010      	b.n	517e <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    515c:	0783      	lsls	r3, r0, #30
    515e:	d001      	beq.n	5164 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    5160:	2a06      	cmp	r2, #6
    5162:	d10e      	bne.n	5182 <onoff_request+0x76>
	parent->next = child;
    5164:	2300      	movs	r3, #0
    5166:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    5168:	6863      	ldr	r3, [r4, #4]
    516a:	b993      	cbnz	r3, 5192 <onoff_request+0x86>
	list->head = node;
    516c:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    5170:	4615      	mov	r5, r2
    5172:	b962      	cbnz	r2, 518e <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    5174:	460a      	mov	r2, r1
    5176:	4620      	mov	r0, r4
    5178:	2102      	movs	r1, #2
    517a:	f7fb fa23 	bl	5c4 <process_event>
		}
	}

	return rv;
}
    517e:	4628      	mov	r0, r5
    5180:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    5182:	2a05      	cmp	r2, #5
    5184:	bf0c      	ite	eq
    5186:	f06f 0522 	mvneq.w	r5, #34	; 0x22
    518a:	f06f 0504 	mvnne.w	r5, #4
    518e:	2300      	movs	r3, #0
    5190:	e7d9      	b.n	5146 <onoff_request+0x3a>
	parent->next = child;
    5192:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5194:	6066      	str	r6, [r4, #4]
}
    5196:	e7eb      	b.n	5170 <onoff_request+0x64>
		rv = -EAGAIN;
    5198:	f06f 050a 	mvn.w	r5, #10
    519c:	e7f7      	b.n	518e <onoff_request+0x82>

0000519e <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    519e:	4604      	mov	r4, r0
    51a0:	b508      	push	{r3, lr}
    51a2:	4608      	mov	r0, r1
    51a4:	4611      	mov	r1, r2
	entry(p1, p2, p3);
    51a6:	461a      	mov	r2, r3
    51a8:	47a0      	blx	r4
	return z_impl_k_current_get();
    51aa:	f7fe fda1 	bl	3cf0 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
    51ae:	f7fd f995 	bl	24dc <z_impl_k_thread_abort>

000051b2 <chunk_field>:
				 enum chunk_fields f)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    51b2:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    51b4:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    51b8:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
		return ((uint32_t *)cmem)[f];
    51bc:	bf2c      	ite	cs
    51be:	f851 0022 	ldrcs.w	r0, [r1, r2, lsl #2]
	} else {
		return ((uint16_t *)cmem)[f];
    51c2:	f831 0012 	ldrhcc.w	r0, [r1, r2, lsl #1]
	}
}
    51c6:	4770      	bx	lr

000051c8 <chunk_set>:
			     enum chunk_fields f, chunkid_t val)
{
	CHECK(c <= h->len);

	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];
    51c8:	eb00 01c1 	add.w	r1, r0, r1, lsl #3

	if (big_heap(h)) {
    51cc:	6880      	ldr	r0, [r0, #8]
    51ce:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
		CHECK(val == (uint32_t)val);
		((uint32_t *)cmem)[f] = val;
    51d2:	bf2c      	ite	cs
    51d4:	f841 3022 	strcs.w	r3, [r1, r2, lsl #2]
	} else {
		CHECK(val == (uint16_t)val);
		((uint16_t *)cmem)[f] = val;
    51d8:	f821 3012 	strhcc.w	r3, [r1, r2, lsl #1]
	}
}
    51dc:	4770      	bx	lr

000051de <chunk_size>:
	return chunk_field(h, c, SIZE_AND_USED) & 1U;
}

static inline size_t chunk_size(struct z_heap *h, chunkid_t c)
{
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    51de:	2201      	movs	r2, #1
{
    51e0:	b508      	push	{r3, lr}
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    51e2:	f7ff ffe6 	bl	51b2 <chunk_field>
}
    51e6:	0840      	lsrs	r0, r0, #1
    51e8:	bd08      	pop	{r3, pc}

000051ea <set_chunk_used>:
static inline void set_chunk_used(struct z_heap *h, chunkid_t c, bool used)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    51ea:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    51ec:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    51f0:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    51f4:	d308      	bcc.n	5208 <set_chunk_used+0x1e>
		if (used) {
    51f6:	684b      	ldr	r3, [r1, #4]
    51f8:	b11a      	cbz	r2, 5202 <set_chunk_used+0x18>
			((uint32_t *)cmem)[SIZE_AND_USED] |= 1U;
    51fa:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint32_t *)cmem)[SIZE_AND_USED] &= ~1U;
    51fe:	604b      	str	r3, [r1, #4]
    5200:	4770      	bx	lr
    5202:	f023 0301 	bic.w	r3, r3, #1
    5206:	e7fa      	b.n	51fe <set_chunk_used+0x14>
		}
	} else {
		if (used) {
    5208:	884b      	ldrh	r3, [r1, #2]
    520a:	b11a      	cbz	r2, 5214 <set_chunk_used+0x2a>
			((uint16_t *)cmem)[SIZE_AND_USED] |= 1U;
    520c:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1U;
    5210:	804b      	strh	r3, [r1, #2]
		}
	}
}
    5212:	4770      	bx	lr
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1U;
    5214:	f023 0301 	bic.w	r3, r3, #1
    5218:	e7fa      	b.n	5210 <set_chunk_used+0x26>

0000521a <set_chunk_size>:
 * when its size is modified, and potential set_chunk_used() is always
 * invoked after set_chunk_size().
 */
static inline void set_chunk_size(struct z_heap *h, chunkid_t c, size_t size)
{
	chunk_set(h, c, SIZE_AND_USED, size << 1);
    521a:	0053      	lsls	r3, r2, #1
    521c:	2201      	movs	r2, #1
    521e:	f7ff bfd3 	b.w	51c8 <chunk_set>

00005222 <bucket_idx>:
	return big_heap(h) && chunk_size(h, c) == 1U;
}

static inline size_t chunk_header_bytes(struct z_heap *h)
{
	return big_heap(h) ? 8 : 4;
    5222:	6880      	ldr	r0, [r0, #8]
	return bytes_to_chunksz(h, 1);
}

static inline int bucket_idx(struct z_heap *h, size_t sz)
{
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    5224:	3101      	adds	r1, #1
	return (bytes + CHUNK_UNIT - 1U) / CHUNK_UNIT;
    5226:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
    522a:	bf2c      	ite	cs
    522c:	2002      	movcs	r0, #2
    522e:	2001      	movcc	r0, #1
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    5230:	1a08      	subs	r0, r1, r0
	return 31 - __builtin_clz(usable_sz);
    5232:	fab0 f080 	clz	r0, r0
}
    5236:	f1c0 001f 	rsb	r0, r0, #31
    523a:	4770      	bx	lr

0000523c <free_list_add>:
		set_prev_free_chunk(h, second, c);
	}
}

static void free_list_add(struct z_heap *h, chunkid_t c)
{
    523c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5240:	4604      	mov	r4, r0
    5242:	460d      	mov	r5, r1
	return sizeof(void *) > 4U || chunks > 0x7fffU;
    5244:	f7ff ffcb 	bl	51de <chunk_size>
	return big_heap(h) && chunk_size(h, c) == 1U;
    5248:	68a3      	ldr	r3, [r4, #8]
    524a:	4601      	mov	r1, r0
    524c:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    5250:	d301      	bcc.n	5256 <free_list_add+0x1a>
	if (!solo_free_header(h, c)) {
    5252:	2801      	cmp	r0, #1
    5254:	d035      	beq.n	52c2 <free_list_add+0x86>
		int bidx = bucket_idx(h, chunk_size(h, c));
    5256:	4620      	mov	r0, r4
    5258:	f7ff ffe3 	bl	5222 <bucket_idx>
	if (b->next == 0U) {
    525c:	eb04 0280 	add.w	r2, r4, r0, lsl #2
    5260:	6916      	ldr	r6, [r2, #16]
    5262:	b99e      	cbnz	r6, 528c <free_list_add+0x50>
		h->avail_buckets |= (1 << bidx);
    5264:	2301      	movs	r3, #1
    5266:	fa03 f000 	lsl.w	r0, r3, r0
    526a:	68e3      	ldr	r3, [r4, #12]
	chunk_set(h, c, FREE_PREV, prev);
    526c:	4629      	mov	r1, r5
    526e:	4303      	orrs	r3, r0
    5270:	60e3      	str	r3, [r4, #12]
    5272:	4620      	mov	r0, r4
		b->next = c;
    5274:	6115      	str	r5, [r2, #16]
    5276:	462b      	mov	r3, r5
    5278:	2202      	movs	r2, #2
    527a:	f7ff ffa5 	bl	51c8 <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    527e:	2203      	movs	r2, #3
    5280:	4629      	mov	r1, r5
	chunk_set(h, c, FREE_PREV, prev);
    5282:	4620      	mov	r0, r4
		free_list_add_bidx(h, c, bidx);
	}
}
    5284:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    5288:	f7ff bf9e 	b.w	51c8 <chunk_set>
	return chunk_field(h, c, FREE_PREV);
    528c:	2202      	movs	r2, #2
    528e:	4631      	mov	r1, r6
    5290:	4620      	mov	r0, r4
    5292:	f7ff ff8e 	bl	51b2 <chunk_field>
    5296:	4607      	mov	r7, r0
	chunk_set(h, c, FREE_PREV, prev);
    5298:	4603      	mov	r3, r0
    529a:	2202      	movs	r2, #2
    529c:	4629      	mov	r1, r5
    529e:	4620      	mov	r0, r4
    52a0:	f7ff ff92 	bl	51c8 <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    52a4:	4633      	mov	r3, r6
    52a6:	2203      	movs	r2, #3
    52a8:	4629      	mov	r1, r5
    52aa:	4620      	mov	r0, r4
    52ac:	f7ff ff8c 	bl	51c8 <chunk_set>
    52b0:	2203      	movs	r2, #3
    52b2:	4639      	mov	r1, r7
    52b4:	462b      	mov	r3, r5
    52b6:	4620      	mov	r0, r4
    52b8:	f7ff ff86 	bl	51c8 <chunk_set>
	chunk_set(h, c, FREE_PREV, prev);
    52bc:	2202      	movs	r2, #2
    52be:	4631      	mov	r1, r6
    52c0:	e7df      	b.n	5282 <free_list_add+0x46>
    52c2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000052c6 <sys_heap_init>:
	return big_heap_bytes(size) ? 8 : 4;
    52c6:	f5b2 2f80 	cmp.w	r2, #262144	; 0x40000
	set_chunk_used(h, c, true);
	return mem;
}

void sys_heap_init(struct sys_heap *heap, void *mem, size_t bytes)
{
    52ca:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    52cc:	bf2c      	ite	cs
    52ce:	2508      	movcs	r5, #8
    52d0:	2504      	movcc	r5, #4
	CHECK(end > addr);
	__ASSERT(buf_sz > chunksz(sizeof(struct z_heap)), "heap size is too small");

	struct z_heap *h = (struct z_heap *)addr;
	heap->heap = h;
	h->chunk0_hdr_area = 0;
    52d2:	2300      	movs	r3, #0
	bytes -= heap_footer_bytes(bytes);
    52d4:	1b55      	subs	r5, r2, r5
	h->chunk0_hdr_area = 0;
    52d6:	2200      	movs	r2, #0
	uintptr_t addr = ROUND_UP(mem, CHUNK_UNIT);
    52d8:	1dcc      	adds	r4, r1, #7
    52da:	f024 0407 	bic.w	r4, r4, #7
	heap->heap = h;
    52de:	6004      	str	r4, [r0, #0]
	h->chunk0_hdr_area = 0;
    52e0:	e9c4 2300 	strd	r2, r3, [r4]
	h->len = buf_sz;
	h->avail_buckets = 0;
    52e4:	2300      	movs	r3, #0
	uintptr_t end = ROUND_DOWN((uint8_t *)mem + bytes, CHUNK_UNIT);
    52e6:	440d      	add	r5, r1
    52e8:	f025 0507 	bic.w	r5, r5, #7
	size_t buf_sz = (end - addr) / CHUNK_UNIT;
    52ec:	1b2d      	subs	r5, r5, r4
    52ee:	08ed      	lsrs	r5, r5, #3

	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    52f0:	4629      	mov	r1, r5
    52f2:	4620      	mov	r0, r4
	h->len = buf_sz;
    52f4:	60a5      	str	r5, [r4, #8]
	h->avail_buckets = 0;
    52f6:	60e3      	str	r3, [r4, #12]
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    52f8:	f7ff ff93 	bl	5222 <bucket_idx>
	size_t chunk0_size = chunksz(sizeof(struct z_heap) +
    52fc:	0086      	lsls	r6, r0, #2
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    52fe:	1c41      	adds	r1, r0, #1
				     nb_buckets * sizeof(struct z_heap_bucket));

	__ASSERT(chunk0_size + min_chunk_size(h) < buf_sz, "heap size is too small");

	for (int i = 0; i < nb_buckets; i++) {
		h->buckets[i].next = 0;
    5300:	4618      	mov	r0, r3
	return (bytes + CHUNK_UNIT - 1U) / CHUNK_UNIT;
    5302:	361b      	adds	r6, #27
    5304:	08f6      	lsrs	r6, r6, #3
	for (int i = 0; i < nb_buckets; i++) {
    5306:	f104 0210 	add.w	r2, r4, #16
    530a:	428b      	cmp	r3, r1
    530c:	db29      	blt.n	5362 <sys_heap_init+0x9c>
	}

	/* chunk containing our struct z_heap */
	set_chunk_size(h, 0, chunk0_size);
    530e:	4632      	mov	r2, r6
    5310:	4620      	mov	r0, r4
    5312:	2100      	movs	r1, #0
    5314:	f7ff ff81 	bl	521a <set_chunk_size>
	set_chunk_used(h, 0, true);

	/* chunk containing the free heap */
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    5318:	1baf      	subs	r7, r5, r6
	set_chunk_used(h, 0, true);
    531a:	4620      	mov	r0, r4
    531c:	2201      	movs	r2, #1
    531e:	2100      	movs	r1, #0
    5320:	f7ff ff63 	bl	51ea <set_chunk_used>
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    5324:	463a      	mov	r2, r7
    5326:	4631      	mov	r1, r6
    5328:	f7ff ff77 	bl	521a <set_chunk_size>
	chunk_set(h, c, LEFT_SIZE, size);
    532c:	4633      	mov	r3, r6
    532e:	4631      	mov	r1, r6
    5330:	4620      	mov	r0, r4
    5332:	2200      	movs	r2, #0
    5334:	f7ff ff48 	bl	51c8 <chunk_set>
	set_left_chunk_size(h, chunk0_size, chunk0_size);

	/* the end marker chunk */
	set_chunk_size(h, buf_sz, 0);
    5338:	4629      	mov	r1, r5
    533a:	4620      	mov	r0, r4
    533c:	2200      	movs	r2, #0
    533e:	f7ff ff6c 	bl	521a <set_chunk_size>
    5342:	463b      	mov	r3, r7
    5344:	4629      	mov	r1, r5
    5346:	4620      	mov	r0, r4
    5348:	2200      	movs	r2, #0
    534a:	f7ff ff3d 	bl	51c8 <chunk_set>
	set_left_chunk_size(h, buf_sz, buf_sz - chunk0_size);
	set_chunk_used(h, buf_sz, true);
    534e:	4629      	mov	r1, r5
    5350:	4620      	mov	r0, r4
    5352:	2201      	movs	r2, #1
    5354:	f7ff ff49 	bl	51ea <set_chunk_used>

	free_list_add(h, chunk0_size);
    5358:	4631      	mov	r1, r6
}
    535a:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	free_list_add(h, chunk0_size);
    535e:	f7ff bf6d 	b.w	523c <free_list_add>
		h->buckets[i].next = 0;
    5362:	f842 0b04 	str.w	r0, [r2], #4
	for (int i = 0; i < nb_buckets; i++) {
    5366:	3301      	adds	r3, #1
    5368:	e7cf      	b.n	530a <sys_heap_init+0x44>

0000536a <_rlrshift>:
	*v = (*v & 1) + (*v >> 1);
    536a:	2100      	movs	r1, #0
{
    536c:	b570      	push	{r4, r5, r6, lr}
	*v = (*v & 1) + (*v >> 1);
    536e:	e9d0 6500 	ldrd	r6, r5, [r0]
    5372:	0872      	lsrs	r2, r6, #1
    5374:	f006 0301 	and.w	r3, r6, #1
    5378:	ea42 72c5 	orr.w	r2, r2, r5, lsl #31
    537c:	189b      	adds	r3, r3, r2
    537e:	ea4f 0455 	mov.w	r4, r5, lsr #1
    5382:	eb44 0101 	adc.w	r1, r4, r1
    5386:	e9c0 3100 	strd	r3, r1, [r0]
}
    538a:	bd70      	pop	{r4, r5, r6, pc}

0000538c <_ldiv5>:
	__asm__ ("" : "+r" (m));
    538c:	f04f 3133 	mov.w	r1, #858993459	; 0x33333333
	result = ((uint64_t)(m * 3U) << 32) | (m * 3U);
    5390:	eb01 0341 	add.w	r3, r1, r1, lsl #1
{
    5394:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	uint32_t v_lo = *v;
    5398:	e9d0 2400 	ldrd	r2, r4, [r0]
	result = ((uint64_t)(m * 3U) << 32) | (m * 3U);
    539c:	461d      	mov	r5, r3
	result >>= 32;
    539e:	2700      	movs	r7, #0
	result += (uint64_t)v_lo * m;
    53a0:	fba2 8901 	umull	r8, r9, r2, r1
    53a4:	eb18 0505 	adds.w	r5, r8, r5
	result += (uint64_t)v_hi * m;
    53a8:	fba4 4501 	umull	r4, r5, r4, r1
	result += (uint64_t)v_lo * m;
    53ac:	eb49 0603 	adc.w	r6, r9, r3
	result += (uint64_t)v_hi * m;
    53b0:	eb18 0204 	adds.w	r2, r8, r4
    53b4:	eb49 0105 	adc.w	r1, r9, r5
    53b8:	1992      	adds	r2, r2, r6
	result >>= 32;
    53ba:	463a      	mov	r2, r7
	result += (uint64_t)v_hi * m;
    53bc:	eb47 0101 	adc.w	r1, r7, r1
	result += (uint64_t)v_hi * m;
    53c0:	1863      	adds	r3, r4, r1
    53c2:	eb45 0202 	adc.w	r2, r5, r2
	*v = result;
    53c6:	e9c0 3200 	strd	r3, r2, [r0]
}
    53ca:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}

000053ce <_get_digit>:
	if (*digit_count > 0) {
    53ce:	680b      	ldr	r3, [r1, #0]
{
    53d0:	b570      	push	{r4, r5, r6, lr}
	if (*digit_count > 0) {
    53d2:	2b00      	cmp	r3, #0
    53d4:	dd10      	ble.n	53f8 <_get_digit+0x2a>
		--*digit_count;
    53d6:	3b01      	subs	r3, #1
    53d8:	600b      	str	r3, [r1, #0]
		*fr *= 10U;
    53da:	210a      	movs	r1, #10
    53dc:	6802      	ldr	r2, [r0, #0]
    53de:	6844      	ldr	r4, [r0, #4]
    53e0:	fba2 5601 	umull	r5, r6, r2, r1
    53e4:	fb01 6604 	mla	r6, r1, r4, r6
		*fr &= (BIT64(60) - 1U);
    53e8:	f026 4370 	bic.w	r3, r6, #4026531840	; 0xf0000000
    53ec:	e9c0 5300 	strd	r5, r3, [r0]
		rval = ((*fr >> 60) & 0xF) + '0';
    53f0:	0f31      	lsrs	r1, r6, #28
    53f2:	3130      	adds	r1, #48	; 0x30
}
    53f4:	4608      	mov	r0, r1
    53f6:	bd70      	pop	{r4, r5, r6, pc}
		rval = '0';
    53f8:	2130      	movs	r1, #48	; 0x30
    53fa:	e7fb      	b.n	53f4 <_get_digit+0x26>

000053fc <encode_uint>:
{
    53fc:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5400:	4699      	mov	r9, r3
	bool upcase = isupper((int)conv->specifier);
    5402:	78d3      	ldrb	r3, [r2, #3]
{
    5404:	4614      	mov	r4, r2
	switch (specifier) {
    5406:	2b6f      	cmp	r3, #111	; 0x6f
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    5408:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
{
    540c:	4606      	mov	r6, r0
    540e:	460f      	mov	r7, r1
    5410:	9201      	str	r2, [sp, #4]
	switch (specifier) {
    5412:	d02d      	beq.n	5470 <encode_uint+0x74>
    5414:	d828      	bhi.n	5468 <encode_uint+0x6c>
		return 16;
    5416:	2b58      	cmp	r3, #88	; 0x58
    5418:	bf14      	ite	ne
    541a:	250a      	movne	r5, #10
    541c:	2510      	moveq	r5, #16
		unsigned int lsv = (unsigned int)(value % radix);
    541e:	46aa      	mov	sl, r5
    5420:	f04f 0b00 	mov.w	fp, #0
	char *bp = bps + (bpe - bps);
    5424:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
		unsigned int lsv = (unsigned int)(value % radix);
    5428:	4652      	mov	r2, sl
    542a:	465b      	mov	r3, fp
    542c:	4630      	mov	r0, r6
    542e:	4639      	mov	r1, r7
    5430:	f7fa ff04 	bl	23c <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5434:	2a09      	cmp	r2, #9
    5436:	b2d3      	uxtb	r3, r2
    5438:	d81f      	bhi.n	547a <encode_uint+0x7e>
    543a:	3330      	adds	r3, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    543c:	455f      	cmp	r7, fp
		*--bp = (lsv <= 9) ? ('0' + lsv)
    543e:	b2db      	uxtb	r3, r3
	} while ((value != 0) && (bps < bp));
    5440:	bf08      	it	eq
    5442:	4556      	cmpeq	r6, sl
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5444:	f808 3d01 	strb.w	r3, [r8, #-1]!
	} while ((value != 0) && (bps < bp));
    5448:	d301      	bcc.n	544e <encode_uint+0x52>
    544a:	45c8      	cmp	r8, r9
    544c:	d812      	bhi.n	5474 <encode_uint+0x78>
	if (conv->flag_hash) {
    544e:	7823      	ldrb	r3, [r4, #0]
    5450:	069b      	lsls	r3, r3, #26
    5452:	d505      	bpl.n	5460 <encode_uint+0x64>
		if (radix == 8) {
    5454:	2d08      	cmp	r5, #8
    5456:	d116      	bne.n	5486 <encode_uint+0x8a>
			conv->altform_0 = true;
    5458:	78a3      	ldrb	r3, [r4, #2]
    545a:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    545e:	70a3      	strb	r3, [r4, #2]
}
    5460:	4640      	mov	r0, r8
    5462:	b003      	add	sp, #12
    5464:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    5468:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
    546c:	2b70      	cmp	r3, #112	; 0x70
    546e:	e7d3      	b.n	5418 <encode_uint+0x1c>
	switch (specifier) {
    5470:	2508      	movs	r5, #8
    5472:	e7d4      	b.n	541e <encode_uint+0x22>
		value /= radix;
    5474:	4606      	mov	r6, r0
    5476:	460f      	mov	r7, r1
    5478:	e7d6      	b.n	5428 <encode_uint+0x2c>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    547a:	9a01      	ldr	r2, [sp, #4]
    547c:	2a19      	cmp	r2, #25
    547e:	bf94      	ite	ls
    5480:	3337      	addls	r3, #55	; 0x37
    5482:	3357      	addhi	r3, #87	; 0x57
    5484:	e7da      	b.n	543c <encode_uint+0x40>
		} else if (radix == 16) {
    5486:	2d10      	cmp	r5, #16
    5488:	d1ea      	bne.n	5460 <encode_uint+0x64>
			conv->altform_0c = true;
    548a:	78a3      	ldrb	r3, [r4, #2]
    548c:	f043 0310 	orr.w	r3, r3, #16
    5490:	e7e5      	b.n	545e <encode_uint+0x62>

00005492 <outs>:
{
    5492:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5496:	4680      	mov	r8, r0
    5498:	4689      	mov	r9, r1
    549a:	4616      	mov	r6, r2
    549c:	461f      	mov	r7, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    549e:	4615      	mov	r5, r2
    54a0:	42bd      	cmp	r5, r7
    54a2:	eba5 0406 	sub.w	r4, r5, r6
    54a6:	d305      	bcc.n	54b4 <outs+0x22>
    54a8:	b10f      	cbz	r7, 54ae <outs+0x1c>
	return (int)count;
    54aa:	4620      	mov	r0, r4
    54ac:	e008      	b.n	54c0 <outs+0x2e>
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    54ae:	782b      	ldrb	r3, [r5, #0]
    54b0:	2b00      	cmp	r3, #0
    54b2:	d0fa      	beq.n	54aa <outs+0x18>
		int rc = out((int)*sp++, ctx);
    54b4:	4649      	mov	r1, r9
    54b6:	f815 0b01 	ldrb.w	r0, [r5], #1
    54ba:	47c0      	blx	r8
		if (rc < 0) {
    54bc:	2800      	cmp	r0, #0
    54be:	daef      	bge.n	54a0 <outs+0xe>
}
    54c0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000054c4 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM(CONFIG_REBOOT, 1);
GEN_ABSOLUTE_SYM(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    54c4:	4770      	bx	lr

000054c6 <z_platform_init>:

void z_platform_init(void)
{
	SystemInit();
    54c6:	f7fd bc4d 	b.w	2d64 <SystemInit>

000054ca <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    54ca:	b2cb      	uxtb	r3, r1
    54cc:	210c      	movs	r1, #12
    54ce:	68c2      	ldr	r2, [r0, #12]
    54d0:	fb03 2101 	mla	r1, r3, r1, r2
    54d4:	6c08      	ldr	r0, [r1, #64]	; 0x40
}
    54d6:	f000 0007 	and.w	r0, r0, #7
    54da:	4770      	bx	lr

000054dc <set_off_state>:
	__asm__ volatile(
    54dc:	f04f 0320 	mov.w	r3, #32
    54e0:	f3ef 8211 	mrs	r2, BASEPRI
    54e4:	f383 8811 	msr	BASEPRI, r3
    54e8:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    54ec:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    54ee:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    54f2:	d001      	beq.n	54f8 <set_off_state+0x1c>
    54f4:	428b      	cmp	r3, r1
    54f6:	d107      	bne.n	5508 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    54f8:	2301      	movs	r3, #1
    54fa:	6003      	str	r3, [r0, #0]
	int err = 0;
    54fc:	2000      	movs	r0, #0
	__asm__ volatile(
    54fe:	f382 8811 	msr	BASEPRI, r2
    5502:	f3bf 8f6f 	isb	sy
}
    5506:	4770      	bx	lr
		err = -EPERM;
    5508:	f04f 30ff 	mov.w	r0, #4294967295
    550c:	e7f7      	b.n	54fe <set_off_state+0x22>

0000550e <set_starting_state>:
{
    550e:	b510      	push	{r4, lr}
	__asm__ volatile(
    5510:	f04f 0320 	mov.w	r3, #32
    5514:	f3ef 8211 	mrs	r2, BASEPRI
    5518:	f383 8811 	msr	BASEPRI, r3
    551c:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    5520:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    5522:	f003 0407 	and.w	r4, r3, #7
    5526:	2c01      	cmp	r4, #1
    5528:	d106      	bne.n	5538 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    552a:	6001      	str	r1, [r0, #0]
	int err = 0;
    552c:	2000      	movs	r0, #0
	__asm__ volatile(
    552e:	f382 8811 	msr	BASEPRI, r2
    5532:	f3bf 8f6f 	isb	sy
}
    5536:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    5538:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    553c:	428b      	cmp	r3, r1
		err = -EALREADY;
    553e:	bf14      	ite	ne
    5540:	f04f 30ff 	movne.w	r0, #4294967295
    5544:	f06f 0044 	mvneq.w	r0, #68	; 0x44
    5548:	e7f1      	b.n	552e <set_starting_state+0x20>

0000554a <set_on_state>:
	__asm__ volatile(
    554a:	f04f 0320 	mov.w	r3, #32
    554e:	f3ef 8211 	mrs	r2, BASEPRI
    5552:	f383 8811 	msr	BASEPRI, r3
    5556:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    555a:	6803      	ldr	r3, [r0, #0]
    555c:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    5560:	f043 0302 	orr.w	r3, r3, #2
    5564:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    5566:	f382 8811 	msr	BASEPRI, r2
    556a:	f3bf 8f6f 	isb	sy
}
    556e:	4770      	bx	lr

00005570 <onoff_started_callback>:
{
    5570:	b410      	push	{r4}
	notify(mgr, 0);
    5572:	241c      	movs	r4, #28
	return &data->mgr[type];
    5574:	68c0      	ldr	r0, [r0, #12]
    5576:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    5578:	fb03 0004 	mla	r0, r3, r4, r0
    557c:	2100      	movs	r1, #0
}
    557e:	f85d 4b04 	ldr.w	r4, [sp], #4
	notify(mgr, 0);
    5582:	4710      	bx	r2

00005584 <blocking_start_callback>:
{
    5584:	4610      	mov	r0, r2
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    5586:	f7fe bbb9 	b.w	3cfc <z_impl_k_sem_give>

0000558a <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    558a:	2000      	movs	r0, #0
    558c:	f7fd bce6 	b.w	2f5c <nrfx_clock_stop>

00005590 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    5590:	2000      	movs	r0, #0
    5592:	f7fd bcb1 	b.w	2ef8 <nrfx_clock_start>

00005596 <api_stop>:
{
    5596:	b538      	push	{r3, r4, r5, lr}
	err = set_off_state(&subdata->flags, ctx);
    5598:	230c      	movs	r3, #12
    559a:	b2cc      	uxtb	r4, r1
    559c:	4363      	muls	r3, r4
{
    559e:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    55a0:	68c0      	ldr	r0, [r0, #12]
    55a2:	3340      	adds	r3, #64	; 0x40
    55a4:	2180      	movs	r1, #128	; 0x80
    55a6:	4418      	add	r0, r3
    55a8:	f7ff ff98 	bl	54dc <set_off_state>
	if (err < 0) {
    55ac:	2800      	cmp	r0, #0
    55ae:	db05      	blt.n	55bc <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    55b0:	6869      	ldr	r1, [r5, #4]
    55b2:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
    55b6:	6863      	ldr	r3, [r4, #4]
    55b8:	4798      	blx	r3
	return 0;
    55ba:	2000      	movs	r0, #0
}
    55bc:	bd38      	pop	{r3, r4, r5, pc}

000055be <api_start>:
{
    55be:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	err = set_starting_state(&subdata->flags, ctx);
    55c2:	270c      	movs	r7, #12
    55c4:	b2cd      	uxtb	r5, r1
    55c6:	436f      	muls	r7, r5
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    55c8:	68c4      	ldr	r4, [r0, #12]
{
    55ca:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    55cc:	f107 0040 	add.w	r0, r7, #64	; 0x40
    55d0:	2180      	movs	r1, #128	; 0x80
    55d2:	4420      	add	r0, r4
{
    55d4:	4690      	mov	r8, r2
    55d6:	4699      	mov	r9, r3
	err = set_starting_state(&subdata->flags, ctx);
    55d8:	f7ff ff99 	bl	550e <set_starting_state>
	if (err < 0) {
    55dc:	2800      	cmp	r0, #0
    55de:	db07      	blt.n	55f0 <api_start+0x32>
	subdata->cb = cb;
    55e0:	443c      	add	r4, r7
	subdata->user_data = user_data;
    55e2:	e9c4 890e 	strd	r8, r9, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    55e6:	6873      	ldr	r3, [r6, #4]
    55e8:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
    55ec:	4798      	blx	r3
	return 0;
    55ee:	2000      	movs	r0, #0
}
    55f0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000055f4 <z_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces: */

void __weak z_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    55f4:	4770      	bx	lr

000055f6 <z_clock_idle_exit>:
{
}

void __weak z_clock_idle_exit(void)
{
}
    55f6:	4770      	bx	lr

000055f8 <sys_clock_disable>:
    55f8:	4770      	bx	lr

000055fa <spm_secure_services_init>:
	mbedtls_platform_context platform_ctx = {0};
    55fa:	2300      	movs	r3, #0
{
    55fc:	b507      	push	{r0, r1, r2, lr}
	err = mbedtls_platform_setup(&platform_ctx);
    55fe:	a801      	add	r0, sp, #4
	mbedtls_platform_context platform_ctx = {0};
    5600:	f88d 3004 	strb.w	r3, [sp, #4]
	err = mbedtls_platform_setup(&platform_ctx);
    5604:	f7fe fee2 	bl	43cc <mbedtls_platform_setup>
}
    5608:	b003      	add	sp, #12
    560a:	f85d fb04 	ldr.w	pc, [sp], #4

0000560e <__acle_se_spm_request_random_number_nse>:
	if (len != MBEDTLS_ENTROPY_MAX_GATHER) {
    560e:	2990      	cmp	r1, #144	; 0x90
{
    5610:	b508      	push	{r3, lr}
    5612:	4613      	mov	r3, r2
	if (len != MBEDTLS_ENTROPY_MAX_GATHER) {
    5614:	d139      	bne.n	568a <__acle_se_spm_request_random_number_nse+0x7c>
	err = mbedtls_hardware_poll(NULL, output, len, olen);
    5616:	460a      	mov	r2, r1
    5618:	4601      	mov	r1, r0
    561a:	2000      	movs	r0, #0
    561c:	f7fe fee2 	bl	43e4 <mbedtls_hardware_poll>
}
    5620:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    5624:	4671      	mov	r1, lr
    5626:	4672      	mov	r2, lr
    5628:	4673      	mov	r3, lr
    562a:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    562e:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    5632:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    5636:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    563a:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    563e:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    5642:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    5646:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    564a:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    564e:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    5652:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    5656:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    565a:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    565e:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    5662:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    5666:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    566a:	f38e 8c00 	msr	CPSR_fs, lr
    566e:	b410      	push	{r4}
    5670:	eef1 ca10 	vmrs	ip, fpscr
    5674:	f64f 7460 	movw	r4, #65376	; 0xff60
    5678:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    567c:	ea0c 0c04 	and.w	ip, ip, r4
    5680:	eee1 ca10 	vmsr	fpscr, ip
    5684:	bc10      	pop	{r4}
    5686:	46f4      	mov	ip, lr
    5688:	4774      	bxns	lr
		return -EINVAL;
    568a:	f06f 0015 	mvn.w	r0, #21
    568e:	e7c7      	b.n	5620 <__acle_se_spm_request_random_number_nse+0x12>

00005690 <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
    5690:	2000      	movs	r0, #0
    5692:	f7fb bebb 	b.w	140c <sys_reboot>

00005696 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    5696:	2100      	movs	r1, #0
    5698:	2001      	movs	r0, #1
    569a:	f000 b832 	b.w	5702 <z_arm_fatal_error>

0000569e <irq_target_state_set>:
irq_target_state_t irq_target_state_set(unsigned int irq,
	irq_target_state_t irq_target_state)
{
	uint32_t result;

	if (irq_target_state == IRQ_TARGET_STATE_SECURE) {
    569e:	b243      	sxtb	r3, r0
    56a0:	b9c9      	cbnz	r1, 56d6 <irq_target_state_set+0x38>
  if ((int32_t)(IRQn) >= 0)
    56a2:	2b00      	cmp	r3, #0
    56a4:	db15      	blt.n	56d2 <irq_target_state_set+0x34>
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    56a6:	2101      	movs	r1, #1
    56a8:	095b      	lsrs	r3, r3, #5
    56aa:	009b      	lsls	r3, r3, #2
    56ac:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    56b0:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    56b4:	f8d3 2280 	ldr.w	r2, [r3, #640]	; 0x280
    56b8:	f000 001f 	and.w	r0, r0, #31
    56bc:	4081      	lsls	r1, r0
    56be:	ea22 0201 	bic.w	r2, r2, r1
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    56c2:	f8c3 2280 	str.w	r2, [r3, #640]	; 0x280
    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
    56c6:	f8d3 1280 	ldr.w	r1, [r3, #640]	; 0x280
    56ca:	40c1      	lsrs	r1, r0
    56cc:	f001 0101 	and.w	r1, r1, #1
	} else {
		/* Set target to Non-Secure */
		result = NVIC_SetTargetState(irq);
	}

	if (result) {
    56d0:	b2c9      	uxtb	r1, r1
		return IRQ_TARGET_STATE_NON_SECURE;
	} else {
		return IRQ_TARGET_STATE_SECURE;
	}
}
    56d2:	4608      	mov	r0, r1
    56d4:	4770      	bx	lr
  if ((int32_t)(IRQn) >= 0)
    56d6:	2b00      	cmp	r3, #0
    56d8:	db0d      	blt.n	56f6 <irq_target_state_set+0x58>
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    56da:	2201      	movs	r2, #1
    56dc:	095b      	lsrs	r3, r3, #5
    56de:	009b      	lsls	r3, r3, #2
    56e0:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    56e4:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    56e8:	f8d3 1280 	ldr.w	r1, [r3, #640]	; 0x280
    56ec:	f000 001f 	and.w	r0, r0, #31
    56f0:	4082      	lsls	r2, r0
    56f2:	430a      	orrs	r2, r1
    56f4:	e7e5      	b.n	56c2 <irq_target_state_set+0x24>
		return IRQ_TARGET_STATE_SECURE;
    56f6:	2100      	movs	r1, #0
    56f8:	e7eb      	b.n	56d2 <irq_target_state_set+0x34>

000056fa <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    56fa:	6e83      	ldr	r3, [r0, #104]	; 0x68
    56fc:	f383 880b 	msr	PSPLIM, r3
}
    5700:	4770      	bx	lr

00005702 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    5702:	f000 b929 	b.w	5958 <z_fatal_error>

00005706 <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    5706:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    5708:	6800      	ldr	r0, [r0, #0]
    570a:	f000 b925 	b.w	5958 <z_fatal_error>

0000570e <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    570e:	b508      	push	{r3, lr}
	handler();
    5710:	f7fc fce8 	bl	20e4 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    5714:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    5718:	f7fc be7e 	b.w	2418 <z_arm_exc_exit>

0000571c <mpu_configure_region>:
{
    571c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	p_attr->rbar = attr->rbar &
    571e:	890a      	ldrh	r2, [r1, #8]
    5720:	7a8e      	ldrb	r6, [r1, #10]
	region_conf.base = new_region->start;
    5722:	680b      	ldr	r3, [r1, #0]
	get_region_attr_from_k_mem_partition_info(&region_conf.attr,
    5724:	684d      	ldr	r5, [r1, #4]
    5726:	f002 021f 	and.w	r2, r2, #31
    572a:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
	region_conf.base = new_region->start;
    572e:	9300      	str	r3, [sp, #0]
    5730:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    5734:	f023 031f 	bic.w	r3, r3, #31
    5738:	1e6a      	subs	r2, r5, #1
    573a:	4413      	add	r3, r2
    573c:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1U)) {
    5740:	280f      	cmp	r0, #15
    5742:	9303      	str	r3, [sp, #12]
    5744:	d804      	bhi.n	5750 <mpu_configure_region+0x34>
	region_init(index, region_conf);
    5746:	4669      	mov	r1, sp
    5748:	f7fc ff14 	bl	2574 <region_init>
}
    574c:	b004      	add	sp, #16
    574e:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    5750:	f06f 0015 	mvn.w	r0, #21
	return region_allocate_and_init(index,
    5754:	e7fa      	b.n	574c <mpu_configure_region+0x30>

00005756 <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    5756:	e840 f000 	tt	r0, r0
    575a:	b2c3      	uxtb	r3, r0

int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
    575c:	f410 3f80 	tst.w	r0, #65536	; 0x10000
		return addr_info.flags.mpu_region;
	}

	return -EINVAL;
}
    5760:	bf14      	ite	ne
    5762:	4618      	movne	r0, r3
    5764:	f06f 0015 	mvneq.w	r0, #21
    5768:	4770      	bx	lr

0000576a <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    576a:	4603      	mov	r3, r0
	size_t n = 0;
    576c:	2000      	movs	r0, #0

	while (*s != '\0') {
    576e:	5c1a      	ldrb	r2, [r3, r0]
    5770:	b902      	cbnz	r2, 5774 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    5772:	4770      	bx	lr
		n++;
    5774:	3001      	adds	r0, #1
    5776:	e7fa      	b.n	576e <strlen+0x4>

00005778 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    5778:	3801      	subs	r0, #1
    577a:	3901      	subs	r1, #1
    577c:	f810 3f01 	ldrb.w	r3, [r0, #1]!
    5780:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    5784:	4293      	cmp	r3, r2
    5786:	d101      	bne.n	578c <strcmp+0x14>
    5788:	2b00      	cmp	r3, #0
    578a:	d1f7      	bne.n	577c <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    578c:	1a98      	subs	r0, r3, r2
    578e:	4770      	bx	lr

00005790 <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    5790:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    5792:	b15a      	cbz	r2, 57ac <memcmp+0x1c>
    5794:	3901      	subs	r1, #1
    5796:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    5798:	f810 2b01 	ldrb.w	r2, [r0], #1
    579c:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    57a0:	42a0      	cmp	r0, r4
    57a2:	d001      	beq.n	57a8 <memcmp+0x18>
    57a4:	429a      	cmp	r2, r3
    57a6:	d0f7      	beq.n	5798 <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    57a8:	1ad0      	subs	r0, r2, r3
}
    57aa:	bd10      	pop	{r4, pc}
		return 0;
    57ac:	4610      	mov	r0, r2
    57ae:	e7fc      	b.n	57aa <memcmp+0x1a>

000057b0 <memmove>:
void *memmove(void *d, const void *s, size_t n)
{
	char *dest = d;
	const char *src  = s;

	if ((size_t) (dest - src) < n) {
    57b0:	1a43      	subs	r3, r0, r1
    57b2:	4293      	cmp	r3, r2
{
    57b4:	b510      	push	{r4, lr}
    57b6:	eb00 0302 	add.w	r3, r0, r2
	if ((size_t) (dest - src) < n) {
    57ba:	d308      	bcc.n	57ce <memmove+0x1e>
	char *dest = d;
    57bc:	4602      	mov	r2, r0
    57be:	3901      	subs	r1, #1
			n--;
			dest[n] = src[n];
		}
	} else {
		/* It is safe to perform a forward-copy */
		while (n > 0) {
    57c0:	429a      	cmp	r2, r3
    57c2:	d00b      	beq.n	57dc <memmove+0x2c>
			*dest = *src;
    57c4:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    57c8:	f802 4b01 	strb.w	r4, [r2], #1
			dest++;
			src++;
			n--;
    57cc:	e7f8      	b.n	57c0 <memmove+0x10>
    57ce:	440a      	add	r2, r1
			dest[n] = src[n];
    57d0:	f812 4d01 	ldrb.w	r4, [r2, #-1]!
		while (n > 0) {
    57d4:	428a      	cmp	r2, r1
			dest[n] = src[n];
    57d6:	f803 4d01 	strb.w	r4, [r3, #-1]!
		while (n > 0) {
    57da:	d1f9      	bne.n	57d0 <memmove+0x20>
		}
	}

	return d;
}
    57dc:	bd10      	pop	{r4, pc}

000057de <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
    57de:	b5f0      	push	{r4, r5, r6, r7, lr}

	unsigned char *d_byte = (unsigned char *)d;
	const unsigned char *s_byte = (const unsigned char *)s;
	const uintptr_t mask = sizeof(mem_word_t) - 1;

	if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) {
    57e0:	ea81 0400 	eor.w	r4, r1, r0
    57e4:	07a5      	lsls	r5, r4, #30
    57e6:	4603      	mov	r3, r0
    57e8:	d00b      	beq.n	5802 <memcpy+0x24>
    57ea:	3b01      	subs	r3, #1
    57ec:	440a      	add	r2, r1
		s_byte = (unsigned char *)s_word;
	}

	/* do byte-sized copying until finished */

	while (n > 0) {
    57ee:	4291      	cmp	r1, r2
    57f0:	d11b      	bne.n	582a <memcpy+0x4c>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    57f2:	bdf0      	pop	{r4, r5, r6, r7, pc}
			if (n == 0) {
    57f4:	2a00      	cmp	r2, #0
    57f6:	d0fc      	beq.n	57f2 <memcpy+0x14>
			*(d_byte++) = *(s_byte++);
    57f8:	f811 4b01 	ldrb.w	r4, [r1], #1
			n--;
    57fc:	3a01      	subs	r2, #1
			*(d_byte++) = *(s_byte++);
    57fe:	f803 4b01 	strb.w	r4, [r3], #1
		while (((uintptr_t)d_byte) & mask) {
    5802:	079c      	lsls	r4, r3, #30
    5804:	d1f6      	bne.n	57f4 <memcpy+0x16>
    5806:	f022 0403 	bic.w	r4, r2, #3
    580a:	1f1d      	subs	r5, r3, #4
    580c:	0896      	lsrs	r6, r2, #2
    580e:	190f      	adds	r7, r1, r4
		while (n >= sizeof(mem_word_t)) {
    5810:	42b9      	cmp	r1, r7
    5812:	d105      	bne.n	5820 <memcpy+0x42>
    5814:	f06f 0503 	mvn.w	r5, #3
    5818:	4423      	add	r3, r4
    581a:	fb05 2206 	mla	r2, r5, r6, r2
    581e:	e7e4      	b.n	57ea <memcpy+0xc>
			*(d_word++) = *(s_word++);
    5820:	f851 cb04 	ldr.w	ip, [r1], #4
    5824:	f845 cf04 	str.w	ip, [r5, #4]!
			n -= sizeof(mem_word_t);
    5828:	e7f2      	b.n	5810 <memcpy+0x32>
		*(d_byte++) = *(s_byte++);
    582a:	f811 4b01 	ldrb.w	r4, [r1], #1
    582e:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    5832:	e7dc      	b.n	57ee <memcpy+0x10>

00005834 <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    5834:	4603      	mov	r3, r0
{
    5836:	b570      	push	{r4, r5, r6, lr}
	unsigned char c_byte = (unsigned char)c;
    5838:	b2c9      	uxtb	r1, r1

	while (((uintptr_t)d_byte) & (sizeof(mem_word_t) - 1)) {
    583a:	079c      	lsls	r4, r3, #30
    583c:	d111      	bne.n	5862 <memset+0x2e>
	/* do word-sized initialization as long as possible */

	mem_word_t *d_word = (mem_word_t *)d_byte;
	mem_word_t c_word = (mem_word_t)c_byte;

	c_word |= c_word << 8;
    583e:	ea41 2401 	orr.w	r4, r1, r1, lsl #8
	c_word |= c_word << 16;
    5842:	f022 0603 	bic.w	r6, r2, #3
    5846:	ea44 4504 	orr.w	r5, r4, r4, lsl #16
#if Z_MEM_WORD_T_WIDTH > 32
	c_word |= c_word << 32;
#endif

	while (n >= sizeof(mem_word_t)) {
    584a:	441e      	add	r6, r3
    584c:	0894      	lsrs	r4, r2, #2
    584e:	42b3      	cmp	r3, r6
    5850:	d10d      	bne.n	586e <memset+0x3a>
    5852:	f06f 0503 	mvn.w	r5, #3
    5856:	fb05 2204 	mla	r2, r5, r4, r2
    585a:	441a      	add	r2, r3

	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;

	while (n > 0) {
    585c:	4293      	cmp	r3, r2
    585e:	d109      	bne.n	5874 <memset+0x40>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    5860:	bd70      	pop	{r4, r5, r6, pc}
		if (n == 0) {
    5862:	2a00      	cmp	r2, #0
    5864:	d0fc      	beq.n	5860 <memset+0x2c>
		*(d_byte++) = c_byte;
    5866:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    586a:	3a01      	subs	r2, #1
    586c:	e7e5      	b.n	583a <memset+0x6>
		*(d_word++) = c_word;
    586e:	f843 5b04 	str.w	r5, [r3], #4
		n -= sizeof(mem_word_t);
    5872:	e7ec      	b.n	584e <memset+0x1a>
		*(d_byte++) = c_byte;
    5874:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5878:	e7f0      	b.n	585c <memset+0x28>

0000587a <_stdout_hook_default>:
}
    587a:	f04f 30ff 	mov.w	r0, #4294967295
    587e:	4770      	bx	lr

00005880 <uarte_nrfx_isr_int>:
	return config->uarte_regs;
    5880:	6843      	ldr	r3, [r0, #4]
    5882:	681b      	ldr	r3, [r3, #0]
    return p_reg->INTENSET & mask;
    5884:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    5888:	05d2      	lsls	r2, r2, #23
    588a:	d518      	bpl.n	58be <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    588c:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    5890:	b1aa      	cbz	r2, 58be <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    5892:	f04f 0120 	mov.w	r1, #32
    5896:	f3ef 8211 	mrs	r2, BASEPRI
    589a:	f381 8811 	msr	BASEPRI, r1
    589e:	f3bf 8f6f 	isb	sy
    58a2:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    58a6:	b131      	cbz	r1, 58b6 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    58a8:	2100      	movs	r1, #0
    58aa:	f8c3 1120 	str.w	r1, [r3, #288]	; 0x120
    58ae:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    58b2:	2101      	movs	r1, #1
    58b4:	60d9      	str	r1, [r3, #12]
	__asm__ volatile(
    58b6:	f382 8811 	msr	BASEPRI, r2
    58ba:	f3bf 8f6f 	isb	sy
}
    58be:	4770      	bx	lr

000058c0 <uarte_nrfx_config_get>:
{
    58c0:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
    58c2:	68c2      	ldr	r2, [r0, #12]
    58c4:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    58c8:	e883 0003 	stmia.w	r3, {r0, r1}
}
    58cc:	2000      	movs	r0, #0
    58ce:	4770      	bx	lr

000058d0 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    58d0:	6843      	ldr	r3, [r0, #4]
    58d2:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    58d4:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    58d8:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    58dc:	4770      	bx	lr

000058de <is_tx_ready>:
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    58de:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    58e0:	6813      	ldr	r3, [r2, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    58e2:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    58e6:	b938      	cbnz	r0, 58f8 <is_tx_ready+0x1a>
    58e8:	7992      	ldrb	r2, [r2, #6]
    58ea:	b932      	cbnz	r2, 58fa <is_tx_ready+0x1c>
    58ec:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    58f0:	3800      	subs	r0, #0
    58f2:	bf18      	it	ne
    58f4:	2001      	movne	r0, #1
    58f6:	4770      	bx	lr
    58f8:	2001      	movs	r0, #1
}
    58fa:	4770      	bx	lr

000058fc <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    58fc:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = get_dev_data(dev);
    58fe:	68c2      	ldr	r2, [r0, #12]
	return config->uarte_regs;
    5900:	681b      	ldr	r3, [r3, #0]
    5902:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    5906:	b148      	cbz	r0, 591c <uarte_nrfx_poll_in+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5908:	2000      	movs	r0, #0
	*c = data->rx_data;
    590a:	7b52      	ldrb	r2, [r2, #13]
    590c:	700a      	strb	r2, [r1, #0]
    590e:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    5912:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5916:	2201      	movs	r2, #1
    5918:	601a      	str	r2, [r3, #0]
	return 0;
    591a:	4770      	bx	lr
		return -1;
    591c:	f04f 30ff 	mov.w	r0, #4294967295
}
    5920:	4770      	bx	lr

00005922 <k_sys_fatal_error_handler>:
	ARG_UNUSED(reason);

	LOG_PANIC();

	LOG_ERR("Resetting system");
	sys_arch_reboot(0);
    5922:	2000      	movs	r0, #0
{
    5924:	b508      	push	{r3, lr}
	sys_arch_reboot(0);
    5926:	f7fc fd85 	bl	2434 <sys_arch_reboot>

0000592a <hw_cc3xx_init>:
#include <nrf_cc3xx_platform.h>

#if CONFIG_HW_CC3XX

static int hw_cc3xx_init(const struct device *dev)
{
    592a:	b508      	push	{r3, lr}
	int res;

	__ASSERT_NO_MSG(dev != NULL);

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    592c:	f7fc fa5e 	bl	1dec <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    5930:	f7fc fae0 	bl	1ef4 <nrf_cc3xx_platform_mutex_init>
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
#endif
	return res;
}
    5934:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    5938:	f7fe be0a 	b.w	4550 <nrf_cc3xx_platform_init_no_rng>

0000593c <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    593c:	4700      	bx	r0

0000593e <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    593e:	f000 b8fd 	b.w	5b3c <z_impl_k_busy_wait>

00005942 <nrfx_clock_enable>:
{
    5942:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    5944:	2005      	movs	r0, #5
    5946:	f7fc fb51 	bl	1fec <arch_irq_is_enabled>
    594a:	b920      	cbnz	r0, 5956 <nrfx_clock_enable+0x14>
}
    594c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    5950:	2005      	movs	r0, #5
    5952:	f7fc bb3b 	b.w	1fcc <arch_irq_enable>
    5956:	bd08      	pop	{r3, pc}

00005958 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    5958:	b573      	push	{r0, r1, r4, r5, r6, lr}
    595a:	4605      	mov	r5, r0
    595c:	9101      	str	r1, [sp, #4]
	__asm__ volatile(
    595e:	f04f 0320 	mov.w	r3, #32
    5962:	f3ef 8611 	mrs	r6, BASEPRI
    5966:	f383 8811 	msr	BASEPRI, r3
    596a:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
    596e:	f7fe f9bf 	bl	3cf0 <z_impl_k_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	z_coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    5972:	9901      	ldr	r1, [sp, #4]
    5974:	4604      	mov	r4, r0
    5976:	4628      	mov	r0, r5
    5978:	f7ff ffd3 	bl	5922 <k_sys_fatal_error_handler>
	__asm__ volatile(
    597c:	f386 8811 	msr	BASEPRI, r6
    5980:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    5984:	4620      	mov	r0, r4
#endif /*CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION */
	}

	arch_irq_unlock(key);
	k_thread_abort(thread);
}
    5986:	b002      	add	sp, #8
    5988:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    598c:	f7fc bda6 	b.w	24dc <z_impl_k_thread_abort>

00005990 <z_sys_power_save_idle_exit>:
	z_clock_idle_exit();
    5990:	f7ff be31 	b.w	55f6 <z_clock_idle_exit>

00005994 <k_mem_slab_init>:
{
    5994:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
    5996:	2400      	movs	r4, #0
    5998:	6184      	str	r4, [r0, #24]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    599a:	ea41 0402 	orr.w	r4, r1, r2
    599e:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
    59a2:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->buffer = buffer;
    59a6:	6101      	str	r1, [r0, #16]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    59a8:	d10c      	bne.n	59c4 <k_mem_slab_init+0x30>
	slab->free_list = NULL;
    59aa:	6144      	str	r4, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    59ac:	42a3      	cmp	r3, r4
    59ae:	d103      	bne.n	59b8 <k_mem_slab_init+0x24>
	list->tail = (sys_dnode_t *)list;
    59b0:	e9c0 0000 	strd	r0, r0, [r0]
}
    59b4:	2000      	movs	r0, #0
}
    59b6:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
    59b8:	6945      	ldr	r5, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    59ba:	3401      	adds	r4, #1
		*(char **)p = slab->free_list;
    59bc:	600d      	str	r5, [r1, #0]
		slab->free_list = p;
    59be:	6141      	str	r1, [r0, #20]
		p += slab->block_size;
    59c0:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
    59c2:	e7f3      	b.n	59ac <k_mem_slab_init+0x18>
		return -EINVAL;
    59c4:	f06f 0015 	mvn.w	r0, #21
	return rc;
    59c8:	e7f5      	b.n	59b6 <k_mem_slab_init+0x22>

000059ca <z_impl_k_mutex_init>:
	mutex->owner = NULL;
    59ca:	2300      	movs	r3, #0
    59cc:	e9c0 0000 	strd	r0, r0, [r0]
	mutex->lock_count = 0U;
    59d0:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    59d4:	4618      	mov	r0, r3
    59d6:	4770      	bx	lr

000059d8 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    59d8:	4603      	mov	r3, r0
    59da:	b920      	cbnz	r0, 59e6 <z_reschedule_irqlock+0xe>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    59dc:	f3ef 8205 	mrs	r2, IPSR
    59e0:	b90a      	cbnz	r2, 59e6 <z_reschedule_irqlock+0xe>
    59e2:	f7fc ba9d 	b.w	1f20 <arch_swap>
    59e6:	f383 8811 	msr	BASEPRI, r3
    59ea:	f3bf 8f6f 	isb	sy
}
    59ee:	4770      	bx	lr

000059f0 <z_reschedule_unlocked>:
	__asm__ volatile(
    59f0:	f04f 0320 	mov.w	r3, #32
    59f4:	f3ef 8011 	mrs	r0, BASEPRI
    59f8:	f383 8811 	msr	BASEPRI, r3
    59fc:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    5a00:	f7ff bfea 	b.w	59d8 <z_reschedule_irqlock>

00005a04 <unpend_thread_no_timeout>:
{
    5a04:	4601      	mov	r1, r0
    5a06:	b508      	push	{r3, lr}
	_priq_wait_remove(&pended_on(thread)->waitq, thread);
    5a08:	6880      	ldr	r0, [r0, #8]
    5a0a:	f7fd fe4f 	bl	36ac <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    5a0e:	7b4b      	ldrb	r3, [r1, #13]
    5a10:	f023 0302 	bic.w	r3, r3, #2
    5a14:	734b      	strb	r3, [r1, #13]
	thread->base.pended_on = NULL;
    5a16:	2300      	movs	r3, #0
    5a18:	608b      	str	r3, [r1, #8]
}
    5a1a:	bd08      	pop	{r3, pc}

00005a1c <z_priq_dumb_best>:
	return list->head == list;
    5a1c:	6803      	ldr	r3, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5a1e:	4298      	cmp	r0, r3
    5a20:	d004      	beq.n	5a2c <z_priq_dumb_best+0x10>
	if (n != NULL) {
    5a22:	2b00      	cmp	r3, #0
    5a24:	bf38      	it	cc
    5a26:	2300      	movcc	r3, #0
    5a28:	4618      	mov	r0, r3
    5a2a:	4770      	bx	lr
	struct k_thread *thread = NULL;
    5a2c:	2000      	movs	r0, #0
}
    5a2e:	4770      	bx	lr

00005a30 <z_ready_thread>:
{
    5a30:	b510      	push	{r4, lr}
    5a32:	f04f 0320 	mov.w	r3, #32
    5a36:	f3ef 8411 	mrs	r4, BASEPRI
    5a3a:	f383 8811 	msr	BASEPRI, r3
    5a3e:	f3bf 8f6f 	isb	sy
		ready_thread(thread);
    5a42:	f7fd fe8d 	bl	3760 <ready_thread>
	__asm__ volatile(
    5a46:	f384 8811 	msr	BASEPRI, r4
    5a4a:	f3bf 8f6f 	isb	sy
}
    5a4e:	bd10      	pop	{r4, pc}

00005a50 <z_thread_timeout>:
{
    5a50:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5a52:	4604      	mov	r4, r0
	__asm__ volatile(
    5a54:	f04f 0320 	mov.w	r3, #32
    5a58:	f3ef 8511 	mrs	r5, BASEPRI
    5a5c:	f383 8811 	msr	BASEPRI, r3
    5a60:	f3bf 8f6f 	isb	sy
		if (thread->base.pended_on != NULL) {
    5a64:	f854 3c10 	ldr.w	r3, [r4, #-16]
		struct k_thread *thread = CONTAINER_OF(timeout,
    5a68:	3818      	subs	r0, #24
		if (thread->base.pended_on != NULL) {
    5a6a:	b11b      	cbz	r3, 5a74 <z_thread_timeout+0x24>
			unpend_thread_no_timeout(thread);
    5a6c:	9001      	str	r0, [sp, #4]
    5a6e:	f7ff ffc9 	bl	5a04 <unpend_thread_no_timeout>
    5a72:	9801      	ldr	r0, [sp, #4]
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    5a74:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
    5a78:	f023 0314 	bic.w	r3, r3, #20
    5a7c:	f804 3c0b 	strb.w	r3, [r4, #-11]
		ready_thread(thread);
    5a80:	f7fd fe6e 	bl	3760 <ready_thread>
	__asm__ volatile(
    5a84:	f385 8811 	msr	BASEPRI, r5
    5a88:	f3bf 8f6f 	isb	sy
}
    5a8c:	b003      	add	sp, #12
    5a8e:	bd30      	pop	{r4, r5, pc}

00005a90 <add_to_waitq_locked>:
{
    5a90:	b538      	push	{r3, r4, r5, lr}
    5a92:	4604      	mov	r4, r0
    5a94:	460d      	mov	r5, r1
	unready_thread(thread);
    5a96:	f7fd ffeb 	bl	3a70 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    5a9a:	7b63      	ldrb	r3, [r4, #13]
    5a9c:	f043 0302 	orr.w	r3, r3, #2
    5aa0:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    5aa2:	b1c5      	cbz	r5, 5ad6 <add_to_waitq_locked+0x46>
	return list->head == list;
    5aa4:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    5aa6:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5aa8:	429d      	cmp	r5, r3
    5aaa:	bf08      	it	eq
    5aac:	2300      	moveq	r3, #0
    5aae:	2b00      	cmp	r3, #0
    5ab0:	bf38      	it	cc
    5ab2:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5ab4:	b183      	cbz	r3, 5ad8 <add_to_waitq_locked+0x48>
	if (thread_1->base.prio < thread_2->base.prio) {
    5ab6:	f994 100e 	ldrsb.w	r1, [r4, #14]
    5aba:	f993 200e 	ldrsb.w	r2, [r3, #14]
    5abe:	4291      	cmp	r1, r2
    5ac0:	db04      	blt.n	5acc <add_to_waitq_locked+0x3c>
	return (node == list->tail) ? NULL : node->next;
    5ac2:	686a      	ldr	r2, [r5, #4]
    5ac4:	429a      	cmp	r2, r3
    5ac6:	d007      	beq.n	5ad8 <add_to_waitq_locked+0x48>
    5ac8:	681b      	ldr	r3, [r3, #0]
    5aca:	e7f3      	b.n	5ab4 <add_to_waitq_locked+0x24>
	node->prev = successor->prev;
    5acc:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    5ace:	e9c4 3200 	strd	r3, r2, [r4]
	successor->prev->next = node;
    5ad2:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    5ad4:	605c      	str	r4, [r3, #4]
}
    5ad6:	bd38      	pop	{r3, r4, r5, pc}
	node->prev = list->tail;
    5ad8:	686b      	ldr	r3, [r5, #4]
	node->next = list;
    5ada:	6025      	str	r5, [r4, #0]
	node->prev = list->tail;
    5adc:	6063      	str	r3, [r4, #4]
	list->tail->next = node;
    5ade:	686b      	ldr	r3, [r5, #4]
    5ae0:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5ae2:	606c      	str	r4, [r5, #4]
    5ae4:	e7f7      	b.n	5ad6 <add_to_waitq_locked+0x46>

00005ae6 <z_unpend_first_thread>:
{
    5ae6:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    5ae8:	f04f 0320 	mov.w	r3, #32
    5aec:	f3ef 8211 	mrs	r2, BASEPRI
    5af0:	f383 8811 	msr	BASEPRI, r3
    5af4:	f3bf 8f6f 	isb	sy
		ret = _priq_wait_best(&wait_q->waitq);
    5af8:	f7ff ff90 	bl	5a1c <z_priq_dumb_best>
    5afc:	4604      	mov	r4, r0
	__asm__ volatile(
    5afe:	f382 8811 	msr	BASEPRI, r2
    5b02:	f3bf 8f6f 	isb	sy

static inline struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q)
{
	struct k_thread *thread = z_find_first_thread_to_unpend(wait_q, NULL);

	if (thread != NULL) {
    5b06:	b188      	cbz	r0, 5b2c <z_unpend_first_thread+0x46>
	__asm__ volatile(
    5b08:	f04f 0320 	mov.w	r3, #32
    5b0c:	f3ef 8511 	mrs	r5, BASEPRI
    5b10:	f383 8811 	msr	BASEPRI, r3
    5b14:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
    5b18:	f7ff ff74 	bl	5a04 <unpend_thread_no_timeout>
	__asm__ volatile(
    5b1c:	f385 8811 	msr	BASEPRI, r5
    5b20:	f3bf 8f6f 	isb	sy
	return z_abort_timeout(&thread->base.timeout);
    5b24:	f104 0018 	add.w	r0, r4, #24
    5b28:	f000 f80c 	bl	5b44 <z_abort_timeout>
}
    5b2c:	4620      	mov	r0, r4
    5b2e:	bd38      	pop	{r3, r4, r5, pc}

00005b30 <k_is_in_isr>:
    5b30:	f3ef 8005 	mrs	r0, IPSR
}
    5b34:	3800      	subs	r0, #0
    5b36:	bf18      	it	ne
    5b38:	2001      	movne	r0, #1
    5b3a:	4770      	bx	lr

00005b3c <z_impl_k_busy_wait>:
	if (usec_to_wait == 0) {
    5b3c:	b108      	cbz	r0, 5b42 <z_impl_k_busy_wait+0x6>
	arch_busy_wait(usec_to_wait);
    5b3e:	f7fb bc5b 	b.w	13f8 <arch_busy_wait>
}
    5b42:	4770      	bx	lr

00005b44 <z_abort_timeout>:
{
    5b44:	b510      	push	{r4, lr}
	__asm__ volatile(
    5b46:	f04f 0220 	mov.w	r2, #32
    5b4a:	f3ef 8411 	mrs	r4, BASEPRI
    5b4e:	f382 8811 	msr	BASEPRI, r2
    5b52:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    5b56:	6803      	ldr	r3, [r0, #0]
    5b58:	b13b      	cbz	r3, 5b6a <z_abort_timeout+0x26>
			remove_timeout(to);
    5b5a:	f7fe f9c5 	bl	3ee8 <remove_timeout>
			ret = 0;
    5b5e:	2000      	movs	r0, #0
	__asm__ volatile(
    5b60:	f384 8811 	msr	BASEPRI, r4
    5b64:	f3bf 8f6f 	isb	sy
}
    5b68:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    5b6a:	f06f 0015 	mvn.w	r0, #21
    5b6e:	e7f7      	b.n	5b60 <z_abort_timeout+0x1c>

00005b70 <z_get_next_timeout_expiry>:
{
    5b70:	b510      	push	{r4, lr}
	__asm__ volatile(
    5b72:	f04f 0320 	mov.w	r3, #32
    5b76:	f3ef 8411 	mrs	r4, BASEPRI
    5b7a:	f383 8811 	msr	BASEPRI, r3
    5b7e:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    5b82:	f7fe f9cb 	bl	3f1c <next_timeout>
	__asm__ volatile(
    5b86:	f384 8811 	msr	BASEPRI, r4
    5b8a:	f3bf 8f6f 	isb	sy
}
    5b8e:	bd10      	pop	{r4, pc}

00005b90 <z_set_timeout_expiry>:
{
    5b90:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5b92:	4604      	mov	r4, r0
    5b94:	9101      	str	r1, [sp, #4]
	__asm__ volatile(
    5b96:	f04f 0320 	mov.w	r3, #32
    5b9a:	f3ef 8511 	mrs	r5, BASEPRI
    5b9e:	f383 8811 	msr	BASEPRI, r3
    5ba2:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    5ba6:	f7fe f9b9 	bl	3f1c <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    5baa:	2801      	cmp	r0, #1
    5bac:	dd05      	ble.n	5bba <z_set_timeout_expiry+0x2a>
    5bae:	42a0      	cmp	r0, r4
    5bb0:	9901      	ldr	r1, [sp, #4]
    5bb2:	dd02      	ble.n	5bba <z_set_timeout_expiry+0x2a>
			z_clock_set_timeout(ticks, is_idle);
    5bb4:	4620      	mov	r0, r4
    5bb6:	f7fb fe4d 	bl	1854 <z_clock_set_timeout>
	__asm__ volatile(
    5bba:	f385 8811 	msr	BASEPRI, r5
    5bbe:	f3bf 8f6f 	isb	sy
}
    5bc2:	b003      	add	sp, #12
    5bc4:	bd30      	pop	{r4, r5, pc}

00005bc6 <z_tick_get_32>:

uint32_t z_tick_get_32(void)
{
    5bc6:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)z_tick_get();
    5bc8:	f7fe fac6 	bl	4158 <z_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    5bcc:	bd08      	pop	{r3, pc}

00005bce <k_heap_init>:
{
    5bce:	b410      	push	{r4}
	sys_dlist_init(&w->waitq);
    5bd0:	f100 040c 	add.w	r4, r0, #12
	list->tail = (sys_dnode_t *)list;
    5bd4:	e9c0 4403 	strd	r4, r4, [r0, #12]
}
    5bd8:	f85d 4b04 	ldr.w	r4, [sp], #4
	sys_heap_init(&h->heap, mem, bytes);
    5bdc:	f7ff bb73 	b.w	52c6 <sys_heap_init>

00005be0 <_OffsetAbsSyms>:
#include "offsets_aarch64.c"
#else
#include "offsets_aarch32.c"
#endif

GEN_ABS_SYM_END
    5be0:	4770      	bx	lr

Disassembly of section .gnu.sgstubs:

000066a0 <spm_firmware_info_nse-0x1940>:
	...

00007fe0 <spm_firmware_info_nse>:
    7fe0:	e97f e97f 	sg
    7fe4:	f7f9 be98 	b.w	1d18 <__acle_se_spm_firmware_info_nse>

00007fe8 <spm_request_random_number_nse>:
    7fe8:	e97f e97f 	sg
    7fec:	f7fd bb0f 	b.w	560e <__acle_se_spm_request_random_number_nse>

00007ff0 <spm_request_read_nse>:
    7ff0:	e97f e97f 	sg
    7ff4:	f7f9 be38 	b.w	1c68 <__acle_se_spm_request_read_nse>
	...
