// ----------------------------------------
//  PWM_PPI_INIT (only use RX)
// ----------------------------------------
void pwm_ppi_init( void )
{
    uint32_t rfrx_evt_addr;
    uint32_t pwm_task_addr;
    nrf_ppi_channel_t pwm_ppi_channel0;

//  PPI
    nrf_drv_ppi_init();

    rfrx_evt_addr = nrf_radio_event_address_get(NRF_RADIO_EVENT_PAYLOAD);
    pwm_task_addr = nrfx_pwm_task_address_get(&PWM_0,NRF_PWM_TASK_SEQSTART1);

    nrf_drv_ppi_channel_alloc(&pwm_ppi_channel0);
    nrf_drv_ppi_channel_assign(pwm_ppi_channel0, rfrx_evt_addr, pwm_task_addr);
    nrf_drv_ppi_channel_enable(pwm_ppi_channel0);

    return;
}




// ----------------------------------------
//  GPIOE_PIN become to make SPI (only use RX)
// ----------------------------------------
void ppi_init(void)
{
    uint32_t gpio_evt1_addr, gpio_evt2_addr, spi_evt_addr;
    uint32_t spi_task_addr, spiss_task_addr1, spiss_task_addr2;
    
    uint32_t rfrx_evt_addr, gpio_evt_addr, timer_evt_addr;
    uint32_t gpioh_task_addr, gpiol_task_addr;

    nrf_drv_gpiote_init();
    nrf_drv_ppi_init();

    nrf_gpio_cfg_output(SPI_CONV);
    nrf_gpio_pin_set(SPI_CONV);
    nrf_drv_gpiote_out_config_t spiss_gpiote_config = GPIOTE_CONFIG_OUT_TASK_LOW;
    nrf_drv_gpiote_out_init(SPI_CONV, &spiss_gpiote_config); 


//  ----------- Initialize of GPIO's output & input -----------
//  The timing of GPIOE's output.
//  GPIOE_POUT is first timing. Other timing is by PWM(9 pulses).
//  ------------------------------------------------------------
    nrf_drv_gpiote_out_config_t gpiote_config = NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(false);
    nrf_drv_gpiote_out_init(GPIOE_POUT, &gpiote_config);


//  ------------------------------------------------------------
//  Initialize of GOIO's input
//  GPIO_PIN11 & GPIO_PIN12 are the timing of spi's action.
//  Config of INPUT GPIO_PIN11 & GPIO_PIN12
//  ------------------------------------------------------------
    nrf_drv_gpiote_in_config_t gpiote_spi_config1 = GPIOTE_CONFIG_IN_SENSE_LOTOHI(true);    //CAUTION!! false
    nrf_drv_gpiote_in_init(GPIO_PIN11,&gpiote_spi_config1,gpioe_event_handler1);
    nrf_drv_gpiote_in_init(GPIO_PIN12,&gpiote_spi_config1,gpioe_event_handler2);


//  ----------- Configuration of PPI ----------
//  PPI for GPIOE_POUT (The first timing)

//  GPIOE_POUT (L to H)
    rfrx_evt_addr = nrf_radio_event_address_get(NRF_RADIO_EVENT_PAYLOAD);                   //triger by RX
    gpioh_task_addr=nrf_drv_gpiote_out_task_addr_get(GPIOE_POUT);

    nrf_drv_ppi_channel_alloc(&gpio_ppi_channel0);
    nrf_drv_ppi_channel_assign(gpio_ppi_channel0, rfrx_evt_addr, gpioh_task_addr);
    nrf_drv_ppi_channel_enable(gpio_ppi_channel0);


//  PPI for SPI
    gpio_evt1_addr = nrf_drv_gpiote_in_event_addr_get (GPIO_PIN11);
    gpio_evt2_addr = nrf_drv_gpiote_in_event_addr_get (GPIO_PIN12);
    spi_task_addr=nrf_drv_spi_start_task_get(&SPI_0);

    nrf_drv_ppi_channel_alloc(&spi_ppi_channel1);
    nrf_drv_ppi_channel_assign(spi_ppi_channel1, gpio_evt1_addr, spi_task_addr);
    nrf_drv_ppi_channel_alloc(&spi_ppi_channel2);
    nrf_drv_ppi_channel_assign(spi_ppi_channel2, gpio_evt2_addr, spi_task_addr);

    nrf_drv_ppi_channel_enable(spi_ppi_channel1);
    nrf_drv_ppi_channel_enable(spi_ppi_channel2);


//  GPIOE_POUT (H to L)
    gpiol_task_addr = nrf_drv_gpiote_clr_task_addr_get(GPIOE_POUT);

    nrf_drv_ppi_channel_alloc(&gpio_ppi_channel1);
    nrf_drv_ppi_channel_assign(gpio_ppi_channel1, gpio_evt2_addr, gpiol_task_addr);
    nrf_drv_ppi_channel_enable(gpio_ppi_channel1);

    nrf_drv_gpiote_out_task_enable(GPIOE_POUT);

//    nrfx_gpiote_in_event_enable(GPIO_PIN11,false);    2022/05/26
//    nrfx_gpiote_in_event_enable(GPIO_PIN12,false);
    nrfx_gpiote_in_event_enable(GPIO_PIN11,true);
    nrfx_gpiote_in_event_enable(GPIO_PIN12,true);


//  PPI for SPI_CONV 
//  (H to L)
    spiss_task_addr1=nrf_drv_gpiote_clr_task_addr_get(SPI_CONV);
    nrf_drv_ppi_channel_alloc(&spiss_channl1);
    nrf_drv_ppi_channel_assign(spiss_channl1, gpio_evt1_addr, spiss_task_addr1);
    nrf_drv_ppi_channel_enable(spiss_channl1);

    nrf_drv_ppi_channel_alloc(&spiss_channl2);
    nrf_drv_ppi_channel_assign(spiss_channl2, gpio_evt2_addr, spiss_task_addr1);
    nrf_drv_ppi_channel_enable(spiss_channl2);

//  (L to H)
    spiss_task_addr2=nrf_drv_gpiote_set_task_addr_get(SPI_CONV);
    spi_evt_addr=nrf_drv_spi_end_event_get(&SPI_0);
    nrf_drv_ppi_channel_alloc(&spiss_channl3);
    nrf_drv_ppi_channel_assign(spiss_channl3, spi_evt_addr, spiss_task_addr2);
    nrf_drv_ppi_channel_enable(spiss_channl3);

    nrf_drv_gpiote_out_task_enable(SPI_CONV);

    return;
}