nrf52832 SPIM Driver "Missing" MISO Bits

RE: nrf52832 SPIM Driver "Missing" MISO Bits

dlewis — Mon, 12 Jun 2023 13:56:56 GMT

Hi, I should have clarified more. In the code samples I posted in the comments, I had currently been using SPI MODE 3. The pictures taken in the original post were using MODE 0. We have been going back and forth with the manufacturer of the AFE for some time now, their documentation and reps have been giving us incorrect information. We currently believe that SPI MODE 3 is the correct mode to use with their chip. Since switching to MODE 3, we have not seen the missing bits issue, which is good. I would still be concerned about the missing bits when using SPI MODE 0 though, because even if it's the wrong mode, the micro should still be reading the signal shown on the scope correctly, which it was not.

I did try the manual pin configurations to increase the drive strength and that did not seem to have an impact on performance.

RE: nrf52832 SPIM Driver "Missing" MISO Bits

hmolesworth — Thu, 08 Jun 2023 18:01:45 GMT

Yes, that looks good and just repeat for both MOSI and CS. I would also enable the pull-up on the MISO input, but that may be the default already and is not the issue you are reporting. As an aside, in case you ever disable the SPI for (say) extended low-power sleep set the default output state of SCK, MOSI and CS to '1' before spi_init() unless you use a port pin to power down the ADS in which case they should be '0' or changed to inputs to avoid phantom powering the ADS/AFE in such an extended sleep.

Edit: I see you are using Mode 3; I thought the FAE said use Mode 0? In passing, other manufacturers such as TI AFEs can use Mode 1 or Mode 3, which implies Mode 0 would not be interchangeable with Mode 3.

RE: nrf52832 SPIM Driver "Missing" MISO Bits

dlewis — Wed, 07 Jun 2023 17:52:23 GMT

Thanks for the reply. I have not tried that yet. I found the use of nrf_gpio_cfg() in nrfx_spim.c and copied it to right after the spim init. Does this look correct? And would I just repeat with MOSI and CS with all of the same parameters besides the pin #?

RE: nrf52832 SPIM Driver "Missing" MISO Bits

hmolesworth — Wed, 07 Jun 2023 16:40:16 GMT

You may have already tried this, but if not it will improve reliability of reception. Increase the nRF52 drive strength to CS, SCK and MOSI output drivers to H0H1 instead of the default S0S1. This can be done after the SPI init nrfx_spim_init() if you are using Nordic libraries and want to avoid editing those.

H0H1 on the clock pin SCK in particular can avoid incorrect data reception on MISO and only a very high bandwidth 'scope will show the jitter on the AFE clock in pin transition which can cause bit corruption.

RE: nrf52832 SPIM Driver "Missing" MISO Bits

dlewis — Wed, 07 Jun 2023 14:31:51 GMT

Also, after talking to reps from analog devices, the chip response in the posted scope screenshot is supposed to be 0x88 not 0x89 as I mentioned in the post. The last bit looks visually to be very close to being HIGH during the last rising edge clock cycle, but it is supposed to go HIGH immediately after the last clock cycle because the MISO pin on the chip is dual purpose pin with a sample rdy interrupt function.

RE: nrf52832 SPIM Driver "Missing" MISO Bits

dlewis — Wed, 07 Jun 2023 13:30:39 GMT

Attached are 3 files. app.c is where the SPI init and ad7785 init functions are called. ad7785_init is where the SPI transactions in question are called. spi_driver.c is where nrfx_spim_xfer() is called.

devzone.nordicsemi.com/.../app.c devzone.nordicsemi.com/.../ad7785.c devzone.nordicsemi.com/.../spi_5F00_driver.c