https://devzone.nordicsemi.com/f/nordic-q-a/10071/spi-slave-data-offsetI&#39;m using the 0.9.2 SDK SPI slave example to connect to a SPI master (Atmel SAM4S). When I initiate a SPI transfer from the master side I can see that all the data arrives correctly on the nrf52 side (ABCDEFGHIJKLMNOP) every time. However, on the masteren-USTelligent Community 13Thu, 05 Nov 2015 03:14:52 GMThttps://devzone.nordicsemi.com/thread/37340?ContentTypeID=1Thu, 05 Nov 2015 03:14:52 GMT137ad170-7792-4731-bb38-c0d22fbe4515:8877e773-5c31-47f5-91c4-5fd22f8373fcBernd (nvisionary)<p>I solved the issue by looking at it on the logic analyzer. Apparently there were two issues:</p> <ul> <li>On the master side I didn&#39;t deselect the chip select before reading the SPI RX data which apparently resulted in extra frames sent on the SPI bus. Therefore the shift.</li> <li>I still saw 0xAA&#39;s for the first Byte in every transaction. Turns out that the timing was off froCS going low to the first clock toggle. Once the delay was large enough all the data is correctly transmitted to both sides. Closing.</li> </ul><div style="clear:both;"></div>