MISO Pin not working properly in SPIS mode

RE: MISO Pin not working properly in SPIS mode

AhmedPs19 — Tue, 09 Sep 2025 10:31:25 GMT

The issue was coming from the node capacitance on the PCB trace which was not allowing MISO pin to function properly on nRF53.

RE: MISO Pin not working properly in SPIS mode

Naeem Maroof — Wed, 09 Aug 2023 11:44:44 GMT

Is it reproducible on the DK?

You may look at the PIN_CNF register for both the pins in consideration and see if there are any differences.

Also, on the custom board vs the DK.

RE: MISO Pin not working properly in SPIS mode

AhmedPs19 — Mon, 07 Aug 2023 14:56:13 GMT

[quote userid="119245" url="~/f/nordic-q-a/102501/miso-pin-not-working-properly-in-spis-mode/440166"]specification[/quote]

I have tried it in both ways , i.e in H0H1 and S0S1 . Nothing worked on P0.19.

Regards,

Ahmed

RE: MISO Pin not working properly in SPIS mode

Naeem Maroof — Mon, 07 Aug 2023 14:51:05 GMT

Hello Ahmed,

Good to know that you have made progress and somehow the issue is resolved.

I can see that you have set MISO pin (Pin 0.19) configuration as H0H1 drive.

spis_config.miso_drive = NRF_GPIO_PIN_H0H1 ;

From the product specification, we see that P0.13 - P0.18 should be used for H0H1 drive configuration from the Pin assignment chapter of nrf5340 product specification.

BR, Naeem

RE: MISO Pin not working properly in SPIS mode

AhmedPs19 — Mon, 07 Aug 2023 14:34:39 GMT

Hello Naeem,

I have changed the MISO pin from P0.19 to P0.13 and the issue is resolved but I want to further investigate what could be cause of this issue. I have checked the bare boards , there is no hardware issue in the custom boards.

Best Regards,

Ahmed

RE: MISO Pin not working properly in SPIS mode

AhmedPs19 — Thu, 03 Aug 2023 15:56:45 GMT

Hello Naeem,

Following are the contents of the conf file

CONFIG_BOARD_ENABLE_DCDC_APP=n
CONFIG_BOARD_ENABLE_DCDC_NET=n
CONFIG_BOARD_ENABLE_DCDC_HV=n
CONFIG_LOG=n
CONFIG_NRFX_SPIS1=y
CONFIG_BOOT_BANNER=n
CONFIG_ASSERT=y
CONFIG_SPEED_OPTIMIZATIONS=n
CONFIG_ZERO_LATENCY_IRQS=y
CONFIG_BUILD_WITH_TFM=n

CONFIG_PRINTK=n

CONFIG_BOARD_ENABLE_CPUNET=y
CONFIG_MBOX_NRFX_IPC=y
CONFIG_IPC_SERVICE=y
CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
CONFIG_MBOX=y

CONFIG_LOG=n
CONFIG_ASSERT=y

--------------------------------------------------------------------------

Following are the contents of the overlay file

&spi1 {
    status = "okay";
    compatible = "nordic,nrf-spis";
    def-char = <0xFF>;
};

/{
   chosen {
       /delete-property/ zephyr,ipc_shm;
   };

   reserved-memory {
       /delete-node/ memory@20070000;

       sram_rx: memory@20070000 {
           reg = <0x20070000 0x0800>;
       };

       sram_tx: memory@20078000 {
           reg = <0x20078000 0x0800>;
       };
   };

   ipc {
       /delete-node/ ipc0;

       ipc0: ipc0 {
           compatible = "zephyr,ipc-icmsg";
           tx-region = <&sram_tx>;
           rx-region = <&sram_rx>;
           mboxes = <&mbox 0>, <&mbox 1>;
           mbox-names = "rx", "tx";
           status = "okay";
       };
   };
};

----------------------------------------------------------------------------------------------------------------------------------

code spinet from main.c file

#define SPIS_INST_IDX 1

void * p_context = "Some context";

nrfx_spis_t spis = NRFX_SPIS_INSTANCE(SPIS_INST_IDX);

    nrfx_spis_config_t spis_config = NRFX_SPIS_DEFAULT_CONFIG(APP_SPIS_SCK_PIN,
                                                              APP_SPIS_MOSI_PIN,
                                                              APP_SPIS_MISO_PIN,
                                                              APP_SPIS_CS_PIN);
//   spis_config.miso_drive= NRF_GPIO_PIN_H0H1;                                              
 spis_config.irq_priority = 2 ;
 spis_config.miso_drive = NRF_GPIO_PIN_H0H1 ;
spis_config.skip_gpio_cfg = 0 ;
spis_config.skip_psel_cfg = 0 ;
NRF_SPIS1->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
status = nrfx_spis_init(&spis, &spis_config, spis_handler, p_context);
     NRFX_ASSERT(status == NRFX_SUCCESS);


#define SPIS_INST         NRFX_CONCAT_2(NRF_SPIS, SPIS_INST_IDX)
#define SPIS_INST_HANDLER NRFX_CONCAT_3(nrfx_spis_, SPIS_INST_IDX, _irq_handler)
IRQ_DIRECT_CONNECT(NRFX_IRQ_NUMBER_GET(SPIS_INST), IRQ_PRIO_LOWEST, SPIS_INST_HANDLER, 0)

Kind Regards,

Ahmed

RE: MISO Pin not working properly in SPIS mode

Naeem Maroof — Thu, 03 Aug 2023 15:33:31 GMT

Hello,

Thank you for contacting DevZone at NordicSemi.

As the problem does not occur with the DK, I doubt there could be problem with your board.

How many custom boards do you have? All are showing the same problem?

How does your overlay look like?

Maybe you can revisit your board, and check everything including device-tree and the connections are correct.

BR,

Naeem

RE: MISO Pin not working properly in SPIS mode

AhmedPs19 — Thu, 03 Aug 2023 13:57:34 GMT

One thing I would like to add is that I have confirmed that NRF5340 is sampling MOSI data correctly with the help of breakpoints and Segger Jlink. SPIS registers are correctly setting but due to some reason MISO pin is not outputting the loaded buffer , it just remains low throughout the whole transaction.

I kindly request your advice on this matter, as we are pressed for time. A quick response would be greatly appreciated.

Kind Regards,

Ahmed