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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Should nRF9160 be powered during SWD programming?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/102854/should-nrf9160-be-powered-during-swd-programming</link><description>On our custom board with the nRF9160, we are supplying different voltages to VDD (from a single-cell Lipo) and to VDD_GPIO (fixed 1.8V). We plan to use an nRF9160DK as the programmer. 
 During programming, should both VDD and VDD_GPIO be supplied? And</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 15 Aug 2023 08:38:05 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/102854/should-nrf9160-be-powered-during-swd-programming" /><item><title>RE: Should nRF9160 be powered during SWD programming?</title><link>https://devzone.nordicsemi.com/thread/441312?ContentTypeID=1</link><pubDate>Tue, 15 Aug 2023 08:38:05 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fc81c106-19ca-414e-bbac-1d41553dfd8f</guid><dc:creator>allard.p</dc:creator><description>&lt;p&gt;The VDD pin provides the reference voltage for the I/O of the programmer. This makes the JLink compatible with 1V8/3V3/5V targets.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>