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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Reduce the time delay between each SPIM transfer</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/103217/reduce-the-time-delay-between-each-spim-transfer</link><description>Hello Support team, 
 I am working with SPIM3 - 16MHz. 
 what I done is setup the SPI function then call it in the while loop with different int reg_addr. 
 nrfx_spim_xfer_desc_t xfer_desc = NRFX_SPIM_XFER_TRX(spi_tx_buf, 4, spi_rx_buf, 4); 
 int LIS3DSH_read_reg</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 30 Aug 2023 09:02:00 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/103217/reduce-the-time-delay-between-each-spim-transfer" /><item><title>RE: Reduce the time delay between each SPIM transfer</title><link>https://devzone.nordicsemi.com/thread/443673?ContentTypeID=1</link><pubDate>Wed, 30 Aug 2023 09:02:00 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:651527f2-ec44-4d41-891c-19d3918771b6</guid><dc:creator>MinhDuc</dc:creator><description>&lt;p&gt;Thank you Susheel. Now I understand the difference between lib/driver and&amp;nbsp;&lt;span&gt;direct access of the peripheral register.&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;I write SPIM again with fully&amp;nbsp;direct access of the peripheral register. The result looks so great.&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Best,&amp;nbsp;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Reduce the time delay between each SPIM transfer</title><link>https://devzone.nordicsemi.com/thread/443640?ContentTypeID=1</link><pubDate>Wed, 30 Aug 2023 05:58:32 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4e928091-72f3-4065-8e76-d941f9c322eb</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;I do not think that the application is supposed to write to EVENTS_XXX.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;You are using the SPI libs and drivers that we provide and so, I do not suggest to experiment anything with the SHORTS while using the lib/driver API. This might confuse them.&lt;/p&gt;
&lt;p&gt;If you want to use shorts, then it is best to handle the whole transaction and events through direct access of the registers. I strongly suggest you not to mix driver/library API use with direct access of the peripheral register.&lt;/p&gt;
&lt;p&gt;Have you tried to figure out where the bottleneck is when using the&amp;nbsp;&lt;span&gt;nrfx_spim_xfer? Have you tried using the Segger Systemview as I recommended to see which contexts are running between your SPI transfers?&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Reduce the time delay between each SPIM transfer</title><link>https://devzone.nordicsemi.com/thread/443631?ContentTypeID=1</link><pubDate>Wed, 30 Aug 2023 00:59:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9abd99c5-cdcf-4cf8-9e28-c80d517b53d4</guid><dc:creator>MinhDuc</dc:creator><description>&lt;p&gt;Hello Susheel.&lt;/p&gt;
&lt;p&gt;I have play around register for SPIM and I reach 3us interrupt between each SPI transfer.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I followed the sugggestion&amp;nbsp;of Haakonsh from the similar topic.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;img style="height:69px;max-height:69px;max-width:469px;" height="59" src="https://devzone.nordicsemi.com/resized-image/__size/938x138/__key/communityserver-discussions-components-files/4/pastedimage1693356905413v2.png" width="468" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;What I have done is call&amp;nbsp;&lt;span&gt;TASKS_START then&amp;nbsp;EVENTS_END then update the content of spi_tx_buf then call&amp;nbsp;&amp;nbsp;TASKS_START again...&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;I realize that the main delay come from everytime I call nrfx_spim_xfer().&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;nrfx_spim_xfer(&amp;amp;spi, &amp;amp;xfer_desc_rd, flags);&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;NRF_SPIM3-&amp;gt;TASKS_START = 1;&lt;br /&gt; NRF_SPIM3-&amp;gt;EVENTS_END = 1;&lt;br /&gt; spi_tx_buf[1] = false &amp;lt;&amp;lt; 7 | false &amp;lt;&amp;lt; 6 | channel_begin+1;&lt;br /&gt; nrfx_spim_xfer(&amp;amp;spi, &amp;amp;xfer_desc_rd, flags);&lt;br /&gt; NRF_SPIM3-&amp;gt;TASKS_START = 1;&lt;br /&gt; NRF_SPIM3-&amp;gt;EVENTS_END = 1;&lt;/p&gt;
&lt;p&gt;.....&lt;/p&gt;
&lt;p&gt;Please kindly explain the suggestion from&amp;nbsp;&lt;span&gt;Haakonsh above. What should I do with SHORTS?&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Best,&amp;nbsp;&amp;nbsp;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Reduce the time delay between each SPIM transfer</title><link>https://devzone.nordicsemi.com/thread/443335?ContentTypeID=1</link><pubDate>Mon, 28 Aug 2023 10:46:43 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3111f555-90f0-49b2-a7ff-ad823971c486</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;I would suggest you to run &lt;a href="https://www.google.com/search?q=segger+systemview"&gt;Segger SystemView&lt;/a&gt;&amp;nbsp;and get an overview on all the contexts you are running to see what that 8us time is spent on. If this is another peripheral interrupt context or if this is still in the SPI peripheral context. Without knowing where that 8uS are spent, it is hard to optimize it.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>