nRF52 maximum throughput of EasyDMA on PWM device

RE: nRF52 maximum throughput of EasyDMA on PWM device

ovrebekk — Mon, 23 Nov 2015 15:06:54 GMT

As mentioned most of the peripherals are clocked at 16MHz, to reduce power consumption and to make the peripheral behavior aligned with the nRF51. The same goes for the peripheral bus.

Feel free to accept the answer if you are happy with it :)

RE: nRF52 maximum throughput of EasyDMA on PWM device

puz_md — Fri, 20 Nov 2015 19:13:28 GMT

I just saw it in the block diagram.. thanks.

RE: nRF52 maximum throughput of EasyDMA on PWM device

Eric Stutzenberger — Fri, 20 Nov 2015 18:37:48 GMT

The APB Bus on the nRF52 is running at 16 MHz. So, even though the CPU core is running at 64 MHz, the APB peripheral clocks are still limited to 16 MHz. Check out the nRF52 Performance information here: infocenter.nordicsemi.com/.../performance.html

RE: nRF52 maximum throughput of EasyDMA on PWM device

puz_md — Fri, 20 Nov 2015 13:18:15 GMT

Hi Torbjørn, thanks for this high quality info! This really helps a lot! Just one question: You mention one EasyDMA transfer per 2 16MHz clock cycles. Shouldn't it be per 2 64MHz cycles on the nRF52?

RE: nRF52 maximum throughput of EasyDMA on PWM device

ovrebekk — Fri, 20 Nov 2015 12:50:38 GMT

You can run one EasyDMA transfer per 2 16MHz clock cycles (every 125ns) maximum for each block of the RAM. The nRF52832 has 8 RAM blocks, so in theory you could run 8 EasyDMA transfers per 125ns if each transfer goes to its own RAM block.
Yes, the PWM updates 2 compare values at once to utilize the 32-bit capacity of the EasyDMA.
Higher priority devices will delay lower priority devices, but unless the higher priority device accesses the RAM 100% of the time there will interleaving naturally.
If you assign one of the 8 RAM blocks to PWM exclusively there will be no impact on the system. If you put everything on the same block then lower priority channels will be delayed when there is a lot of BLE activity. In your case this means the PWM update would be pulled out to give priority to the radio, encryption modules and CPU. If the PWM doesn't get the update in time it will just replay the previous duty cycle, so there are no glitches, just a delayed update.
The PWM register are double buffered, yes. As soon as it has loaded the current duty cycle it will request the next value, to make sure you have the entire interval time (1us) to get the new data.

Best regards
Torbjørn