RE: I2C how to check device readiness?

ovrebekk — Sat, 16 Sep 2023 08:14:13 GMT

Great to hear you found the problem 🙂

I will consider the case resolved then.

Best regards
Torbjørn

RE: I2C how to check device readiness?

MrHarmonSr — Fri, 15 Sep 2023 15:22:06 GMT

I found that using the twi callback events I would get address NACK events, indicating the device was not ready.
I was able to use this t retry the operation.
My real problem was the address byte order. These needed to be swapped to be in the MSB first format required by the 24c64 product. I now have working firmware.

RE: I2C how to check device readiness?

ovrebekk — Wed, 13 Sep 2023 13:58:17 GMT

You can find the 24c64 datasheet here. It is correct that it has a page size of 32 bytes, meaning you can only read or write 32 bytes in each transaction.

The 24c512 for comparison has 128 byte pages, and will allow longer transactions.

[quote user=""]The code comment says " * @attention If you wish to communicate with real EEPROM memory chip, check its readiness
* after writing the data."[/quote]

Write and erase operations are generally slow for flash memory devices, and after performing one of these operations you need to check the status of the device before issuing more commands.

Many flash devices allow you to read out a status register, which indicates whether or not the device is busy executing a write or erase.

Apparently the 24C series don't have any status registers to read, but I found the following statement in the datasheet:

BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).

In other words you should get a NACK on the I2C bus if you try to issue more commands while the previous command is being executed.

Best regards
Torbjørn