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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Share the same pins on TWIM0 &amp;amp; TWIM1</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/103948/share-the-same-pins-on-twim0-twim1</link><description>I would like to set up TWI transactions to two peripherals triggered by a single PPI event. Reading prior forum posts, it looks like this can only be done if the transactions to the two peripherals are identical (e.g. sending/receiving the same number</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 11 Oct 2023 15:31:24 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/103948/share-the-same-pins-on-twim0-twim1" /><item><title>RE: Share the same pins on TWIM0 &amp; TWIM1</title><link>https://devzone.nordicsemi.com/thread/449894?ContentTypeID=1</link><pubDate>Wed, 11 Oct 2023 15:31:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9c2ee304-fe1a-4ed7-9120-d8a81c34d92e</guid><dc:creator>KWolfe81</dc:creator><description>&lt;p&gt;Again, setting up the PPI, events, and tasks isn&amp;#39;t the issue.&amp;nbsp; If I have both TWI&amp;nbsp;peripherals using the same pins and both are enabled, the transactions do not begin properly. (no, I am not attempting to execute both transactions at the same time).&lt;/p&gt;
&lt;p&gt;I am going to close the ticket and assume this isn&amp;#39;t possible due to the master-mode issue outlined in the original post.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Share the same pins on TWIM0 &amp; TWIM1</title><link>https://devzone.nordicsemi.com/thread/449838?ContentTypeID=1</link><pubDate>Wed, 11 Oct 2023 13:14:05 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:80c8ab96-334a-4b96-bd4a-29c9ca6c7a98</guid><dc:creator>Maria Gilje</dc:creator><description>&lt;p&gt;Have you considered a sequential read? I.e. the 5ms timeout is the EEP event which starts the TEP read task for peripheral A, and the TWIM STOPPED event is the EEP to trigger the TEP for reading from peripheral B. &lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Share the same pins on TWIM0 &amp; TWIM1</title><link>https://devzone.nordicsemi.com/thread/449221?ContentTypeID=1</link><pubDate>Fri, 06 Oct 2023 15:47:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:40a62b55-c941-465b-a6f0-d8ea9822e1eb</guid><dc:creator>KWolfe81</dc:creator><description>&lt;p&gt;I can set up the ppi chain fine. The issue is that the twi transactions do not begin when both twi peripherals are enabled.&amp;nbsp;&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Share the same pins on TWIM0 &amp; TWIM1</title><link>https://devzone.nordicsemi.com/thread/449157?ContentTypeID=1</link><pubDate>Fri, 06 Oct 2023 11:45:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1d669a46-6922-4bf9-aee3-ab1c57220472</guid><dc:creator>Maria Gilje</dc:creator><description>&lt;p&gt;Have you looked into setting up a TEP fork? From the &lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf52833/ppi.html?cp=5_1_0_5_14"&gt;PPI documentation&lt;/a&gt; for nRF52833:&lt;/p&gt;
&lt;p&gt;&lt;em&gt;Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0]. &lt;/em&gt;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Maria&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Share the same pins on TWIM0 &amp; TWIM1</title><link>https://devzone.nordicsemi.com/thread/446944?ContentTypeID=1</link><pubDate>Wed, 20 Sep 2023 16:26:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f93c8cfd-3146-40ed-92df-1552553de693</guid><dc:creator>KWolfe81</dc:creator><description>&lt;p&gt;Scenario: I have two&amp;nbsp;peripheral devices on the same TWI bus.&amp;nbsp;&amp;nbsp;Every 5 mSec, I would like to automatically read 5 bytes from register 0x00 on peripheral A, and 20 bytes from register 0x10 on peripheral B. All of this would happen using PPI and zero CPU cycles.&lt;/p&gt;
&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/35359/2-devices-on-a-single-twi-instance-ppi"&gt;Here&amp;#39;s&lt;/a&gt;&amp;nbsp;the link to a prior forum post stating that this can be done if the transactions to both peripherals are identical.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Share the same pins on TWIM0 &amp; TWIM1</title><link>https://devzone.nordicsemi.com/thread/446937?ContentTypeID=1</link><pubDate>Wed, 20 Sep 2023 15:41:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1ff527f5-a8a6-44fa-a777-2d75d4d5acdc</guid><dc:creator>Maria Gilje</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;I have been assigned this ticket, and I will get back to you soon. In the meantime, I appreciate if you can share more information on what your goal is with this.&lt;/p&gt;
&lt;p&gt;It is helpful if you can share more details on what you want to achieve with this. I.e. what is your use case?&lt;/p&gt;
[quote user=""]&amp;nbsp;&amp;nbsp;Reading prior forum posts,[/quote]
&lt;p&gt;Please share which posts these are.&lt;/p&gt;
&lt;p&gt;I encourage the community to share their insights on this! &lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Maria&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>