I2S first and second cycle data is not available, causing a problem with the level.

RE: I2S first and second cycle data is not available, causing a problem with the level.

JONATHAN LL — Mon, 16 Oct 2023 09:19:08 GMT

Hi Stars,

[quote user="stars"]What causes right channel data to overwrite left channel data[/quote]

I am not sure but it could be related to the ERRATA 54: https://infocenter.nordicsemi.com/topic/errata_nRF52832_Rev3/ERR/nRF52832/Rev3/latest/anomaly_832_54.html?cp=5_2_1_0_1_6

When using Aligned mode left and right samples are swapped.

So to summarize:
you have a product\deice that is a PCB that has the nRF52832 mounted and you are using I2S.
- There is an issue with the I2S signal, the cause seems to be from the PCB(?), so it is not SoC related.
- increasing the length of debug wires solves the signal issue seen on I2S.
- The issue is that the Right cannel overwrites the Left channel data.

Regards,
Jonathan

RE: I2S first and second cycle data is not available, causing a problem with the level.

stars — Mon, 16 Oct 2023 01:12:55 GMT

Hi，

Yes, the circuit board caused the cause, but do not know what the specific reason is, because now increase the length of the wire data is normal. We can't understand how it works. What causes right channel data to overwrite left channel data

Best regards,

Stars

RE: I2S first and second cycle data is not available, causing a problem with the level.

JONATHAN LL — Fri, 13 Oct 2023 13:57:18 GMT

[quote user="stars"]There are chip exchange tests, it can be determined that this phenomenon is followed by the board. [/quote]

Does that mean that the board is the cause for the error? is that what you are saying?

Regards,
Jonathan

RE: I2S first and second cycle data is not available, causing a problem with the level.

stars — Fri, 13 Oct 2023 10:16:29 GMT

Hi，

Now in the research and development stage, the second batch of half of the board has a problem, we want to determine the problem, otherwise this is a fatal problem in the batch. I'm on the third batch of boards, not sure if we'll have the same problem.

There are chip exchange tests, it can be determined that this phenomenon is followed by the board. It is normal to replace the chip data on the wrong board on the normal board.

Best regards,

Stars

RE: I2S first and second cycle data is not available, causing a problem with the level.

JONATHAN LL — Fri, 13 Oct 2023 09:00:36 GMT

Thanks for providing all the details but I would like to have the option to reproduce the issues.

Can you provide a minimal sample that produces the issue?

How many board do you have that exhibit the "bad" behavior.

Are you able to switch the SoC from a "bad" board to a good one? this will help eliminate if there is any issues with the PCB.

Regards,
Jonathan

RE: I2S first and second cycle data is not available, causing a problem with the level.

stars — Thu, 12 Oct 2023 06:00:32 GMT

Hi，

After testing, the correct data can be obtained if a wire is added directly to the logic analyzer and the three output pins of the I2S.

We suspect a parasitic capacitor on the wire is making the data normal, but why is that?

Can you give me some advice on screening?

Best regards,

Stars

RE: I2S first and second cycle data is not available, causing a problem with the level.

stars — Wed, 11 Oct 2023 10:41:14 GMT

Hi Jonathan，

Now we can accept empty data for the first few cycles at startup, but a new fatal problem has been discovered.

We have two batches of boards, and the equipment of the first batch is consistent with the DK board. However, the second batch of boards had equipment problems: the transmission of left and right channel data, the right channel data to cover the left channel data.

The comparison test is as follows:

1.The chip is completely erased before each download

2.The program configuration is the same, right-justified：

Test data are as follows：

3.Download the program to the DK board and the second batch of faulty equipment, and collect the waveform：

Why does this happen? And confirmed that the silk screen on the two batches of chips are N52832-QFAAG1-2238AT.

This problem has a great impact on our development process, please provide me with some ideas to determine the cause of the problem.

Best regards,

Stars

RE: I2S first and second cycle data is not available, causing a problem with the level.

JONATHAN LL — Thu, 05 Oct 2023 10:42:54 GMT

Hi Stars,

Yes I can preproduce this on the 52DK. I have done some testing, and fond that there will always be some gap in time from when the clock's start and to when the data is sent. But it also depends on the format mode used.

In the default mode, also known as I2S mode, each frame contains one left and right sample pair, with the left sample being transferred during the low half period of LRCK followed by the right sample being transferred during the high period of LRCK 1.

In Aligned mode, each frame contains one left and right sample pair, with the left sample being transferred during the high half period of LRCK followed by the right sample being transferred during the low period of LRCK 1. Consequently, the LRCK frequency is equivalent to the audio sample rate

It never start on the first rising\falling edge of the LRCK, but from the second shift it is either after the rising or falling.

Regards,
Jonathan

RE: I2S first and second cycle data is not available, causing a problem with the level.

stars — Thu, 28 Sep 2023 01:29:15 GMT

Hi，

I used the default example and didn't make any changes. The requirement is that you want the data to be synchronized with the clock. Can you reproduce the phenomenon using nrf52DK?

For example, there is no data in the red circled part of the picture. I want the data to appear with the clock. Is that even possible? Or my understanding of I2S is wrong, I2S communication, the first part of the data and the clock is not synchronized?

Best regards,

Stars

RE: I2S first and second cycle data is not available, causing a problem with the level.

JONATHAN LL — Wed, 27 Sep 2023 08:44:08 GMT

HI,

What changes have you made to the example?

What bit rate are you using?

We have info on use and configuration information here https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/i2s.html?cp=5_2_0_43#concept_z2v_24y_vr .

Regards,
Jonathan