<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/105325/cannot-output-high-frequency-signal-via-pwm</link><description>I am attempting to generate a square wave on a GPIO in order to drive the clock of another IC. I have configured a PWM to do this, but it has been behaving strangely. I would expect the code below to output a 50% duty cycle square wave at 50kHz, instead</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Fri, 10 Nov 2023 00:57:10 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/105325/cannot-output-high-frequency-signal-via-pwm" /><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/455036?ContentTypeID=1</link><pubDate>Fri, 10 Nov 2023 00:57:10 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:5e4d5a93-410f-4b9a-8821-9ed2b6283410</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;Ok, maybe also boost the pin strength:&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;Change
      NRF_GPIO_PIN_S0S1,
tp
      NRF_GPIO_PIN_H0H1,
&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;Edit: Ok, why would I suggest this as if you are just driving the pin high or low with no clock then drive strength is pretty unimportant for a pin even with a large capacitor connected. The reason is earlier I think you suggested the pin driver (the internal FET) might have been damaged, which is quite possible. The internal FET driving the pin high or low with a modest RDSon resistance might have vaporised; magically it can be repaired (actually replaced) with a spare internal FET in parallel&amp;nbsp;which happens to have a lower RDSon and hence stronger drive high or low.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454981?ContentTypeID=1</link><pubDate>Thu, 09 Nov 2023 15:58:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3f16e912-f506-4971-83e6-dbaaf4045c8a</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;Hey hmolesworth,&lt;/p&gt;
&lt;p&gt;&amp;nbsp; At this point I am just attempting to get P0.18 to get set high, rather than worrying about the PWM signal, now that I have found the PWM code works when selecting another pin, so the capacitor should be ruled out as an issue.&amp;nbsp; Relevant code snippets below:&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;
#define FL_CLK_PIN NRF_GPIO_PIN_MAP(0,18)


    nrf_gpio_cfg	(
      FL_CLK_PIN,
      NRF_GPIO_PIN_DIR_OUTPUT,
      NRF_GPIO_PIN_INPUT_DISCONNECT,
      NRF_GPIO_PIN_NOPULL,
      NRF_GPIO_PIN_S0S1,
      NRF_GPIO_PIN_NOSENSE
    );
    
    
    nrf_gpio_pin_set(FL_CLK_PIN);
&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Also I have confirmed that the relevant memory locations in the UICR seem to have the correct values.&amp;nbsp; Memory read outputs below:&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;C:\Program Files (x86)\Nordic Semiconductor\nrf-command-line-tools\bin&amp;gt;nrfjprog -f nrf52 --memrd 0x10001200
0x10001200: FFFFFFFF                              |....|

C:\Program Files (x86)\Nordic Semiconductor\nrf-command-line-tools\bin&amp;gt;nrfjprog -f nrf52 --memrd 0x10001204
0x10001204: FFFFFFFF                              |....|&lt;/pre&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454807?ContentTypeID=1</link><pubDate>Thu, 09 Nov 2023 01:15:50 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:666bed2e-f0a3-4436-a5cc-5db35d99ad12</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;Did you check for a capacitor fitted on that pin? If not it might be killing the signal ..&lt;/p&gt;
&lt;p&gt;UICR is flash memory and flash memory bits can only be &amp;quot;programmed&amp;quot; low, not high; high requires a flash erase which means more than just one memory location.&amp;nbsp;For this command to work would imply nrfjprog first reads the UICR, then erases it, then rewrites it with the original data save for that 1 location. Does nrfjprog actually do that?&lt;/p&gt;
&lt;p&gt;&lt;span&gt;nrfjprog -f nrf52 --memwr 0x10001200 --val 0xFFFFFFFF&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;span&gt;More notes:&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;// User information configuration registers (UICR) are written in the same way as Flash. After UICR has been
// written, the new UICR configuration will only take effect after a reset.

// The Non-volatile memory controller (NVMC) is used for writing and erasing the internal Flash memory and
// the UICR.
// Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before
// an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN. The user must make sure
// that writing and erasing are not enabled at the same time. Failing to do so may result in unpredictable behavior.
// Writing to Flash
// When writing is enabled, the Flash is written by writing a full 32-bit word to a word-aligned address in the
// Flash.
// The NVMC is only able to write &amp;#39;0&amp;#39; to bits in the Flash that are erased, that is, set to &amp;#39;1&amp;#39;. It cannot write back a
// bit to &amp;#39;1&amp;#39;.
&lt;/pre&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454796?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:48:12 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:acbbd67a-161a-4848-a7dd-8e780263f975</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;Hey Snoopy, way ahead of you.&amp;nbsp; Been doing that for most of my testing for a while, and had no luck unfortunately.&amp;nbsp; And thank you for all of your suggestions, they have been greatly appreciated.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454795?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:42:33 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:afa4b9a1-b6a2-4b5b-9ebd-cd3433d7e379</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;Sorry must have typed at the same time and missed your reply. Can you set the pin high (disable pwm code) and see if there&amp;#39;s a level high from it?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454793?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:31:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fe042323-7ffb-4eb9-ae42-0b951ad0ce45</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;As I said, I have read the output of the location after each of my changes, and confirmed that there was no change when its value was set to 0x00000000, or 0xFFFFFFFF&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454792?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:29:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d67b0ca6-b27c-41d8-98d4-a223d4ea0bfc</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;Read the memory location first...&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454791?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:28:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:0c0155e5-f793-49ea-84c3-d77b45ca63ad</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;I am starting to worry perhaps I have a HW issue, perhaps something happened to burn out this one pin.&amp;nbsp; I will get a second board set up to test on.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454790?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:27:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3697fc0f-e7e6-4dc6-a054-892f2273daea</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;After I ran your command the output was 0, no change to behavior.&amp;nbsp; I also tried with&amp;nbsp;&lt;span&gt;0x10001200 set to 0 as well.&amp;nbsp; And with both set to all F&amp;#39;s, none allowed the pin to function as&amp;nbsp; GPIO.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454789?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 22:25:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:be57ee7c-bc82-4ee8-ab63-097262e1df01</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;Read the output of that memory location?&lt;br /&gt;&lt;br /&gt;Sorry my value=0 was wrong, try nrfjprog -f nrf52 --memwr 0x10001200 --val 0xFFFFFFFF&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454786?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 21:41:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e324475e-ad99-44c7-b0a5-6e7760b52229</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;Hey Snoopy, gave this a try as well.&amp;nbsp; There was no change.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454773?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:35:28 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:0acde1e9-32e3-4e9e-a217-81665f712e2e</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;Same thing then&lt;br /&gt;&lt;br /&gt;&lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fug_getting_started%2FUG%2Fgs%2Fdevelop_sw.html&amp;amp;cp=1_0_2"&gt;infocenter.nordicsemi.com/index.jsp&lt;/a&gt;&lt;br /&gt;&lt;br /&gt;nrfjprog -f nrf52 --memwr 0x10001200 --val 0&lt;br /&gt;&lt;br /&gt;Edit:&lt;br /&gt;&lt;br /&gt;That didn&amp;#39;t copy/paste properly. The pin is disabled by default apparently but somehow you have the opposite.&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;h3 id="ariaid-title6" class="title topictitle3"&gt;PSELRESET[n] (n=0..1)&lt;/h3&gt;
&lt;div class="body refbody"&gt;
&lt;div class="section"&gt;
&lt;p class="p"&gt;&lt;span class="ph"&gt;Address offset: 0x200 + (n &amp;times; 0x4)&lt;/span&gt;&lt;/p&gt;
&lt;p class="p"&gt;&lt;span class="ph"&gt;Mapping of the nRESET function (see POWER chapter for details)&lt;/span&gt;&lt;/p&gt;
&lt;p class="p"&gt;&lt;span class="ph"&gt;All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start independently of the levels present on any of the GPIOs.&lt;/span&gt;&lt;/p&gt;
&lt;div id="register.PSELRESET-0-1__pPSELRESET-0-1" class="p"&gt;
&lt;div class="tablenoborder"&gt;
&lt;table id="register.PSELRESET-0-1__PSELRESET-0-1" class="table register" border="1" cellpadding="4" cellspacing="0" frame="border" rules="all" summary=""&gt;&lt;colgroup span="1"&gt;&lt;col style="width:3.97456279809221%;" span="1" /&gt;&lt;col style="width:3.1796502384737675%;" span="1" /&gt;&lt;col style="width:15.89825119236884%;" span="1" /&gt;&lt;col style="width:15.89825119236884%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;col style="width:1.9077901430842605%;" span="1" /&gt;&lt;/colgroup&gt;
&lt;thead class="thead" style="text-align:left;"&gt;
&lt;tr class="row"&gt;
&lt;th id="d2014525e3212" class="entry nocellnorowborder" style="vertical-align:top;" colspan="4" rowspan="1"&gt;Bit number&lt;/th&gt;
&lt;th id="d2014525e3215" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;31&lt;/th&gt;
&lt;th id="d2014525e3218" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;30&lt;/th&gt;
&lt;th id="d2014525e3221" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;29&lt;/th&gt;
&lt;th id="d2014525e3224" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;28&lt;/th&gt;
&lt;th id="d2014525e3228" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;27&lt;/th&gt;
&lt;th id="d2014525e3231" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;26&lt;/th&gt;
&lt;th id="d2014525e3234" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;25&lt;/th&gt;
&lt;th id="d2014525e3237" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;24&lt;/th&gt;
&lt;th id="d2014525e3240" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;23&lt;/th&gt;
&lt;th id="d2014525e3243" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;22&lt;/th&gt;
&lt;th id="d2014525e3247" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;21&lt;/th&gt;
&lt;th id="d2014525e3250" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;20&lt;/th&gt;
&lt;th id="d2014525e3253" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;19&lt;/th&gt;
&lt;th id="d2014525e3256" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;18&lt;/th&gt;
&lt;th id="d2014525e3259" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;17&lt;/th&gt;
&lt;th id="d2014525e3262" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;16&lt;/th&gt;
&lt;th id="d2014525e3266" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;15&lt;/th&gt;
&lt;th id="d2014525e3269" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;14&lt;/th&gt;
&lt;th id="d2014525e3272" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;13&lt;/th&gt;
&lt;th id="d2014525e3275" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;12&lt;/th&gt;
&lt;th id="d2014525e3278" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;11&lt;/th&gt;
&lt;th id="d2014525e3281" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;10&lt;/th&gt;
&lt;th id="d2014525e3285" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;9&lt;/th&gt;
&lt;th id="d2014525e3288" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;8&lt;/th&gt;
&lt;th id="d2014525e3291" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;7&lt;/th&gt;
&lt;th id="d2014525e3294" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;6&lt;/th&gt;
&lt;th id="d2014525e3297" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;5&lt;/th&gt;
&lt;th id="d2014525e3300" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;4&lt;/th&gt;
&lt;th id="d2014525e3304" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;3&lt;/th&gt;
&lt;th id="d2014525e3307" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;2&lt;/th&gt;
&lt;th id="d2014525e3310" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3313" class="entry cell-norowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;0&lt;/th&gt;
&lt;/tr&gt;
&lt;tr class="row"&gt;
&lt;th id="d2014525e3319" class="entry nocellnorowborder" style="vertical-align:top;" colspan="4" rowspan="1"&gt;ID&lt;/th&gt;
&lt;th id="d2014525e3322" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;C&lt;/th&gt;
&lt;th id="d2014525e3325" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3327" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3329" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3332" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3334" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3336" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3338" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3340" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3342" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3345" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3347" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3349" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3351" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3353" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3355" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3358" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3360" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3362" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3364" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3366" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3368" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3371" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3373" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3375" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3377" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;&amp;nbsp;&lt;/th&gt;
&lt;th id="d2014525e3379" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;
&lt;p class="p"&gt;B&lt;/p&gt;
&lt;/th&gt;
&lt;th id="d2014525e3385" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;A&lt;/th&gt;
&lt;th id="d2014525e3389" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;A&lt;/th&gt;
&lt;th id="d2014525e3392" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;A&lt;/th&gt;
&lt;th id="d2014525e3395" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;A&lt;/th&gt;
&lt;th id="d2014525e3398" class="entry cell-norowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;A&lt;/th&gt;
&lt;/tr&gt;
&lt;tr class="row"&gt;
&lt;th id="d2014525e3404" class="entry nocellnorowborder" style="vertical-align:top;" colspan="4" rowspan="1"&gt;Reset 0xFFFFFFFF&lt;/th&gt;
&lt;th id="d2014525e3407" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3410" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3413" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3416" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3420" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3423" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3426" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3429" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3432" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3435" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3439" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3442" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3445" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3448" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3451" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3454" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3458" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3461" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3464" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3467" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3470" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3473" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3477" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3480" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3483" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3486" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3489" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3492" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3496" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3499" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3502" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;th id="d2014525e3505" class="entry cell-norowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;1&lt;/th&gt;
&lt;/tr&gt;
&lt;tr class="row"&gt;
&lt;th id="d2014525e3511" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;ID&lt;/th&gt;
&lt;th id="d2014525e3514" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;Access&lt;/th&gt;
&lt;th id="d2014525e3517" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;Field&lt;/th&gt;
&lt;th id="d2014525e3520" class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" rowspan="1"&gt;Value ID&lt;/th&gt;
&lt;th id="d2014525e3523" class="entry nocellnorowborder" style="vertical-align:top;" colspan="8" rowspan="1"&gt;Value&lt;/th&gt;
&lt;th id="d2014525e3527" class="entry cell-norowborder" style="vertical-align:top;" colspan="24" rowspan="1"&gt;Description&lt;/th&gt;
&lt;/tr&gt;
&lt;/thead&gt;
&lt;tbody class="tbody"&gt;
&lt;tr class="row field"&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3511" rowspan="1"&gt;A&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3514" rowspan="1"&gt;RW&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3517" rowspan="1"&gt;
&lt;p class="p"&gt;PIN&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3520" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="8" headers="d2014525e3215 d2014525e3218 d2014525e3221 d2014525e3224 d2014525e3228 d2014525e3231 d2014525e3234 d2014525e3237 d2014525e3322 d2014525e3325 d2014525e3327 d2014525e3329 d2014525e3332 d2014525e3334 d2014525e3336 d2014525e3338 d2014525e3407 d2014525e3410 d2014525e3413 d2014525e3416 d2014525e3420 d2014525e3423 d2014525e3426 d2014525e3429 d2014525e3523" rowspan="1"&gt;
&lt;p class="p"&gt;18&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="20" headers="d2014525e3240 d2014525e3243 d2014525e3247 d2014525e3250 d2014525e3253 d2014525e3256 d2014525e3259 d2014525e3262 d2014525e3266 d2014525e3269 d2014525e3272 d2014525e3275 d2014525e3278 d2014525e3281 d2014525e3285 d2014525e3288 d2014525e3291 d2014525e3294 d2014525e3297 d2014525e3300 d2014525e3340 d2014525e3342 d2014525e3345 d2014525e3347 d2014525e3349 d2014525e3351 d2014525e3353 d2014525e3355 d2014525e3358 d2014525e3360 d2014525e3362 d2014525e3364 d2014525e3366 d2014525e3368 d2014525e3371 d2014525e3373 d2014525e3375 d2014525e3377 d2014525e3379 d2014525e3385 d2014525e3432 d2014525e3435 d2014525e3439 d2014525e3442 d2014525e3445 d2014525e3448 d2014525e3451 d2014525e3454 d2014525e3458 d2014525e3461 d2014525e3464 d2014525e3467 d2014525e3470 d2014525e3473 d2014525e3477 d2014525e3480 d2014525e3483 d2014525e3486 d2014525e3489 d2014525e3492 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;GPIO pin number onto which nRESET is exposed&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry cell-norowborder" style="vertical-align:top;" colspan="4" headers="d2014525e3304 d2014525e3307 d2014525e3310 d2014525e3313 d2014525e3389 d2014525e3392 d2014525e3395 d2014525e3398 d2014525e3496 d2014525e3499 d2014525e3502 d2014525e3505 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;&lt;/p&gt;
&lt;/td&gt;
&lt;/tr&gt;
&lt;tr class="row field"&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3511" rowspan="1"&gt;B&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3514" rowspan="1"&gt;RW&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3517" rowspan="1"&gt;
&lt;p class="p"&gt;PORT&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3520" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="8" headers="d2014525e3215 d2014525e3218 d2014525e3221 d2014525e3224 d2014525e3228 d2014525e3231 d2014525e3234 d2014525e3237 d2014525e3322 d2014525e3325 d2014525e3327 d2014525e3329 d2014525e3332 d2014525e3334 d2014525e3336 d2014525e3338 d2014525e3407 d2014525e3410 d2014525e3413 d2014525e3416 d2014525e3420 d2014525e3423 d2014525e3426 d2014525e3429 d2014525e3523" rowspan="1"&gt;
&lt;p class="p"&gt;0&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="20" headers="d2014525e3240 d2014525e3243 d2014525e3247 d2014525e3250 d2014525e3253 d2014525e3256 d2014525e3259 d2014525e3262 d2014525e3266 d2014525e3269 d2014525e3272 d2014525e3275 d2014525e3278 d2014525e3281 d2014525e3285 d2014525e3288 d2014525e3291 d2014525e3294 d2014525e3297 d2014525e3300 d2014525e3340 d2014525e3342 d2014525e3345 d2014525e3347 d2014525e3349 d2014525e3351 d2014525e3353 d2014525e3355 d2014525e3358 d2014525e3360 d2014525e3362 d2014525e3364 d2014525e3366 d2014525e3368 d2014525e3371 d2014525e3373 d2014525e3375 d2014525e3377 d2014525e3379 d2014525e3385 d2014525e3432 d2014525e3435 d2014525e3439 d2014525e3442 d2014525e3445 d2014525e3448 d2014525e3451 d2014525e3454 d2014525e3458 d2014525e3461 d2014525e3464 d2014525e3467 d2014525e3470 d2014525e3473 d2014525e3477 d2014525e3480 d2014525e3483 d2014525e3486 d2014525e3489 d2014525e3492 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;Port number onto which nRESET is exposed&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry cell-norowborder" style="vertical-align:top;" colspan="4" headers="d2014525e3304 d2014525e3307 d2014525e3310 d2014525e3313 d2014525e3389 d2014525e3392 d2014525e3395 d2014525e3398 d2014525e3496 d2014525e3499 d2014525e3502 d2014525e3505 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;&lt;/p&gt;
&lt;/td&gt;
&lt;/tr&gt;
&lt;tr class="row field"&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3511" rowspan="1"&gt;C&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3514" rowspan="1"&gt;RW&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3517" rowspan="1"&gt;
&lt;p class="p"&gt;CONNECT&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3520" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="8" headers="d2014525e3215 d2014525e3218 d2014525e3221 d2014525e3224 d2014525e3228 d2014525e3231 d2014525e3234 d2014525e3237 d2014525e3322 d2014525e3325 d2014525e3327 d2014525e3329 d2014525e3332 d2014525e3334 d2014525e3336 d2014525e3338 d2014525e3407 d2014525e3410 d2014525e3413 d2014525e3416 d2014525e3420 d2014525e3423 d2014525e3426 d2014525e3429 d2014525e3523" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="20" headers="d2014525e3240 d2014525e3243 d2014525e3247 d2014525e3250 d2014525e3253 d2014525e3256 d2014525e3259 d2014525e3262 d2014525e3266 d2014525e3269 d2014525e3272 d2014525e3275 d2014525e3278 d2014525e3281 d2014525e3285 d2014525e3288 d2014525e3291 d2014525e3294 d2014525e3297 d2014525e3300 d2014525e3340 d2014525e3342 d2014525e3345 d2014525e3347 d2014525e3349 d2014525e3351 d2014525e3353 d2014525e3355 d2014525e3358 d2014525e3360 d2014525e3362 d2014525e3364 d2014525e3366 d2014525e3368 d2014525e3371 d2014525e3373 d2014525e3375 d2014525e3377 d2014525e3379 d2014525e3385 d2014525e3432 d2014525e3435 d2014525e3439 d2014525e3442 d2014525e3445 d2014525e3448 d2014525e3451 d2014525e3454 d2014525e3458 d2014525e3461 d2014525e3464 d2014525e3467 d2014525e3470 d2014525e3473 d2014525e3477 d2014525e3480 d2014525e3483 d2014525e3486 d2014525e3489 d2014525e3492 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;Connection&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry cell-norowborder" style="vertical-align:top;" colspan="4" headers="d2014525e3304 d2014525e3307 d2014525e3310 d2014525e3313 d2014525e3389 d2014525e3392 d2014525e3395 d2014525e3398 d2014525e3496 d2014525e3499 d2014525e3502 d2014525e3505 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;&lt;/p&gt;
&lt;/td&gt;
&lt;/tr&gt;
&lt;tr class="row"&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3511" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3514" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3517" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3520" rowspan="1"&gt;
&lt;p class="p"&gt;Disconnected&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="8" headers="d2014525e3215 d2014525e3218 d2014525e3221 d2014525e3224 d2014525e3228 d2014525e3231 d2014525e3234 d2014525e3237 d2014525e3322 d2014525e3325 d2014525e3327 d2014525e3329 d2014525e3332 d2014525e3334 d2014525e3336 d2014525e3338 d2014525e3407 d2014525e3410 d2014525e3413 d2014525e3416 d2014525e3420 d2014525e3423 d2014525e3426 d2014525e3429 d2014525e3523" rowspan="1"&gt;
&lt;p class="p"&gt;1&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" style="vertical-align:top;" colspan="20" headers="d2014525e3240 d2014525e3243 d2014525e3247 d2014525e3250 d2014525e3253 d2014525e3256 d2014525e3259 d2014525e3262 d2014525e3266 d2014525e3269 d2014525e3272 d2014525e3275 d2014525e3278 d2014525e3281 d2014525e3285 d2014525e3288 d2014525e3291 d2014525e3294 d2014525e3297 d2014525e3300 d2014525e3340 d2014525e3342 d2014525e3345 d2014525e3347 d2014525e3349 d2014525e3351 d2014525e3353 d2014525e3355 d2014525e3358 d2014525e3360 d2014525e3362 d2014525e3364 d2014525e3366 d2014525e3368 d2014525e3371 d2014525e3373 d2014525e3375 d2014525e3377 d2014525e3379 d2014525e3385 d2014525e3432 d2014525e3435 d2014525e3439 d2014525e3442 d2014525e3445 d2014525e3448 d2014525e3451 d2014525e3454 d2014525e3458 d2014525e3461 d2014525e3464 d2014525e3467 d2014525e3470 d2014525e3473 d2014525e3477 d2014525e3480 d2014525e3483 d2014525e3486 d2014525e3489 d2014525e3492 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;Disconnect&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry cell-norowborder" style="vertical-align:top;" colspan="4" headers="d2014525e3304 d2014525e3307 d2014525e3310 d2014525e3313 d2014525e3389 d2014525e3392 d2014525e3395 d2014525e3398 d2014525e3496 d2014525e3499 d2014525e3502 d2014525e3505 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;&lt;/p&gt;
&lt;/td&gt;
&lt;/tr&gt;
&lt;tr class="row"&gt;
&lt;td class="entry row-nocellborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3511" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry row-nocellborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3514" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry row-nocellborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3517" rowspan="1"&gt;&amp;nbsp;&lt;/td&gt;
&lt;td class="entry row-nocellborder" style="vertical-align:top;" colspan="1" headers="d2014525e3212 d2014525e3319 d2014525e3404 d2014525e3520" rowspan="1"&gt;
&lt;p class="p"&gt;Connected&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry row-nocellborder" style="vertical-align:top;" colspan="8" headers="d2014525e3215 d2014525e3218 d2014525e3221 d2014525e3224 d2014525e3228 d2014525e3231 d2014525e3234 d2014525e3237 d2014525e3322 d2014525e3325 d2014525e3327 d2014525e3329 d2014525e3332 d2014525e3334 d2014525e3336 d2014525e3338 d2014525e3407 d2014525e3410 d2014525e3413 d2014525e3416 d2014525e3420 d2014525e3423 d2014525e3426 d2014525e3429 d2014525e3523" rowspan="1"&gt;
&lt;p class="p"&gt;0&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry row-nocellborder" style="vertical-align:top;" colspan="20" headers="d2014525e3240 d2014525e3243 d2014525e3247 d2014525e3250 d2014525e3253 d2014525e3256 d2014525e3259 d2014525e3262 d2014525e3266 d2014525e3269 d2014525e3272 d2014525e3275 d2014525e3278 d2014525e3281 d2014525e3285 d2014525e3288 d2014525e3291 d2014525e3294 d2014525e3297 d2014525e3300 d2014525e3340 d2014525e3342 d2014525e3345 d2014525e3347 d2014525e3349 d2014525e3351 d2014525e3353 d2014525e3355 d2014525e3358 d2014525e3360 d2014525e3362 d2014525e3364 d2014525e3366 d2014525e3368 d2014525e3371 d2014525e3373 d2014525e3375 d2014525e3377 d2014525e3379 d2014525e3385 d2014525e3432 d2014525e3435 d2014525e3439 d2014525e3442 d2014525e3445 d2014525e3448 d2014525e3451 d2014525e3454 d2014525e3458 d2014525e3461 d2014525e3464 d2014525e3467 d2014525e3470 d2014525e3473 d2014525e3477 d2014525e3480 d2014525e3483 d2014525e3486 d2014525e3489 d2014525e3492 d2014525e3527" rowspan="1"&gt;
&lt;p class="p"&gt;Connect&lt;/p&gt;
&lt;/td&gt;
&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;p&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454771?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:32:43 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d7b8712f-fe2c-4c30-a063-b5bab8dfae65</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;Often there is a huge (exaggerating) capacitor to Gnd on the reset pin which can clobber a high frequency signal output; worth a check ..&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454770?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:30:05 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:0638e97a-800b-458c-8869-3db1be523ee3</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;Hey there, yes I&amp;#39;ve given this a shot and still no luck unfortunately.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454769?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:28:49 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:267780fd-e43a-463d-a05c-003eac2dd131</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;Hey Snoopy, I appreciate the tip.&amp;nbsp; I&amp;#39;m using an 833, and it seems the NFC pins are&amp;nbsp;P0.09 and&amp;nbsp;P0.10, so no luck there unfortunately.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454768?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:25:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a8ae2e24-6ac8-4883-b2d4-ab92677ad67f</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;&lt;span&gt;Yes, CONFIG_GPIO_AS_PINRESET is used to set the pin as a reset input, but it cannot reset the pin to be a general output. To force the pin back to a general i/o pin do an &lt;em&gt;Erase All&lt;/em&gt;, which erases UICR, and of course ensure&amp;nbsp;CONFIG_GPIO_AS_PINRESET is not defined.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR-&amp;gt;PSELRESET[0] &amp;amp; UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected &amp;lt;&amp;lt; UICR_PSELRESET_CONNECT_Pos)) ||
            ((NRF_UICR-&amp;gt;PSELRESET[1] &amp;amp; UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected &amp;lt;&amp;lt; UICR_PSELRESET_CONNECT_Pos))){
            NRF_NVMC-&amp;gt;CONFIG = NVMC_CONFIG_WEN_Wen &amp;lt;&amp;lt; NVMC_CONFIG_WEN_Pos;
            while (NRF_NVMC-&amp;gt;READY == NVMC_READY_READY_Busy){}
            NRF_UICR-&amp;gt;PSELRESET[0] = 18;
            while (NRF_NVMC-&amp;gt;READY == NVMC_READY_READY_Busy){}
            NRF_UICR-&amp;gt;PSELRESET[1] = 18;
            while (NRF_NVMC-&amp;gt;READY == NVMC_READY_READY_Busy){}
            NRF_NVMC-&amp;gt;CONFIG = NVMC_CONFIG_WEN_Ren &amp;lt;&amp;lt; NVMC_CONFIG_WEN_Pos;
            while (NRF_NVMC-&amp;gt;READY == NVMC_READY_READY_Busy){}
            NVIC_SystemReset();
        }
    #endif&lt;/pre&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454767?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:24:05 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:78a305f5-be21-4ba4-b626-71494c5b082c</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;Unsure of your chip but if it&amp;#39;s a 832 or higher the NFC pins are enabled by default and iirc they are on 16 and 17, or 17 and 18, something like that.&lt;br /&gt;&lt;br /&gt;See NFCPINS, and you can set it using nrfjprog.&lt;br /&gt;&lt;br /&gt;&lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52832.ps.v1.1%2Fuicr.html&amp;amp;cp=2_1_0_13_0_62&amp;amp;anchor=register.NFCPINS"&gt;infocenter.nordicsemi.com/index.jsp&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454765?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 18:17:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:74a27ed2-d558-48ac-b967-70e51f903f96</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;A little more information.&amp;nbsp; Based off my research, I have removed&amp;nbsp;&lt;span&gt;CONFIG_GPIO_AS_PINRESET from my projects preprocessor macros.&amp;nbsp; I have also run the following:&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;pre class="ui-code" data-mode="text"&gt;nrfjprog -e&lt;/pre&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Then built and downloaded my project onto my board, but I still could not output the PWM to P0.18, or even set the pin to high like a normal GPIO.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;I also ran:&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;pre class="ui-code" data-mode="text"&gt;nrfjprog --readuicr uicr.hex&lt;/pre&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;and have attached the resulting file below.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/8321.uicr.hex"&gt;devzone.nordicsemi.com/.../8321.uicr.hex&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454762?ContentTypeID=1</link><pubDate>Wed, 08 Nov 2023 17:34:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:90e84e11-c519-413d-8675-3cc94fe4d2cd</guid><dc:creator>Drew</dc:creator><description>&lt;p&gt;Hey there, after some experimentation, I found that the core issue with my code is the pin that I am using.&amp;nbsp;&amp;nbsp;NRF_GPIO_PIN_MAP(0,18), which also happens to be the MCU reset line.&amp;nbsp; The same code generates the expected signal on&amp;nbsp;NRF_GPIO_PIN_MAP(0,17).&amp;nbsp; So it seems either that pin cannot output a PWM signal, or it requires some additional configuration.&lt;/p&gt;
&lt;p&gt;Do you know if there is any configuration that I can do to get the signal to output from&amp;nbsp;NRF_GPIO_PIN_MAP(0,18)?&lt;/p&gt;
&lt;p&gt;Thanks,&lt;/p&gt;
&lt;p&gt;Drew&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454182?ContentTypeID=1</link><pubDate>Mon, 06 Nov 2023 12:00:33 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:dd30933a-89a2-4c9c-82bf-4cfc540332e7</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;What&amp;nbsp;&lt;a href="https://devzone.nordicsemi.com/members/snoopy20"&gt;snoopy20&lt;/a&gt;&amp;nbsp; suggested&amp;nbsp;could be a good solution. Another solution if you want a simple fixed duty-cycle PWM signal is to use TIMER and PPI, as is done by the&amp;nbsp;&lt;a href="https://infocenter.nordicsemi.com/topic/sdk_nrf5_v17.1.0/lib_pwm.html"&gt;PWM library&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;That said, I think I see the issue in your code. You are providing the duty cycle in the format used for individual configs (nrf_pwm_values_individual_t), but used load mode common. When I test your code and set&amp;nbsp;NRF_PWM_LOAD_INDIVIDUAL instead of NRF_PWM_LOAD_COMMON, I get the expected 50% duty cycle.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/454025?ContentTypeID=1</link><pubDate>Fri, 03 Nov 2023 16:38:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:78be5a12-ce9e-4269-9253-27de607ca8da</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;If you&amp;#39;re happy to break out of the helper libraries here&amp;#39;s some code that&amp;#39;ll do it.&lt;br /&gt;&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;  #define CFG_PWM_INVERT (1 &amp;lt;&amp;lt; 15)
  uint16_t nrf_pwm_duty[4] = {CFG_PWM_INVERT, CFG_PWM_INVERT, CFG_PWM_INVERT, CFG_PWM_INVERT};

  NRF_PWM0-&amp;gt;COUNTERTOP = CFG_PWM_COUNT &amp;lt;&amp;lt; PWM_COUNTERTOP_COUNTERTOP_Pos; // 100 = 16MHz/100 = 160KHz
  NRF_PWM0-&amp;gt;DECODER = (PWM_DECODER_LOAD_Individual &amp;lt;&amp;lt; PWM_DECODER_LOAD_Pos) | (PWM_DECODER_MODE_RefreshCount &amp;lt;&amp;lt; PWM_DECODER_MODE_Pos);
  NRF_PWM0-&amp;gt;SEQ[0].PTR = ((uint32_t) nrf_pwm_duty) &amp;lt;&amp;lt; PWM_SEQ_PTR_PTR_Pos;
  NRF_PWM0-&amp;gt;SEQ[0].CNT = (sizeof(nrf_pwm_duty) / sizeof(uint16_t)) &amp;lt;&amp;lt; PWM_SEQ_CNT_CNT_Pos;
  NRF_PWM0-&amp;gt;SEQ[1].PTR = ((uint32_t) nrf_pwm_duty) &amp;lt;&amp;lt; PWM_SEQ_PTR_PTR_Pos;
  NRF_PWM0-&amp;gt;SEQ[1].CNT = (sizeof(nrf_pwm_duty) / sizeof(uint16_t)) &amp;lt;&amp;lt; PWM_SEQ_CNT_CNT_Pos;
  NRF_PWM0-&amp;gt;SHORTS = PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled &amp;lt;&amp;lt; PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos;
  NRF_PWM0-&amp;gt;PSEL.OUT[CFG_PWM_OUTPUT_USB_NUM] = (CFG_PIN_POWERMANAGER_USB_DAC &amp;lt;&amp;lt; PWM_PSEL_OUT_PIN_Pos) | (PWM_PSEL_OUT_CONNECT_Connected &amp;lt;&amp;lt; PWM_PSEL_OUT_CONNECT_Pos);
  NRF_PWM0-&amp;gt;PSEL.OUT[CFG_PWM_OUTPUT_FRONT_NUM] = (CFG_PIN_POWERMANAGER_FRONT_DAC &amp;lt;&amp;lt; PWM_PSEL_OUT_PIN_Pos) | (PWM_PSEL_OUT_CONNECT_Connected &amp;lt;&amp;lt; PWM_PSEL_OUT_CONNECT_Pos);
  NRF_PWM0-&amp;gt;PSEL.OUT[CFG_PWM_OUTPUT_REAR_NUM] = (CFG_PIN_POWERMANAGER_REAR_DAC &amp;lt;&amp;lt; PWM_PSEL_OUT_PIN_Pos) | (PWM_PSEL_OUT_CONNECT_Connected &amp;lt;&amp;lt; PWM_PSEL_OUT_CONNECT_Pos);
  NRF_PWM0-&amp;gt;PSEL.OUT[CFG_PWM_MPPT_DAC_NUM] = (CFG_PIN_MPPT_DAC &amp;lt;&amp;lt; PWM_PSEL_OUT_PIN_Pos) | (PWM_PSEL_OUT_CONNECT_Connected &amp;lt;&amp;lt; PWM_PSEL_OUT_CONNECT_Pos);
  NRF_PWM0-&amp;gt;LOOP = 1 &amp;lt;&amp;lt; PWM_LOOP_CNT_Pos;
  NRF_PWM0-&amp;gt;ENABLE = PWM_ENABLE_ENABLE_Enabled &amp;lt;&amp;lt; PWM_ENABLE_ENABLE_Pos;
  NRF_PWM0-&amp;gt;TASKS_SEQSTART[0] = PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger &amp;lt;&amp;lt; PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos;&lt;/pre&gt;&lt;br /&gt;&lt;br /&gt;Set CFG_PWM_COUNT to your period, 1/f&lt;br /&gt;&lt;br /&gt;And then use&lt;br /&gt;&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;nrf_pwm_duty[CFG_PWM_MPPT_DAC_NUM] = CFG_PWM_INVERT | duty;&lt;/pre&gt;&lt;br /&gt;&lt;br /&gt;Where duty is 50% of your period.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;For example 160KHz, use period = 100 and duty = 50.&lt;br /&gt;&lt;br /&gt;Enjoy.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cannot output high frequency signal via PWM</title><link>https://devzone.nordicsemi.com/thread/453996?ContentTypeID=1</link><pubDate>Fri, 03 Nov 2023 14:06:39 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:74955c7f-30aa-49ba-8de4-f8c5539a3098</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;I did not immediately spot the issue so I need to test on my end on Monday. I will get back to you then.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>