SPI receives FF each time (MISO in high impedance)

RE: SPI receives FF each time (MISO in high impedance)

Tania V — Tue, 14 Nov 2023 01:25:58 GMT

Hi Naeem Maroof,

I solved by changing the overlay file (keeping spi2).

-> CLK, MOSI, MISO

From

GPIO0 13, 11 and 12

GPIO0 19, 21 and 22

Thank you for your support.

Bes regards,

Tania

RE: SPI receives FF each time (MISO in high impedance)

Naeem Maroof — Fri, 10 Nov 2023 09:09:59 GMT

Hello

Yes, the INTF_SEL should be high (VDD) for using the SPI interface as per their data-sheet

How does your hardware setup look like

It does not seem to be case at SoC side, but rather at the peripheral side

Can you make sure connections are correct and solid.

Sharing hardware snap would be great.

RE: SPI receives FF each time (MISO in high impedance)

Tania V — Thu, 09 Nov 2023 15:44:27 GMT

Hi hmolesworth,

Sorry for the misunderstanding. I was referring to the pin INTF_SEL (I still have the same issue with MISO).

If I find the solution I will write here.

Regards,

Tania

RE: SPI receives FF each time (MISO in high impedance)

hmolesworth — Thu, 09 Nov 2023 01:37:52 GMT

Yes, wonderful .. but for future readers (surely someone reads these posts ..) what did you change? Was it pin 9 INTF_SEL? :-)

Regards - Hugh

RE: SPI receives FF each time (MISO in high impedance)

Tania V — Thu, 09 Nov 2023 01:23:06 GMT

Hi hmolesworth,

I did it.

Oscilloscope captures:

Regards,

Tania

RE: SPI receives FF each time (MISO in high impedance)

hmolesworth — Tue, 07 Nov 2023 15:16:17 GMT

Data on MOSI looks correct except there are 4 bytes not 3 (which doesn't matter). Is pin 9 INTF_SEL correct? It must be high (VDD) for SPI.

spi_config needs input from Nordic, assuming it's similar to their example code. It looks ok.

RE: SPI receives FF each time (MISO in high impedance)

Tania V — Tue, 07 Nov 2023 01:15:23 GMT

Hi hmolesworth,

I had this result.

Regards,

Tania

RE: SPI receives FF each time (MISO in high impedance)

hmolesworth — Fri, 03 Nov 2023 20:52:34 GMT

I don't have those definitions to hand, but you want both bitfields to be 0 so just comment SPI_MODE_CPOL and SPI_MODE_CPHA out or delete them as follows:

static const struct spi_config _gSpiCfg = {
   .operation = SPI_WORD_SET(8) |
   SPI_TRANSFER_MSB |
   SPI_OP_MODE_MASTER,
   .frequency = 1000000,
   .slave = 0,
   .cs = &spim_cs,
};

RE: SPI receives FF each time (MISO in high impedance)

Tania V — Fri, 03 Nov 2023 17:59:09 GMT

Hi hmolesworth,

I will try it.

Do you know how I can change POL and CPHA of the clk?

From the actual configuration to CPOL=0 and CPHA=0.

It shows in the config struct but can I change it?

static const struct spi_config _gSpiCfg = {
.operation = SPI_WORD_SET(8) |
SPI_TRANSFER_MSB |
SPI_MODE_CPOL |
SPI_MODE_CPHA |
SPI_OP_MODE_MASTER,
.frequency = 1000000,
.slave = 0,
.cs = &spim_cs,
};

Thank you for your support.

RE: SPI receives FF each time (MISO in high impedance)

hmolesworth — Thu, 02 Nov 2023 23:14:29 GMT

This accelerometer is slightly unusual in that to read a single byte requires a 24-bit (3 byte) transaction as the 2nd byte is basically ignored and allows internal timing stuff, so increase the Rx buffer size from 2 bytes to 3 bytes and the "I am .." response will be in the 3rd byte.

"SPI read operations with 4-wire mode A register read operation is initiated by transmitting a 1 for the R/W bit. Then, the 7- bit register read address, A[6:0] is encoded in the first byte. Following this first byte, a second byte of 0s or 1s (don't care condition) transfers. After this transfer completes, the next 8 SCLK cycles (pulses 17 through 24) output the selected register content"

// Tx can stay unchanged, Rx has to be 3 bytes minimum
uint8_t rxBuf[2];
// to
uint8_t rxBuf[3];