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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF52833 ADC tolerance over 0 ~ 100C operating temperature</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/106836/nrf52833-adc-tolerance-over-0-100c-operating-temperature</link><description>Hi, 
 
 The right photo is our NTC SCH, AN0 and AN4 connect MCU(nrf52833) ADC I/O. 
 
 Reference the spec, we find DNL12(we use 12bit) type 4.7 LSB, it means ADC 4096 value has +/- 4.7 deviation? 
 
 We want to know for the AN0 &amp;amp; AN4 total deviation ADC</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 02 Jan 2024 14:58:18 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/106836/nrf52833-adc-tolerance-over-0-100c-operating-temperature" /><item><title>RE: nRF52833 ADC tolerance over 0 ~ 100C operating temperature</title><link>https://devzone.nordicsemi.com/thread/462343?ContentTypeID=1</link><pubDate>Tue, 02 Jan 2024 14:58:18 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1ddd2d53-ca3d-43e0-93c0-2c43539d5c2e</guid><dc:creator>helsing</dc:creator><description>&lt;p&gt;Hi Edwin,&lt;/p&gt;
&lt;p&gt;I will have a look at this while Jared is out of office.&lt;/p&gt;
[quote user=""]Reference the spec, we find DNL12(we use 12bit) type 4.7 LSB, it means ADC 4096 value has +/- 4.7 deviation?[/quote]
&lt;p&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1704207424569v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;Sorry for the confusion, are we talking about INL12 or DNL12?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52833 ADC tolerance over 0 ~ 100C operating temperature</title><link>https://devzone.nordicsemi.com/thread/461889?ContentTypeID=1</link><pubDate>Thu, 28 Dec 2023 03:26:06 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4db36c2e-1667-458a-86d3-c66b532cf901</guid><dc:creator>Edwin_TTi</dc:creator><description>&lt;p&gt;Hi Jared,&lt;/p&gt;
&lt;p&gt;I&amp;#39;m sorry, I&amp;nbsp;don&amp;#39;t get your means.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;AN0 deviation is +4.7 ADC, AN4 ADC is -4.7 ADC at the same time?&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1703733754629v1.png" alt=" " /&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1703733949954v4.png" alt=" " /&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;span&gt;Thanks,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Edwin&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52833 ADC tolerance over 0 ~ 100C operating temperature</title><link>https://devzone.nordicsemi.com/thread/461545?ContentTypeID=1</link><pubDate>Fri, 22 Dec 2023 10:23:12 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:49d168b7-41e5-4b14-9ccf-f0fa5a67430e</guid><dc:creator>Jared</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
[quote user=""]Reference the spec, we find DNL12(we use 12bit) type 4.7 LSB, it means ADC 4096 value has +/- 4.7 deviation[/quote]
&lt;p&gt;4.7 LSB yes,&lt;/p&gt;
&lt;p&gt;DNL error for a specific bit tells you how much wider the actual step width the converter is from the ideal step width of the transfer function. All of the errors listed in the product specification is specific for the SAADC peripheral itself, the deviation should not be different between analog pins. At least it should be within the MIN and TYP as listed in the Product spec. The ideal step width is 1 LSB.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;regards&lt;/p&gt;
&lt;p&gt;Jared&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>