RE: nRF52 Level-triggered Interrupts

hmolesworth — Tue, 12 Mar 2024 17:12:51 GMT

Not what you seek, as Events are edge-triggered, but Interrupts are level-triggered. An enabled event triggers on an "edge" and remains "set" until manually cleared by either SHORT, PPI or firmware. An enabled interrupt triggered from such an enabled-and-triggered Event remains "active" and will trigger the interrupt handler until the corresponding Event is cleared or the interrupt disabled. Typically the interrupt handler clears the enabled-and-triggered Event which stops the interrupt occurring until the next event; if the interrupt does not clear the enabled-and-triggered Event then on return-from-interrupt is followed by the same interrupt handler invocation often using tail-chaining.

Side-effects include clearing the enabled-and-triggered Event as the very last instruction in the interrupt handler; since the peripheral register is on a separate bus and uses a 16MHz clock, the 64MHz instruction bus invokes a second unwanted interrupt handler via tail-chaining before that event gets cleared. This can be avoided by inserting extra instructions after the event clear, reading back the register or (better) by inserting a __DSB() after the event clear. This discussion applies to the nRF52 series; not tested nRF53 or nRF54 for this yet.

Regarding the GPIO; no, this is not what you are seeking "The ISR should never stop repeatedly executing until the GPIO level is changed to the inactive state" unless a pin input check is made within the interrupt which as noted can lead to interrupt thrashing.