Measuring signals above and below VSS with the ADC

RE: Measuring signals above and below VSS with the ADC

Kenneth — Mon, 17 Jun 2024 09:00:49 GMT

[quote user="Ohad Gal"]maybe they are due to the AGC offset?[/quote]

Very likely yes.

[quote user="Ohad Gal"]but you are saying that all GPIOs and all Analog inputs must not go below VSS. Is that correct?[/quote]

Correct.

Kenneth

RE: Measuring signals above and below VSS with the ADC

Ohad Gal — Thu, 13 Jun 2024 14:33:14 GMT

We actually se when measuring single ended between A5 to GND that we get negative values.
although small, they are real.
maybe they are due to the AGC offset?

but you are saying that all GPIOs and all Analog inputs must not go below VSS. Is that correct?

RE: Measuring signals above and below VSS with the ADC

Kenneth — Wed, 12 Jun 2024 19:11:42 GMT

Hi,

I totally agree with you that this was confusing, but I can also find that on the line below where you copied that it does say it's not possible "The AIN0-AIN7 inputs cannot exceed VDD_GPIO, or be lower than VSS":

Honestly speaking I am not entirely sure why there is an ± sign, but it might be because there is an differential mode, where you measure two the differential analog level between two inputs, so I guess it make sense in that mode.

Hope that helps,
Kenneth