PDM Channel swapping at High PDM clock

RE: PDM Channel swapping at High PDM clock

Simonr — Thu, 01 Aug 2024 07:47:05 GMT

Hi again Obaid

So, as I feared this issue seems to be rooted in that the PDM clock frequency doesn't support frequencies this high, and the highest configurable configuration is 1.33 MHz as per the PDM_CLK register and output sampling rate:

Best regards,

Simon

RE: PDM Channel swapping at High PDM clock

Simonr — Wed, 24 Jul 2024 06:47:24 GMT

Hi Obaid

I'm currently investigating the PDM clock frequency as 3.2MHz might be higher than what the PDM peripheral can handle reliably. Will let you know when I hear back internally on this.

Best regards,

Simon

RE: PDM Channel swapping at High PDM clock

Simonr — Mon, 22 Jul 2024 08:42:39 GMT

Hi Obaid,

Just wanted to let you know that I'm back, but that I need to run these outputs by some devs internally before getting back to you with any further suggestions. Thank you for your patience. I'll get back to you by end of week with another update.

Best regards,

Simon

RE: PDM Channel swapping at High PDM clock

Hieu — Fri, 12 Jul 2024 12:04:16 GMT

Hi Obaid,

Simon is unfortunately out of office at the moment. He will return after next week and continue to help you.

Hieu

RE: PDM Channel swapping at High PDM clock

Obaid ur Rehman — Tue, 09 Jul 2024 06:56:19 GMT

HI Simonr sorry for the late reply,
I have captured the oscilloscopes outputs for both cases, In all the images the red graph is clock and blue graph is data line,

Here is the output of the oscilloscope for 1.2MHz clock with 1us divisions

I have also captured the result at 200ns division for 1.2MHz clock

Similarly here is the output for 3.2MHz clock with 1us division

and here is the output at 200ns Division for 3.2MHz clock

I have also uploaded the complete logs on google drive as i cannot upload the files here, so if you want to view the complete logs you can use this Google Drive Link.
Please note that you need picoscope software to view the logs.

Thank you

RE: PDM Channel swapping at High PDM clock

Simonr — Wed, 26 Jun 2024 08:07:48 GMT

Hi again Obaid

Okay, thank you for the clarification. It seems very strange that it would swap like this. Would it be possible for you to use a scope to check the left-right word alignment for both scenarios so we can see if this is the driver that messes up or what. I have asked a bit around but we can't recall seeing this issue in the past unfortunately.

Best regards,

Simon

RE: PDM Channel swapping at High PDM clock

Obaid ur Rehman — Mon, 24 Jun 2024 12:29:53 GMT

Hi, so nothing is wrong with any channels in term of sensitivity or volume, both mics work correctly, however at 3.2MHz the PCM data containing the left and right channel pairs is swapped so when i separate them and plot the STFTs of each channel the Left channel data actually contains the right channel data and vice versa.
To further explain the issue here is an experiment I did.
1. I intentionally made the Left channel Deaf (Covered the Left mic with glue so that its sensitivity will be really low).
2. I took a stereo recording at PDM clock 1.2MHz where I played a 500Hz tone on speaker and plot the STFT of Left and right channel.

3. As expected the left channel is Deaf and the Right channel shows a 500Hz Freq.

4. I repeated the experiment with PDM clock 3.2Mhz, with the same setup (Left mic covered with glue and played a 500 Hz tone).

5. This time the channels have swapped, instead of getting a straight line on the Right channel, I am getting the Line in Left channel . (Left channel was supposed to be deaf and should have nothing in the STFT).
So the data is correct however it is Swapped at 3.2 MHz

RE: PDM Channel swapping at High PDM clock

Obaid ur Rehman — Mon, 24 Jun 2024 11:50:28 GMT

Hi Simonr, Thank you for the reply, I am using PDM Library by Nordic, and I am using NRF5SDK v17.1.0
here is my configuration

ret_code_t err_code;
uint32_t clk_freq = 0x19000000;
nrfx_pdm_config_t config = NRFX_PDM_DEFAULT_CONFIG(PDM_CONFIG_IO_PDM_CLK, PDM_CONFIG_IO_PDM_DATA);
config.gain_l = rec_config.gain;
config.gain_r = rec_config.gain;
config.clock_freq = ( nrf_pdm_freq_t )(clk_freq);
config.edge = PDM_MODE_EDGE_LeftFalling;
config.mode = PDM_MODE_OPERATION_Stereo;
// set ratio to 80x
NRF_PDM->RATIO = 1;

err_code = nrfx_pdm_init(&config, PDM_drv_pdm_handler);
APP_ERROR_CHECK(err_code);
err_code = nrfx_pdm_start();
APP_ERROR_CHECK(err_code);

RE: PDM Channel swapping at High PDM clock

Simonr — Mon, 24 Jun 2024 11:15:40 GMT

I haven't seen this exact issue before, so exactly what is causing the left channel to be off is a bit of guesswork. Could it be that using PPI would help out here perhaps as is recommended for the ADC available here.

Can you provide some more details about what exactly is wrong on the left channel, is the sound higher or just the sensitivity so the output audio is incorrect?

Best regards,

Simon

RE: PDM Channel swapping at High PDM clock

Simonr — Mon, 24 Jun 2024 06:06:33 GMT

Just letting you know that we're currently looking into this issue. What library/driver are you using for PDM here, and what version of the SDK are you using exactly?

Best regards,

Simon