SPIS (SPI Slave interface) Set Up and Hold Timings

RE: SPIS (SPI Slave interface) Set Up and Hold Timings

Håkon Alseth — Tue, 25 Jun 2024 08:26:03 GMT

Hi,

[quote user="David Nix"]However, if I understand you correctly, the SPIS interface of the nRf52833 must detect a transition of the CSN driven by the SPI controller before it will allow a transfer. Is this correct?[/quote]

This is correct.

Kind regards,

Håkon

RE: SPIS (SPI Slave interface) Set Up and Hold Timings

David Nix — Mon, 24 Jun 2024 14:49:28 GMT

Thank you for your prompt reply. Just to be clear, I was asking if the SPI controller (the host) could drive CSN low (assert) indefinitely. However, if I understand you correctly, the SPIS interface of the nRf52833 must detect a transition of the CSN driven by the SPI controller before it will allow a transfer. Is this correct?

RE: SPIS (SPI Slave interface) Set Up and Hold Timings

Håkon Alseth — Mon, 24 Jun 2024 14:40:02 GMT

Hi,

No, it will be locked until a transaction is complete (ie. CSN deasserts):

https://docs.nordicsemi.com/bundle/ps_nrf52833/page/spis.html#ariaid-title4

Kind regards,

Håkon

RE: SPIS (SPI Slave interface) Set Up and Hold Timings

David Nix — Mon, 24 Jun 2024 14:32:41 GMT

May I ask a follow-up question, then? If we assert CS# continuously between bus transfers, will the nRf52833 SPI peripheral (SPIS) still work properly? That would eliminate any timing constraints related to our SPI controller. For example, after initializing the SPI bus, can we driver CS low and leave it low indefinitely - while transferring data as needed?

RE: SPIS (SPI Slave interface) Set Up and Hold Timings

Håkon Alseth — Mon, 24 Jun 2024 12:43:17 GMT

Hi,

Unfortunately, this is the timing limitations of the nRF52(833) SPIS module:

https://docs.nordicsemi.com/bundle/ps_nrf52833/page/spis.html#ariaid-title35

Kind regards,

Håkon