nRF52840 input pin(A12 P0.02 Digital I/O) usage.

RE: nRF52840 input pin(A12 P0.02 Digital I/O) usage.

hmolesworth — Tue, 23 Jul 2024 16:49:31 GMT

If I may add a comment, Digital I/O has internal schottky diode protection to VDD on every I/O pin; if VDD is near 0V (GND) while Digital I/O pin A12 has some voltage above 300mV the schottky diode will conduct and raise VDD which can cause unwanted reset behaviour.

Summary: A12 must be less than VDD to avoid incorrect operation

RE: nRF52840 input pin(A12 P0.02 Digital I/O) usage.

SwRa — Tue, 23 Jul 2024 12:29:57 GMT

Hello,

[quote user="Munkhdelger"]So i just wondering is there any problem with it. [/quote]

Nope.. There are no restrictions. As long as it is within the specs, there would be no issue in doing it the way you do.

Regards,

Swathy

RE: nRF52840 input pin(A12 P0.02 Digital I/O) usage.

Munkhdelger — Wed, 17 Jul 2024 04:11:58 GMT

current circuit works as intended without any problem (VDDH mode) but my circuit built like providing voltage to the Digital I/O when there is no voltage on VDD. So i just wondering is there any problem with it.

RE: nRF52840 input pin(A12 P0.02 Digital I/O) usage.

Search — Fri, 12 Jul 2024 05:20:29 GMT

According to your description, the possible reason is that nRF works in VDDH mode, at which time IO output level can be configured through registers. For specific information, please refer to nRF52840 Product Specification v1.10 -- 5.3.1.2 GPIO levels. Hope the above information is useful to you!

Ref:5.3.1.2 GPIO levels
5.3.1.2 GPIO levels The GPIO high reference voltage is equal to the level on the VDD pin. In Normal Voltage mode, the GPIO high level equals the voltage supplied to the VDD pin. In High Voltage mode, it equals the level specified in register REGOUT0 on page 63.