RE: GPIO bit-banging and BLE radio activity

Droidik — Thu, 18 Jul 2024 11:50:48 GMT

Hello Vidar,

thank you for the insights. For now, I found a workaround that works for my setup: Lock interrupts only for the single SCK signals (25 times 1us lock) instead of a single lock for the whole conversion period (~50us) and it seems that the BLE stack handles it without any crash.
I'll experiment with the SPIM and if it ends well, I'll provide the implementation in the driver.

Thank you very much.

Jan

RE: GPIO bit-banging and BLE radio activity

Vidar Berg — Thu, 18 Jul 2024 08:48:21 GMT

Hello Jan,

Using the timeslot API sounds like a good approach to avoid this problem. I'm not sure if it is feasible to use the SPIM, though it may be worth experimenting with if you want to offload the CPU more. The ADC expects the controller to output 25-27 clock cycles, which does not align with the 8 cycles clocked out for each byte by the SPIM. However, you could generate a clock pulses with the MOSI similar to how it is done in the ws2812 neopixel driver. The question is if the SPIM will be able to receive the data clocked out by the ADC correctly.

Best regards,

Vidar