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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Delay between read and write SPI operation</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/113633/delay-between-read-and-write-spi-operation</link><description>Hello, 
 We are using Zephyr OS and SDK v2.5.0 on nrf52840 chip. We have noticed some delay between spi_write and spi_read of 29&amp;#181;s,which is critical for our goal. Comparing to the bare metal version this delay is reduced to around 4&amp;#181;s. We wanted to know</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 07 Aug 2024 14:08:44 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/113633/delay-between-read-and-write-spi-operation" /><item><title>RE: Delay between read and write SPI operation</title><link>https://devzone.nordicsemi.com/thread/497356?ContentTypeID=1</link><pubDate>Wed, 07 Aug 2024 14:08:44 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b1d24158-2783-4a4b-a21f-617e1367a4cd</guid><dc:creator>Naeem Maroof</dc:creator><description>&lt;p&gt;You are reading 2 bytes, right? If there should come 2 actual bytes on MISO from the sensor then you can configure buffers like this and test again: (please review the code and modify accordingly if you are receiving different amount of data)&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;uint8_t regs[3];
regs[0] = reg_addr;
regs[1] = 0xFF;
regs[2] = 0xFF;
uint8_t readbuf[3];		//3 is used as you are to receive 2 bytes
                        //1st byte received will be dummy byte

struct spi_buf 	tx_spi_buf 		    = {.buf = (void *)&amp;amp;regs, .len = sizeof(regs)};
struct spi_buf_set tx_spi_buf_set	= {.buffers = &amp;amp;tx_spi_buf, .count = 1};
struct spi_buf 	rx_spi_bufs		    = {.buf = readbuf, .len = sizeof(regs)};
struct spi_buf_set rx_spi_buffer_set	= {.buffers = &amp;amp;rx_spi_bufs, .count = 1};

//use spi-transceive or spi-transceive-dt as per your overall code setup
err = spi_transceive_dt(&amp;amp;spispec, &amp;amp;tx_spi_buf_set, &amp;amp;rx_spi_buffer_set);
if (err &amp;lt; 0) {
	LOG_ERR(&amp;quot;spi_transceive_dt() failed, err: %d&amp;quot;, err);
	return err;
}&lt;/pre&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Delay between read and write SPI operation</title><link>https://devzone.nordicsemi.com/thread/497275?ContentTypeID=1</link><pubDate>Wed, 07 Aug 2024 07:43:52 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:45b78802-2dae-4243-83b2-0b3de17b031b</guid><dc:creator>Mahdibs</dc:creator><description>&lt;p&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;    
    const struct spi_buf tx_buf = {
		.buf = &amp;amp;reg_addr,
		.len = 1,
	};
	const struct spi_buf_set tx = {
		.buffers = &amp;amp;tx_buf,
		.count = 1,
	};
    struct spi_buf rx_buf = {
        .buf = reg_data,
        .len = 2,
	};

	const struct spi_buf_set rx = {
		.buffers = &amp;amp;rx_buf,
		.count = 1,
	};&lt;/pre&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Delay between read and write SPI operation</title><link>https://devzone.nordicsemi.com/thread/497219?ContentTypeID=1</link><pubDate>Tue, 06 Aug 2024 17:03:00 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:576467a6-0d98-49a2-9459-4be10493a5fc</guid><dc:creator>Naeem Maroof</dc:creator><description>&lt;p&gt;How you have configured the buffers?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Delay between read and write SPI operation</title><link>https://devzone.nordicsemi.com/thread/497158?ContentTypeID=1</link><pubDate>Tue, 06 Aug 2024 12:38:46 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b927e8f3-8e24-4792-81f1-b5bd71693c77</guid><dc:creator>Mahdibs</dc:creator><description>&lt;p&gt;Thank you for your reply.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;I have tried with spi transceive and I got a wrong rx data but the timing is better:&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;rc |= spi_transceive(spi_spec-&amp;gt;bus, &amp;amp;spi_spec-&amp;gt;config, &amp;amp;tx, &amp;amp;rx);&lt;/pre&gt;&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:191px;max-width:642px;" height="191" src="https://devzone.nordicsemi.com/resized-image/__size/1284x382/__key/communityserver-discussions-components-files/4/pastedimage1722944288702v1.png" width="642" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;I also tried 2 spi &lt;span&gt;transceive&amp;nbsp;&lt;/span&gt;like the following, and I got the same result as separate write and read which is obvious since the spi write and read are based on the spi &lt;span&gt;transceive&lt;/span&gt;.&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;    rc |= spi_transceive(spi_spec-&amp;gt;bus, &amp;amp;spi_spec-&amp;gt;config, &amp;amp;tx, NULL);
    rc |= spi_transceive(spi_spec-&amp;gt;bus, &amp;amp;spi_spec-&amp;gt;config, NULL, &amp;amp;rx);&lt;/pre&gt;&amp;nbsp;&amp;nbsp;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;I&amp;#39;m trying to implement nrfx in my project, I&amp;#39;ll post update once done.&lt;br /&gt;&lt;br /&gt;Thanks&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Delay between read and write SPI operation</title><link>https://devzone.nordicsemi.com/thread/497103?ContentTypeID=1</link><pubDate>Tue, 06 Aug 2024 08:15:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:dc72e9f1-2c12-41fa-b01e-ad8ea49d4b20</guid><dc:creator>Naeem Maroof</dc:creator><description>&lt;p&gt;Have you tried with spi transceive function rather than a separate write and read?&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Otherwise, you could use nrfx as the delay might be unavoidable due to zephyr layer.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>