https://devzone.nordicsemi.com/f/nordic-q-a/114640/gpio-pin-states-in-pin-resetIn the nrf5340 Product Specification, the GPIO registers OUT, DIR, LATCH, DETECTMODE, DETECTMODE_SEC, and PIN_CNF[n] are all labeled as &quot;Retained Registers&quot;. The definition of a retained register according to section 4.10.8 is the following: &quot;A retaineden-USTelligent Community 13Wed, 11 Sep 2024 11:23:01 GMThttps://devzone.nordicsemi.com/thread/502095?ContentTypeID=1Wed, 11 Sep 2024 11:23:01 GMT137ad170-7792-4731-bb38-c0d22fbe4515:90524ac5-ce7a-4f2e-8274-4f61aeef918bKenneth<p>Hello,</p> <p>Think the confusion here may come from what happens upon release of reset,&nbsp;so when pin reset is de-asserted the program will run from start of program execution, and the gpio peripheral is then reset, it&#39;s not necessarily the case that the pins will be reset when reset pin is asserted. While the pin reset is asserted it&#39;s likely a bit undefined what the behavior is, e.g. depending on the pins are controlled by a serial peripheral (e.g. spi, uart etc) or directly by the gpio peripheral. It&#39;s not intended to keep the pin reset asserted for a long period of time, since the current consumption can also be up to active current during this period.</p> <p>Kenneth</p><div style="clear:both;"></div>