OFF mode and GPIOs ??

RE: OFF mode and GPIOs ??

Håkon Alseth — Tue, 08 Oct 2024 07:38:17 GMT

Hi,

Glad to hear that you have found the root-cause of the higher current consumption. Please let me know if you run into any other issues or have questions. Hope you have a wonderful day!

Kind regards,

Håkon

RE: OFF mode and GPIOs ??

Pierre Landau — Mon, 07 Oct 2024 21:27:13 GMT

I'm reaching out to the vendor of the chip: I tracked it to one GPIO line, which drives a transistor connected to the enable pin of a chip.The transistor (and the enable pin) are pulled up with a 1M resistor, though a safer design might have been to make the thing default-off. To turn off the device, we set a logic 1 which turns on the transistor tied to ground. It's sort of unusual for the Enable pin of any chip to source that much current, so I'm hoping they have an answer. It appears that my changes since I posted the question have confirmed that the CPU is able to go into OFF mode, and that what I'm seeing is an external process. - I apologize for not withdrawing this question

RE: OFF mode and GPIOs ??

Håkon Alseth — Mon, 07 Oct 2024 14:06:25 GMT

Hi,

The state of the GPIOs is latched when going into systemoff mode.

This means that the state set in the NRF_GPIO structure will determine what each GPIO is configured for.

That being said; if there are bus peripherals that has previously used a GPIO, like UART/TWI/SPI, then the level must be defined before going to system off mode. This is because each bus peripheral will claim a pin, and override the configuration, and when going to system off, the bus peripheral releases the pin.

[quote user=""]However, if I have one GPIO left to output mode (with no load connected) before calling sd_power_system_off(), the ammeter is showing 1.04mA, which is a lot more than makes any sense. At that point, I've already shut down BLE connections, advertising, and ADC processes. [/quote]

Is all other pins connected to external circuitry set to a defined level?

Kind regards,

Håkon