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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>TWI slave</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/115518/twi-slave</link><description>I am building a TWI slave with nRF52832. 
 I am attaching a part of twis_event_handler. 
 I can read even a 1-byte register value by executing i2c_read_register(SLAVE_ADDR, 0x11, &amp;amp;data); from the master side, but when I execute i2c_write_register(SLAVE_ADDR</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 28 Oct 2024 13:06:27 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/115518/twi-slave" /><item><title>RE: TWI slave</title><link>https://devzone.nordicsemi.com/thread/508157?ContentTypeID=1</link><pubDate>Mon, 28 Oct 2024 13:06:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:834dfd9d-ff49-46f2-a99d-9b866c7723b8</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;Have you taken a look at the twi slave example?&lt;br /&gt;&lt;a href="https://docs.nordicsemi.com/bundle/sdk_nrf5_v17.1.0/page/twi_master_with_twis_slave_example.html"&gt;https://docs.nordicsemi.com/bundle/sdk_nrf5_v17.1.0/page/twi_master_with_twis_slave_example.html&lt;/a&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This example emulate an I2C eeprom, so I would think reading and writing is supported.&lt;/p&gt;
&lt;p&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI slave</title><link>https://devzone.nordicsemi.com/thread/507920?ContentTypeID=1</link><pubDate>Fri, 25 Oct 2024 11:45:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e2bdd1b0-0a22-4e6b-a654-e2908129d4e7</guid><dc:creator>Junichi</dc:creator><description>&lt;p&gt;The TWI slave handler is created and executed as follows:&lt;/p&gt;
&lt;p&gt;void twis_event_handler(nrf_drv_twis_evt_t const * p_event)&lt;br /&gt;{&lt;br /&gt;static bool address_received = false; // Track whether the register address was received&lt;/p&gt;
&lt;p&gt;switch (p_event-&amp;gt;type)&lt;br /&gt;{&lt;br /&gt;case NRFX_TWIS_EVT_READ_REQ:&lt;br /&gt;// If there is a read request from the master&lt;br /&gt;nrf_drv_twis_tx_prepare(&amp;amp;m_twis, &amp;amp;m_twi_register[m_register_address], TWI_BUFFER_SIZE - m_register_address);&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Read request: register address = 0x%02X&amp;quot;, m_register_address);&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;case NRFX_TWIS_EVT_WRITE_REQ:&lt;br /&gt;if (!address_received) {&lt;br /&gt;// If the register address has not yet been received, prepare to receive the register address&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Preparing to receive register address...&amp;quot;);&lt;br /&gt;nrf_drv_twis_rx_prepare(&amp;amp;m_twis, &amp;amp;m_register_address, 1);&lt;br /&gt;} else {&lt;br /&gt;// If register address received, prepare to write data&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Register address received: 0x%02X&amp;quot;, m_register_address);&lt;br /&gt;if (m_register_address &amp;lt; TWI_BUFFER_SIZE) {&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Preparing to write data to register 0x%02X&amp;quot;, m_register_address);&lt;br /&gt;nrf_drv_twis_rx_prepare(&amp;amp;m_twis, &amp;amp;m_twi_register[m_register_address], TWI_BUFFER_SIZE - m_register_address);&lt;br /&gt;} else {&lt;br /&gt;NRF_LOG_ERROR(&amp;quot;Invalid register address: 0x%02X&amp;quot;, m_register_address);&lt;br /&gt;}&lt;br /&gt;}&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;case NRFX_TWIS_EVT_WRITE_DONE:&lt;br /&gt;if (!address_received) {&lt;br /&gt;// If register address was received&lt;br /&gt;address_received = true; // Set flag&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Register address 0x%02X received&amp;quot;, m_register_address);&lt;br /&gt;} else {&lt;br /&gt;// If data was written&lt;br /&gt;address_received = false; // Reset flag&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Data written to register 0x%02X: 0x%02X&amp;quot;, m_register_address, m_twi_register[m_register_address]);&lt;br /&gt;}&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;case NRFX_TWIS_EVT_READ_DONE:&lt;br /&gt;NRF_LOG_INFO(&amp;quot;Read completed&amp;quot;);&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;case NRFX_TWIS_EVT_READ_ERROR:&lt;br /&gt;NRF_LOG_ERROR(&amp;quot;TWIS EVT READ ERROR&amp;quot;);&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;case NRFX_TWIS_EVT_WRITE_ERROR:&lt;br /&gt;NRF_LOG_ERROR(&amp;quot;TWIS EVT WRITE ERROR&amp;quot;);&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;case NRFX_TWIS_EVT_GENERAL_ERROR:&lt;br /&gt;NRF_LOG_ERROR(&amp;quot;TWIS EVT GENERAL ERROR&amp;quot;);&lt;br /&gt;break;&lt;/p&gt;
&lt;p&gt;default:&lt;br /&gt;break;&lt;br /&gt;}&lt;br /&gt;}&lt;/p&gt;
&lt;p&gt;Read works fine from the master side, but Write gives NRFX_TWIS_EVT_GENERAL_ERROR&lt;br /&gt;and does not write to the register properly.&lt;br /&gt;Please tell me the problem with the source.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI slave</title><link>https://devzone.nordicsemi.com/thread/506292?ContentTypeID=1</link><pubDate>Tue, 15 Oct 2024 11:30:05 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:178a9970-fa30-4826-a74e-35dbb47e2093</guid><dc:creator>Turbo J</dc:creator><description>&lt;p&gt;The code shown &lt;em&gt;is&lt;/em&gt; incomplete, but I missed it when glancing over it.&lt;/p&gt;
&lt;p&gt;The idea is to give the WRITE_REQ event a bigger buffer than one byte - and then to handle it in the &amp;quot;WRITE_DONE&amp;quot; event when there was &amp;gt;1 byte transmitted.&lt;/p&gt;
&lt;p&gt;I recommend an oscilloscope / logic analyser. You should have seen the NACK&amp;nbsp; in the write transaction on the bus since the buffer was too small.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI slave</title><link>https://devzone.nordicsemi.com/thread/506270?ContentTypeID=1</link><pubDate>Tue, 15 Oct 2024 10:45:37 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:508e01f7-b5c1-4794-8c63-25cfae9c2b7f</guid><dc:creator>Junichi</dc:creator><description>&lt;p&gt;Thank you for your answer.&lt;/p&gt;
&lt;p&gt;Please give me a bit more detail.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI slave</title><link>https://devzone.nordicsemi.com/thread/506250?ContentTypeID=1</link><pubDate>Tue, 15 Oct 2024 08:27:09 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:82f38257-626c-4b18-b9b8-b77c9f7fcaa8</guid><dc:creator>Turbo J</dc:creator><description>&lt;p&gt;Error is in code not shown.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>