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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nrf5340 SPI 32MHz, HFCLK128M 128MHz and QSPI usage</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/116768/nrf5340-spi-32mhz-hfclk128m-128mhz-and-qspi-usage</link><description>Hello, 
 
 We have a Nor flash connected to the QSPI and another peripheral connected to the classic SPI. 
 Due to the errata [159] , the HFCLK128M is running at 64MHz and so the SPI is running at 16MHz. 
 
 We want to increase the processing performance</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 27 Nov 2024 15:19:45 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/116768/nrf5340-spi-32mhz-hfclk128m-128mhz-and-qspi-usage" /><item><title>RE: nrf5340 SPI 32MHz, HFCLK128M 128MHz and QSPI usage</title><link>https://devzone.nordicsemi.com/thread/512416?ContentTypeID=1</link><pubDate>Wed, 27 Nov 2024 15:19:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ae500429-06d9-41b8-9d10-189ed97525a3</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Sorry, since you mention SPI at 16MHz, you are ofcourse referring to the high-speed SPI4. My apologies for&amp;nbsp;my mix up.&lt;/p&gt;
&lt;p&gt;SPIM4 can run on 32 MHz, but only if the HFCLK128M is used.&lt;/p&gt;
[quote user="tcube"]What happens if the nrf5340 SPI starts a transaction à 32Mhz and changes the&amp;nbsp;&lt;span&gt;HFCLK128M&amp;nbsp;to 64MHz to start a QSPI transaction?&lt;/span&gt;[/quote]
&lt;p&gt;The clock will continue to run at configured frequency, but it is not a supported combination and there is not guaranteed to work. If running SPIM4 at 32 MHz, the CPU must&amp;nbsp;be configured&amp;nbsp;at 128 MHz.&lt;/p&gt;
&lt;p&gt;If you are asynchronously (with respect to the SPIM4 handling) switching CPU frequency, then I would recommend that you lower&amp;nbsp;SPIM4 to 16 MHz.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nrf5340 SPI 32MHz, HFCLK128M 128MHz and QSPI usage</title><link>https://devzone.nordicsemi.com/thread/512398?ContentTypeID=1</link><pubDate>Wed, 27 Nov 2024 14:31:03 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3e0a67b0-5c22-43e6-b4e5-e9d28aab9cff</guid><dc:creator>tcube</dc:creator><description>&lt;p&gt;A last&amp;nbsp;question for my understanding:&lt;br /&gt;Configuring the SPI to 32MHz requires the&amp;nbsp;HFCLK128M to be at 128MHz.&lt;br /&gt;What happens if the nrf5340 SPI starts a transaction &amp;agrave; 32Mhz and changes the&amp;nbsp;&lt;span&gt;HFCLK128M&amp;nbsp;to 64MHz to start a QSPI transaction? Does the SPI clock remain at 32 Mhz?&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nrf5340 SPI 32MHz, HFCLK128M 128MHz and QSPI usage</title><link>https://devzone.nordicsemi.com/thread/512380?ContentTypeID=1</link><pubDate>Wed, 27 Nov 2024 13:51:02 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:27dc4196-0016-464e-af8a-f00d32fd7bf0</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
[quote user=""]Can we change the HFCLK128M&amp;nbsp;speed to 64MHz before any access to the QSPI and restore it to 128MHz when it&amp;#39;s finished?[/quote]
&lt;p&gt;Yes, it is designed to be performed at any time (except for scenarios given in the errata you pointed to), as stated here:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title3"&gt;https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title3&lt;/a&gt;&lt;/p&gt;
[quote user=""]Is this can have a negative impact (corrupted data) on SPI, I2C, or BLE if we change the core clock during a transaction?[/quote]
&lt;p&gt;This changes the scaling to the CPU, not the peripheral clocks.&lt;/p&gt;
&lt;p&gt;The PCLK nets listed here will remain to whichever configuration they are set to use:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title2"&gt;https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title2&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>