How to change nRF54L15DK sram size

RE: How to change nRF54L15DK sram size

arslan — Fri, 18 Apr 2025 04:58:46 GMT

Thanks! Worked for me!!!

RE: How to change nRF54L15DK sram size

DmytroSes — Thu, 17 Apr 2025 19:04:39 GMT

Hello! Yes, some of the RAM is used by the FLPR core by default. You need to change it in your device tree. See my ticket here.

RE: How to change nRF54L15DK sram size

marcoster — Thu, 17 Apr 2025 14:41:55 GMT

I also just stumbled over this - we're still fine with the usage (~90kB) but still it irritates me somehow...

RE: How to change nRF54L15DK sram size

arslan — Thu, 17 Apr 2025 12:34:42 GMT

I am also stuck here. Did you have any update on this?

RE: How to change nRF54L15DK sram size

DmytroSes — Mon, 27 Jan 2025 15:51:46 GMT

Hello! I have the similar issue. However, I use Partition manager, instead of defining partitions in a devicetree. In the pm_static.yml i declare the following:

sram_primary:
  address: 0x20000000
  end_address: 0x20040000
  region: sram_primary
  size: 0x40000

But at the end of a build I get a memory report, that says 188kB of RAM is available. During build, I see, that it uses the pm_static.yml file, so I assume, that the build system uses partition manager.
What is the correct way to use the whole RAM region for the cpuapp with Partition manager?

RE: How to change nRF54L15DK sram size

loquat — Mon, 09 Dec 2024 05:19:30 GMT

OK.Thanks.

Very good.

RE: How to change nRF54L15DK sram size

Kazi Afroza Sultana — Wed, 04 Dec 2024 12:42:06 GMT

Hello,

I think you can either delete the FLPR part and adding the entire 256kB for SRAM or set the allocation zero for FLPR (if deleting is not allowed).

For the first one, you need to increase the RAM size range. Currently, it is set to 0x2F000 for cpuapp, which corresponds to 168k and 0x11000 for cpuflpr, which corresponds to 68k.

You can edit the rf54l15.dtsi file in following way:

cpuapp_sram: memory@20000000 {
      compatible = "mmio-sram";
      reg = <0x20000000 DT_SIZE_K(256)>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0x0 0x20000000 0x40000>;
    };

 

    cpuflpr_sram: memory@20040000 {
      compatible = "mmio-sram";
      reg = <0x20040000 DT_SIZE_K(0)>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0x0 0x20040000 0x00000>;
    };

cpuapp_sram: memory@20000000 {
			compatible = "mmio-sram";
			reg = <0x20000000 DT_SIZE_K(256)>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x20000000 0x40000>;
		};