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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SPI and UART configurations</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/117220/spi-and-uart-configurations</link><description>Dear Customer Support, 
 Reaching out for help / example on couple peripheral configurations 
 We are using nRF Connect 2.5.0 
 1-UART 
 we have the following configuration 
 
 uart1_default: uart1_default { 
 group1 { 
 psels = &amp;lt; NRF_PSEL ( UART_TX </description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 19 Dec 2024 19:27:15 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/117220/spi-and-uart-configurations" /><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/515819?ContentTypeID=1</link><pubDate>Thu, 19 Dec 2024 19:27:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8dcdacd3-1959-449f-b466-e3d6601745e5</guid><dc:creator>Jamal_nRF</dc:creator><description>&lt;p&gt;Update: your recommendation is working on multiple test boards as expected.&lt;/p&gt;
&lt;p&gt;Thank you for your good support&lt;/p&gt;
&lt;p&gt;Ticket may be closed&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/515164?ContentTypeID=1</link><pubDate>Mon, 16 Dec 2024 15:15:39 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:7b635dee-3a85-48ed-bdb0-8f8d84caf888</guid><dc:creator>Jamal_nRF</dc:creator><description>&lt;p&gt;Hello Hieu,&lt;/p&gt;
&lt;p&gt;Your recommendation on group1 / UART-TX configuration seems to provide desirable outcome.&lt;/p&gt;
&lt;p&gt;We are in the process of testing on multiple test boards to assess stability...&lt;/p&gt;
&lt;p&gt;Will back to you later today if any more questions...&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/514958?ContentTypeID=1</link><pubDate>Fri, 13 Dec 2024 17:23:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a55e77bc-1348-4b45-a4b1-c5785a80e419</guid><dc:creator>Hieu</dc:creator><description>&lt;p&gt;Hi Jamal_nRF,&lt;/p&gt;
&lt;p&gt;Once again my apology for my previous unhelpful replies. I&amp;nbsp;have&amp;nbsp;not&amp;nbsp;touched this topic for far too long and clearly my knowledge has developed severe holes.&lt;/p&gt;
&lt;p&gt;True open drain is not possible with the nRF52840, and you can only achieve a quasi-open-drain configuration by disabling all bias/pulls and setting drive mode to S0D1.&lt;br /&gt;Below is how you can configure that in DeviceTree:&lt;/p&gt;
&lt;div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;amp;uart1_default {&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; group1 {&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; psels = &amp;lt;NRF_PSEL(UART_TX, 0, 20)&amp;gt;;&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; bias-disable;&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; nordic,drive-mode = &amp;lt;NRF_DRIVE_S0D1&amp;gt;;&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; };&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; group2 {&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; psels = &amp;lt;NRF_PSEL(UART_RTS, 0, 21)&amp;gt;;&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; };&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; group3 {&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; psels = &amp;lt;NRF_PSEL(UART_RX, 0, 22)&amp;gt;,&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;lt;NRF_PSEL(UART_CTS, 0, 23)&amp;gt;;&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; bias-pull-down;&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;&amp;nbsp; &amp;nbsp; };&lt;/span&gt;&lt;/div&gt;
&lt;div&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;};&lt;/span&gt;&lt;/div&gt;
&lt;/div&gt;
&lt;p&gt;Without a bias property, there is no bias by default, so &lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;bias-disable&lt;/span&gt; is optional.&lt;/p&gt;
&lt;p&gt;Note that not while P0.20, which you chose for UART_TX, can support S0D1, not all pins can.&amp;nbsp;&lt;br /&gt;Refer to &lt;a href="https://docs.nordicsemi.com/bundle/ps_nrf52840/page/pin.html"&gt;the Pin Assignment section of the Product Specification&lt;/a&gt; for more information.&lt;/p&gt;
&lt;p&gt;Please refer to these cases for more information on limitation of the quasi open drain configuration.&lt;/p&gt;
&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/28373/nrf52810-open-drain-gpio"&gt;https://devzone.nordicsemi.com/f/nordic-q-a/28373/nrf52810-open-drain-gpio&lt;br /&gt;&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/40629/nrf52840-open-drain-gpio"&gt;https://devzone.nordicsemi.com/f/nordic-q-a/40629/nrf52840-open-drain-gpio&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Hieu&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/514950?ContentTypeID=1</link><pubDate>Fri, 13 Dec 2024 16:25:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ff029ae4-d87b-49b7-be34-5f5add6bb46e</guid><dc:creator>Hieu</dc:creator><description>&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;Sorry I started using a different term and created confusion. No bias is no pull up or pull down, so it&amp;#39;s open drain.&lt;/span&gt;&lt;br /&gt;My apology again, I had some misunderstanding of the internal pin behavior. I will update you soon.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/514929?ContentTypeID=1</link><pubDate>Fri, 13 Dec 2024 15:04:02 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d1c3ddba-a435-40a2-ad44-0b2dea6b6d9d</guid><dc:creator>Jamal_nRF</dc:creator><description>&lt;p&gt;Unfortunately, that does NOT answer my question&lt;/p&gt;
&lt;p&gt;I was not asking about setting a bias for the UART / TX line&lt;/p&gt;
&lt;p&gt;I was rather asking about setting the TX line to OPEN DRAIN&lt;/p&gt;
&lt;p&gt;Thank you&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/514874?ContentTypeID=1</link><pubDate>Fri, 13 Dec 2024 10:47:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ff2ecffc-f1a2-438d-9686-a40de595a622</guid><dc:creator>Hieu</dc:creator><description>&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;Hi Jamal_nRF,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;Referring to &lt;a href="https://docs.nordicsemi.com/bundle/ncs-2.8.0/page/nrf/app_dev/config_and_build/hardware/pin_control.html"&gt;the Pin Control documentation&lt;/a&gt;, when no bias is specified, the pins will be configured without bias.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;As the TX pin is in group 1, and neither the pin nor the group has any bias specified, it will have no bias by default.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;If you want to be extra sure, simply add a&amp;nbsp;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;bias-disable&lt;/span&gt; property to the pin group.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;Edit: using &lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;bias-disable&lt;/span&gt; doesn&amp;#39;t seem to matter as of NCS v2.8.0.&amp;nbsp;Only &lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;bias-pull-down&lt;/span&gt; and &lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;bias-pull-up&lt;/span&gt; result in any particular configuration. Both &lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;bias-disable&lt;/span&gt; and an absence of bias property result in no pull configured. See:&amp;nbsp;&lt;a href="https://github.com/nrfconnect/sdk-zephyr/blob/v3.7.99-ncs1/soc/nordic/common/pinctrl_soc.h#L69-L86"&gt;https://github.com/nrfconnect/sdk-zephyr/blob/v3.7.99-ncs1/soc/nordic/common/pinctrl_soc.h#L69-L86&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="text-decoration:line-through;"&gt;Hieu&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/514801?ContentTypeID=1</link><pubDate>Thu, 12 Dec 2024 16:34:25 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:19c474ae-1627-4944-91bb-d80ce04e397f</guid><dc:creator>Jamal_nRF</dc:creator><description>&lt;p&gt;Ok, understood&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;How about the first question on the UART configuration?&lt;/p&gt;
&lt;p&gt;we want to configure the TX line P0.20 to be OPEN_DRAIN&lt;/p&gt;
&lt;p&gt;Thank you&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI and UART configurations</title><link>https://devzone.nordicsemi.com/thread/514748?ContentTypeID=1</link><pubDate>Thu, 12 Dec 2024 13:19:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:62bae9a9-5423-47b1-b6ee-cb6d36b70ed3</guid><dc:creator>Susheel Nuguru</dc:creator><description>[quote user=""]&lt;p&gt;&lt;a href="https://docs.zephyrproject.org/2.5.0/reference/devicetree/bindings/nordic,nrf-spi.html?highlight=miso%20pull%20up"&gt;https://docs.zephyrproject.org/2.5.0/reference/devicetree/bindings/nordic,nrf-spi.html?highlight=miso%20pull%20up&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;by adding this property&lt;/p&gt;
&lt;p&gt;miso-pull-down&lt;/p&gt;
&lt;p&gt;Unfortunately, we get this compile error&lt;/p&gt;
&lt;p&gt;devicetree error: &amp;#39;miso-pull-down&amp;#39; appears in /soc/spi@40004000 in C:/GitAV/AutoVentive/application/build_P1/zephyr/zephyr.dts.pre, but is not declared in &amp;#39;properties:&amp;#39; in C:/GitAV/AutoVentive/external/zephyr/dts/bindings\spi\nordic,nrf-spi.yaml&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Please advise how to proceed...&lt;/p&gt;[/quote]
&lt;p&gt;NCSv2.5.0 is not the same as Zephyr RTOS v2.5.0.&lt;/p&gt;
&lt;p&gt;As you can see in the &lt;a href="https://github.com/nrfconnect/sdk-nrf/blob/v2.5.0/west.yml"&gt;west.yml&lt;/a&gt; file of nrf connect sdkv2.5.0 The zephyr version used is v3.4.99-ncs1(same as 3.5.0)&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;- name: zephyr
      repo-path: sdk-zephyr
      revision: v3.4.99-ncs1
      import:&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;And if you look at the documentation for &lt;a href="https://docs.zephyrproject.org/3.5.0/build/dts/api/bindings/spi/nordic,nrf-spi.html#nordic-nrf-spi"&gt;nrf-spi in this version&amp;nbsp;&lt;/a&gt;&amp;nbsp;you will see that you do not have this property anymore as things are done in pinctrl now.&lt;/p&gt;
&lt;p&gt;You can probably do this (untested and copied from other post)&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;&amp;amp;spi1 {
    compatible = &amp;quot;nordic,nrf-spi&amp;quot;;
    status = &amp;quot;okay&amp;quot;;
    pinctrl-0 = &amp;lt;&amp;amp;spi1_default&amp;gt;;
    pinctrl-1 = &amp;lt;&amp;amp;spi1_sleep&amp;gt;;
    pinctrl-names = &amp;quot;default&amp;quot;, &amp;quot;sleep&amp;quot;;
};

pinctrl {
    spi1_default: spi1_default {
        group1 {
            psels = &amp;lt;NRF_PSEL(SPIM_SCK, PIN_SCK)&amp;gt;,  // not sure if you mentioned SPI pin numbers
                    &amp;lt;NRF_PSEL(SPIM_MOSI, PIN_MOSI)&amp;gt;,
                    &amp;lt;NRF_PSEL(SPIM_MISO, PIN_MISO)&amp;gt;;
            bias-pull-down; // Configure pull-down on pins
        };
    };

    spi1_sleep: spi1_sleep {
        group1 {
            psels = &amp;lt;NRF_PSEL(SPIM_SCK, PIN_SCK)&amp;gt;, 
                    &amp;lt;NRF_PSEL(SPIM_MOSI, PIN_MOSI)&amp;gt;, 
                    &amp;lt;NRF_PSEL(SPIM_MISO, PIN_MISO)&amp;gt;;
            bias-disable; 
        };
    };
};&lt;/pre&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>