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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>How to limit QSPI to 48 MHz on the nRF7002DK / nRF5340?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/117820/how-to-limit-qspi-to-48-mhz-on-the-nrf7002dk-nrf5340</link><description>The nRF7002DK board has a Vdd of 1.8 V, unlike every other Nordic board I&amp;#39;ve seen which use 3.3V. I assume this is due to the nRF5340 errata that state that the QSPI bus (used to connect to the nRF7002) doesn&amp;#39;t function properly at 96 MHz for Vdd &amp;gt; 2</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 08 Jan 2025 10:05:49 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/117820/how-to-limit-qspi-to-48-mhz-on-the-nrf7002dk-nrf5340" /><item><title>RE: How to limit QSPI to 48 MHz on the nRF7002DK / nRF5340?</title><link>https://devzone.nordicsemi.com/thread/517424?ContentTypeID=1</link><pubDate>Wed, 08 Jan 2025 10:05:49 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:438e9534-0663-408e-b36a-d870f7be5f5e</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;There are two different clocks, one that goes into the QSPI (PCLK), and the actual QSPI output.&lt;/p&gt;
&lt;p&gt;The PCLK, controlled in&amp;nbsp;CLOCK domain, is 192 MHz, which can be divided by 1, 2, or 4, providing 192/96/48 MHz options.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Switching the PCLK to 48 MHz is a requirement in order to obtain a low current consumption in sleep, as explained here:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title3"&gt;https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title3&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;In addition to #133 and #136, there is this erratum #159:&amp;nbsp;&lt;a href="https://docs.nordicsemi.com/bundle/errata_nRF5340_Rev1/page/ERR/nRF5340/Rev1/latest/anomaly_340_159.html"&gt;https://docs.nordicsemi.com/bundle/errata_nRF5340_Rev1/page/ERR/nRF5340/Rev1/latest/anomaly_340_159.html&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
[quote user=""]I assume this is due to the&amp;nbsp;nRF5340 errata that state that the QSPI bus (used to connect to the nRF7002) doesn&amp;#39;t function properly at 96 MHz for Vdd &amp;gt; 2.0 V.&amp;nbsp; Another errata states that the radio performance (both BT and Wi-Fi?) is significantly degraded with 96 MHZ QSPI at a higher voltage.&amp;nbsp; See:[/quote]
&lt;p&gt;This is related to the nRF5340 radio performance.&lt;/p&gt;
[quote user=""]How can I set the&amp;nbsp;QSPI clock high frequency with the nRF Connect SDK?&amp;nbsp; I see that the device tree sets sck-frequency = 24 MHz, but it looks like the driver code boosts that during some operations (to 96 MHz I believe - I don&amp;#39;t have a fast scope handy).&amp;nbsp; Is there a user setting that will affect the boosted frequency, or is that buried in the driver code?[/quote]
&lt;p&gt;The QSPI output speed is set in device tree.&lt;/p&gt;
&lt;p&gt;The qspi driver in NCS will handle &amp;quot;active&amp;quot; and &amp;quot;inactive&amp;quot; (ie. for low power mode), as per the above linked errata #159. This means that when the QSPI is active, it will run on PCLK != 48 MHz.&lt;/p&gt;
[quote user=""]Wi-Fi throughput is critical to us, so I would like to see how our application is affected by using 48 MHz instead of 96 MHz for the QSPI.&amp;nbsp; If the system throughput is not affected much, it might be better for us to run at 48 MHz to allow the use of 3.3V serial ports.[/quote]
&lt;p&gt;The QSPI output speed is limited by the nRF7002 in this case.&amp;nbsp;Due to the different erratas related to the QSPI, we strongly recommend to use &amp;lt; 2.0V IO voltage.&lt;/p&gt;
&lt;p&gt;If you need 3.3V operation, SPI operation can be used, but this will lower the overall throughput.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>