DC/DC power consumption peaks after TX

RE: DC/DC power consumption peaks after TX

run_ar — Tue, 16 Feb 2016 08:43:10 GMT

I assume they are caused by the dcdc beeing turned off / coupled to the battery, so you will get a power distribution between the capacitors on the power source and the one on the dcdc. What power source are you testing with? If you test wuth a battery as source I would expect the spike to be reduced due to the internal resistance in the battery.

You should not use the dcdc with the second revision chip as it could affect radio performance. Regardless I would recommend using the latest revision ic for development as this is also the chip revision you will be able to buy for productions.

RE: DC/DC power consumption peaks after TX

Sven — Fri, 12 Feb 2016 19:31:10 GMT

Ok thanks, good to know, are you able to elaborate more? Is there somewhere (like PAN) said something about this?

Still, from a perspective of engineering, what those peaks could be caused of?

RE: DC/DC power consumption peaks after TX

run_ar — Fri, 12 Feb 2016 15:18:50 GMT

This is a rev 2 IC. So the dc/dc is not really supporter when running the softdevice.

RE: DC/DC power consumption peaks after TX

Sven — Fri, 12 Feb 2016 10:16:40 GMT

The full revision - QFAAE0

RE: DC/DC power consumption peaks after TX

run_ar — Fri, 12 Feb 2016 10:10:39 GMT

What is the build code on this chip? QAAA??