RE: nRF54L15-CAAA Reference Design Questions

Jennifer Gibbs — Tue, 04 Feb 2025 20:18:59 GMT

Thank you!

RE: nRF54L15-CAAA Reference Design Questions

JONATHAN LL — Mon, 03 Feb 2025 14:45:16 GMT

Hi there Jennifer,

[quote user=""]Additionally, the reference schematic makes note that the matching components are preliminary and subject to change. [/quote]

For the latest version of the schematic dated 12.12.2024, V0.4. There is not expected to be major changes but some minor changes to the component values. And it is the same as the one you link to here.

So its not finalized and changes is still expected, but what we have now should be ok.

[quote user=""]he nRF54L15-CAAA reference designs currently show an 8 layer board which includes 2 GND layers that seem redundant and possibly unnecessary? Can someone confirm that the -CAAA can be done on a 6 layer board, removing 2 of the 3 stacked internal GND layers?[/quote]

using 6 layers you will loose access to one GPIO pin if the customer use a similar stack up as we have. Currently if we where to go fro 6 layers then there will be limits to what the production capabilities.
So with changes in PCB thickness it can be possible as you could then be able to stack micro vias or not drill through the core of the PCB in the same way that is limiting us wit the current setup. Drilling though the core requires a bigger\thicker drill and that will compromise other things so it is a no go and therefore a single GPIO will be lost if going down to a 6 layer design from 8.

So if going for a 6 layer variant then P2.08 will be inaccessible.

From mid layer 3 in the 8 layer design.

But customer can use 6 layers if they want. It is also possible to go lower, but then more pins will be inaccessible and its difficult to choose what is best, so we dont have any examples for this as of now at least. many complex options to consider and it will depend a lot on use case what would be the best.

Regards,
Jonathan