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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Confusion with chip revision</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/118766/confusion-with-chip-revision</link><description>Hello, 
 
 I am using the nRF52832 WLCSP with the imprint &amp;quot;N52832 CIAAE0 2207A5&amp;quot;, and my FICR reports a codepage size ox 0x400 and a code size of 0x100. This results in a size of 256 KB, right? 
 
 After looking at the compatibility matrix here I am left</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 10 Feb 2025 11:57:35 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/118766/confusion-with-chip-revision" /><item><title>RE: Confusion with chip revision</title><link>https://devzone.nordicsemi.com/thread/522174?ContentTypeID=1</link><pubDate>Mon, 10 Feb 2025 11:57:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b2624b23-3424-4517-a0a2-55a20d57a7ab</guid><dc:creator>Vidar Berg</dc:creator><description>&lt;p&gt;It happens. I&amp;#39;m glad you figured it out and took the time to update the ticket. Thank you.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Confusion with chip revision</title><link>https://devzone.nordicsemi.com/thread/522087?ContentTypeID=1</link><pubDate>Sat, 08 Feb 2025 21:15:50 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:766ab3cd-6331-4581-9f6f-2c4ade2c03bc</guid><dc:creator>Daniel Dakhno</dc:creator><description>&lt;p&gt;Oh, I had another chip on the SWD bus...&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>