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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF54L15: 32 MHz dual QSPI/SPI devices</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/119416/nrf54l15-32-mhz-dual-qspi-spi-devices</link><description>I am currently in the scoping phase for a product that saves high frequency data to an external SPI flash chip and dumps that data over Wi-Fi once it returns to an area covered by an Access Point. For power efficiency reasons, it is desirable to complete</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Sun, 02 Mar 2025 03:50:52 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/119416/nrf54l15-32-mhz-dual-qspi-spi-devices" /><item><title>RE: nRF54L15: 32 MHz dual QSPI/SPI devices</title><link>https://devzone.nordicsemi.com/thread/525387?ContentTypeID=1</link><pubDate>Sun, 02 Mar 2025 03:50:52 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9e5b2127-00a4-4174-922f-64c714fb7fa5</guid><dc:creator>JordanYates</dc:creator><description>&lt;p&gt;Thanks Simon, I didn&amp;#39;t read closely enough to see SPIM00/21 existed.&lt;/p&gt;
&lt;p&gt;I take your note regarding timelines for the emulated peripherals, is there any documentation on the consequences of using them, or how they work in general?&lt;/p&gt;
&lt;p&gt;My assumption is that the FLPR core will be quite heavily loaded if trying to emulate 32 MHz QSPI from software, and so it would probably be unavailable for other purposes while running that.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15: 32 MHz dual QSPI/SPI devices</title><link>https://devzone.nordicsemi.com/thread/525326?ContentTypeID=1</link><pubDate>Fri, 28 Feb 2025 15:11:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c2dd49ec-b33f-4390-ba49-3b6cb855d68c</guid><dc:creator>Simonr</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;There are enough pins on P2 for both the FLPR to run QSPI, and SPIM00 to run a 32MHz SPI instance. If we go through the dedicated pins for QSPI, that will take up the following pins: P2.00, P2.01, P2.02, P2.03, P2.04 and P2.05. SPIM00 can still use P2.06 (clock pin) and pins P2.07-P2.10 for data, so it should be possible to run both an nRF7002 with QSPI for example and an external flash on the high-speed SPIM00. This would be the best approach to maximize throughput I think.&lt;/p&gt;
&lt;p&gt;Please note that the software emulated peripherals (such as QSPI) is still under development in terms of software, but this is something we&amp;#39;re working on. Please contact the Nordic sales representative of your area for details on roadmaps/timelines.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>