nRF5340 ADC resolution vs conversion time

RE: nRF5340 ADC resolution vs conversion time

Priyanka — Tue, 08 Jul 2025 08:44:59 GMT

Happy to hear. Thank you for the update. 🙂

RE: nRF5340 ADC resolution vs conversion time

Wolfgang R — Mon, 07 Jul 2025 14:43:27 GMT

No more answer needed:
We have just tested it on actual HW and the ADC is indead running at exactly 200 kHz with 14 bit resolution and 8 times oversampling, delivering the expected results.

RE: nRF5340 ADC resolution vs conversion time

Wolfgang R — Thu, 03 Jul 2025 15:44:18 GMT

Ok, thanks.

So IIUC the ADC runs on PCLK32M which is synchronous to the rest of the system.

However: the original question remains:
How long in terms of PCLK32M periods is tCONV? Is it EXACTLY 2 µs = 64 periods, or does this vary with SAADC RESOLUTION?

RE: nRF5340 ADC resolution vs conversion time

Priyanka — Mon, 16 Jun 2025 13:23:16 GMT

[quote user="Wolfgang R"]

Q2: Is the ADC clock stable relative to PCLK16M, or does it vary, e.g. over temperature?

[/quote]

Clock stability shouldn’t be a big concern here if HFXO is present. Then the accuracy of ADC clock is mostly dependent on HFXO accuracy, which is roughly +/-60 ppm over ETC.HFXO is present. Then the accuracy of ADC clock is mostly dependent on HFXO accuracy, which is roughly +/-60 ppm over ETC.
To achieve better ADC performance, TIMER module should be used. The internal TIMER runs on clock source PCLK16M and PCLK1M.

[quote user="Wolfgang R"]Under which conditions do regulators and references start or shut down and restart so that their startup times come to effect?[/quote]

To start an ADC, first ENABLE = 1, ADC gives access to the analog input pins. Then the ADC resources are started by triggering the START task. To start sampling, if you picked internal TIMER, it is sufficient to trigger SAMPLE task only once in order to start the SAADC and triggering the STOP task will stop sampling. ENABLE = 0 if one wants to disable ADC.

Also please note the following:

Mentioned jitter is from the clock source (PCLK32M), clock path through digital domain etc. It is hard to give a specific number. Please note that the startup only happens once before the ADC sampling is triggered. It is purely digital controlled. Jitter should not be an issue for the startup time of SAADC, but jitter can affect the accuracy when doing continuous mode sampling and a time series analysis of the results. So again, please use the TIMER module, HFXO clock source, and Constant Latency mode to achieve the best performance.

-Priyanka

RE: nRF5340 ADC resolution vs conversion time

Priyanka — Wed, 04 Jun 2025 09:03:10 GMT

[quote user="Wolfgang R"]

Q1: What clock source does the ADC run on? It seems to be a 16 MHz clock (assumption based on SAADC.SAMPLERATE.CC) - is it PCLK16M?

Out plan is to let the ADC run in continuous mode triggered by internal timer with SAMPLERATE.CC=80 (5 µs), CH[n].CONFIG.TACQ=0 (3µs) plus 2µs tCONV resulting in 200 kHz sample rate, then Oversample 8x to get averaged results at 25 kHz rate. Not using Scan Mode.

[/quote]

ADC itself runs on PCLK32M. Sampling freq source clock can be from 32.768 kHz RTC or more accurate internal 16MHz TIMER.
Yes, SAMPLERATE.CC=80 sets sample rate at 200 kHz. With oversampling 8x, the signal freq can be up to 25 kHz.

[quote user="Wolfgang R"]Q3: Under which conditions do regulators and references start or shut down and restart so that their startup times come to effect?[/quote]

After configuring RESULT.PTR and RESULT.MAXCNT, the ADC resources are started by triggering the START task. To start sampling, if you picked internal TIMER, it is sufficient to trigger SAMPLE task only once in order to start the SAADC and triggering the STOP task will stop sampling.

[quote user="Wolfgang R"]Q4: How long are these times?[/quote]

As soon as the START task is triggered, startup times of regulators and references timings should come into effect.

I will get back to you regarding the temperature effect.

-Priyanka

RE: nRF5340 ADC resolution vs conversion time

Wolfgang R — Tue, 27 May 2025 11:56:57 GMT

Thanks

RE: nRF5340 ADC resolution vs conversion time

Priyanka — Tue, 27 May 2025 11:17:44 GMT

Hi,

Apologies for the delay. I am checking for further data internally form the team and will keep you updated.

-Priyanka

RE: nRF5340 ADC resolution vs conversion time

Wolfgang R — Mon, 12 May 2025 14:38:56 GMT

Ok, sounds like we could get 200kHz even at 14 bit.

However, we're still a bit concerned about terms like "not much effect" or "typically around 2 µs". This sounds a little vague.
Is there any documentation about EXACT ADC timing?
Q1: What clock source does the ADC run on? It seems to be a 16 MHz clock (assumption based on SAADC.SAMPLERATE.CC) - is it PCLK16M?

The actual rate need not be 25 kHz, but it must be stable (for signal processing).
Q2: Is the ADC clock stable relative to PCLK16M, or does it vary, e.g. over temperature?

Product spec S v1.6 says in 7.29.13 Performance factors:
"... startup times of regulators and references will contribute to variability."
There doesn't seem to be any option to enable ADC hardware other than START, so it seems the ADC manages startup and shutdown of regulators and references automatically.
Q3: Under which conditions do regulators and references start or shut down and restart so that their startup times come to effect?
Q4: How long are these times?

RE: nRF5340 ADC resolution vs conversion time

Priyanka — Mon, 12 May 2025 07:42:43 GMT

Hi,

No, for the 52/53 series, the settings of SAADC RESOLUTION register does not have much affect on the conversion time tCONV ( typically it's around 2us). So your benefit would be the reduced data size and processing requirements, not increased sampling rate or lower latency.

Though for the 54 series, this is different and the tCONV is lesser.

Priyanka