MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Mon, 07 Jul 2025 11:41:53 GMT

Thank you for your expert opinions hmolesworth . I have resolved the SPI communication issue between ADS1299 and nRF52. Now, I can establish communication between the two devices. The problem was caused by an incorrect power supply to ADS1299. Additionally, the issue with the DK board was due to the incorrect connection you mentioned for JP21. I realised that it prevented connection with the device because it couldn't activate the CS pin. It really bothered me to deal with such simple issues for so long, but I appreciate everything.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Wed, 02 Jul 2025 03:05:57 GMT

A schematic would help. To get going in unipolar supply mode all these pins must be connected:

AVDD = AVDD1 = VREFP = +5V so Pins 19,21,22,24,54,56,59 all connected together

AVSS = AVSS1 = DGND = RESV1 = AGND = VREFN = nRF52 GND so Pins 20,23,25,32,33,49,51,53,57,58 all connected together

DVDD = nRF52 3.3V or 3.0V so Pins 48,50 connected together

VCAP1, VCAP2, VCAP3, VCAP4 all require appropriate capacitors to AVSS

By default, the device wakes up in external reference mode which is why VREFP can be connected to AVDD.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Mon, 30 Jun 2025 07:14:37 GMT

Hello hmolesworth . Did you have a chance to check the outputs I specified? As I mentioned, when I set the START pin to high voltage, the DRDY pin begins toggling, but I don't observe such a toggle after the power-up sequence. Additionally, this site states that VCAP2 should be (AVDD + AVSS)/2, but it displays 0V. Thank you for your response.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Sat, 28 Jun 2025 07:45:59 GMT

I modified the code based on your suggestion. According to the datasheet of the ADS1299, after the power-up sequence, ADS1299 enters RDATAC mode. I checked the DRDY pin, but there are no DRDY pulses after the power-up sequence. I am confident the power-up sequence works correctly because during this process, VCAP1 rises above 1.1v. Additionally, on the TI website, it states that after the power-up sequence, VCAP2 should be (AVDD-AVSS)/2, but it shows 0v. Could this be the issue?

Edit:
When I give the START pin a high voltage, the DRDY pin starts to toggle.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Sat, 28 Jun 2025 00:20:01 GMT

"To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral as described in Table 69: GPIO configuration on page 288 prior to enabling the SPI."

CS, SCLK, MOSI and MISO pins must all be configured before the SPI is enabled; your code has these commented out. Additionally to start testing don't use SPIM_FREQUENCY_FREQUENCY_M4 but instead start with 500KHZ and only try to use a faster clock speed once you have basic functionality.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Thu, 26 Jun 2025 16:00:02 GMT

Sorry to bother you again hmolesworth . I have a new board. I am feeding the AVDD with 5V and the DVDD with 3V from the nRF52840DK. I know the picture doesn't help, but I put the ADS1299 chip on the board and brought all the pins out. So, I am getting this result: MISO line returns 0x00 all the time, but it shows like toggling. I am supplying voltages from the nRF52840DK. I am using 5V to 0 as an AVDD-AVSS. I cannot get any response. I controlled VCAP1, and I measured it as 1.2V. Really, I do not understand where the problem is. I did not change anything in my code.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Thu, 26 Jun 2025 14:25:34 GMT

Yes. Also note JP2 pins 1 and 3 rely on an external 5V supply which is required. Good luck ..

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Thu, 26 Jun 2025 14:18:57 GMT

Thanks for your reply hmolesworth . I am taking up too much of your time. So basically, I want to discuss the general following path of the configuration. Using the same configuration architecture, I created a simple SPI test with nRF52840DK as the master and Arduino Uno as the slave. As a result, I achieved successful communication between them. I can now read and write values to the Arduino Uno via nRF52840. On the other hand, ADS1299 configuration fails every time. According to our discussion, we end up with a power management problem.

The point I want to make is that, if I follow the path I have outlined below, can I also establish communication between the ADS1299 and the nRF52840? If the problem I am experiencing is not a configuration problem, can I get a system ready for communication once I solve the power problem?

Thanks for your reply.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Thu, 26 Jun 2025 14:10:37 GMT

Edit: Photo shows J2 but I misread your last post - I see you now have JP2 not J2

J2 is only present for physically attaching to MMB0 board; there are no electrical connections to J2 on the ADS board according to the ADS schematic. The MMBO 20-pin connectors are connected in parallel, but ADS J2 goes nowhere. For reference this is the MMBO schematic:

devzone.nordicsemi.com/.../1121.MMB0_5F00_Sch_5F00_RevD.PDF

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Thu, 26 Jun 2025 07:39:10 GMT

Based on the traces, J2 is not connected because I am not using the MMB0 board. Therefore, I am connecting 5V to the third pin of JP2. I believed that when I connect 5V this way, it would supply power to the board. Thank you for clarifying the SPI_CS. Following that, I moved the SPI_CS pin to the third pin of JP21. Thanks for your reply hmolesworth .

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Thu, 26 Jun 2025 07:33:32 GMT

Thanks for your reply Turbo J . Thanks for your help.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Wed, 25 Jun 2025 15:23:19 GMT

Look at the trace diagram in the user manual, the square pin on 3-pin JP21 and 3-pin JP22 headers indicate which end is pin 1. JP21 and JP22 both have pin 1 connected together and both connect to J3 pin 1. Therefore assuming the schematic is correct you are using the wrong jumper position if you want SPI_CS on P0.31 and J3 pin 7: therefore change jumper on JP21 to the 2-3 position.

J2 is shown as a dummy connector; where is the 5V going?

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

Turbo J — Wed, 25 Jun 2025 15:15:07 GMT

In my ADS1299_EK_MAN schematic (SLAU443 dated May 2012, YMMV), J2 is a dummy connector without any pins connected.

No further discussion from me on this platform about this issue. You clearly have not a problem on the nordic side, and they can't really help you here further either.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Wed, 25 Jun 2025 14:39:25 GMT

Now, I go back to the ADS board, I am not using the MMB0 board. I supplied DVDD with the nRF VDD, and for the AVDD, I am giving 5V externally.

These are the pin connections that I did in my configuration. I have mentioned the code I tried above. What am I doing wrong? Thanks for your replies hmolesworth and Turbo J .

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Wed, 25 Jun 2025 10:08:46 GMT

Thanks for your reply. I did not pay attention to that part. I can add a voltage regulator to that part. With this problem, I go back to the starting point. Is there any misconfiguration present in my code? Any misleading operation? Thanks again Turbo J .

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

Turbo J — Wed, 25 Jun 2025 09:52:25 GMT

Re-read the ADS1299 datasheet. It clearly stated in chapter 7.3 that you need at least 4.75V between AVDD and AVSS.

Unsurprisingly the chip won't work when your supply is significantly below that.

Sounds like you need to redesign your board...

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Wed, 25 Jun 2025 08:05:40 GMT

Thank you for your help hmolesworth and Turbo J . I haven't made any progress in this section so far. I think this is because I have problems feeding the ADS1299, and therefore, I can't communicate. While working on the coding, I also designed a PCB with the ADS1299 chip and the nRF52840 module as suggested by TI, and it arrived.

I made the connections on the ADS1299 chip as follows:

ADS1299 ------------------------- nRF52
AVDD VDD
DVDD VDD
AVSS GND
CLKSEL VDD
DAISYIN GND
DRDY P0.12
SCK P0.13
MISO P0.14
MOSI P0.15
CS P0.16
START P0.17
RESET P0.19
PWDN P0.20

I measured the VCAP1 voltage, and it is above 1.1V, but I still cannot establish communication. ADS1299 returns 0x00 as a result. This is the latest library code that I created.

#include "ADS1299_nRF.h"
#include <nrf.h>
#include <nrf_log.h>
#include <nrf_log_ctrl.h>
#include <nrf_log_default_backends.h>
#include <nrf_gpio.h>
#include <nrf_delay.h>
#include "ads1299_delay.h"
#include "nrfx_spim.h"

// Enable polling mode for DRDY
#define POLL_DREADY

#define SPIM2 NRF_SPIM2
#define ADS_POWER_RAMP_TIME_MSECS 30 // Delay for regulator to stabilize

bool new_data_available = false;
uint8_t rx_buffer[27], tx_buffer[8];
uint8_t sample_number = 0;
static uint8_t regData[24]; // Mirror of ADS1299 registers

/** @brief SPI interface initialization. Accurate timing use HFCLK clock */
void spi_init(void) {
    // Start HFCLK source for accurate timing
    NRF_CLOCK->TASKS_HFCLKSTART = 1;
    while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0);
    NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
    
    // Disable SPIM to configure it
    SPIM2->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
    
    // Configure SPIM2 pins
    SPIM2->PSEL.SCK = ((PIN_SCK << SPIM_PSEL_SCK_PIN_Pos) |
                        (0 << SPIM_PSEL_SCK_PORT_Pos) |
                        (SPIM_PSEL_SCK_CONNECT_Connected << SPIM_PSEL_SCK_CONNECT_Pos));

    SPIM2->PSEL.MOSI = ((PIN_MOSI << SPIM_PSEL_MOSI_PIN_Pos) |
                        (0 << SPIM_PSEL_MOSI_PORT_Pos) |
                        (SPIM_PSEL_MOSI_CONNECT_Connected << SPIM_PSEL_MOSI_CONNECT_Pos));

    SPIM2->PSEL.MISO = ((PIN_MISO << SPIM_PSEL_MISO_PIN_Pos) |
                        (0 << SPIM_PSEL_MISO_PORT_Pos) |
                        (SPIM_PSEL_MISO_CONNECT_Connected << SPIM_PSEL_MISO_CONNECT_Pos));
    
    SPIM2->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M4; // 2 MHz (t_CLK = 500 ns)
    
    SPIM2->ORC = 0xFF;

    // ADS1299 set Data mode: clock polarity = 0, clock phase = 1
    SPIM2->CONFIG = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |  // CPOL = 0
                    (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) |     // CPHA = 1
                    (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos);
    
    SPIM2->EVENTS_END = 0;
    SPIM2->EVENTS_ENDTX = 0;
    SPIM2->EVENTS_ENDRX = 0;
    
    SPIM2->INTENCLR = 0xFFFFFFFFUL;
    SPIM2->INTENSET = 0x040;
    
    SPIM2->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
}

void gpio_init(void)
{
    
    //NRF_P0->PIN_CNF[CS_PIN]   = 0x301;  // output, high drive high and low H0H1
    //NRF_P0->PIN_CNF[PIN_SCK]  = 0x301;  // output, high drive high and low H0H1
    //NRF_P0->PIN_CNF[PIN_MOSI] = 0x301;      // output, standard drive S0S1
    //nrf_gpio_cfg(PIN_MISO, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
    nrf_gpio_cfg(PWDN_PIN, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
    nrf_gpio_cfg(RESET_PIN, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
    nrf_gpio_cfg_input(PIN_DRDY, GPIO_PIN_CNF_PULL_Pullup);	
    nrf_gpio_pin_clear(CS_PIN);
    nrf_delay_ms(50);
    nrf_gpio_pin_set(CS_PIN);
    nrf_delay_ms(10);


}

static void spi_uninit(void) {
    SPIM2->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
    nrf_gpio_cfg_input(PIN_SCK, NRF_GPIO_PIN_NOPULL);
    nrf_gpio_cfg_input(PIN_MOSI, NRF_GPIO_PIN_NOPULL);
    nrf_gpio_cfg_input(PIN_MISO, NRF_GPIO_PIN_NOPULL);
}

bool spi_transfer_byte(uint8_t *tx, uint8_t *rx, size_t len) {
    if (!(SPIM2->ENABLE & SPIM_ENABLE_ENABLE_Msk)) {
        SPIM2->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    }

    SPIM2->EVENTS_END = 0;
    SPIM2->TXD.PTR = (uint32_t)tx;
    SPIM2->TXD.MAXCNT = len;
    SPIM2->RXD.PTR = (uint32_t)rx;
    SPIM2->RXD.MAXCNT = len;

    SPIM2->TASKS_START = 1;
    while (!SPIM2->EVENTS_END);

    SPIM2->TASKS_STOP = 1;
    while (!SPIM2->EVENTS_STOPPED);

    NRF_LOG_INFO("SPI TX: 0x%02x, RX: 0x%02x", tx[0], rx ? rx[0] : 0);
    return true;
}

bool spi_transfer_bytes(const uint8_t *tx, uint8_t *rx, size_t len) {
    if (!(SPIM2->ENABLE & SPIM_ENABLE_ENABLE_Msk)) {
        SPIM2->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    }
    
    static uint8_t dummy_tx = 0xFF;
    static uint8_t dummy_rx;

    SPIM2->EVENTS_END = 0;
    SPIM2->TXD.PTR = (uint32_t)(tx ? tx : &dummy_tx);
    SPIM2->TXD.MAXCNT = len;
    SPIM2->RXD.PTR = (uint32_t)(rx ? rx : &dummy_rx);
    SPIM2->RXD.MAXCNT = len;

    SPIM2->TASKS_START = 1;
    while (!SPIM2->EVENTS_END);
    SPIM2->ENABLE = SPIM_ENABLE_ENABLE_Disabled; // Disable SPIM to allow pull-up to take effect
    return true;
}

void ADS1299_pwr_up_seq(void) {

    nrf_gpio_pin_set(PWDN_PIN); // Power on
    nrf_gpio_pin_set(RESET_PIN); // Reset low
    nrf_delay_ms(150);          // Wait for tPOR

    nrf_gpio_pin_clear(RESET_PIN); // Reset low
    nrf_delay_us(2);             // ≥2 clock cycles
    nrf_gpio_pin_set(RESET_PIN);  // Reset high
    nrf_delay_ms(10);              // Stabilization
}

void Reset_ADS(void)
{
	nrf_gpio_pin_set(PWDN_PIN);
	nrf_delay_us(100000);
	nrf_gpio_pin_clear(PWDN_PIN);
	nrf_delay_us(100000);
	nrf_gpio_pin_set(PWDN_PIN);
	nrf_delay_us(100000);
}

bool ADS1299_init(void) {
    // Recommended power-up sequence for ADS1299
    
    NRF_LOG_INFO("Initializing ADS1299");
    //Reset_ADS();
    ADS1299_pwr_up_seq();
        
    NRF_LOG_INFO("SPI init success");
#ifdef POLL_DREADY
    NRF_LOG_INFO("DRDY polling enabled");
#else
    NRF_LOG_INFO("DRDY interrupt not implemented");
#endif
    return true;
}

void poll_dready(void) {
#ifdef POLL_DREADY
    NRF_LOG_INFO("Polling DRDY, state: %d", nrf_gpio_pin_read(PIN_DRDY));
    if (nrf_gpio_pin_read(PIN_DRDY) == 0) {
        NRF_LOG_INFO("DRDY low, receiving data");
        ADS1299_receive_data();
        send_new_available_data();
    }
#endif
}

bool ADS1299_write_register(uint8_t address, uint8_t value) {

    uint8_t cmd[] = {
        (uint8_t)(address | COMMAND_WREG),
        0x00, // Write 1 register
        value
    };

    nrf_gpio_pin_clear(CS_PIN);
    nrf_delay_us(2); // t_CSSC: Delay from CS low to first SCLK (min 6 ns, use 50 ns for safety)
    spi_transfer_byte(cmd, NULL, 3);
    nrf_delay_us(2); // t_CSH: Delay from last SCLK to CS high (min 1 µs)
    nrf_gpio_pin_set(CS_PIN);
    nrf_delay_us(1); // t_CSH hold time after CS high

    regData[address] = value;
    return true;
}

uint8_t ADS1299_read_reg(uint8_t address) {
    uint8_t tx_data = 0x20 | address;  // RREG command (0x20) + address
    uint8_t dummy = 0x00;
    uint8_t rx_data = 0;
    
    // Pull CS low to start transaction
    nrf_gpio_pin_clear(CS_PIN);
    
    // Send RREG command + address (transmit only)
    spi_transfer_byte(&tx_data, NULL, 1);
    nrf_delay_us(2);
    
    // Send dummy byte and receive register data
    spi_transfer_byte(&dummy, &rx_data, 1);
    nrf_delay_us(2);
    
    // Pull CS high to end transaction
    nrf_gpio_pin_set(CS_PIN);
    
    // Store in global array if you're using it
    regData[address] = rx_data;
    
    return rx_data;  // Return the register value directly
}

bool ADS1299_send_command(uint8_t command) {
    uint8_t dummy;
    nrf_gpio_pin_clear(CS_PIN);
    spi_transfer_byte(&command, NULL, 1);
    nrf_delay_us(2);
    nrf_gpio_pin_set(CS_PIN);
    nrf_delay_us(2); // t_CSH hold time after CS high
    return true;
}

bool ADS1299_send_start(void) {
    bool result = ADS1299_send_command(COMMAND_START);    
    return result;
}

bool ADS1299_send_read_continuous(void) {
    bool result = ADS1299_send_command(COMMAND_RDATAC);
    nrf_delay_us(3); // Allow RDATAC to settle
    return result;
}

bool ADS1299_send_reset(void) {
    bool result = ADS1299_send_command(COMMAND_RESET);
    NRF_LOG_INFO("Reset command sent, result: %d", result);
    return result;
}

bool ADS1299_send_sdatac(void) {
    bool result = ADS1299_send_command(COMMAND_SDATAC);
    NRF_LOG_INFO("Stop read continuously command sent, result: %d", result);
    return result;
}

bool ADS1299_receive_data(void) {
    new_data_available = false;
    if (!spi_transfer_bytes(NULL, rx_buffer, 27)) {
        NRF_LOG_ERROR("Failed to receive data");
        return false;
    }
    new_data_available = true;
    NRF_LOG_INFO("Data received, triggering send_new_available_data");
    return true;
}

bool ADS1299_poll_new_data(ADS1299_data_t *data) {
    if (new_data_available) {
        new_data_available = false;
        *data = ADS1299_convert_data();
        return true;
    }
    return false;
}

static inline int32_t buffer_to_channel(uint8_t id) {
    int32_t value = (rx_buffer[3 + id * 3] << 16) | (rx_buffer[4 + id * 3] << 8) | rx_buffer[5 + id * 3];
    if (value & 0x00800000) {
        value |= 0xFF000000;
    } else {
        value &= 0x00FFFFFF;
    }
    return value;
}

ADS1299_data_t ADS1299_convert_data(void) {
    ADS1299_data_t data;
    data.lead_off_positive = rx_buffer[0] << 4;
    data.lead_off_positive |= (rx_buffer[1] & 0b11110000) >> 4;
    data.lead_off_negative = rx_buffer[1] << 4;
    data.lead_off_negative |= (rx_buffer[2] & 0b11110000) >> 4;
    data.gpio_0 = rx_buffer[2] & 0b00001000;
    data.gpio_1 = rx_buffer[2] & 0b00000100;
    data.gpio_2 = rx_buffer[2] & 0b00000010;
    data.gpio_3 = rx_buffer[2] & 0b00000001;
    data.channel_0 = buffer_to_channel(0);
    data.channel_1 = buffer_to_channel(1);
    data.channel_2 = buffer_to_channel(2);
    data.channel_3 = buffer_to_channel(3);
    data.channel_4 = buffer_to_channel(4);
    data.channel_5 = buffer_to_channel(5);
    data.channel_6 = buffer_to_channel(6);
    data.channel_7 = buffer_to_channel(7);
    return data;
}

void send_new_available_data(void) {
    if (new_data_available) {
        new_data_available = false;
        NRF_LOG_INFO("Sample: %d", sample_number++);
        for (uint8_t i = 0; i < 27; i++) {
            NRF_LOG_INFO("Byte %d: 0x%02x", i, rx_buffer[i]);
        }
    }
}

This is the main part.

#include <nrf.h>
#include <nrf_log.h>
#include <nrf_log_ctrl.h>
#include <nrf_log_default_backends.h>
#include "ADS1299_nRF.h"
#include "nrf_delay.h"
#include "nrf_gpio.h"


extern bool new_data_available;

int main(void) {
    NRF_LOG_INIT(NULL);
    NRF_LOG_DEFAULT_BACKENDS_INIT();

    NRF_LOG_INFO("Starting ADS1299 initialization");
    
    gpio_init();
    spi_init();
    if (!ADS1299_init()) 
    {
        NRF_LOG_ERROR("ADS1299 init failed");
        while (1) {
            //nrf_gpio_pin_toggle(LED_PIN);
            NRF_LOG_FLUSH();
            nrf_delay_ms(200);
        }
    }
    
    ADS1299_send_reset();
    nrf_delay_ms(1);
    ADS1299_send_sdatac();
    uint8_t id = 0x00;

    id = ADS1299_read_reg(ID);

    if (id == 0x3E) 
    {
        NRF_LOG_INFO("ADS1299 communication success, ID: 0x%02x", id);
    }
    else 
    {
        NRF_LOG_INFO("ADS1299 communication fail, ID: 0x%02x", id);
    }
}

Thank you for your suggestions and help so far. It would be easier to reach the problem through a card that has been put together rather than trying to debug the problem through DK.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

Turbo J — Wed, 25 Jun 2025 06:47:15 GMT

The symmetric voltage supply on the EK board can accept anything from ~3V to 5V DC and provide stable symmetric 2.5V to the chip (as long as the source can supply roughly 50mA). Adjust your jumpers to use the outputs from the LDOs, your description does not sound correct to me.

It may be a good idea to draw your own schematic that includes the connections to the STM/NRF board(s).

The ADS1299 absolutely refuses to work when the analog voltages or the pin config is not 100% correct.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Wed, 25 Jun 2025 06:11:55 GMT

Hi hmolesworth thanks for your answer. Yes, when I measure the voltage between AVSS, AVDD I see 3V.

I didn't have a 5V external power supply and yes, I connect my 3V power supply to the VCC_5V side, not to the 2nd leg.

JP20 1-2 means they are shorted. In the image I shared before, when I connected pins 1-2 together, AVSS was connected to GND. I did not share J3 part because there is no challenging part in there, I connected them directly to the microcontroller side defined pins.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Wed, 25 Jun 2025 05:33:19 GMT

Well, .. it is not very clear how you are powering the board. Maybe you could measure AVDD and AVSS & AGND which I think you are assuming are 3V and 0V.

JP2 VDD supplied from the 3rd pin That is 2.5V (or 5V) which requires an external 5V (Vcc_5V). Did you mean to supply 3V to JP2 middle (2nd) pin to provide 3V on AVDD?

JP20 1-2 (GND) Does that mean an external wire to pin 2? AVSS must also be connected to AGND (or 2.5V which doesn't exist if there is no 5V) which looks like pin 2 to pin 3 not 1-2 (the schematic doesn't exactly make pin numbers clear)

supply 3V to JP2 middle (2nd) pin to provide 3V on AVDD

J3 connections? Why are these not all detailed

JP21 1-2 means SPI_CS is on J3 pin 1
JP22 2-3 means SPI_START is on J3 pin 14

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Tue, 24 Jun 2025 16:44:31 GMT

Jumper Name	Settings
JP2	VDD supplied from the 3rd pin
JP4	Not installed
JP5	1st pin used as PWDN
JP18	2-3
JP19	1-2
JP20	1-2 (GND)
JP21	1-2
JP22	2-3
JP23	1-2
JP24	VDD supplied from the 2nd pin

This is the pin configuration that I use.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Tue, 24 Jun 2025 16:18:39 GMT

Ok, so is JP2 in position 2, JP20 in position 2, JP4 disconnected, JP24 where, JP21, JP22 & JP23 where? A table would save time ..

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Tue, 24 Jun 2025 16:04:16 GMT

There is no MMB0 board in this setup. I am simply using the ADS1299 part (the upper part of the DK). That's why I am not using any 5V supply. Instead, I am supplying 3V to the AVDD and DVDD parts of the ADS1299, as I mentioned in the previous message.

In here I am using CLKSEL pin => directly connected high

ADS1299 ----- nRF52 or STM32

GND pin -> GND of the STM32 or nRF52
RESET pin -> defined pins in the STM32 or nRF52
CS pin -> CS pin
DIN pin -> MOSI pin
DOUT pin -> MISO pin
DRDYB pin -> defined pins in the STM32 or nRF52

Thanks for your reply hmolesworth . Sorry for the misunderstanding.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

hmolesworth — Tue, 24 Jun 2025 15:46:22 GMT

Not so helpful and not what I asked; what is on each pin? As an example I don't see a 5V supply provided anywhere: "The main power supplies (+5V, +3V and +1.8V) for the front-end board are supplied by the host board (MMB0) through connector J4." Am I missing something?

Digital lines are connected - to which pins? Which pins have no connection? The photo is not easy to see.

RE: MISO line mimics the MOSI line in SPIM configuration sdk 17.1.0

omerBzkrt — Tue, 24 Jun 2025 14:54:42 GMT

Thanks for your reply hmolesworth .

I connect the VDD of the STM32 and nRF52 to the JP2 3rd leg. I connect JP20 1-2 to the GND.

For the DVDD part, I connect the 2nd leg of the JP24 to the VDD of the STM32 and nRF52.

* Digital lines are connected.
* CLKSEL pin is connected to the VDD.

* I used JP5 1st leg for the PWDN pin.

I said STM32 and nRF52 because I tried this configuration separately for both devices. This is my latest configuration for the read ADS1299.