nrf54L15 LFRC 32KHz clock configuration issue

RE: nrf54L15 LFRC 32KHz clock configuration issue

Yongwoo Kim — Wed, 02 Jul 2025 06:32:49 GMT

The merged.hex file didn't work either:

The Holyiot module is also ENGA. As ppatel mentioned last time, there seems to be a problem with the NRF54L15, which is an ENGA.

RE: nrf54L15 LFRC 32KHz clock configuration issue

ppatel — Thu, 26 Jun 2025 17:57:47 GMT

Hi Hung Bui ,

Up until we had REVA/ENGA of nRF54L15. We just replaced FANSTEL package to have REVB/ENGB of nRF54L15 and it is working now.

So all along REVA/ENGA of nRF54L15 had some issue which is now fixed in REVB/ENGB of nRF54L15.

Thanks for all the support!

RE: nrf54L15 LFRC 32KHz clock configuration issue

Hung Bui — Thu, 26 Jun 2025 11:06:29 GMT

Hi Yongwoo,

Could you try to flash with the merged.hex file I provided ?
If you have the 32kHz xtal, have you tried to flash a simple blinky sample without any modification (build for the DK) ?

RE: nrf54L15 LFRC 32KHz clock configuration issue

Yongwoo Kim — Thu, 26 Jun 2025 10:34:32 GMT

Hello, Hung.

I'm trying to start development with Holyiot's nRF54L15 module:

but like ppatel, it gets stuck at nrfy_grtc_sys_counter_start.

Something's not right. The Holyiot nRF54L15 module already has 32k Xtal and 32M xtal.

And I followed this post, the kconfig, DT overlay, and blinky_RC_2 in this post all fail to initialize GRTC.

RE: nrf54L15 LFRC 32KHz clock configuration issue

Hung Bui — Tue, 24 Jun 2025 11:53:01 GMT

Hi PPatel,

I did a quick test here and it seems to work in my case. I cut SB4 and SB3 on the DK so that the crystal was not connected. When I flashed the default Blinky it doesn't run (meaning the XTAL has been disconnected) but when I modify the blinky to use RC it start to blink.

Could you try to flash the following hex file to see if it run on the FANSTEL ?

I assume you don't have anything special on FANSTEL that may block the run of the blink example ? For example if P2.09 (LED0) is used for something else ?

Have you pulled this https://github.com/zephyrproject-rtos/zephyr/pull/89670 There are 2 commits needed.

devzone.nordicsemi.com/.../6428.merged.hex

devzone.nordicsemi.com/.../blinky_5F00_RC_5F00_2.zip

RE: nrf54L15 LFRC 32KHz clock configuration issue

ppatel — Tue, 24 Jun 2025 00:01:52 GMT

Hi Hung,

Yes, I have 2 different board files for the DK and the FANSTEL board.

Yes, I added overlay but it still doesn't work.

Flashing HEX built for the DK on the FANSTEL doesn't work.

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y and all the other CONFIGs which worked on the DK, I copied those directly for the FANSTEL. But it still doesn't work.

RE: nrf54L15 LFRC 32KHz clock configuration issue

Hung Bui — Mon, 23 Jun 2025 12:03:09 GMT

Hi PPatel,

Could you tell how you built for the DK and how you built for the FANSTEL board ?
I assume you have different board files ?
Have you added the overlay I mentioned in the last reply ?

If you simply flash the hex file built for the DK on the FANSTEL, would it work ?

I would guess there could be an issue with the board file made for the FANSTEL.

Please also check the .config file in \build\blinky\zephyr\ when you build for FANSTEL and check if you have CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y there. Please try to compile to the same .config file when you build for the DK.

RE: nrf54L15 LFRC 32KHz clock configuration issue

ppatel — Fri, 20 Jun 2025 18:13:34 GMT

Hi Hung,

I added the changes you suggested.

I modified our prj.conf / XXX_defconfig to the following:

# Enable UART driver
CONFIG_SERIAL=y

# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

# Enable GPIO
CONFIG_GPIO=y

# Enable MPU
CONFIG_ARM_MPU=y

# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y

CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_NRF=y

# use grtc as system timer
CONFIG_NRF_GRTC_TIMER=y
CONFIG_NRF_GRTC_START_SYSCOUNTER=y

# Enable LFRC (internal RC oscillator)
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_FREQUENCY=32768

# Disable LFXO (external 32kHz crystal)
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n

# Disable synthesized LFCLK from HFCLK
CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=y
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON=y

Also modified the Blinky sample to the minimal:

#include <stdio.h>
#include <zephyr/kernel.h>

#define SLEEP_TIME_MS   1000

int main(void)
{
    uint32_t counter = 0;
    while (1) {
        printf("Counter: %u\n", counter++);
        k_msleep(SLEEP_TIME_MS);
    }
    return 0;
}

With the above changes,
For NRF54L15 DevKit I see GRTC (GLOBAL_GRTC_NS)-->CLKCFG(0x00020001)-->CLKSEL-->LFLPRC and can confirm Counter value incrementing on UART.

With the same changes,
For FANSTEL BM15C (NRF54L15) module, I see GRTC (GLOBAL_GRTC_NS)-->CLKCFG(0x00000001)-->CLKSEL-->LFXO.
I get stuck with this call stack:

nrfy_grtc_sys_counter_start(NRF_GRTC_Type * p_reg, _Bool busy_wait) (PATH\modules\hal\nordic\nrfx\haly\nrfy_grtc.h:987)
nrfx_grtc_syscounter_start(_Bool busy_wait, uint8_t * p_main_cc_channel) (PATH\modules\hal\nordic\nrfx\drivers\src\nrfx_grtc.c:566)
sys_clock_driver_init() (PATH\zephyr\drivers\timer\nrf_grtc_timer.c:483)
z_sys_init_run_level(enum init_level level) (PATH\zephyr\kernel\init.c:377)
z_cstart() (PATH\zephyr\kernel\init.c:801)
z_prep_c() (PATH\zephyr\arch\arm\core\cortex_m\prep_c.c:220)
z_arm_reset() (PATH\zephyr\arch\arm\core\cortex_m\reset.S:207)

Can you please suggest if I need additional changes to make this work on FANSTEL BM15C module ?

Thanks!

RE: nrf54L15 LFRC 32KHz clock configuration issue

Hung Bui — Tue, 17 Jun 2025 12:42:55 GMT

Hi PPatel,

As far as I know you would need to remove the lfxo from the device tree. Please add this to an overlay file (app.overlay for example):

/delete-node/ &lfxo;

grtc {
      /delete-property/ clocks;
      /delete-property/ clock-names;
      clocks = <&pclk>;
      clock-names = "hfclock";
};

And this is also required: https://github.com/zephyrproject-rtos/zephyr/pull/89670

Please try to test with one of our sample in the SDK so we can align easier.