RE: MPSL Assert 107,291 and 107,301

Amanda Hsieh — Tue, 01 Jul 2025 13:15:16 GMT

Hi,

We tried to reproduce, but the uploaded files seem to be incomplete.

Could you please share the full project with the building commands to build the project? If it's sensitive, I can set this case private. Therefore, the project would only be shared with us.

In the meantime, we investigated a bit:

The reason for the

MPSL ASSERT: 107, 291

MPSL ASSERT: 107, 301

Assertion failures can be a delay in handling the RTC0 interrupt. It looks strange, because this interrupt should work without any delays on the highest priority (hardware prio 0).

You could check the following:

CONFIG_ZERO_LATENCY_IRQS is set to y

This can be checked in the build/<app_name>/zephyr/.config file.

If debugging, any breakpoint hit can cause a delay (CPU gets halted, but RTC is still running), so stepping through the code can also result in such behavior.

Could you also share the entire .config as well as zephyr.dts file under the build/<app_name>/zephyr/? Maybe some peripherals have been configured to IRQ Prio = 0?

Regards,
Amanda H.

RE: MPSL Assert 107,291 and 107,301

Amanda Hsieh — Wed, 25 Jun 2025 13:05:09 GMT

Hi,

Thank you for notifying us. The team is trying to reproduce to figure out what might cause this assertion. I will update later when I collect enough information. Please give us more time. Thanks.

Regards,
Amanda H.