How to configure and confirm CPU frequency on nRF5340? (LVGL performance concern with ST7789)

RE: How to configure and confirm CPU frequency on nRF5340? (LVGL performance concern with ST7789)

Vidar Berg — Mon, 21 Jul 2025 11:37:50 GMT

Thanks for updating the ticket after you found the solution. Here's also code snippet copied from one of the Zephyr samples that reads back the current CPU frequency as well:

#include <nrfx_clock.h>

static int nrf53_cpu_boost(void)
{
	int err;

	/* For optimal performance, the CPU frequency should be set to 128 MHz */
	err = nrfx_clock_divider_set(NRF_CLOCK_DOMAIN_HFCLK, NRF_CLOCK_HFCLK_DIV_1);
	err -= NRFX_ERROR_BASE_NUM;
	if (err != 0) {
		printk("Failed to set 128 MHz: %d\n", err);
	}

	printk("Starting %s with CPU frequency: %d MHz\n", CONFIG_BOARD, SystemCoreClock/MHZ(1));

	return err;
}

RE: How to configure and confirm CPU frequency on nRF5340? (LVGL performance concern with ST7789)

Sab1e — Sun, 20 Jul 2025 16:00:25 GMT

You can also refer to this link: devzone.nordicsemi.com/.../nrf5340-128mhz-spi-32-mhz

RE: How to configure and confirm CPU frequency on nRF5340? (LVGL performance concern with ST7789)

Sab1e — Sun, 20 Jul 2025 15:37:38 GMT

Hi all,

I was trying to improve the performance of LVGL on the nRF5340 by increasing the application core clock speed. I’m using an ST7789 display with a resolution of 240×284, and I noticed rendering was slow, so I wanted to verify and potentially increase the running frequency.

After some investigation and DWT (Data Watchpoint and Trace) measurement, it appeared that my application core was running at 64 MHz rather than the expected 128 MHz.

Eventually, I found that the solution is to explicitly set the HFCLK divider to 1 using the nrfx_clock_divider_set API. This feature is available when CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT is defined.

Here is the working fix I applied:

#include <nrfx_clock.h>

int main(){
...
#if NRFX_CLOCK_ENABLED && (defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M)
    nrfx_clock_divider_set(NRF_CLOCK_DOMAIN_HFCLK, NRF_CLOCK_HFCLK_DIV_1);
#endif
...
    return 0;
}

This successfully configured the HFCLK to 1x divider, giving me 128 MHz, and my LVGL performance improved significantly.

The solution was originally provided in this thread.

Additionally, the standard SPIM modules only support speeds up to 16 Mbps, whereas SPIM4 can support up to 32 Mbps when the application core is running at 128 MHz.

Hope this helps others facing the same issue!

Best regards,

Sab1e