SAADC channel interference due to software bad configuration or hardware design?

RE: SAADC channel interference due to software bad configuration or hardware design?

DimitraN — Tue, 19 Aug 2025 09:09:21 GMT

[quote userid="128023" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/546009"]

hmolesworth said:
To simplify the equations the floating Vn drives could be driven high to parallel the measured resistor or driven low to parallel the 12k net pulldown resistance. For V1:A3 measuring S6 driving V2 and V3 high S6 would then be more simply seen as:

S6 || S7 || S8

V1, V2 and V3 outputs should be High-Drive H0H1 to reduce the output pin FET series resistance; Standard-Drive L0L1 is something like 160 Ohm and H0H1 is something like 35 Ohm.

I will try this and come back at you

[/quote]

I tried this but didnt get good results, except if I did something wrong.

To read S6 (V1 and A3) I configure the pins as follows:

nrf_gpio_cfg(V2, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
nrf_gpio_cfg(V3, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
nrf_gpio_cfg_output(V1);
nrf_gpio_pin_set(V1);

the same configuration is made for every S0-S8

but I get :

[S0, S3, S6]
[S1, S4, S7]
[S2, S5, S8]

RE: SAADC channel interference due to software bad configuration or hardware design?

DimitraN — Tue, 19 Aug 2025 08:35:47 GMT

Hello,

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/545711"]Edit all the functions like nrf_drv_saadc_channel_uninit() to also turn off the port pull-down[/quote]

Yes I tried this but didn't help.

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/545711"] S6 || (S7 + ((S4+S3) || (S1+S0))) || (S8 + ((S5+S3) || (S2+S0)))[/quote]

Could you please by the way explain to me how did you calculate this formula ? How/why the rest resistors affect the one that is about to be measured, even if we have "disconnected" the rest of the pins (Vx and saadc pins)?

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/545785"]

To simplify the equations the floating Vn drives could be driven high to parallel the measured resistor or driven low to parallel the 12k net pulldown resistance. For V1:A3 measuring S6 driving V2 and V3 high S6 would then be more simply seen as:

S6 || S7 || S8

V1, V2 and V3 outputs should be High-Drive H0H1 to reduce the output pin FET series resistance; Standard-Drive L0L1 is something like 160 Ohm and H0H1 is something like 35 Ohm.

[/quote]

I will try this and come back at you

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/545785"]I'm assuming adding series schottky diodes is not an option?[/quote]

It is an option, this is what I tried right now.. but I can do it with some constraints.

The grid is a ready-made sensor that I want to read, so the only points in the circuit where I can integrate something are at the black "X" below, which are the wires going to my electronics.

I connected 1N5817 diodes at the points but with no effect.
Maybe I should try with MOSFET too?

RE: SAADC channel interference due to software bad configuration or hardware design?

hmolesworth — Fri, 15 Aug 2025 12:36:51 GMT

S6 || S7 || S8

V1, V2 and V3 outputs should be High-Drive H0H1 to reduce the output pin FET series resistance; Standard-Drive L0L1 is something like 160 Ohm and H0H1 is something like 35 Ohm.

I'm assuming adding series schottky diodes is not an option?

RE: SAADC channel interference due to software bad configuration or hardware design?

hmolesworth — Thu, 14 Aug 2025 18:59:46 GMT

The pull-downs for both port io and SAADC must be turned off for the other two analogue channels when reading an analogue channel. For example for reading channel V2/A3 both V1 and V3 pins must be floated (inputs) and both A1 and A2 pins must have both port io and SAADC pull-downs turned off:

Uncomment all these
  //nrf_drv_saadc_channel_uninit(0);
  //nrf_drv_saadc_channel_uninit(2);

Edit all the functions like nrf_drv_saadc_channel_uninit() to also turn off the port pull-down

Edit: Ah this will not work easily I'm afraid. I just looked at your updated schematic and see that the effective resistor is still affected by the other resistors. Instead of (say) measuring S6 using V1/A3 the measured value would be approximately:

S6 || (S7 + ((S4+S3) || (S1+S0))) || (S8 + ((S5+S3) || (S2+S0)))

which explains why the measured value is higher than expected. S0 is less affected since it has the lowest resistance value.

Without knowing what the "resistors" (the analogue sensors) consist of, it is not clear whether this is simple to pre-calculate by applying the parallel resistor values in the formula; easier if only a single resistor changes value at a time.

RE: SAADC channel interference due to software bad configuration or hardware design?

DimitraN — Wed, 13 Aug 2025 08:01:47 GMT

The new circuit is

The code is the same as above, where I enable one SAADC channel at a time for each column of resistors, first channel 1 for A1 and I set V1 output pin and drive it high to read S0. Then I set V1, V3 input and no pull and disconnect them, set V2 output and high to read S1, etc. When I finish with one column, I uninitialize channels and enable only channel 2 for A2 pin, and set V pins accordingly for S3, S4,S5 etc.

I have put RP resistors in the drawing which are the equivalent of the two parallel pull down resistors (of SAADC and internal of GPIO as you mentioned).

As you said, with this drawing right now I should be able to read properly each resistor, so probably the fault is in my code. If you need more of my code please let me know..

The results in the debugger are:
[S0, S3, S6]
[S1, S4, S7]
[S2, S5, S8]

while I expect (using 12k equivalent pull down resistor)

I really appreciate your help, I have been struggling with this several hours.

Thank you

RE: SAADC channel interference due to software bad configuration or hardware design?

hmolesworth — Tue, 12 Aug 2025 15:26:56 GMT

Best if you upload the updated grid drawing and the code you are now testing with.

RE: SAADC channel interference due to software bad configuration or hardware design?

DimitraN — Tue, 12 Aug 2025 11:59:33 GMT

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/543646"]However a simple modification would allow measurement of S3 to S8 with the same number of pins; break all connections to S3-S8 and wire similar to S0-S2 such that V1 directly drives S0, S3 and S6 (direct, not in a daisy-chain) which are measured by A1, A2 and A3 but for each measurement eg V2/A2 disable pulldowns on the other SAADC channels in this case A1 and A3 and float the drivers V1 and V3. Similar for S1, S4 and S7 and also for S2, S5 and S8[/quote]

Hello again,

I created this circuit on my breadboard and I still cannot read the resistors properly. Can you find maybe the issue in my code? have you tested it that it works?

RE: SAADC channel interference due to software bad configuration or hardware design?

DimitraN — Fri, 08 Aug 2025 11:55:28 GMT

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/543646"]Not so for other than S0, S1 and S2; assuming the dots on the schematic are connections and not open switches.[/quote]

So if I understand correctly I cannot achieve what I want with the current hardware connection of the sensors. Because for each row of the grid the previous resistors interfere - drop the voltage. e.g. I read S6, S0 and S3 drop the voltage even if I disconnect A1 and A2..

[quote userid="65515" url="~/f/nordic-q-a/123259/saadc-channel-interference-due-to-software-bad-configuration-or-hardware-design/543646"]Note also there are two pulldown resistors; the internal bias pulldown for the SAADC is 160k and the internal pulldown for an input pin is about 13k.[/quote]

Thank you for this note! I hadn't found this but I should have

RE: SAADC channel interference due to software bad configuration or hardware design?

hmolesworth — Fri, 25 Jul 2025 20:52:23 GMT

"The idea is that if we disconnect every pin and set only V1 high and connect only A1 analog pin to the ADC, we will read the "signal" of the resistor S0 only without any interference of the rest."

Not so for other than S0, S1 and S2; assuming the dots on the schematic are connections and not open switches.

Note also there are two pulldown resistors; the internal bias pulldown for the SAADC is 160k and the internal pulldown for an input pin is about 13k. That second input pin pulldown is not documented to work on the pin in SAADC mode, though I believe it does work.

  channel0_config.resistor_p = NRF_SAADC_RESISTOR_PULLDOWN; //Disable the 13k pulldown resistor. (Bypass resistor ladder).
actually:
  channel0_config.resistor_p = NRF_SAADC_RESISTOR_PULLDOWN; //Enable the 160k pulldown resistor. (Bypass resistor ladder).

V1 high, A1 pulled low by 160k||13k ==12k

V1 = (2^14)*(12k)/(12K+1K) = 16384*(12/13) = 15,124

This only allows measurements of S0, S1 and S2. However a simple modification would allow measurement of S3 to S8 with the same number of pins; break all connections to S3-S8 and wire similar to S0-S2 such that V1 directly drives S0, S3 and S6 (direct, not in a daisy-chain) which are measured by A1, A2 and A3 but for each measurement eg V2/A2 disable pulldowns on the other SAADC channels in this case A1 and A3 and float the drivers V1 and V3. Similar for S1, S4 and S7 and also for S2, S5 and S8

Better results can be obtained by using differential mode and measuring in both directions; I discuss this here:

seeking-more-information-on-adc-reference-and-buffer-offset