Try to program a custom board using BL5340PA module to see LOG

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Mon, 15 Sep 2025 07:43:45 GMT

resolve need to add in prj.conf

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Thu, 07 Aug 2025 08:51:03 GMT

When i try to debug, i still block in line 131 of the cpu_idle.c, what that means ?

/*
 * Copyright (c) 2013-2014 Wind River Systems, Inc.
 * Copyright (c) 2023 Arm Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief ARM Cortex-M power management
 */
#include <zephyr/kernel.h>
#include <cmsis_core.h>

#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
#include <soc_cpu_idle.h>
#endif

/**
 * @brief Initialization of CPU idle
 *
 * Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's
 * duration.
 */
void z_arm_cpu_idle_init(void)
{
	SCB->SCR = SCB_SCR_SEVONPEND_Msk;
}

#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
#define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
#else
#define ON_EXIT_IDLE_HOOK do {} while (false)
#endif

#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
#define SLEEP_IF_ALLOWED(wait_instr) do { \
	/* Skip the wait instr if on_enter_cpu_idle returns false */ \
	if (z_arm_on_enter_cpu_idle()) { \
		/* Wait for all memory transaction to complete */ \
		/* before entering low power state. */ \
		__DSB(); \
		wait_instr(); \
		/* Inline the macro provided by SoC-specific code */ \
		ON_EXIT_IDLE_HOOK; \
	} \
} while (false)
#else
#define SLEEP_IF_ALLOWED(wait_instr) do { \
	__DSB(); \
	wait_instr(); \
	ON_EXIT_IDLE_HOOK; \
} while (false)
#endif

void arch_cpu_idle(void)
{
#if defined(CONFIG_TRACING)
	sys_trace_idle();
#endif

#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
	z_arm_on_enter_cpu_idle_prepare();
#endif

#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/*
	 * PRIMASK is always cleared on ARMv7-M and ARMv8-M (not used
	 * for interrupt locking), and configuring BASEPRI to the lowest
	 * priority to ensure wake-up will cause interrupts to be serviced
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	__disable_irq();

	/*
	 * Set wake-up interrupt priority to the lowest and synchronize to
	 * ensure that this is visible to the WFI instruction.
	 */
	__set_BASEPRI(0);
	__ISB();
#else
	/*
	 * For all the other ARM architectures that do not implement BASEPRI,
	 * PRIMASK is used as the interrupt locking mechanism, and it is not
	 * necessary to set PRIMASK here, as PRIMASK would have already been
	 * set by the caller as part of interrupt locking if necessary
	 * (i.e. if the caller sets _kernel.idle).
	 */
#endif

	SLEEP_IF_ALLOWED(__WFI);

	__enable_irq();
	__ISB();
}

void arch_cpu_atomic_idle(unsigned int key)
{
#if defined(CONFIG_TRACING)
	sys_trace_idle();
#endif

#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
	z_arm_on_enter_cpu_idle_prepare();
#endif

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	__disable_irq();

	/*
	 * No need to set SEVONPEND, it's set once in z_arm_cpu_idle_init()
	 * and never touched again.
	 */

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	/* No BASEPRI, call wfe directly. (SEVONPEND is set in z_arm_cpu_idle_init()) */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts  */
	__set_BASEPRI(0);
	__ISB();
#else
#error Unsupported architecture
#endif

	SLEEP_IF_ALLOWED(__WFE);

	arch_irq_unlock(key);
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__enable_irq();
#endif
}

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Tue, 05 Aug 2025 12:08:42 GMT

I have create my board's DTS file but i don't know what to put inside.

/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "custom_bl5340pa-pinctrl.dtsi"

/ {
	model = "Custom Board auto generated by nRF Connect for VS Code (CPUAPP)";
	compatible = "Ezurio,custom-bl5340pa-cpuapp";

	chosen {
		zephyr,sram = &sram0_image;
		zephyr,flash = &flash0;
		zephyr,code-partition = &slot0_partition;
		zephyr,sram-secure-partition = &sram0_s;
		zephyr,sram-non-secure-partition = &sram0_ns;
	};
};

#include "custom_bl5340pa-cpuapp_partitioning.dtsi"
#include "custom_bl5340pa-shared_sram.dtsi"

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Tue, 05 Aug 2025 08:21:39 GMT

Ok thanks yes i think i flash code but my module is not enable to run it, probably i need custom files like DTS, i go check how to do that

RE: Try to program a custom board using BL5340PA module to see LOG

Turbo J — Tue, 05 Aug 2025 08:00:30 GMT

Depends.

I got away using the dk board with a lot of DTS magic in the overlay. Its quite powerful once you learn how to delete nodes and properties.

Note that you MUST customise prj.conf and the DTS if you are missing the LF crystal or the DC/DC inductor.

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Tue, 05 Aug 2025 07:22:53 GMT

Is it necessary to create a custom boards on my folders or i can just compile the code using nrf5340dk_nrf5340_cpuapp ?

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Tue, 05 Aug 2025 07:09:26 GMT

LOG: J-Link RTT Viewer V8.18: Logging started.
LOG: Connecting to J-Link via USB...
LOG: Device "NRF5340_XXAA_APP" selected.
LOG: ConfigTargetSettings() start
LOG: ConfigTargetSettings() end - Took 11us
LOG: InitTarget() start
LOG: InitTarget() end - Took 1.33ms
LOG: Found SW-DP with ID 0x6BA02477
LOG: DPIDR: 0x6BA02477
LOG: CoreSight SoC-400 or earlier
LOG: AP map detection skipped. Manually configured AP map found.
LOG: AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[1]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[3]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[0]: Core found
LOG: AP[0]: AHB-AP ROM base: 0xE00FE000
LOG: CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
LOG: Feature set: Mainline
LOG: Cache: No cache
LOG: Found Cortex-M33 r0p4, Little endian.
LOG: FPUnit: 8 code (BP) slots and 0 literal slots
LOG: Security extension: implemented
LOG: Secure debug: enabled
LOG: CoreSight components:
LOG: ROMTbl[0] @ E00FE000
LOG: [0][0]: E00FF000 CID B105100D PID 000BB4C9 ROM Table
LOG: ROMTbl[1] @ E00FF000
LOG: [1][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33
LOG: [1][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT
LOG: [1][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB
LOG: [1][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM
LOG: [1][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM
LOG: [1][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
LOG: [0][1]: E0040000 CID B105900D PID 000BBD21 DEVARCH 00000000 DEVTYPE 11 TPIU
LOG: RTT Viewer connected.

RE: Try to program a custom board using BL5340PA module to see LOG

D.MASSIALA — Tue, 05 Aug 2025 07:07:19 GMT

CONFIG_LOG=y
CONFIG_LOG_DEFAULT_LEVEL=4
CONFIG_LOG_MODE_IMMEDIATE=y
CONFIG_USE_SEGGER_RTT=y
CONFIG_LOG_BACKEND_RTT=y