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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/123830/mpsl-assert-1-1310</link><description>I encountered the error MPSL ASSERT: 1, 1310 when establishing a BLE connection on my custom board, only happens when using an external 32 kHZ crystal oscillator ( 
 
 CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL). Could you provide information on what issue</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 25 Aug 2025 13:14:26 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/123830/mpsl-assert-1-1310" /><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546640?ContentTypeID=1</link><pubDate>Mon, 25 Aug 2025 13:14:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fabff2ef-b807-456f-9808-dbd6b957e8e1</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;No, it&amp;#39;s telling the software how far ahead of the BLE event that it should startup the HFCLK.&lt;/p&gt;
&lt;p&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546552?ContentTypeID=1</link><pubDate>Mon, 25 Aug 2025 02:49:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fae50047-a760-4389-9157-58ce963690f1</guid><dc:creator>HauJohn</dc:creator><description>&lt;p&gt;I just want to clearly understand what the parameter &lt;code data-start="63" data-end="90"&gt;CONFIG_MPSL_HFCLK_LATENCY&lt;/code&gt; means. Is it the ramp-up time during packet transmission and reception as shown in this diagram? &lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1756090000304v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;If that&amp;rsquo;s the case, then increasing this parameter could reduce the transmission speed, right?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546501?ContentTypeID=1</link><pubDate>Fri, 22 Aug 2025 16:59:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ce8c49fa-00c7-4e27-8e94-71713a31c792</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;This is directly related to the settling time of the HFXO,&amp;nbsp;in nRF Connect SDK v2.9.x it simply was configured to short.&lt;/p&gt;
&lt;p&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546402?ContentTypeID=1</link><pubDate>Fri, 22 Aug 2025 06:13:22 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9895a01a-208f-4628-a821-131fd193502f</guid><dc:creator>HauJohn</dc:creator><description>&lt;p&gt;As I understand, the most accurate method is to use a spectrum analyzer through a radio test to precisely determine the required capacitor value for stable radio clock operation. Increasing &lt;code data-start="272" data-end="292"&gt;MPSL_HFCLK_LATENCY&lt;/code&gt; is only a workaround, correct?&lt;/p&gt;
&lt;p&gt;Could you explain in detail what aspects are affected by increasing &lt;code data-start="149" data-end="169"&gt;MPSL_HFCLK_LATENCY&lt;/code&gt;? For example, does it impact data transmission speed, power consumption during data transfer, etc.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546372?ContentTypeID=1</link><pubDate>Thu, 21 Aug 2025 18:37:43 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4eb84166-b1a5-41d2-a6ad-70adadeb315f</guid><dc:creator>Kenneth</dc:creator><description>[quote user="HauJohn"]&lt;code&gt;MPSL_HFCLK_LATENCY&lt;/code&gt; [/quote]
&lt;p&gt;Use this one yes.&lt;/p&gt;
[quote user="HauJohn"]HFXO internal capacitor configuration[/quote]
&lt;p&gt;You should only configure this parameter during radio_test to ensure the carrier is as close as possible to the configured frequency when you are outputting a continuous carrier. For instance if you setup a carrier on channel 2, then use a spectrum analyzer and check which setting that get you closest to frequency 2402MHz. This parameter can also indirectly affect the startup time, but with wrong setting you can be off frequency (e.g. out of spec). The carrier should for a BLE device be maximum +-96kHz off center frequency (+-40ppm at 2.4GHz).&lt;/p&gt;
&lt;p&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546318?ContentTypeID=1</link><pubDate>Thu, 21 Aug 2025 09:17:53 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ae0f1fe1-15b5-498e-a992-5f335b58328f</guid><dc:creator>HauJohn</dc:creator><description>&lt;p&gt;Hi, your method works. I also tried another approach by configuring the internal capacitor for the HFXO. With values from 4000 to 10750, the issue no longer occurs. However, specifically with the value 10500, the device encounters the same error immediately during advertising.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1755767284838v2.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;From what I read, increasing &lt;code data-start="104" data-end="124"&gt;MPSL_HFCLK_LATENCY&lt;/code&gt; impacts power consumption.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1755767697028v3.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;Could you clarify the relationship between &lt;code data-start="120" data-end="140"&gt;MPSL_HFCLK_LATENCY&lt;/code&gt; and the HFXO internal capacitor configuration as described above? Which approach would be the most appropriate to resolve the issue?.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MPSL ASSERT: 1, 1310</title><link>https://devzone.nordicsemi.com/thread/546165?ContentTypeID=1</link><pubDate>Wed, 20 Aug 2025 10:38:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:56b9ff6f-ed9b-49b1-9e18-88fa88baefb7</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;Try to change&amp;nbsp;&lt;span&gt;CONFIG_MPSL_HFCLK_LATENCY=1500&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Kenneth&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>