RE: Documentation contradiction in LATCH register clearing description (Page 323, nRF52840 PS v1.11)

Priyanka — Mon, 29 Sep 2025 07:43:50 GMT

Hi,

I don't think the documentation is contradictory. What I understood from the docs is that, say, PIN0.DETECT is high, then the 0 bit in the LATCH register goes high. After that, even if CPU writes 1 in order to clear the LATCH register's 0 bit, this will actually be done only if the PIN0.DETECT goes low and then the CPU writes 1 to the LATCH register.
As long as these two conditions (PIN0.DETECT should go low & CPU then writes 1 to the LATCH register) are not met, the 0 bit in the LATCH register is not cleared.

Nevertheless, I have inquired internally in order to verify this and will get back to you.

-Priyanka